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git.proxmox.com Git - rustc.git/blob - src/llvm/test/CodeGen/SystemZ/Large/branch-range-09.py
1 # Test 32-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of
2 # instructions causes some branches to be out of range.
3 # RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
8 # conditional branch to after0
11 # conditional branch to after0
13 # 0xffcc bytes, from MVIY instructions
14 # conditional branch to main
17 # conditional branch to main
20 # Each conditional branch sequence occupies 12 bytes if it uses a short
21 # branch and 14 if it uses a long one. The ones before "main:" have to
22 # take the branch length into account, which is 6 for short branches,
23 # so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
24 # The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
25 # can use short branches.
27 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
28 # CHECK: clr %r4, [[REG]]
29 # CHECK: jgl [[LABEL:\.L[^ ]*]]
30 # CHECK: lb [[REG:%r[0-5]]], 1(%r3)
31 # CHECK: clr %r4, [[REG]]
32 # CHECK: jgl [[LABEL]]
33 # CHECK: lb [[REG:%r[0-5]]], 2(%r3)
34 # CHECK: clr %r4, [[REG]]
35 # CHECK: jgl [[LABEL]]
36 # CHECK: lb [[REG:%r[0-5]]], 3(%r3)
37 # CHECK: clr %r4, [[REG]]
38 # CHECK: jgl [[LABEL]]
39 # CHECK: lb [[REG:%r[0-5]]], 4(%r3)
40 # CHECK: clr %r4, [[REG]]
41 # CHECK: jgl [[LABEL]]
42 # CHECK: lb [[REG:%r[0-5]]], 5(%r3)
43 # CHECK: clrjl %r4, [[REG]], [[LABEL]]
44 # CHECK: lb [[REG:%r[0-5]]], 6(%r3)
45 # CHECK: clrjl %r4, [[REG]], [[LABEL]]
46 # CHECK: lb [[REG:%r[0-5]]], 7(%r3)
47 # CHECK: clrjl %r4, [[REG]], [[LABEL]]
48 # ...main goes here...
49 # CHECK: lb [[REG:%r[0-5]]], 25(%r3)
50 # CHECK: clrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]]
51 # CHECK: lb [[REG:%r[0-5]]], 26(%r3)
52 # CHECK: clrjl %r4, [[REG]], [[LABEL]]
53 # CHECK: lb [[REG:%r[0-5]]], 27(%r3)
54 # CHECK: clrjl %r4, [[REG]], [[LABEL]]
55 # CHECK: lb [[REG:%r[0-5]]], 28(%r3)
56 # CHECK: clrjl %r4, [[REG]], [[LABEL]]
57 # CHECK: lb [[REG:%r[0-5]]], 29(%r3)
58 # CHECK: clr %r4, [[REG]]
59 # CHECK: jgl [[LABEL]]
60 # CHECK: lb [[REG:%r[0-5]]], 30(%r3)
61 # CHECK: clr %r4, [[REG]]
62 # CHECK: jgl [[LABEL]]
63 # CHECK: lb [[REG:%r[0-5]]], 31(%r3)
64 # CHECK: clr %r4, [[REG]]
65 # CHECK: jgl [[LABEL]]
66 # CHECK: lb [[REG:%r[0-5]]], 32(%r3)
67 # CHECK: clr %r4, [[REG]]
68 # CHECK: jgl [[LABEL]]
73 print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {'
75 print ' br label %before0'
78 for i
in xrange(branch_blocks
):
79 next
= 'before%d' % (i
+ 1) if i
+ 1 < branch_blocks
else 'main'
81 print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i
, i
)
82 print ' %%bcur%d = load i8 *%%bstop%d' % (i
, i
)
83 print ' %%bext%d = sext i8 %%bcur%d to i32' % (i
, i
)
84 print ' %%btest%d = icmp ult i32 %%limit, %%bext%d' % (i
, i
)
85 print ' br i1 %%btest%d, label %%after0, label %%%s' % (i
, next
)
90 for i
in xrange(0, main_size
, 6):
92 offset
= 4096 + b
% 500000
94 print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i
, offset
)
95 print ' store volatile i8 %d, i8 *%%ptr%d' % (value
, i
)
97 for i
in xrange(branch_blocks
):
98 print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i
, i
+ 25)
99 print ' %%acur%d = load i8 *%%astop%d' % (i
, i
)
100 print ' %%aext%d = sext i8 %%acur%d to i32' % (i
, i
)
101 print ' %%atest%d = icmp ult i32 %%limit, %%aext%d' % (i
, i
)
102 print ' br i1 %%atest%d, label %%main, label %%after%d' % (i
, i
)