src/llvm/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt

   1 # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
   2 # RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
   3
   4 # None of these instructions should be classified as unpredictable:
   5
   6 # CHECK-NOT: potentially undefined instruction encoding
   7
   8 # Stores from duplicated registers should be fine.
   9 0xe3 0x0f 0x80 0xa8
  10 # CHECK: stp x3, x3, [sp], #0
  11
  12 # d5 != x5 so "ldp d5, d6, [x5], #24" is fine.
  13 0xa5 0x98 0xc1 0x6c
  14 # CHECK: ldp d5, d6, [x5], #24
  15
  16 # xzr != sp so "stp xzr, xzr, [sp], #8" is fine.
  17 0xff 0xff 0x80 0xa8
  18 # CHECK: stp xzr, xzr, [sp], #8