src/stdarch/crates/std_detect/src/detect/arch/x86.rs

   1 //! This module implements minimal run-time feature detection for x86.
   2 //!
   3 //! The features are detected using the `detect_features` function below.
   4 //! This function uses the CPUID instruction to read the feature flags from the
   5 //! CPU and encodes them in an `usize` where each bit position represents
   6 //! whether a feature is available (bit is set) or unavaiable (bit is cleared).
   7 //!
   8 //! The enum `Feature` is used to map bit positions to feature names, and the
   9 //! the `__crate::detect::check_for!` macro is used to map string literals (e.g.,
  10 //! "avx") to these bit positions (e.g., `Feature::avx`).
  11 //!
  12 //! The run-time feature detection is performed by the
  13 //! `__crate::detect::check_for(Feature) -> bool` function. On its first call,
  14 //! this functions queries the CPU for the available features and stores them
  15 //! in a global `AtomicUsize` variable. The query is performed by just checking
  16 //! whether the feature bit in this global variable is set or cleared.
  17
  18 features! {
  19     @TARGET: x86;
  20     @MACRO_NAME: is_x86_feature_detected;
  21     @MACRO_ATTRS:
  22     /// A macro to test at *runtime* whether a CPU feature is available on
  23     /// x86/x86-64 platforms.
  24     ///
  25     /// This macro is provided in the standard library and will detect at runtime
  26     /// whether the specified CPU feature is detected. This does **not** resolve at
  27     /// compile time unless the specified feature is already enabled for the entire
  28     /// crate. Runtime detection currently relies mostly on the `cpuid` instruction.
  29     ///
  30     /// This macro only takes one argument which is a string literal of the feature
  31     /// being tested for. The feature names supported are the lowercase versions of
  32     /// the ones defined by Intel in [their documentation][docs].
  33     ///
  34     /// ## Supported arguments
  35     ///
  36     /// This macro supports the same names that `#[target_feature]` supports. Unlike
  37     /// `#[target_feature]`, however, this macro does not support names separated
  38     /// with a comma. Instead testing for multiple features must be done through
  39     /// separate macro invocations for now.
  40     ///
  41     /// Supported arguments are:
  42     ///
  43     /// * `"aes"`
  44     /// * `"pclmulqdq"`
  45     /// * `"rdrand"`
  46     /// * `"rdseed"`
  47     /// * `"tsc"`
  48     /// * `"mmx"`
  49     /// * `"sse"`
  50     /// * `"sse2"`
  51     /// * `"sse3"`
  52     /// * `"ssse3"`
  53     /// * `"sse4.1"`
  54     /// * `"sse4.2"`
  55     /// * `"sse4a"`
  56     /// * `"sha"`
  57     /// * `"avx"`
  58     /// * `"avx2"`
  59     /// * `"avx512f"`
  60     /// * `"avx512cd"`
  61     /// * `"avx512er"`
  62     /// * `"avx512pf"`
  63     /// * `"avx512bw"`
  64     /// * `"avx512dq"`
  65     /// * `"avx512vl"`
  66     /// * `"avx512ifma"`
  67     /// * `"avx512vbmi"`
  68     /// * `"avx512vpopcntdq"`
  69     /// * `"avx512vbmi2"`
  70     /// * `"avx512gfni"`
  71     /// * `"avx512vaes"`
  72     /// * `"avx512vpclmulqdq"`
  73     /// * `"avx512vnni"`
  74     /// * `"avx512bitalg"`
  75     /// * `"avx512bf16"`
  76     /// * `"avx512vp2intersect"`
  77     /// * `"f16c"`
  78     /// * `"fma"`
  79     /// * `"bmi1"`
  80     /// * `"bmi2"`
  81     /// * `"abm"`
  82     /// * `"lzcnt"`
  83     /// * `"tbm"`
  84     /// * `"popcnt"`
  85     /// * `"fxsr"`
  86     /// * `"xsave"`
  87     /// * `"xsaveopt"`
  88     /// * `"xsaves"`
  89     /// * `"xsavec"`
  90     /// * `"cmpxchg16b"`
  91     /// * `"adx"`
  92     /// * `"rtm"`
  93     ///
  94     /// [docs]: https://software.intel.com/sites/landingpage/IntrinsicsGuide
  95     #[stable(feature = "simd_x86", since = "1.27.0")]
  96     @BIND_FEATURE_NAME: "abm"; "lzcnt"; // abm is a synonym for lzcnt
  97     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] aes: "aes";
  98     /// AES (Advanced Encryption Standard New Instructions AES-NI)
  99     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] pclmulqdq: "pclmulqdq";
 100     /// CLMUL (Carry-less Multiplication)
 101     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdrand: "rdrand";
 102     /// RDRAND
 103     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdseed: "rdseed";
 104     /// RDSEED
 105     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tsc: "tsc";
 106     /// TSC (Time Stamp Counter)
 107     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] mmx: "mmx";
 108     /// MMX (MultiMedia eXtensions)
 109     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse: "sse";
 110     /// SSE (Streaming SIMD Extensions)
 111     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse2: "sse2";
 112     /// SSE2 (Streaming SIMD Extensions 2)
 113     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse3: "sse3";
 114     /// SSE3 (Streaming SIMD Extensions 3)
 115     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] ssse3: "ssse3";
 116     /// SSSE3 (Supplemental Streaming SIMD Extensions 3)
 117     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_1: "sse4.1";
 118     /// SSE4.1 (Streaming SIMD Extensions 4.1)
 119     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_2: "sse4.2";
 120     /// SSE4.2 (Streaming SIMD Extensions 4.2)
 121     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4a: "sse4a";
 122     /// SSE4a (Streaming SIMD Extensions 4a)
 123     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sha: "sha";
 124     /// SHA
 125     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx: "avx";
 126     /// AVX (Advanced Vector Extensions)
 127     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx2: "avx2";
 128     /// AVX2 (Advanced Vector Extensions 2)
 129     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512f: "avx512f" ;
 130     /// AVX-512 F (Foundation)
 131     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512cd: "avx512cd" ;
 132     /// AVX-512 CD (Conflict Detection Instructions)
 133     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512er: "avx512er";
 134     /// AVX-512 ER (Expo nential and Reciprocal Instructions)
 135     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512pf: "avx512pf";
 136     /// AVX-512 PF (Prefetch Instructions)
 137     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bw: "avx512bw";
 138     /// AVX-512 BW (Byte and Word Instructions)
 139     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512dq: "avx512dq";
 140     /// AVX-512 DQ (Doubleword and Quadword)
 141     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vl: "avx512vl";
 142     /// AVX-512 VL (Vector Length Extensions)
 143     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512ifma: "avx512ifma";
 144     /// AVX-512 IFMA (Integer Fused Multiply Add)
 145     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi: "avx512vbmi";
 146     /// AVX-512 VBMI (Vector Byte Manipulation Instructions)
 147     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vpopcntdq: "avx512vpopcntdq";
 148     /// AVX-512 VPOPCNTDQ (Vector Population Count Doubleword and
 149     /// Quadword)
 150     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi2: "avx512vbmi2";
 151     /// AVX-512 VBMI2 (Additional byte, word, dword and qword capabilities)
 152     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512gfni: "avx512gfni";
 153     /// AVX-512 GFNI (Galois Field New Instruction)
 154     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vaes: "avx512vaes";
 155     /// AVX-512 VAES (Vector AES instruction)
 156     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vpclmulqdq: "avx512vpclmulqdq";
 157     /// AVX-512 VPCLMULQDQ (Vector PCLMULQDQ instructions)
 158     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vnni: "avx512vnni";
 159     /// AVX-512 VNNI (Vector Neural Network Instructions)
 160     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bitalg: "avx512bitalg";
 161     /// AVX-512 BITALG (Support for VPOPCNT[B,W] and VPSHUFBITQMB)
 162     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bf16: "avx512bf16";
 163     /// AVX-512 BF16 (BFLOAT16 instructions)
 164     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vp2intersect: "avx512vp2intersect";
 165     /// AVX-512 P2INTERSECT
 166     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] f16c: "f16c";
 167     /// F16C (Conversions between IEEE-754 `binary16` and `binary32` formats)
 168     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fma: "fma";
 169     /// FMA (Fused Multiply Add)
 170     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi1: "bmi1" ;
 171     /// BMI1 (Bit Manipulation Instructions 1)
 172     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi2: "bmi2" ;
 173     /// BMI2 (Bit Manipulation Instructions 2)
 174     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] lzcnt: "lzcnt";
 175     /// ABM (Advanced Bit Manipulation) / LZCNT (Leading Zero Count)
 176     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tbm: "tbm";
 177     /// TBM (Trailing Bit Manipulation)
 178     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] popcnt: "popcnt";
 179     /// POPCNT (Population Count)
 180     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fxsr: "fxsr";
 181     /// FXSR (Floating-point context fast save and restor)
 182     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsave: "xsave";
 183     /// XSAVE (Save Processor Extended States)
 184     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaveopt: "xsaveopt";
 185     /// XSAVEOPT (Save Processor Extended States Optimized)
 186     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaves: "xsaves";
 187     /// XSAVES (Save Processor Extended States Supervisor)
 188     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsavec: "xsavec";
 189     /// XSAVEC (Save Processor Extended States Compacted)
 190     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] cmpxchg16b: "cmpxchg16b";
 191     /// CMPXCH16B (16-byte compare-and-swap instruction)
 192     @FEATURE: #[stable(feature = "simd_x86_adx", since = "1.33.0")] adx: "adx";
 193     /// ADX, Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
 194     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rtm: "rtm";
 195     /// RTM, Intel (Restricted Transactional Memory)
 196 }