src/stdsimd/crates/core_arch/src/aarch64/crc.rs

   1 extern "C" {
   2     #[link_name = "llvm.aarch64.crc32b"]
   3     fn crc32b_(crc: u32, data: u32) -> u32;
   4     #[link_name = "llvm.aarch64.crc32h"]
   5     fn crc32h_(crc: u32, data: u32) -> u32;
   6     #[link_name = "llvm.aarch64.crc32w"]
   7     fn crc32w_(crc: u32, data: u32) -> u32;
   8     #[link_name = "llvm.aarch64.crc32x"]
   9     fn crc32x_(crc: u32, data: u64) -> u32;
  10
  11     #[link_name = "llvm.aarch64.crc32cb"]
  12     fn crc32cb_(crc: u32, data: u32) -> u32;
  13     #[link_name = "llvm.aarch64.crc32ch"]
  14     fn crc32ch_(crc: u32, data: u32) -> u32;
  15     #[link_name = "llvm.aarch64.crc32cw"]
  16     fn crc32cw_(crc: u32, data: u32) -> u32;
  17     #[link_name = "llvm.aarch64.crc32cx"]
  18     fn crc32cx_(crc: u32, data: u64) -> u32;
  19 }
  20
  21 #[cfg(test)]
  22 use stdsimd_test::assert_instr;
  23
  24 /// CRC32 single round checksum for bytes (8 bits).
  25 #[inline]
  26 #[target_feature(enable = "crc")]
  27 #[cfg_attr(test, assert_instr(crc32b))]
  28 pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
  29     crc32b_(crc, data as u32)
  30 }
  31
  32 /// CRC32 single round checksum for half words (16 bits).
  33 #[inline]
  34 #[target_feature(enable = "crc")]
  35 #[cfg_attr(test, assert_instr(crc32h))]
  36 pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
  37     crc32h_(crc, data as u32)
  38 }
  39
  40 /// CRC32 single round checksum for words (32 bits).
  41 #[inline]
  42 #[target_feature(enable = "crc")]
  43 #[cfg_attr(test, assert_instr(crc32w))]
  44 pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
  45     crc32w_(crc, data)
  46 }
  47
  48 /// CRC32 single round checksum for quad words (64 bits).
  49 #[inline]
  50 #[target_feature(enable = "crc")]
  51 #[cfg_attr(test, assert_instr(crc32x))]
  52 pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
  53     crc32x_(crc, data)
  54 }
  55
  56 /// CRC32-C single round checksum for bytes (8 bits).
  57 #[inline]
  58 #[target_feature(enable = "crc")]
  59 #[cfg_attr(test, assert_instr(crc32cb))]
  60 pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
  61     crc32cb_(crc, data as u32)
  62 }
  63
  64 /// CRC32-C single round checksum for half words (16 bits).
  65 #[inline]
  66 #[target_feature(enable = "crc")]
  67 #[cfg_attr(test, assert_instr(crc32ch))]
  68 pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
  69     crc32ch_(crc, data as u32)
  70 }
  71
  72 /// CRC32-C single round checksum for words (32 bits).
  73 #[inline]
  74 #[target_feature(enable = "crc")]
  75 #[cfg_attr(test, assert_instr(crc32cw))]
  76 pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
  77     crc32cw_(crc, data)
  78 }
  79
  80 /// CRC32-C single round checksum for quad words (64 bits).
  81 #[inline]
  82 #[target_feature(enable = "crc")]
  83 #[cfg_attr(test, assert_instr(crc32cx))]
  84 pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
  85     crc32cx_(crc, data)
  86 }
  87
  88 #[cfg(test)]
  89 mod tests {
  90     use crate::core_arch::{aarch64::*, simd::*};
  91     use std::mem;
  92     use stdsimd_test::simd_test;
  93
  94     #[simd_test(enable = "crc")]
  95     unsafe fn test_crc32b() {
  96         assert_eq!(__crc32b(0, 0), 0);
  97         assert_eq!(__crc32b(0, 255), 755167117);
  98     }
  99
 100     #[simd_test(enable = "crc")]
 101     unsafe fn test_crc32h() {
 102         assert_eq!(__crc32h(0, 0), 0);
 103         assert_eq!(__crc32h(0, 16384), 1994146192);
 104     }
 105
 106     #[simd_test(enable = "crc")]
 107     unsafe fn test_crc32w() {
 108         assert_eq!(__crc32w(0, 0), 0);
 109         assert_eq!(__crc32w(0, 4294967295), 3736805603);
 110     }
 111
 112     #[simd_test(enable = "crc")]
 113     unsafe fn test_crc32d() {
 114         assert_eq!(__crc32d(0, 0), 0);
 115         assert_eq!(__crc32d(0, 18446744073709551615), 1147535477);
 116     }
 117
 118     #[simd_test(enable = "crc")]
 119     unsafe fn test_crc32cb() {
 120         assert_eq!(__crc32cb(0, 0), 0);
 121         assert_eq!(__crc32cb(0, 255), 2910671697);
 122     }
 123
 124     #[simd_test(enable = "crc")]
 125     unsafe fn test_crc32ch() {
 126         assert_eq!(__crc32ch(0, 0), 0);
 127         assert_eq!(__crc32ch(0, 16384), 1098587580);
 128     }
 129
 130     #[simd_test(enable = "crc")]
 131     unsafe fn test_crc32cw() {
 132         assert_eq!(__crc32cw(0, 0), 0);
 133         assert_eq!(__crc32cw(0, 4294967295), 3080238136);
 134     }
 135
 136     #[simd_test(enable = "crc")]
 137     unsafe fn test_crc32cd() {
 138         assert_eq!(__crc32cd(0, 0), 0);
 139         assert_eq!(__crc32cd(0, 18446744073709551615), 3293575501);
 140     }
 141
 142 }