src/test/codegen/simd-wide-sum.rs

   1 // compile-flags: -C opt-level=3 --edition=2021
   2 // only-x86_64
   3 // ignore-debug: the debug assertions get in the way
   4
   5 #![crate_type = "lib"]
   6 #![feature(portable_simd)]
   7
   8 use std::simd::{Simd, SimdUint};
   9 const N: usize = 8;
  10
  11 #[no_mangle]
  12 // CHECK-LABEL: @wider_reduce_simd
  13 pub fn wider_reduce_simd(x: Simd<u8, N>) -> u16 {
  14     // CHECK: zext <8 x i8>
  15     // CHECK-SAME: to <8 x i16>
  16     // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
  17     let x: Simd<u16, N> = x.cast();
  18     x.reduce_sum()
  19 }
  20
  21 #[no_mangle]
  22 // CHECK-LABEL: @wider_reduce_loop
  23 pub fn wider_reduce_loop(x: Simd<u8, N>) -> u16 {
  24     // CHECK: zext <8 x i8>
  25     // CHECK-SAME: to <8 x i16>
  26     // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
  27     let mut sum = 0_u16;
  28     for i in 0..N {
  29         sum += u16::from(x[i]);
  30     }
  31     sum
  32 }
  33
  34 #[no_mangle]
  35 // CHECK-LABEL: @wider_reduce_iter
  36 pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
  37     // CHECK: zext <8 x i8>
  38     // CHECK-SAME: to <8 x i16>
  39     // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
  40     x.as_array().iter().copied().map(u16::from).sum()
  41 }
  42
  43 // This iterator one is the most interesting, as it's the one
  44 // which used to not auto-vectorize due to a suboptimality in the
  45 // `<array::IntoIter as Iterator>::fold` implementation.
  46
  47 #[no_mangle]
  48 // CHECK-LABEL: @wider_reduce_into_iter
  49 pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
  50     // FIXME MIR inlining messes up LLVM optimizations.
  51     // WOULD-CHECK: zext <8 x i8>
  52     // WOULD-CHECK-SAME: to <8 x i16>
  53     // WOULD-CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
  54     x.to_array().into_iter().map(u16::from).sum()
  55 }