src/test/incremental/hashes/inline_asm.rs

   1 // This test case tests the incremental compilation hash (ICH) implementation
   2 // for inline asm.
   3
   4 // The general pattern followed here is: Change one thing between rev1 and rev2
   5 // and make sure that the hash has changed, then change nothing between rev2 and
   6 // rev3 and make sure that the hash has not changed.
   7
   8 // build-pass (FIXME(62277): could be check-pass?)
   9 // revisions: cfail1 cfail2 cfail3 cfail4 cfail5 cfail6
  10 // compile-flags: -Z query-dep-graph
  11 // [cfail1]compile-flags: -Zincremental-ignore-spans
  12 // [cfail2]compile-flags: -Zincremental-ignore-spans
  13 // [cfail3]compile-flags: -Zincremental-ignore-spans
  14 // [cfail4]compile-flags: -Zincremental-relative-spans
  15 // [cfail5]compile-flags: -Zincremental-relative-spans
  16 // [cfail6]compile-flags: -Zincremental-relative-spans
  17
  18 #![allow(warnings)]
  19 #![feature(rustc_attrs)]
  20 #![feature(llvm_asm)]
  21 #![crate_type="rlib"]
  22
  23
  24
  25 // Change template
  26 #[cfg(any(cfail1,cfail4))]
  27 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
  28 pub fn change_template(a: i32) -> i32 {
  29     let c: i32;
  30     unsafe {
  31         llvm_asm!("add 1, $0"
  32                   : "=r"(c)
  33                   : "0"(a)
  34                   :
  35                   :
  36                   );
  37     }
  38     c
  39 }
  40
  41 #[cfg(not(any(cfail1,cfail4)))]
  42 #[rustc_clean(cfg="cfail2", except="hir_owner_nodes, optimized_mir")]
  43 #[rustc_clean(cfg="cfail3")]
  44 #[rustc_clean(cfg="cfail5", except="hir_owner_nodes, optimized_mir")]
  45 #[rustc_clean(cfg="cfail6")]
  46 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
  47 pub fn change_template(a: i32) -> i32 {
  48     let c: i32;
  49     unsafe {
  50         llvm_asm!("add 2, $0"
  51                   : "=r"(c)
  52                   : "0"(a)
  53                   :
  54                   :
  55                   );
  56     }
  57     c
  58 }
  59
  60
  61
  62 // Change output
  63 #[cfg(any(cfail1,cfail4))]
  64 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
  65 pub fn change_output(a: i32) -> i32 {
  66     let mut _out1: i32 = 0;
  67     let mut _out2: i32 = 0;
  68     unsafe {
  69         llvm_asm!("add 1, $0"
  70                   : "=r"(_out1)
  71                   : "0"(a)
  72                   :
  73                   :
  74                   );
  75     }
  76     _out1
  77 }
  78
  79 #[cfg(not(any(cfail1,cfail4)))]
  80 #[rustc_clean(cfg="cfail2", except="hir_owner_nodes, optimized_mir")]
  81 #[rustc_clean(cfg="cfail3")]
  82 #[rustc_clean(cfg="cfail5", except="hir_owner_nodes, optimized_mir")]
  83 #[rustc_clean(cfg="cfail6")]
  84 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
  85 pub fn change_output(a: i32) -> i32 {
  86     let mut _out1: i32 = 0;
  87     let mut _out2: i32 = 0;
  88     unsafe {
  89         llvm_asm!("add 1, $0"
  90                   : "=r"(_out2)
  91                   : "0"(a)
  92                   :
  93                   :
  94                   );
  95     }
  96     _out1
  97 }
  98
  99
 100
 101 // Change input
 102 #[cfg(any(cfail1,cfail4))]
 103 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 104 pub fn change_input(_a: i32, _b: i32) -> i32 {
 105     let _out;
 106     unsafe {
 107         llvm_asm!("add 1, $0"
 108                   : "=r"(_out)
 109                   : "0"(_a)
 110                   :
 111                   :
 112                   );
 113     }
 114     _out
 115 }
 116
 117 #[cfg(not(any(cfail1,cfail4)))]
 118 #[rustc_clean(cfg="cfail2", except="hir_owner_nodes, optimized_mir")]
 119 #[rustc_clean(cfg="cfail3")]
 120 #[rustc_clean(cfg="cfail5", except="hir_owner_nodes, optimized_mir")]
 121 #[rustc_clean(cfg="cfail6")]
 122 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 123 pub fn change_input(_a: i32, _b: i32) -> i32 {
 124     let _out;
 125     unsafe {
 126         llvm_asm!("add 1, $0"
 127                   : "=r"(_out)
 128                   : "0"(_b)
 129                   :
 130                   :
 131                   );
 132     }
 133     _out
 134 }
 135
 136
 137
 138 // Change input constraint
 139 #[cfg(any(cfail1,cfail4))]
 140 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 141 pub fn change_input_constraint(_a: i32, _b: i32) -> i32 {
 142     let _out;
 143     unsafe {
 144         llvm_asm!("add 1, $0"
 145                   : "=r"(_out)
 146                   : "0"(_a), "r"(_b)
 147                   :
 148                   :
 149                   );
 150     }
 151     _out
 152 }
 153
 154 #[cfg(not(any(cfail1,cfail4)))]
 155 #[rustc_clean(cfg="cfail2", except="hir_owner_nodes, optimized_mir")]
 156 #[rustc_clean(cfg="cfail3")]
 157 #[rustc_clean(cfg="cfail5", except="hir_owner_nodes, optimized_mir")]
 158 #[rustc_clean(cfg="cfail6")]
 159 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 160 pub fn change_input_constraint(_a: i32, _b: i32) -> i32 {
 161     let _out;
 162     unsafe {
 163         llvm_asm!("add 1, $0"
 164                   : "=r"(_out)
 165                   : "r"(_a), "0"(_b)
 166                   :
 167                   :
 168                   );
 169     }
 170     _out
 171 }
 172
 173
 174
 175 // Change clobber
 176 #[cfg(any(cfail1,cfail4))]
 177 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 178 pub fn change_clobber(_a: i32) -> i32 {
 179     let _out;
 180     unsafe {
 181         llvm_asm!("add 1, $0"
 182                   : "=r"(_out)
 183                   : "0"(_a)
 184                   :/*--*/
 185                   :
 186                   );
 187     }
 188     _out
 189 }
 190
 191 #[cfg(not(any(cfail1,cfail4)))]
 192 #[rustc_clean(cfg="cfail2", except="hir_owner_nodes, optimized_mir")]
 193 #[rustc_clean(cfg="cfail3")]
 194 #[rustc_clean(cfg="cfail5", except="hir_owner_nodes, optimized_mir")]
 195 #[rustc_clean(cfg="cfail6")]
 196 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 197 pub fn change_clobber(_a: i32) -> i32 {
 198     let _out;
 199     unsafe {
 200         llvm_asm!("add 1, $0"
 201                   : "=r"(_out)
 202                   : "0"(_a)
 203                   : "eax"
 204                   :
 205                   );
 206     }
 207     _out
 208 }
 209
 210
 211
 212 // Change options
 213 #[cfg(any(cfail1,cfail4))]
 214 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 215 pub fn change_options(_a: i32) -> i32 {
 216     let _out;
 217     unsafe {
 218         llvm_asm!("add 1, $0"
 219                   : "=r"(_out)
 220                   : "0"(_a)
 221                   :
 222                   :/*-------*/
 223                   );
 224     }
 225     _out
 226 }
 227
 228 #[cfg(not(any(cfail1,cfail4)))]
 229 #[rustc_clean(cfg="cfail2", except="hir_owner_nodes, optimized_mir")]
 230 #[rustc_clean(cfg="cfail3")]
 231 #[rustc_clean(cfg="cfail5", except="hir_owner_nodes, optimized_mir")]
 232 #[rustc_clean(cfg="cfail6")]
 233 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 234 pub fn change_options(_a: i32) -> i32 {
 235     let _out;
 236     unsafe {
 237         llvm_asm!("add 1, $0"
 238                   : "=r"(_out)
 239                   : "0"(_a)
 240                   :
 241                   : "volatile"
 242                   );
 243     }
 244     _out
 245 }