src/test/mir-opt/inline/inline_diverging.g.Inline.diff

   1 - // MIR for `g` before Inline
   2 + // MIR for `g` after Inline
   3
   4   fn g(_1: i32) -> u32 {
   5       debug i => _1;                       // in scope 0 at $DIR/inline-diverging.rs:12:10: 12:11
   6       let mut _0: u32;                     // return place in scope 0 at $DIR/inline-diverging.rs:12:21: 12:24
   7       let mut _2: bool;                    // in scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
   8       let mut _3: i32;                     // in scope 0 at $DIR/inline-diverging.rs:13:8: 13:9
   9       let mut _4: i32;                     // in scope 0 at $DIR/inline-diverging.rs:14:9: 14:10
  10       let mut _5: !;                       // in scope 0 at $DIR/inline-diverging.rs:15:12: 17:6
  11       let _6: !;                           // in scope 0 at $DIR/inline-diverging.rs:16:9: 16:16
  12 +     scope 1 (inlined panic) {            // at $DIR/inline-diverging.rs:16:9: 16:16
  13 +         let mut _7: !;                   // in scope 1 at $SRC_DIR/std/src/panic.rs:LL:COL
  14 +     }
  15
  16       bb0: {
  17           StorageLive(_2);                 // scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
  18           StorageLive(_3);                 // scope 0 at $DIR/inline-diverging.rs:13:8: 13:9
  19           _3 = _1;                         // scope 0 at $DIR/inline-diverging.rs:13:8: 13:9
  20           _2 = Gt(move _3, const 0_i32);   // scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
  21           StorageDead(_3);                 // scope 0 at $DIR/inline-diverging.rs:13:12: 13:13
  22           switchInt(move _2) -> [false: bb2, otherwise: bb1]; // scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
  23       }
  24
  25       bb1: {
  26           StorageLive(_4);                 // scope 0 at $DIR/inline-diverging.rs:14:9: 14:10
  27           _4 = _1;                         // scope 0 at $DIR/inline-diverging.rs:14:9: 14:10
  28           _0 = move _4 as u32 (Misc);      // scope 0 at $DIR/inline-diverging.rs:14:9: 14:17
  29           StorageDead(_4);                 // scope 0 at $DIR/inline-diverging.rs:14:16: 14:17
  30           StorageDead(_2);                 // scope 0 at $DIR/inline-diverging.rs:17:5: 17:6
  31           return;                          // scope 0 at $DIR/inline-diverging.rs:18:2: 18:2
  32       }
  33
  34       bb2: {
  35           StorageLive(_6);                 // scope 0 at $DIR/inline-diverging.rs:16:9: 16:16
  36 -         _6 = panic();                    // scope 0 at $DIR/inline-diverging.rs:16:9: 16:16
  37 +         StorageLive(_7);                 // scope 1 at $SRC_DIR/std/src/panic.rs:LL:COL
  38 +         _7 = begin_panic::<&str>(const "explicit panic"); // scope 1 at $SRC_DIR/std/src/panic.rs:LL:COL
  39                                            // mir::Constant
  40 -                                          // + span: $DIR/inline-diverging.rs:16:9: 16:14
  41 -                                          // + literal: Const { ty: fn() -> ! {panic}, val: Value(Scalar(<ZST>)) }
  42 +                                          // + span: $SRC_DIR/std/src/panic.rs:LL:COL
  43 +                                          // + literal: Const { ty: fn(&str) -> ! {begin_panic::<&str>}, val: Value(Scalar(<ZST>)) }
  44 +                                          // mir::Constant
  45 +                                          // + span: $SRC_DIR/std/src/panic.rs:LL:COL
  46 +                                          // + literal: Const { ty: &str, val: Value(Slice(..)) }
  47 +     }
  48 +
  49 +     bb3 (cleanup): {
  50 +         resume;                          // scope 0 at $DIR/inline-diverging.rs:12:1: 18:2
  51       }
  52   }
  53