src/test/ui/asm-in-out-operand.rs

   1 // run-pass
   2
   3 #![feature(asm)]
   4
   5 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
   6 unsafe fn next_power_of_2(n: u32) -> u32 {
   7     let mut tmp = n;
   8     asm!("dec $0" : "+rm"(tmp) :: "cc");
   9     let mut shift = 1_u32;
  10     while shift <= 16 {
  11         asm!(
  12             "shr %cl, $2
  13             or $2, $0
  14             shl $$1, $1"
  15             : "+&rm"(tmp), "+{ecx}"(shift) : "r"(tmp) : "cc"
  16         );
  17     }
  18     asm!("inc $0" : "+rm"(tmp) :: "cc");
  19     return tmp;
  20 }
  21
  22 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
  23 pub fn main() {
  24     unsafe {
  25         assert_eq!(64, next_power_of_2(37));
  26         assert_eq!(2147483648, next_power_of_2(2147483647));
  27     }
  28
  29     let mut y: isize = 5;
  30     let x: isize;
  31     unsafe {
  32         // Treat the output as initialization.
  33         asm!(
  34             "shl $2, $1
  35             add $3, $1
  36             mov $1, $0"
  37             : "=r"(x), "+r"(y) : "i"(3_usize), "ir"(7_usize) : "cc"
  38         );
  39     }
  40     assert_eq!(x, 47);
  41     assert_eq!(y, 47);
  42
  43     let mut x = x + 1;
  44     assert_eq!(x, 48);
  45
  46     unsafe {
  47         // Assignment to mutable.
  48         // Early clobber "&":
  49         // Forbids the use of a single register by both operands.
  50         asm!("shr $$2, $1; add $1, $0" : "+&r"(x) : "r"(x) : "cc");
  51     }
  52     assert_eq!(x, 60);
  53 }
  54
  55 #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
  56 pub fn main() {}