target/alpha/cpu.c

   1 /*
   2  * QEMU Alpha CPU
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "exec/exec-all.h"
  27
  28
  29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     CPUAlphaState *env = cpu_env(cs);
  32     env->pc = value;
  33 }
  34
  35 static vaddr alpha_cpu_get_pc(CPUState *cs)
  36 {
  37     CPUAlphaState *env = cpu_env(cs);
  38     return env->pc;
  39 }
  40
  41 static void alpha_cpu_synchronize_from_tb(CPUState *cs,
  42                                           const TranslationBlock *tb)
  43 {
  44     /* The program counter is always up to date with CF_PCREL. */
  45     if (!(tb_cflags(tb) & CF_PCREL)) {
  46         CPUAlphaState *env = cpu_env(cs);
  47         env->pc = tb->pc;
  48     }
  49 }
  50
  51 static void alpha_restore_state_to_opc(CPUState *cs,
  52                                        const TranslationBlock *tb,
  53                                        const uint64_t *data)
  54 {
  55     CPUAlphaState *env = cpu_env(cs);
  56
  57     if (tb_cflags(tb) & CF_PCREL) {
  58         env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
  59     } else {
  60         env->pc = data[0];
  61     }
  62 }
  63
  64 static bool alpha_cpu_has_work(CPUState *cs)
  65 {
  66     /* Here we are checking to see if the CPU should wake up from HALT.
  67        We will have gotten into this state only for WTINT from PALmode.  */
  68     /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
  69        asleep even if (some) interrupts have been asserted.  For now,
  70        assume that if a CPU really wants to stay asleep, it will mask
  71        interrupts at the chipset level, which will prevent these bits
  72        from being set in the first place.  */
  73     return cs->interrupt_request & (CPU_INTERRUPT_HARD
  74                                     | CPU_INTERRUPT_TIMER
  75                                     | CPU_INTERRUPT_SMP
  76                                     | CPU_INTERRUPT_MCHK);
  77 }
  78
  79 static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
  80 {
  81     return alpha_env_mmu_index(cpu_env(cs));
  82 }
  83
  84 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  85 {
  86     info->mach = bfd_mach_alpha_ev6;
  87     info->print_insn = print_insn_alpha;
  88 }
  89
  90 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
  91 {
  92     CPUState *cs = CPU(dev);
  93     AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
  94     Error *local_err = NULL;
  95
  96 #ifndef CONFIG_USER_ONLY
  97     /* Use pc-relative instructions in system-mode */
  98     cs->tcg_cflags |= CF_PCREL;
  99 #endif
 100
 101     cpu_exec_realizefn(cs, &local_err);
 102     if (local_err != NULL) {
 103         error_propagate(errp, local_err);
 104         return;
 105     }
 106
 107     qemu_init_vcpu(cs);
 108
 109     acc->parent_realize(dev, errp);
 110 }
 111
 112 /* Models */
 113 typedef struct AlphaCPUAlias {
 114     const char *alias;
 115     const char *typename;
 116 } AlphaCPUAlias;
 117
 118 static const AlphaCPUAlias alpha_cpu_aliases[] = {
 119     { "21064",   ALPHA_CPU_TYPE_NAME("ev4") },
 120     { "21164",   ALPHA_CPU_TYPE_NAME("ev5") },
 121     { "21164a",  ALPHA_CPU_TYPE_NAME("ev56") },
 122     { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
 123     { "21264",   ALPHA_CPU_TYPE_NAME("ev6") },
 124     { "21264a",  ALPHA_CPU_TYPE_NAME("ev67") },
 125 };
 126
 127 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
 128 {
 129     ObjectClass *oc;
 130     char *typename;
 131     int i;
 132
 133     oc = object_class_by_name(cpu_model);
 134     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) {
 135         return oc;
 136     }
 137
 138     for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
 139         if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
 140             oc = object_class_by_name(alpha_cpu_aliases[i].typename);
 141             assert(oc != NULL && !object_class_is_abstract(oc));
 142             return oc;
 143         }
 144     }
 145
 146     typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
 147     oc = object_class_by_name(typename);
 148     g_free(typename);
 149
 150     return oc;
 151 }
 152
 153 static void ev4_cpu_initfn(Object *obj)
 154 {
 155     cpu_env(CPU(obj))->implver = IMPLVER_2106x;
 156 }
 157
 158 static void ev5_cpu_initfn(Object *obj)
 159 {
 160     cpu_env(CPU(obj))->implver = IMPLVER_21164;
 161 }
 162
 163 static void ev56_cpu_initfn(Object *obj)
 164 {
 165     cpu_env(CPU(obj))->amask |= AMASK_BWX;
 166 }
 167
 168 static void pca56_cpu_initfn(Object *obj)
 169 {
 170     cpu_env(CPU(obj))->amask |= AMASK_MVI;
 171 }
 172
 173 static void ev6_cpu_initfn(Object *obj)
 174 {
 175     CPUAlphaState *env = cpu_env(CPU(obj));
 176
 177     env->implver = IMPLVER_21264;
 178     env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
 179 }
 180
 181 static void ev67_cpu_initfn(Object *obj)
 182 {
 183     cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH;
 184 }
 185
 186 static void alpha_cpu_initfn(Object *obj)
 187 {
 188     CPUAlphaState *env = cpu_env(CPU(obj));
 189
 190     env->lock_addr = -1;
 191 #if defined(CONFIG_USER_ONLY)
 192     env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
 193     cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
 194                                          | FPCR_UNFD | FPCR_INED | FPCR_DNOD
 195                                          | FPCR_DYN_NORMAL) << 32);
 196 #else
 197     env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;
 198 #endif
 199 }
 200
 201 #ifndef CONFIG_USER_ONLY
 202 #include "hw/core/sysemu-cpu-ops.h"
 203
 204 static const struct SysemuCPUOps alpha_sysemu_ops = {
 205     .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
 206 };
 207 #endif
 208
 209 #include "hw/core/tcg-cpu-ops.h"
 210
 211 static const TCGCPUOps alpha_tcg_ops = {
 212     .initialize = alpha_translate_init,
 213     .synchronize_from_tb = alpha_cpu_synchronize_from_tb,
 214     .restore_state_to_opc = alpha_restore_state_to_opc,
 215
 216 #ifdef CONFIG_USER_ONLY
 217     .record_sigsegv = alpha_cpu_record_sigsegv,
 218     .record_sigbus = alpha_cpu_record_sigbus,
 219 #else
 220     .tlb_fill = alpha_cpu_tlb_fill,
 221     .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
 222     .do_interrupt = alpha_cpu_do_interrupt,
 223     .do_transaction_failed = alpha_cpu_do_transaction_failed,
 224     .do_unaligned_access = alpha_cpu_do_unaligned_access,
 225 #endif /* !CONFIG_USER_ONLY */
 226 };
 227
 228 static void alpha_cpu_class_init(ObjectClass *oc, void *data)
 229 {
 230     DeviceClass *dc = DEVICE_CLASS(oc);
 231     CPUClass *cc = CPU_CLASS(oc);
 232     AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
 233
 234     device_class_set_parent_realize(dc, alpha_cpu_realizefn,
 235                                     &acc->parent_realize);
 236
 237     cc->class_by_name = alpha_cpu_class_by_name;
 238     cc->has_work = alpha_cpu_has_work;
 239     cc->mmu_index = alpha_cpu_mmu_index;
 240     cc->dump_state = alpha_cpu_dump_state;
 241     cc->set_pc = alpha_cpu_set_pc;
 242     cc->get_pc = alpha_cpu_get_pc;
 243     cc->gdb_read_register = alpha_cpu_gdb_read_register;
 244     cc->gdb_write_register = alpha_cpu_gdb_write_register;
 245 #ifndef CONFIG_USER_ONLY
 246     dc->vmsd = &vmstate_alpha_cpu;
 247     cc->sysemu_ops = &alpha_sysemu_ops;
 248 #endif
 249     cc->disas_set_info = alpha_cpu_disas_set_info;
 250
 251     cc->tcg_ops = &alpha_tcg_ops;
 252     cc->gdb_num_core_regs = 67;
 253 }
 254
 255 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
 256      {                                                      \
 257          .parent = base_type,                               \
 258          .instance_init = initfn,                           \
 259          .name = ALPHA_CPU_TYPE_NAME(cpu_model),            \
 260      }
 261
 262 static const TypeInfo alpha_cpu_type_infos[] = {
 263     {
 264         .name = TYPE_ALPHA_CPU,
 265         .parent = TYPE_CPU,
 266         .instance_size = sizeof(AlphaCPU),
 267         .instance_align = __alignof(AlphaCPU),
 268         .instance_init = alpha_cpu_initfn,
 269         .abstract = true,
 270         .class_size = sizeof(AlphaCPUClass),
 271         .class_init = alpha_cpu_class_init,
 272     },
 273     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn),
 274     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn),
 275     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn),
 276     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
 277                           pca56_cpu_initfn),
 278     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn),
 279     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn),
 280     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL),
 281 };
 282
 283 DEFINE_TYPES(alpha_cpu_type_infos)