4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
26 #include "exec/exec-all.h"
29 static void alpha_cpu_set_pc(CPUState
*cs
, vaddr value
)
31 AlphaCPU
*cpu
= ALPHA_CPU(cs
);
36 static vaddr
alpha_cpu_get_pc(CPUState
*cs
)
38 AlphaCPU
*cpu
= ALPHA_CPU(cs
);
43 static void alpha_restore_state_to_opc(CPUState
*cs
,
44 const TranslationBlock
*tb
,
47 AlphaCPU
*cpu
= ALPHA_CPU(cs
);
49 cpu
->env
.pc
= data
[0];
52 static bool alpha_cpu_has_work(CPUState
*cs
)
54 /* Here we are checking to see if the CPU should wake up from HALT.
55 We will have gotten into this state only for WTINT from PALmode. */
56 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
57 asleep even if (some) interrupts have been asserted. For now,
58 assume that if a CPU really wants to stay asleep, it will mask
59 interrupts at the chipset level, which will prevent these bits
60 from being set in the first place. */
61 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
64 | CPU_INTERRUPT_MCHK
);
67 static void alpha_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
69 info
->mach
= bfd_mach_alpha_ev6
;
70 info
->print_insn
= print_insn_alpha
;
73 static void alpha_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
75 CPUState
*cs
= CPU(dev
);
76 AlphaCPUClass
*acc
= ALPHA_CPU_GET_CLASS(dev
);
77 Error
*local_err
= NULL
;
79 cpu_exec_realizefn(cs
, &local_err
);
80 if (local_err
!= NULL
) {
81 error_propagate(errp
, local_err
);
87 acc
->parent_realize(dev
, errp
);
90 static void alpha_cpu_list_entry(gpointer data
, gpointer user_data
)
92 ObjectClass
*oc
= data
;
94 qemu_printf(" %s\n", object_class_get_name(oc
));
97 void alpha_cpu_list(void)
101 list
= object_class_get_list_sorted(TYPE_ALPHA_CPU
, false);
102 qemu_printf("Available CPUs:\n");
103 g_slist_foreach(list
, alpha_cpu_list_entry
, NULL
);
108 typedef struct AlphaCPUAlias
{
110 const char *typename
;
113 static const AlphaCPUAlias alpha_cpu_aliases
[] = {
114 { "21064", ALPHA_CPU_TYPE_NAME("ev4") },
115 { "21164", ALPHA_CPU_TYPE_NAME("ev5") },
116 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") },
117 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
118 { "21264", ALPHA_CPU_TYPE_NAME("ev6") },
119 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") },
122 static ObjectClass
*alpha_cpu_class_by_name(const char *cpu_model
)
128 oc
= object_class_by_name(cpu_model
);
129 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_ALPHA_CPU
) != NULL
) {
133 for (i
= 0; i
< ARRAY_SIZE(alpha_cpu_aliases
); i
++) {
134 if (strcmp(cpu_model
, alpha_cpu_aliases
[i
].alias
) == 0) {
135 oc
= object_class_by_name(alpha_cpu_aliases
[i
].typename
);
136 assert(oc
!= NULL
&& !object_class_is_abstract(oc
));
141 typename
= g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model
);
142 oc
= object_class_by_name(typename
);
145 /* TODO: remove match everything nonsense */
146 if (!oc
|| object_class_is_abstract(oc
)) {
147 /* Default to ev67; no reason not to emulate insns by default. */
148 oc
= object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
154 static void ev4_cpu_initfn(Object
*obj
)
156 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
157 CPUAlphaState
*env
= &cpu
->env
;
159 env
->implver
= IMPLVER_2106x
;
162 static void ev5_cpu_initfn(Object
*obj
)
164 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
165 CPUAlphaState
*env
= &cpu
->env
;
167 env
->implver
= IMPLVER_21164
;
170 static void ev56_cpu_initfn(Object
*obj
)
172 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
173 CPUAlphaState
*env
= &cpu
->env
;
175 env
->amask
|= AMASK_BWX
;
178 static void pca56_cpu_initfn(Object
*obj
)
180 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
181 CPUAlphaState
*env
= &cpu
->env
;
183 env
->amask
|= AMASK_MVI
;
186 static void ev6_cpu_initfn(Object
*obj
)
188 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
189 CPUAlphaState
*env
= &cpu
->env
;
191 env
->implver
= IMPLVER_21264
;
192 env
->amask
= AMASK_BWX
| AMASK_FIX
| AMASK_MVI
| AMASK_TRAP
;
195 static void ev67_cpu_initfn(Object
*obj
)
197 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
198 CPUAlphaState
*env
= &cpu
->env
;
200 env
->amask
|= AMASK_CIX
| AMASK_PREFETCH
;
203 static void alpha_cpu_initfn(Object
*obj
)
205 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
206 CPUAlphaState
*env
= &cpu
->env
;
209 #if defined(CONFIG_USER_ONLY)
210 env
->flags
= ENV_FLAG_PS_USER
| ENV_FLAG_FEN
;
211 cpu_alpha_store_fpcr(env
, (uint64_t)(FPCR_INVD
| FPCR_DZED
| FPCR_OVFD
212 | FPCR_UNFD
| FPCR_INED
| FPCR_DNOD
213 | FPCR_DYN_NORMAL
) << 32);
215 env
->flags
= ENV_FLAG_PAL_MODE
| ENV_FLAG_FEN
;
219 #ifndef CONFIG_USER_ONLY
220 #include "hw/core/sysemu-cpu-ops.h"
222 static const struct SysemuCPUOps alpha_sysemu_ops
= {
223 .get_phys_page_debug
= alpha_cpu_get_phys_page_debug
,
227 #include "hw/core/tcg-cpu-ops.h"
229 static const struct TCGCPUOps alpha_tcg_ops
= {
230 .initialize
= alpha_translate_init
,
231 .restore_state_to_opc
= alpha_restore_state_to_opc
,
233 #ifdef CONFIG_USER_ONLY
234 .record_sigsegv
= alpha_cpu_record_sigsegv
,
235 .record_sigbus
= alpha_cpu_record_sigbus
,
237 .tlb_fill
= alpha_cpu_tlb_fill
,
238 .cpu_exec_interrupt
= alpha_cpu_exec_interrupt
,
239 .do_interrupt
= alpha_cpu_do_interrupt
,
240 .do_transaction_failed
= alpha_cpu_do_transaction_failed
,
241 .do_unaligned_access
= alpha_cpu_do_unaligned_access
,
242 #endif /* !CONFIG_USER_ONLY */
245 static void alpha_cpu_class_init(ObjectClass
*oc
, void *data
)
247 DeviceClass
*dc
= DEVICE_CLASS(oc
);
248 CPUClass
*cc
= CPU_CLASS(oc
);
249 AlphaCPUClass
*acc
= ALPHA_CPU_CLASS(oc
);
251 device_class_set_parent_realize(dc
, alpha_cpu_realizefn
,
252 &acc
->parent_realize
);
254 cc
->class_by_name
= alpha_cpu_class_by_name
;
255 cc
->has_work
= alpha_cpu_has_work
;
256 cc
->dump_state
= alpha_cpu_dump_state
;
257 cc
->set_pc
= alpha_cpu_set_pc
;
258 cc
->get_pc
= alpha_cpu_get_pc
;
259 cc
->gdb_read_register
= alpha_cpu_gdb_read_register
;
260 cc
->gdb_write_register
= alpha_cpu_gdb_write_register
;
261 #ifndef CONFIG_USER_ONLY
262 dc
->vmsd
= &vmstate_alpha_cpu
;
263 cc
->sysemu_ops
= &alpha_sysemu_ops
;
265 cc
->disas_set_info
= alpha_cpu_disas_set_info
;
267 cc
->tcg_ops
= &alpha_tcg_ops
;
268 cc
->gdb_num_core_regs
= 67;
271 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
273 .parent = base_type, \
274 .instance_init = initfn, \
275 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \
278 static const TypeInfo alpha_cpu_type_infos
[] = {
280 .name
= TYPE_ALPHA_CPU
,
282 .instance_size
= sizeof(AlphaCPU
),
283 .instance_align
= __alignof(AlphaCPU
),
284 .instance_init
= alpha_cpu_initfn
,
286 .class_size
= sizeof(AlphaCPUClass
),
287 .class_init
= alpha_cpu_class_init
,
289 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev4", ev4_cpu_initfn
),
290 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev5", ev5_cpu_initfn
),
291 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn
),
292 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
294 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev6", ev6_cpu_initfn
),
295 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn
),
296 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL
),
299 DEFINE_TYPES(alpha_cpu_type_infos
)