target/alpha/cpu.h

   1 /*
   2  *  Alpha emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef ALPHA_CPU_H
  21 #define ALPHA_CPU_H
  22
  23 #include "qemu-common.h"
  24 #include "cpu-qom.h"
  25
  26 #define TARGET_LONG_BITS 64
  27 #define ALIGNED_ONLY
  28
  29 #define CPUArchState struct CPUAlphaState
  30
  31 /* Alpha processors have a weak memory model */
  32 #define TCG_GUEST_DEFAULT_MO      (0)
  33
  34 #include "exec/cpu-defs.h"
  35
  36 #define ICACHE_LINE_SIZE 32
  37 #define DCACHE_LINE_SIZE 32
  38
  39 #define TARGET_PAGE_BITS 13
  40
  41 #ifdef CONFIG_USER_ONLY
  42 /* ??? The kernel likes to give addresses in high memory.  If the host has
  43    more virtual address space than the guest, this can lead to impossible
  44    allocations.  Honor the long-standing assumption that only kernel addrs
  45    are negative, but otherwise allow allocations anywhere.  This could lead
  46    to tricky emulation problems for programs doing tagged addressing, but
  47    that's far fewer than encounter the impossible allocation problem.  */
  48 #define TARGET_PHYS_ADDR_SPACE_BITS  63
  49 #define TARGET_VIRT_ADDR_SPACE_BITS  63
  50 #else
  51 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
  52 #define TARGET_PHYS_ADDR_SPACE_BITS  44
  53 #define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
  54 #endif
  55
  56 /* Alpha major type */
  57 enum {
  58     ALPHA_EV3  = 1,
  59     ALPHA_EV4  = 2,
  60     ALPHA_SIM  = 3,
  61     ALPHA_LCA  = 4,
  62     ALPHA_EV5  = 5, /* 21164 */
  63     ALPHA_EV45 = 6, /* 21064A */
  64     ALPHA_EV56 = 7, /* 21164A */
  65 };
  66
  67 /* EV4 minor type */
  68 enum {
  69     ALPHA_EV4_2 = 0,
  70     ALPHA_EV4_3 = 1,
  71 };
  72
  73 /* LCA minor type */
  74 enum {
  75     ALPHA_LCA_1 = 1, /* 21066 */
  76     ALPHA_LCA_2 = 2, /* 20166 */
  77     ALPHA_LCA_3 = 3, /* 21068 */
  78     ALPHA_LCA_4 = 4, /* 21068 */
  79     ALPHA_LCA_5 = 5, /* 21066A */
  80     ALPHA_LCA_6 = 6, /* 21068A */
  81 };
  82
  83 /* EV5 minor type */
  84 enum {
  85     ALPHA_EV5_1 = 1, /* Rev BA, CA */
  86     ALPHA_EV5_2 = 2, /* Rev DA, EA */
  87     ALPHA_EV5_3 = 3, /* Pass 3 */
  88     ALPHA_EV5_4 = 4, /* Pass 3.2 */
  89     ALPHA_EV5_5 = 5, /* Pass 4 */
  90 };
  91
  92 /* EV45 minor type */
  93 enum {
  94     ALPHA_EV45_1 = 1, /* Pass 1 */
  95     ALPHA_EV45_2 = 2, /* Pass 1.1 */
  96     ALPHA_EV45_3 = 3, /* Pass 2 */
  97 };
  98
  99 /* EV56 minor type */
 100 enum {
 101     ALPHA_EV56_1 = 1, /* Pass 1 */
 102     ALPHA_EV56_2 = 2, /* Pass 2 */
 103 };
 104
 105 enum {
 106     IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
 107     IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
 108     IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
 109     IMPLVER_21364 = 3, /* EV7 & EV79 */
 110 };
 111
 112 enum {
 113     AMASK_BWX      = 0x00000001,
 114     AMASK_FIX      = 0x00000002,
 115     AMASK_CIX      = 0x00000004,
 116     AMASK_MVI      = 0x00000100,
 117     AMASK_TRAP     = 0x00000200,
 118     AMASK_PREFETCH = 0x00001000,
 119 };
 120
 121 enum {
 122     VAX_ROUND_NORMAL = 0,
 123     VAX_ROUND_CHOPPED,
 124 };
 125
 126 enum {
 127     IEEE_ROUND_NORMAL = 0,
 128     IEEE_ROUND_DYNAMIC,
 129     IEEE_ROUND_PLUS,
 130     IEEE_ROUND_MINUS,
 131     IEEE_ROUND_CHOPPED,
 132 };
 133
 134 /* IEEE floating-point operations encoding */
 135 /* Trap mode */
 136 enum {
 137     FP_TRAP_I   = 0x0,
 138     FP_TRAP_U   = 0x1,
 139     FP_TRAP_S  = 0x4,
 140     FP_TRAP_SU  = 0x5,
 141     FP_TRAP_SUI = 0x7,
 142 };
 143
 144 /* Rounding mode */
 145 enum {
 146     FP_ROUND_CHOPPED = 0x0,
 147     FP_ROUND_MINUS   = 0x1,
 148     FP_ROUND_NORMAL  = 0x2,
 149     FP_ROUND_DYNAMIC = 0x3,
 150 };
 151
 152 /* FPCR bits -- right-shifted 32 so we can use a uint32_t.  */
 153 #define FPCR_SUM                (1U << (63 - 32))
 154 #define FPCR_INED               (1U << (62 - 32))
 155 #define FPCR_UNFD               (1U << (61 - 32))
 156 #define FPCR_UNDZ               (1U << (60 - 32))
 157 #define FPCR_DYN_SHIFT          (58 - 32)
 158 #define FPCR_DYN_CHOPPED        (0U << FPCR_DYN_SHIFT)
 159 #define FPCR_DYN_MINUS          (1U << FPCR_DYN_SHIFT)
 160 #define FPCR_DYN_NORMAL         (2U << FPCR_DYN_SHIFT)
 161 #define FPCR_DYN_PLUS           (3U << FPCR_DYN_SHIFT)
 162 #define FPCR_DYN_MASK           (3U << FPCR_DYN_SHIFT)
 163 #define FPCR_IOV                (1U << (57 - 32))
 164 #define FPCR_INE                (1U << (56 - 32))
 165 #define FPCR_UNF                (1U << (55 - 32))
 166 #define FPCR_OVF                (1U << (54 - 32))
 167 #define FPCR_DZE                (1U << (53 - 32))
 168 #define FPCR_INV                (1U << (52 - 32))
 169 #define FPCR_OVFD               (1U << (51 - 32))
 170 #define FPCR_DZED               (1U << (50 - 32))
 171 #define FPCR_INVD               (1U << (49 - 32))
 172 #define FPCR_DNZ                (1U << (48 - 32))
 173 #define FPCR_DNOD               (1U << (47 - 32))
 174 #define FPCR_STATUS_MASK        (FPCR_IOV | FPCR_INE | FPCR_UNF \
 175                                  | FPCR_OVF | FPCR_DZE | FPCR_INV)
 176
 177 /* The silly software trap enables implemented by the kernel emulation.
 178    These are more or less architecturally required, since the real hardware
 179    has read-as-zero bits in the FPCR when the features aren't implemented.
 180    For the purposes of QEMU, we pretend the FPCR can hold everything.  */
 181 #define SWCR_TRAP_ENABLE_INV    (1U << 1)
 182 #define SWCR_TRAP_ENABLE_DZE    (1U << 2)
 183 #define SWCR_TRAP_ENABLE_OVF    (1U << 3)
 184 #define SWCR_TRAP_ENABLE_UNF    (1U << 4)
 185 #define SWCR_TRAP_ENABLE_INE    (1U << 5)
 186 #define SWCR_TRAP_ENABLE_DNO    (1U << 6)
 187 #define SWCR_TRAP_ENABLE_MASK   ((1U << 7) - (1U << 1))
 188
 189 #define SWCR_MAP_DMZ            (1U << 12)
 190 #define SWCR_MAP_UMZ            (1U << 13)
 191 #define SWCR_MAP_MASK           (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
 192
 193 #define SWCR_STATUS_INV         (1U << 17)
 194 #define SWCR_STATUS_DZE         (1U << 18)
 195 #define SWCR_STATUS_OVF         (1U << 19)
 196 #define SWCR_STATUS_UNF         (1U << 20)
 197 #define SWCR_STATUS_INE         (1U << 21)
 198 #define SWCR_STATUS_DNO         (1U << 22)
 199 #define SWCR_STATUS_MASK        ((1U << 23) - (1U << 17))
 200
 201 #define SWCR_STATUS_TO_EXCSUM_SHIFT  16
 202
 203 #define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
 204
 205 /* MMU modes definitions */
 206
 207 /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
 208    The Unix PALcode only exposes the kernel and user modes; presumably
 209    executive and supervisor are used by VMS.
 210
 211    PALcode itself uses physical mode for code and kernel mode for data;
 212    there are PALmode instructions that can access data via physical mode
 213    or via an os-installed "alternate mode", which is one of the 4 above.
 214
 215    That said, we're only emulating Unix PALcode, and not attempting VMS,
 216    so we don't need to implement Executive and Supervisor.  QEMU's own
 217    PALcode cheats and usees the KSEG mapping for its code+data rather than
 218    physical addresses.  */
 219
 220 #define NB_MMU_MODES 3
 221
 222 #define MMU_MODE0_SUFFIX _kernel
 223 #define MMU_MODE1_SUFFIX _user
 224 #define MMU_KERNEL_IDX   0
 225 #define MMU_USER_IDX     1
 226 #define MMU_PHYS_IDX     2
 227
 228 typedef struct CPUAlphaState CPUAlphaState;
 229
 230 struct CPUAlphaState {
 231     uint64_t ir[31];
 232     float64 fir[31];
 233     uint64_t pc;
 234     uint64_t unique;
 235     uint64_t lock_addr;
 236     uint64_t lock_value;
 237
 238     /* The FPCR, and disassembled portions thereof.  */
 239     uint32_t fpcr;
 240 #ifdef CONFIG_USER_ONLY
 241     uint32_t swcr;
 242 #endif
 243     uint32_t fpcr_exc_enable;
 244     float_status fp_status;
 245     uint8_t fpcr_dyn_round;
 246     uint8_t fpcr_flush_to_zero;
 247
 248     /* Mask of PALmode, Processor State et al.  Most of this gets copied
 249        into the TranslatorBlock flags and controls code generation.  */
 250     uint32_t flags;
 251
 252     /* The high 32-bits of the processor cycle counter.  */
 253     uint32_t pcc_ofs;
 254
 255     /* These pass data from the exception logic in the translator and
 256        helpers to the OS entry point.  This is used for both system
 257        emulation and user-mode.  */
 258     uint64_t trap_arg0;
 259     uint64_t trap_arg1;
 260     uint64_t trap_arg2;
 261
 262 #if !defined(CONFIG_USER_ONLY)
 263     /* The internal data required by our emulation of the Unix PALcode.  */
 264     uint64_t exc_addr;
 265     uint64_t palbr;
 266     uint64_t ptbr;
 267     uint64_t vptptr;
 268     uint64_t sysval;
 269     uint64_t usp;
 270     uint64_t shadow[8];
 271     uint64_t scratch[24];
 272 #endif
 273
 274     /* This alarm doesn't exist in real hardware; we wish it did.  */
 275     uint64_t alarm_expire;
 276
 277     /* Those resources are used only in QEMU core */
 278     CPU_COMMON
 279
 280     int error_code;
 281
 282     uint32_t features;
 283     uint32_t amask;
 284     int implver;
 285 };
 286
 287 /**
 288  * AlphaCPU:
 289  * @env: #CPUAlphaState
 290  *
 291  * An Alpha CPU.
 292  */
 293 struct AlphaCPU {
 294     /*< private >*/
 295     CPUState parent_obj;
 296     /*< public >*/
 297
 298     CPUAlphaState env;
 299
 300     /* This alarm doesn't exist in real hardware; we wish it did.  */
 301     QEMUTimer *alarm_timer;
 302 };
 303
 304 static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
 305 {
 306     return container_of(env, AlphaCPU, env);
 307 }
 308
 309 #define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e))
 310
 311 #define ENV_OFFSET offsetof(AlphaCPU, env)
 312
 313 #ifndef CONFIG_USER_ONLY
 314 extern const struct VMStateDescription vmstate_alpha_cpu;
 315 #endif
 316
 317 void alpha_cpu_do_interrupt(CPUState *cpu);
 318 bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
 319 void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
 320 hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 321 int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 322 int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 323 void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 324                                    MMUAccessType access_type,
 325                                    int mmu_idx, uintptr_t retaddr);
 326
 327 #define cpu_list alpha_cpu_list
 328 #define cpu_signal_handler cpu_alpha_signal_handler
 329
 330 #include "exec/cpu-all.h"
 331
 332 enum {
 333     FEATURE_ASN    = 0x00000001,
 334     FEATURE_SPS    = 0x00000002,
 335     FEATURE_VIRBND = 0x00000004,
 336     FEATURE_TBCHK  = 0x00000008,
 337 };
 338
 339 enum {
 340     EXCP_RESET,
 341     EXCP_MCHK,
 342     EXCP_SMP_INTERRUPT,
 343     EXCP_CLK_INTERRUPT,
 344     EXCP_DEV_INTERRUPT,
 345     EXCP_MMFAULT,
 346     EXCP_UNALIGN,
 347     EXCP_OPCDEC,
 348     EXCP_ARITH,
 349     EXCP_FEN,
 350     EXCP_CALL_PAL,
 351 };
 352
 353 /* Alpha-specific interrupt pending bits.  */
 354 #define CPU_INTERRUPT_TIMER     CPU_INTERRUPT_TGT_EXT_0
 355 #define CPU_INTERRUPT_SMP       CPU_INTERRUPT_TGT_EXT_1
 356 #define CPU_INTERRUPT_MCHK      CPU_INTERRUPT_TGT_EXT_2
 357
 358 /* OSF/1 Page table bits.  */
 359 enum {
 360     PTE_VALID = 0x0001,
 361     PTE_FOR   = 0x0002,  /* used for page protection (fault on read) */
 362     PTE_FOW   = 0x0004,  /* used for page protection (fault on write) */
 363     PTE_FOE   = 0x0008,  /* used for page protection (fault on exec) */
 364     PTE_ASM   = 0x0010,
 365     PTE_KRE   = 0x0100,
 366     PTE_URE   = 0x0200,
 367     PTE_KWE   = 0x1000,
 368     PTE_UWE   = 0x2000
 369 };
 370
 371 /* Hardware interrupt (entInt) constants.  */
 372 enum {
 373     INT_K_IP,
 374     INT_K_CLK,
 375     INT_K_MCHK,
 376     INT_K_DEV,
 377     INT_K_PERF,
 378 };
 379
 380 /* Memory management (entMM) constants.  */
 381 enum {
 382     MM_K_TNV,
 383     MM_K_ACV,
 384     MM_K_FOR,
 385     MM_K_FOE,
 386     MM_K_FOW
 387 };
 388
 389 /* Arithmetic exception (entArith) constants.  */
 390 enum {
 391     EXC_M_SWC = 1,      /* Software completion */
 392     EXC_M_INV = 2,      /* Invalid operation */
 393     EXC_M_DZE = 4,      /* Division by zero */
 394     EXC_M_FOV = 8,      /* Overflow */
 395     EXC_M_UNF = 16,     /* Underflow */
 396     EXC_M_INE = 32,     /* Inexact result */
 397     EXC_M_IOV = 64      /* Integer Overflow */
 398 };
 399
 400 /* Processor status constants.  */
 401 /* Low 3 bits are interrupt mask level.  */
 402 #define PS_INT_MASK   7u
 403
 404 /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
 405    The Unix PALcode only uses bit 4.  */
 406 #define PS_USER_MODE  8u
 407
 408 /* CPUAlphaState->flags constants.  These are layed out so that we
 409    can set or reset the pieces individually by assigning to the byte,
 410    or manipulated as a whole.  */
 411
 412 #define ENV_FLAG_PAL_SHIFT    0
 413 #define ENV_FLAG_PS_SHIFT     8
 414 #define ENV_FLAG_RX_SHIFT     16
 415 #define ENV_FLAG_FEN_SHIFT    24
 416
 417 #define ENV_FLAG_PAL_MODE     (1u << ENV_FLAG_PAL_SHIFT)
 418 #define ENV_FLAG_PS_USER      (PS_USER_MODE << ENV_FLAG_PS_SHIFT)
 419 #define ENV_FLAG_RX_FLAG      (1u << ENV_FLAG_RX_SHIFT)
 420 #define ENV_FLAG_FEN          (1u << ENV_FLAG_FEN_SHIFT)
 421
 422 #define ENV_FLAG_TB_MASK \
 423     (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
 424
 425 static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
 426 {
 427     int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
 428     if (env->flags & ENV_FLAG_PAL_MODE) {
 429         ret = MMU_KERNEL_IDX;
 430     }
 431     return ret;
 432 }
 433
 434 enum {
 435     IR_V0   = 0,
 436     IR_T0   = 1,
 437     IR_T1   = 2,
 438     IR_T2   = 3,
 439     IR_T3   = 4,
 440     IR_T4   = 5,
 441     IR_T5   = 6,
 442     IR_T6   = 7,
 443     IR_T7   = 8,
 444     IR_S0   = 9,
 445     IR_S1   = 10,
 446     IR_S2   = 11,
 447     IR_S3   = 12,
 448     IR_S4   = 13,
 449     IR_S5   = 14,
 450     IR_S6   = 15,
 451     IR_FP   = IR_S6,
 452     IR_A0   = 16,
 453     IR_A1   = 17,
 454     IR_A2   = 18,
 455     IR_A3   = 19,
 456     IR_A4   = 20,
 457     IR_A5   = 21,
 458     IR_T8   = 22,
 459     IR_T9   = 23,
 460     IR_T10  = 24,
 461     IR_T11  = 25,
 462     IR_RA   = 26,
 463     IR_T12  = 27,
 464     IR_PV   = IR_T12,
 465     IR_AT   = 28,
 466     IR_GP   = 29,
 467     IR_SP   = 30,
 468     IR_ZERO = 31,
 469 };
 470
 471 void alpha_translate_init(void);
 472
 473 #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
 474 #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
 475 #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
 476
 477 void alpha_cpu_list(void);
 478 /* you can call this signal handler from your SIGBUS and SIGSEGV
 479    signal handlers to inform the virtual CPU of exceptions. non zero
 480    is returned if the signal was handled by the virtual CPU.  */
 481 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
 482                              void *puc);
 483 bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 484                         MMUAccessType access_type, int mmu_idx,
 485                         bool probe, uintptr_t retaddr);
 486 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
 487 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
 488
 489 uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
 490 void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
 491 uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
 492 void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
 493 #ifndef CONFIG_USER_ONLY
 494 void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 495                                      vaddr addr, unsigned size,
 496                                      MMUAccessType access_type,
 497                                      int mmu_idx, MemTxAttrs attrs,
 498                                      MemTxResult response, uintptr_t retaddr);
 499 #endif
 500
 501 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
 502                                         target_ulong *cs_base, uint32_t *pflags)
 503 {
 504     *pc = env->pc;
 505     *cs_base = 0;
 506     *pflags = env->flags & ENV_FLAG_TB_MASK;
 507 }
 508
 509 #ifdef CONFIG_USER_ONLY
 510 /* Copied from linux ieee_swcr_to_fpcr.  */
 511 static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
 512 {
 513     uint64_t fpcr = 0;
 514
 515     fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
 516     fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
 517     fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
 518                       | SWCR_TRAP_ENABLE_DZE
 519                       | SWCR_TRAP_ENABLE_OVF)) << 48;
 520     fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
 521                       | SWCR_TRAP_ENABLE_INE)) << 57;
 522     fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
 523     fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
 524
 525     return fpcr;
 526 }
 527
 528 /* Copied from linux ieee_fpcr_to_swcr.  */
 529 static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
 530 {
 531     uint64_t swcr = 0;
 532
 533     swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
 534     swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
 535     swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
 536                              | SWCR_TRAP_ENABLE_DZE
 537                              | SWCR_TRAP_ENABLE_OVF);
 538     swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
 539     swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
 540     swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
 541
 542     return swcr;
 543 }
 544 #endif /* CONFIG_USER_ONLY */
 545
 546 #endif /* ALPHA_CPU_H */