4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 /* CPUClass::reset() */
159 static void arm_cpu_reset(CPUState
*s
)
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(s
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
178 s
->halted
= cpu
->start_powered_off
;
180 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
181 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
184 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
185 /* 64 bit CPUs always start in 64 bit mode */
187 #if defined(CONFIG_USER_ONLY)
188 env
->pstate
= PSTATE_MODE_EL0t
;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
191 /* Enable all PAC keys. */
192 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
193 SCTLR_EnDA
| SCTLR_EnDB
);
194 /* Enable all PAC instructions */
195 env
->cp15
.hcr_el2
|= HCR_API
;
196 env
->cp15
.scr_el3
|= SCR_API
;
197 /* and to the FP/Neon instructions */
198 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
199 /* and to the SVE instructions */
200 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
201 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
202 /* with maximum vector length */
203 env
->vfp
.zcr_el
[1] = cpu_isar_feature(aa64_sve
, cpu
) ?
204 cpu
->sve_max_vq
- 1 : 0;
205 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
206 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
208 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
209 * turning on both here will produce smaller code and otherwise
210 * make no difference to the user-level emulation.
212 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
214 /* Reset into the highest available EL */
215 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
216 env
->pstate
= PSTATE_MODE_EL3h
;
217 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
218 env
->pstate
= PSTATE_MODE_EL2h
;
220 env
->pstate
= PSTATE_MODE_EL1h
;
222 env
->pc
= cpu
->rvbar
;
225 #if defined(CONFIG_USER_ONLY)
226 /* Userspace expects access to cp10 and cp11 for FP/Neon */
227 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
231 #if defined(CONFIG_USER_ONLY)
232 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
233 /* For user mode we must enable access to coprocessors */
234 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
235 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
236 env
->cp15
.c15_cpar
= 3;
237 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
238 env
->cp15
.c15_cpar
= 1;
243 * If the highest available EL is EL2, AArch32 will start in Hyp
244 * mode; otherwise it starts in SVC. Note that if we start in
245 * AArch64 then these values in the uncached_cpsr will be ignored.
247 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
248 !arm_feature(env
, ARM_FEATURE_EL3
)) {
249 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
251 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
253 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
255 if (arm_feature(env
, ARM_FEATURE_M
)) {
256 uint32_t initial_msp
; /* Loaded from 0x0 */
257 uint32_t initial_pc
; /* Loaded from 0x4 */
261 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
262 env
->v7m
.secure
= true;
264 /* This bit resets to 0 if security is supported, but 1 if
265 * it is not. The bit is not present in v7M, but we set it
266 * here so we can avoid having to make checks on it conditional
267 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
269 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
271 * Set NSACR to indicate "NS access permitted to everything";
272 * this avoids having to have all the tests of it being
273 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
274 * v8.1M the guest-visible value of NSACR in a CPU without the
275 * Security Extension is 0xcff.
277 env
->v7m
.nsacr
= 0xcff;
280 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
281 * that it resets to 1, so QEMU always does that rather than making
282 * it dependent on CPU model. In v8M it is RES1.
284 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
285 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
286 if (arm_feature(env
, ARM_FEATURE_V8
)) {
287 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
288 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
289 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
291 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
292 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
293 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
296 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
297 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
298 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
299 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
301 /* Unlike A/R profile, M profile defines the reset LR value */
302 env
->regs
[14] = 0xffffffff;
304 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
306 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
307 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
308 rom
= rom_ptr(vecbase
, 8);
310 /* Address zero is covered by ROM which hasn't yet been
311 * copied into physical memory.
313 initial_msp
= ldl_p(rom
);
314 initial_pc
= ldl_p(rom
+ 4);
316 /* Address zero not covered by a ROM blob, or the ROM blob
317 * is in non-modifiable memory and this is a second reset after
318 * it got copied into memory. In the latter case, rom_ptr
319 * will return a NULL pointer and we should use ldl_phys instead.
321 initial_msp
= ldl_phys(s
->as
, vecbase
);
322 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
325 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
326 env
->regs
[15] = initial_pc
& ~1;
327 env
->thumb
= initial_pc
& 1;
330 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
331 * executing as AArch32 then check if highvecs are enabled and
332 * adjust the PC accordingly.
334 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
335 env
->regs
[15] = 0xFFFF0000;
338 /* M profile requires that reset clears the exclusive monitor;
339 * A profile does not, but clearing it makes more sense than having it
340 * set with an exclusive access on address zero.
342 arm_clear_exclusive(env
);
344 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
347 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
348 if (cpu
->pmsav7_dregion
> 0) {
349 if (arm_feature(env
, ARM_FEATURE_V8
)) {
350 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
351 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
352 * cpu
->pmsav7_dregion
);
353 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
354 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
355 * cpu
->pmsav7_dregion
);
356 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
357 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
358 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
359 * cpu
->pmsav7_dregion
);
360 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
361 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
362 * cpu
->pmsav7_dregion
);
364 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
365 memset(env
->pmsav7
.drbar
, 0,
366 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
367 memset(env
->pmsav7
.drsr
, 0,
368 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
369 memset(env
->pmsav7
.dracr
, 0,
370 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
373 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
374 env
->pmsav7
.rnr
[M_REG_S
] = 0;
375 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
376 env
->pmsav8
.mair0
[M_REG_S
] = 0;
377 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
378 env
->pmsav8
.mair1
[M_REG_S
] = 0;
381 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
382 if (cpu
->sau_sregion
> 0) {
383 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
384 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
387 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
388 * the Cortex-M33 does.
393 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
394 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
395 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
396 set_float_detect_tininess(float_tininess_before_rounding
,
397 &env
->vfp
.fp_status
);
398 set_float_detect_tininess(float_tininess_before_rounding
,
399 &env
->vfp
.standard_fp_status
);
400 set_float_detect_tininess(float_tininess_before_rounding
,
401 &env
->vfp
.fp_status_f16
);
402 #ifndef CONFIG_USER_ONLY
404 kvm_arm_reset_vcpu(cpu
);
408 hw_breakpoint_update_all(cpu
);
409 hw_watchpoint_update_all(cpu
);
410 arm_rebuild_hflags(env
);
413 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
414 unsigned int target_el
,
415 unsigned int cur_el
, bool secure
,
418 CPUARMState
*env
= cs
->env_ptr
;
419 bool pstate_unmasked
;
420 bool unmasked
= false;
423 * Don't take exceptions if they target a lower EL.
424 * This check should catch any exceptions that would not be taken
427 if (cur_el
> target_el
) {
433 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
437 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
441 if (secure
|| !(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
442 /* VFIQs are only taken when hypervized and non-secure. */
445 return !(env
->daif
& PSTATE_F
);
447 if (secure
|| !(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
448 /* VIRQs are only taken when hypervized and non-secure. */
451 return !(env
->daif
& PSTATE_I
);
453 g_assert_not_reached();
457 * Use the target EL, current execution state and SCR/HCR settings to
458 * determine whether the corresponding CPSR bit is used to mask the
461 if ((target_el
> cur_el
) && (target_el
!= 1)) {
462 /* Exceptions targeting a higher EL may not be maskable */
463 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
465 * 64-bit masking rules are simple: exceptions to EL3
466 * can't be masked, and exceptions to EL2 can only be
467 * masked from Secure state. The HCR and SCR settings
468 * don't affect the masking logic, only the interrupt routing.
470 if (target_el
== 3 || !secure
) {
475 * The old 32-bit-only environment has a more complicated
476 * masking setup. HCR and SCR bits not only affect interrupt
477 * routing but also change the behaviour of masking.
484 * If FIQs are routed to EL3 or EL2 then there are cases where
485 * we override the CPSR.F in determining if the exception is
486 * masked or not. If neither of these are set then we fall back
487 * to the CPSR.F setting otherwise we further assess the state
490 hcr
= hcr_el2
& HCR_FMO
;
491 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
494 * When EL3 is 32-bit, the SCR.FW bit controls whether the
495 * CPSR.F bit masks FIQ interrupts when taken in non-secure
496 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
497 * when non-secure but only when FIQs are only routed to EL3.
499 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
503 * When EL3 execution state is 32-bit, if HCR.IMO is set then
504 * we may override the CPSR.I masking when in non-secure state.
505 * The SCR.IRQ setting has already been taken into consideration
506 * when setting the target EL, so it does not have a further
509 hcr
= hcr_el2
& HCR_IMO
;
513 g_assert_not_reached();
516 if ((scr
|| hcr
) && !secure
) {
523 * The PSTATE bits only mask the interrupt if we have not overriden the
526 return unmasked
|| pstate_unmasked
;
529 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
531 CPUClass
*cc
= CPU_GET_CLASS(cs
);
532 CPUARMState
*env
= cs
->env_ptr
;
533 uint32_t cur_el
= arm_current_el(env
);
534 bool secure
= arm_is_secure(env
);
535 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
540 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
542 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
543 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
544 cur_el
, secure
, hcr_el2
)) {
545 cs
->exception_index
= excp_idx
;
546 env
->exception
.target_el
= target_el
;
547 cc
->do_interrupt(cs
);
551 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
553 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
554 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
555 cur_el
, secure
, hcr_el2
)) {
556 cs
->exception_index
= excp_idx
;
557 env
->exception
.target_el
= target_el
;
558 cc
->do_interrupt(cs
);
562 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
563 excp_idx
= EXCP_VIRQ
;
565 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
566 cur_el
, secure
, hcr_el2
)) {
567 cs
->exception_index
= excp_idx
;
568 env
->exception
.target_el
= target_el
;
569 cc
->do_interrupt(cs
);
573 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
574 excp_idx
= EXCP_VFIQ
;
576 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
577 cur_el
, secure
, hcr_el2
)) {
578 cs
->exception_index
= excp_idx
;
579 env
->exception
.target_el
= target_el
;
580 cc
->do_interrupt(cs
);
588 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
589 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
591 CPUClass
*cc
= CPU_GET_CLASS(cs
);
592 ARMCPU
*cpu
= ARM_CPU(cs
);
593 CPUARMState
*env
= &cpu
->env
;
596 /* ARMv7-M interrupt masking works differently than -A or -R.
597 * There is no FIQ/IRQ distinction. Instead of I and F bits
598 * masking FIQ and IRQ interrupts, an exception is taken only
599 * if it is higher priority than the current execution priority
600 * (which depends on state like BASEPRI, FAULTMASK and the
601 * currently active exception).
603 if (interrupt_request
& CPU_INTERRUPT_HARD
604 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
605 cs
->exception_index
= EXCP_IRQ
;
606 cc
->do_interrupt(cs
);
613 void arm_cpu_update_virq(ARMCPU
*cpu
)
616 * Update the interrupt level for VIRQ, which is the logical OR of
617 * the HCR_EL2.VI bit and the input line level from the GIC.
619 CPUARMState
*env
= &cpu
->env
;
620 CPUState
*cs
= CPU(cpu
);
622 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
623 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
625 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
627 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
629 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
634 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
637 * Update the interrupt level for VFIQ, which is the logical OR of
638 * the HCR_EL2.VF bit and the input line level from the GIC.
640 CPUARMState
*env
= &cpu
->env
;
641 CPUState
*cs
= CPU(cpu
);
643 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
644 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
646 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
648 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
650 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
655 #ifndef CONFIG_USER_ONLY
656 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
658 ARMCPU
*cpu
= opaque
;
659 CPUARMState
*env
= &cpu
->env
;
660 CPUState
*cs
= CPU(cpu
);
661 static const int mask
[] = {
662 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
663 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
664 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
665 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
669 env
->irq_line_state
|= mask
[irq
];
671 env
->irq_line_state
&= ~mask
[irq
];
676 assert(arm_feature(env
, ARM_FEATURE_EL2
));
677 arm_cpu_update_virq(cpu
);
680 assert(arm_feature(env
, ARM_FEATURE_EL2
));
681 arm_cpu_update_vfiq(cpu
);
686 cpu_interrupt(cs
, mask
[irq
]);
688 cpu_reset_interrupt(cs
, mask
[irq
]);
692 g_assert_not_reached();
696 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
699 ARMCPU
*cpu
= opaque
;
700 CPUARMState
*env
= &cpu
->env
;
701 CPUState
*cs
= CPU(cpu
);
702 uint32_t linestate_bit
;
707 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
708 linestate_bit
= CPU_INTERRUPT_HARD
;
711 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
712 linestate_bit
= CPU_INTERRUPT_FIQ
;
715 g_assert_not_reached();
719 env
->irq_line_state
|= linestate_bit
;
721 env
->irq_line_state
&= ~linestate_bit
;
723 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
727 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
729 ARMCPU
*cpu
= ARM_CPU(cs
);
730 CPUARMState
*env
= &cpu
->env
;
732 cpu_synchronize_state(cs
);
733 return arm_cpu_data_is_big_endian(env
);
738 static inline void set_feature(CPUARMState
*env
, int feature
)
740 env
->features
|= 1ULL << feature
;
743 static inline void unset_feature(CPUARMState
*env
, int feature
)
745 env
->features
&= ~(1ULL << feature
);
749 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
751 return print_insn_arm(pc
| 1, info
);
754 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
756 ARMCPU
*ac
= ARM_CPU(cpu
);
757 CPUARMState
*env
= &ac
->env
;
761 /* We might not be compiled with the A64 disassembler
762 * because it needs a C++ compiler. Leave print_insn
763 * unset in this case to use the caller default behaviour.
765 #if defined(CONFIG_ARM_A64_DIS)
766 info
->print_insn
= print_insn_arm_a64
;
768 info
->cap_arch
= CS_ARCH_ARM64
;
769 info
->cap_insn_unit
= 4;
770 info
->cap_insn_split
= 4;
774 info
->print_insn
= print_insn_thumb1
;
775 info
->cap_insn_unit
= 2;
776 info
->cap_insn_split
= 4;
777 cap_mode
= CS_MODE_THUMB
;
779 info
->print_insn
= print_insn_arm
;
780 info
->cap_insn_unit
= 4;
781 info
->cap_insn_split
= 4;
782 cap_mode
= CS_MODE_ARM
;
784 if (arm_feature(env
, ARM_FEATURE_V8
)) {
785 cap_mode
|= CS_MODE_V8
;
787 if (arm_feature(env
, ARM_FEATURE_M
)) {
788 cap_mode
|= CS_MODE_MCLASS
;
790 info
->cap_arch
= CS_ARCH_ARM
;
791 info
->cap_mode
= cap_mode
;
794 sctlr_b
= arm_sctlr_b(env
);
795 if (bswap_code(sctlr_b
)) {
796 #ifdef TARGET_WORDS_BIGENDIAN
797 info
->endian
= BFD_ENDIAN_LITTLE
;
799 info
->endian
= BFD_ENDIAN_BIG
;
802 info
->flags
&= ~INSN_ARM_BE32
;
803 #ifndef CONFIG_USER_ONLY
805 info
->flags
|= INSN_ARM_BE32
;
810 #ifdef TARGET_AARCH64
812 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
814 ARMCPU
*cpu
= ARM_CPU(cs
);
815 CPUARMState
*env
= &cpu
->env
;
816 uint32_t psr
= pstate_read(env
);
818 int el
= arm_current_el(env
);
819 const char *ns_status
;
821 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
822 for (i
= 0; i
< 32; i
++) {
824 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
826 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
827 (i
+ 2) % 3 ? " " : "\n");
831 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
832 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
836 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
838 psr
& PSTATE_N
? 'N' : '-',
839 psr
& PSTATE_Z
? 'Z' : '-',
840 psr
& PSTATE_C
? 'C' : '-',
841 psr
& PSTATE_V
? 'V' : '-',
844 psr
& PSTATE_SP
? 'h' : 't');
846 if (cpu_isar_feature(aa64_bti
, cpu
)) {
847 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
849 if (!(flags
& CPU_DUMP_FPU
)) {
850 qemu_fprintf(f
, "\n");
853 if (fp_exception_el(env
, el
) != 0) {
854 qemu_fprintf(f
, " FPU disabled\n");
857 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
858 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
860 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
861 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
863 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
865 if (i
== FFR_PRED_NUM
) {
866 qemu_fprintf(f
, "FFR=");
867 /* It's last, so end the line. */
870 qemu_fprintf(f
, "P%02d=", i
);
883 /* More than one quadword per predicate. */
888 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
890 if (j
* 4 + 4 <= zcr_len
+ 1) {
893 digits
= (zcr_len
% 4 + 1) * 4;
895 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
896 env
->vfp
.pregs
[i
].p
[j
],
897 j
? ":" : eol
? "\n" : " ");
901 for (i
= 0; i
< 32; i
++) {
903 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
904 i
, env
->vfp
.zregs
[i
].d
[1],
905 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
906 } else if (zcr_len
== 1) {
907 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
908 ":%016" PRIx64
":%016" PRIx64
"\n",
909 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
910 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
912 for (j
= zcr_len
; j
>= 0; j
--) {
913 bool odd
= (zcr_len
- j
) % 2 != 0;
915 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
918 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
920 qemu_fprintf(f
, " [%x]=", j
);
923 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
924 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
925 env
->vfp
.zregs
[i
].d
[j
* 2],
926 odd
|| j
== 0 ? "\n" : ":");
931 for (i
= 0; i
< 32; i
++) {
932 uint64_t *q
= aa64_vfp_qreg(env
, i
);
933 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
934 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
941 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
943 g_assert_not_reached();
948 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
950 ARMCPU
*cpu
= ARM_CPU(cs
);
951 CPUARMState
*env
= &cpu
->env
;
955 aarch64_cpu_dump_state(cs
, f
, flags
);
959 for (i
= 0; i
< 16; i
++) {
960 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
962 qemu_fprintf(f
, "\n");
964 qemu_fprintf(f
, " ");
968 if (arm_feature(env
, ARM_FEATURE_M
)) {
969 uint32_t xpsr
= xpsr_read(env
);
971 const char *ns_status
= "";
973 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
974 ns_status
= env
->v7m
.secure
? "S " : "NS ";
977 if (xpsr
& XPSR_EXCP
) {
980 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
981 mode
= "unpriv-thread";
983 mode
= "priv-thread";
987 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
989 xpsr
& XPSR_N
? 'N' : '-',
990 xpsr
& XPSR_Z
? 'Z' : '-',
991 xpsr
& XPSR_C
? 'C' : '-',
992 xpsr
& XPSR_V
? 'V' : '-',
993 xpsr
& XPSR_T
? 'T' : 'A',
997 uint32_t psr
= cpsr_read(env
);
998 const char *ns_status
= "";
1000 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1001 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1002 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1005 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1007 psr
& CPSR_N
? 'N' : '-',
1008 psr
& CPSR_Z
? 'Z' : '-',
1009 psr
& CPSR_C
? 'C' : '-',
1010 psr
& CPSR_V
? 'V' : '-',
1011 psr
& CPSR_T
? 'T' : 'A',
1013 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1016 if (flags
& CPU_DUMP_FPU
) {
1018 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1021 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1024 for (i
= 0; i
< numvfpregs
; i
++) {
1025 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1026 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1028 i
* 2 + 1, (uint32_t)(v
>> 32),
1031 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1035 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1037 uint32_t Aff1
= idx
/ clustersz
;
1038 uint32_t Aff0
= idx
% clustersz
;
1039 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1042 static void cpreg_hashtable_data_destroy(gpointer data
)
1045 * Destroy function for cpu->cp_regs hashtable data entries.
1046 * We must free the name string because it was g_strdup()ed in
1047 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1048 * from r->name because we know we definitely allocated it.
1050 ARMCPRegInfo
*r
= data
;
1052 g_free((void *)r
->name
);
1056 static void arm_cpu_initfn(Object
*obj
)
1058 ARMCPU
*cpu
= ARM_CPU(obj
);
1060 cpu_set_cpustate_pointers(cpu
);
1061 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1062 g_free
, cpreg_hashtable_data_destroy
);
1064 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1065 QLIST_INIT(&cpu
->el_change_hooks
);
1067 #ifndef CONFIG_USER_ONLY
1068 /* Our inbound IRQ and FIQ lines */
1069 if (kvm_enabled()) {
1070 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1071 * the same interface as non-KVM CPUs.
1073 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1075 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1078 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1079 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1081 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1082 "gicv3-maintenance-interrupt", 1);
1083 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1084 "pmu-interrupt", 1);
1087 /* DTB consumers generally don't in fact care what the 'compatible'
1088 * string is, so always provide some string and trust that a hypothetical
1089 * picky DTB consumer will also provide a helpful error message.
1091 cpu
->dtb_compatible
= "qemu,unknown";
1092 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1093 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1095 if (tcg_enabled()) {
1096 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1100 static Property arm_cpu_gt_cntfrq_property
=
1101 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1102 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1104 static Property arm_cpu_reset_cbar_property
=
1105 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1107 static Property arm_cpu_reset_hivecs_property
=
1108 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1110 static Property arm_cpu_rvbar_property
=
1111 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1113 static Property arm_cpu_has_el2_property
=
1114 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1116 static Property arm_cpu_has_el3_property
=
1117 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1119 static Property arm_cpu_cfgend_property
=
1120 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1122 static Property arm_cpu_has_vfp_property
=
1123 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1125 static Property arm_cpu_has_neon_property
=
1126 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1128 static Property arm_cpu_has_dsp_property
=
1129 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1131 static Property arm_cpu_has_mpu_property
=
1132 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1134 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1135 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1136 * the right value for that particular CPU type, and we don't want
1137 * to override that with an incorrect constant value.
1139 static Property arm_cpu_pmsav7_dregion_property
=
1140 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1142 qdev_prop_uint32
, uint32_t);
1144 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1146 ARMCPU
*cpu
= ARM_CPU(obj
);
1148 return cpu
->has_pmu
;
1151 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1153 ARMCPU
*cpu
= ARM_CPU(obj
);
1156 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu
))) {
1157 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1160 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1162 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1164 cpu
->has_pmu
= value
;
1167 static void arm_get_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1168 void *opaque
, Error
**errp
)
1170 ARMCPU
*cpu
= ARM_CPU(obj
);
1172 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1175 static void arm_set_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1176 void *opaque
, Error
**errp
)
1178 ARMCPU
*cpu
= ARM_CPU(obj
);
1180 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1183 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1186 * The exact approach to calculating guest ticks is:
1188 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1189 * NANOSECONDS_PER_SECOND);
1191 * We don't do that. Rather we intentionally use integer division
1192 * truncation below and in the caller for the conversion of host monotonic
1193 * time to guest ticks to provide the exact inverse for the semantics of
1194 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1195 * it loses precision when representing frequencies where
1196 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1197 * provide an exact inverse leads to scheduling timers with negative
1198 * periods, which in turn leads to sticky behaviour in the guest.
1200 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1201 * cannot become zero.
1203 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1204 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1207 void arm_cpu_post_init(Object
*obj
)
1209 ARMCPU
*cpu
= ARM_CPU(obj
);
1211 /* M profile implies PMSA. We have to do this here rather than
1212 * in realize with the other feature-implication checks because
1213 * we look at the PMSA bit to see if we should add some properties.
1215 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1216 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1218 /* Similarly for the VFP feature bits */
1219 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP4
)) {
1220 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1222 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP3
)) {
1223 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1226 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1227 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1228 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1231 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1232 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1235 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1236 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1239 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1240 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1241 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1243 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1245 #ifndef CONFIG_USER_ONLY
1246 object_property_add_link(obj
, "secure-memory",
1248 (Object
**)&cpu
->secure_memory
,
1249 qdev_prop_allow_set_link_before_realize
,
1250 OBJ_PROP_LINK_STRONG
,
1255 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1256 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1259 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1260 cpu
->has_pmu
= true;
1261 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
,
1266 * Allow user to turn off VFP and Neon support, but only for TCG --
1267 * KVM does not currently allow us to lie to the guest about its
1268 * ID/feature registers, so the guest always sees what the host has.
1270 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1271 cpu
->has_vfp
= true;
1272 if (!kvm_enabled()) {
1273 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1277 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1278 cpu
->has_neon
= true;
1279 if (!kvm_enabled()) {
1280 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1284 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1285 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1286 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1289 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1290 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1291 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1292 qdev_property_add_static(DEVICE(obj
),
1293 &arm_cpu_pmsav7_dregion_property
);
1297 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1298 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1299 qdev_prop_allow_set_link_before_realize
,
1300 OBJ_PROP_LINK_STRONG
,
1303 * M profile: initial value of the Secure VTOR. We can't just use
1304 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1305 * the property to be set after realize.
1307 object_property_add(obj
, "init-svtor", "uint32",
1308 arm_get_init_svtor
, arm_set_init_svtor
,
1309 NULL
, NULL
, &error_abort
);
1312 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1314 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1315 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1319 static void arm_cpu_finalizefn(Object
*obj
)
1321 ARMCPU
*cpu
= ARM_CPU(obj
);
1322 ARMELChangeHook
*hook
, *next
;
1324 g_hash_table_destroy(cpu
->cp_regs
);
1326 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1327 QLIST_REMOVE(hook
, node
);
1330 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1331 QLIST_REMOVE(hook
, node
);
1334 #ifndef CONFIG_USER_ONLY
1335 if (cpu
->pmu_timer
) {
1336 timer_del(cpu
->pmu_timer
);
1337 timer_deinit(cpu
->pmu_timer
);
1338 timer_free(cpu
->pmu_timer
);
1343 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1345 Error
*local_err
= NULL
;
1347 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1348 arm_cpu_sve_finalize(cpu
, &local_err
);
1349 if (local_err
!= NULL
) {
1350 error_propagate(errp
, local_err
);
1356 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1358 CPUState
*cs
= CPU(dev
);
1359 ARMCPU
*cpu
= ARM_CPU(dev
);
1360 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1361 CPUARMState
*env
= &cpu
->env
;
1363 Error
*local_err
= NULL
;
1364 bool no_aa32
= false;
1366 /* If we needed to query the host kernel for the CPU features
1367 * then it's possible that might have failed in the initfn, but
1368 * this is the first point where we can report it.
1370 if (cpu
->host_cpu_probe_failed
) {
1371 if (!kvm_enabled()) {
1372 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1374 error_setg(errp
, "Failed to retrieve host CPU features");
1379 #ifndef CONFIG_USER_ONLY
1380 /* The NVIC and M-profile CPU are two halves of a single piece of
1381 * hardware; trying to use one without the other is a command line
1382 * error and will result in segfaults if not caught here.
1384 if (arm_feature(env
, ARM_FEATURE_M
)) {
1386 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1391 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1399 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1400 if (!cpu
->gt_cntfrq_hz
) {
1401 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1405 scale
= gt_cntfrq_period_ns(cpu
);
1407 scale
= GTIMER_SCALE
;
1410 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1411 arm_gt_ptimer_cb
, cpu
);
1412 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1413 arm_gt_vtimer_cb
, cpu
);
1414 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1415 arm_gt_htimer_cb
, cpu
);
1416 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1417 arm_gt_stimer_cb
, cpu
);
1418 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1419 arm_gt_hvtimer_cb
, cpu
);
1423 cpu_exec_realizefn(cs
, &local_err
);
1424 if (local_err
!= NULL
) {
1425 error_propagate(errp
, local_err
);
1429 arm_cpu_finalize_features(cpu
, &local_err
);
1430 if (local_err
!= NULL
) {
1431 error_propagate(errp
, local_err
);
1435 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1436 cpu
->has_vfp
!= cpu
->has_neon
) {
1438 * This is an architectural requirement for AArch64; AArch32 is
1439 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1442 "AArch64 CPUs must have both VFP and Neon or neither");
1446 if (!cpu
->has_vfp
) {
1450 unset_feature(env
, ARM_FEATURE_VFP
);
1451 unset_feature(env
, ARM_FEATURE_VFP3
);
1452 unset_feature(env
, ARM_FEATURE_VFP4
);
1454 t
= cpu
->isar
.id_aa64isar1
;
1455 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1456 cpu
->isar
.id_aa64isar1
= t
;
1458 t
= cpu
->isar
.id_aa64pfr0
;
1459 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1460 cpu
->isar
.id_aa64pfr0
= t
;
1462 u
= cpu
->isar
.id_isar6
;
1463 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1464 cpu
->isar
.id_isar6
= u
;
1466 u
= cpu
->isar
.mvfr0
;
1467 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1468 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1469 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1470 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1471 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1472 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1473 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1474 cpu
->isar
.mvfr0
= u
;
1476 u
= cpu
->isar
.mvfr1
;
1477 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1478 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1479 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1480 cpu
->isar
.mvfr1
= u
;
1482 u
= cpu
->isar
.mvfr2
;
1483 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1484 cpu
->isar
.mvfr2
= u
;
1487 if (!cpu
->has_neon
) {
1491 unset_feature(env
, ARM_FEATURE_NEON
);
1493 t
= cpu
->isar
.id_aa64isar0
;
1494 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1495 cpu
->isar
.id_aa64isar0
= t
;
1497 t
= cpu
->isar
.id_aa64isar1
;
1498 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1499 cpu
->isar
.id_aa64isar1
= t
;
1501 t
= cpu
->isar
.id_aa64pfr0
;
1502 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1503 cpu
->isar
.id_aa64pfr0
= t
;
1505 u
= cpu
->isar
.id_isar5
;
1506 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1507 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1508 cpu
->isar
.id_isar5
= u
;
1510 u
= cpu
->isar
.id_isar6
;
1511 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1512 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1513 cpu
->isar
.id_isar6
= u
;
1515 u
= cpu
->isar
.mvfr1
;
1516 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1517 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1518 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1519 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1520 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1521 cpu
->isar
.mvfr1
= u
;
1523 u
= cpu
->isar
.mvfr2
;
1524 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1525 cpu
->isar
.mvfr2
= u
;
1528 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1532 t
= cpu
->isar
.id_aa64isar0
;
1533 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1534 cpu
->isar
.id_aa64isar0
= t
;
1536 t
= cpu
->isar
.id_aa64isar1
;
1537 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1538 cpu
->isar
.id_aa64isar1
= t
;
1540 u
= cpu
->isar
.mvfr0
;
1541 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1542 cpu
->isar
.mvfr0
= u
;
1545 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1548 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1550 u
= cpu
->isar
.id_isar1
;
1551 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1552 cpu
->isar
.id_isar1
= u
;
1554 u
= cpu
->isar
.id_isar2
;
1555 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1556 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1557 cpu
->isar
.id_isar2
= u
;
1559 u
= cpu
->isar
.id_isar3
;
1560 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1561 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1562 cpu
->isar
.id_isar3
= u
;
1565 /* Some features automatically imply others: */
1566 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1567 if (arm_feature(env
, ARM_FEATURE_M
)) {
1568 set_feature(env
, ARM_FEATURE_V7
);
1570 set_feature(env
, ARM_FEATURE_V7VE
);
1575 * There exist AArch64 cpus without AArch32 support. When KVM
1576 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1577 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1578 * As a general principle, we also do not make ID register
1579 * consistency checks anywhere unless using TCG, because only
1580 * for TCG would a consistency-check failure be a QEMU bug.
1582 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1583 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1586 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1587 /* v7 Virtualization Extensions. In real hardware this implies
1588 * EL2 and also the presence of the Security Extensions.
1589 * For QEMU, for backwards-compatibility we implement some
1590 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1591 * include the various other features that V7VE implies.
1592 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1593 * Security Extensions is ARM_FEATURE_EL3.
1595 assert(!tcg_enabled() || no_aa32
|| cpu_isar_feature(arm_div
, cpu
));
1596 set_feature(env
, ARM_FEATURE_LPAE
);
1597 set_feature(env
, ARM_FEATURE_V7
);
1599 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1600 set_feature(env
, ARM_FEATURE_VAPA
);
1601 set_feature(env
, ARM_FEATURE_THUMB2
);
1602 set_feature(env
, ARM_FEATURE_MPIDR
);
1603 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1604 set_feature(env
, ARM_FEATURE_V6K
);
1606 set_feature(env
, ARM_FEATURE_V6
);
1609 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1610 * non-EL3 configs. This is needed by some legacy boards.
1612 set_feature(env
, ARM_FEATURE_VBAR
);
1614 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1615 set_feature(env
, ARM_FEATURE_V6
);
1616 set_feature(env
, ARM_FEATURE_MVFR
);
1618 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1619 set_feature(env
, ARM_FEATURE_V5
);
1620 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1621 assert(!tcg_enabled() || no_aa32
|| cpu_isar_feature(jazelle
, cpu
));
1622 set_feature(env
, ARM_FEATURE_AUXCR
);
1625 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1626 set_feature(env
, ARM_FEATURE_V4T
);
1628 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1629 set_feature(env
, ARM_FEATURE_V7MP
);
1630 set_feature(env
, ARM_FEATURE_PXN
);
1632 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1633 set_feature(env
, ARM_FEATURE_CBAR
);
1635 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1636 !arm_feature(env
, ARM_FEATURE_M
)) {
1637 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1641 * We rely on no XScale CPU having VFP so we can use the same bits in the
1642 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1644 assert(!(arm_feature(env
, ARM_FEATURE_VFP
) &&
1645 arm_feature(env
, ARM_FEATURE_XSCALE
)));
1647 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1648 !arm_feature(env
, ARM_FEATURE_M
) &&
1649 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1650 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1655 /* For CPUs which might have tiny 1K pages, or which have an
1656 * MPU and might have small region sizes, stick with 1K pages.
1660 if (!set_preferred_target_page_bits(pagebits
)) {
1661 /* This can only ever happen for hotplugging a CPU, or if
1662 * the board code incorrectly creates a CPU which it has
1663 * promised via minimum_page_size that it will not.
1665 error_setg(errp
, "This CPU requires a smaller page size than the "
1670 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1671 * We don't support setting cluster ID ([16..23]) (known as Aff2
1672 * in later ARM ARM versions), or any of the higher affinity level fields,
1673 * so these bits always RAZ.
1675 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1676 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1677 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1680 if (cpu
->reset_hivecs
) {
1681 cpu
->reset_sctlr
|= (1 << 13);
1685 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1686 cpu
->reset_sctlr
|= SCTLR_EE
;
1688 cpu
->reset_sctlr
|= SCTLR_B
;
1692 if (!cpu
->has_el3
) {
1693 /* If the has_el3 CPU property is disabled then we need to disable the
1696 unset_feature(env
, ARM_FEATURE_EL3
);
1698 /* Disable the security extension feature bits in the processor feature
1699 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1701 cpu
->id_pfr1
&= ~0xf0;
1702 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1705 if (!cpu
->has_el2
) {
1706 unset_feature(env
, ARM_FEATURE_EL2
);
1709 if (!cpu
->has_pmu
) {
1710 unset_feature(env
, ARM_FEATURE_PMU
);
1712 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1715 if (!kvm_enabled()) {
1716 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1717 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1720 #ifndef CONFIG_USER_ONLY
1721 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1725 cpu
->id_aa64dfr0
&= ~0xf00;
1726 cpu
->id_dfr0
&= ~(0xf << 24);
1731 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1732 /* Disable the hypervisor feature bits in the processor feature
1733 * registers if we don't have EL2. These are id_pfr1[15:12] and
1734 * id_aa64pfr0_el1[11:8].
1736 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1737 cpu
->id_pfr1
&= ~0xf000;
1740 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1741 * to false or by setting pmsav7-dregion to 0.
1743 if (!cpu
->has_mpu
) {
1744 cpu
->pmsav7_dregion
= 0;
1746 if (cpu
->pmsav7_dregion
== 0) {
1747 cpu
->has_mpu
= false;
1750 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1751 arm_feature(env
, ARM_FEATURE_V7
)) {
1752 uint32_t nr
= cpu
->pmsav7_dregion
;
1755 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1760 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1762 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1763 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1764 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1765 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1766 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1769 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1770 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1771 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1776 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1777 uint32_t nr
= cpu
->sau_sregion
;
1780 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1785 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1786 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1790 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1791 set_feature(env
, ARM_FEATURE_VBAR
);
1794 register_cp_regs_for_features(cpu
);
1795 arm_cpu_register_gdb_regs_for_features(cpu
);
1797 init_cpreg_list(cpu
);
1799 #ifndef CONFIG_USER_ONLY
1800 MachineState
*ms
= MACHINE(qdev_get_machine());
1801 unsigned int smp_cpus
= ms
->smp
.cpus
;
1803 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1806 if (!cpu
->secure_memory
) {
1807 cpu
->secure_memory
= cs
->memory
;
1809 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1810 cpu
->secure_memory
);
1814 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1816 /* No core_count specified, default to smp_cpus. */
1817 if (cpu
->core_count
== -1) {
1818 cpu
->core_count
= smp_cpus
;
1825 acc
->parent_realize(dev
, errp
);
1828 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1833 const char *cpunamestr
;
1835 cpuname
= g_strsplit(cpu_model
, ",", 1);
1836 cpunamestr
= cpuname
[0];
1837 #ifdef CONFIG_USER_ONLY
1838 /* For backwards compatibility usermode emulation allows "-cpu any",
1839 * which has the same semantics as "-cpu max".
1841 if (!strcmp(cpunamestr
, "any")) {
1845 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1846 oc
= object_class_by_name(typename
);
1847 g_strfreev(cpuname
);
1849 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1850 object_class_is_abstract(oc
)) {
1856 /* CPU models. These are not needed for the AArch64 linux-user build. */
1857 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1859 static void arm926_initfn(Object
*obj
)
1861 ARMCPU
*cpu
= ARM_CPU(obj
);
1863 cpu
->dtb_compatible
= "arm,arm926";
1864 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1865 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1866 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1867 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1868 cpu
->midr
= 0x41069265;
1869 cpu
->reset_fpsid
= 0x41011090;
1870 cpu
->ctr
= 0x1dd20d2;
1871 cpu
->reset_sctlr
= 0x00090078;
1874 * ARMv5 does not have the ID_ISAR registers, but we can still
1875 * set the field to indicate Jazelle support within QEMU.
1877 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1879 * Similarly, we need to set MVFR0 fields to enable double precision
1880 * and short vector support even though ARMv5 doesn't have this register.
1882 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1883 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1886 static void arm946_initfn(Object
*obj
)
1888 ARMCPU
*cpu
= ARM_CPU(obj
);
1890 cpu
->dtb_compatible
= "arm,arm946";
1891 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1892 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1893 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1894 cpu
->midr
= 0x41059461;
1895 cpu
->ctr
= 0x0f004006;
1896 cpu
->reset_sctlr
= 0x00000078;
1899 static void arm1026_initfn(Object
*obj
)
1901 ARMCPU
*cpu
= ARM_CPU(obj
);
1903 cpu
->dtb_compatible
= "arm,arm1026";
1904 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1905 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1906 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1907 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1908 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1909 cpu
->midr
= 0x4106a262;
1910 cpu
->reset_fpsid
= 0x410110a0;
1911 cpu
->ctr
= 0x1dd20d2;
1912 cpu
->reset_sctlr
= 0x00090078;
1913 cpu
->reset_auxcr
= 1;
1916 * ARMv5 does not have the ID_ISAR registers, but we can still
1917 * set the field to indicate Jazelle support within QEMU.
1919 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1921 * Similarly, we need to set MVFR0 fields to enable double precision
1922 * and short vector support even though ARMv5 doesn't have this register.
1924 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1925 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1928 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1929 ARMCPRegInfo ifar
= {
1930 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1932 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1935 define_one_arm_cp_reg(cpu
, &ifar
);
1939 static void arm1136_r2_initfn(Object
*obj
)
1941 ARMCPU
*cpu
= ARM_CPU(obj
);
1942 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1943 * older core than plain "arm1136". In particular this does not
1944 * have the v6K features.
1945 * These ID register values are correct for 1136 but may be wrong
1946 * for 1136_r2 (in particular r0p2 does not actually implement most
1947 * of the ID registers).
1950 cpu
->dtb_compatible
= "arm,arm1136";
1951 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1952 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1953 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1954 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1955 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1956 cpu
->midr
= 0x4107b362;
1957 cpu
->reset_fpsid
= 0x410120b4;
1958 cpu
->isar
.mvfr0
= 0x11111111;
1959 cpu
->isar
.mvfr1
= 0x00000000;
1960 cpu
->ctr
= 0x1dd20d2;
1961 cpu
->reset_sctlr
= 0x00050078;
1962 cpu
->id_pfr0
= 0x111;
1966 cpu
->id_mmfr0
= 0x01130003;
1967 cpu
->id_mmfr1
= 0x10030302;
1968 cpu
->id_mmfr2
= 0x01222110;
1969 cpu
->isar
.id_isar0
= 0x00140011;
1970 cpu
->isar
.id_isar1
= 0x12002111;
1971 cpu
->isar
.id_isar2
= 0x11231111;
1972 cpu
->isar
.id_isar3
= 0x01102131;
1973 cpu
->isar
.id_isar4
= 0x141;
1974 cpu
->reset_auxcr
= 7;
1977 static void arm1136_initfn(Object
*obj
)
1979 ARMCPU
*cpu
= ARM_CPU(obj
);
1981 cpu
->dtb_compatible
= "arm,arm1136";
1982 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1983 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1984 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1985 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1986 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1987 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1988 cpu
->midr
= 0x4117b363;
1989 cpu
->reset_fpsid
= 0x410120b4;
1990 cpu
->isar
.mvfr0
= 0x11111111;
1991 cpu
->isar
.mvfr1
= 0x00000000;
1992 cpu
->ctr
= 0x1dd20d2;
1993 cpu
->reset_sctlr
= 0x00050078;
1994 cpu
->id_pfr0
= 0x111;
1998 cpu
->id_mmfr0
= 0x01130003;
1999 cpu
->id_mmfr1
= 0x10030302;
2000 cpu
->id_mmfr2
= 0x01222110;
2001 cpu
->isar
.id_isar0
= 0x00140011;
2002 cpu
->isar
.id_isar1
= 0x12002111;
2003 cpu
->isar
.id_isar2
= 0x11231111;
2004 cpu
->isar
.id_isar3
= 0x01102131;
2005 cpu
->isar
.id_isar4
= 0x141;
2006 cpu
->reset_auxcr
= 7;
2009 static void arm1176_initfn(Object
*obj
)
2011 ARMCPU
*cpu
= ARM_CPU(obj
);
2013 cpu
->dtb_compatible
= "arm,arm1176";
2014 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
2015 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
2016 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
2017 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2018 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
2019 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
2020 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2021 cpu
->midr
= 0x410fb767;
2022 cpu
->reset_fpsid
= 0x410120b5;
2023 cpu
->isar
.mvfr0
= 0x11111111;
2024 cpu
->isar
.mvfr1
= 0x00000000;
2025 cpu
->ctr
= 0x1dd20d2;
2026 cpu
->reset_sctlr
= 0x00050078;
2027 cpu
->id_pfr0
= 0x111;
2028 cpu
->id_pfr1
= 0x11;
2029 cpu
->id_dfr0
= 0x33;
2031 cpu
->id_mmfr0
= 0x01130003;
2032 cpu
->id_mmfr1
= 0x10030302;
2033 cpu
->id_mmfr2
= 0x01222100;
2034 cpu
->isar
.id_isar0
= 0x0140011;
2035 cpu
->isar
.id_isar1
= 0x12002111;
2036 cpu
->isar
.id_isar2
= 0x11231121;
2037 cpu
->isar
.id_isar3
= 0x01102131;
2038 cpu
->isar
.id_isar4
= 0x01141;
2039 cpu
->reset_auxcr
= 7;
2042 static void arm11mpcore_initfn(Object
*obj
)
2044 ARMCPU
*cpu
= ARM_CPU(obj
);
2046 cpu
->dtb_compatible
= "arm,arm11mpcore";
2047 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
2048 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
2049 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
2050 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
2051 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2052 cpu
->midr
= 0x410fb022;
2053 cpu
->reset_fpsid
= 0x410120b4;
2054 cpu
->isar
.mvfr0
= 0x11111111;
2055 cpu
->isar
.mvfr1
= 0x00000000;
2056 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
2057 cpu
->id_pfr0
= 0x111;
2061 cpu
->id_mmfr0
= 0x01100103;
2062 cpu
->id_mmfr1
= 0x10020302;
2063 cpu
->id_mmfr2
= 0x01222000;
2064 cpu
->isar
.id_isar0
= 0x00100011;
2065 cpu
->isar
.id_isar1
= 0x12002111;
2066 cpu
->isar
.id_isar2
= 0x11221011;
2067 cpu
->isar
.id_isar3
= 0x01102131;
2068 cpu
->isar
.id_isar4
= 0x141;
2069 cpu
->reset_auxcr
= 1;
2072 static void cortex_m0_initfn(Object
*obj
)
2074 ARMCPU
*cpu
= ARM_CPU(obj
);
2075 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
2076 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2078 cpu
->midr
= 0x410cc200;
2081 static void cortex_m3_initfn(Object
*obj
)
2083 ARMCPU
*cpu
= ARM_CPU(obj
);
2084 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2085 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2086 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2087 cpu
->midr
= 0x410fc231;
2088 cpu
->pmsav7_dregion
= 8;
2089 cpu
->id_pfr0
= 0x00000030;
2090 cpu
->id_pfr1
= 0x00000200;
2091 cpu
->id_dfr0
= 0x00100000;
2092 cpu
->id_afr0
= 0x00000000;
2093 cpu
->id_mmfr0
= 0x00000030;
2094 cpu
->id_mmfr1
= 0x00000000;
2095 cpu
->id_mmfr2
= 0x00000000;
2096 cpu
->id_mmfr3
= 0x00000000;
2097 cpu
->isar
.id_isar0
= 0x01141110;
2098 cpu
->isar
.id_isar1
= 0x02111000;
2099 cpu
->isar
.id_isar2
= 0x21112231;
2100 cpu
->isar
.id_isar3
= 0x01111110;
2101 cpu
->isar
.id_isar4
= 0x01310102;
2102 cpu
->isar
.id_isar5
= 0x00000000;
2103 cpu
->isar
.id_isar6
= 0x00000000;
2106 static void cortex_m4_initfn(Object
*obj
)
2108 ARMCPU
*cpu
= ARM_CPU(obj
);
2110 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2111 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2112 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2113 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2114 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2115 cpu
->midr
= 0x410fc240; /* r0p0 */
2116 cpu
->pmsav7_dregion
= 8;
2117 cpu
->isar
.mvfr0
= 0x10110021;
2118 cpu
->isar
.mvfr1
= 0x11000011;
2119 cpu
->isar
.mvfr2
= 0x00000000;
2120 cpu
->id_pfr0
= 0x00000030;
2121 cpu
->id_pfr1
= 0x00000200;
2122 cpu
->id_dfr0
= 0x00100000;
2123 cpu
->id_afr0
= 0x00000000;
2124 cpu
->id_mmfr0
= 0x00000030;
2125 cpu
->id_mmfr1
= 0x00000000;
2126 cpu
->id_mmfr2
= 0x00000000;
2127 cpu
->id_mmfr3
= 0x00000000;
2128 cpu
->isar
.id_isar0
= 0x01141110;
2129 cpu
->isar
.id_isar1
= 0x02111000;
2130 cpu
->isar
.id_isar2
= 0x21112231;
2131 cpu
->isar
.id_isar3
= 0x01111110;
2132 cpu
->isar
.id_isar4
= 0x01310102;
2133 cpu
->isar
.id_isar5
= 0x00000000;
2134 cpu
->isar
.id_isar6
= 0x00000000;
2137 static void cortex_m7_initfn(Object
*obj
)
2139 ARMCPU
*cpu
= ARM_CPU(obj
);
2141 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2142 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2143 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2144 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2145 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2146 cpu
->midr
= 0x411fc272; /* r1p2 */
2147 cpu
->pmsav7_dregion
= 8;
2148 cpu
->isar
.mvfr0
= 0x10110221;
2149 cpu
->isar
.mvfr1
= 0x12000011;
2150 cpu
->isar
.mvfr2
= 0x00000040;
2151 cpu
->id_pfr0
= 0x00000030;
2152 cpu
->id_pfr1
= 0x00000200;
2153 cpu
->id_dfr0
= 0x00100000;
2154 cpu
->id_afr0
= 0x00000000;
2155 cpu
->id_mmfr0
= 0x00100030;
2156 cpu
->id_mmfr1
= 0x00000000;
2157 cpu
->id_mmfr2
= 0x01000000;
2158 cpu
->id_mmfr3
= 0x00000000;
2159 cpu
->isar
.id_isar0
= 0x01101110;
2160 cpu
->isar
.id_isar1
= 0x02112000;
2161 cpu
->isar
.id_isar2
= 0x20232231;
2162 cpu
->isar
.id_isar3
= 0x01111131;
2163 cpu
->isar
.id_isar4
= 0x01310132;
2164 cpu
->isar
.id_isar5
= 0x00000000;
2165 cpu
->isar
.id_isar6
= 0x00000000;
2168 static void cortex_m33_initfn(Object
*obj
)
2170 ARMCPU
*cpu
= ARM_CPU(obj
);
2172 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2173 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2174 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2175 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
2176 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2177 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2178 cpu
->midr
= 0x410fd213; /* r0p3 */
2179 cpu
->pmsav7_dregion
= 16;
2180 cpu
->sau_sregion
= 8;
2181 cpu
->isar
.mvfr0
= 0x10110021;
2182 cpu
->isar
.mvfr1
= 0x11000011;
2183 cpu
->isar
.mvfr2
= 0x00000040;
2184 cpu
->id_pfr0
= 0x00000030;
2185 cpu
->id_pfr1
= 0x00000210;
2186 cpu
->id_dfr0
= 0x00200000;
2187 cpu
->id_afr0
= 0x00000000;
2188 cpu
->id_mmfr0
= 0x00101F40;
2189 cpu
->id_mmfr1
= 0x00000000;
2190 cpu
->id_mmfr2
= 0x01000000;
2191 cpu
->id_mmfr3
= 0x00000000;
2192 cpu
->isar
.id_isar0
= 0x01101110;
2193 cpu
->isar
.id_isar1
= 0x02212000;
2194 cpu
->isar
.id_isar2
= 0x20232232;
2195 cpu
->isar
.id_isar3
= 0x01111131;
2196 cpu
->isar
.id_isar4
= 0x01310132;
2197 cpu
->isar
.id_isar5
= 0x00000000;
2198 cpu
->isar
.id_isar6
= 0x00000000;
2199 cpu
->clidr
= 0x00000000;
2200 cpu
->ctr
= 0x8000c000;
2203 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
2205 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2206 CPUClass
*cc
= CPU_CLASS(oc
);
2209 #ifndef CONFIG_USER_ONLY
2210 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
2213 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
2216 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
2217 /* Dummy the TCM region regs for the moment */
2218 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2219 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2220 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2221 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2222 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
2223 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
2227 static void cortex_r5_initfn(Object
*obj
)
2229 ARMCPU
*cpu
= ARM_CPU(obj
);
2231 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2232 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2233 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
2234 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2235 cpu
->midr
= 0x411fc153; /* r1p3 */
2236 cpu
->id_pfr0
= 0x0131;
2237 cpu
->id_pfr1
= 0x001;
2238 cpu
->id_dfr0
= 0x010400;
2240 cpu
->id_mmfr0
= 0x0210030;
2241 cpu
->id_mmfr1
= 0x00000000;
2242 cpu
->id_mmfr2
= 0x01200000;
2243 cpu
->id_mmfr3
= 0x0211;
2244 cpu
->isar
.id_isar0
= 0x02101111;
2245 cpu
->isar
.id_isar1
= 0x13112111;
2246 cpu
->isar
.id_isar2
= 0x21232141;
2247 cpu
->isar
.id_isar3
= 0x01112131;
2248 cpu
->isar
.id_isar4
= 0x0010142;
2249 cpu
->isar
.id_isar5
= 0x0;
2250 cpu
->isar
.id_isar6
= 0x0;
2251 cpu
->mp_is_up
= true;
2252 cpu
->pmsav7_dregion
= 16;
2253 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
2256 static void cortex_r5f_initfn(Object
*obj
)
2258 ARMCPU
*cpu
= ARM_CPU(obj
);
2260 cortex_r5_initfn(obj
);
2261 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2262 cpu
->isar
.mvfr0
= 0x10110221;
2263 cpu
->isar
.mvfr1
= 0x00000011;
2266 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
2267 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
2268 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2269 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2270 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2274 static void cortex_a8_initfn(Object
*obj
)
2276 ARMCPU
*cpu
= ARM_CPU(obj
);
2278 cpu
->dtb_compatible
= "arm,cortex-a8";
2279 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2280 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2281 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2282 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2283 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2284 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2285 cpu
->midr
= 0x410fc080;
2286 cpu
->reset_fpsid
= 0x410330c0;
2287 cpu
->isar
.mvfr0
= 0x11110222;
2288 cpu
->isar
.mvfr1
= 0x00011111;
2289 cpu
->ctr
= 0x82048004;
2290 cpu
->reset_sctlr
= 0x00c50078;
2291 cpu
->id_pfr0
= 0x1031;
2292 cpu
->id_pfr1
= 0x11;
2293 cpu
->id_dfr0
= 0x400;
2295 cpu
->id_mmfr0
= 0x31100003;
2296 cpu
->id_mmfr1
= 0x20000000;
2297 cpu
->id_mmfr2
= 0x01202000;
2298 cpu
->id_mmfr3
= 0x11;
2299 cpu
->isar
.id_isar0
= 0x00101111;
2300 cpu
->isar
.id_isar1
= 0x12112111;
2301 cpu
->isar
.id_isar2
= 0x21232031;
2302 cpu
->isar
.id_isar3
= 0x11112131;
2303 cpu
->isar
.id_isar4
= 0x00111142;
2304 cpu
->dbgdidr
= 0x15141000;
2305 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
2306 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
2307 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
2308 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
2309 cpu
->reset_auxcr
= 2;
2310 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
2313 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
2314 /* power_control should be set to maximum latency. Again,
2315 * default to 0 and set by private hook
2317 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2318 .access
= PL1_RW
, .resetvalue
= 0,
2319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
2320 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
2321 .access
= PL1_RW
, .resetvalue
= 0,
2322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
2323 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
2324 .access
= PL1_RW
, .resetvalue
= 0,
2325 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
2326 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2327 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2328 /* TLB lockdown control */
2329 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
2330 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2331 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
2332 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2333 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
2334 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2335 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
2336 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2337 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
2338 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2342 static void cortex_a9_initfn(Object
*obj
)
2344 ARMCPU
*cpu
= ARM_CPU(obj
);
2346 cpu
->dtb_compatible
= "arm,cortex-a9";
2347 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2348 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2349 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2350 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2351 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2352 /* Note that A9 supports the MP extensions even for
2353 * A9UP and single-core A9MP (which are both different
2354 * and valid configurations; we don't model A9UP).
2356 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2357 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
2358 cpu
->midr
= 0x410fc090;
2359 cpu
->reset_fpsid
= 0x41033090;
2360 cpu
->isar
.mvfr0
= 0x11110222;
2361 cpu
->isar
.mvfr1
= 0x01111111;
2362 cpu
->ctr
= 0x80038003;
2363 cpu
->reset_sctlr
= 0x00c50078;
2364 cpu
->id_pfr0
= 0x1031;
2365 cpu
->id_pfr1
= 0x11;
2366 cpu
->id_dfr0
= 0x000;
2368 cpu
->id_mmfr0
= 0x00100103;
2369 cpu
->id_mmfr1
= 0x20000000;
2370 cpu
->id_mmfr2
= 0x01230000;
2371 cpu
->id_mmfr3
= 0x00002111;
2372 cpu
->isar
.id_isar0
= 0x00101111;
2373 cpu
->isar
.id_isar1
= 0x13112111;
2374 cpu
->isar
.id_isar2
= 0x21232041;
2375 cpu
->isar
.id_isar3
= 0x11112131;
2376 cpu
->isar
.id_isar4
= 0x00111142;
2377 cpu
->dbgdidr
= 0x35141000;
2378 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
2379 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
2380 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
2381 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
2384 #ifndef CONFIG_USER_ONLY
2385 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2387 MachineState
*ms
= MACHINE(qdev_get_machine());
2389 /* Linux wants the number of processors from here.
2390 * Might as well set the interrupt-controller bit too.
2392 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2396 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2397 #ifndef CONFIG_USER_ONLY
2398 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2399 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2400 .writefn
= arm_cp_write_ignore
, },
2402 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2403 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2407 static void cortex_a7_initfn(Object
*obj
)
2409 ARMCPU
*cpu
= ARM_CPU(obj
);
2411 cpu
->dtb_compatible
= "arm,cortex-a7";
2412 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2413 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2414 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2415 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2416 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2417 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2418 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2419 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2420 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2421 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2422 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2423 cpu
->midr
= 0x410fc075;
2424 cpu
->reset_fpsid
= 0x41023075;
2425 cpu
->isar
.mvfr0
= 0x10110222;
2426 cpu
->isar
.mvfr1
= 0x11111111;
2427 cpu
->ctr
= 0x84448003;
2428 cpu
->reset_sctlr
= 0x00c50078;
2429 cpu
->id_pfr0
= 0x00001131;
2430 cpu
->id_pfr1
= 0x00011011;
2431 cpu
->id_dfr0
= 0x02010555;
2432 cpu
->id_afr0
= 0x00000000;
2433 cpu
->id_mmfr0
= 0x10101105;
2434 cpu
->id_mmfr1
= 0x40000000;
2435 cpu
->id_mmfr2
= 0x01240000;
2436 cpu
->id_mmfr3
= 0x02102211;
2437 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2438 * table 4-41 gives 0x02101110, which includes the arm div insns.
2440 cpu
->isar
.id_isar0
= 0x02101110;
2441 cpu
->isar
.id_isar1
= 0x13112111;
2442 cpu
->isar
.id_isar2
= 0x21232041;
2443 cpu
->isar
.id_isar3
= 0x11112131;
2444 cpu
->isar
.id_isar4
= 0x10011142;
2445 cpu
->dbgdidr
= 0x3515f005;
2446 cpu
->clidr
= 0x0a200023;
2447 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2448 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2449 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2450 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2453 static void cortex_a15_initfn(Object
*obj
)
2455 ARMCPU
*cpu
= ARM_CPU(obj
);
2457 cpu
->dtb_compatible
= "arm,cortex-a15";
2458 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2459 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2460 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2461 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2462 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2463 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2464 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2465 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2466 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2467 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2468 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2469 cpu
->midr
= 0x412fc0f1;
2470 cpu
->reset_fpsid
= 0x410430f0;
2471 cpu
->isar
.mvfr0
= 0x10110222;
2472 cpu
->isar
.mvfr1
= 0x11111111;
2473 cpu
->ctr
= 0x8444c004;
2474 cpu
->reset_sctlr
= 0x00c50078;
2475 cpu
->id_pfr0
= 0x00001131;
2476 cpu
->id_pfr1
= 0x00011011;
2477 cpu
->id_dfr0
= 0x02010555;
2478 cpu
->id_afr0
= 0x00000000;
2479 cpu
->id_mmfr0
= 0x10201105;
2480 cpu
->id_mmfr1
= 0x20000000;
2481 cpu
->id_mmfr2
= 0x01240000;
2482 cpu
->id_mmfr3
= 0x02102211;
2483 cpu
->isar
.id_isar0
= 0x02101110;
2484 cpu
->isar
.id_isar1
= 0x13112111;
2485 cpu
->isar
.id_isar2
= 0x21232041;
2486 cpu
->isar
.id_isar3
= 0x11112131;
2487 cpu
->isar
.id_isar4
= 0x10011142;
2488 cpu
->dbgdidr
= 0x3515f021;
2489 cpu
->clidr
= 0x0a200023;
2490 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2491 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2492 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2493 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2496 static void ti925t_initfn(Object
*obj
)
2498 ARMCPU
*cpu
= ARM_CPU(obj
);
2499 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
2500 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
2501 cpu
->midr
= ARM_CPUID_TI925T
;
2502 cpu
->ctr
= 0x5109149;
2503 cpu
->reset_sctlr
= 0x00000070;
2506 static void sa1100_initfn(Object
*obj
)
2508 ARMCPU
*cpu
= ARM_CPU(obj
);
2510 cpu
->dtb_compatible
= "intel,sa1100";
2511 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2512 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2513 cpu
->midr
= 0x4401A11B;
2514 cpu
->reset_sctlr
= 0x00000070;
2517 static void sa1110_initfn(Object
*obj
)
2519 ARMCPU
*cpu
= ARM_CPU(obj
);
2520 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2521 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2522 cpu
->midr
= 0x6901B119;
2523 cpu
->reset_sctlr
= 0x00000070;
2526 static void pxa250_initfn(Object
*obj
)
2528 ARMCPU
*cpu
= ARM_CPU(obj
);
2530 cpu
->dtb_compatible
= "marvell,xscale";
2531 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2532 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2533 cpu
->midr
= 0x69052100;
2534 cpu
->ctr
= 0xd172172;
2535 cpu
->reset_sctlr
= 0x00000078;
2538 static void pxa255_initfn(Object
*obj
)
2540 ARMCPU
*cpu
= ARM_CPU(obj
);
2542 cpu
->dtb_compatible
= "marvell,xscale";
2543 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2544 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2545 cpu
->midr
= 0x69052d00;
2546 cpu
->ctr
= 0xd172172;
2547 cpu
->reset_sctlr
= 0x00000078;
2550 static void pxa260_initfn(Object
*obj
)
2552 ARMCPU
*cpu
= ARM_CPU(obj
);
2554 cpu
->dtb_compatible
= "marvell,xscale";
2555 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2556 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2557 cpu
->midr
= 0x69052903;
2558 cpu
->ctr
= 0xd172172;
2559 cpu
->reset_sctlr
= 0x00000078;
2562 static void pxa261_initfn(Object
*obj
)
2564 ARMCPU
*cpu
= ARM_CPU(obj
);
2566 cpu
->dtb_compatible
= "marvell,xscale";
2567 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2568 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2569 cpu
->midr
= 0x69052d05;
2570 cpu
->ctr
= 0xd172172;
2571 cpu
->reset_sctlr
= 0x00000078;
2574 static void pxa262_initfn(Object
*obj
)
2576 ARMCPU
*cpu
= ARM_CPU(obj
);
2578 cpu
->dtb_compatible
= "marvell,xscale";
2579 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2580 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2581 cpu
->midr
= 0x69052d06;
2582 cpu
->ctr
= 0xd172172;
2583 cpu
->reset_sctlr
= 0x00000078;
2586 static void pxa270a0_initfn(Object
*obj
)
2588 ARMCPU
*cpu
= ARM_CPU(obj
);
2590 cpu
->dtb_compatible
= "marvell,xscale";
2591 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2592 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2593 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2594 cpu
->midr
= 0x69054110;
2595 cpu
->ctr
= 0xd172172;
2596 cpu
->reset_sctlr
= 0x00000078;
2599 static void pxa270a1_initfn(Object
*obj
)
2601 ARMCPU
*cpu
= ARM_CPU(obj
);
2603 cpu
->dtb_compatible
= "marvell,xscale";
2604 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2605 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2606 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2607 cpu
->midr
= 0x69054111;
2608 cpu
->ctr
= 0xd172172;
2609 cpu
->reset_sctlr
= 0x00000078;
2612 static void pxa270b0_initfn(Object
*obj
)
2614 ARMCPU
*cpu
= ARM_CPU(obj
);
2616 cpu
->dtb_compatible
= "marvell,xscale";
2617 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2618 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2619 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2620 cpu
->midr
= 0x69054112;
2621 cpu
->ctr
= 0xd172172;
2622 cpu
->reset_sctlr
= 0x00000078;
2625 static void pxa270b1_initfn(Object
*obj
)
2627 ARMCPU
*cpu
= ARM_CPU(obj
);
2629 cpu
->dtb_compatible
= "marvell,xscale";
2630 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2631 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2632 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2633 cpu
->midr
= 0x69054113;
2634 cpu
->ctr
= 0xd172172;
2635 cpu
->reset_sctlr
= 0x00000078;
2638 static void pxa270c0_initfn(Object
*obj
)
2640 ARMCPU
*cpu
= ARM_CPU(obj
);
2642 cpu
->dtb_compatible
= "marvell,xscale";
2643 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2644 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2645 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2646 cpu
->midr
= 0x69054114;
2647 cpu
->ctr
= 0xd172172;
2648 cpu
->reset_sctlr
= 0x00000078;
2651 static void pxa270c5_initfn(Object
*obj
)
2653 ARMCPU
*cpu
= ARM_CPU(obj
);
2655 cpu
->dtb_compatible
= "marvell,xscale";
2656 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2657 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2658 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2659 cpu
->midr
= 0x69054117;
2660 cpu
->ctr
= 0xd172172;
2661 cpu
->reset_sctlr
= 0x00000078;
2664 #ifndef TARGET_AARCH64
2665 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2666 * otherwise, a CPU with as many features enabled as our emulation supports.
2667 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2668 * this only needs to handle 32 bits.
2670 static void arm_max_initfn(Object
*obj
)
2672 ARMCPU
*cpu
= ARM_CPU(obj
);
2674 if (kvm_enabled()) {
2675 kvm_arm_set_cpu_features_from_host(cpu
);
2676 kvm_arm_add_vcpu_properties(obj
);
2678 cortex_a15_initfn(obj
);
2680 /* old-style VFP short-vector support */
2681 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2683 #ifdef CONFIG_USER_ONLY
2684 /* We don't set these in system emulation mode for the moment,
2685 * since we don't correctly set (all of) the ID registers to
2688 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2692 t
= cpu
->isar
.id_isar5
;
2693 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2694 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2695 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2696 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2697 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2698 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2699 cpu
->isar
.id_isar5
= t
;
2701 t
= cpu
->isar
.id_isar6
;
2702 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2703 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2704 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2705 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2706 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2707 cpu
->isar
.id_isar6
= t
;
2709 t
= cpu
->isar
.mvfr1
;
2710 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 2); /* v8.0 FP support */
2711 cpu
->isar
.mvfr1
= t
;
2713 t
= cpu
->isar
.mvfr2
;
2714 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2715 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2716 cpu
->isar
.mvfr2
= t
;
2719 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2727 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2731 void (*initfn
)(Object
*obj
);
2732 void (*class_init
)(ObjectClass
*oc
, void *data
);
2735 static const ARMCPUInfo arm_cpus
[] = {
2736 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2737 { .name
= "arm926", .initfn
= arm926_initfn
},
2738 { .name
= "arm946", .initfn
= arm946_initfn
},
2739 { .name
= "arm1026", .initfn
= arm1026_initfn
},
2740 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2741 * older core than plain "arm1136". In particular this does not
2742 * have the v6K features.
2744 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
2745 { .name
= "arm1136", .initfn
= arm1136_initfn
},
2746 { .name
= "arm1176", .initfn
= arm1176_initfn
},
2747 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
2748 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
2749 .class_init
= arm_v7m_class_init
},
2750 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
2751 .class_init
= arm_v7m_class_init
},
2752 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
2753 .class_init
= arm_v7m_class_init
},
2754 { .name
= "cortex-m7", .initfn
= cortex_m7_initfn
,
2755 .class_init
= arm_v7m_class_init
},
2756 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2757 .class_init
= arm_v7m_class_init
},
2758 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2759 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2760 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2761 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2762 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2763 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2764 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2765 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2766 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2767 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2768 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2769 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2770 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2771 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2772 /* "pxa270" is an alias for "pxa270-a0" */
2773 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2774 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2775 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2776 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2777 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2778 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2779 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2780 #ifndef TARGET_AARCH64
2781 { .name
= "max", .initfn
= arm_max_initfn
},
2783 #ifdef CONFIG_USER_ONLY
2784 { .name
= "any", .initfn
= arm_max_initfn
},
2790 static Property arm_cpu_properties
[] = {
2791 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2792 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2793 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2794 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2795 mp_affinity
, ARM64_AFFINITY_INVALID
),
2796 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2797 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2798 DEFINE_PROP_END_OF_LIST()
2801 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2803 ARMCPU
*cpu
= ARM_CPU(cs
);
2804 CPUARMState
*env
= &cpu
->env
;
2806 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2807 return g_strdup("iwmmxt");
2809 return g_strdup("arm");
2812 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2814 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2815 CPUClass
*cc
= CPU_CLASS(acc
);
2816 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2818 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2819 &acc
->parent_realize
);
2821 device_class_set_props(dc
, arm_cpu_properties
);
2822 cpu_class_set_parent_reset(cc
, arm_cpu_reset
, &acc
->parent_reset
);
2824 cc
->class_by_name
= arm_cpu_class_by_name
;
2825 cc
->has_work
= arm_cpu_has_work
;
2826 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2827 cc
->dump_state
= arm_cpu_dump_state
;
2828 cc
->set_pc
= arm_cpu_set_pc
;
2829 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2830 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2831 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2832 #ifndef CONFIG_USER_ONLY
2833 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2834 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2835 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2836 cc
->vmsd
= &vmstate_arm_cpu
;
2837 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2838 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2839 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2841 cc
->gdb_num_core_regs
= 26;
2842 cc
->gdb_core_xml_file
= "arm-core.xml";
2843 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2844 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2845 cc
->gdb_stop_before_watchpoint
= true;
2846 cc
->disas_set_info
= arm_disas_set_info
;
2848 cc
->tcg_initialize
= arm_translate_init
;
2849 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2850 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2851 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2852 #if !defined(CONFIG_USER_ONLY)
2853 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2854 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2855 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2856 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2861 static void arm_host_initfn(Object
*obj
)
2863 ARMCPU
*cpu
= ARM_CPU(obj
);
2865 kvm_arm_set_cpu_features_from_host(cpu
);
2866 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2867 aarch64_add_sve_properties(obj
);
2869 kvm_arm_add_vcpu_properties(obj
);
2870 arm_cpu_post_init(obj
);
2873 static const TypeInfo host_arm_cpu_type_info
= {
2874 .name
= TYPE_ARM_HOST_CPU
,
2875 #ifdef TARGET_AARCH64
2876 .parent
= TYPE_AARCH64_CPU
,
2878 .parent
= TYPE_ARM_CPU
,
2880 .instance_init
= arm_host_initfn
,
2885 static void arm_cpu_instance_init(Object
*obj
)
2887 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2889 acc
->info
->initfn(obj
);
2890 arm_cpu_post_init(obj
);
2893 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2895 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2900 static void cpu_register(const ARMCPUInfo
*info
)
2902 TypeInfo type_info
= {
2903 .parent
= TYPE_ARM_CPU
,
2904 .instance_size
= sizeof(ARMCPU
),
2905 .instance_init
= arm_cpu_instance_init
,
2906 .class_size
= sizeof(ARMCPUClass
),
2907 .class_init
= info
->class_init
?: cpu_register_class_init
,
2908 .class_data
= (void *)info
,
2911 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2912 type_register(&type_info
);
2913 g_free((void *)type_info
.name
);
2916 static const TypeInfo arm_cpu_type_info
= {
2917 .name
= TYPE_ARM_CPU
,
2919 .instance_size
= sizeof(ARMCPU
),
2920 .instance_init
= arm_cpu_initfn
,
2921 .instance_finalize
= arm_cpu_finalizefn
,
2923 .class_size
= sizeof(ARMCPUClass
),
2924 .class_init
= arm_cpu_class_init
,
2927 static const TypeInfo idau_interface_type_info
= {
2928 .name
= TYPE_IDAU_INTERFACE
,
2929 .parent
= TYPE_INTERFACE
,
2930 .class_size
= sizeof(IDAUInterfaceClass
),
2933 static void arm_cpu_register_types(void)
2935 const ARMCPUInfo
*info
= arm_cpus
;
2937 type_register_static(&arm_cpu_type_info
);
2938 type_register_static(&idau_interface_type_info
);
2940 while (info
->name
) {
2946 type_register_static(&host_arm_cpu_type_info
);
2950 type_init(arm_cpu_register_types
)