4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "target/arm/idau.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
26 #include "internals.h"
27 #include "qemu-common.h"
28 #include "exec/exec-all.h"
29 #include "hw/qdev-properties.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/loader.h"
33 #include "hw/arm/arm.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/hw_accel.h"
37 #include "disas/capstone.h"
38 #include "fpu/softfloat.h"
40 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
42 ARMCPU
*cpu
= ARM_CPU(cs
);
44 cpu
->env
.regs
[15] = value
;
47 static bool arm_cpu_has_work(CPUState
*cs
)
49 ARMCPU
*cpu
= ARM_CPU(cs
);
51 return (cpu
->power_state
!= PSCI_OFF
)
52 && cs
->interrupt_request
&
53 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
54 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
55 | CPU_INTERRUPT_EXITTB
);
58 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
61 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
64 entry
->opaque
= opaque
;
66 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
69 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
72 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
75 entry
->opaque
= opaque
;
77 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
80 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
82 /* Reset a single ARMCPRegInfo register */
83 ARMCPRegInfo
*ri
= value
;
86 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
91 ri
->resetfn(&cpu
->env
, ri
);
95 /* A zero offset is never possible as it would be regs[0]
96 * so we use it to indicate that reset is being handled elsewhere.
97 * This is basically only used for fields in non-core coprocessors
98 * (like the pxa2xx ones).
100 if (!ri
->fieldoffset
) {
104 if (cpreg_field_is_64bit(ri
)) {
105 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
107 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
111 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
113 /* Purely an assertion check: we've already done reset once,
114 * so now check that running the reset for the cpreg doesn't
115 * change its value. This traps bugs where two different cpregs
116 * both try to reset the same state field but to different values.
118 ARMCPRegInfo
*ri
= value
;
119 ARMCPU
*cpu
= opaque
;
120 uint64_t oldvalue
, newvalue
;
122 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
126 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
127 cp_reg_reset(key
, value
, opaque
);
128 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
129 assert(oldvalue
== newvalue
);
132 /* CPUClass::reset() */
133 static void arm_cpu_reset(CPUState
*s
)
135 ARMCPU
*cpu
= ARM_CPU(s
);
136 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
137 CPUARMState
*env
= &cpu
->env
;
139 acc
->parent_reset(s
);
141 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
143 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
144 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
146 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
147 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
148 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
149 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
151 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
152 s
->halted
= cpu
->start_powered_off
;
154 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
155 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
158 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
159 /* 64 bit CPUs always start in 64 bit mode */
161 #if defined(CONFIG_USER_ONLY)
162 env
->pstate
= PSTATE_MODE_EL0t
;
163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
164 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
165 /* and to the FP/Neon instructions */
166 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
168 /* Reset into the highest available EL */
169 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
170 env
->pstate
= PSTATE_MODE_EL3h
;
171 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
172 env
->pstate
= PSTATE_MODE_EL2h
;
174 env
->pstate
= PSTATE_MODE_EL1h
;
176 env
->pc
= cpu
->rvbar
;
179 #if defined(CONFIG_USER_ONLY)
180 /* Userspace expects access to cp10 and cp11 for FP/Neon */
181 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
185 #if defined(CONFIG_USER_ONLY)
186 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
187 /* For user mode we must enable access to coprocessors */
188 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
189 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
190 env
->cp15
.c15_cpar
= 3;
191 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
192 env
->cp15
.c15_cpar
= 1;
195 /* SVC mode with interrupts disabled. */
196 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
197 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
199 if (arm_feature(env
, ARM_FEATURE_M
)) {
200 uint32_t initial_msp
; /* Loaded from 0x0 */
201 uint32_t initial_pc
; /* Loaded from 0x4 */
205 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
206 env
->v7m
.secure
= true;
208 /* This bit resets to 0 if security is supported, but 1 if
209 * it is not. The bit is not present in v7M, but we set it
210 * here so we can avoid having to make checks on it conditional
211 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
213 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
216 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
217 * that it resets to 1, so QEMU always does that rather than making
218 * it dependent on CPU model. In v8M it is RES1.
220 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
221 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
222 if (arm_feature(env
, ARM_FEATURE_V8
)) {
223 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
224 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
225 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
228 /* Unlike A/R profile, M profile defines the reset LR value */
229 env
->regs
[14] = 0xffffffff;
231 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
233 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
234 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
235 rom
= rom_ptr(vecbase
);
237 /* Address zero is covered by ROM which hasn't yet been
238 * copied into physical memory.
240 initial_msp
= ldl_p(rom
);
241 initial_pc
= ldl_p(rom
+ 4);
243 /* Address zero not covered by a ROM blob, or the ROM blob
244 * is in non-modifiable memory and this is a second reset after
245 * it got copied into memory. In the latter case, rom_ptr
246 * will return a NULL pointer and we should use ldl_phys instead.
248 initial_msp
= ldl_phys(s
->as
, vecbase
);
249 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
252 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
253 env
->regs
[15] = initial_pc
& ~1;
254 env
->thumb
= initial_pc
& 1;
257 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
258 * executing as AArch32 then check if highvecs are enabled and
259 * adjust the PC accordingly.
261 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
262 env
->regs
[15] = 0xFFFF0000;
265 /* M profile requires that reset clears the exclusive monitor;
266 * A profile does not, but clearing it makes more sense than having it
267 * set with an exclusive access on address zero.
269 arm_clear_exclusive(env
);
271 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
274 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
275 if (cpu
->pmsav7_dregion
> 0) {
276 if (arm_feature(env
, ARM_FEATURE_V8
)) {
277 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
278 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
279 * cpu
->pmsav7_dregion
);
280 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
281 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
282 * cpu
->pmsav7_dregion
);
283 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
284 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
285 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
286 * cpu
->pmsav7_dregion
);
287 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
288 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
289 * cpu
->pmsav7_dregion
);
291 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
292 memset(env
->pmsav7
.drbar
, 0,
293 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
294 memset(env
->pmsav7
.drsr
, 0,
295 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
296 memset(env
->pmsav7
.dracr
, 0,
297 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
300 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
301 env
->pmsav7
.rnr
[M_REG_S
] = 0;
302 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
303 env
->pmsav8
.mair0
[M_REG_S
] = 0;
304 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
305 env
->pmsav8
.mair1
[M_REG_S
] = 0;
308 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
309 if (cpu
->sau_sregion
> 0) {
310 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
311 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
314 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
315 * the Cortex-M33 does.
320 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
321 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
322 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
323 set_float_detect_tininess(float_tininess_before_rounding
,
324 &env
->vfp
.fp_status
);
325 set_float_detect_tininess(float_tininess_before_rounding
,
326 &env
->vfp
.standard_fp_status
);
327 set_float_detect_tininess(float_tininess_before_rounding
,
328 &env
->vfp
.fp_status_f16
);
329 #ifndef CONFIG_USER_ONLY
331 kvm_arm_reset_vcpu(cpu
);
335 hw_breakpoint_update_all(cpu
);
336 hw_watchpoint_update_all(cpu
);
339 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
341 CPUClass
*cc
= CPU_GET_CLASS(cs
);
342 CPUARMState
*env
= cs
->env_ptr
;
343 uint32_t cur_el
= arm_current_el(env
);
344 bool secure
= arm_is_secure(env
);
349 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
351 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
352 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
353 cs
->exception_index
= excp_idx
;
354 env
->exception
.target_el
= target_el
;
355 cc
->do_interrupt(cs
);
359 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
361 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
362 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
363 cs
->exception_index
= excp_idx
;
364 env
->exception
.target_el
= target_el
;
365 cc
->do_interrupt(cs
);
369 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
370 excp_idx
= EXCP_VIRQ
;
372 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
373 cs
->exception_index
= excp_idx
;
374 env
->exception
.target_el
= target_el
;
375 cc
->do_interrupt(cs
);
379 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
380 excp_idx
= EXCP_VFIQ
;
382 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
383 cs
->exception_index
= excp_idx
;
384 env
->exception
.target_el
= target_el
;
385 cc
->do_interrupt(cs
);
393 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
394 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
396 CPUClass
*cc
= CPU_GET_CLASS(cs
);
397 ARMCPU
*cpu
= ARM_CPU(cs
);
398 CPUARMState
*env
= &cpu
->env
;
401 /* ARMv7-M interrupt masking works differently than -A or -R.
402 * There is no FIQ/IRQ distinction. Instead of I and F bits
403 * masking FIQ and IRQ interrupts, an exception is taken only
404 * if it is higher priority than the current execution priority
405 * (which depends on state like BASEPRI, FAULTMASK and the
406 * currently active exception).
408 if (interrupt_request
& CPU_INTERRUPT_HARD
409 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
410 cs
->exception_index
= EXCP_IRQ
;
411 cc
->do_interrupt(cs
);
418 #ifndef CONFIG_USER_ONLY
419 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
421 ARMCPU
*cpu
= opaque
;
422 CPUARMState
*env
= &cpu
->env
;
423 CPUState
*cs
= CPU(cpu
);
424 static const int mask
[] = {
425 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
426 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
427 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
428 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
434 assert(arm_feature(env
, ARM_FEATURE_EL2
));
439 cpu_interrupt(cs
, mask
[irq
]);
441 cpu_reset_interrupt(cs
, mask
[irq
]);
445 g_assert_not_reached();
449 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
452 ARMCPU
*cpu
= opaque
;
453 CPUState
*cs
= CPU(cpu
);
454 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
458 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
461 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
464 g_assert_not_reached();
466 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
467 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
471 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
473 ARMCPU
*cpu
= ARM_CPU(cs
);
474 CPUARMState
*env
= &cpu
->env
;
476 cpu_synchronize_state(cs
);
477 return arm_cpu_data_is_big_endian(env
);
482 static inline void set_feature(CPUARMState
*env
, int feature
)
484 env
->features
|= 1ULL << feature
;
487 static inline void unset_feature(CPUARMState
*env
, int feature
)
489 env
->features
&= ~(1ULL << feature
);
493 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
495 return print_insn_arm(pc
| 1, info
);
498 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
500 ARMCPU
*ac
= ARM_CPU(cpu
);
501 CPUARMState
*env
= &ac
->env
;
505 /* We might not be compiled with the A64 disassembler
506 * because it needs a C++ compiler. Leave print_insn
507 * unset in this case to use the caller default behaviour.
509 #if defined(CONFIG_ARM_A64_DIS)
510 info
->print_insn
= print_insn_arm_a64
;
512 info
->cap_arch
= CS_ARCH_ARM64
;
513 info
->cap_insn_unit
= 4;
514 info
->cap_insn_split
= 4;
518 info
->print_insn
= print_insn_thumb1
;
519 info
->cap_insn_unit
= 2;
520 info
->cap_insn_split
= 4;
521 cap_mode
= CS_MODE_THUMB
;
523 info
->print_insn
= print_insn_arm
;
524 info
->cap_insn_unit
= 4;
525 info
->cap_insn_split
= 4;
526 cap_mode
= CS_MODE_ARM
;
528 if (arm_feature(env
, ARM_FEATURE_V8
)) {
529 cap_mode
|= CS_MODE_V8
;
531 if (arm_feature(env
, ARM_FEATURE_M
)) {
532 cap_mode
|= CS_MODE_MCLASS
;
534 info
->cap_arch
= CS_ARCH_ARM
;
535 info
->cap_mode
= cap_mode
;
538 sctlr_b
= arm_sctlr_b(env
);
539 if (bswap_code(sctlr_b
)) {
540 #ifdef TARGET_WORDS_BIGENDIAN
541 info
->endian
= BFD_ENDIAN_LITTLE
;
543 info
->endian
= BFD_ENDIAN_BIG
;
546 info
->flags
&= ~INSN_ARM_BE32
;
547 #ifndef CONFIG_USER_ONLY
549 info
->flags
|= INSN_ARM_BE32
;
554 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
556 uint32_t Aff1
= idx
/ clustersz
;
557 uint32_t Aff0
= idx
% clustersz
;
558 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
561 static void arm_cpu_initfn(Object
*obj
)
563 CPUState
*cs
= CPU(obj
);
564 ARMCPU
*cpu
= ARM_CPU(obj
);
566 cs
->env_ptr
= &cpu
->env
;
567 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
570 QLIST_INIT(&cpu
->pre_el_change_hooks
);
571 QLIST_INIT(&cpu
->el_change_hooks
);
573 #ifndef CONFIG_USER_ONLY
574 /* Our inbound IRQ and FIQ lines */
576 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
577 * the same interface as non-KVM CPUs.
579 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
581 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
584 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
585 arm_gt_ptimer_cb
, cpu
);
586 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
587 arm_gt_vtimer_cb
, cpu
);
588 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
589 arm_gt_htimer_cb
, cpu
);
590 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
591 arm_gt_stimer_cb
, cpu
);
592 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
593 ARRAY_SIZE(cpu
->gt_timer_outputs
));
595 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
596 "gicv3-maintenance-interrupt", 1);
597 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
601 /* DTB consumers generally don't in fact care what the 'compatible'
602 * string is, so always provide some string and trust that a hypothetical
603 * picky DTB consumer will also provide a helpful error message.
605 cpu
->dtb_compatible
= "qemu,unknown";
606 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
607 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
610 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
614 static Property arm_cpu_reset_cbar_property
=
615 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
617 static Property arm_cpu_reset_hivecs_property
=
618 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
620 static Property arm_cpu_rvbar_property
=
621 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
623 static Property arm_cpu_has_el2_property
=
624 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
626 static Property arm_cpu_has_el3_property
=
627 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
629 static Property arm_cpu_cfgend_property
=
630 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
632 /* use property name "pmu" to match other archs and virt tools */
633 static Property arm_cpu_has_pmu_property
=
634 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
636 static Property arm_cpu_has_mpu_property
=
637 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
639 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
640 * because the CPU initfn will have already set cpu->pmsav7_dregion to
641 * the right value for that particular CPU type, and we don't want
642 * to override that with an incorrect constant value.
644 static Property arm_cpu_pmsav7_dregion_property
=
645 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
647 qdev_prop_uint32
, uint32_t);
649 /* M profile: initial value of the Secure VTOR */
650 static Property arm_cpu_initsvtor_property
=
651 DEFINE_PROP_UINT32("init-svtor", ARMCPU
, init_svtor
, 0);
653 static void arm_cpu_post_init(Object
*obj
)
655 ARMCPU
*cpu
= ARM_CPU(obj
);
657 /* M profile implies PMSA. We have to do this here rather than
658 * in realize with the other feature-implication checks because
659 * we look at the PMSA bit to see if we should add some properties.
661 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
662 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
665 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
666 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
667 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
671 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
672 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
676 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
677 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
681 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
682 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
683 * prevent "has_el3" from existing on CPUs which cannot support EL3.
685 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
688 #ifndef CONFIG_USER_ONLY
689 object_property_add_link(obj
, "secure-memory",
691 (Object
**)&cpu
->secure_memory
,
692 qdev_prop_allow_set_link_before_realize
,
693 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
698 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
699 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
703 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
704 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
708 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
709 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
711 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
712 qdev_property_add_static(DEVICE(obj
),
713 &arm_cpu_pmsav7_dregion_property
,
718 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
719 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
720 qdev_prop_allow_set_link_before_realize
,
721 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
723 qdev_property_add_static(DEVICE(obj
), &arm_cpu_initsvtor_property
,
727 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
731 static void arm_cpu_finalizefn(Object
*obj
)
733 ARMCPU
*cpu
= ARM_CPU(obj
);
734 ARMELChangeHook
*hook
, *next
;
736 g_hash_table_destroy(cpu
->cp_regs
);
738 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
739 QLIST_REMOVE(hook
, node
);
742 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
743 QLIST_REMOVE(hook
, node
);
748 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
750 CPUState
*cs
= CPU(dev
);
751 ARMCPU
*cpu
= ARM_CPU(dev
);
752 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
753 CPUARMState
*env
= &cpu
->env
;
755 Error
*local_err
= NULL
;
757 /* If we needed to query the host kernel for the CPU features
758 * then it's possible that might have failed in the initfn, but
759 * this is the first point where we can report it.
761 if (cpu
->host_cpu_probe_failed
) {
762 if (!kvm_enabled()) {
763 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
765 error_setg(errp
, "Failed to retrieve host CPU features");
770 cpu_exec_realizefn(cs
, &local_err
);
771 if (local_err
!= NULL
) {
772 error_propagate(errp
, local_err
);
776 /* Some features automatically imply others: */
777 if (arm_feature(env
, ARM_FEATURE_V8
)) {
778 set_feature(env
, ARM_FEATURE_V7
);
779 set_feature(env
, ARM_FEATURE_ARM_DIV
);
780 set_feature(env
, ARM_FEATURE_LPAE
);
782 if (arm_feature(env
, ARM_FEATURE_V7
)) {
783 set_feature(env
, ARM_FEATURE_VAPA
);
784 set_feature(env
, ARM_FEATURE_THUMB2
);
785 set_feature(env
, ARM_FEATURE_MPIDR
);
786 if (!arm_feature(env
, ARM_FEATURE_M
)) {
787 set_feature(env
, ARM_FEATURE_V6K
);
789 set_feature(env
, ARM_FEATURE_V6
);
792 /* Always define VBAR for V7 CPUs even if it doesn't exist in
793 * non-EL3 configs. This is needed by some legacy boards.
795 set_feature(env
, ARM_FEATURE_VBAR
);
797 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
798 set_feature(env
, ARM_FEATURE_V6
);
799 set_feature(env
, ARM_FEATURE_MVFR
);
801 if (arm_feature(env
, ARM_FEATURE_V6
)) {
802 set_feature(env
, ARM_FEATURE_V5
);
803 set_feature(env
, ARM_FEATURE_JAZELLE
);
804 if (!arm_feature(env
, ARM_FEATURE_M
)) {
805 set_feature(env
, ARM_FEATURE_AUXCR
);
808 if (arm_feature(env
, ARM_FEATURE_V5
)) {
809 set_feature(env
, ARM_FEATURE_V4T
);
811 if (arm_feature(env
, ARM_FEATURE_M
)) {
812 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
814 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
815 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
817 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
818 set_feature(env
, ARM_FEATURE_VFP3
);
819 set_feature(env
, ARM_FEATURE_VFP_FP16
);
821 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
822 set_feature(env
, ARM_FEATURE_VFP
);
824 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
825 set_feature(env
, ARM_FEATURE_V7MP
);
826 set_feature(env
, ARM_FEATURE_PXN
);
828 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
829 set_feature(env
, ARM_FEATURE_CBAR
);
831 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
832 !arm_feature(env
, ARM_FEATURE_M
)) {
833 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
836 if (arm_feature(env
, ARM_FEATURE_V7
) &&
837 !arm_feature(env
, ARM_FEATURE_M
) &&
838 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
839 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
844 /* For CPUs which might have tiny 1K pages, or which have an
845 * MPU and might have small region sizes, stick with 1K pages.
849 if (!set_preferred_target_page_bits(pagebits
)) {
850 /* This can only ever happen for hotplugging a CPU, or if
851 * the board code incorrectly creates a CPU which it has
852 * promised via minimum_page_size that it will not.
854 error_setg(errp
, "This CPU requires a smaller page size than the "
859 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
860 * We don't support setting cluster ID ([16..23]) (known as Aff2
861 * in later ARM ARM versions), or any of the higher affinity level fields,
862 * so these bits always RAZ.
864 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
865 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
866 ARM_DEFAULT_CPUS_PER_CLUSTER
);
869 if (cpu
->reset_hivecs
) {
870 cpu
->reset_sctlr
|= (1 << 13);
874 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
875 cpu
->reset_sctlr
|= SCTLR_EE
;
877 cpu
->reset_sctlr
|= SCTLR_B
;
882 /* If the has_el3 CPU property is disabled then we need to disable the
885 unset_feature(env
, ARM_FEATURE_EL3
);
887 /* Disable the security extension feature bits in the processor feature
888 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
890 cpu
->id_pfr1
&= ~0xf0;
891 cpu
->id_aa64pfr0
&= ~0xf000;
895 unset_feature(env
, ARM_FEATURE_EL2
);
899 unset_feature(env
, ARM_FEATURE_PMU
);
900 cpu
->id_aa64dfr0
&= ~0xf00;
903 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
904 /* Disable the hypervisor feature bits in the processor feature
905 * registers if we don't have EL2. These are id_pfr1[15:12] and
906 * id_aa64pfr0_el1[11:8].
908 cpu
->id_aa64pfr0
&= ~0xf00;
909 cpu
->id_pfr1
&= ~0xf000;
912 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
913 * to false or by setting pmsav7-dregion to 0.
916 cpu
->pmsav7_dregion
= 0;
918 if (cpu
->pmsav7_dregion
== 0) {
919 cpu
->has_mpu
= false;
922 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
923 arm_feature(env
, ARM_FEATURE_V7
)) {
924 uint32_t nr
= cpu
->pmsav7_dregion
;
927 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
932 if (arm_feature(env
, ARM_FEATURE_V8
)) {
934 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
935 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
936 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
937 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
938 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
941 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
942 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
943 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
948 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
949 uint32_t nr
= cpu
->sau_sregion
;
952 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
957 env
->sau
.rbar
= g_new0(uint32_t, nr
);
958 env
->sau
.rlar
= g_new0(uint32_t, nr
);
962 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
963 set_feature(env
, ARM_FEATURE_VBAR
);
966 register_cp_regs_for_features(cpu
);
967 arm_cpu_register_gdb_regs_for_features(cpu
);
969 init_cpreg_list(cpu
);
971 #ifndef CONFIG_USER_ONLY
972 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
975 if (!cpu
->secure_memory
) {
976 cpu
->secure_memory
= cs
->memory
;
978 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
983 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
985 /* No core_count specified, default to smp_cpus. */
986 if (cpu
->core_count
== -1) {
987 cpu
->core_count
= smp_cpus
;
994 acc
->parent_realize(dev
, errp
);
997 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1002 const char *cpunamestr
;
1004 cpuname
= g_strsplit(cpu_model
, ",", 1);
1005 cpunamestr
= cpuname
[0];
1006 #ifdef CONFIG_USER_ONLY
1007 /* For backwards compatibility usermode emulation allows "-cpu any",
1008 * which has the same semantics as "-cpu max".
1010 if (!strcmp(cpunamestr
, "any")) {
1014 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1015 oc
= object_class_by_name(typename
);
1016 g_strfreev(cpuname
);
1018 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1019 object_class_is_abstract(oc
)) {
1025 /* CPU models. These are not needed for the AArch64 linux-user build. */
1026 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1028 static void arm926_initfn(Object
*obj
)
1030 ARMCPU
*cpu
= ARM_CPU(obj
);
1032 cpu
->dtb_compatible
= "arm,arm926";
1033 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1034 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1035 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1036 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1037 set_feature(&cpu
->env
, ARM_FEATURE_JAZELLE
);
1038 cpu
->midr
= 0x41069265;
1039 cpu
->reset_fpsid
= 0x41011090;
1040 cpu
->ctr
= 0x1dd20d2;
1041 cpu
->reset_sctlr
= 0x00090078;
1044 static void arm946_initfn(Object
*obj
)
1046 ARMCPU
*cpu
= ARM_CPU(obj
);
1048 cpu
->dtb_compatible
= "arm,arm946";
1049 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1050 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1051 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1052 cpu
->midr
= 0x41059461;
1053 cpu
->ctr
= 0x0f004006;
1054 cpu
->reset_sctlr
= 0x00000078;
1057 static void arm1026_initfn(Object
*obj
)
1059 ARMCPU
*cpu
= ARM_CPU(obj
);
1061 cpu
->dtb_compatible
= "arm,arm1026";
1062 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1063 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1064 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1065 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1066 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1067 set_feature(&cpu
->env
, ARM_FEATURE_JAZELLE
);
1068 cpu
->midr
= 0x4106a262;
1069 cpu
->reset_fpsid
= 0x410110a0;
1070 cpu
->ctr
= 0x1dd20d2;
1071 cpu
->reset_sctlr
= 0x00090078;
1072 cpu
->reset_auxcr
= 1;
1074 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1075 ARMCPRegInfo ifar
= {
1076 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1078 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1081 define_one_arm_cp_reg(cpu
, &ifar
);
1085 static void arm1136_r2_initfn(Object
*obj
)
1087 ARMCPU
*cpu
= ARM_CPU(obj
);
1088 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1089 * older core than plain "arm1136". In particular this does not
1090 * have the v6K features.
1091 * These ID register values are correct for 1136 but may be wrong
1092 * for 1136_r2 (in particular r0p2 does not actually implement most
1093 * of the ID registers).
1096 cpu
->dtb_compatible
= "arm,arm1136";
1097 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1098 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1099 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1100 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1101 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1102 cpu
->midr
= 0x4107b362;
1103 cpu
->reset_fpsid
= 0x410120b4;
1104 cpu
->mvfr0
= 0x11111111;
1105 cpu
->mvfr1
= 0x00000000;
1106 cpu
->ctr
= 0x1dd20d2;
1107 cpu
->reset_sctlr
= 0x00050078;
1108 cpu
->id_pfr0
= 0x111;
1112 cpu
->id_mmfr0
= 0x01130003;
1113 cpu
->id_mmfr1
= 0x10030302;
1114 cpu
->id_mmfr2
= 0x01222110;
1115 cpu
->id_isar0
= 0x00140011;
1116 cpu
->id_isar1
= 0x12002111;
1117 cpu
->id_isar2
= 0x11231111;
1118 cpu
->id_isar3
= 0x01102131;
1119 cpu
->id_isar4
= 0x141;
1120 cpu
->reset_auxcr
= 7;
1123 static void arm1136_initfn(Object
*obj
)
1125 ARMCPU
*cpu
= ARM_CPU(obj
);
1127 cpu
->dtb_compatible
= "arm,arm1136";
1128 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1129 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1130 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1131 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1132 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1133 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1134 cpu
->midr
= 0x4117b363;
1135 cpu
->reset_fpsid
= 0x410120b4;
1136 cpu
->mvfr0
= 0x11111111;
1137 cpu
->mvfr1
= 0x00000000;
1138 cpu
->ctr
= 0x1dd20d2;
1139 cpu
->reset_sctlr
= 0x00050078;
1140 cpu
->id_pfr0
= 0x111;
1144 cpu
->id_mmfr0
= 0x01130003;
1145 cpu
->id_mmfr1
= 0x10030302;
1146 cpu
->id_mmfr2
= 0x01222110;
1147 cpu
->id_isar0
= 0x00140011;
1148 cpu
->id_isar1
= 0x12002111;
1149 cpu
->id_isar2
= 0x11231111;
1150 cpu
->id_isar3
= 0x01102131;
1151 cpu
->id_isar4
= 0x141;
1152 cpu
->reset_auxcr
= 7;
1155 static void arm1176_initfn(Object
*obj
)
1157 ARMCPU
*cpu
= ARM_CPU(obj
);
1159 cpu
->dtb_compatible
= "arm,arm1176";
1160 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1161 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1162 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1163 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1164 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1165 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1166 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1167 cpu
->midr
= 0x410fb767;
1168 cpu
->reset_fpsid
= 0x410120b5;
1169 cpu
->mvfr0
= 0x11111111;
1170 cpu
->mvfr1
= 0x00000000;
1171 cpu
->ctr
= 0x1dd20d2;
1172 cpu
->reset_sctlr
= 0x00050078;
1173 cpu
->id_pfr0
= 0x111;
1174 cpu
->id_pfr1
= 0x11;
1175 cpu
->id_dfr0
= 0x33;
1177 cpu
->id_mmfr0
= 0x01130003;
1178 cpu
->id_mmfr1
= 0x10030302;
1179 cpu
->id_mmfr2
= 0x01222100;
1180 cpu
->id_isar0
= 0x0140011;
1181 cpu
->id_isar1
= 0x12002111;
1182 cpu
->id_isar2
= 0x11231121;
1183 cpu
->id_isar3
= 0x01102131;
1184 cpu
->id_isar4
= 0x01141;
1185 cpu
->reset_auxcr
= 7;
1188 static void arm11mpcore_initfn(Object
*obj
)
1190 ARMCPU
*cpu
= ARM_CPU(obj
);
1192 cpu
->dtb_compatible
= "arm,arm11mpcore";
1193 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1194 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1195 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1196 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1197 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1198 cpu
->midr
= 0x410fb022;
1199 cpu
->reset_fpsid
= 0x410120b4;
1200 cpu
->mvfr0
= 0x11111111;
1201 cpu
->mvfr1
= 0x00000000;
1202 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1203 cpu
->id_pfr0
= 0x111;
1207 cpu
->id_mmfr0
= 0x01100103;
1208 cpu
->id_mmfr1
= 0x10020302;
1209 cpu
->id_mmfr2
= 0x01222000;
1210 cpu
->id_isar0
= 0x00100011;
1211 cpu
->id_isar1
= 0x12002111;
1212 cpu
->id_isar2
= 0x11221011;
1213 cpu
->id_isar3
= 0x01102131;
1214 cpu
->id_isar4
= 0x141;
1215 cpu
->reset_auxcr
= 1;
1218 static void cortex_m3_initfn(Object
*obj
)
1220 ARMCPU
*cpu
= ARM_CPU(obj
);
1221 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1222 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1223 cpu
->midr
= 0x410fc231;
1224 cpu
->pmsav7_dregion
= 8;
1225 cpu
->id_pfr0
= 0x00000030;
1226 cpu
->id_pfr1
= 0x00000200;
1227 cpu
->id_dfr0
= 0x00100000;
1228 cpu
->id_afr0
= 0x00000000;
1229 cpu
->id_mmfr0
= 0x00000030;
1230 cpu
->id_mmfr1
= 0x00000000;
1231 cpu
->id_mmfr2
= 0x00000000;
1232 cpu
->id_mmfr3
= 0x00000000;
1233 cpu
->id_isar0
= 0x01141110;
1234 cpu
->id_isar1
= 0x02111000;
1235 cpu
->id_isar2
= 0x21112231;
1236 cpu
->id_isar3
= 0x01111110;
1237 cpu
->id_isar4
= 0x01310102;
1238 cpu
->id_isar5
= 0x00000000;
1241 static void cortex_m4_initfn(Object
*obj
)
1243 ARMCPU
*cpu
= ARM_CPU(obj
);
1245 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1246 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1247 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1248 cpu
->midr
= 0x410fc240; /* r0p0 */
1249 cpu
->pmsav7_dregion
= 8;
1250 cpu
->id_pfr0
= 0x00000030;
1251 cpu
->id_pfr1
= 0x00000200;
1252 cpu
->id_dfr0
= 0x00100000;
1253 cpu
->id_afr0
= 0x00000000;
1254 cpu
->id_mmfr0
= 0x00000030;
1255 cpu
->id_mmfr1
= 0x00000000;
1256 cpu
->id_mmfr2
= 0x00000000;
1257 cpu
->id_mmfr3
= 0x00000000;
1258 cpu
->id_isar0
= 0x01141110;
1259 cpu
->id_isar1
= 0x02111000;
1260 cpu
->id_isar2
= 0x21112231;
1261 cpu
->id_isar3
= 0x01111110;
1262 cpu
->id_isar4
= 0x01310102;
1263 cpu
->id_isar5
= 0x00000000;
1266 static void cortex_m33_initfn(Object
*obj
)
1268 ARMCPU
*cpu
= ARM_CPU(obj
);
1270 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1271 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1272 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
1273 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1274 cpu
->midr
= 0x410fd213; /* r0p3 */
1275 cpu
->pmsav7_dregion
= 16;
1276 cpu
->sau_sregion
= 8;
1277 cpu
->id_pfr0
= 0x00000030;
1278 cpu
->id_pfr1
= 0x00000210;
1279 cpu
->id_dfr0
= 0x00200000;
1280 cpu
->id_afr0
= 0x00000000;
1281 cpu
->id_mmfr0
= 0x00101F40;
1282 cpu
->id_mmfr1
= 0x00000000;
1283 cpu
->id_mmfr2
= 0x01000000;
1284 cpu
->id_mmfr3
= 0x00000000;
1285 cpu
->id_isar0
= 0x01101110;
1286 cpu
->id_isar1
= 0x02212000;
1287 cpu
->id_isar2
= 0x20232232;
1288 cpu
->id_isar3
= 0x01111131;
1289 cpu
->id_isar4
= 0x01310132;
1290 cpu
->id_isar5
= 0x00000000;
1291 cpu
->clidr
= 0x00000000;
1292 cpu
->ctr
= 0x8000c000;
1295 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1297 CPUClass
*cc
= CPU_CLASS(oc
);
1299 #ifndef CONFIG_USER_ONLY
1300 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1303 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1306 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1307 /* Dummy the TCM region regs for the moment */
1308 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1309 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1310 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1311 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1312 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1313 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1317 static void cortex_r5_initfn(Object
*obj
)
1319 ARMCPU
*cpu
= ARM_CPU(obj
);
1321 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1322 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1323 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1324 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1325 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1326 cpu
->midr
= 0x411fc153; /* r1p3 */
1327 cpu
->id_pfr0
= 0x0131;
1328 cpu
->id_pfr1
= 0x001;
1329 cpu
->id_dfr0
= 0x010400;
1331 cpu
->id_mmfr0
= 0x0210030;
1332 cpu
->id_mmfr1
= 0x00000000;
1333 cpu
->id_mmfr2
= 0x01200000;
1334 cpu
->id_mmfr3
= 0x0211;
1335 cpu
->id_isar0
= 0x2101111;
1336 cpu
->id_isar1
= 0x13112111;
1337 cpu
->id_isar2
= 0x21232141;
1338 cpu
->id_isar3
= 0x01112131;
1339 cpu
->id_isar4
= 0x0010142;
1340 cpu
->id_isar5
= 0x0;
1341 cpu
->mp_is_up
= true;
1342 cpu
->pmsav7_dregion
= 16;
1343 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1346 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1347 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1348 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1349 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1350 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1354 static void cortex_a8_initfn(Object
*obj
)
1356 ARMCPU
*cpu
= ARM_CPU(obj
);
1358 cpu
->dtb_compatible
= "arm,cortex-a8";
1359 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1360 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1361 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1362 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1363 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1364 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1365 cpu
->midr
= 0x410fc080;
1366 cpu
->reset_fpsid
= 0x410330c0;
1367 cpu
->mvfr0
= 0x11110222;
1368 cpu
->mvfr1
= 0x00011111;
1369 cpu
->ctr
= 0x82048004;
1370 cpu
->reset_sctlr
= 0x00c50078;
1371 cpu
->id_pfr0
= 0x1031;
1372 cpu
->id_pfr1
= 0x11;
1373 cpu
->id_dfr0
= 0x400;
1375 cpu
->id_mmfr0
= 0x31100003;
1376 cpu
->id_mmfr1
= 0x20000000;
1377 cpu
->id_mmfr2
= 0x01202000;
1378 cpu
->id_mmfr3
= 0x11;
1379 cpu
->id_isar0
= 0x00101111;
1380 cpu
->id_isar1
= 0x12112111;
1381 cpu
->id_isar2
= 0x21232031;
1382 cpu
->id_isar3
= 0x11112131;
1383 cpu
->id_isar4
= 0x00111142;
1384 cpu
->dbgdidr
= 0x15141000;
1385 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1386 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1387 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1388 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1389 cpu
->reset_auxcr
= 2;
1390 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1393 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1394 /* power_control should be set to maximum latency. Again,
1395 * default to 0 and set by private hook
1397 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1398 .access
= PL1_RW
, .resetvalue
= 0,
1399 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1400 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1401 .access
= PL1_RW
, .resetvalue
= 0,
1402 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1403 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1404 .access
= PL1_RW
, .resetvalue
= 0,
1405 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1406 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1407 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1408 /* TLB lockdown control */
1409 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1410 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1411 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1412 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1413 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1414 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1415 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1416 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1417 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1418 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1422 static void cortex_a9_initfn(Object
*obj
)
1424 ARMCPU
*cpu
= ARM_CPU(obj
);
1426 cpu
->dtb_compatible
= "arm,cortex-a9";
1427 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1428 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1429 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1430 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1431 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1432 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1433 /* Note that A9 supports the MP extensions even for
1434 * A9UP and single-core A9MP (which are both different
1435 * and valid configurations; we don't model A9UP).
1437 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1438 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1439 cpu
->midr
= 0x410fc090;
1440 cpu
->reset_fpsid
= 0x41033090;
1441 cpu
->mvfr0
= 0x11110222;
1442 cpu
->mvfr1
= 0x01111111;
1443 cpu
->ctr
= 0x80038003;
1444 cpu
->reset_sctlr
= 0x00c50078;
1445 cpu
->id_pfr0
= 0x1031;
1446 cpu
->id_pfr1
= 0x11;
1447 cpu
->id_dfr0
= 0x000;
1449 cpu
->id_mmfr0
= 0x00100103;
1450 cpu
->id_mmfr1
= 0x20000000;
1451 cpu
->id_mmfr2
= 0x01230000;
1452 cpu
->id_mmfr3
= 0x00002111;
1453 cpu
->id_isar0
= 0x00101111;
1454 cpu
->id_isar1
= 0x13112111;
1455 cpu
->id_isar2
= 0x21232041;
1456 cpu
->id_isar3
= 0x11112131;
1457 cpu
->id_isar4
= 0x00111142;
1458 cpu
->dbgdidr
= 0x35141000;
1459 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1460 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1461 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1462 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1465 #ifndef CONFIG_USER_ONLY
1466 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1468 /* Linux wants the number of processors from here.
1469 * Might as well set the interrupt-controller bit too.
1471 return ((smp_cpus
- 1) << 24) | (1 << 23);
1475 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1476 #ifndef CONFIG_USER_ONLY
1477 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1478 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1479 .writefn
= arm_cp_write_ignore
, },
1481 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1482 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1486 static void cortex_a7_initfn(Object
*obj
)
1488 ARMCPU
*cpu
= ARM_CPU(obj
);
1490 cpu
->dtb_compatible
= "arm,cortex-a7";
1491 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1492 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1493 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1494 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1495 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1496 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1497 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1498 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1499 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1500 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1501 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1502 cpu
->midr
= 0x410fc075;
1503 cpu
->reset_fpsid
= 0x41023075;
1504 cpu
->mvfr0
= 0x10110222;
1505 cpu
->mvfr1
= 0x11111111;
1506 cpu
->ctr
= 0x84448003;
1507 cpu
->reset_sctlr
= 0x00c50078;
1508 cpu
->id_pfr0
= 0x00001131;
1509 cpu
->id_pfr1
= 0x00011011;
1510 cpu
->id_dfr0
= 0x02010555;
1511 cpu
->pmceid0
= 0x00000000;
1512 cpu
->pmceid1
= 0x00000000;
1513 cpu
->id_afr0
= 0x00000000;
1514 cpu
->id_mmfr0
= 0x10101105;
1515 cpu
->id_mmfr1
= 0x40000000;
1516 cpu
->id_mmfr2
= 0x01240000;
1517 cpu
->id_mmfr3
= 0x02102211;
1518 cpu
->id_isar0
= 0x01101110;
1519 cpu
->id_isar1
= 0x13112111;
1520 cpu
->id_isar2
= 0x21232041;
1521 cpu
->id_isar3
= 0x11112131;
1522 cpu
->id_isar4
= 0x10011142;
1523 cpu
->dbgdidr
= 0x3515f005;
1524 cpu
->clidr
= 0x0a200023;
1525 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1526 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1527 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1528 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1531 static void cortex_a15_initfn(Object
*obj
)
1533 ARMCPU
*cpu
= ARM_CPU(obj
);
1535 cpu
->dtb_compatible
= "arm,cortex-a15";
1536 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1537 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1538 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1539 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1540 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1541 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1542 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1543 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1544 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1545 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1546 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1547 cpu
->midr
= 0x412fc0f1;
1548 cpu
->reset_fpsid
= 0x410430f0;
1549 cpu
->mvfr0
= 0x10110222;
1550 cpu
->mvfr1
= 0x11111111;
1551 cpu
->ctr
= 0x8444c004;
1552 cpu
->reset_sctlr
= 0x00c50078;
1553 cpu
->id_pfr0
= 0x00001131;
1554 cpu
->id_pfr1
= 0x00011011;
1555 cpu
->id_dfr0
= 0x02010555;
1556 cpu
->pmceid0
= 0x0000000;
1557 cpu
->pmceid1
= 0x00000000;
1558 cpu
->id_afr0
= 0x00000000;
1559 cpu
->id_mmfr0
= 0x10201105;
1560 cpu
->id_mmfr1
= 0x20000000;
1561 cpu
->id_mmfr2
= 0x01240000;
1562 cpu
->id_mmfr3
= 0x02102211;
1563 cpu
->id_isar0
= 0x02101110;
1564 cpu
->id_isar1
= 0x13112111;
1565 cpu
->id_isar2
= 0x21232041;
1566 cpu
->id_isar3
= 0x11112131;
1567 cpu
->id_isar4
= 0x10011142;
1568 cpu
->dbgdidr
= 0x3515f021;
1569 cpu
->clidr
= 0x0a200023;
1570 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1571 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1572 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1573 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1576 static void ti925t_initfn(Object
*obj
)
1578 ARMCPU
*cpu
= ARM_CPU(obj
);
1579 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1580 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1581 cpu
->midr
= ARM_CPUID_TI925T
;
1582 cpu
->ctr
= 0x5109149;
1583 cpu
->reset_sctlr
= 0x00000070;
1586 static void sa1100_initfn(Object
*obj
)
1588 ARMCPU
*cpu
= ARM_CPU(obj
);
1590 cpu
->dtb_compatible
= "intel,sa1100";
1591 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1592 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1593 cpu
->midr
= 0x4401A11B;
1594 cpu
->reset_sctlr
= 0x00000070;
1597 static void sa1110_initfn(Object
*obj
)
1599 ARMCPU
*cpu
= ARM_CPU(obj
);
1600 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1601 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1602 cpu
->midr
= 0x6901B119;
1603 cpu
->reset_sctlr
= 0x00000070;
1606 static void pxa250_initfn(Object
*obj
)
1608 ARMCPU
*cpu
= ARM_CPU(obj
);
1610 cpu
->dtb_compatible
= "marvell,xscale";
1611 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1612 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1613 cpu
->midr
= 0x69052100;
1614 cpu
->ctr
= 0xd172172;
1615 cpu
->reset_sctlr
= 0x00000078;
1618 static void pxa255_initfn(Object
*obj
)
1620 ARMCPU
*cpu
= ARM_CPU(obj
);
1622 cpu
->dtb_compatible
= "marvell,xscale";
1623 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1624 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1625 cpu
->midr
= 0x69052d00;
1626 cpu
->ctr
= 0xd172172;
1627 cpu
->reset_sctlr
= 0x00000078;
1630 static void pxa260_initfn(Object
*obj
)
1632 ARMCPU
*cpu
= ARM_CPU(obj
);
1634 cpu
->dtb_compatible
= "marvell,xscale";
1635 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1636 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1637 cpu
->midr
= 0x69052903;
1638 cpu
->ctr
= 0xd172172;
1639 cpu
->reset_sctlr
= 0x00000078;
1642 static void pxa261_initfn(Object
*obj
)
1644 ARMCPU
*cpu
= ARM_CPU(obj
);
1646 cpu
->dtb_compatible
= "marvell,xscale";
1647 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1648 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1649 cpu
->midr
= 0x69052d05;
1650 cpu
->ctr
= 0xd172172;
1651 cpu
->reset_sctlr
= 0x00000078;
1654 static void pxa262_initfn(Object
*obj
)
1656 ARMCPU
*cpu
= ARM_CPU(obj
);
1658 cpu
->dtb_compatible
= "marvell,xscale";
1659 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1660 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1661 cpu
->midr
= 0x69052d06;
1662 cpu
->ctr
= 0xd172172;
1663 cpu
->reset_sctlr
= 0x00000078;
1666 static void pxa270a0_initfn(Object
*obj
)
1668 ARMCPU
*cpu
= ARM_CPU(obj
);
1670 cpu
->dtb_compatible
= "marvell,xscale";
1671 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1672 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1673 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1674 cpu
->midr
= 0x69054110;
1675 cpu
->ctr
= 0xd172172;
1676 cpu
->reset_sctlr
= 0x00000078;
1679 static void pxa270a1_initfn(Object
*obj
)
1681 ARMCPU
*cpu
= ARM_CPU(obj
);
1683 cpu
->dtb_compatible
= "marvell,xscale";
1684 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1685 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1686 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1687 cpu
->midr
= 0x69054111;
1688 cpu
->ctr
= 0xd172172;
1689 cpu
->reset_sctlr
= 0x00000078;
1692 static void pxa270b0_initfn(Object
*obj
)
1694 ARMCPU
*cpu
= ARM_CPU(obj
);
1696 cpu
->dtb_compatible
= "marvell,xscale";
1697 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1698 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1699 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1700 cpu
->midr
= 0x69054112;
1701 cpu
->ctr
= 0xd172172;
1702 cpu
->reset_sctlr
= 0x00000078;
1705 static void pxa270b1_initfn(Object
*obj
)
1707 ARMCPU
*cpu
= ARM_CPU(obj
);
1709 cpu
->dtb_compatible
= "marvell,xscale";
1710 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1711 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1712 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1713 cpu
->midr
= 0x69054113;
1714 cpu
->ctr
= 0xd172172;
1715 cpu
->reset_sctlr
= 0x00000078;
1718 static void pxa270c0_initfn(Object
*obj
)
1720 ARMCPU
*cpu
= ARM_CPU(obj
);
1722 cpu
->dtb_compatible
= "marvell,xscale";
1723 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1724 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1725 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1726 cpu
->midr
= 0x69054114;
1727 cpu
->ctr
= 0xd172172;
1728 cpu
->reset_sctlr
= 0x00000078;
1731 static void pxa270c5_initfn(Object
*obj
)
1733 ARMCPU
*cpu
= ARM_CPU(obj
);
1735 cpu
->dtb_compatible
= "marvell,xscale";
1736 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1737 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1738 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1739 cpu
->midr
= 0x69054117;
1740 cpu
->ctr
= 0xd172172;
1741 cpu
->reset_sctlr
= 0x00000078;
1744 #ifndef TARGET_AARCH64
1745 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1746 * otherwise, a CPU with as many features enabled as our emulation supports.
1747 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1748 * this only needs to handle 32 bits.
1750 static void arm_max_initfn(Object
*obj
)
1752 ARMCPU
*cpu
= ARM_CPU(obj
);
1754 if (kvm_enabled()) {
1755 kvm_arm_set_cpu_features_from_host(cpu
);
1757 cortex_a15_initfn(obj
);
1758 #ifdef CONFIG_USER_ONLY
1759 /* We don't set these in system emulation mode for the moment,
1760 * since we don't correctly set the ID registers to advertise them,
1762 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1763 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1764 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1765 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1766 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1767 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1768 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1769 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1770 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1771 set_feature(&cpu
->env
, ARM_FEATURE_V8_RDM
);
1772 set_feature(&cpu
->env
, ARM_FEATURE_V8_FCMA
);
1778 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1780 typedef struct ARMCPUInfo
{
1782 void (*initfn
)(Object
*obj
);
1783 void (*class_init
)(ObjectClass
*oc
, void *data
);
1786 static const ARMCPUInfo arm_cpus
[] = {
1787 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1788 { .name
= "arm926", .initfn
= arm926_initfn
},
1789 { .name
= "arm946", .initfn
= arm946_initfn
},
1790 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1791 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1792 * older core than plain "arm1136". In particular this does not
1793 * have the v6K features.
1795 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1796 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1797 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1798 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1799 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1800 .class_init
= arm_v7m_class_init
},
1801 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1802 .class_init
= arm_v7m_class_init
},
1803 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
1804 .class_init
= arm_v7m_class_init
},
1805 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1806 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1807 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1808 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1809 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1810 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1811 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1812 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1813 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1814 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1815 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1816 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1817 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1818 /* "pxa270" is an alias for "pxa270-a0" */
1819 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1820 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1821 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1822 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1823 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1824 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1825 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1826 #ifndef TARGET_AARCH64
1827 { .name
= "max", .initfn
= arm_max_initfn
},
1829 #ifdef CONFIG_USER_ONLY
1830 { .name
= "any", .initfn
= arm_max_initfn
},
1836 static Property arm_cpu_properties
[] = {
1837 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1838 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1839 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1840 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1841 mp_affinity
, ARM64_AFFINITY_INVALID
),
1842 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1843 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
1844 DEFINE_PROP_END_OF_LIST()
1847 #ifdef CONFIG_USER_ONLY
1848 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
,
1849 int rw
, int mmu_idx
)
1851 ARMCPU
*cpu
= ARM_CPU(cs
);
1852 CPUARMState
*env
= &cpu
->env
;
1854 env
->exception
.vaddress
= address
;
1856 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1858 cs
->exception_index
= EXCP_DATA_ABORT
;
1864 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1866 ARMCPU
*cpu
= ARM_CPU(cs
);
1867 CPUARMState
*env
= &cpu
->env
;
1869 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1870 return g_strdup("iwmmxt");
1872 return g_strdup("arm");
1875 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1877 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1878 CPUClass
*cc
= CPU_CLASS(acc
);
1879 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1881 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
1882 &acc
->parent_realize
);
1883 dc
->props
= arm_cpu_properties
;
1885 acc
->parent_reset
= cc
->reset
;
1886 cc
->reset
= arm_cpu_reset
;
1888 cc
->class_by_name
= arm_cpu_class_by_name
;
1889 cc
->has_work
= arm_cpu_has_work
;
1890 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1891 cc
->dump_state
= arm_cpu_dump_state
;
1892 cc
->set_pc
= arm_cpu_set_pc
;
1893 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1894 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1895 #ifdef CONFIG_USER_ONLY
1896 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1898 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1899 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1900 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
1901 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1902 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1903 cc
->vmsd
= &vmstate_arm_cpu
;
1904 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1905 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1906 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1908 cc
->gdb_num_core_regs
= 26;
1909 cc
->gdb_core_xml_file
= "arm-core.xml";
1910 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1911 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
1912 cc
->gdb_stop_before_watchpoint
= true;
1913 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1914 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1915 #if !defined(CONFIG_USER_ONLY)
1916 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1919 cc
->disas_set_info
= arm_disas_set_info
;
1921 cc
->tcg_initialize
= arm_translate_init
;
1926 static void arm_host_initfn(Object
*obj
)
1928 ARMCPU
*cpu
= ARM_CPU(obj
);
1930 kvm_arm_set_cpu_features_from_host(cpu
);
1933 static const TypeInfo host_arm_cpu_type_info
= {
1934 .name
= TYPE_ARM_HOST_CPU
,
1935 #ifdef TARGET_AARCH64
1936 .parent
= TYPE_AARCH64_CPU
,
1938 .parent
= TYPE_ARM_CPU
,
1940 .instance_init
= arm_host_initfn
,
1945 static void cpu_register(const ARMCPUInfo
*info
)
1947 TypeInfo type_info
= {
1948 .parent
= TYPE_ARM_CPU
,
1949 .instance_size
= sizeof(ARMCPU
),
1950 .instance_init
= info
->initfn
,
1951 .class_size
= sizeof(ARMCPUClass
),
1952 .class_init
= info
->class_init
,
1955 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1956 type_register(&type_info
);
1957 g_free((void *)type_info
.name
);
1960 static const TypeInfo arm_cpu_type_info
= {
1961 .name
= TYPE_ARM_CPU
,
1963 .instance_size
= sizeof(ARMCPU
),
1964 .instance_init
= arm_cpu_initfn
,
1965 .instance_post_init
= arm_cpu_post_init
,
1966 .instance_finalize
= arm_cpu_finalizefn
,
1968 .class_size
= sizeof(ARMCPUClass
),
1969 .class_init
= arm_cpu_class_init
,
1972 static const TypeInfo idau_interface_type_info
= {
1973 .name
= TYPE_IDAU_INTERFACE
,
1974 .parent
= TYPE_INTERFACE
,
1975 .class_size
= sizeof(IDAUInterfaceClass
),
1978 static void arm_cpu_register_types(void)
1980 const ARMCPUInfo
*info
= arm_cpus
;
1982 type_register_static(&arm_cpu_type_info
);
1983 type_register_static(&idau_interface_type_info
);
1985 while (info
->name
) {
1991 type_register_static(&host_arm_cpu_type_info
);
1995 type_init(arm_cpu_register_types
)