4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "exec/exec-all.h"
35 #include "hw/qdev-properties.h"
36 #if !defined(CONFIG_USER_ONLY)
37 #include "hw/loader.h"
38 #include "hw/boards.h"
40 #include "hw/intc/armv7m_nvic.h"
41 #endif /* CONFIG_TCG */
42 #endif /* !CONFIG_USER_ONLY */
43 #include "sysemu/tcg.h"
44 #include "sysemu/qtest.h"
45 #include "sysemu/hw_accel.h"
47 #include "disas/capstone.h"
48 #include "fpu/softfloat.h"
51 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
53 ARMCPU
*cpu
= ARM_CPU(cs
);
54 CPUARMState
*env
= &cpu
->env
;
60 env
->regs
[15] = value
& ~1;
61 env
->thumb
= value
& 1;
65 static vaddr
arm_cpu_get_pc(CPUState
*cs
)
67 ARMCPU
*cpu
= ARM_CPU(cs
);
68 CPUARMState
*env
= &cpu
->env
;
78 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
79 const TranslationBlock
*tb
)
81 /* The program counter is always up to date with CF_PCREL. */
82 if (!(tb_cflags(tb
) & CF_PCREL
)) {
83 CPUARMState
*env
= cpu_env(cs
);
85 * It's OK to look at env for the current mode here, because it's
86 * never possible for an AArch64 TB to chain to an AArch32 TB.
91 env
->regs
[15] = tb
->pc
;
96 void arm_restore_state_to_opc(CPUState
*cs
,
97 const TranslationBlock
*tb
,
100 CPUARMState
*env
= cpu_env(cs
);
103 if (tb_cflags(tb
) & CF_PCREL
) {
104 env
->pc
= (env
->pc
& TARGET_PAGE_MASK
) | data
[0];
108 env
->condexec_bits
= 0;
109 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
111 if (tb_cflags(tb
) & CF_PCREL
) {
112 env
->regs
[15] = (env
->regs
[15] & TARGET_PAGE_MASK
) | data
[0];
114 env
->regs
[15] = data
[0];
116 env
->condexec_bits
= data
[1];
117 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
120 #endif /* CONFIG_TCG */
122 static bool arm_cpu_has_work(CPUState
*cs
)
124 ARMCPU
*cpu
= ARM_CPU(cs
);
126 return (cpu
->power_state
!= PSCI_OFF
)
127 && cs
->interrupt_request
&
128 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
129 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
| CPU_INTERRUPT_VSERR
130 | CPU_INTERRUPT_EXITTB
);
133 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
136 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
139 entry
->opaque
= opaque
;
141 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
144 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
147 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
150 entry
->opaque
= opaque
;
152 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
155 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
157 /* Reset a single ARMCPRegInfo register */
158 ARMCPRegInfo
*ri
= value
;
159 ARMCPU
*cpu
= opaque
;
161 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
)) {
166 ri
->resetfn(&cpu
->env
, ri
);
170 /* A zero offset is never possible as it would be regs[0]
171 * so we use it to indicate that reset is being handled elsewhere.
172 * This is basically only used for fields in non-core coprocessors
173 * (like the pxa2xx ones).
175 if (!ri
->fieldoffset
) {
179 if (cpreg_field_is_64bit(ri
)) {
180 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
182 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
186 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
188 /* Purely an assertion check: we've already done reset once,
189 * so now check that running the reset for the cpreg doesn't
190 * change its value. This traps bugs where two different cpregs
191 * both try to reset the same state field but to different values.
193 ARMCPRegInfo
*ri
= value
;
194 ARMCPU
*cpu
= opaque
;
195 uint64_t oldvalue
, newvalue
;
197 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
201 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
202 cp_reg_reset(key
, value
, opaque
);
203 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
204 assert(oldvalue
== newvalue
);
207 static void arm_cpu_reset_hold(Object
*obj
)
209 CPUState
*s
= CPU(obj
);
210 ARMCPU
*cpu
= ARM_CPU(s
);
211 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
212 CPUARMState
*env
= &cpu
->env
;
214 if (acc
->parent_phases
.hold
) {
215 acc
->parent_phases
.hold(obj
);
218 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
220 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
221 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
223 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
224 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
225 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
226 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
228 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
230 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
231 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
234 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
235 /* 64 bit CPUs always start in 64 bit mode */
237 #if defined(CONFIG_USER_ONLY)
238 env
->pstate
= PSTATE_MODE_EL0t
;
239 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
240 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
241 /* Enable all PAC keys. */
242 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
243 SCTLR_EnDA
| SCTLR_EnDB
);
244 /* Trap on btype=3 for PACIxSP. */
245 env
->cp15
.sctlr_el
[1] |= SCTLR_BT0
;
246 /* Trap on implementation defined registers. */
247 if (cpu_isar_feature(aa64_tidcp1
, cpu
)) {
248 env
->cp15
.sctlr_el
[1] |= SCTLR_TIDCP
;
250 /* and to the FP/Neon instructions */
251 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
253 /* and to the SVE instructions, with default vector length */
254 if (cpu_isar_feature(aa64_sve
, cpu
)) {
255 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
257 env
->vfp
.zcr_el
[1] = cpu
->sve_default_vq
- 1;
259 /* and for SME instructions, with default vector length, and TPIDR2 */
260 if (cpu_isar_feature(aa64_sme
, cpu
)) {
261 env
->cp15
.sctlr_el
[1] |= SCTLR_EnTP2
;
262 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
264 env
->vfp
.smcr_el
[1] = cpu
->sme_default_vq
- 1;
265 if (cpu_isar_feature(aa64_sme_fa64
, cpu
)) {
266 env
->vfp
.smcr_el
[1] = FIELD_DP64(env
->vfp
.smcr_el
[1],
271 * Enable 48-bit address space (TODO: take reserved_va into account).
272 * Enable TBI0 but not TBI1.
273 * Note that this must match useronly_clean_ptr.
275 env
->cp15
.tcr_el
[1] = 5 | (1ULL << 37);
278 if (cpu_isar_feature(aa64_mte
, cpu
)) {
279 /* Enable tag access, but leave TCF0 as No Effect (0). */
280 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
282 * Exclude all tags, so that tag 0 is always used.
283 * This corresponds to Linux current->thread.gcr_incl = 0.
285 * Set RRND, so that helper_irg() will generate a seed later.
286 * Here in cpu_reset(), the crypto subsystem has not yet been
289 env
->cp15
.gcr_el1
= 0x1ffff;
292 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
293 * This is not yet exposed from the Linux kernel in any way.
295 env
->cp15
.sctlr_el
[1] |= SCTLR_TSCXT
;
296 /* Disable access to Debug Communication Channel (DCC). */
297 env
->cp15
.mdscr_el1
|= 1 << 12;
299 /* Reset into the highest available EL */
300 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
301 env
->pstate
= PSTATE_MODE_EL3h
;
302 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
303 env
->pstate
= PSTATE_MODE_EL2h
;
305 env
->pstate
= PSTATE_MODE_EL1h
;
308 /* Sample rvbar at reset. */
309 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
310 env
->pc
= env
->cp15
.rvbar
;
313 #if defined(CONFIG_USER_ONLY)
314 /* Userspace expects access to cp10 and cp11 for FP/Neon */
315 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
317 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
320 if (arm_feature(env
, ARM_FEATURE_V8
)) {
321 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
322 env
->regs
[15] = cpu
->rvbar_prop
;
326 #if defined(CONFIG_USER_ONLY)
327 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
328 /* For user mode we must enable access to coprocessors */
329 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
330 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
331 env
->cp15
.c15_cpar
= 3;
332 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
333 env
->cp15
.c15_cpar
= 1;
338 * If the highest available EL is EL2, AArch32 will start in Hyp
339 * mode; otherwise it starts in SVC. Note that if we start in
340 * AArch64 then these values in the uncached_cpsr will be ignored.
342 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
343 !arm_feature(env
, ARM_FEATURE_EL3
)) {
344 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
346 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
348 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
350 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
351 * executing as AArch32 then check if highvecs are enabled and
352 * adjust the PC accordingly.
354 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
355 env
->regs
[15] = 0xFFFF0000;
358 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
361 if (arm_feature(env
, ARM_FEATURE_M
)) {
362 #ifndef CONFIG_USER_ONLY
363 uint32_t initial_msp
; /* Loaded from 0x0 */
364 uint32_t initial_pc
; /* Loaded from 0x4 */
369 if (cpu_isar_feature(aa32_lob
, cpu
)) {
371 * LTPSIZE is constant 4 if MVE not implemented, and resets
372 * to an UNKNOWN value if MVE is implemented. We choose to
375 env
->v7m
.ltpsize
= 4;
376 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
377 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
378 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
381 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
382 env
->v7m
.secure
= true;
384 /* This bit resets to 0 if security is supported, but 1 if
385 * it is not. The bit is not present in v7M, but we set it
386 * here so we can avoid having to make checks on it conditional
387 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
389 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
391 * Set NSACR to indicate "NS access permitted to everything";
392 * this avoids having to have all the tests of it being
393 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
394 * v8.1M the guest-visible value of NSACR in a CPU without the
395 * Security Extension is 0xcff.
397 env
->v7m
.nsacr
= 0xcff;
400 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
401 * that it resets to 1, so QEMU always does that rather than making
402 * it dependent on CPU model. In v8M it is RES1.
404 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
405 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
406 if (arm_feature(env
, ARM_FEATURE_V8
)) {
407 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
408 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
409 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
411 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
412 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
413 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
416 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
417 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
418 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
419 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
422 #ifndef CONFIG_USER_ONLY
423 /* Unlike A/R profile, M profile defines the reset LR value */
424 env
->regs
[14] = 0xffffffff;
426 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
427 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
429 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
430 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
431 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
433 /* Address zero is covered by ROM which hasn't yet been
434 * copied into physical memory.
436 initial_msp
= ldl_p(rom
);
437 initial_pc
= ldl_p(rom
+ 4);
439 /* Address zero not covered by a ROM blob, or the ROM blob
440 * is in non-modifiable memory and this is a second reset after
441 * it got copied into memory. In the latter case, rom_ptr
442 * will return a NULL pointer and we should use ldl_phys instead.
444 initial_msp
= ldl_phys(s
->as
, vecbase
);
445 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
448 qemu_log_mask(CPU_LOG_INT
,
449 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
450 initial_msp
, initial_pc
);
452 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
453 env
->regs
[15] = initial_pc
& ~1;
454 env
->thumb
= initial_pc
& 1;
457 * For user mode we run non-secure and with access to the FPU.
458 * The FPU context is active (ie does not need further setup)
459 * and is owned by non-secure.
461 env
->v7m
.secure
= false;
462 env
->v7m
.nsacr
= 0xcff;
463 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
464 env
->v7m
.fpccr
[M_REG_S
] &=
465 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
466 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
470 /* M profile requires that reset clears the exclusive monitor;
471 * A profile does not, but clearing it makes more sense than having it
472 * set with an exclusive access on address zero.
474 arm_clear_exclusive(env
);
476 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
477 if (cpu
->pmsav7_dregion
> 0) {
478 if (arm_feature(env
, ARM_FEATURE_V8
)) {
479 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
480 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
481 * cpu
->pmsav7_dregion
);
482 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
483 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
484 * cpu
->pmsav7_dregion
);
485 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
486 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
487 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
488 * cpu
->pmsav7_dregion
);
489 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
490 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
491 * cpu
->pmsav7_dregion
);
493 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
494 memset(env
->pmsav7
.drbar
, 0,
495 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
496 memset(env
->pmsav7
.drsr
, 0,
497 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
498 memset(env
->pmsav7
.dracr
, 0,
499 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
503 if (cpu
->pmsav8r_hdregion
> 0) {
504 memset(env
->pmsav8
.hprbar
, 0,
505 sizeof(*env
->pmsav8
.hprbar
) * cpu
->pmsav8r_hdregion
);
506 memset(env
->pmsav8
.hprlar
, 0,
507 sizeof(*env
->pmsav8
.hprlar
) * cpu
->pmsav8r_hdregion
);
510 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
511 env
->pmsav7
.rnr
[M_REG_S
] = 0;
512 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
513 env
->pmsav8
.mair0
[M_REG_S
] = 0;
514 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
515 env
->pmsav8
.mair1
[M_REG_S
] = 0;
518 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
519 if (cpu
->sau_sregion
> 0) {
520 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
521 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
524 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
525 * the Cortex-M33 does.
530 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
531 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
532 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
533 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
534 set_float_detect_tininess(float_tininess_before_rounding
,
535 &env
->vfp
.fp_status
);
536 set_float_detect_tininess(float_tininess_before_rounding
,
537 &env
->vfp
.standard_fp_status
);
538 set_float_detect_tininess(float_tininess_before_rounding
,
539 &env
->vfp
.fp_status_f16
);
540 set_float_detect_tininess(float_tininess_before_rounding
,
541 &env
->vfp
.standard_fp_status_f16
);
542 #ifndef CONFIG_USER_ONLY
544 kvm_arm_reset_vcpu(cpu
);
549 hw_breakpoint_update_all(cpu
);
550 hw_watchpoint_update_all(cpu
);
552 arm_rebuild_hflags(env
);
556 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
558 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
559 unsigned int target_el
,
560 unsigned int cur_el
, bool secure
,
563 CPUARMState
*env
= cpu_env(cs
);
564 bool pstate_unmasked
;
565 bool unmasked
= false;
568 * Don't take exceptions if they target a lower EL.
569 * This check should catch any exceptions that would not be taken
572 if (cur_el
> target_el
) {
578 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
582 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
586 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
587 /* VFIQs are only taken when hypervized. */
590 return !(env
->daif
& PSTATE_F
);
592 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
593 /* VIRQs are only taken when hypervized. */
596 return !(env
->daif
& PSTATE_I
);
598 if (!(hcr_el2
& HCR_AMO
) || (hcr_el2
& HCR_TGE
)) {
599 /* VIRQs are only taken when hypervized. */
602 return !(env
->daif
& PSTATE_A
);
604 g_assert_not_reached();
608 * Use the target EL, current execution state and SCR/HCR settings to
609 * determine whether the corresponding CPSR bit is used to mask the
612 if ((target_el
> cur_el
) && (target_el
!= 1)) {
613 /* Exceptions targeting a higher EL may not be maskable */
614 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
618 * According to ARM DDI 0487H.a, an interrupt can be masked
619 * when HCR_E2H and HCR_TGE are both set regardless of the
620 * current Security state. Note that we need to revisit this
621 * part again once we need to support NMI.
623 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
628 /* Interrupt cannot be masked when the target EL is 3 */
632 g_assert_not_reached();
636 * The old 32-bit-only environment has a more complicated
637 * masking setup. HCR and SCR bits not only affect interrupt
638 * routing but also change the behaviour of masking.
645 * If FIQs are routed to EL3 or EL2 then there are cases where
646 * we override the CPSR.F in determining if the exception is
647 * masked or not. If neither of these are set then we fall back
648 * to the CPSR.F setting otherwise we further assess the state
651 hcr
= hcr_el2
& HCR_FMO
;
652 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
655 * When EL3 is 32-bit, the SCR.FW bit controls whether the
656 * CPSR.F bit masks FIQ interrupts when taken in non-secure
657 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
658 * when non-secure but only when FIQs are only routed to EL3.
660 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
664 * When EL3 execution state is 32-bit, if HCR.IMO is set then
665 * we may override the CPSR.I masking when in non-secure state.
666 * The SCR.IRQ setting has already been taken into consideration
667 * when setting the target EL, so it does not have a further
670 hcr
= hcr_el2
& HCR_IMO
;
674 g_assert_not_reached();
677 if ((scr
|| hcr
) && !secure
) {
684 * The PSTATE bits only mask the interrupt if we have not overridden the
687 return unmasked
|| pstate_unmasked
;
690 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
692 CPUClass
*cc
= CPU_GET_CLASS(cs
);
693 CPUARMState
*env
= cpu_env(cs
);
694 uint32_t cur_el
= arm_current_el(env
);
695 bool secure
= arm_is_secure(env
);
696 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
700 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
702 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
704 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
705 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
706 cur_el
, secure
, hcr_el2
)) {
710 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
712 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
713 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
714 cur_el
, secure
, hcr_el2
)) {
718 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
719 excp_idx
= EXCP_VIRQ
;
721 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
722 cur_el
, secure
, hcr_el2
)) {
726 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
727 excp_idx
= EXCP_VFIQ
;
729 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
730 cur_el
, secure
, hcr_el2
)) {
734 if (interrupt_request
& CPU_INTERRUPT_VSERR
) {
735 excp_idx
= EXCP_VSERR
;
737 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
738 cur_el
, secure
, hcr_el2
)) {
739 /* Taking a virtual abort clears HCR_EL2.VSE */
740 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
741 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
748 cs
->exception_index
= excp_idx
;
749 env
->exception
.target_el
= target_el
;
750 cc
->tcg_ops
->do_interrupt(cs
);
754 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
756 void arm_cpu_update_virq(ARMCPU
*cpu
)
759 * Update the interrupt level for VIRQ, which is the logical OR of
760 * the HCR_EL2.VI bit and the input line level from the GIC.
762 CPUARMState
*env
= &cpu
->env
;
763 CPUState
*cs
= CPU(cpu
);
765 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
766 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
768 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
770 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
772 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
777 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
780 * Update the interrupt level for VFIQ, which is the logical OR of
781 * the HCR_EL2.VF bit and the input line level from the GIC.
783 CPUARMState
*env
= &cpu
->env
;
784 CPUState
*cs
= CPU(cpu
);
786 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
787 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
789 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
791 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
793 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
798 void arm_cpu_update_vserr(ARMCPU
*cpu
)
801 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
803 CPUARMState
*env
= &cpu
->env
;
804 CPUState
*cs
= CPU(cpu
);
806 bool new_state
= env
->cp15
.hcr_el2
& HCR_VSE
;
808 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) != 0)) {
810 cpu_interrupt(cs
, CPU_INTERRUPT_VSERR
);
812 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
817 #ifndef CONFIG_USER_ONLY
818 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
820 ARMCPU
*cpu
= opaque
;
821 CPUARMState
*env
= &cpu
->env
;
822 CPUState
*cs
= CPU(cpu
);
823 static const int mask
[] = {
824 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
825 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
826 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
827 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
830 if (!arm_feature(env
, ARM_FEATURE_EL2
) &&
831 (irq
== ARM_CPU_VIRQ
|| irq
== ARM_CPU_VFIQ
)) {
833 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
834 * have EL2 support we don't care. (Unless the guest is doing something
835 * silly this will only be calls saying "level is still 0".)
841 env
->irq_line_state
|= mask
[irq
];
843 env
->irq_line_state
&= ~mask
[irq
];
848 arm_cpu_update_virq(cpu
);
851 arm_cpu_update_vfiq(cpu
);
856 cpu_interrupt(cs
, mask
[irq
]);
858 cpu_reset_interrupt(cs
, mask
[irq
]);
862 g_assert_not_reached();
866 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
869 ARMCPU
*cpu
= opaque
;
870 CPUARMState
*env
= &cpu
->env
;
871 CPUState
*cs
= CPU(cpu
);
872 uint32_t linestate_bit
;
877 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
878 linestate_bit
= CPU_INTERRUPT_HARD
;
881 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
882 linestate_bit
= CPU_INTERRUPT_FIQ
;
885 g_assert_not_reached();
889 env
->irq_line_state
|= linestate_bit
;
891 env
->irq_line_state
&= ~linestate_bit
;
893 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
897 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
899 ARMCPU
*cpu
= ARM_CPU(cs
);
900 CPUARMState
*env
= &cpu
->env
;
902 cpu_synchronize_state(cs
);
903 return arm_cpu_data_is_big_endian(env
);
908 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
910 ARMCPU
*ac
= ARM_CPU(cpu
);
911 CPUARMState
*env
= &ac
->env
;
915 info
->cap_arch
= CS_ARCH_ARM64
;
916 info
->cap_insn_unit
= 4;
917 info
->cap_insn_split
= 4;
921 info
->cap_insn_unit
= 2;
922 info
->cap_insn_split
= 4;
923 cap_mode
= CS_MODE_THUMB
;
925 info
->cap_insn_unit
= 4;
926 info
->cap_insn_split
= 4;
927 cap_mode
= CS_MODE_ARM
;
929 if (arm_feature(env
, ARM_FEATURE_V8
)) {
930 cap_mode
|= CS_MODE_V8
;
932 if (arm_feature(env
, ARM_FEATURE_M
)) {
933 cap_mode
|= CS_MODE_MCLASS
;
935 info
->cap_arch
= CS_ARCH_ARM
;
936 info
->cap_mode
= cap_mode
;
939 sctlr_b
= arm_sctlr_b(env
);
940 if (bswap_code(sctlr_b
)) {
941 #if TARGET_BIG_ENDIAN
942 info
->endian
= BFD_ENDIAN_LITTLE
;
944 info
->endian
= BFD_ENDIAN_BIG
;
947 info
->flags
&= ~INSN_ARM_BE32
;
948 #ifndef CONFIG_USER_ONLY
950 info
->flags
|= INSN_ARM_BE32
;
955 #ifdef TARGET_AARCH64
957 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
959 ARMCPU
*cpu
= ARM_CPU(cs
);
960 CPUARMState
*env
= &cpu
->env
;
961 uint32_t psr
= pstate_read(env
);
963 int el
= arm_current_el(env
);
964 const char *ns_status
;
967 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
968 for (i
= 0; i
< 32; i
++) {
970 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
972 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
973 (i
+ 2) % 3 ? " " : "\n");
977 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
978 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
982 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
984 psr
& PSTATE_N
? 'N' : '-',
985 psr
& PSTATE_Z
? 'Z' : '-',
986 psr
& PSTATE_C
? 'C' : '-',
987 psr
& PSTATE_V
? 'V' : '-',
990 psr
& PSTATE_SP
? 'h' : 't');
992 if (cpu_isar_feature(aa64_sme
, cpu
)) {
993 qemu_fprintf(f
, " SVCR=%08" PRIx64
" %c%c",
995 (FIELD_EX64(env
->svcr
, SVCR
, ZA
) ? 'Z' : '-'),
996 (FIELD_EX64(env
->svcr
, SVCR
, SM
) ? 'S' : '-'));
998 if (cpu_isar_feature(aa64_bti
, cpu
)) {
999 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
1001 if (!(flags
& CPU_DUMP_FPU
)) {
1002 qemu_fprintf(f
, "\n");
1005 if (fp_exception_el(env
, el
) != 0) {
1006 qemu_fprintf(f
, " FPU disabled\n");
1009 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
1010 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
1012 if (cpu_isar_feature(aa64_sme
, cpu
) && FIELD_EX64(env
->svcr
, SVCR
, SM
)) {
1013 sve
= sme_exception_el(env
, el
) == 0;
1014 } else if (cpu_isar_feature(aa64_sve
, cpu
)) {
1015 sve
= sve_exception_el(env
, el
) == 0;
1021 int zcr_len
= sve_vqm1_for_el(env
, el
);
1023 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
1025 if (i
== FFR_PRED_NUM
) {
1026 qemu_fprintf(f
, "FFR=");
1027 /* It's last, so end the line. */
1030 qemu_fprintf(f
, "P%02d=", i
);
1043 /* More than one quadword per predicate. */
1048 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
1050 if (j
* 4 + 4 <= zcr_len
+ 1) {
1053 digits
= (zcr_len
% 4 + 1) * 4;
1055 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
1056 env
->vfp
.pregs
[i
].p
[j
],
1057 j
? ":" : eol
? "\n" : " ");
1063 * With vl=16, there are only 37 columns per register,
1064 * so output two registers per line.
1066 for (i
= 0; i
< 32; i
++) {
1067 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
1068 i
, env
->vfp
.zregs
[i
].d
[1],
1069 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
1072 for (i
= 0; i
< 32; i
++) {
1073 qemu_fprintf(f
, "Z%02d=", i
);
1074 for (j
= zcr_len
; j
>= 0; j
--) {
1075 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
1076 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
1077 env
->vfp
.zregs
[i
].d
[j
* 2 + 0],
1083 for (i
= 0; i
< 32; i
++) {
1084 uint64_t *q
= aa64_vfp_qreg(env
, i
);
1085 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
1086 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
1090 if (cpu_isar_feature(aa64_sme
, cpu
) &&
1091 FIELD_EX64(env
->svcr
, SVCR
, ZA
) &&
1092 sme_exception_el(env
, el
) == 0) {
1093 int zcr_len
= sve_vqm1_for_el_sm(env
, el
, true);
1094 int svl
= (zcr_len
+ 1) * 16;
1095 int svl_lg10
= svl
< 100 ? 2 : 3;
1097 for (i
= 0; i
< svl
; i
++) {
1098 qemu_fprintf(f
, "ZA[%0*d]=", svl_lg10
, i
);
1099 for (j
= zcr_len
; j
>= 0; --j
) {
1100 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%c",
1101 env
->zarray
[i
].d
[2 * j
+ 1],
1102 env
->zarray
[i
].d
[2 * j
],
1111 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1113 g_assert_not_reached();
1118 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1120 ARMCPU
*cpu
= ARM_CPU(cs
);
1121 CPUARMState
*env
= &cpu
->env
;
1125 aarch64_cpu_dump_state(cs
, f
, flags
);
1129 for (i
= 0; i
< 16; i
++) {
1130 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
1132 qemu_fprintf(f
, "\n");
1134 qemu_fprintf(f
, " ");
1138 if (arm_feature(env
, ARM_FEATURE_M
)) {
1139 uint32_t xpsr
= xpsr_read(env
);
1141 const char *ns_status
= "";
1143 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1144 ns_status
= env
->v7m
.secure
? "S " : "NS ";
1147 if (xpsr
& XPSR_EXCP
) {
1150 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
1151 mode
= "unpriv-thread";
1153 mode
= "priv-thread";
1157 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
1159 xpsr
& XPSR_N
? 'N' : '-',
1160 xpsr
& XPSR_Z
? 'Z' : '-',
1161 xpsr
& XPSR_C
? 'C' : '-',
1162 xpsr
& XPSR_V
? 'V' : '-',
1163 xpsr
& XPSR_T
? 'T' : 'A',
1167 uint32_t psr
= cpsr_read(env
);
1168 const char *ns_status
= "";
1170 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1171 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1172 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1175 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1177 psr
& CPSR_N
? 'N' : '-',
1178 psr
& CPSR_Z
? 'Z' : '-',
1179 psr
& CPSR_C
? 'C' : '-',
1180 psr
& CPSR_V
? 'V' : '-',
1181 psr
& CPSR_T
? 'T' : 'A',
1183 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1186 if (flags
& CPU_DUMP_FPU
) {
1188 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1190 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1193 for (i
= 0; i
< numvfpregs
; i
++) {
1194 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1195 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1197 i
* 2 + 1, (uint32_t)(v
>> 32),
1200 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1201 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1202 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1207 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1209 uint32_t Aff1
= idx
/ clustersz
;
1210 uint32_t Aff0
= idx
% clustersz
;
1211 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1214 static void arm_cpu_initfn(Object
*obj
)
1216 ARMCPU
*cpu
= ARM_CPU(obj
);
1218 cpu
->cp_regs
= g_hash_table_new_full(g_direct_hash
, g_direct_equal
,
1221 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1222 QLIST_INIT(&cpu
->el_change_hooks
);
1224 #ifdef CONFIG_USER_ONLY
1225 # ifdef TARGET_AARCH64
1227 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1228 * These values were chosen to fit within the default signal frame.
1229 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1230 * and our corresponding cpu property.
1232 cpu
->sve_default_vq
= 4;
1233 cpu
->sme_default_vq
= 2;
1236 /* Our inbound IRQ and FIQ lines */
1237 if (kvm_enabled()) {
1238 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1239 * the same interface as non-KVM CPUs.
1241 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1243 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1246 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1247 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1249 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1250 "gicv3-maintenance-interrupt", 1);
1251 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1252 "pmu-interrupt", 1);
1255 /* DTB consumers generally don't in fact care what the 'compatible'
1256 * string is, so always provide some string and trust that a hypothetical
1257 * picky DTB consumer will also provide a helpful error message.
1259 cpu
->dtb_compatible
= "qemu,unknown";
1260 cpu
->psci_version
= QEMU_PSCI_VERSION_0_1
; /* By default assume PSCI v0.1 */
1261 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1263 if (tcg_enabled() || hvf_enabled()) {
1264 /* TCG and HVF implement PSCI 1.1 */
1265 cpu
->psci_version
= QEMU_PSCI_VERSION_1_1
;
1269 static Property arm_cpu_gt_cntfrq_property
=
1270 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1271 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1273 static Property arm_cpu_reset_cbar_property
=
1274 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1276 static Property arm_cpu_reset_hivecs_property
=
1277 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1279 #ifndef CONFIG_USER_ONLY
1280 static Property arm_cpu_has_el2_property
=
1281 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1283 static Property arm_cpu_has_el3_property
=
1284 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1287 static Property arm_cpu_cfgend_property
=
1288 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1290 static Property arm_cpu_has_vfp_property
=
1291 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1293 static Property arm_cpu_has_vfp_d32_property
=
1294 DEFINE_PROP_BOOL("vfp-d32", ARMCPU
, has_vfp_d32
, true);
1296 static Property arm_cpu_has_neon_property
=
1297 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1299 static Property arm_cpu_has_dsp_property
=
1300 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1302 static Property arm_cpu_has_mpu_property
=
1303 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1305 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1306 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1307 * the right value for that particular CPU type, and we don't want
1308 * to override that with an incorrect constant value.
1310 static Property arm_cpu_pmsav7_dregion_property
=
1311 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1313 qdev_prop_uint32
, uint32_t);
1315 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1317 ARMCPU
*cpu
= ARM_CPU(obj
);
1319 return cpu
->has_pmu
;
1322 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1324 ARMCPU
*cpu
= ARM_CPU(obj
);
1327 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1328 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1331 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1333 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1335 cpu
->has_pmu
= value
;
1338 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1341 * The exact approach to calculating guest ticks is:
1343 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1344 * NANOSECONDS_PER_SECOND);
1346 * We don't do that. Rather we intentionally use integer division
1347 * truncation below and in the caller for the conversion of host monotonic
1348 * time to guest ticks to provide the exact inverse for the semantics of
1349 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1350 * it loses precision when representing frequencies where
1351 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1352 * provide an exact inverse leads to scheduling timers with negative
1353 * periods, which in turn leads to sticky behaviour in the guest.
1355 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1356 * cannot become zero.
1358 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1359 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1362 static void arm_cpu_propagate_feature_implications(ARMCPU
*cpu
)
1364 CPUARMState
*env
= &cpu
->env
;
1365 bool no_aa32
= false;
1368 * Some features automatically imply others: set the feature
1369 * bits explicitly for these cases.
1372 if (arm_feature(env
, ARM_FEATURE_M
)) {
1373 set_feature(env
, ARM_FEATURE_PMSA
);
1376 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1377 if (arm_feature(env
, ARM_FEATURE_M
)) {
1378 set_feature(env
, ARM_FEATURE_V7
);
1380 set_feature(env
, ARM_FEATURE_V7VE
);
1385 * There exist AArch64 cpus without AArch32 support. When KVM
1386 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1387 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1388 * As a general principle, we also do not make ID register
1389 * consistency checks anywhere unless using TCG, because only
1390 * for TCG would a consistency-check failure be a QEMU bug.
1392 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1393 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1396 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1398 * v7 Virtualization Extensions. In real hardware this implies
1399 * EL2 and also the presence of the Security Extensions.
1400 * For QEMU, for backwards-compatibility we implement some
1401 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1402 * include the various other features that V7VE implies.
1403 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1404 * Security Extensions is ARM_FEATURE_EL3.
1406 assert(!tcg_enabled() || no_aa32
||
1407 cpu_isar_feature(aa32_arm_div
, cpu
));
1408 set_feature(env
, ARM_FEATURE_LPAE
);
1409 set_feature(env
, ARM_FEATURE_V7
);
1411 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1412 set_feature(env
, ARM_FEATURE_VAPA
);
1413 set_feature(env
, ARM_FEATURE_THUMB2
);
1414 set_feature(env
, ARM_FEATURE_MPIDR
);
1415 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1416 set_feature(env
, ARM_FEATURE_V6K
);
1418 set_feature(env
, ARM_FEATURE_V6
);
1422 * Always define VBAR for V7 CPUs even if it doesn't exist in
1423 * non-EL3 configs. This is needed by some legacy boards.
1425 set_feature(env
, ARM_FEATURE_VBAR
);
1427 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1428 set_feature(env
, ARM_FEATURE_V6
);
1429 set_feature(env
, ARM_FEATURE_MVFR
);
1431 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1432 set_feature(env
, ARM_FEATURE_V5
);
1433 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1434 assert(!tcg_enabled() || no_aa32
||
1435 cpu_isar_feature(aa32_jazelle
, cpu
));
1436 set_feature(env
, ARM_FEATURE_AUXCR
);
1439 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1440 set_feature(env
, ARM_FEATURE_V4T
);
1442 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1443 set_feature(env
, ARM_FEATURE_V7MP
);
1445 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1446 set_feature(env
, ARM_FEATURE_CBAR
);
1448 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1449 !arm_feature(env
, ARM_FEATURE_M
)) {
1450 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1454 void arm_cpu_post_init(Object
*obj
)
1456 ARMCPU
*cpu
= ARM_CPU(obj
);
1459 * Some features imply others. Figure this out now, because we
1460 * are going to look at the feature bits in deciding which
1461 * properties to add.
1463 arm_cpu_propagate_feature_implications(cpu
);
1465 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1466 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1467 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1470 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1471 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1474 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1475 object_property_add_uint64_ptr(obj
, "rvbar",
1477 OBJ_PROP_FLAG_READWRITE
);
1480 #ifndef CONFIG_USER_ONLY
1481 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1482 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1483 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1485 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1487 object_property_add_link(obj
, "secure-memory",
1489 (Object
**)&cpu
->secure_memory
,
1490 qdev_prop_allow_set_link_before_realize
,
1491 OBJ_PROP_LINK_STRONG
);
1494 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1495 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1499 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1500 cpu
->has_pmu
= true;
1501 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1505 * Allow user to turn off VFP and Neon support, but only for TCG --
1506 * KVM does not currently allow us to lie to the guest about its
1507 * ID/feature registers, so the guest always sees what the host has.
1509 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1510 if (cpu_isar_feature(aa64_fp_simd
, cpu
)) {
1511 cpu
->has_vfp
= true;
1512 cpu
->has_vfp_d32
= true;
1513 if (tcg_enabled() || qtest_enabled()) {
1514 qdev_property_add_static(DEVICE(obj
),
1515 &arm_cpu_has_vfp_property
);
1518 } else if (cpu_isar_feature(aa32_vfp
, cpu
)) {
1519 cpu
->has_vfp
= true;
1520 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1521 cpu
->has_vfp_d32
= true;
1523 * The permitted values of the SIMDReg bits [3:0] on
1524 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1525 * make sure that has_vfp_d32 can not be set to false.
1527 if ((tcg_enabled() || qtest_enabled())
1528 && !(arm_feature(&cpu
->env
, ARM_FEATURE_V8
)
1529 && !arm_feature(&cpu
->env
, ARM_FEATURE_M
))) {
1530 qdev_property_add_static(DEVICE(obj
),
1531 &arm_cpu_has_vfp_d32_property
);
1536 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1537 cpu
->has_neon
= true;
1538 if (!kvm_enabled()) {
1539 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1543 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1544 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1545 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1548 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1549 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1550 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1551 qdev_property_add_static(DEVICE(obj
),
1552 &arm_cpu_pmsav7_dregion_property
);
1556 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1557 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1558 qdev_prop_allow_set_link_before_realize
,
1559 OBJ_PROP_LINK_STRONG
);
1561 * M profile: initial value of the Secure VTOR. We can't just use
1562 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1563 * the property to be set after realize.
1565 object_property_add_uint32_ptr(obj
, "init-svtor",
1567 OBJ_PROP_FLAG_READWRITE
);
1569 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1571 * Initial value of the NS VTOR (for cores without the Security
1572 * extension, this is the only VTOR)
1574 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1576 OBJ_PROP_FLAG_READWRITE
);
1579 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1580 object_property_add_uint32_ptr(obj
, "psci-conduit",
1582 OBJ_PROP_FLAG_READWRITE
);
1584 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1586 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1587 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1590 if (kvm_enabled()) {
1591 kvm_arm_add_vcpu_properties(obj
);
1594 #ifndef CONFIG_USER_ONLY
1595 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1596 cpu_isar_feature(aa64_mte
, cpu
)) {
1597 object_property_add_link(obj
, "tag-memory",
1599 (Object
**)&cpu
->tag_memory
,
1600 qdev_prop_allow_set_link_before_realize
,
1601 OBJ_PROP_LINK_STRONG
);
1603 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1604 object_property_add_link(obj
, "secure-tag-memory",
1606 (Object
**)&cpu
->secure_tag_memory
,
1607 qdev_prop_allow_set_link_before_realize
,
1608 OBJ_PROP_LINK_STRONG
);
1614 static void arm_cpu_finalizefn(Object
*obj
)
1616 ARMCPU
*cpu
= ARM_CPU(obj
);
1617 ARMELChangeHook
*hook
, *next
;
1619 g_hash_table_destroy(cpu
->cp_regs
);
1621 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1622 QLIST_REMOVE(hook
, node
);
1625 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1626 QLIST_REMOVE(hook
, node
);
1629 #ifndef CONFIG_USER_ONLY
1630 if (cpu
->pmu_timer
) {
1631 timer_free(cpu
->pmu_timer
);
1636 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1638 Error
*local_err
= NULL
;
1640 #ifdef TARGET_AARCH64
1641 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1642 arm_cpu_sve_finalize(cpu
, &local_err
);
1643 if (local_err
!= NULL
) {
1644 error_propagate(errp
, local_err
);
1648 arm_cpu_sme_finalize(cpu
, &local_err
);
1649 if (local_err
!= NULL
) {
1650 error_propagate(errp
, local_err
);
1654 arm_cpu_pauth_finalize(cpu
, &local_err
);
1655 if (local_err
!= NULL
) {
1656 error_propagate(errp
, local_err
);
1660 arm_cpu_lpa2_finalize(cpu
, &local_err
);
1661 if (local_err
!= NULL
) {
1662 error_propagate(errp
, local_err
);
1668 if (kvm_enabled()) {
1669 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1670 if (local_err
!= NULL
) {
1671 error_propagate(errp
, local_err
);
1677 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1679 CPUState
*cs
= CPU(dev
);
1680 ARMCPU
*cpu
= ARM_CPU(dev
);
1681 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1682 CPUARMState
*env
= &cpu
->env
;
1684 Error
*local_err
= NULL
;
1686 /* Use pc-relative instructions in system-mode */
1687 #ifndef CONFIG_USER_ONLY
1688 cs
->tcg_cflags
|= CF_PCREL
;
1691 /* If we needed to query the host kernel for the CPU features
1692 * then it's possible that might have failed in the initfn, but
1693 * this is the first point where we can report it.
1695 if (cpu
->host_cpu_probe_failed
) {
1696 if (!kvm_enabled() && !hvf_enabled()) {
1697 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1699 error_setg(errp
, "Failed to retrieve host CPU features");
1704 #ifndef CONFIG_USER_ONLY
1705 /* The NVIC and M-profile CPU are two halves of a single piece of
1706 * hardware; trying to use one without the other is a command line
1707 * error and will result in segfaults if not caught here.
1709 if (arm_feature(env
, ARM_FEATURE_M
)) {
1711 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1716 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1721 if (!tcg_enabled() && !qtest_enabled()) {
1723 * We assume that no accelerator except TCG (and the "not really an
1724 * accelerator" qtest) can handle these features, because Arm hardware
1725 * virtualization can't virtualize them.
1727 * Catch all the cases which might cause us to create more than one
1728 * address space for the CPU (otherwise we will assert() later in
1729 * cpu_address_space_init()).
1731 if (arm_feature(env
, ARM_FEATURE_M
)) {
1733 "Cannot enable %s when using an M-profile guest CPU",
1734 current_accel_name());
1739 "Cannot enable %s when guest CPU has EL3 enabled",
1740 current_accel_name());
1743 if (cpu
->tag_memory
) {
1745 "Cannot enable %s when guest CPUs has MTE enabled",
1746 current_accel_name());
1754 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1755 if (!cpu
->gt_cntfrq_hz
) {
1756 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1760 scale
= gt_cntfrq_period_ns(cpu
);
1762 scale
= GTIMER_SCALE
;
1765 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1766 arm_gt_ptimer_cb
, cpu
);
1767 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1768 arm_gt_vtimer_cb
, cpu
);
1769 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1770 arm_gt_htimer_cb
, cpu
);
1771 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1772 arm_gt_stimer_cb
, cpu
);
1773 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1774 arm_gt_hvtimer_cb
, cpu
);
1778 cpu_exec_realizefn(cs
, &local_err
);
1779 if (local_err
!= NULL
) {
1780 error_propagate(errp
, local_err
);
1784 arm_cpu_finalize_features(cpu
, &local_err
);
1785 if (local_err
!= NULL
) {
1786 error_propagate(errp
, local_err
);
1790 #ifdef CONFIG_USER_ONLY
1792 * User mode relies on IC IVAU instructions to catch modification of
1795 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
1796 * IC IVAU even if the emulated processor does not normally require it.
1798 cpu
->ctr
= FIELD_DP64(cpu
->ctr
, CTR_EL0
, DIC
, 0);
1801 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1802 cpu
->has_vfp
!= cpu
->has_neon
) {
1804 * This is an architectural requirement for AArch64; AArch32 is
1805 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1808 "AArch64 CPUs must have both VFP and Neon or neither");
1812 if (cpu
->has_vfp_d32
!= cpu
->has_neon
) {
1813 error_setg(errp
, "ARM CPUs must have both VFP-D32 and Neon or neither");
1817 if (!cpu
->has_vfp_d32
) {
1820 u
= cpu
->isar
.mvfr0
;
1821 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 1); /* 16 registers */
1822 cpu
->isar
.mvfr0
= u
;
1825 if (!cpu
->has_vfp
) {
1829 t
= cpu
->isar
.id_aa64isar1
;
1830 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1831 cpu
->isar
.id_aa64isar1
= t
;
1833 t
= cpu
->isar
.id_aa64pfr0
;
1834 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1835 cpu
->isar
.id_aa64pfr0
= t
;
1837 u
= cpu
->isar
.id_isar6
;
1838 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1839 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1840 cpu
->isar
.id_isar6
= u
;
1842 u
= cpu
->isar
.mvfr0
;
1843 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1844 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1845 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1846 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1847 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1848 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1849 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1850 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1852 cpu
->isar
.mvfr0
= u
;
1854 u
= cpu
->isar
.mvfr1
;
1855 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1856 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1857 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1858 if (arm_feature(env
, ARM_FEATURE_M
)) {
1859 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1861 cpu
->isar
.mvfr1
= u
;
1863 u
= cpu
->isar
.mvfr2
;
1864 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1865 cpu
->isar
.mvfr2
= u
;
1868 if (!cpu
->has_neon
) {
1872 unset_feature(env
, ARM_FEATURE_NEON
);
1874 t
= cpu
->isar
.id_aa64isar0
;
1875 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 0);
1876 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 0);
1877 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 0);
1878 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 0);
1879 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 0);
1880 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 0);
1881 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1882 cpu
->isar
.id_aa64isar0
= t
;
1884 t
= cpu
->isar
.id_aa64isar1
;
1885 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1886 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
1887 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
1888 cpu
->isar
.id_aa64isar1
= t
;
1890 t
= cpu
->isar
.id_aa64pfr0
;
1891 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1892 cpu
->isar
.id_aa64pfr0
= t
;
1894 u
= cpu
->isar
.id_isar5
;
1895 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 0);
1896 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 0);
1897 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 0);
1898 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1899 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1900 cpu
->isar
.id_isar5
= u
;
1902 u
= cpu
->isar
.id_isar6
;
1903 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1904 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1905 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1906 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
1907 cpu
->isar
.id_isar6
= u
;
1909 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1910 u
= cpu
->isar
.mvfr1
;
1911 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1912 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1913 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1914 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1915 cpu
->isar
.mvfr1
= u
;
1917 u
= cpu
->isar
.mvfr2
;
1918 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1919 cpu
->isar
.mvfr2
= u
;
1923 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1927 t
= cpu
->isar
.id_aa64isar0
;
1928 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1929 cpu
->isar
.id_aa64isar0
= t
;
1931 t
= cpu
->isar
.id_aa64isar1
;
1932 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1933 cpu
->isar
.id_aa64isar1
= t
;
1935 u
= cpu
->isar
.mvfr0
;
1936 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1937 cpu
->isar
.mvfr0
= u
;
1939 /* Despite the name, this field covers both VFP and Neon */
1940 u
= cpu
->isar
.mvfr1
;
1941 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1942 cpu
->isar
.mvfr1
= u
;
1945 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1948 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1950 u
= cpu
->isar
.id_isar1
;
1951 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1952 cpu
->isar
.id_isar1
= u
;
1954 u
= cpu
->isar
.id_isar2
;
1955 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1956 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1957 cpu
->isar
.id_isar2
= u
;
1959 u
= cpu
->isar
.id_isar3
;
1960 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1961 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1962 cpu
->isar
.id_isar3
= u
;
1967 * We rely on no XScale CPU having VFP so we can use the same bits in the
1968 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1970 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1971 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1972 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1974 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1975 !arm_feature(env
, ARM_FEATURE_M
) &&
1976 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1977 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1982 /* For CPUs which might have tiny 1K pages, or which have an
1983 * MPU and might have small region sizes, stick with 1K pages.
1987 if (!set_preferred_target_page_bits(pagebits
)) {
1988 /* This can only ever happen for hotplugging a CPU, or if
1989 * the board code incorrectly creates a CPU which it has
1990 * promised via minimum_page_size that it will not.
1992 error_setg(errp
, "This CPU requires a smaller page size than the "
1997 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1998 * We don't support setting cluster ID ([16..23]) (known as Aff2
1999 * in later ARM ARM versions), or any of the higher affinity level fields,
2000 * so these bits always RAZ.
2002 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
2003 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
2004 ARM_DEFAULT_CPUS_PER_CLUSTER
);
2007 if (cpu
->reset_hivecs
) {
2008 cpu
->reset_sctlr
|= (1 << 13);
2012 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
2013 cpu
->reset_sctlr
|= SCTLR_EE
;
2015 cpu
->reset_sctlr
|= SCTLR_B
;
2019 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
2020 /* If the has_el3 CPU property is disabled then we need to disable the
2023 unset_feature(env
, ARM_FEATURE_EL3
);
2026 * Disable the security extension feature bits in the processor
2027 * feature registers as well.
2029 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
, ID_PFR1
, SECURITY
, 0);
2030 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPSDBG
, 0);
2031 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2032 ID_AA64PFR0
, EL3
, 0);
2034 /* Disable the realm management extension, which requires EL3. */
2035 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2036 ID_AA64PFR0
, RME
, 0);
2039 if (!cpu
->has_el2
) {
2040 unset_feature(env
, ARM_FEATURE_EL2
);
2043 if (!cpu
->has_pmu
) {
2044 unset_feature(env
, ARM_FEATURE_PMU
);
2046 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
2049 if (!kvm_enabled()) {
2050 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
2051 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
2054 #ifndef CONFIG_USER_ONLY
2055 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
2059 cpu
->isar
.id_aa64dfr0
=
2060 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
2061 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
2066 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2068 * Disable the hypervisor feature bits in the processor feature
2069 * registers if we don't have EL2.
2071 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2072 ID_AA64PFR0
, EL2
, 0);
2073 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
,
2074 ID_PFR1
, VIRTUALIZATION
, 0);
2077 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2079 * The architectural range of GM blocksize is 2-6, however qemu
2080 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2082 if (tcg_enabled()) {
2083 assert(cpu
->gm_blocksize
>= 3 && cpu
->gm_blocksize
<= 6);
2086 #ifndef CONFIG_USER_ONLY
2088 * If we do not have tag-memory provided by the machine,
2089 * reduce MTE support to instructions enabled at EL0.
2090 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2092 if (cpu
->tag_memory
== NULL
) {
2093 cpu
->isar
.id_aa64pfr1
=
2094 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 1);
2099 if (tcg_enabled()) {
2101 * Don't report some architectural features in the ID registers
2102 * where TCG does not yet implement it (not even a minimal
2103 * stub version). This avoids guests falling over when they
2104 * try to access the non-existent system registers for them.
2106 /* FEAT_SPE (Statistical Profiling Extension) */
2107 cpu
->isar
.id_aa64dfr0
=
2108 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMSVER
, 0);
2109 /* FEAT_TRBE (Trace Buffer Extension) */
2110 cpu
->isar
.id_aa64dfr0
=
2111 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEBUFFER
, 0);
2112 /* FEAT_TRF (Self-hosted Trace Extension) */
2113 cpu
->isar
.id_aa64dfr0
=
2114 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEFILT
, 0);
2116 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, TRACEFILT
, 0);
2117 /* Trace Macrocell system register access */
2118 cpu
->isar
.id_aa64dfr0
=
2119 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEVER
, 0);
2121 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPTRC
, 0);
2122 /* Memory mapped trace */
2124 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, MMAPTRC
, 0);
2125 /* FEAT_AMU (Activity Monitors Extension) */
2126 cpu
->isar
.id_aa64pfr0
=
2127 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, AMU
, 0);
2129 FIELD_DP32(cpu
->isar
.id_pfr0
, ID_PFR0
, AMU
, 0);
2130 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2131 cpu
->isar
.id_aa64pfr0
=
2132 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, MPAM
, 0);
2133 /* FEAT_NV (Nested Virtualization) */
2134 cpu
->isar
.id_aa64mmfr2
=
2135 FIELD_DP64(cpu
->isar
.id_aa64mmfr2
, ID_AA64MMFR2
, NV
, 0);
2138 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2139 * to false or by setting pmsav7-dregion to 0.
2141 if (!cpu
->has_mpu
|| cpu
->pmsav7_dregion
== 0) {
2142 cpu
->has_mpu
= false;
2143 cpu
->pmsav7_dregion
= 0;
2144 cpu
->pmsav8r_hdregion
= 0;
2147 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
2148 arm_feature(env
, ARM_FEATURE_V7
)) {
2149 uint32_t nr
= cpu
->pmsav7_dregion
;
2152 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
2157 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2159 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2160 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2161 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2162 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
2163 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
2166 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
2167 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
2168 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
2172 if (cpu
->pmsav8r_hdregion
> 0xff) {
2173 error_setg(errp
, "PMSAv8 MPU EL2 #regions invalid %" PRIu32
,
2174 cpu
->pmsav8r_hdregion
);
2178 if (cpu
->pmsav8r_hdregion
) {
2179 env
->pmsav8
.hprbar
= g_new0(uint32_t,
2180 cpu
->pmsav8r_hdregion
);
2181 env
->pmsav8
.hprlar
= g_new0(uint32_t,
2182 cpu
->pmsav8r_hdregion
);
2186 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2187 uint32_t nr
= cpu
->sau_sregion
;
2190 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
2195 env
->sau
.rbar
= g_new0(uint32_t, nr
);
2196 env
->sau
.rlar
= g_new0(uint32_t, nr
);
2200 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2201 set_feature(env
, ARM_FEATURE_VBAR
);
2204 #ifndef CONFIG_USER_ONLY
2205 if (tcg_enabled() && cpu_isar_feature(aa64_rme
, cpu
)) {
2206 arm_register_el_change_hook(cpu
, >_rme_post_el_change
, 0);
2210 register_cp_regs_for_features(cpu
);
2211 arm_cpu_register_gdb_regs_for_features(cpu
);
2213 init_cpreg_list(cpu
);
2215 #ifndef CONFIG_USER_ONLY
2216 MachineState
*ms
= MACHINE(qdev_get_machine());
2217 unsigned int smp_cpus
= ms
->smp
.cpus
;
2218 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
2221 * We must set cs->num_ases to the final value before
2222 * the first call to cpu_address_space_init.
2224 if (cpu
->tag_memory
!= NULL
) {
2225 cs
->num_ases
= 3 + has_secure
;
2227 cs
->num_ases
= 1 + has_secure
;
2231 if (!cpu
->secure_memory
) {
2232 cpu
->secure_memory
= cs
->memory
;
2234 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
2235 cpu
->secure_memory
);
2238 if (cpu
->tag_memory
!= NULL
) {
2239 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
2242 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
2243 cpu
->secure_tag_memory
);
2247 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
2249 /* No core_count specified, default to smp_cpus. */
2250 if (cpu
->core_count
== -1) {
2251 cpu
->core_count
= smp_cpus
;
2255 if (tcg_enabled()) {
2256 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
2259 * We only support DCZ blocklen that fits on one page.
2261 * Architectually this is always true. However TARGET_PAGE_SIZE
2262 * is variable and, for compatibility with -machine virt-2.7,
2263 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2264 * But even then, while the largest architectural DCZ blocklen
2265 * is 2KiB, no cpu actually uses such a large blocklen.
2267 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
2270 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2271 * both nibbles of each byte storing tag data may be written at once.
2272 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2274 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2275 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
2282 acc
->parent_realize(dev
, errp
);
2285 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
2290 const char *cpunamestr
;
2292 cpuname
= g_strsplit(cpu_model
, ",", 1);
2293 cpunamestr
= cpuname
[0];
2294 #ifdef CONFIG_USER_ONLY
2295 /* For backwards compatibility usermode emulation allows "-cpu any",
2296 * which has the same semantics as "-cpu max".
2298 if (!strcmp(cpunamestr
, "any")) {
2302 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
2303 oc
= object_class_by_name(typename
);
2304 g_strfreev(cpuname
);
2306 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
2307 object_class_is_abstract(oc
)) {
2313 static Property arm_cpu_properties
[] = {
2314 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2315 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2316 mp_affinity
, ARM64_AFFINITY_INVALID
),
2317 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2318 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2319 DEFINE_PROP_END_OF_LIST()
2322 static const gchar
*arm_gdb_arch_name(CPUState
*cs
)
2324 ARMCPU
*cpu
= ARM_CPU(cs
);
2325 CPUARMState
*env
= &cpu
->env
;
2327 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2333 #ifndef CONFIG_USER_ONLY
2334 #include "hw/core/sysemu-cpu-ops.h"
2336 static const struct SysemuCPUOps arm_sysemu_ops
= {
2337 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2338 .asidx_from_attrs
= arm_asidx_from_attrs
,
2339 .write_elf32_note
= arm_cpu_write_elf32_note
,
2340 .write_elf64_note
= arm_cpu_write_elf64_note
,
2341 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2342 .legacy_vmsd
= &vmstate_arm_cpu
,
2347 static const struct TCGCPUOps arm_tcg_ops
= {
2348 .initialize
= arm_translate_init
,
2349 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2350 .debug_excp_handler
= arm_debug_excp_handler
,
2351 .restore_state_to_opc
= arm_restore_state_to_opc
,
2353 #ifdef CONFIG_USER_ONLY
2354 .record_sigsegv
= arm_cpu_record_sigsegv
,
2355 .record_sigbus
= arm_cpu_record_sigbus
,
2357 .tlb_fill
= arm_cpu_tlb_fill
,
2358 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2359 .do_interrupt
= arm_cpu_do_interrupt
,
2360 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2361 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2362 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2363 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2364 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2365 #endif /* !CONFIG_USER_ONLY */
2367 #endif /* CONFIG_TCG */
2369 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2371 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2372 CPUClass
*cc
= CPU_CLASS(acc
);
2373 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2374 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
2376 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2377 &acc
->parent_realize
);
2379 device_class_set_props(dc
, arm_cpu_properties
);
2381 resettable_class_set_parent_phases(rc
, NULL
, arm_cpu_reset_hold
, NULL
,
2382 &acc
->parent_phases
);
2384 cc
->class_by_name
= arm_cpu_class_by_name
;
2385 cc
->has_work
= arm_cpu_has_work
;
2386 cc
->dump_state
= arm_cpu_dump_state
;
2387 cc
->set_pc
= arm_cpu_set_pc
;
2388 cc
->get_pc
= arm_cpu_get_pc
;
2389 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2390 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2391 #ifndef CONFIG_USER_ONLY
2392 cc
->sysemu_ops
= &arm_sysemu_ops
;
2394 cc
->gdb_num_core_regs
= 26;
2395 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2396 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2397 cc
->gdb_stop_before_watchpoint
= true;
2398 cc
->disas_set_info
= arm_disas_set_info
;
2401 cc
->tcg_ops
= &arm_tcg_ops
;
2402 #endif /* CONFIG_TCG */
2405 static void arm_cpu_instance_init(Object
*obj
)
2407 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2409 acc
->info
->initfn(obj
);
2410 arm_cpu_post_init(obj
);
2413 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2415 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2416 CPUClass
*cc
= CPU_CLASS(acc
);
2419 cc
->gdb_core_xml_file
= "arm-core.xml";
2422 void arm_cpu_register(const ARMCPUInfo
*info
)
2424 TypeInfo type_info
= {
2425 .parent
= TYPE_ARM_CPU
,
2426 .instance_init
= arm_cpu_instance_init
,
2427 .class_init
= info
->class_init
?: cpu_register_class_init
,
2428 .class_data
= (void *)info
,
2431 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2432 type_register(&type_info
);
2433 g_free((void *)type_info
.name
);
2436 static const TypeInfo arm_cpu_type_info
= {
2437 .name
= TYPE_ARM_CPU
,
2439 .instance_size
= sizeof(ARMCPU
),
2440 .instance_align
= __alignof__(ARMCPU
),
2441 .instance_init
= arm_cpu_initfn
,
2442 .instance_finalize
= arm_cpu_finalizefn
,
2444 .class_size
= sizeof(ARMCPUClass
),
2445 .class_init
= arm_cpu_class_init
,
2448 static void arm_cpu_register_types(void)
2450 type_register_static(&arm_cpu_type_info
);
2453 type_init(arm_cpu_register_types
)