target/arm/cpu_tcg.c

   1 /*
   2  * QEMU ARM TCG CPUs.
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This code is licensed under the GNU GPL v2 or later.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "cpu.h"
  13 #ifdef CONFIG_TCG
  14 #include "hw/core/tcg-cpu-ops.h"
  15 #endif /* CONFIG_TCG */
  16 #include "internals.h"
  17 #include "target/arm/idau.h"
  18 #if !defined(CONFIG_USER_ONLY)
  19 #include "hw/boards.h"
  20 #endif
  21 #include "cpregs.h"
  22
  23 /* CPU models. These are not needed for the AArch64 linux-user build. */
  24 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
  25
  26 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  27 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  28 {
  29     CPUClass *cc = CPU_GET_CLASS(cs);
  30     ARMCPU *cpu = ARM_CPU(cs);
  31     CPUARMState *env = &cpu->env;
  32     bool ret = false;
  33
  34     /*
  35      * ARMv7-M interrupt masking works differently than -A or -R.
  36      * There is no FIQ/IRQ distinction. Instead of I and F bits
  37      * masking FIQ and IRQ interrupts, an exception is taken only
  38      * if it is higher priority than the current execution priority
  39      * (which depends on state like BASEPRI, FAULTMASK and the
  40      * currently active exception).
  41      */
  42     if (interrupt_request & CPU_INTERRUPT_HARD
  43         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
  44         cs->exception_index = EXCP_IRQ;
  45         cc->tcg_ops->do_interrupt(cs);
  46         ret = true;
  47     }
  48     return ret;
  49 }
  50 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
  51
  52 static void arm926_initfn(Object *obj)
  53 {
  54     ARMCPU *cpu = ARM_CPU(obj);
  55
  56     cpu->dtb_compatible = "arm,arm926";
  57     set_feature(&cpu->env, ARM_FEATURE_V5);
  58     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  59     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
  60     cpu->midr = 0x41069265;
  61     cpu->reset_fpsid = 0x41011090;
  62     cpu->ctr = 0x1dd20d2;
  63     cpu->reset_sctlr = 0x00090078;
  64
  65     /*
  66      * ARMv5 does not have the ID_ISAR registers, but we can still
  67      * set the field to indicate Jazelle support within QEMU.
  68      */
  69     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
  70     /*
  71      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
  72      * support even though ARMv5 doesn't have this register.
  73      */
  74     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
  75     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
  76     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
  77 }
  78
  79 static void arm946_initfn(Object *obj)
  80 {
  81     ARMCPU *cpu = ARM_CPU(obj);
  82
  83     cpu->dtb_compatible = "arm,arm946";
  84     set_feature(&cpu->env, ARM_FEATURE_V5);
  85     set_feature(&cpu->env, ARM_FEATURE_PMSA);
  86     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  87     cpu->midr = 0x41059461;
  88     cpu->ctr = 0x0f004006;
  89     cpu->reset_sctlr = 0x00000078;
  90 }
  91
  92 static void arm1026_initfn(Object *obj)
  93 {
  94     ARMCPU *cpu = ARM_CPU(obj);
  95
  96     cpu->dtb_compatible = "arm,arm1026";
  97     set_feature(&cpu->env, ARM_FEATURE_V5);
  98     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
  99     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 100     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 101     cpu->midr = 0x4106a262;
 102     cpu->reset_fpsid = 0x410110a0;
 103     cpu->ctr = 0x1dd20d2;
 104     cpu->reset_sctlr = 0x00090078;
 105     cpu->reset_auxcr = 1;
 106
 107     /*
 108      * ARMv5 does not have the ID_ISAR registers, but we can still
 109      * set the field to indicate Jazelle support within QEMU.
 110      */
 111     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 112     /*
 113      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 114      * support even though ARMv5 doesn't have this register.
 115      */
 116     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 117     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 118     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 119
 120     {
 121         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 122         ARMCPRegInfo ifar = {
 123             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 124             .access = PL1_RW,
 125             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 126             .resetvalue = 0
 127         };
 128         define_one_arm_cp_reg(cpu, &ifar);
 129     }
 130 }
 131
 132 static void arm1136_r2_initfn(Object *obj)
 133 {
 134     ARMCPU *cpu = ARM_CPU(obj);
 135     /*
 136      * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 137      * older core than plain "arm1136". In particular this does not
 138      * have the v6K features.
 139      * These ID register values are correct for 1136 but may be wrong
 140      * for 1136_r2 (in particular r0p2 does not actually implement most
 141      * of the ID registers).
 142      */
 143
 144     cpu->dtb_compatible = "arm,arm1136";
 145     set_feature(&cpu->env, ARM_FEATURE_V6);
 146     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 147     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 148     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 149     cpu->midr = 0x4107b362;
 150     cpu->reset_fpsid = 0x410120b4;
 151     cpu->isar.mvfr0 = 0x11111111;
 152     cpu->isar.mvfr1 = 0x00000000;
 153     cpu->ctr = 0x1dd20d2;
 154     cpu->reset_sctlr = 0x00050078;
 155     cpu->isar.id_pfr0 = 0x111;
 156     cpu->isar.id_pfr1 = 0x1;
 157     cpu->isar.id_dfr0 = 0x2;
 158     cpu->id_afr0 = 0x3;
 159     cpu->isar.id_mmfr0 = 0x01130003;
 160     cpu->isar.id_mmfr1 = 0x10030302;
 161     cpu->isar.id_mmfr2 = 0x01222110;
 162     cpu->isar.id_isar0 = 0x00140011;
 163     cpu->isar.id_isar1 = 0x12002111;
 164     cpu->isar.id_isar2 = 0x11231111;
 165     cpu->isar.id_isar3 = 0x01102131;
 166     cpu->isar.id_isar4 = 0x141;
 167     cpu->reset_auxcr = 7;
 168 }
 169
 170 static void arm1136_initfn(Object *obj)
 171 {
 172     ARMCPU *cpu = ARM_CPU(obj);
 173
 174     cpu->dtb_compatible = "arm,arm1136";
 175     set_feature(&cpu->env, ARM_FEATURE_V6K);
 176     set_feature(&cpu->env, ARM_FEATURE_V6);
 177     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 178     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 179     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 180     cpu->midr = 0x4117b363;
 181     cpu->reset_fpsid = 0x410120b4;
 182     cpu->isar.mvfr0 = 0x11111111;
 183     cpu->isar.mvfr1 = 0x00000000;
 184     cpu->ctr = 0x1dd20d2;
 185     cpu->reset_sctlr = 0x00050078;
 186     cpu->isar.id_pfr0 = 0x111;
 187     cpu->isar.id_pfr1 = 0x1;
 188     cpu->isar.id_dfr0 = 0x2;
 189     cpu->id_afr0 = 0x3;
 190     cpu->isar.id_mmfr0 = 0x01130003;
 191     cpu->isar.id_mmfr1 = 0x10030302;
 192     cpu->isar.id_mmfr2 = 0x01222110;
 193     cpu->isar.id_isar0 = 0x00140011;
 194     cpu->isar.id_isar1 = 0x12002111;
 195     cpu->isar.id_isar2 = 0x11231111;
 196     cpu->isar.id_isar3 = 0x01102131;
 197     cpu->isar.id_isar4 = 0x141;
 198     cpu->reset_auxcr = 7;
 199 }
 200
 201 static void arm1176_initfn(Object *obj)
 202 {
 203     ARMCPU *cpu = ARM_CPU(obj);
 204
 205     cpu->dtb_compatible = "arm,arm1176";
 206     set_feature(&cpu->env, ARM_FEATURE_V6K);
 207     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 208     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 209     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 210     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 211     set_feature(&cpu->env, ARM_FEATURE_EL3);
 212     cpu->midr = 0x410fb767;
 213     cpu->reset_fpsid = 0x410120b5;
 214     cpu->isar.mvfr0 = 0x11111111;
 215     cpu->isar.mvfr1 = 0x00000000;
 216     cpu->ctr = 0x1dd20d2;
 217     cpu->reset_sctlr = 0x00050078;
 218     cpu->isar.id_pfr0 = 0x111;
 219     cpu->isar.id_pfr1 = 0x11;
 220     cpu->isar.id_dfr0 = 0x33;
 221     cpu->id_afr0 = 0;
 222     cpu->isar.id_mmfr0 = 0x01130003;
 223     cpu->isar.id_mmfr1 = 0x10030302;
 224     cpu->isar.id_mmfr2 = 0x01222100;
 225     cpu->isar.id_isar0 = 0x0140011;
 226     cpu->isar.id_isar1 = 0x12002111;
 227     cpu->isar.id_isar2 = 0x11231121;
 228     cpu->isar.id_isar3 = 0x01102131;
 229     cpu->isar.id_isar4 = 0x01141;
 230     cpu->reset_auxcr = 7;
 231 }
 232
 233 static void arm11mpcore_initfn(Object *obj)
 234 {
 235     ARMCPU *cpu = ARM_CPU(obj);
 236
 237     cpu->dtb_compatible = "arm,arm11mpcore";
 238     set_feature(&cpu->env, ARM_FEATURE_V6K);
 239     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 240     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 241     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 242     cpu->midr = 0x410fb022;
 243     cpu->reset_fpsid = 0x410120b4;
 244     cpu->isar.mvfr0 = 0x11111111;
 245     cpu->isar.mvfr1 = 0x00000000;
 246     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 247     cpu->isar.id_pfr0 = 0x111;
 248     cpu->isar.id_pfr1 = 0x1;
 249     cpu->isar.id_dfr0 = 0;
 250     cpu->id_afr0 = 0x2;
 251     cpu->isar.id_mmfr0 = 0x01100103;
 252     cpu->isar.id_mmfr1 = 0x10020302;
 253     cpu->isar.id_mmfr2 = 0x01222000;
 254     cpu->isar.id_isar0 = 0x00100011;
 255     cpu->isar.id_isar1 = 0x12002111;
 256     cpu->isar.id_isar2 = 0x11221011;
 257     cpu->isar.id_isar3 = 0x01102131;
 258     cpu->isar.id_isar4 = 0x141;
 259     cpu->reset_auxcr = 1;
 260 }
 261
 262 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 263     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 264       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 265     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 266       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 267 };
 268
 269 static void cortex_a8_initfn(Object *obj)
 270 {
 271     ARMCPU *cpu = ARM_CPU(obj);
 272
 273     cpu->dtb_compatible = "arm,cortex-a8";
 274     set_feature(&cpu->env, ARM_FEATURE_V7);
 275     set_feature(&cpu->env, ARM_FEATURE_NEON);
 276     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 277     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 278     set_feature(&cpu->env, ARM_FEATURE_EL3);
 279     cpu->midr = 0x410fc080;
 280     cpu->reset_fpsid = 0x410330c0;
 281     cpu->isar.mvfr0 = 0x11110222;
 282     cpu->isar.mvfr1 = 0x00011111;
 283     cpu->ctr = 0x82048004;
 284     cpu->reset_sctlr = 0x00c50078;
 285     cpu->isar.id_pfr0 = 0x1031;
 286     cpu->isar.id_pfr1 = 0x11;
 287     cpu->isar.id_dfr0 = 0x400;
 288     cpu->id_afr0 = 0;
 289     cpu->isar.id_mmfr0 = 0x31100003;
 290     cpu->isar.id_mmfr1 = 0x20000000;
 291     cpu->isar.id_mmfr2 = 0x01202000;
 292     cpu->isar.id_mmfr3 = 0x11;
 293     cpu->isar.id_isar0 = 0x00101111;
 294     cpu->isar.id_isar1 = 0x12112111;
 295     cpu->isar.id_isar2 = 0x21232031;
 296     cpu->isar.id_isar3 = 0x11112131;
 297     cpu->isar.id_isar4 = 0x00111142;
 298     cpu->isar.dbgdidr = 0x15141000;
 299     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 300     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 301     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 302     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 303     cpu->reset_auxcr = 2;
 304     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 305 }
 306
 307 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 308     /*
 309      * power_control should be set to maximum latency. Again,
 310      * default to 0 and set by private hook
 311      */
 312     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 313       .access = PL1_RW, .resetvalue = 0,
 314       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 315     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 316       .access = PL1_RW, .resetvalue = 0,
 317       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 318     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 319       .access = PL1_RW, .resetvalue = 0,
 320       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 321     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 322       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 323     /* TLB lockdown control */
 324     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 325       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 326     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 327       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 328     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 329       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 330     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 331       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 332     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 333       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 334 };
 335
 336 static void cortex_a9_initfn(Object *obj)
 337 {
 338     ARMCPU *cpu = ARM_CPU(obj);
 339
 340     cpu->dtb_compatible = "arm,cortex-a9";
 341     set_feature(&cpu->env, ARM_FEATURE_V7);
 342     set_feature(&cpu->env, ARM_FEATURE_NEON);
 343     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 344     set_feature(&cpu->env, ARM_FEATURE_EL3);
 345     /*
 346      * Note that A9 supports the MP extensions even for
 347      * A9UP and single-core A9MP (which are both different
 348      * and valid configurations; we don't model A9UP).
 349      */
 350     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 351     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 352     cpu->midr = 0x410fc090;
 353     cpu->reset_fpsid = 0x41033090;
 354     cpu->isar.mvfr0 = 0x11110222;
 355     cpu->isar.mvfr1 = 0x01111111;
 356     cpu->ctr = 0x80038003;
 357     cpu->reset_sctlr = 0x00c50078;
 358     cpu->isar.id_pfr0 = 0x1031;
 359     cpu->isar.id_pfr1 = 0x11;
 360     cpu->isar.id_dfr0 = 0x000;
 361     cpu->id_afr0 = 0;
 362     cpu->isar.id_mmfr0 = 0x00100103;
 363     cpu->isar.id_mmfr1 = 0x20000000;
 364     cpu->isar.id_mmfr2 = 0x01230000;
 365     cpu->isar.id_mmfr3 = 0x00002111;
 366     cpu->isar.id_isar0 = 0x00101111;
 367     cpu->isar.id_isar1 = 0x13112111;
 368     cpu->isar.id_isar2 = 0x21232041;
 369     cpu->isar.id_isar3 = 0x11112131;
 370     cpu->isar.id_isar4 = 0x00111142;
 371     cpu->isar.dbgdidr = 0x35141000;
 372     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 373     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 374     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 375     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 376 }
 377
 378 #ifndef CONFIG_USER_ONLY
 379 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 380 {
 381     MachineState *ms = MACHINE(qdev_get_machine());
 382
 383     /*
 384      * Linux wants the number of processors from here.
 385      * Might as well set the interrupt-controller bit too.
 386      */
 387     return ((ms->smp.cpus - 1) << 24) | (1 << 23);
 388 }
 389 #endif
 390
 391 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 392 #ifndef CONFIG_USER_ONLY
 393     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 394       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 395       .writefn = arm_cp_write_ignore, },
 396 #endif
 397     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 398       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 399 };
 400
 401 static void cortex_a7_initfn(Object *obj)
 402 {
 403     ARMCPU *cpu = ARM_CPU(obj);
 404
 405     cpu->dtb_compatible = "arm,cortex-a7";
 406     set_feature(&cpu->env, ARM_FEATURE_V7VE);
 407     set_feature(&cpu->env, ARM_FEATURE_NEON);
 408     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 409     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 410     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 411     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 412     set_feature(&cpu->env, ARM_FEATURE_EL2);
 413     set_feature(&cpu->env, ARM_FEATURE_EL3);
 414     set_feature(&cpu->env, ARM_FEATURE_PMU);
 415     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
 416     cpu->midr = 0x410fc075;
 417     cpu->reset_fpsid = 0x41023075;
 418     cpu->isar.mvfr0 = 0x10110222;
 419     cpu->isar.mvfr1 = 0x11111111;
 420     cpu->ctr = 0x84448003;
 421     cpu->reset_sctlr = 0x00c50078;
 422     cpu->isar.id_pfr0 = 0x00001131;
 423     cpu->isar.id_pfr1 = 0x00011011;
 424     cpu->isar.id_dfr0 = 0x02010555;
 425     cpu->id_afr0 = 0x00000000;
 426     cpu->isar.id_mmfr0 = 0x10101105;
 427     cpu->isar.id_mmfr1 = 0x40000000;
 428     cpu->isar.id_mmfr2 = 0x01240000;
 429     cpu->isar.id_mmfr3 = 0x02102211;
 430     /*
 431      * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
 432      * table 4-41 gives 0x02101110, which includes the arm div insns.
 433      */
 434     cpu->isar.id_isar0 = 0x02101110;
 435     cpu->isar.id_isar1 = 0x13112111;
 436     cpu->isar.id_isar2 = 0x21232041;
 437     cpu->isar.id_isar3 = 0x11112131;
 438     cpu->isar.id_isar4 = 0x10011142;
 439     cpu->isar.dbgdidr = 0x3515f005;
 440     cpu->clidr = 0x0a200023;
 441     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 442     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 443     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 444     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
 445 }
 446
 447 static void cortex_a15_initfn(Object *obj)
 448 {
 449     ARMCPU *cpu = ARM_CPU(obj);
 450
 451     cpu->dtb_compatible = "arm,cortex-a15";
 452     set_feature(&cpu->env, ARM_FEATURE_V7VE);
 453     set_feature(&cpu->env, ARM_FEATURE_NEON);
 454     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 455     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 456     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 457     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 458     set_feature(&cpu->env, ARM_FEATURE_EL2);
 459     set_feature(&cpu->env, ARM_FEATURE_EL3);
 460     set_feature(&cpu->env, ARM_FEATURE_PMU);
 461     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 462     cpu->midr = 0x412fc0f1;
 463     cpu->reset_fpsid = 0x410430f0;
 464     cpu->isar.mvfr0 = 0x10110222;
 465     cpu->isar.mvfr1 = 0x11111111;
 466     cpu->ctr = 0x8444c004;
 467     cpu->reset_sctlr = 0x00c50078;
 468     cpu->isar.id_pfr0 = 0x00001131;
 469     cpu->isar.id_pfr1 = 0x00011011;
 470     cpu->isar.id_dfr0 = 0x02010555;
 471     cpu->id_afr0 = 0x00000000;
 472     cpu->isar.id_mmfr0 = 0x10201105;
 473     cpu->isar.id_mmfr1 = 0x20000000;
 474     cpu->isar.id_mmfr2 = 0x01240000;
 475     cpu->isar.id_mmfr3 = 0x02102211;
 476     cpu->isar.id_isar0 = 0x02101110;
 477     cpu->isar.id_isar1 = 0x13112111;
 478     cpu->isar.id_isar2 = 0x21232041;
 479     cpu->isar.id_isar3 = 0x11112131;
 480     cpu->isar.id_isar4 = 0x10011142;
 481     cpu->isar.dbgdidr = 0x3515f021;
 482     cpu->clidr = 0x0a200023;
 483     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 484     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 485     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 486     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 487 }
 488
 489 static void cortex_m0_initfn(Object *obj)
 490 {
 491     ARMCPU *cpu = ARM_CPU(obj);
 492     set_feature(&cpu->env, ARM_FEATURE_V6);
 493     set_feature(&cpu->env, ARM_FEATURE_M);
 494
 495     cpu->midr = 0x410cc200;
 496
 497     /*
 498      * These ID register values are not guest visible, because
 499      * we do not implement the Main Extension. They must be set
 500      * to values corresponding to the Cortex-M0's implemented
 501      * features, because QEMU generally controls its emulation
 502      * by looking at ID register fields. We use the same values as
 503      * for the M3.
 504      */
 505     cpu->isar.id_pfr0 = 0x00000030;
 506     cpu->isar.id_pfr1 = 0x00000200;
 507     cpu->isar.id_dfr0 = 0x00100000;
 508     cpu->id_afr0 = 0x00000000;
 509     cpu->isar.id_mmfr0 = 0x00000030;
 510     cpu->isar.id_mmfr1 = 0x00000000;
 511     cpu->isar.id_mmfr2 = 0x00000000;
 512     cpu->isar.id_mmfr3 = 0x00000000;
 513     cpu->isar.id_isar0 = 0x01141110;
 514     cpu->isar.id_isar1 = 0x02111000;
 515     cpu->isar.id_isar2 = 0x21112231;
 516     cpu->isar.id_isar3 = 0x01111110;
 517     cpu->isar.id_isar4 = 0x01310102;
 518     cpu->isar.id_isar5 = 0x00000000;
 519     cpu->isar.id_isar6 = 0x00000000;
 520 }
 521
 522 static void cortex_m3_initfn(Object *obj)
 523 {
 524     ARMCPU *cpu = ARM_CPU(obj);
 525     set_feature(&cpu->env, ARM_FEATURE_V7);
 526     set_feature(&cpu->env, ARM_FEATURE_M);
 527     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 528     cpu->midr = 0x410fc231;
 529     cpu->pmsav7_dregion = 8;
 530     cpu->isar.id_pfr0 = 0x00000030;
 531     cpu->isar.id_pfr1 = 0x00000200;
 532     cpu->isar.id_dfr0 = 0x00100000;
 533     cpu->id_afr0 = 0x00000000;
 534     cpu->isar.id_mmfr0 = 0x00000030;
 535     cpu->isar.id_mmfr1 = 0x00000000;
 536     cpu->isar.id_mmfr2 = 0x00000000;
 537     cpu->isar.id_mmfr3 = 0x00000000;
 538     cpu->isar.id_isar0 = 0x01141110;
 539     cpu->isar.id_isar1 = 0x02111000;
 540     cpu->isar.id_isar2 = 0x21112231;
 541     cpu->isar.id_isar3 = 0x01111110;
 542     cpu->isar.id_isar4 = 0x01310102;
 543     cpu->isar.id_isar5 = 0x00000000;
 544     cpu->isar.id_isar6 = 0x00000000;
 545 }
 546
 547 static void cortex_m4_initfn(Object *obj)
 548 {
 549     ARMCPU *cpu = ARM_CPU(obj);
 550
 551     set_feature(&cpu->env, ARM_FEATURE_V7);
 552     set_feature(&cpu->env, ARM_FEATURE_M);
 553     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 554     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 555     cpu->midr = 0x410fc240; /* r0p0 */
 556     cpu->pmsav7_dregion = 8;
 557     cpu->isar.mvfr0 = 0x10110021;
 558     cpu->isar.mvfr1 = 0x11000011;
 559     cpu->isar.mvfr2 = 0x00000000;
 560     cpu->isar.id_pfr0 = 0x00000030;
 561     cpu->isar.id_pfr1 = 0x00000200;
 562     cpu->isar.id_dfr0 = 0x00100000;
 563     cpu->id_afr0 = 0x00000000;
 564     cpu->isar.id_mmfr0 = 0x00000030;
 565     cpu->isar.id_mmfr1 = 0x00000000;
 566     cpu->isar.id_mmfr2 = 0x00000000;
 567     cpu->isar.id_mmfr3 = 0x00000000;
 568     cpu->isar.id_isar0 = 0x01141110;
 569     cpu->isar.id_isar1 = 0x02111000;
 570     cpu->isar.id_isar2 = 0x21112231;
 571     cpu->isar.id_isar3 = 0x01111110;
 572     cpu->isar.id_isar4 = 0x01310102;
 573     cpu->isar.id_isar5 = 0x00000000;
 574     cpu->isar.id_isar6 = 0x00000000;
 575 }
 576
 577 static void cortex_m7_initfn(Object *obj)
 578 {
 579     ARMCPU *cpu = ARM_CPU(obj);
 580
 581     set_feature(&cpu->env, ARM_FEATURE_V7);
 582     set_feature(&cpu->env, ARM_FEATURE_M);
 583     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 584     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 585     cpu->midr = 0x411fc272; /* r1p2 */
 586     cpu->pmsav7_dregion = 8;
 587     cpu->isar.mvfr0 = 0x10110221;
 588     cpu->isar.mvfr1 = 0x12000011;
 589     cpu->isar.mvfr2 = 0x00000040;
 590     cpu->isar.id_pfr0 = 0x00000030;
 591     cpu->isar.id_pfr1 = 0x00000200;
 592     cpu->isar.id_dfr0 = 0x00100000;
 593     cpu->id_afr0 = 0x00000000;
 594     cpu->isar.id_mmfr0 = 0x00100030;
 595     cpu->isar.id_mmfr1 = 0x00000000;
 596     cpu->isar.id_mmfr2 = 0x01000000;
 597     cpu->isar.id_mmfr3 = 0x00000000;
 598     cpu->isar.id_isar0 = 0x01101110;
 599     cpu->isar.id_isar1 = 0x02112000;
 600     cpu->isar.id_isar2 = 0x20232231;
 601     cpu->isar.id_isar3 = 0x01111131;
 602     cpu->isar.id_isar4 = 0x01310132;
 603     cpu->isar.id_isar5 = 0x00000000;
 604     cpu->isar.id_isar6 = 0x00000000;
 605 }
 606
 607 static void cortex_m33_initfn(Object *obj)
 608 {
 609     ARMCPU *cpu = ARM_CPU(obj);
 610
 611     set_feature(&cpu->env, ARM_FEATURE_V8);
 612     set_feature(&cpu->env, ARM_FEATURE_M);
 613     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 614     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 615     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 616     cpu->midr = 0x410fd213; /* r0p3 */
 617     cpu->pmsav7_dregion = 16;
 618     cpu->sau_sregion = 8;
 619     cpu->isar.mvfr0 = 0x10110021;
 620     cpu->isar.mvfr1 = 0x11000011;
 621     cpu->isar.mvfr2 = 0x00000040;
 622     cpu->isar.id_pfr0 = 0x00000030;
 623     cpu->isar.id_pfr1 = 0x00000210;
 624     cpu->isar.id_dfr0 = 0x00200000;
 625     cpu->id_afr0 = 0x00000000;
 626     cpu->isar.id_mmfr0 = 0x00101F40;
 627     cpu->isar.id_mmfr1 = 0x00000000;
 628     cpu->isar.id_mmfr2 = 0x01000000;
 629     cpu->isar.id_mmfr3 = 0x00000000;
 630     cpu->isar.id_isar0 = 0x01101110;
 631     cpu->isar.id_isar1 = 0x02212000;
 632     cpu->isar.id_isar2 = 0x20232232;
 633     cpu->isar.id_isar3 = 0x01111131;
 634     cpu->isar.id_isar4 = 0x01310132;
 635     cpu->isar.id_isar5 = 0x00000000;
 636     cpu->isar.id_isar6 = 0x00000000;
 637     cpu->clidr = 0x00000000;
 638     cpu->ctr = 0x8000c000;
 639 }
 640
 641 static void cortex_m55_initfn(Object *obj)
 642 {
 643     ARMCPU *cpu = ARM_CPU(obj);
 644
 645     set_feature(&cpu->env, ARM_FEATURE_V8);
 646     set_feature(&cpu->env, ARM_FEATURE_V8_1M);
 647     set_feature(&cpu->env, ARM_FEATURE_M);
 648     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 649     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 650     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 651     cpu->midr = 0x410fd221; /* r0p1 */
 652     cpu->revidr = 0;
 653     cpu->pmsav7_dregion = 16;
 654     cpu->sau_sregion = 8;
 655     /* These are the MVFR* values for the FPU + full MVE configuration */
 656     cpu->isar.mvfr0 = 0x10110221;
 657     cpu->isar.mvfr1 = 0x12100211;
 658     cpu->isar.mvfr2 = 0x00000040;
 659     cpu->isar.id_pfr0 = 0x20000030;
 660     cpu->isar.id_pfr1 = 0x00000230;
 661     cpu->isar.id_dfr0 = 0x10200000;
 662     cpu->id_afr0 = 0x00000000;
 663     cpu->isar.id_mmfr0 = 0x00111040;
 664     cpu->isar.id_mmfr1 = 0x00000000;
 665     cpu->isar.id_mmfr2 = 0x01000000;
 666     cpu->isar.id_mmfr3 = 0x00000011;
 667     cpu->isar.id_isar0 = 0x01103110;
 668     cpu->isar.id_isar1 = 0x02212000;
 669     cpu->isar.id_isar2 = 0x20232232;
 670     cpu->isar.id_isar3 = 0x01111131;
 671     cpu->isar.id_isar4 = 0x01310132;
 672     cpu->isar.id_isar5 = 0x00000000;
 673     cpu->isar.id_isar6 = 0x00000000;
 674     cpu->clidr = 0x00000000; /* caches not implemented */
 675     cpu->ctr = 0x8303c003;
 676 }
 677
 678 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 679     /* Dummy the TCM region regs for the moment */
 680     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 681       .access = PL1_RW, .type = ARM_CP_CONST },
 682     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 683       .access = PL1_RW, .type = ARM_CP_CONST },
 684     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
 685       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 686 };
 687
 688 static void cortex_r5_initfn(Object *obj)
 689 {
 690     ARMCPU *cpu = ARM_CPU(obj);
 691
 692     set_feature(&cpu->env, ARM_FEATURE_V7);
 693     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 694     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 695     set_feature(&cpu->env, ARM_FEATURE_PMU);
 696     cpu->midr = 0x411fc153; /* r1p3 */
 697     cpu->isar.id_pfr0 = 0x0131;
 698     cpu->isar.id_pfr1 = 0x001;
 699     cpu->isar.id_dfr0 = 0x010400;
 700     cpu->id_afr0 = 0x0;
 701     cpu->isar.id_mmfr0 = 0x0210030;
 702     cpu->isar.id_mmfr1 = 0x00000000;
 703     cpu->isar.id_mmfr2 = 0x01200000;
 704     cpu->isar.id_mmfr3 = 0x0211;
 705     cpu->isar.id_isar0 = 0x02101111;
 706     cpu->isar.id_isar1 = 0x13112111;
 707     cpu->isar.id_isar2 = 0x21232141;
 708     cpu->isar.id_isar3 = 0x01112131;
 709     cpu->isar.id_isar4 = 0x0010142;
 710     cpu->isar.id_isar5 = 0x0;
 711     cpu->isar.id_isar6 = 0x0;
 712     cpu->mp_is_up = true;
 713     cpu->pmsav7_dregion = 16;
 714     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 715 }
 716
 717 static void cortex_r5f_initfn(Object *obj)
 718 {
 719     ARMCPU *cpu = ARM_CPU(obj);
 720
 721     cortex_r5_initfn(obj);
 722     cpu->isar.mvfr0 = 0x10110221;
 723     cpu->isar.mvfr1 = 0x00000011;
 724 }
 725
 726 static void ti925t_initfn(Object *obj)
 727 {
 728     ARMCPU *cpu = ARM_CPU(obj);
 729     set_feature(&cpu->env, ARM_FEATURE_V4T);
 730     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 731     cpu->midr = ARM_CPUID_TI925T;
 732     cpu->ctr = 0x5109149;
 733     cpu->reset_sctlr = 0x00000070;
 734 }
 735
 736 static void sa1100_initfn(Object *obj)
 737 {
 738     ARMCPU *cpu = ARM_CPU(obj);
 739
 740     cpu->dtb_compatible = "intel,sa1100";
 741     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 742     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 743     cpu->midr = 0x4401A11B;
 744     cpu->reset_sctlr = 0x00000070;
 745 }
 746
 747 static void sa1110_initfn(Object *obj)
 748 {
 749     ARMCPU *cpu = ARM_CPU(obj);
 750     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 751     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 752     cpu->midr = 0x6901B119;
 753     cpu->reset_sctlr = 0x00000070;
 754 }
 755
 756 static void pxa250_initfn(Object *obj)
 757 {
 758     ARMCPU *cpu = ARM_CPU(obj);
 759
 760     cpu->dtb_compatible = "marvell,xscale";
 761     set_feature(&cpu->env, ARM_FEATURE_V5);
 762     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 763     cpu->midr = 0x69052100;
 764     cpu->ctr = 0xd172172;
 765     cpu->reset_sctlr = 0x00000078;
 766 }
 767
 768 static void pxa255_initfn(Object *obj)
 769 {
 770     ARMCPU *cpu = ARM_CPU(obj);
 771
 772     cpu->dtb_compatible = "marvell,xscale";
 773     set_feature(&cpu->env, ARM_FEATURE_V5);
 774     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 775     cpu->midr = 0x69052d00;
 776     cpu->ctr = 0xd172172;
 777     cpu->reset_sctlr = 0x00000078;
 778 }
 779
 780 static void pxa260_initfn(Object *obj)
 781 {
 782     ARMCPU *cpu = ARM_CPU(obj);
 783
 784     cpu->dtb_compatible = "marvell,xscale";
 785     set_feature(&cpu->env, ARM_FEATURE_V5);
 786     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 787     cpu->midr = 0x69052903;
 788     cpu->ctr = 0xd172172;
 789     cpu->reset_sctlr = 0x00000078;
 790 }
 791
 792 static void pxa261_initfn(Object *obj)
 793 {
 794     ARMCPU *cpu = ARM_CPU(obj);
 795
 796     cpu->dtb_compatible = "marvell,xscale";
 797     set_feature(&cpu->env, ARM_FEATURE_V5);
 798     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 799     cpu->midr = 0x69052d05;
 800     cpu->ctr = 0xd172172;
 801     cpu->reset_sctlr = 0x00000078;
 802 }
 803
 804 static void pxa262_initfn(Object *obj)
 805 {
 806     ARMCPU *cpu = ARM_CPU(obj);
 807
 808     cpu->dtb_compatible = "marvell,xscale";
 809     set_feature(&cpu->env, ARM_FEATURE_V5);
 810     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 811     cpu->midr = 0x69052d06;
 812     cpu->ctr = 0xd172172;
 813     cpu->reset_sctlr = 0x00000078;
 814 }
 815
 816 static void pxa270a0_initfn(Object *obj)
 817 {
 818     ARMCPU *cpu = ARM_CPU(obj);
 819
 820     cpu->dtb_compatible = "marvell,xscale";
 821     set_feature(&cpu->env, ARM_FEATURE_V5);
 822     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 823     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 824     cpu->midr = 0x69054110;
 825     cpu->ctr = 0xd172172;
 826     cpu->reset_sctlr = 0x00000078;
 827 }
 828
 829 static void pxa270a1_initfn(Object *obj)
 830 {
 831     ARMCPU *cpu = ARM_CPU(obj);
 832
 833     cpu->dtb_compatible = "marvell,xscale";
 834     set_feature(&cpu->env, ARM_FEATURE_V5);
 835     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 836     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 837     cpu->midr = 0x69054111;
 838     cpu->ctr = 0xd172172;
 839     cpu->reset_sctlr = 0x00000078;
 840 }
 841
 842 static void pxa270b0_initfn(Object *obj)
 843 {
 844     ARMCPU *cpu = ARM_CPU(obj);
 845
 846     cpu->dtb_compatible = "marvell,xscale";
 847     set_feature(&cpu->env, ARM_FEATURE_V5);
 848     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 849     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 850     cpu->midr = 0x69054112;
 851     cpu->ctr = 0xd172172;
 852     cpu->reset_sctlr = 0x00000078;
 853 }
 854
 855 static void pxa270b1_initfn(Object *obj)
 856 {
 857     ARMCPU *cpu = ARM_CPU(obj);
 858
 859     cpu->dtb_compatible = "marvell,xscale";
 860     set_feature(&cpu->env, ARM_FEATURE_V5);
 861     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 862     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 863     cpu->midr = 0x69054113;
 864     cpu->ctr = 0xd172172;
 865     cpu->reset_sctlr = 0x00000078;
 866 }
 867
 868 static void pxa270c0_initfn(Object *obj)
 869 {
 870     ARMCPU *cpu = ARM_CPU(obj);
 871
 872     cpu->dtb_compatible = "marvell,xscale";
 873     set_feature(&cpu->env, ARM_FEATURE_V5);
 874     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 875     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 876     cpu->midr = 0x69054114;
 877     cpu->ctr = 0xd172172;
 878     cpu->reset_sctlr = 0x00000078;
 879 }
 880
 881 static void pxa270c5_initfn(Object *obj)
 882 {
 883     ARMCPU *cpu = ARM_CPU(obj);
 884
 885     cpu->dtb_compatible = "marvell,xscale";
 886     set_feature(&cpu->env, ARM_FEATURE_V5);
 887     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 888     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 889     cpu->midr = 0x69054117;
 890     cpu->ctr = 0xd172172;
 891     cpu->reset_sctlr = 0x00000078;
 892 }
 893
 894 #ifdef CONFIG_TCG
 895 static const struct TCGCPUOps arm_v7m_tcg_ops = {
 896     .initialize = arm_translate_init,
 897     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
 898     .debug_excp_handler = arm_debug_excp_handler,
 899
 900 #ifdef CONFIG_USER_ONLY
 901     .record_sigsegv = arm_cpu_record_sigsegv,
 902     .record_sigbus = arm_cpu_record_sigbus,
 903 #else
 904     .tlb_fill = arm_cpu_tlb_fill,
 905     .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
 906     .do_interrupt = arm_v7m_cpu_do_interrupt,
 907     .do_transaction_failed = arm_cpu_do_transaction_failed,
 908     .do_unaligned_access = arm_cpu_do_unaligned_access,
 909     .adjust_watchpoint_address = arm_adjust_watchpoint_address,
 910     .debug_check_watchpoint = arm_debug_check_watchpoint,
 911     .debug_check_breakpoint = arm_debug_check_breakpoint,
 912 #endif /* !CONFIG_USER_ONLY */
 913 };
 914 #endif /* CONFIG_TCG */
 915
 916 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 917 {
 918     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 919     CPUClass *cc = CPU_CLASS(oc);
 920
 921     acc->info = data;
 922 #ifdef CONFIG_TCG
 923     cc->tcg_ops = &arm_v7m_tcg_ops;
 924 #endif /* CONFIG_TCG */
 925
 926     cc->gdb_core_xml_file = "arm-m-profile.xml";
 927 }
 928
 929 #ifndef TARGET_AARCH64
 930 /*
 931  * -cpu max: a CPU with as many features enabled as our emulation supports.
 932  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
 933  * this only needs to handle 32 bits, and need not care about KVM.
 934  */
 935 static void arm_max_initfn(Object *obj)
 936 {
 937     ARMCPU *cpu = ARM_CPU(obj);
 938
 939     cortex_a15_initfn(obj);
 940
 941     /* old-style VFP short-vector support */
 942     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 943
 944 #ifdef CONFIG_USER_ONLY
 945     /*
 946      * We don't set these in system emulation mode for the moment,
 947      * since we don't correctly set (all of) the ID registers to
 948      * advertise them.
 949      */
 950     set_feature(&cpu->env, ARM_FEATURE_V8);
 951     {
 952         uint32_t t;
 953
 954         t = cpu->isar.id_isar5;
 955         t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 956         t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 957         t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 958         t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 959         t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 960         t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 961         cpu->isar.id_isar5 = t;
 962
 963         t = cpu->isar.id_isar6;
 964         t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 965         t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 966         t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 967         t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 968         t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 969         t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 970         t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 971         cpu->isar.id_isar6 = t;
 972
 973         t = cpu->isar.mvfr1;
 974         t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 975         t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 976         cpu->isar.mvfr1 = t;
 977
 978         t = cpu->isar.mvfr2;
 979         t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 980         t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 981         cpu->isar.mvfr2 = t;
 982
 983         t = cpu->isar.id_mmfr3;
 984         t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 985         cpu->isar.id_mmfr3 = t;
 986
 987         t = cpu->isar.id_mmfr4;
 988         t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 989         t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 990         t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 991         t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 992         cpu->isar.id_mmfr4 = t;
 993
 994         t = cpu->isar.id_pfr0;
 995         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 996         cpu->isar.id_pfr0 = t;
 997
 998         t = cpu->isar.id_pfr2;
 999         t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
1000         cpu->isar.id_pfr2 = t;
1001     }
1002 #endif /* CONFIG_USER_ONLY */
1003 }
1004 #endif /* !TARGET_AARCH64 */
1005
1006 static const ARMCPUInfo arm_tcg_cpus[] = {
1007     { .name = "arm926",      .initfn = arm926_initfn },
1008     { .name = "arm946",      .initfn = arm946_initfn },
1009     { .name = "arm1026",     .initfn = arm1026_initfn },
1010     /*
1011      * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1012      * older core than plain "arm1136". In particular this does not
1013      * have the v6K features.
1014      */
1015     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1016     { .name = "arm1136",     .initfn = arm1136_initfn },
1017     { .name = "arm1176",     .initfn = arm1176_initfn },
1018     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1019     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1020     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1021     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1022     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1023     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
1024                              .class_init = arm_v7m_class_init },
1025     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1026                              .class_init = arm_v7m_class_init },
1027     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1028                              .class_init = arm_v7m_class_init },
1029     { .name = "cortex-m7",   .initfn = cortex_m7_initfn,
1030                              .class_init = arm_v7m_class_init },
1031     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
1032                              .class_init = arm_v7m_class_init },
1033     { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
1034                              .class_init = arm_v7m_class_init },
1035     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1036     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
1037     { .name = "ti925t",      .initfn = ti925t_initfn },
1038     { .name = "sa1100",      .initfn = sa1100_initfn },
1039     { .name = "sa1110",      .initfn = sa1110_initfn },
1040     { .name = "pxa250",      .initfn = pxa250_initfn },
1041     { .name = "pxa255",      .initfn = pxa255_initfn },
1042     { .name = "pxa260",      .initfn = pxa260_initfn },
1043     { .name = "pxa261",      .initfn = pxa261_initfn },
1044     { .name = "pxa262",      .initfn = pxa262_initfn },
1045     /* "pxa270" is an alias for "pxa270-a0" */
1046     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1047     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1048     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1049     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1050     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1051     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1052     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1053 #ifndef TARGET_AARCH64
1054     { .name = "max",         .initfn = arm_max_initfn },
1055 #endif
1056 #ifdef CONFIG_USER_ONLY
1057     { .name = "any",         .initfn = arm_max_initfn },
1058 #endif
1059 };
1060
1061 static const TypeInfo idau_interface_type_info = {
1062     .name = TYPE_IDAU_INTERFACE,
1063     .parent = TYPE_INTERFACE,
1064     .class_size = sizeof(IDAUInterfaceClass),
1065 };
1066
1067 static void arm_tcg_cpu_register_types(void)
1068 {
1069     size_t i;
1070
1071     type_register_static(&idau_interface_type_info);
1072     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1073         arm_cpu_register(&arm_tcg_cpus[i]);
1074     }
1075 }
1076
1077 type_init(arm_tcg_cpu_register_types)
1078
1079 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */