4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/gdbstub.h"
23 #include "internals.h"
26 typedef struct RegisterSysregXmlParam
{
30 } RegisterSysregXmlParam
;
32 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
33 whatever the target description contains. Due to a historical mishap
34 the FPA registers appear in between core integer regs and the CPSR.
35 We hack round this by giving the FPA regs zero size when talking to a
38 int arm_cpu_gdb_read_register(CPUState
*cs
, GByteArray
*mem_buf
, int n
)
40 ARMCPU
*cpu
= ARM_CPU(cs
);
41 CPUARMState
*env
= &cpu
->env
;
44 /* Core integer register. */
45 return gdb_get_reg32(mem_buf
, env
->regs
[n
]);
52 return gdb_get_zeroes(mem_buf
, 12);
56 /* FPA status register. */
60 return gdb_get_reg32(mem_buf
, 0);
62 /* CPSR, or XPSR for M-profile */
63 if (arm_feature(env
, ARM_FEATURE_M
)) {
64 return gdb_get_reg32(mem_buf
, xpsr_read(env
));
66 return gdb_get_reg32(mem_buf
, cpsr_read(env
));
69 /* Unknown register. */
73 int arm_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
76 CPUARMState
*env
= &cpu
->env
;
82 * Mask out low bits of PC to workaround gdb bugs.
83 * This avoids an assert in thumb_tr_translate_insn, because it is
84 * architecturally impossible to misalign the pc.
85 * This will probably cause problems if we ever implement the
86 * Jazelle DBX extensions.
93 /* Core integer register. */
94 if (n
== 13 && arm_feature(env
, ARM_FEATURE_M
)) {
95 /* M profile SP low bits are always 0 */
101 if (n
< 24) { /* 16-23 */
102 /* FPA registers (ignored). */
110 /* FPA status register (ignored). */
116 /* CPSR, or XPSR for M-profile */
117 if (arm_feature(env
, ARM_FEATURE_M
)) {
119 * Don't allow writing to XPSR.Exception as it can cause
120 * a transition into or out of handler mode (it's not
121 * writable via the MSR insn so this is a reasonable
122 * restriction). Other fields are safe to update.
124 xpsr_write(env
, tmp
, ~XPSR_EXCP
);
126 cpsr_write(env
, tmp
, 0xffffffff, CPSRWriteByGDBStub
);
130 /* Unknown register. */
134 static int vfp_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
136 ARMCPU
*cpu
= env_archcpu(env
);
137 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
139 /* VFP data registers are always little-endian. */
141 return gdb_get_reg64(buf
, *aa32_vfp_dreg(env
, reg
));
143 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
144 /* Aliases for Q regs. */
147 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
148 return gdb_get_reg128(buf
, q
[0], q
[1]);
151 switch (reg
- nregs
) {
153 return gdb_get_reg32(buf
, vfp_get_fpscr(env
));
158 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
160 ARMCPU
*cpu
= env_archcpu(env
);
161 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
164 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
167 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
170 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
171 q
[0] = ldq_le_p(buf
);
172 q
[1] = ldq_le_p(buf
+ 8);
176 switch (reg
- nregs
) {
178 vfp_set_fpscr(env
, ldl_p(buf
));
184 static int vfp_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
188 return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]);
190 return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]);
195 static int vfp_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
199 env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
);
202 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30);
208 static int mve_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
212 return gdb_get_reg32(buf
, env
->v7m
.vpr
);
218 static int mve_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
222 env
->v7m
.vpr
= ldl_p(buf
);
230 * arm_get/set_gdb_*: get/set a gdb register
231 * @env: the CPU state
232 * @buf: a buffer to copy to/from
233 * @reg: register number (offset from start of group)
235 * We return the number of bytes copied
238 static int arm_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
240 ARMCPU
*cpu
= env_archcpu(env
);
241 const ARMCPRegInfo
*ri
;
244 key
= cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
[reg
];
245 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
247 if (cpreg_field_is_64bit(ri
)) {
248 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
250 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
256 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
261 static void arm_gen_one_xml_sysreg_tag(GString
*s
, DynamicGDBXMLInfo
*dyn_xml
,
262 ARMCPRegInfo
*ri
, uint32_t ri_key
,
263 int bitsize
, int regnum
)
265 g_string_append_printf(s
, "<reg name=\"%s\"", ri
->name
);
266 g_string_append_printf(s
, " bitsize=\"%d\"", bitsize
);
267 g_string_append_printf(s
, " regnum=\"%d\"", regnum
);
268 g_string_append_printf(s
, " group=\"cp_regs\"/>");
269 dyn_xml
->data
.cpregs
.keys
[dyn_xml
->num
] = ri_key
;
273 static void arm_register_sysreg_for_xml(gpointer key
, gpointer value
,
276 uint32_t ri_key
= (uintptr_t)key
;
277 ARMCPRegInfo
*ri
= value
;
278 RegisterSysregXmlParam
*param
= (RegisterSysregXmlParam
*)p
;
279 GString
*s
= param
->s
;
280 ARMCPU
*cpu
= ARM_CPU(param
->cs
);
281 CPUARMState
*env
= &cpu
->env
;
282 DynamicGDBXMLInfo
*dyn_xml
= &cpu
->dyn_sysreg_xml
;
284 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_NO_GDB
))) {
285 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
286 if (ri
->state
== ARM_CP_STATE_AA64
) {
287 arm_gen_one_xml_sysreg_tag(s
, dyn_xml
, ri
, ri_key
, 64,
291 if (ri
->state
== ARM_CP_STATE_AA32
) {
292 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
293 (ri
->secure
& ARM_CP_SECSTATE_S
)) {
296 if (ri
->type
& ARM_CP_64BIT
) {
297 arm_gen_one_xml_sysreg_tag(s
, dyn_xml
, ri
, ri_key
, 64,
300 arm_gen_one_xml_sysreg_tag(s
, dyn_xml
, ri
, ri_key
, 32,
308 static int arm_gen_dynamic_sysreg_xml(CPUState
*cs
, int base_reg
)
310 ARMCPU
*cpu
= ARM_CPU(cs
);
311 GString
*s
= g_string_new(NULL
);
312 RegisterSysregXmlParam param
= {cs
, s
, base_reg
};
314 cpu
->dyn_sysreg_xml
.num
= 0;
315 cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
= g_new(uint32_t, g_hash_table_size(cpu
->cp_regs
));
316 g_string_printf(s
, "<?xml version=\"1.0\"?>");
317 g_string_append_printf(s
, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
318 g_string_append_printf(s
, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
319 g_hash_table_foreach(cpu
->cp_regs
, arm_register_sysreg_for_xml
, ¶m
);
320 g_string_append_printf(s
, "</feature>");
321 cpu
->dyn_sysreg_xml
.desc
= g_string_free(s
, false);
322 return cpu
->dyn_sysreg_xml
.num
;
336 static const struct {
340 [M_SYSREG_MSP
] = { "msp", ARM_FEATURE_M
},
341 [M_SYSREG_PSP
] = { "psp", ARM_FEATURE_M
},
342 [M_SYSREG_PRIMASK
] = { "primask", ARM_FEATURE_M
},
343 [M_SYSREG_CONTROL
] = { "control", ARM_FEATURE_M
},
344 [M_SYSREG_BASEPRI
] = { "basepri", ARM_FEATURE_M_MAIN
},
345 [M_SYSREG_FAULTMASK
] = { "faultmask", ARM_FEATURE_M_MAIN
},
346 [M_SYSREG_MSPLIM
] = { "msplim", ARM_FEATURE_V8
},
347 [M_SYSREG_PSPLIM
] = { "psplim", ARM_FEATURE_V8
},
350 static uint32_t *m_sysreg_ptr(CPUARMState
*env
, MProfileSysreg reg
, bool sec
)
356 ptr
= arm_v7m_get_sp_ptr(env
, sec
, false, true);
359 ptr
= arm_v7m_get_sp_ptr(env
, sec
, true, true);
361 case M_SYSREG_MSPLIM
:
362 ptr
= &env
->v7m
.msplim
[sec
];
364 case M_SYSREG_PSPLIM
:
365 ptr
= &env
->v7m
.psplim
[sec
];
367 case M_SYSREG_PRIMASK
:
368 ptr
= &env
->v7m
.primask
[sec
];
370 case M_SYSREG_BASEPRI
:
371 ptr
= &env
->v7m
.basepri
[sec
];
373 case M_SYSREG_FAULTMASK
:
374 ptr
= &env
->v7m
.faultmask
[sec
];
376 case M_SYSREG_CONTROL
:
377 ptr
= &env
->v7m
.control
[sec
];
382 return arm_feature(env
, m_sysreg_def
[reg
].feature
) ? ptr
: NULL
;
385 static int m_sysreg_get(CPUARMState
*env
, GByteArray
*buf
,
386 MProfileSysreg reg
, bool secure
)
388 uint32_t *ptr
= m_sysreg_ptr(env
, reg
, secure
);
393 return gdb_get_reg32(buf
, *ptr
);
396 static int arm_gdb_get_m_systemreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
399 * Here, we emulate MRS instruction, where CONTROL has a mix of
400 * banked and non-banked bits.
402 if (reg
== M_SYSREG_CONTROL
) {
403 return gdb_get_reg32(buf
, arm_v7m_mrs_control(env
, env
->v7m
.secure
));
405 return m_sysreg_get(env
, buf
, reg
, env
->v7m
.secure
);
408 static int arm_gdb_set_m_systemreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
413 static int arm_gen_dynamic_m_systemreg_xml(CPUState
*cs
, int orig_base_reg
)
415 ARMCPU
*cpu
= ARM_CPU(cs
);
416 CPUARMState
*env
= &cpu
->env
;
417 GString
*s
= g_string_new(NULL
);
418 int base_reg
= orig_base_reg
;
421 g_string_printf(s
, "<?xml version=\"1.0\"?>");
422 g_string_append_printf(s
, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
423 g_string_append_printf(s
, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
425 for (i
= 0; i
< ARRAY_SIZE(m_sysreg_def
); i
++) {
426 if (arm_feature(env
, m_sysreg_def
[i
].feature
)) {
427 g_string_append_printf(s
,
428 "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
429 m_sysreg_def
[i
].name
, base_reg
++);
433 g_string_append_printf(s
, "</feature>");
434 cpu
->dyn_m_systemreg_xml
.desc
= g_string_free(s
, false);
435 cpu
->dyn_m_systemreg_xml
.num
= base_reg
- orig_base_reg
;
437 return cpu
->dyn_m_systemreg_xml
.num
;
440 #ifndef CONFIG_USER_ONLY
442 * For user-only, we see the non-secure registers via m_systemreg above.
443 * For secext, encode the non-secure view as even and secure view as odd.
445 static int arm_gdb_get_m_secextreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
447 return m_sysreg_get(env
, buf
, reg
>> 1, reg
& 1);
450 static int arm_gdb_set_m_secextreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
455 static int arm_gen_dynamic_m_secextreg_xml(CPUState
*cs
, int orig_base_reg
)
457 ARMCPU
*cpu
= ARM_CPU(cs
);
458 GString
*s
= g_string_new(NULL
);
459 int base_reg
= orig_base_reg
;
462 g_string_printf(s
, "<?xml version=\"1.0\"?>");
463 g_string_append_printf(s
, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
464 g_string_append_printf(s
, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
466 for (i
= 0; i
< ARRAY_SIZE(m_sysreg_def
); i
++) {
467 g_string_append_printf(s
,
468 "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
469 m_sysreg_def
[i
].name
, base_reg
++);
470 g_string_append_printf(s
,
471 "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
472 m_sysreg_def
[i
].name
, base_reg
++);
475 g_string_append_printf(s
, "</feature>");
476 cpu
->dyn_m_secextreg_xml
.desc
= g_string_free(s
, false);
477 cpu
->dyn_m_secextreg_xml
.num
= base_reg
- orig_base_reg
;
479 return cpu
->dyn_m_secextreg_xml
.num
;
483 const char *arm_gdb_get_dynamic_xml(CPUState
*cs
, const char *xmlname
)
485 ARMCPU
*cpu
= ARM_CPU(cs
);
487 if (strcmp(xmlname
, "system-registers.xml") == 0) {
488 return cpu
->dyn_sysreg_xml
.desc
;
489 } else if (strcmp(xmlname
, "sve-registers.xml") == 0) {
490 return cpu
->dyn_svereg_xml
.desc
;
491 } else if (strcmp(xmlname
, "arm-m-system.xml") == 0) {
492 return cpu
->dyn_m_systemreg_xml
.desc
;
493 #ifndef CONFIG_USER_ONLY
494 } else if (strcmp(xmlname
, "arm-m-secext.xml") == 0) {
495 return cpu
->dyn_m_secextreg_xml
.desc
;
501 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
503 CPUState
*cs
= CPU(cpu
);
504 CPUARMState
*env
= &cpu
->env
;
506 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
508 * The lower part of each SVE register aliases to the FPU
509 * registers so we don't need to include both.
511 #ifdef TARGET_AARCH64
512 if (isar_feature_aa64_sve(&cpu
->isar
)) {
513 int nreg
= arm_gen_dynamic_svereg_xml(cs
, cs
->gdb_num_regs
);
514 gdb_register_coprocessor(cs
, aarch64_gdb_get_sve_reg
,
515 aarch64_gdb_set_sve_reg
, nreg
,
516 "sve-registers.xml", 0);
518 gdb_register_coprocessor(cs
, aarch64_gdb_get_fpu_reg
,
519 aarch64_gdb_set_fpu_reg
,
520 34, "aarch64-fpu.xml", 0);
522 if (isar_feature_aa64_pauth(&cpu
->isar
)) {
523 gdb_register_coprocessor(cs
, aarch64_gdb_get_pauth_reg
,
524 aarch64_gdb_set_pauth_reg
,
525 4, "aarch64-pauth.xml", 0);
529 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
530 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
531 49, "arm-neon.xml", 0);
532 } else if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
533 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
534 33, "arm-vfp3.xml", 0);
535 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
536 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
537 17, "arm-vfp.xml", 0);
539 if (!arm_feature(env
, ARM_FEATURE_M
)) {
541 * A and R profile have FP sysregs FPEXC and FPSID that we
544 gdb_register_coprocessor(cs
, vfp_gdb_get_sysreg
, vfp_gdb_set_sysreg
,
545 2, "arm-vfp-sysregs.xml", 0);
548 if (cpu_isar_feature(aa32_mve
, cpu
)) {
549 gdb_register_coprocessor(cs
, mve_gdb_get_reg
, mve_gdb_set_reg
,
550 1, "arm-m-profile-mve.xml", 0);
552 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
553 arm_gen_dynamic_sysreg_xml(cs
, cs
->gdb_num_regs
),
554 "system-registers.xml", 0);
556 if (arm_feature(env
, ARM_FEATURE_M
)) {
557 gdb_register_coprocessor(cs
,
558 arm_gdb_get_m_systemreg
, arm_gdb_set_m_systemreg
,
559 arm_gen_dynamic_m_systemreg_xml(cs
, cs
->gdb_num_regs
),
560 "arm-m-system.xml", 0);
561 #ifndef CONFIG_USER_ONLY
562 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
563 gdb_register_coprocessor(cs
,
564 arm_gdb_get_m_secextreg
, arm_gdb_set_m_secextreg
,
565 arm_gen_dynamic_m_secextreg_xml(cs
, cs
->gdb_num_regs
),
566 "arm-m-secext.xml", 0);