4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
12 #include "target/arm/idau.h"
15 #include "internals.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/timer.h"
20 #include "qemu/bitops.h"
21 #include "qemu/crc32c.h"
22 #include "qemu/qemu-print.h"
23 #include "exec/exec-all.h"
24 #include <zlib.h> /* For crc32 */
26 #include "semihosting/semihost.h"
27 #include "sysemu/cpus.h"
28 #include "sysemu/cpu-timers.h"
29 #include "sysemu/kvm.h"
30 #include "qemu/range.h"
31 #include "qapi/qapi-commands-machine-target.h"
32 #include "qapi/error.h"
33 #include "qemu/guest-random.h"
36 #include "exec/cpu_ldst.h"
37 #include "semihosting/common-semi.h"
41 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
42 #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
44 #ifndef CONFIG_USER_ONLY
46 static bool get_phys_addr_lpae(CPUARMState
*env
, uint64_t address
,
47 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
49 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
50 target_ulong
*page_size_ptr
,
51 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
52 __attribute__((nonnull
));
55 static void switch_mode(CPUARMState
*env
, int mode
);
56 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
);
58 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 assert(ri
->fieldoffset
);
61 if (cpreg_field_is_64bit(ri
)) {
62 return CPREG_FIELD64(env
, ri
);
64 return CPREG_FIELD32(env
, ri
);
68 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
71 assert(ri
->fieldoffset
);
72 if (cpreg_field_is_64bit(ri
)) {
73 CPREG_FIELD64(env
, ri
) = value
;
75 CPREG_FIELD32(env
, ri
) = value
;
79 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
81 return (char *)env
+ ri
->fieldoffset
;
84 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
86 /* Raw read of a coprocessor register (as needed for migration, etc). */
87 if (ri
->type
& ARM_CP_CONST
) {
88 return ri
->resetvalue
;
89 } else if (ri
->raw_readfn
) {
90 return ri
->raw_readfn(env
, ri
);
91 } else if (ri
->readfn
) {
92 return ri
->readfn(env
, ri
);
94 return raw_read(env
, ri
);
98 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
101 /* Raw write of a coprocessor register (as needed for migration, etc).
102 * Note that constant registers are treated as write-ignored; the
103 * caller should check for success by whether a readback gives the
106 if (ri
->type
& ARM_CP_CONST
) {
108 } else if (ri
->raw_writefn
) {
109 ri
->raw_writefn(env
, ri
, v
);
110 } else if (ri
->writefn
) {
111 ri
->writefn(env
, ri
, v
);
113 raw_write(env
, ri
, v
);
117 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
119 /* Return true if the regdef would cause an assertion if you called
120 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
121 * program bug for it not to have the NO_RAW flag).
122 * NB that returning false here doesn't necessarily mean that calling
123 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
124 * read/write access functions which are safe for raw use" from "has
125 * read/write access functions which have side effects but has forgotten
126 * to provide raw access functions".
127 * The tests here line up with the conditions in read/write_raw_cp_reg()
128 * and assertions in raw_read()/raw_write().
130 if ((ri
->type
& ARM_CP_CONST
) ||
132 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
138 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
140 /* Write the coprocessor state from cpu->env to the (index,value) list. */
144 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
145 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
146 const ARMCPRegInfo
*ri
;
149 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
154 if (ri
->type
& ARM_CP_NO_RAW
) {
158 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
161 * Only sync if the previous list->cpustate sync succeeded.
162 * Rather than tracking the success/failure state for every
163 * item in the list, we just recheck "does the raw write we must
164 * have made in write_list_to_cpustate() read back OK" here.
166 uint64_t oldval
= cpu
->cpreg_values
[i
];
168 if (oldval
== newval
) {
172 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
173 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
177 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
179 cpu
->cpreg_values
[i
] = newval
;
184 bool write_list_to_cpustate(ARMCPU
*cpu
)
189 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
190 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
191 uint64_t v
= cpu
->cpreg_values
[i
];
192 const ARMCPRegInfo
*ri
;
194 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
199 if (ri
->type
& ARM_CP_NO_RAW
) {
202 /* Write value and confirm it reads back as written
203 * (to catch read-only registers and partially read-only
204 * registers where the incoming migration value doesn't match)
206 write_raw_cp_reg(&cpu
->env
, ri
, v
);
207 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
214 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
216 ARMCPU
*cpu
= opaque
;
217 uint32_t regidx
= (uintptr_t)key
;
218 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
220 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
221 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
222 /* The value array need not be initialized at this point */
223 cpu
->cpreg_array_len
++;
227 static void count_cpreg(gpointer key
, gpointer opaque
)
229 ARMCPU
*cpu
= opaque
;
230 const ARMCPRegInfo
*ri
;
232 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
234 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
235 cpu
->cpreg_array_len
++;
239 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
241 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
242 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
253 void init_cpreg_list(ARMCPU
*cpu
)
255 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
256 * Note that we require cpreg_tuples[] to be sorted by key ID.
261 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
262 keys
= g_list_sort(keys
, cpreg_key_compare
);
264 cpu
->cpreg_array_len
= 0;
266 g_list_foreach(keys
, count_cpreg
, cpu
);
268 arraylen
= cpu
->cpreg_array_len
;
269 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
270 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
271 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
272 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
273 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
274 cpu
->cpreg_array_len
= 0;
276 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
278 assert(cpu
->cpreg_array_len
== arraylen
);
284 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
286 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
287 const ARMCPRegInfo
*ri
,
290 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
291 arm_is_secure_below_el3(env
)) {
292 return CP_ACCESS_TRAP_UNCATEGORIZED
;
297 /* Some secure-only AArch32 registers trap to EL3 if used from
298 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
299 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
300 * We assume that the .access field is set to PL1_RW.
302 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
303 const ARMCPRegInfo
*ri
,
306 if (arm_current_el(env
) == 3) {
309 if (arm_is_secure_below_el3(env
)) {
310 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
311 return CP_ACCESS_TRAP_EL2
;
313 return CP_ACCESS_TRAP_EL3
;
315 /* This will be EL1 NS and EL2 NS, which just UNDEF */
316 return CP_ACCESS_TRAP_UNCATEGORIZED
;
319 static uint64_t arm_mdcr_el2_eff(CPUARMState
*env
)
321 return arm_is_el2_enabled(env
) ? env
->cp15
.mdcr_el2
: 0;
324 /* Check for traps to "powerdown debug" registers, which are controlled
327 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
330 int el
= arm_current_el(env
);
331 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
332 bool mdcr_el2_tdosa
= (mdcr_el2
& MDCR_TDOSA
) || (mdcr_el2
& MDCR_TDE
) ||
333 (arm_hcr_el2_eff(env
) & HCR_TGE
);
335 if (el
< 2 && mdcr_el2_tdosa
) {
336 return CP_ACCESS_TRAP_EL2
;
338 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
339 return CP_ACCESS_TRAP_EL3
;
344 /* Check for traps to "debug ROM" registers, which are controlled
345 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
347 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
350 int el
= arm_current_el(env
);
351 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
352 bool mdcr_el2_tdra
= (mdcr_el2
& MDCR_TDRA
) || (mdcr_el2
& MDCR_TDE
) ||
353 (arm_hcr_el2_eff(env
) & HCR_TGE
);
355 if (el
< 2 && mdcr_el2_tdra
) {
356 return CP_ACCESS_TRAP_EL2
;
358 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
359 return CP_ACCESS_TRAP_EL3
;
364 /* Check for traps to general debug registers, which are controlled
365 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
367 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
370 int el
= arm_current_el(env
);
371 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
372 bool mdcr_el2_tda
= (mdcr_el2
& MDCR_TDA
) || (mdcr_el2
& MDCR_TDE
) ||
373 (arm_hcr_el2_eff(env
) & HCR_TGE
);
375 if (el
< 2 && mdcr_el2_tda
) {
376 return CP_ACCESS_TRAP_EL2
;
378 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
379 return CP_ACCESS_TRAP_EL3
;
384 /* Check for traps to performance monitor registers, which are controlled
385 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
387 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
390 int el
= arm_current_el(env
);
391 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
393 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
394 return CP_ACCESS_TRAP_EL2
;
396 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
397 return CP_ACCESS_TRAP_EL3
;
402 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
403 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
406 if (arm_current_el(env
) == 1) {
407 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
408 if (arm_hcr_el2_eff(env
) & trap
) {
409 return CP_ACCESS_TRAP_EL2
;
415 /* Check for traps from EL1 due to HCR_EL2.TSW. */
416 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
419 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
420 return CP_ACCESS_TRAP_EL2
;
425 /* Check for traps from EL1 due to HCR_EL2.TACR. */
426 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
429 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
430 return CP_ACCESS_TRAP_EL2
;
435 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
436 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
439 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
440 return CP_ACCESS_TRAP_EL2
;
445 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
447 ARMCPU
*cpu
= env_archcpu(env
);
449 raw_write(env
, ri
, value
);
450 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
453 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
455 ARMCPU
*cpu
= env_archcpu(env
);
457 if (raw_read(env
, ri
) != value
) {
458 /* Unlike real hardware the qemu TLB uses virtual addresses,
459 * not modified virtual addresses, so this causes a TLB flush.
462 raw_write(env
, ri
, value
);
466 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
469 ARMCPU
*cpu
= env_archcpu(env
);
471 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
472 && !extended_addresses_enabled(env
)) {
473 /* For VMSA (when not using the LPAE long descriptor page table
474 * format) this register includes the ASID, so do a TLB flush.
475 * For PMSA it is purely a process ID and no action is needed.
479 raw_write(env
, ri
, value
);
482 /* IS variants of TLB operations must affect all cores */
483 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
486 CPUState
*cs
= env_cpu(env
);
488 tlb_flush_all_cpus_synced(cs
);
491 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
494 CPUState
*cs
= env_cpu(env
);
496 tlb_flush_all_cpus_synced(cs
);
499 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 CPUState
*cs
= env_cpu(env
);
504 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
507 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
510 CPUState
*cs
= env_cpu(env
);
512 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
516 * Non-IS variants of TLB operations are upgraded to
517 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
518 * force broadcast of these operations.
520 static bool tlb_force_broadcast(CPUARMState
*env
)
522 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
525 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate all (TLBIALL) */
529 CPUState
*cs
= env_cpu(env
);
531 if (tlb_force_broadcast(env
)) {
532 tlb_flush_all_cpus_synced(cs
);
538 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
542 CPUState
*cs
= env_cpu(env
);
544 value
&= TARGET_PAGE_MASK
;
545 if (tlb_force_broadcast(env
)) {
546 tlb_flush_page_all_cpus_synced(cs
, value
);
548 tlb_flush_page(cs
, value
);
552 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
555 /* Invalidate by ASID (TLBIASID) */
556 CPUState
*cs
= env_cpu(env
);
558 if (tlb_force_broadcast(env
)) {
559 tlb_flush_all_cpus_synced(cs
);
565 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
569 CPUState
*cs
= env_cpu(env
);
571 value
&= TARGET_PAGE_MASK
;
572 if (tlb_force_broadcast(env
)) {
573 tlb_flush_page_all_cpus_synced(cs
, value
);
575 tlb_flush_page(cs
, value
);
579 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
582 CPUState
*cs
= env_cpu(env
);
584 tlb_flush_by_mmuidx(cs
,
586 ARMMMUIdxBit_E10_1_PAN
|
590 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
593 CPUState
*cs
= env_cpu(env
);
595 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
597 ARMMMUIdxBit_E10_1_PAN
|
602 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
605 CPUState
*cs
= env_cpu(env
);
607 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
610 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
613 CPUState
*cs
= env_cpu(env
);
615 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
618 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
621 CPUState
*cs
= env_cpu(env
);
622 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
624 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
627 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
630 CPUState
*cs
= env_cpu(env
);
631 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
633 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
637 static const ARMCPRegInfo cp_reginfo
[] = {
638 /* Define the secure and non-secure FCSE identifier CP registers
639 * separately because there is no secure bank in V8 (no _EL3). This allows
640 * the secure register to be properly reset and migrated. There is also no
641 * v8 EL1 version of the register so the non-secure instance stands alone.
644 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
645 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
646 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
647 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
648 { .name
= "FCSEIDR_S",
649 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
650 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
651 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
652 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
653 /* Define the secure and non-secure context identifier CP registers
654 * separately because there is no secure bank in V8 (no _EL3). This allows
655 * the secure register to be properly reset and migrated. In the
656 * non-secure case, the 32-bit register will have reset and migration
657 * disabled during registration as it is handled by the 64-bit instance.
659 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
660 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
661 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
662 .secure
= ARM_CP_SECSTATE_NS
,
663 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
664 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
665 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
666 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
667 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
668 .secure
= ARM_CP_SECSTATE_S
,
669 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
670 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
673 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
674 /* NB: Some of these registers exist in v8 but with more precise
675 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
677 /* MMU Domain access control / MPU write buffer control */
679 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
680 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
681 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
682 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
683 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
684 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
685 * For v6 and v5, these mappings are overly broad.
687 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
688 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
689 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
690 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
691 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
692 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
693 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
694 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
695 /* Cache maintenance ops; some of this space may be overridden later. */
696 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
697 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
698 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
701 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
702 /* Not all pre-v6 cores implemented this WFI, so this is slightly
705 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
706 .access
= PL1_W
, .type
= ARM_CP_WFI
},
709 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
710 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
711 * is UNPREDICTABLE; we choose to NOP as most implementations do).
713 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
714 .access
= PL1_W
, .type
= ARM_CP_WFI
},
715 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
716 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
717 * OMAPCP will override this space.
719 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
720 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
722 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
723 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
725 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
726 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
727 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
729 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
730 * implementing it as RAZ means the "debug architecture version" bits
731 * will read as a reserved value, which should cause Linux to not try
732 * to use the debug hardware.
734 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
735 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
736 /* MMU TLB control. Note that the wildcarding means we cover not just
737 * the unified TLB ops but also the dside/iside/inner-shareable variants.
739 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
740 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
741 .type
= ARM_CP_NO_RAW
},
742 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
743 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
744 .type
= ARM_CP_NO_RAW
},
745 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
746 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
747 .type
= ARM_CP_NO_RAW
},
748 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
749 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
750 .type
= ARM_CP_NO_RAW
},
751 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
752 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
753 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
754 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
757 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
762 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
763 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
764 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
765 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
766 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
768 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
769 /* VFP coprocessor: cp10 & cp11 [23:20] */
770 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
772 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
773 /* ASEDIS [31] bit is RAO/WI */
777 /* VFPv3 and upwards with NEON implement 32 double precision
778 * registers (D0-D31).
780 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
781 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
789 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
790 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
792 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
793 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
794 value
&= ~(0xf << 20);
795 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
798 env
->cp15
.cpacr_el1
= value
;
801 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
804 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
805 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
807 uint64_t value
= env
->cp15
.cpacr_el1
;
809 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
810 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
811 value
&= ~(0xf << 20);
817 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
819 /* Call cpacr_write() so that we reset with the correct RAO bits set
820 * for our CPU features.
822 cpacr_write(env
, ri
, 0);
825 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
828 if (arm_feature(env
, ARM_FEATURE_V8
)) {
829 /* Check if CPACR accesses are to be trapped to EL2 */
830 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
831 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
)) {
832 return CP_ACCESS_TRAP_EL2
;
833 /* Check if CPACR accesses are to be trapped to EL3 */
834 } else if (arm_current_el(env
) < 3 &&
835 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
836 return CP_ACCESS_TRAP_EL3
;
843 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
846 /* Check if CPTR accesses are set to trap to EL3 */
847 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
848 return CP_ACCESS_TRAP_EL3
;
854 static const ARMCPRegInfo v6_cp_reginfo
[] = {
855 /* prefetch by MVA in v6, NOP in v7 */
856 { .name
= "MVA_prefetch",
857 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
858 .access
= PL1_W
, .type
= ARM_CP_NOP
},
859 /* We need to break the TB after ISB to execute self-modifying code
860 * correctly and also to take any pending interrupts immediately.
861 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
863 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
864 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
865 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
866 .access
= PL0_W
, .type
= ARM_CP_NOP
},
867 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
868 .access
= PL0_W
, .type
= ARM_CP_NOP
},
869 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
870 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
871 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
872 offsetof(CPUARMState
, cp15
.ifar_ns
) },
874 /* Watchpoint Fault Address Register : should actually only be present
875 * for 1136, 1176, 11MPCore.
877 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
878 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
879 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
880 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
881 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
882 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
885 typedef struct pm_event
{
886 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
887 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
888 bool (*supported
)(CPUARMState
*);
890 * Retrieve the current count of the underlying event. The programmed
891 * counters hold a difference from the return value from this function
893 uint64_t (*get_count
)(CPUARMState
*);
895 * Return how many nanoseconds it will take (at a minimum) for count events
896 * to occur. A negative value indicates the counter will never overflow, or
897 * that the counter has otherwise arranged for the overflow bit to be set
898 * and the PMU interrupt to be raised on overflow.
900 int64_t (*ns_per_count
)(uint64_t);
903 static bool event_always_supported(CPUARMState
*env
)
908 static uint64_t swinc_get_count(CPUARMState
*env
)
911 * SW_INCR events are written directly to the pmevcntr's by writes to
912 * PMSWINC, so there is no underlying count maintained by the PMU itself
917 static int64_t swinc_ns_per(uint64_t ignored
)
923 * Return the underlying cycle count for the PMU cycle counters. If we're in
924 * usermode, simply return 0.
926 static uint64_t cycles_get_count(CPUARMState
*env
)
928 #ifndef CONFIG_USER_ONLY
929 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
930 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
932 return cpu_get_host_ticks();
936 #ifndef CONFIG_USER_ONLY
937 static int64_t cycles_ns_per(uint64_t cycles
)
939 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
942 static bool instructions_supported(CPUARMState
*env
)
944 return icount_enabled() == 1; /* Precise instruction counting */
947 static uint64_t instructions_get_count(CPUARMState
*env
)
949 return (uint64_t)icount_get_raw();
952 static int64_t instructions_ns_per(uint64_t icount
)
954 return icount_to_ns((int64_t)icount
);
958 static bool pmu_8_1_events_supported(CPUARMState
*env
)
960 /* For events which are supported in any v8.1 PMU */
961 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
964 static bool pmu_8_4_events_supported(CPUARMState
*env
)
966 /* For events which are supported in any v8.1 PMU */
967 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
970 static uint64_t zero_event_get_count(CPUARMState
*env
)
972 /* For events which on QEMU never fire, so their count is always zero */
976 static int64_t zero_event_ns_per(uint64_t cycles
)
978 /* An event which never fires can never overflow */
982 static const pm_event pm_events
[] = {
983 { .number
= 0x000, /* SW_INCR */
984 .supported
= event_always_supported
,
985 .get_count
= swinc_get_count
,
986 .ns_per_count
= swinc_ns_per
,
988 #ifndef CONFIG_USER_ONLY
989 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
990 .supported
= instructions_supported
,
991 .get_count
= instructions_get_count
,
992 .ns_per_count
= instructions_ns_per
,
994 { .number
= 0x011, /* CPU_CYCLES, Cycle */
995 .supported
= event_always_supported
,
996 .get_count
= cycles_get_count
,
997 .ns_per_count
= cycles_ns_per
,
1000 { .number
= 0x023, /* STALL_FRONTEND */
1001 .supported
= pmu_8_1_events_supported
,
1002 .get_count
= zero_event_get_count
,
1003 .ns_per_count
= zero_event_ns_per
,
1005 { .number
= 0x024, /* STALL_BACKEND */
1006 .supported
= pmu_8_1_events_supported
,
1007 .get_count
= zero_event_get_count
,
1008 .ns_per_count
= zero_event_ns_per
,
1010 { .number
= 0x03c, /* STALL */
1011 .supported
= pmu_8_4_events_supported
,
1012 .get_count
= zero_event_get_count
,
1013 .ns_per_count
= zero_event_ns_per
,
1018 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1019 * events (i.e. the statistical profiling extension), this implementation
1020 * should first be updated to something sparse instead of the current
1021 * supported_event_map[] array.
1023 #define MAX_EVENT_ID 0x3c
1024 #define UNSUPPORTED_EVENT UINT16_MAX
1025 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1028 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1029 * of ARM event numbers to indices in our pm_events array.
1031 * Note: Events in the 0x40XX range are not currently supported.
1033 void pmu_init(ARMCPU
*cpu
)
1038 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1041 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1042 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1047 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1048 const pm_event
*cnt
= &pm_events
[i
];
1049 assert(cnt
->number
<= MAX_EVENT_ID
);
1050 /* We do not currently support events in the 0x40xx range */
1051 assert(cnt
->number
<= 0x3f);
1053 if (cnt
->supported(&cpu
->env
)) {
1054 supported_event_map
[cnt
->number
] = i
;
1055 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1056 if (cnt
->number
& 0x20) {
1057 cpu
->pmceid1
|= event_mask
;
1059 cpu
->pmceid0
|= event_mask
;
1066 * Check at runtime whether a PMU event is supported for the current machine
1068 static bool event_supported(uint16_t number
)
1070 if (number
> MAX_EVENT_ID
) {
1073 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1076 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1079 /* Performance monitor registers user accessibility is controlled
1080 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1081 * trapping to EL2 or EL3 for other accesses.
1083 int el
= arm_current_el(env
);
1084 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1086 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1087 return CP_ACCESS_TRAP
;
1089 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1090 return CP_ACCESS_TRAP_EL2
;
1092 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1093 return CP_ACCESS_TRAP_EL3
;
1096 return CP_ACCESS_OK
;
1099 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1100 const ARMCPRegInfo
*ri
,
1103 /* ER: event counter read trap control */
1104 if (arm_feature(env
, ARM_FEATURE_V8
)
1105 && arm_current_el(env
) == 0
1106 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1108 return CP_ACCESS_OK
;
1111 return pmreg_access(env
, ri
, isread
);
1114 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1115 const ARMCPRegInfo
*ri
,
1118 /* SW: software increment write trap control */
1119 if (arm_feature(env
, ARM_FEATURE_V8
)
1120 && arm_current_el(env
) == 0
1121 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1123 return CP_ACCESS_OK
;
1126 return pmreg_access(env
, ri
, isread
);
1129 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1130 const ARMCPRegInfo
*ri
,
1133 /* ER: event counter read trap control */
1134 if (arm_feature(env
, ARM_FEATURE_V8
)
1135 && arm_current_el(env
) == 0
1136 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1137 return CP_ACCESS_OK
;
1140 return pmreg_access(env
, ri
, isread
);
1143 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1144 const ARMCPRegInfo
*ri
,
1147 /* CR: cycle counter read trap control */
1148 if (arm_feature(env
, ARM_FEATURE_V8
)
1149 && arm_current_el(env
) == 0
1150 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1152 return CP_ACCESS_OK
;
1155 return pmreg_access(env
, ri
, isread
);
1158 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1159 * the current EL, security state, and register configuration.
1161 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1164 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1165 bool enabled
, prohibited
, filtered
;
1166 bool secure
= arm_is_secure(env
);
1167 int el
= arm_current_el(env
);
1168 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1169 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1171 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1175 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1176 (counter
< hpmn
|| counter
== 31)) {
1177 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1179 e
= mdcr_el2
& MDCR_HPME
;
1181 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1184 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1185 prohibited
= mdcr_el2
& MDCR_HPMD
;
1190 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1191 !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1194 if (prohibited
&& counter
== 31) {
1195 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1198 if (counter
== 31) {
1199 filter
= env
->cp15
.pmccfiltr_el0
;
1201 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1204 p
= filter
& PMXEVTYPER_P
;
1205 u
= filter
& PMXEVTYPER_U
;
1206 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1207 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1208 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1209 m
= arm_el_is_aa64(env
, 1) &&
1210 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1213 filtered
= secure
? u
: u
!= nsu
;
1214 } else if (el
== 1) {
1215 filtered
= secure
? p
: p
!= nsk
;
1216 } else if (el
== 2) {
1222 if (counter
!= 31) {
1224 * If not checking PMCCNTR, ensure the counter is setup to an event we
1227 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1228 if (!event_supported(event
)) {
1233 return enabled
&& !prohibited
&& !filtered
;
1236 static void pmu_update_irq(CPUARMState
*env
)
1238 ARMCPU
*cpu
= env_archcpu(env
);
1239 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1240 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1244 * Ensure c15_ccnt is the guest-visible count so that operations such as
1245 * enabling/disabling the counter or filtering, modifying the count itself,
1246 * etc. can be done logically. This is essentially a no-op if the counter is
1247 * not enabled at the time of the call.
1249 static void pmccntr_op_start(CPUARMState
*env
)
1251 uint64_t cycles
= cycles_get_count(env
);
1253 if (pmu_counter_enabled(env
, 31)) {
1254 uint64_t eff_cycles
= cycles
;
1255 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1256 /* Increment once every 64 processor clock cycles */
1260 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1262 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1263 1ull << 63 : 1ull << 31;
1264 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1265 env
->cp15
.c9_pmovsr
|= (1 << 31);
1266 pmu_update_irq(env
);
1269 env
->cp15
.c15_ccnt
= new_pmccntr
;
1271 env
->cp15
.c15_ccnt_delta
= cycles
;
1275 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1276 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1279 static void pmccntr_op_finish(CPUARMState
*env
)
1281 if (pmu_counter_enabled(env
, 31)) {
1282 #ifndef CONFIG_USER_ONLY
1283 /* Calculate when the counter will next overflow */
1284 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1285 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1286 remaining_cycles
= (uint32_t)remaining_cycles
;
1288 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1290 if (overflow_in
> 0) {
1291 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1293 ARMCPU
*cpu
= env_archcpu(env
);
1294 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1298 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1299 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1300 /* Increment once every 64 processor clock cycles */
1303 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1307 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1310 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1312 if (event_supported(event
)) {
1313 uint16_t event_idx
= supported_event_map
[event
];
1314 count
= pm_events
[event_idx
].get_count(env
);
1317 if (pmu_counter_enabled(env
, counter
)) {
1318 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1320 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1321 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1322 pmu_update_irq(env
);
1324 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1326 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1329 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1331 if (pmu_counter_enabled(env
, counter
)) {
1332 #ifndef CONFIG_USER_ONLY
1333 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1334 uint16_t event_idx
= supported_event_map
[event
];
1335 uint64_t delta
= UINT32_MAX
-
1336 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1337 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1339 if (overflow_in
> 0) {
1340 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1342 ARMCPU
*cpu
= env_archcpu(env
);
1343 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1347 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1348 env
->cp15
.c14_pmevcntr
[counter
];
1352 void pmu_op_start(CPUARMState
*env
)
1355 pmccntr_op_start(env
);
1356 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1357 pmevcntr_op_start(env
, i
);
1361 void pmu_op_finish(CPUARMState
*env
)
1364 pmccntr_op_finish(env
);
1365 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1366 pmevcntr_op_finish(env
, i
);
1370 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1372 pmu_op_start(&cpu
->env
);
1375 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1377 pmu_op_finish(&cpu
->env
);
1380 void arm_pmu_timer_cb(void *opaque
)
1382 ARMCPU
*cpu
= opaque
;
1385 * Update all the counter values based on the current underlying counts,
1386 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1387 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1388 * counter may expire.
1390 pmu_op_start(&cpu
->env
);
1391 pmu_op_finish(&cpu
->env
);
1394 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1399 if (value
& PMCRC
) {
1400 /* The counter has been reset */
1401 env
->cp15
.c15_ccnt
= 0;
1404 if (value
& PMCRP
) {
1406 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1407 env
->cp15
.c14_pmevcntr
[i
] = 0;
1411 env
->cp15
.c9_pmcr
&= ~PMCR_WRITEABLE_MASK
;
1412 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITEABLE_MASK
);
1417 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1421 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1422 /* Increment a counter's count iff: */
1423 if ((value
& (1 << i
)) && /* counter's bit is set */
1424 /* counter is enabled and not filtered */
1425 pmu_counter_enabled(env
, i
) &&
1426 /* counter is SW_INCR */
1427 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1428 pmevcntr_op_start(env
, i
);
1431 * Detect if this write causes an overflow since we can't predict
1432 * PMSWINC overflows like we can for other events
1434 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1436 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1437 env
->cp15
.c9_pmovsr
|= (1 << i
);
1438 pmu_update_irq(env
);
1441 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1443 pmevcntr_op_finish(env
, i
);
1448 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1451 pmccntr_op_start(env
);
1452 ret
= env
->cp15
.c15_ccnt
;
1453 pmccntr_op_finish(env
);
1457 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1461 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1462 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1465 env
->cp15
.c9_pmselr
= value
& 0x1f;
1468 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1471 pmccntr_op_start(env
);
1472 env
->cp15
.c15_ccnt
= value
;
1473 pmccntr_op_finish(env
);
1476 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1479 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1481 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1484 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1487 pmccntr_op_start(env
);
1488 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1489 pmccntr_op_finish(env
);
1492 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1495 pmccntr_op_start(env
);
1496 /* M is not accessible from AArch32 */
1497 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1498 (value
& PMCCFILTR
);
1499 pmccntr_op_finish(env
);
1502 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1504 /* M is not visible in AArch32 */
1505 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1508 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1511 value
&= pmu_counter_mask(env
);
1512 env
->cp15
.c9_pmcnten
|= value
;
1515 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1518 value
&= pmu_counter_mask(env
);
1519 env
->cp15
.c9_pmcnten
&= ~value
;
1522 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1525 value
&= pmu_counter_mask(env
);
1526 env
->cp15
.c9_pmovsr
&= ~value
;
1527 pmu_update_irq(env
);
1530 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1533 value
&= pmu_counter_mask(env
);
1534 env
->cp15
.c9_pmovsr
|= value
;
1535 pmu_update_irq(env
);
1538 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1539 uint64_t value
, const uint8_t counter
)
1541 if (counter
== 31) {
1542 pmccfiltr_write(env
, ri
, value
);
1543 } else if (counter
< pmu_num_counters(env
)) {
1544 pmevcntr_op_start(env
, counter
);
1547 * If this counter's event type is changing, store the current
1548 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1549 * pmevcntr_op_finish has the correct baseline when it converts back to
1552 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1553 PMXEVTYPER_EVTCOUNT
;
1554 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1555 if (old_event
!= new_event
) {
1557 if (event_supported(new_event
)) {
1558 uint16_t event_idx
= supported_event_map
[new_event
];
1559 count
= pm_events
[event_idx
].get_count(env
);
1561 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1564 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1565 pmevcntr_op_finish(env
, counter
);
1567 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1568 * PMSELR value is equal to or greater than the number of implemented
1569 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1573 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1574 const uint8_t counter
)
1576 if (counter
== 31) {
1577 return env
->cp15
.pmccfiltr_el0
;
1578 } else if (counter
< pmu_num_counters(env
)) {
1579 return env
->cp15
.c14_pmevtyper
[counter
];
1582 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1583 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1589 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1592 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1593 pmevtyper_write(env
, ri
, value
, counter
);
1596 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1599 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1600 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1603 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1604 * pmu_op_finish calls when loading saved state for a migration. Because
1605 * we're potentially updating the type of event here, the value written to
1606 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1607 * different counter type. Therefore, we need to set this value to the
1608 * current count for the counter type we're writing so that pmu_op_finish
1609 * has the correct count for its calculation.
1611 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1612 if (event_supported(event
)) {
1613 uint16_t event_idx
= supported_event_map
[event
];
1614 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1615 pm_events
[event_idx
].get_count(env
);
1619 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1621 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1622 return pmevtyper_read(env
, ri
, counter
);
1625 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1628 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1631 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1633 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1636 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1637 uint64_t value
, uint8_t counter
)
1639 if (counter
< pmu_num_counters(env
)) {
1640 pmevcntr_op_start(env
, counter
);
1641 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1642 pmevcntr_op_finish(env
, counter
);
1645 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1646 * are CONSTRAINED UNPREDICTABLE.
1650 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1653 if (counter
< pmu_num_counters(env
)) {
1655 pmevcntr_op_start(env
, counter
);
1656 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1657 pmevcntr_op_finish(env
, counter
);
1660 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1661 * are CONSTRAINED UNPREDICTABLE. */
1666 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1669 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1670 pmevcntr_write(env
, ri
, value
, counter
);
1673 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1675 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1676 return pmevcntr_read(env
, ri
, counter
);
1679 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1682 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1683 assert(counter
< pmu_num_counters(env
));
1684 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1685 pmevcntr_write(env
, ri
, value
, counter
);
1688 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1690 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1691 assert(counter
< pmu_num_counters(env
));
1692 return env
->cp15
.c14_pmevcntr
[counter
];
1695 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1698 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1701 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1703 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1706 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1710 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1712 env
->cp15
.c9_pmuserenr
= value
& 1;
1716 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1719 /* We have no event counters so only the C bit can be changed */
1720 value
&= pmu_counter_mask(env
);
1721 env
->cp15
.c9_pminten
|= value
;
1722 pmu_update_irq(env
);
1725 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 value
&= pmu_counter_mask(env
);
1729 env
->cp15
.c9_pminten
&= ~value
;
1730 pmu_update_irq(env
);
1733 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1736 /* Note that even though the AArch64 view of this register has bits
1737 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1738 * architectural requirements for bits which are RES0 only in some
1739 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1740 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1742 raw_write(env
, ri
, value
& ~0x1FULL
);
1745 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1747 /* Begin with base v8.0 state. */
1748 uint32_t valid_mask
= 0x3fff;
1749 ARMCPU
*cpu
= env_archcpu(env
);
1751 if (ri
->state
== ARM_CP_STATE_AA64
) {
1752 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1753 !cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
1754 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1756 valid_mask
&= ~SCR_NET
;
1758 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1759 valid_mask
|= SCR_TERR
;
1761 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1762 valid_mask
|= SCR_TLOR
;
1764 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1765 valid_mask
|= SCR_API
| SCR_APK
;
1767 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1768 valid_mask
|= SCR_EEL2
;
1770 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1771 valid_mask
|= SCR_ATA
;
1773 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1774 valid_mask
|= SCR_ENSCXT
;
1777 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1778 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1779 valid_mask
|= SCR_TERR
;
1783 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1784 valid_mask
&= ~SCR_HCE
;
1786 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1787 * supported if EL2 exists. The bit is UNK/SBZP when
1788 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1789 * when EL2 is unavailable.
1790 * On ARMv8, this bit is always available.
1792 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1793 !arm_feature(env
, ARM_FEATURE_V8
)) {
1794 valid_mask
&= ~SCR_SMD
;
1798 /* Clear all-context RES0 bits. */
1799 value
&= valid_mask
;
1800 raw_write(env
, ri
, value
);
1803 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1806 * scr_write will set the RES1 bits on an AArch64-only CPU.
1807 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1809 scr_write(env
, ri
, 0);
1812 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1813 const ARMCPRegInfo
*ri
,
1816 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1817 return CP_ACCESS_TRAP_EL2
;
1820 return CP_ACCESS_OK
;
1823 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1825 ARMCPU
*cpu
= env_archcpu(env
);
1827 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1830 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1831 ri
->secure
& ARM_CP_SECSTATE_S
);
1833 return cpu
->ccsidr
[index
];
1836 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1839 raw_write(env
, ri
, value
& 0xf);
1842 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1844 CPUState
*cs
= env_cpu(env
);
1845 bool el1
= arm_current_el(env
) == 1;
1846 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1849 if (hcr_el2
& HCR_IMO
) {
1850 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1854 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1859 if (hcr_el2
& HCR_FMO
) {
1860 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1864 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1869 if (hcr_el2
& HCR_AMO
) {
1870 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1878 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1881 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1882 return CP_ACCESS_TRAP_EL2
;
1885 return CP_ACCESS_OK
;
1888 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1891 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1892 return access_aa64_tid1(env
, ri
, isread
);
1895 return CP_ACCESS_OK
;
1898 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1899 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1900 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1901 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1902 /* Performance monitors are implementation defined in v7,
1903 * but with an ARM recommended set of registers, which we
1906 * Performance registers fall into three categories:
1907 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1908 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1909 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1910 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1911 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1913 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1914 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1915 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1916 .writefn
= pmcntenset_write
,
1917 .accessfn
= pmreg_access
,
1918 .raw_writefn
= raw_write
},
1919 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1920 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1921 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1922 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1923 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1924 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1926 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1927 .accessfn
= pmreg_access
,
1928 .writefn
= pmcntenclr_write
,
1929 .type
= ARM_CP_ALIAS
},
1930 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1931 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1932 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1933 .type
= ARM_CP_ALIAS
,
1934 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1935 .writefn
= pmcntenclr_write
},
1936 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1937 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1938 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1939 .accessfn
= pmreg_access
,
1940 .writefn
= pmovsr_write
,
1941 .raw_writefn
= raw_write
},
1942 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1943 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1944 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1945 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1946 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1947 .writefn
= pmovsr_write
,
1948 .raw_writefn
= raw_write
},
1949 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1950 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1951 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1952 .writefn
= pmswinc_write
},
1953 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
1954 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
1955 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1956 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1957 .writefn
= pmswinc_write
},
1958 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1959 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1960 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1961 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1962 .raw_writefn
= raw_write
},
1963 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1964 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1965 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1966 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1967 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1968 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1969 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1970 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1971 .accessfn
= pmreg_access_ccntr
},
1972 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1973 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1974 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1976 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
1977 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
1978 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
1979 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
1980 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
1981 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1982 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1984 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1985 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1986 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
1987 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1989 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1991 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1992 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1993 .accessfn
= pmreg_access
,
1994 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1995 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1996 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1997 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1998 .accessfn
= pmreg_access
,
1999 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2000 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2001 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2002 .accessfn
= pmreg_access_xevcntr
,
2003 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2004 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2005 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2006 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2007 .accessfn
= pmreg_access_xevcntr
,
2008 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2009 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2010 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2011 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2013 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2014 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2015 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2016 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2017 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2019 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2020 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2021 .access
= PL1_RW
, .accessfn
= access_tpm
,
2022 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2023 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2025 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2026 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2027 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2028 .access
= PL1_RW
, .accessfn
= access_tpm
,
2030 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2031 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2032 .resetvalue
= 0x0 },
2033 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2034 .access
= PL1_RW
, .accessfn
= access_tpm
,
2035 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2036 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2037 .writefn
= pmintenclr_write
, },
2038 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2039 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2040 .access
= PL1_RW
, .accessfn
= access_tpm
,
2041 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2042 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2043 .writefn
= pmintenclr_write
},
2044 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2045 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2047 .accessfn
= access_aa64_tid2
,
2048 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2049 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2050 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2052 .accessfn
= access_aa64_tid2
,
2053 .writefn
= csselr_write
, .resetvalue
= 0,
2054 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2055 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2056 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2057 * just RAZ for all cores:
2059 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2060 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2061 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2062 .accessfn
= access_aa64_tid1
,
2064 /* Auxiliary fault status registers: these also are IMPDEF, and we
2065 * choose to RAZ/WI for all cores.
2067 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2068 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2069 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2070 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2071 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2072 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2073 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2074 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2075 /* MAIR can just read-as-written because we don't implement caches
2076 * and so don't need to care about memory attributes.
2078 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2079 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2080 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2081 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2083 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2084 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2085 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2087 /* For non-long-descriptor page tables these are PRRR and NMRR;
2088 * regardless they still act as reads-as-written for QEMU.
2090 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2091 * allows them to assign the correct fieldoffset based on the endianness
2092 * handled in the field definitions.
2094 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2095 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2096 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2097 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2098 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2099 .resetfn
= arm_cp_reset_ignore
},
2100 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2101 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2102 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2103 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2104 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2105 .resetfn
= arm_cp_reset_ignore
},
2106 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2107 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2108 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2109 /* 32 bit ITLB invalidates */
2110 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2111 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2112 .writefn
= tlbiall_write
},
2113 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2114 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2115 .writefn
= tlbimva_write
},
2116 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2117 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2118 .writefn
= tlbiasid_write
},
2119 /* 32 bit DTLB invalidates */
2120 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2121 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2122 .writefn
= tlbiall_write
},
2123 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2124 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2125 .writefn
= tlbimva_write
},
2126 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2127 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2128 .writefn
= tlbiasid_write
},
2129 /* 32 bit TLB invalidates */
2130 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2131 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2132 .writefn
= tlbiall_write
},
2133 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2134 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2135 .writefn
= tlbimva_write
},
2136 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2137 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2138 .writefn
= tlbiasid_write
},
2139 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2140 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2141 .writefn
= tlbimvaa_write
},
2144 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2145 /* 32 bit TLB invalidates, Inner Shareable */
2146 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2147 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2148 .writefn
= tlbiall_is_write
},
2149 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2150 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2151 .writefn
= tlbimva_is_write
},
2152 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2153 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2154 .writefn
= tlbiasid_is_write
},
2155 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2156 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2157 .writefn
= tlbimvaa_is_write
},
2160 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2161 /* PMOVSSET is not implemented in v7 before v7ve */
2162 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2163 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2164 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2165 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2166 .writefn
= pmovsset_write
,
2167 .raw_writefn
= raw_write
},
2168 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2169 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2170 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2171 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2172 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2173 .writefn
= pmovsset_write
,
2174 .raw_writefn
= raw_write
},
2177 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2184 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2188 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2189 * at all, so we don't need to check whether we're v8A.
2191 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2192 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2193 return CP_ACCESS_TRAP_EL2
;
2195 return CP_ACCESS_OK
;
2198 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2201 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2202 return CP_ACCESS_TRAP
;
2204 return teecr_access(env
, ri
, isread
);
2207 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2208 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2209 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2211 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2212 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2213 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2214 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2217 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2218 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2219 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2221 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2222 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2224 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2225 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2226 .resetfn
= arm_cp_reset_ignore
},
2227 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2228 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2229 .access
= PL0_R
|PL1_W
,
2230 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2232 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2233 .access
= PL0_R
|PL1_W
,
2234 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2235 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2236 .resetfn
= arm_cp_reset_ignore
},
2237 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2238 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2240 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2241 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2243 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2244 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2248 #ifndef CONFIG_USER_ONLY
2250 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2253 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2254 * Writable only at the highest implemented exception level.
2256 int el
= arm_current_el(env
);
2262 hcr
= arm_hcr_el2_eff(env
);
2263 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2264 cntkctl
= env
->cp15
.cnthctl_el2
;
2266 cntkctl
= env
->cp15
.c14_cntkctl
;
2268 if (!extract32(cntkctl
, 0, 2)) {
2269 return CP_ACCESS_TRAP
;
2273 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2274 arm_is_secure_below_el3(env
)) {
2275 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2276 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2284 if (!isread
&& el
< arm_highest_el(env
)) {
2285 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2288 return CP_ACCESS_OK
;
2291 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2294 unsigned int cur_el
= arm_current_el(env
);
2295 bool has_el2
= arm_is_el2_enabled(env
);
2296 uint64_t hcr
= arm_hcr_el2_eff(env
);
2300 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2301 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2302 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2303 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2306 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2307 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2308 return CP_ACCESS_TRAP
;
2311 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2312 if (hcr
& HCR_E2H
) {
2313 if (timeridx
== GTIMER_PHYS
&&
2314 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2315 return CP_ACCESS_TRAP_EL2
;
2318 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2319 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2320 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2321 return CP_ACCESS_TRAP_EL2
;
2327 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2328 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2330 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2331 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2332 return CP_ACCESS_TRAP_EL2
;
2336 return CP_ACCESS_OK
;
2339 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2342 unsigned int cur_el
= arm_current_el(env
);
2343 bool has_el2
= arm_is_el2_enabled(env
);
2344 uint64_t hcr
= arm_hcr_el2_eff(env
);
2348 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2349 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2350 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2351 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2355 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2356 * EL0 if EL0[PV]TEN is zero.
2358 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2359 return CP_ACCESS_TRAP
;
2364 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2365 if (hcr
& HCR_E2H
) {
2366 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2367 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2368 return CP_ACCESS_TRAP_EL2
;
2371 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2372 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2373 return CP_ACCESS_TRAP_EL2
;
2379 return CP_ACCESS_OK
;
2382 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2383 const ARMCPRegInfo
*ri
,
2386 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2389 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2390 const ARMCPRegInfo
*ri
,
2393 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2396 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2399 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2402 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2405 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2408 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2409 const ARMCPRegInfo
*ri
,
2412 /* The AArch64 register view of the secure physical timer is
2413 * always accessible from EL3, and configurably accessible from
2416 switch (arm_current_el(env
)) {
2418 if (!arm_is_secure(env
)) {
2419 return CP_ACCESS_TRAP
;
2421 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2422 return CP_ACCESS_TRAP_EL3
;
2424 return CP_ACCESS_OK
;
2427 return CP_ACCESS_TRAP
;
2429 return CP_ACCESS_OK
;
2431 g_assert_not_reached();
2435 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2437 ARMCPU
*cpu
= env_archcpu(env
);
2439 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2442 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2444 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2447 /* Timer enabled: calculate and set current ISTATUS, irq, and
2448 * reset timer to when ISTATUS next has to change
2450 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2451 cpu
->env
.cp15
.cntvoff_el2
: 0;
2452 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2453 /* Note that this must be unsigned 64 bit arithmetic: */
2454 int istatus
= count
- offset
>= gt
->cval
;
2458 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2460 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2461 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2464 /* Next transition is when count rolls back over to zero */
2465 nexttick
= UINT64_MAX
;
2467 /* Next transition is when we hit cval */
2468 nexttick
= gt
->cval
+ offset
;
2470 /* Note that the desired next expiry time might be beyond the
2471 * signed-64-bit range of a QEMUTimer -- in this case we just
2472 * set the timer for as far in the future as possible. When the
2473 * timer expires we will reset the timer for any remaining period.
2475 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2476 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2478 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2480 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2482 /* Timer disabled: ISTATUS and timer output always clear */
2484 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2485 timer_del(cpu
->gt_timer
[timeridx
]);
2486 trace_arm_gt_recalc_disabled(timeridx
);
2490 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2493 ARMCPU
*cpu
= env_archcpu(env
);
2495 timer_del(cpu
->gt_timer
[timeridx
]);
2498 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2500 return gt_get_countervalue(env
);
2503 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2507 switch (arm_current_el(env
)) {
2509 hcr
= arm_hcr_el2_eff(env
);
2510 if (hcr
& HCR_E2H
) {
2515 hcr
= arm_hcr_el2_eff(env
);
2516 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2522 return env
->cp15
.cntvoff_el2
;
2525 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2527 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2530 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2534 trace_arm_gt_cval_write(timeridx
, value
);
2535 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2536 gt_recalc_timer(env_archcpu(env
), timeridx
);
2539 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2542 uint64_t offset
= 0;
2546 case GTIMER_HYPVIRT
:
2547 offset
= gt_virt_cnt_offset(env
);
2551 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2552 (gt_get_countervalue(env
) - offset
));
2555 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2559 uint64_t offset
= 0;
2563 case GTIMER_HYPVIRT
:
2564 offset
= gt_virt_cnt_offset(env
);
2568 trace_arm_gt_tval_write(timeridx
, value
);
2569 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2570 sextract64(value
, 0, 32);
2571 gt_recalc_timer(env_archcpu(env
), timeridx
);
2574 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2578 ARMCPU
*cpu
= env_archcpu(env
);
2579 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2581 trace_arm_gt_ctl_write(timeridx
, value
);
2582 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2583 if ((oldval
^ value
) & 1) {
2584 /* Enable toggled */
2585 gt_recalc_timer(cpu
, timeridx
);
2586 } else if ((oldval
^ value
) & 2) {
2587 /* IMASK toggled: don't need to recalculate,
2588 * just set the interrupt line based on ISTATUS
2590 int irqstate
= (oldval
& 4) && !(value
& 2);
2592 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2593 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2597 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2599 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2602 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2605 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2608 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2610 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2613 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2616 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2619 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2622 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2625 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2627 switch (arm_mmu_idx(env
)) {
2628 case ARMMMUIdx_E20_0
:
2629 case ARMMMUIdx_E20_2
:
2630 case ARMMMUIdx_E20_2_PAN
:
2631 case ARMMMUIdx_SE20_0
:
2632 case ARMMMUIdx_SE20_2
:
2633 case ARMMMUIdx_SE20_2_PAN
:
2640 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2642 switch (arm_mmu_idx(env
)) {
2643 case ARMMMUIdx_E20_0
:
2644 case ARMMMUIdx_E20_2
:
2645 case ARMMMUIdx_E20_2_PAN
:
2646 case ARMMMUIdx_SE20_0
:
2647 case ARMMMUIdx_SE20_2
:
2648 case ARMMMUIdx_SE20_2_PAN
:
2649 return GTIMER_HYPVIRT
;
2655 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2656 const ARMCPRegInfo
*ri
)
2658 int timeridx
= gt_phys_redir_timeridx(env
);
2659 return env
->cp15
.c14_timer
[timeridx
].cval
;
2662 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2665 int timeridx
= gt_phys_redir_timeridx(env
);
2666 gt_cval_write(env
, ri
, timeridx
, value
);
2669 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2670 const ARMCPRegInfo
*ri
)
2672 int timeridx
= gt_phys_redir_timeridx(env
);
2673 return gt_tval_read(env
, ri
, timeridx
);
2676 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2679 int timeridx
= gt_phys_redir_timeridx(env
);
2680 gt_tval_write(env
, ri
, timeridx
, value
);
2683 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2684 const ARMCPRegInfo
*ri
)
2686 int timeridx
= gt_phys_redir_timeridx(env
);
2687 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2690 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2693 int timeridx
= gt_phys_redir_timeridx(env
);
2694 gt_ctl_write(env
, ri
, timeridx
, value
);
2697 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2699 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2702 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2705 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2708 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2710 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2713 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2716 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2719 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2722 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2725 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2728 ARMCPU
*cpu
= env_archcpu(env
);
2730 trace_arm_gt_cntvoff_write(value
);
2731 raw_write(env
, ri
, value
);
2732 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2735 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2736 const ARMCPRegInfo
*ri
)
2738 int timeridx
= gt_virt_redir_timeridx(env
);
2739 return env
->cp15
.c14_timer
[timeridx
].cval
;
2742 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2745 int timeridx
= gt_virt_redir_timeridx(env
);
2746 gt_cval_write(env
, ri
, timeridx
, value
);
2749 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2750 const ARMCPRegInfo
*ri
)
2752 int timeridx
= gt_virt_redir_timeridx(env
);
2753 return gt_tval_read(env
, ri
, timeridx
);
2756 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2759 int timeridx
= gt_virt_redir_timeridx(env
);
2760 gt_tval_write(env
, ri
, timeridx
, value
);
2763 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2764 const ARMCPRegInfo
*ri
)
2766 int timeridx
= gt_virt_redir_timeridx(env
);
2767 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2770 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2773 int timeridx
= gt_virt_redir_timeridx(env
);
2774 gt_ctl_write(env
, ri
, timeridx
, value
);
2777 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2779 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2782 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2785 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2788 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2790 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2793 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2796 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2799 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2802 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2805 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2807 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2810 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2813 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2816 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2818 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2821 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2824 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2827 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2830 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2833 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2835 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2838 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2841 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2844 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2846 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2849 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2852 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2855 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2858 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2861 void arm_gt_ptimer_cb(void *opaque
)
2863 ARMCPU
*cpu
= opaque
;
2865 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2868 void arm_gt_vtimer_cb(void *opaque
)
2870 ARMCPU
*cpu
= opaque
;
2872 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2875 void arm_gt_htimer_cb(void *opaque
)
2877 ARMCPU
*cpu
= opaque
;
2879 gt_recalc_timer(cpu
, GTIMER_HYP
);
2882 void arm_gt_stimer_cb(void *opaque
)
2884 ARMCPU
*cpu
= opaque
;
2886 gt_recalc_timer(cpu
, GTIMER_SEC
);
2889 void arm_gt_hvtimer_cb(void *opaque
)
2891 ARMCPU
*cpu
= opaque
;
2893 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
2896 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2898 ARMCPU
*cpu
= env_archcpu(env
);
2900 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
2903 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2904 /* Note that CNTFRQ is purely reads-as-written for the benefit
2905 * of software; writing it doesn't actually change the timer frequency.
2906 * Our reset value matches the fixed frequency we implement the timer at.
2908 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2909 .type
= ARM_CP_ALIAS
,
2910 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2911 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2913 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2914 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2915 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2916 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2917 .resetfn
= arm_gt_cntfrq_reset
,
2919 /* overall control: mostly access permissions */
2920 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2921 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2923 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2926 /* per-timer control */
2927 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2928 .secure
= ARM_CP_SECSTATE_NS
,
2929 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2930 .accessfn
= gt_ptimer_access
,
2931 .fieldoffset
= offsetoflow32(CPUARMState
,
2932 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2933 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2934 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2936 { .name
= "CNTP_CTL_S",
2937 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2938 .secure
= ARM_CP_SECSTATE_S
,
2939 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2940 .accessfn
= gt_ptimer_access
,
2941 .fieldoffset
= offsetoflow32(CPUARMState
,
2942 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2943 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2945 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2946 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2947 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2948 .accessfn
= gt_ptimer_access
,
2949 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2951 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2952 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2954 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2955 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2956 .accessfn
= gt_vtimer_access
,
2957 .fieldoffset
= offsetoflow32(CPUARMState
,
2958 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2959 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2960 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2962 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2963 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2964 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2965 .accessfn
= gt_vtimer_access
,
2966 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2968 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2969 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2971 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2972 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2973 .secure
= ARM_CP_SECSTATE_NS
,
2974 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2975 .accessfn
= gt_ptimer_access
,
2976 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2978 { .name
= "CNTP_TVAL_S",
2979 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2980 .secure
= ARM_CP_SECSTATE_S
,
2981 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2982 .accessfn
= gt_ptimer_access
,
2983 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2985 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2986 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2987 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2988 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2989 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2991 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2992 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2993 .accessfn
= gt_vtimer_access
,
2994 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
2996 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2997 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2998 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2999 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3000 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3002 /* The counter itself */
3003 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3004 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3005 .accessfn
= gt_pct_access
,
3006 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3008 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3009 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3010 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3011 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3013 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3014 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3015 .accessfn
= gt_vct_access
,
3016 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3018 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3019 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3020 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3021 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3023 /* Comparison value, indicating when the timer goes off */
3024 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3025 .secure
= ARM_CP_SECSTATE_NS
,
3027 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3028 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3029 .accessfn
= gt_ptimer_access
,
3030 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3031 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3033 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3034 .secure
= ARM_CP_SECSTATE_S
,
3036 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3037 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3038 .accessfn
= gt_ptimer_access
,
3039 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3041 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3042 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3045 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3046 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3047 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3048 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3050 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3052 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3053 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3054 .accessfn
= gt_vtimer_access
,
3055 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3056 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3058 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3059 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3062 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3063 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3064 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3065 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3067 /* Secure timer -- this is actually restricted to only EL3
3068 * and configurably Secure-EL1 via the accessfn.
3070 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3071 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3072 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3073 .accessfn
= gt_stimer_access
,
3074 .readfn
= gt_sec_tval_read
,
3075 .writefn
= gt_sec_tval_write
,
3076 .resetfn
= gt_sec_timer_reset
,
3078 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3079 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3080 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3081 .accessfn
= gt_stimer_access
,
3082 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3084 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3086 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3087 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3088 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3089 .accessfn
= gt_stimer_access
,
3090 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3091 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3095 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3098 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3099 return CP_ACCESS_TRAP
;
3101 return CP_ACCESS_OK
;
3106 /* In user-mode most of the generic timer registers are inaccessible
3107 * however modern kernels (4.12+) allow access to cntvct_el0
3110 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3112 ARMCPU
*cpu
= env_archcpu(env
);
3114 /* Currently we have no support for QEMUTimer in linux-user so we
3115 * can't call gt_get_countervalue(env), instead we directly
3116 * call the lower level functions.
3118 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3121 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3122 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3123 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3124 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3125 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3126 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3128 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3129 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3130 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3131 .readfn
= gt_virt_cnt_read
,
3137 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3139 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3140 raw_write(env
, ri
, value
);
3141 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3142 raw_write(env
, ri
, value
& 0xfffff6ff);
3144 raw_write(env
, ri
, value
& 0xfffff1ff);
3148 #ifndef CONFIG_USER_ONLY
3149 /* get_phys_addr() isn't present for user-mode-only targets */
3151 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3155 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3156 * Secure EL1 (which can only happen if EL3 is AArch64).
3157 * They are simply UNDEF if executed from NS EL1.
3158 * They function normally from EL2 or EL3.
3160 if (arm_current_el(env
) == 1) {
3161 if (arm_is_secure_below_el3(env
)) {
3162 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3163 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3165 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3167 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3170 return CP_ACCESS_OK
;
3174 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3175 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3178 target_ulong page_size
;
3182 bool format64
= false;
3183 MemTxAttrs attrs
= {};
3184 ARMMMUFaultInfo fi
= {};
3185 ARMCacheAttrs cacheattrs
= {};
3187 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3188 &prot
, &page_size
, &fi
, &cacheattrs
);
3192 * Some kinds of translation fault must cause exceptions rather
3193 * than being reported in the PAR.
3195 int current_el
= arm_current_el(env
);
3197 uint32_t syn
, fsr
, fsc
;
3198 bool take_exc
= false;
3200 if (fi
.s1ptw
&& current_el
== 1
3201 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3203 * Synchronous stage 2 fault on an access made as part of the
3204 * translation table walk for AT S1E0* or AT S1E1* insn
3205 * executed from NS EL1. If this is a synchronous external abort
3206 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3207 * to EL3. Otherwise the fault is taken as an exception to EL2,
3208 * and HPFAR_EL2 holds the faulting IPA.
3210 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3211 (env
->cp15
.scr_el3
& SCR_EA
)) {
3214 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3215 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3216 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3221 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3223 * Synchronous external aborts during a translation table walk
3224 * are taken as Data Abort exceptions.
3227 if (current_el
== 3) {
3233 target_el
= exception_target_el(env
);
3239 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3240 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3241 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3242 fsr
= arm_fi_to_lfsc(&fi
);
3243 fsc
= extract32(fsr
, 0, 6);
3245 fsr
= arm_fi_to_sfsc(&fi
);
3249 * Report exception with ESR indicating a fault due to a
3250 * translation table walk for a cache maintenance instruction.
3252 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3253 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3254 env
->exception
.vaddress
= value
;
3255 env
->exception
.fsr
= fsr
;
3256 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3262 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3265 * * TTBCR.EAE determines whether the result is returned using the
3266 * 32-bit or the 64-bit PAR format
3267 * * Instructions executed in Hyp mode always use the 64bit format
3269 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3270 * * The Non-secure TTBCR.EAE bit is set to 1
3271 * * The implementation includes EL2, and the value of HCR.VM is 1
3273 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3275 * ATS1Hx always uses the 64bit format.
3277 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3279 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3280 if (mmu_idx
== ARMMMUIdx_E10_0
||
3281 mmu_idx
== ARMMMUIdx_E10_1
||
3282 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3283 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3285 format64
|= arm_current_el(env
) == 2;
3291 /* Create a 64-bit PAR */
3292 par64
= (1 << 11); /* LPAE bit always set */
3294 par64
|= phys_addr
& ~0xfffULL
;
3295 if (!attrs
.secure
) {
3296 par64
|= (1 << 9); /* NS */
3298 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3299 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3301 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3304 par64
|= (fsr
& 0x3f) << 1; /* FS */
3306 par64
|= (1 << 9); /* S */
3309 par64
|= (1 << 8); /* PTW */
3313 /* fsr is a DFSR/IFSR value for the short descriptor
3314 * translation table format (with WnR always clear).
3315 * Convert it to a 32-bit PAR.
3318 /* We do not set any attribute bits in the PAR */
3319 if (page_size
== (1 << 24)
3320 && arm_feature(env
, ARM_FEATURE_V7
)) {
3321 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3323 par64
= phys_addr
& 0xfffff000;
3325 if (!attrs
.secure
) {
3326 par64
|= (1 << 9); /* NS */
3329 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3331 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3332 ((fsr
& 0xf) << 1) | 1;
3337 #endif /* CONFIG_TCG */
3339 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3342 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3345 int el
= arm_current_el(env
);
3346 bool secure
= arm_is_secure_below_el3(env
);
3348 switch (ri
->opc2
& 6) {
3350 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3353 mmu_idx
= ARMMMUIdx_SE3
;
3356 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3359 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3360 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3361 : ARMMMUIdx_Stage1_E1_PAN
);
3363 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3367 g_assert_not_reached();
3371 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3374 mmu_idx
= ARMMMUIdx_SE10_0
;
3377 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3378 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3381 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3384 g_assert_not_reached();
3388 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3389 mmu_idx
= ARMMMUIdx_E10_1
;
3392 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3393 mmu_idx
= ARMMMUIdx_E10_0
;
3396 g_assert_not_reached();
3399 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3401 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3403 /* Handled by hardware accelerator. */
3404 g_assert_not_reached();
3405 #endif /* CONFIG_TCG */
3408 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3412 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3415 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3417 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3419 /* Handled by hardware accelerator. */
3420 g_assert_not_reached();
3421 #endif /* CONFIG_TCG */
3424 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3427 if (arm_current_el(env
) == 3 &&
3428 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3429 return CP_ACCESS_TRAP
;
3431 return CP_ACCESS_OK
;
3434 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3438 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3440 int secure
= arm_is_secure_below_el3(env
);
3442 switch (ri
->opc2
& 6) {
3445 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3446 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3447 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3448 : ARMMMUIdx_Stage1_E1_PAN
);
3450 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3453 case 4: /* AT S1E2R, AT S1E2W */
3454 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3456 case 6: /* AT S1E3R, AT S1E3W */
3457 mmu_idx
= ARMMMUIdx_SE3
;
3460 g_assert_not_reached();
3463 case 2: /* AT S1E0R, AT S1E0W */
3464 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3466 case 4: /* AT S12E1R, AT S12E1W */
3467 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3469 case 6: /* AT S12E0R, AT S12E0W */
3470 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3473 g_assert_not_reached();
3476 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3478 /* Handled by hardware accelerator. */
3479 g_assert_not_reached();
3480 #endif /* CONFIG_TCG */
3484 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3485 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3486 .access
= PL1_RW
, .resetvalue
= 0,
3487 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3488 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3489 .writefn
= par_write
},
3490 #ifndef CONFIG_USER_ONLY
3491 /* This underdecoding is safe because the reginfo is NO_RAW. */
3492 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3493 .access
= PL1_W
, .accessfn
= ats_access
,
3494 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3498 /* Return basic MPU access permission bits. */
3499 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3506 for (i
= 0; i
< 16; i
+= 2) {
3507 ret
|= (val
>> i
) & mask
;
3513 /* Pad basic MPU access permission bits to extended format. */
3514 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3521 for (i
= 0; i
< 16; i
+= 2) {
3522 ret
|= (val
& mask
) << i
;
3528 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3531 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3534 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3536 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3539 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3542 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3545 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3547 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3550 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3552 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3558 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3562 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3565 ARMCPU
*cpu
= env_archcpu(env
);
3566 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3572 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3573 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3577 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3580 ARMCPU
*cpu
= env_archcpu(env
);
3581 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3583 if (value
>= nrgs
) {
3584 qemu_log_mask(LOG_GUEST_ERROR
,
3585 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3586 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3590 raw_write(env
, ri
, value
);
3593 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3594 /* Reset for all these registers is handled in arm_cpu_reset(),
3595 * because the PMSAv7 is also used by M-profile CPUs, which do
3596 * not register cpregs but still need the state to be reset.
3598 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3599 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3600 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3601 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3602 .resetfn
= arm_cp_reset_ignore
},
3603 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3604 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3605 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3606 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3607 .resetfn
= arm_cp_reset_ignore
},
3608 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3609 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3610 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3611 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3612 .resetfn
= arm_cp_reset_ignore
},
3613 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3615 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3616 .writefn
= pmsav7_rgnr_write
,
3617 .resetfn
= arm_cp_reset_ignore
},
3620 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3621 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3622 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3623 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3624 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3625 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3626 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3627 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3628 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3629 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3631 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3633 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3635 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3637 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3639 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3640 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3642 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3643 /* Protection region base and size registers */
3644 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3645 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3646 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3647 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3648 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3649 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3650 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3651 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3652 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3653 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3654 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3655 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3656 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3657 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3658 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3659 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3660 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3661 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3662 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3663 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3664 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3665 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3666 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3667 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3670 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3673 TCR
*tcr
= raw_ptr(env
, ri
);
3674 int maskshift
= extract32(value
, 0, 3);
3676 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3677 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3678 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3679 * using Long-desciptor translation table format */
3680 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3681 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3682 /* In an implementation that includes the Security Extensions
3683 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3684 * Short-descriptor translation table format.
3686 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3692 /* Update the masks corresponding to the TCR bank being written
3693 * Note that we always calculate mask and base_mask, but
3694 * they are only used for short-descriptor tables (ie if EAE is 0);
3695 * for long-descriptor tables the TCR fields are used differently
3696 * and the mask and base_mask values are meaningless.
3698 tcr
->raw_tcr
= value
;
3699 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3700 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3703 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3706 ARMCPU
*cpu
= env_archcpu(env
);
3707 TCR
*tcr
= raw_ptr(env
, ri
);
3709 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3710 /* With LPAE the TTBCR could result in a change of ASID
3711 * via the TTBCR.A1 bit, so do a TLB flush.
3713 tlb_flush(CPU(cpu
));
3715 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3716 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3717 vmsa_ttbcr_raw_write(env
, ri
, value
);
3720 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3722 TCR
*tcr
= raw_ptr(env
, ri
);
3724 /* Reset both the TCR as well as the masks corresponding to the bank of
3725 * the TCR being reset.
3729 tcr
->base_mask
= 0xffffc000u
;
3732 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3735 ARMCPU
*cpu
= env_archcpu(env
);
3736 TCR
*tcr
= raw_ptr(env
, ri
);
3738 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3739 tlb_flush(CPU(cpu
));
3740 tcr
->raw_tcr
= value
;
3743 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3746 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3747 if (cpreg_field_is_64bit(ri
) &&
3748 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3749 ARMCPU
*cpu
= env_archcpu(env
);
3750 tlb_flush(CPU(cpu
));
3752 raw_write(env
, ri
, value
);
3755 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3759 * If we are running with E2&0 regime, then an ASID is active.
3760 * Flush if that might be changing. Note we're not checking
3761 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3762 * holds the active ASID, only checking the field that might.
3764 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3765 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3766 uint16_t mask
= ARMMMUIdxBit_E20_2
|
3767 ARMMMUIdxBit_E20_2_PAN
|
3770 if (arm_is_secure_below_el3(env
)) {
3771 mask
>>= ARM_MMU_IDX_A_NS
;
3774 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
3776 raw_write(env
, ri
, value
);
3779 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3782 ARMCPU
*cpu
= env_archcpu(env
);
3783 CPUState
*cs
= CPU(cpu
);
3786 * A change in VMID to the stage2 page table (Stage2) invalidates
3787 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3789 if (raw_read(env
, ri
) != value
) {
3790 uint16_t mask
= ARMMMUIdxBit_E10_1
|
3791 ARMMMUIdxBit_E10_1_PAN
|
3794 if (arm_is_secure_below_el3(env
)) {
3795 mask
>>= ARM_MMU_IDX_A_NS
;
3798 tlb_flush_by_mmuidx(cs
, mask
);
3799 raw_write(env
, ri
, value
);
3803 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3804 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3805 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
3806 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3807 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3808 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3809 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3810 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3811 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3812 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3813 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3814 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3815 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3816 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3817 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3818 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3819 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3823 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3824 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3825 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3826 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3827 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3828 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3829 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3830 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3831 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3832 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3833 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3834 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3835 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3836 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3837 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3838 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3839 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3840 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3841 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3842 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3843 .writefn
= vmsa_tcr_el12_write
,
3844 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3845 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3846 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3847 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3848 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3849 .raw_writefn
= vmsa_ttbcr_raw_write
,
3850 /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
3851 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.tcr_el
[3]),
3852 offsetof(CPUARMState
, cp15
.tcr_el
[1])} },
3855 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3856 * qemu tlbs nor adjusting cached masks.
3858 static const ARMCPRegInfo ttbcr2_reginfo
= {
3859 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3860 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3861 .type
= ARM_CP_ALIAS
,
3862 .bank_fieldoffsets
= {
3863 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3].raw_tcr
),
3864 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1].raw_tcr
),
3868 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3871 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3872 /* The OS_TYPE bit in this register changes the reported CPUID! */
3873 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3874 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3877 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3880 env
->cp15
.c15_threadid
= value
& 0xffff;
3883 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3886 /* Wait-for-interrupt (deprecated) */
3887 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3890 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3893 /* On OMAP there are registers indicating the max/min index of dcache lines
3894 * containing a dirty line; cache flush operations have to reset these.
3896 env
->cp15
.c15_i_max
= 0x000;
3897 env
->cp15
.c15_i_min
= 0xff0;
3900 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3901 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3902 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3903 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3905 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3906 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3907 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3909 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3910 .writefn
= omap_ticonfig_write
},
3911 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3913 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3914 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3915 .access
= PL1_RW
, .resetvalue
= 0xff0,
3916 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3917 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3919 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3920 .writefn
= omap_threadid_write
},
3921 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3922 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3923 .type
= ARM_CP_NO_RAW
,
3924 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3925 /* TODO: Peripheral port remap register:
3926 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3927 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3930 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3931 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3932 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3933 .writefn
= omap_cachemaint_write
},
3934 { .name
= "C9", .cp
= 15, .crn
= 9,
3935 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3936 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3939 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3942 env
->cp15
.c15_cpar
= value
& 0x3fff;
3945 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3946 { .name
= "XSCALE_CPAR",
3947 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3948 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3949 .writefn
= xscale_cpar_write
, },
3950 { .name
= "XSCALE_AUXCR",
3951 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3952 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3954 /* XScale specific cache-lockdown: since we have no cache we NOP these
3955 * and hope the guest does not really rely on cache behaviour.
3957 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3958 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3959 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3960 { .name
= "XSCALE_UNLOCK_ICACHE",
3961 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3962 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3963 { .name
= "XSCALE_DCACHE_LOCK",
3964 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3965 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3966 { .name
= "XSCALE_UNLOCK_DCACHE",
3967 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3968 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3971 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3972 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3973 * implementation of this implementation-defined space.
3974 * Ideally this should eventually disappear in favour of actually
3975 * implementing the correct behaviour for all cores.
3977 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3978 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3980 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3984 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3985 /* Cache status: RAZ because we have no cache so it's always clean */
3986 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3987 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3991 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3992 /* We never have a a block transfer operation in progress */
3993 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3994 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3996 /* The cache ops themselves: these all NOP for QEMU */
3997 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3998 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3999 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4000 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4001 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4002 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4003 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4004 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4005 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4006 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4007 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4008 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4011 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4012 /* The cache test-and-clean instructions always return (1 << 30)
4013 * to indicate that there are no dirty cache lines.
4015 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4016 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4017 .resetvalue
= (1 << 30) },
4018 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4019 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4020 .resetvalue
= (1 << 30) },
4023 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4024 /* Ignore ReadBuffer accesses */
4025 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4026 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4027 .access
= PL1_RW
, .resetvalue
= 0,
4028 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4031 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4033 unsigned int cur_el
= arm_current_el(env
);
4035 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4036 return env
->cp15
.vpidr_el2
;
4038 return raw_read(env
, ri
);
4041 static uint64_t mpidr_read_val(CPUARMState
*env
)
4043 ARMCPU
*cpu
= env_archcpu(env
);
4044 uint64_t mpidr
= cpu
->mp_affinity
;
4046 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4047 mpidr
|= (1U << 31);
4048 /* Cores which are uniprocessor (non-coherent)
4049 * but still implement the MP extensions set
4050 * bit 30. (For instance, Cortex-R5).
4052 if (cpu
->mp_is_up
) {
4053 mpidr
|= (1u << 30);
4059 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4061 unsigned int cur_el
= arm_current_el(env
);
4063 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4064 return env
->cp15
.vmpidr_el2
;
4066 return mpidr_read_val(env
);
4069 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4071 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4072 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4073 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4074 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4075 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4076 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4077 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4078 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4079 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4080 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4081 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4082 offsetof(CPUARMState
, cp15
.par_ns
)} },
4083 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4084 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4085 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4086 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4087 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4088 .writefn
= vmsa_ttbr_write
, },
4089 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4090 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4091 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4092 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4093 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4094 .writefn
= vmsa_ttbr_write
, },
4097 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4099 return vfp_get_fpcr(env
);
4102 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4105 vfp_set_fpcr(env
, value
);
4108 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4110 return vfp_get_fpsr(env
);
4113 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4116 vfp_set_fpsr(env
, value
);
4119 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4122 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4123 return CP_ACCESS_TRAP
;
4125 return CP_ACCESS_OK
;
4128 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4131 env
->daif
= value
& PSTATE_DAIF
;
4134 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4136 return env
->pstate
& PSTATE_PAN
;
4139 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4142 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4145 static const ARMCPRegInfo pan_reginfo
= {
4146 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4147 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4148 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4149 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4152 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4154 return env
->pstate
& PSTATE_UAO
;
4157 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4160 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4163 static const ARMCPRegInfo uao_reginfo
= {
4164 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4165 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4166 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4167 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4170 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4172 return env
->pstate
& PSTATE_DIT
;
4175 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4178 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4181 static const ARMCPRegInfo dit_reginfo
= {
4182 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4183 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4184 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4185 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4188 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4190 return env
->pstate
& PSTATE_SSBS
;
4193 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4196 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4199 static const ARMCPRegInfo ssbs_reginfo
= {
4200 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4201 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4202 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4203 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4206 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4207 const ARMCPRegInfo
*ri
,
4210 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4211 switch (arm_current_el(env
)) {
4213 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4214 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4215 return CP_ACCESS_TRAP
;
4219 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4220 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4221 return CP_ACCESS_TRAP_EL2
;
4225 return CP_ACCESS_OK
;
4228 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4229 const ARMCPRegInfo
*ri
,
4232 /* Cache invalidate/clean to Point of Unification... */
4233 switch (arm_current_el(env
)) {
4235 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4236 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4237 return CP_ACCESS_TRAP
;
4241 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4242 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4243 return CP_ACCESS_TRAP_EL2
;
4247 return CP_ACCESS_OK
;
4250 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4251 * Page D4-1736 (DDI0487A.b)
4254 static int vae1_tlbmask(CPUARMState
*env
)
4256 uint64_t hcr
= arm_hcr_el2_eff(env
);
4259 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4260 mask
= ARMMMUIdxBit_E20_2
|
4261 ARMMMUIdxBit_E20_2_PAN
|
4264 mask
= ARMMMUIdxBit_E10_1
|
4265 ARMMMUIdxBit_E10_1_PAN
|
4269 if (arm_is_secure_below_el3(env
)) {
4270 mask
>>= ARM_MMU_IDX_A_NS
;
4276 /* Return 56 if TBI is enabled, 64 otherwise. */
4277 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4280 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
4281 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4282 int select
= extract64(addr
, 55, 1);
4284 return (tbi
>> select
) & 1 ? 56 : 64;
4287 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4289 uint64_t hcr
= arm_hcr_el2_eff(env
);
4292 /* Only the regime of the mmu_idx below is significant. */
4293 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4294 mmu_idx
= ARMMMUIdx_E20_0
;
4296 mmu_idx
= ARMMMUIdx_E10_0
;
4299 if (arm_is_secure_below_el3(env
)) {
4300 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4303 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4306 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4309 CPUState
*cs
= env_cpu(env
);
4310 int mask
= vae1_tlbmask(env
);
4312 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4315 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4318 CPUState
*cs
= env_cpu(env
);
4319 int mask
= vae1_tlbmask(env
);
4321 if (tlb_force_broadcast(env
)) {
4322 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4324 tlb_flush_by_mmuidx(cs
, mask
);
4328 static int alle1_tlbmask(CPUARMState
*env
)
4331 * Note that the 'ALL' scope must invalidate both stage 1 and
4332 * stage 2 translations, whereas most other scopes only invalidate
4333 * stage 1 translations.
4335 if (arm_is_secure_below_el3(env
)) {
4336 return ARMMMUIdxBit_SE10_1
|
4337 ARMMMUIdxBit_SE10_1_PAN
|
4338 ARMMMUIdxBit_SE10_0
;
4340 return ARMMMUIdxBit_E10_1
|
4341 ARMMMUIdxBit_E10_1_PAN
|
4346 static int e2_tlbmask(CPUARMState
*env
)
4348 if (arm_is_secure_below_el3(env
)) {
4349 return ARMMMUIdxBit_SE20_0
|
4350 ARMMMUIdxBit_SE20_2
|
4351 ARMMMUIdxBit_SE20_2_PAN
|
4354 return ARMMMUIdxBit_E20_0
|
4355 ARMMMUIdxBit_E20_2
|
4356 ARMMMUIdxBit_E20_2_PAN
|
4361 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4364 CPUState
*cs
= env_cpu(env
);
4365 int mask
= alle1_tlbmask(env
);
4367 tlb_flush_by_mmuidx(cs
, mask
);
4370 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4373 CPUState
*cs
= env_cpu(env
);
4374 int mask
= e2_tlbmask(env
);
4376 tlb_flush_by_mmuidx(cs
, mask
);
4379 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4382 ARMCPU
*cpu
= env_archcpu(env
);
4383 CPUState
*cs
= CPU(cpu
);
4385 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4388 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4391 CPUState
*cs
= env_cpu(env
);
4392 int mask
= alle1_tlbmask(env
);
4394 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4397 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4400 CPUState
*cs
= env_cpu(env
);
4401 int mask
= e2_tlbmask(env
);
4403 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4406 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4409 CPUState
*cs
= env_cpu(env
);
4411 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4414 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4417 /* Invalidate by VA, EL2
4418 * Currently handles both VAE2 and VALE2, since we don't support
4419 * flush-last-level-only.
4421 CPUState
*cs
= env_cpu(env
);
4422 int mask
= e2_tlbmask(env
);
4423 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4425 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4428 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4431 /* Invalidate by VA, EL3
4432 * Currently handles both VAE3 and VALE3, since we don't support
4433 * flush-last-level-only.
4435 ARMCPU
*cpu
= env_archcpu(env
);
4436 CPUState
*cs
= CPU(cpu
);
4437 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4439 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4442 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4445 CPUState
*cs
= env_cpu(env
);
4446 int mask
= vae1_tlbmask(env
);
4447 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4448 int bits
= vae1_tlbbits(env
, pageaddr
);
4450 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4453 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4456 /* Invalidate by VA, EL1&0 (AArch64 version).
4457 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4458 * since we don't support flush-for-specific-ASID-only or
4459 * flush-last-level-only.
4461 CPUState
*cs
= env_cpu(env
);
4462 int mask
= vae1_tlbmask(env
);
4463 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4464 int bits
= vae1_tlbbits(env
, pageaddr
);
4466 if (tlb_force_broadcast(env
)) {
4467 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4469 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4473 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4476 CPUState
*cs
= env_cpu(env
);
4477 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4478 bool secure
= arm_is_secure_below_el3(env
);
4479 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4480 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
,
4483 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4486 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4489 CPUState
*cs
= env_cpu(env
);
4490 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4491 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4493 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4494 ARMMMUIdxBit_SE3
, bits
);
4497 #ifdef TARGET_AARCH64
4503 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4506 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4507 /* Extract one bit to represent the va selector in use. */
4508 uint64_t select
= sextract64(value
, 36, 1);
4509 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4510 TLBIRange ret
= { };
4512 page_size_granule
= extract64(value
, 46, 2);
4514 /* The granule encoded in value must match the granule in use. */
4515 if (page_size_granule
!= (param
.using64k
? 3 : param
.using16k
? 2 : 1)) {
4516 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4521 page_shift
= (page_size_granule
- 1) * 2 + 12;
4522 num
= extract64(value
, 39, 5);
4523 scale
= extract64(value
, 44, 2);
4524 exponent
= (5 * scale
) + 1;
4526 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4529 ret
.base
= sextract64(value
, 0, 37);
4531 ret
.base
= extract64(value
, 0, 37);
4535 * With DS=1, BaseADDR is always shifted 16 so that it is able
4536 * to address all 52 va bits. The input address is perforce
4537 * aligned on a 64k boundary regardless of translation granule.
4541 ret
.base
<<= page_shift
;
4546 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4547 int idxmap
, bool synced
)
4549 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4553 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4554 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4557 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4563 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4564 range
.length
, idxmap
, bits
);
4568 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4569 const ARMCPRegInfo
*ri
,
4573 * Invalidate by VA range, EL1&0.
4574 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4575 * since we don't support flush-for-specific-ASID-only or
4576 * flush-last-level-only.
4579 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4580 tlb_force_broadcast(env
));
4583 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4584 const ARMCPRegInfo
*ri
,
4588 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4589 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4590 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4591 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4592 * shareable specific flushes.
4595 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4598 static int vae2_tlbmask(CPUARMState
*env
)
4600 return (arm_is_secure_below_el3(env
)
4601 ? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
);
4604 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4605 const ARMCPRegInfo
*ri
,
4609 * Invalidate by VA range, EL2.
4610 * Currently handles all of RVAE2 and RVALE2,
4611 * since we don't support flush-for-specific-ASID-only or
4612 * flush-last-level-only.
4615 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4616 tlb_force_broadcast(env
));
4621 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4622 const ARMCPRegInfo
*ri
,
4626 * Invalidate by VA range, Inner/Outer Shareable, EL2.
4627 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
4628 * since we don't support flush-for-specific-ASID-only,
4629 * flush-last-level-only or inner/outer shareable specific flushes.
4632 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
4636 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
4637 const ARMCPRegInfo
*ri
,
4641 * Invalidate by VA range, EL3.
4642 * Currently handles all of RVAE3 and RVALE3,
4643 * since we don't support flush-for-specific-ASID-only or
4644 * flush-last-level-only.
4647 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
,
4648 tlb_force_broadcast(env
));
4651 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
4652 const ARMCPRegInfo
*ri
,
4656 * Invalidate by VA range, EL3, Inner/Outer Shareable.
4657 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
4658 * since we don't support flush-for-specific-ASID-only,
4659 * flush-last-level-only or inner/outer specific flushes.
4662 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
, true);
4666 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4669 int cur_el
= arm_current_el(env
);
4672 uint64_t hcr
= arm_hcr_el2_eff(env
);
4675 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4676 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4677 return CP_ACCESS_TRAP_EL2
;
4680 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4681 return CP_ACCESS_TRAP
;
4683 if (hcr
& HCR_TDZ
) {
4684 return CP_ACCESS_TRAP_EL2
;
4687 } else if (hcr
& HCR_TDZ
) {
4688 return CP_ACCESS_TRAP_EL2
;
4691 return CP_ACCESS_OK
;
4694 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4696 ARMCPU
*cpu
= env_archcpu(env
);
4697 int dzp_bit
= 1 << 4;
4699 /* DZP indicates whether DC ZVA access is allowed */
4700 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4703 return cpu
->dcz_blocksize
| dzp_bit
;
4706 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4709 if (!(env
->pstate
& PSTATE_SP
)) {
4710 /* Access to SP_EL0 is undefined if it's being used as
4711 * the stack pointer.
4713 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4715 return CP_ACCESS_OK
;
4718 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4720 return env
->pstate
& PSTATE_SP
;
4723 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4725 update_spsel(env
, val
);
4728 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4731 ARMCPU
*cpu
= env_archcpu(env
);
4733 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4734 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4738 /* ??? Lots of these bits are not implemented. */
4740 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4741 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4742 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4744 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4745 SCTLR_ATA0
| SCTLR_ATA
);
4749 if (raw_read(env
, ri
) == value
) {
4750 /* Skip the TLB flush if nothing actually changed; Linux likes
4751 * to do a lot of pointless SCTLR writes.
4756 raw_write(env
, ri
, value
);
4758 /* This may enable/disable the MMU, so do a TLB flush. */
4759 tlb_flush(CPU(cpu
));
4761 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4763 * Normally we would always end the TB on an SCTLR write; see the
4764 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4765 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4766 * of hflags from the translator, so do it here.
4768 arm_rebuild_hflags(env
);
4772 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4775 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4778 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4779 /* Minimal set of EL0-visible registers. This will need to be expanded
4780 * significantly for system emulation of AArch64 CPUs.
4782 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4783 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4784 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4785 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4786 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4787 .type
= ARM_CP_NO_RAW
,
4788 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4789 .fieldoffset
= offsetof(CPUARMState
, daif
),
4790 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4791 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4792 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4793 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4794 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4795 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4796 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4797 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4798 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4799 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4800 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4801 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4802 .readfn
= aa64_dczid_read
},
4803 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4804 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4805 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4806 #ifndef CONFIG_USER_ONLY
4807 /* Avoid overhead of an access check that always passes in user-mode */
4808 .accessfn
= aa64_zva_access
,
4811 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4812 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4813 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4814 /* Cache ops: all NOPs since we don't emulate caches */
4815 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4816 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4817 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4818 .accessfn
= aa64_cacheop_pou_access
},
4819 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4820 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4821 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4822 .accessfn
= aa64_cacheop_pou_access
},
4823 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4824 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4825 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4826 .accessfn
= aa64_cacheop_pou_access
},
4827 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4828 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4829 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4830 .type
= ARM_CP_NOP
},
4831 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4832 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4833 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4834 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4835 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4836 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4837 .accessfn
= aa64_cacheop_poc_access
},
4838 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4839 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4840 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4841 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4842 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4843 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4844 .accessfn
= aa64_cacheop_pou_access
},
4845 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4846 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4847 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4848 .accessfn
= aa64_cacheop_poc_access
},
4849 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4850 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4851 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4852 /* TLBI operations */
4853 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4854 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4855 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4856 .writefn
= tlbi_aa64_vmalle1is_write
},
4857 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4858 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4859 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4860 .writefn
= tlbi_aa64_vae1is_write
},
4861 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4862 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4863 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4864 .writefn
= tlbi_aa64_vmalle1is_write
},
4865 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4866 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4867 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4868 .writefn
= tlbi_aa64_vae1is_write
},
4869 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4870 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4871 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4872 .writefn
= tlbi_aa64_vae1is_write
},
4873 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4874 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4875 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4876 .writefn
= tlbi_aa64_vae1is_write
},
4877 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4878 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4879 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4880 .writefn
= tlbi_aa64_vmalle1_write
},
4881 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4882 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4883 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4884 .writefn
= tlbi_aa64_vae1_write
},
4885 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4886 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4887 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4888 .writefn
= tlbi_aa64_vmalle1_write
},
4889 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4890 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4891 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4892 .writefn
= tlbi_aa64_vae1_write
},
4893 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4894 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4895 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4896 .writefn
= tlbi_aa64_vae1_write
},
4897 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4898 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4899 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4900 .writefn
= tlbi_aa64_vae1_write
},
4901 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4902 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4903 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4904 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4905 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4906 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4907 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4908 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4909 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4910 .writefn
= tlbi_aa64_alle1is_write
},
4911 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4912 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4913 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4914 .writefn
= tlbi_aa64_alle1is_write
},
4915 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4916 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4917 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4918 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4919 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4920 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4921 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4922 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4923 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4924 .writefn
= tlbi_aa64_alle1_write
},
4925 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4926 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4927 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4928 .writefn
= tlbi_aa64_alle1is_write
},
4929 #ifndef CONFIG_USER_ONLY
4930 /* 64 bit address translation operations */
4931 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4932 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4933 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4934 .writefn
= ats_write64
},
4935 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4936 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4937 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4938 .writefn
= ats_write64
},
4939 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4940 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4941 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4942 .writefn
= ats_write64
},
4943 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4944 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4945 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4946 .writefn
= ats_write64
},
4947 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4948 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4949 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4950 .writefn
= ats_write64
},
4951 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4952 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4953 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4954 .writefn
= ats_write64
},
4955 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4956 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4957 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4958 .writefn
= ats_write64
},
4959 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4960 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4961 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4962 .writefn
= ats_write64
},
4963 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4964 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4965 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4966 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4967 .writefn
= ats_write64
},
4968 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4969 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4970 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4971 .writefn
= ats_write64
},
4972 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4973 .type
= ARM_CP_ALIAS
,
4974 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4975 .access
= PL1_RW
, .resetvalue
= 0,
4976 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4977 .writefn
= par_write
},
4979 /* TLB invalidate last level of translation table walk */
4980 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4981 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4982 .writefn
= tlbimva_is_write
},
4983 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4984 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4985 .writefn
= tlbimvaa_is_write
},
4986 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4987 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4988 .writefn
= tlbimva_write
},
4989 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4990 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4991 .writefn
= tlbimvaa_write
},
4992 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4993 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4994 .writefn
= tlbimva_hyp_write
},
4995 { .name
= "TLBIMVALHIS",
4996 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4997 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4998 .writefn
= tlbimva_hyp_is_write
},
4999 { .name
= "TLBIIPAS2",
5000 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5001 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5002 { .name
= "TLBIIPAS2IS",
5003 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5004 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5005 { .name
= "TLBIIPAS2L",
5006 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5007 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5008 { .name
= "TLBIIPAS2LIS",
5009 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5010 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5011 /* 32 bit cache operations */
5012 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5013 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5014 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5015 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5016 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5017 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5018 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5019 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5020 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5021 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5022 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5023 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5024 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5025 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5026 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5027 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5028 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5029 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5030 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5031 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5032 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5033 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5034 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5035 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5036 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5037 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5038 /* MMU Domain access control / MPU write buffer control */
5039 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5040 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5041 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5042 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5043 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5044 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5045 .type
= ARM_CP_ALIAS
,
5046 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5048 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5049 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5050 .type
= ARM_CP_ALIAS
,
5051 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5053 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5054 /* We rely on the access checks not allowing the guest to write to the
5055 * state field when SPSel indicates that it's being used as the stack
5058 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5059 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5060 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5061 .type
= ARM_CP_ALIAS
,
5062 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5063 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5064 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5065 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5066 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5067 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5068 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5069 .type
= ARM_CP_NO_RAW
,
5070 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5071 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5072 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5074 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5075 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5076 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5077 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5078 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5079 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5080 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5081 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5082 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5083 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5084 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5085 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5086 .type
= ARM_CP_ALIAS
,
5087 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5089 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5090 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5091 .type
= ARM_CP_ALIAS
,
5092 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5094 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5095 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5096 .type
= ARM_CP_ALIAS
,
5097 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5099 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5100 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5101 .type
= ARM_CP_ALIAS
,
5102 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5104 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5105 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5106 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5108 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5109 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5110 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5111 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5112 .writefn
= sdcr_write
,
5113 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5116 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5118 ARMCPU
*cpu
= env_archcpu(env
);
5120 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5121 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5123 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5126 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5127 valid_mask
&= ~HCR_HCD
;
5128 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5129 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5130 * However, if we're using the SMC PSCI conduit then QEMU is
5131 * effectively acting like EL3 firmware and so the guest at
5132 * EL2 should retain the ability to prevent EL1 from being
5133 * able to make SMC calls into the ersatz firmware, so in
5134 * that case HCR.TSC should be read/write.
5136 valid_mask
&= ~HCR_TSC
;
5139 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5140 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5141 valid_mask
|= HCR_E2H
;
5143 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5144 valid_mask
|= HCR_TERR
| HCR_TEA
;
5146 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5147 valid_mask
|= HCR_TLOR
;
5149 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5150 valid_mask
|= HCR_API
| HCR_APK
;
5152 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5153 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5155 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5156 valid_mask
|= HCR_ENSCXT
;
5160 /* Clear RES0 bits. */
5161 value
&= valid_mask
;
5164 * These bits change the MMU setup:
5165 * HCR_VM enables stage 2 translation
5166 * HCR_PTW forbids certain page-table setups
5167 * HCR_DC disables stage1 and enables stage2 translation
5168 * HCR_DCT enables tagging on (disabled) stage1 translation
5170 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
)) {
5171 tlb_flush(CPU(cpu
));
5173 env
->cp15
.hcr_el2
= value
;
5176 * Updates to VI and VF require us to update the status of
5177 * virtual interrupts, which are the logical OR of these bits
5178 * and the state of the input lines from the GIC. (This requires
5179 * that we have the iothread lock, which is done by marking the
5180 * reginfo structs as ARM_CP_IO.)
5181 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5182 * possible for it to be taken immediately, because VIRQ and
5183 * VFIQ are masked unless running at EL0 or EL1, and HCR
5184 * can only be written at EL2.
5186 g_assert(qemu_mutex_iothread_locked());
5187 arm_cpu_update_virq(cpu
);
5188 arm_cpu_update_vfiq(cpu
);
5189 arm_cpu_update_vserr(cpu
);
5192 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5194 do_hcr_write(env
, value
, 0);
5197 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5200 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5201 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5202 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5205 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5208 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5209 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5210 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5214 * Return the effective value of HCR_EL2.
5215 * Bits that are not included here:
5216 * RW (read from SCR_EL3.RW as needed)
5218 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5220 uint64_t ret
= env
->cp15
.hcr_el2
;
5222 if (!arm_is_el2_enabled(env
)) {
5224 * "This register has no effect if EL2 is not enabled in the
5225 * current Security state". This is ARMv8.4-SecEL2 speak for
5226 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5228 * Prior to that, the language was "In an implementation that
5229 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5230 * as if this field is 0 for all purposes other than a direct
5231 * read or write access of HCR_EL2". With lots of enumeration
5232 * on a per-field basis. In current QEMU, this is condition
5233 * is arm_is_secure_below_el3.
5235 * Since the v8.4 language applies to the entire register, and
5236 * appears to be backward compatible, use that.
5242 * For a cpu that supports both aarch64 and aarch32, we can set bits
5243 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5244 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5246 if (!arm_el_is_aa64(env
, 2)) {
5247 uint64_t aa32_valid
;
5250 * These bits are up-to-date as of ARMv8.6.
5251 * For HCR, it's easiest to list just the 2 bits that are invalid.
5252 * For HCR2, list those that are valid.
5254 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5255 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5256 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5260 if (ret
& HCR_TGE
) {
5261 /* These bits are up-to-date as of ARMv8.6. */
5262 if (ret
& HCR_E2H
) {
5263 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5264 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5265 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5266 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5267 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5268 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5270 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5272 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5273 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5274 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5281 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5285 * For A-profile AArch32 EL3, if NSACR.CP10
5286 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5288 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5289 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5290 value
&= ~(0x3 << 10);
5291 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
5293 env
->cp15
.cptr_el
[2] = value
;
5296 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5299 * For A-profile AArch32 EL3, if NSACR.CP10
5300 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5302 uint64_t value
= env
->cp15
.cptr_el
[2];
5304 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5305 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5311 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5312 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5314 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5315 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5316 .writefn
= hcr_write
},
5317 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5318 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5319 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5320 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5321 .writefn
= hcr_writelow
},
5322 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5323 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5324 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5325 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5326 .type
= ARM_CP_ALIAS
,
5327 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5329 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5330 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5331 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5332 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5333 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5334 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5335 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5336 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5337 .type
= ARM_CP_ALIAS
,
5338 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5340 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5341 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5342 .type
= ARM_CP_ALIAS
,
5343 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5345 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5346 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5347 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5348 .access
= PL2_RW
, .writefn
= vbar_write
,
5349 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5351 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5352 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5353 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5354 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5355 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5356 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5357 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5358 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5359 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5360 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5361 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5362 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5364 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5365 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5366 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5367 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5368 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5369 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5370 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5372 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5373 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5374 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5375 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5377 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5378 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5379 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5381 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5382 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5383 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5385 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5386 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5387 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5388 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5389 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5390 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5391 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5392 .type
= ARM_CP_ALIAS
,
5393 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5394 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5395 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5396 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5398 /* no .writefn needed as this can't cause an ASID change;
5399 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5401 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5402 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5403 .cp
= 15, .opc1
= 6, .crm
= 2,
5404 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5405 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5406 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5407 .writefn
= vttbr_write
},
5408 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5409 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5410 .access
= PL2_RW
, .writefn
= vttbr_write
,
5411 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5412 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5413 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5414 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5415 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5416 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5417 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5418 .access
= PL2_RW
, .resetvalue
= 0,
5419 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5420 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5421 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5422 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5423 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5424 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5425 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5426 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5427 { .name
= "TLBIALLNSNH",
5428 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5429 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5430 .writefn
= tlbiall_nsnh_write
},
5431 { .name
= "TLBIALLNSNHIS",
5432 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5433 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5434 .writefn
= tlbiall_nsnh_is_write
},
5435 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5436 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5437 .writefn
= tlbiall_hyp_write
},
5438 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5439 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5440 .writefn
= tlbiall_hyp_is_write
},
5441 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5442 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5443 .writefn
= tlbimva_hyp_write
},
5444 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5445 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5446 .writefn
= tlbimva_hyp_is_write
},
5447 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5448 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5449 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5450 .writefn
= tlbi_aa64_alle2_write
},
5451 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5452 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5453 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5454 .writefn
= tlbi_aa64_vae2_write
},
5455 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5456 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5457 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5458 .writefn
= tlbi_aa64_vae2_write
},
5459 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5460 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5461 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5462 .writefn
= tlbi_aa64_alle2is_write
},
5463 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5464 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5465 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5466 .writefn
= tlbi_aa64_vae2is_write
},
5467 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5468 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5469 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5470 .writefn
= tlbi_aa64_vae2is_write
},
5471 #ifndef CONFIG_USER_ONLY
5472 /* Unlike the other EL2-related AT operations, these must
5473 * UNDEF from EL3 if EL2 is not implemented, which is why we
5474 * define them here rather than with the rest of the AT ops.
5476 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5477 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5478 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5479 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5480 .writefn
= ats_write64
},
5481 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5482 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5483 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5484 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5485 .writefn
= ats_write64
},
5486 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5487 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5488 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5489 * to behave as if SCR.NS was 1.
5491 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5493 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5494 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5496 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5497 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5498 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5499 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5500 * reset values as IMPDEF. We choose to reset to 3 to comply with
5501 * both ARMv7 and ARMv8.
5503 .access
= PL2_RW
, .resetvalue
= 3,
5504 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5505 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5506 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5507 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5508 .writefn
= gt_cntvoff_write
,
5509 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5510 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5511 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5512 .writefn
= gt_cntvoff_write
,
5513 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5514 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5515 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5516 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5517 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5518 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5519 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5520 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5521 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5522 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5523 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5524 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5525 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5526 .resetfn
= gt_hyp_timer_reset
,
5527 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5528 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5530 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5532 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5534 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5536 /* The only field of MDCR_EL2 that has a defined architectural reset value
5537 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
5539 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5540 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5541 .access
= PL2_RW
, .resetvalue
= PMCR_NUM_COUNTERS
,
5542 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5543 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5544 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5545 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5546 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5547 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5548 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5550 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5551 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5552 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5554 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5557 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5558 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5559 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5560 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5562 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5563 .writefn
= hcr_writehigh
},
5566 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5569 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5570 return CP_ACCESS_OK
;
5572 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5575 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5576 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5578 .access
= PL2_RW
, .accessfn
= sel2_access
,
5579 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5580 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5581 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5582 .access
= PL2_RW
, .accessfn
= sel2_access
,
5583 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5586 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5589 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5590 * At Secure EL1 it traps to EL3 or EL2.
5592 if (arm_current_el(env
) == 3) {
5593 return CP_ACCESS_OK
;
5595 if (arm_is_secure_below_el3(env
)) {
5596 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5597 return CP_ACCESS_TRAP_EL2
;
5599 return CP_ACCESS_TRAP_EL3
;
5601 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5603 return CP_ACCESS_OK
;
5605 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5608 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5609 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5610 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5611 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5612 .resetfn
= scr_reset
, .writefn
= scr_write
},
5613 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5614 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5615 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5616 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5617 .writefn
= scr_write
},
5618 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5619 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5620 .access
= PL3_RW
, .resetvalue
= 0,
5621 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5623 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5624 .access
= PL3_RW
, .resetvalue
= 0,
5625 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5626 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5627 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5628 .writefn
= vbar_write
, .resetvalue
= 0,
5629 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5630 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5631 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5632 .access
= PL3_RW
, .resetvalue
= 0,
5633 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5634 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5635 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5637 /* no .writefn needed as this can't cause an ASID change;
5638 * we must provide a .raw_writefn and .resetfn because we handle
5639 * reset and migration for the AArch32 TTBCR(S), which might be
5640 * using mask and base_mask.
5642 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5643 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5644 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5645 .type
= ARM_CP_ALIAS
,
5646 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5648 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5649 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5650 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5651 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5652 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5653 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5654 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5655 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5656 .type
= ARM_CP_ALIAS
,
5657 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5659 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5660 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5661 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5662 .access
= PL3_RW
, .writefn
= vbar_write
,
5663 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5665 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5666 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5667 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5668 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5669 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5670 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5671 .access
= PL3_RW
, .resetvalue
= 0,
5672 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5673 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5674 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5675 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5677 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5678 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5679 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5681 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5682 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5683 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5685 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5686 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5687 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5688 .writefn
= tlbi_aa64_alle3is_write
},
5689 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5690 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5691 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5692 .writefn
= tlbi_aa64_vae3is_write
},
5693 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5694 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5695 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5696 .writefn
= tlbi_aa64_vae3is_write
},
5697 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5698 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5699 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5700 .writefn
= tlbi_aa64_alle3_write
},
5701 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5702 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5703 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5704 .writefn
= tlbi_aa64_vae3_write
},
5705 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5706 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5707 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5708 .writefn
= tlbi_aa64_vae3_write
},
5711 #ifndef CONFIG_USER_ONLY
5712 /* Test if system register redirection is to occur in the current state. */
5713 static bool redirect_for_e2h(CPUARMState
*env
)
5715 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5718 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5722 if (redirect_for_e2h(env
)) {
5723 /* Switch to the saved EL2 version of the register. */
5725 readfn
= ri
->readfn
;
5727 readfn
= ri
->orig_readfn
;
5729 if (readfn
== NULL
) {
5732 return readfn(env
, ri
);
5735 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5740 if (redirect_for_e2h(env
)) {
5741 /* Switch to the saved EL2 version of the register. */
5743 writefn
= ri
->writefn
;
5745 writefn
= ri
->orig_writefn
;
5747 if (writefn
== NULL
) {
5748 writefn
= raw_write
;
5750 writefn(env
, ri
, value
);
5753 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5756 uint32_t src_key
, dst_key
, new_key
;
5757 const char *src_name
, *dst_name
, *new_name
;
5758 bool (*feature
)(const ARMISARegisters
*id
);
5761 #define K(op0, op1, crn, crm, op2) \
5762 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5764 static const struct E2HAlias aliases
[] = {
5765 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5766 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5767 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5768 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5769 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5770 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5771 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5772 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5773 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5774 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5775 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5776 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5777 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5778 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5779 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5780 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5781 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5782 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5783 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5784 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5785 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5786 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5787 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5788 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5789 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5790 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5791 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5792 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5793 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5794 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5795 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5796 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5799 * Note that redirection of ZCR is mentioned in the description
5800 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5801 * not in the summary table.
5803 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5804 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5806 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5807 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5809 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
5810 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
5811 isar_feature_aa64_scxtnum
},
5813 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5814 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5820 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5821 const struct E2HAlias
*a
= &aliases
[i
];
5822 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
5825 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5829 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5830 (gpointer
)(uintptr_t)a
->src_key
);
5831 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5832 (gpointer
)(uintptr_t)a
->dst_key
);
5833 g_assert(src_reg
!= NULL
);
5834 g_assert(dst_reg
!= NULL
);
5836 /* Cross-compare names to detect typos in the keys. */
5837 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5838 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5840 /* None of the core system registers use opaque; we will. */
5841 g_assert(src_reg
->opaque
== NULL
);
5843 /* Create alias before redirection so we dup the right data. */
5844 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5846 new_reg
->name
= a
->new_name
;
5847 new_reg
->type
|= ARM_CP_ALIAS
;
5848 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5849 new_reg
->access
&= PL2_RW
| PL3_RW
;
5851 ok
= g_hash_table_insert(cpu
->cp_regs
,
5852 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
5855 src_reg
->opaque
= dst_reg
;
5856 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5857 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5858 if (!src_reg
->raw_readfn
) {
5859 src_reg
->raw_readfn
= raw_read
;
5861 if (!src_reg
->raw_writefn
) {
5862 src_reg
->raw_writefn
= raw_write
;
5864 src_reg
->readfn
= el2_e2h_read
;
5865 src_reg
->writefn
= el2_e2h_write
;
5870 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5873 int cur_el
= arm_current_el(env
);
5876 uint64_t hcr
= arm_hcr_el2_eff(env
);
5879 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5880 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5881 return CP_ACCESS_TRAP_EL2
;
5884 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5885 return CP_ACCESS_TRAP
;
5887 if (hcr
& HCR_TID2
) {
5888 return CP_ACCESS_TRAP_EL2
;
5891 } else if (hcr
& HCR_TID2
) {
5892 return CP_ACCESS_TRAP_EL2
;
5896 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5897 return CP_ACCESS_TRAP_EL2
;
5900 return CP_ACCESS_OK
;
5903 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5906 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5907 * read via a bit in OSLSR_EL1.
5911 if (ri
->state
== ARM_CP_STATE_AA32
) {
5912 oslock
= (value
== 0xC5ACCE55);
5917 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5920 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5921 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5922 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5923 * unlike DBGDRAR it is never accessible from EL0.
5924 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5927 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5928 .access
= PL0_R
, .accessfn
= access_tdra
,
5929 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5930 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5931 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5932 .access
= PL1_R
, .accessfn
= access_tdra
,
5933 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5934 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5935 .access
= PL0_R
, .accessfn
= access_tdra
,
5936 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5937 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5938 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5939 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5940 .access
= PL1_RW
, .accessfn
= access_tda
,
5941 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5944 * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external
5945 * Debug Communication Channel is not implemented.
5947 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_AA64
,
5948 .opc0
= 2, .opc1
= 3, .crn
= 0, .crm
= 1, .opc2
= 0,
5949 .access
= PL0_R
, .accessfn
= access_tda
,
5950 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5952 * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
5953 * it is unlikely a guest will care.
5954 * We don't implement the configurable EL0 access.
5956 { .name
= "DBGDSCRint", .state
= ARM_CP_STATE_AA32
,
5957 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5958 .type
= ARM_CP_ALIAS
,
5959 .access
= PL1_R
, .accessfn
= access_tda
,
5960 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5961 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5962 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5963 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5964 .accessfn
= access_tdosa
,
5965 .writefn
= oslar_write
},
5966 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5967 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5968 .access
= PL1_R
, .resetvalue
= 10,
5969 .accessfn
= access_tdosa
,
5970 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5971 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5972 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5973 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5974 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5975 .type
= ARM_CP_NOP
},
5976 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5977 * implement vector catch debug events yet.
5980 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5981 .access
= PL1_RW
, .accessfn
= access_tda
,
5982 .type
= ARM_CP_NOP
},
5983 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5984 * to save and restore a 32-bit guest's DBGVCR)
5986 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5987 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5988 .access
= PL2_RW
, .accessfn
= access_tda
,
5989 .type
= ARM_CP_NOP
| ARM_CP_EL3_NO_EL2_KEEP
},
5990 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5991 * Channel but Linux may try to access this register. The 32-bit
5992 * alias is DBGDCCINT.
5994 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5995 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5996 .access
= PL1_RW
, .accessfn
= access_tda
,
5997 .type
= ARM_CP_NOP
},
6000 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
6001 /* 64 bit access versions of the (dummy) debug registers */
6002 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
6003 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6004 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
6005 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6009 * Check for traps to RAS registers, which are controlled
6010 * by HCR_EL2.TERR and SCR_EL3.TERR.
6012 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6015 int el
= arm_current_el(env
);
6017 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6018 return CP_ACCESS_TRAP_EL2
;
6020 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6021 return CP_ACCESS_TRAP_EL3
;
6023 return CP_ACCESS_OK
;
6026 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6028 int el
= arm_current_el(env
);
6030 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6031 return env
->cp15
.vdisr_el2
;
6033 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6034 return 0; /* RAZ/WI */
6036 return env
->cp15
.disr_el1
;
6039 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6041 int el
= arm_current_el(env
);
6043 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6044 env
->cp15
.vdisr_el2
= val
;
6047 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6048 return; /* RAZ/WI */
6050 env
->cp15
.disr_el1
= val
;
6054 * Minimal RAS implementation with no Error Records.
6055 * Which means that all of the Error Record registers:
6063 * ERXPFGCDN_EL1 (RASv1p1)
6064 * ERXPFGCTL_EL1 (RASv1p1)
6065 * ERXPFGF_EL1 (RASv1p1)
6069 * may generate UNDEFINED, which is the effect we get by not
6070 * listing them at all.
6072 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6073 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6074 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6075 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6076 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6077 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6078 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6079 .access
= PL1_R
, .accessfn
= access_terr
,
6080 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6081 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6082 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6083 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6084 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6085 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6086 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6089 /* Return the exception level to which exceptions should be taken
6090 * via SVEAccessTrap. If an exception should be routed through
6091 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6092 * take care of raising that exception.
6093 * C.f. the ARM pseudocode function CheckSVEEnabled.
6095 int sve_exception_el(CPUARMState
*env
, int el
)
6097 #ifndef CONFIG_USER_ONLY
6098 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
6100 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6101 /* Check CPACR.ZEN. */
6102 switch (extract32(env
->cp15
.cpacr_el1
, 16, 2)) {
6111 return hcr_el2
& HCR_TGE
? 2 : 1;
6114 /* Check CPACR.FPEN. */
6115 switch (extract32(env
->cp15
.cpacr_el1
, 20, 2)) {
6128 * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE).
6131 if (hcr_el2
& HCR_E2H
) {
6132 /* Check CPTR_EL2.ZEN. */
6133 switch (extract32(env
->cp15
.cptr_el
[2], 16, 2)) {
6135 if (el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
6144 /* Check CPTR_EL2.FPEN. */
6145 switch (extract32(env
->cp15
.cptr_el
[2], 20, 2)) {
6147 if (el
== 2 || !(hcr_el2
& HCR_TGE
)) {
6155 } else if (arm_is_el2_enabled(env
)) {
6156 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
6159 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
6165 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6166 if (arm_feature(env
, ARM_FEATURE_EL3
)
6167 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
6174 uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
6178 start_len
= MIN(start_len
, ARM_MAX_VQ
- 1);
6179 end_len
= start_len
;
6181 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
6182 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
6183 assert(end_len
< start_len
);
6189 * Given that SVE is enabled, return the vector length for EL.
6191 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
6193 ARMCPU
*cpu
= env_archcpu(env
);
6194 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
6197 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6198 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
6200 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6201 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
6203 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6204 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
6207 return aarch64_sve_zcr_get_valid_len(cpu
, zcr_len
);
6210 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6213 int cur_el
= arm_current_el(env
);
6214 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
6217 /* Bits other than [3:0] are RAZ/WI. */
6218 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6219 raw_write(env
, ri
, value
& 0xf);
6222 * Because we arrived here, we know both FP and SVE are enabled;
6223 * otherwise we would have trapped access to the ZCR_ELn register.
6225 new_len
= sve_zcr_len_for_el(env
, cur_el
);
6226 if (new_len
< old_len
) {
6227 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6231 static const ARMCPRegInfo zcr_reginfo
[] = {
6232 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6233 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6234 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6235 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6236 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6237 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6238 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6239 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6240 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6241 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6242 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6243 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6244 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6245 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6246 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6249 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6251 CPUARMState
*env
= &cpu
->env
;
6253 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6254 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6256 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6258 if (env
->cpu_watchpoint
[n
]) {
6259 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6260 env
->cpu_watchpoint
[n
] = NULL
;
6263 if (!FIELD_EX64(wcr
, DBGWCR
, E
)) {
6264 /* E bit clear : watchpoint disabled */
6268 switch (FIELD_EX64(wcr
, DBGWCR
, LSC
)) {
6270 /* LSC 00 is reserved and must behave as if the wp is disabled */
6273 flags
|= BP_MEM_READ
;
6276 flags
|= BP_MEM_WRITE
;
6279 flags
|= BP_MEM_ACCESS
;
6283 /* Attempts to use both MASK and BAS fields simultaneously are
6284 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6285 * thus generating a watchpoint for every byte in the masked region.
6287 mask
= FIELD_EX64(wcr
, DBGWCR
, MASK
);
6288 if (mask
== 1 || mask
== 2) {
6289 /* Reserved values of MASK; we must act as if the mask value was
6290 * some non-reserved value, or as if the watchpoint were disabled.
6291 * We choose the latter.
6295 /* Watchpoint covers an aligned area up to 2GB in size */
6297 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6298 * whether the watchpoint fires when the unmasked bits match; we opt
6299 * to generate the exceptions.
6303 /* Watchpoint covers bytes defined by the byte address select bits */
6304 int bas
= FIELD_EX64(wcr
, DBGWCR
, BAS
);
6307 if (extract64(wvr
, 2, 1)) {
6308 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6309 * ignored, and BAS[3:0] define which bytes to watch.
6315 /* This must act as if the watchpoint is disabled */
6319 /* The BAS bits are supposed to be programmed to indicate a contiguous
6320 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6321 * we fire for each byte in the word/doubleword addressed by the WVR.
6322 * We choose to ignore any non-zero bits after the first range of 1s.
6324 basstart
= ctz32(bas
);
6325 len
= cto32(bas
>> basstart
);
6329 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6330 &env
->cpu_watchpoint
[n
]);
6333 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6336 CPUARMState
*env
= &cpu
->env
;
6338 /* Completely clear out existing QEMU watchpoints and our array, to
6339 * avoid possible stale entries following migration load.
6341 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6342 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6344 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6345 hw_watchpoint_update(cpu
, i
);
6349 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6352 ARMCPU
*cpu
= env_archcpu(env
);
6356 * Bits [1:0] are RES0.
6358 * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
6359 * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
6360 * they contain the value written. It is CONSTRAINED UNPREDICTABLE
6361 * whether the RESS bits are ignored when comparing an address.
6363 * Therefore we are allowed to compare the entire register, which lets
6364 * us avoid considering whether or not FEAT_LVA is actually enabled.
6368 raw_write(env
, ri
, value
);
6369 hw_watchpoint_update(cpu
, i
);
6372 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6375 ARMCPU
*cpu
= env_archcpu(env
);
6378 raw_write(env
, ri
, value
);
6379 hw_watchpoint_update(cpu
, i
);
6382 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6384 CPUARMState
*env
= &cpu
->env
;
6385 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6386 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6391 if (env
->cpu_breakpoint
[n
]) {
6392 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6393 env
->cpu_breakpoint
[n
] = NULL
;
6396 if (!extract64(bcr
, 0, 1)) {
6397 /* E bit clear : watchpoint disabled */
6401 bt
= extract64(bcr
, 20, 4);
6404 case 4: /* unlinked address mismatch (reserved if AArch64) */
6405 case 5: /* linked address mismatch (reserved if AArch64) */
6406 qemu_log_mask(LOG_UNIMP
,
6407 "arm: address mismatch breakpoint types not implemented\n");
6409 case 0: /* unlinked address match */
6410 case 1: /* linked address match */
6413 * Bits [1:0] are RES0.
6415 * It is IMPLEMENTATION DEFINED whether bits [63:49]
6416 * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
6417 * of the VA field ([48] or [52] for FEAT_LVA), or whether the
6418 * value is read as written. It is CONSTRAINED UNPREDICTABLE
6419 * whether the RESS bits are ignored when comparing an address.
6420 * Therefore we are allowed to compare the entire register, which
6421 * lets us avoid considering whether FEAT_LVA is actually enabled.
6423 * The BAS field is used to allow setting breakpoints on 16-bit
6424 * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6425 * a bp will fire if the addresses covered by the bp and the addresses
6426 * covered by the insn overlap but the insn doesn't start at the
6427 * start of the bp address range. We choose to require the insn and
6428 * the bp to have the same address. The constraints on writing to
6429 * BAS enforced in dbgbcr_write mean we have only four cases:
6430 * 0b0000 => no breakpoint
6431 * 0b0011 => breakpoint on addr
6432 * 0b1100 => breakpoint on addr + 2
6433 * 0b1111 => breakpoint on addr
6434 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6436 int bas
= extract64(bcr
, 5, 4);
6446 case 2: /* unlinked context ID match */
6447 case 8: /* unlinked VMID match (reserved if no EL2) */
6448 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6449 qemu_log_mask(LOG_UNIMP
,
6450 "arm: unlinked context breakpoint types not implemented\n");
6452 case 9: /* linked VMID match (reserved if no EL2) */
6453 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6454 case 3: /* linked context ID match */
6456 /* We must generate no events for Linked context matches (unless
6457 * they are linked to by some other bp/wp, which is handled in
6458 * updates for the linking bp/wp). We choose to also generate no events
6459 * for reserved values.
6464 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6467 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6470 CPUARMState
*env
= &cpu
->env
;
6472 /* Completely clear out existing QEMU breakpoints and our array, to
6473 * avoid possible stale entries following migration load.
6475 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6476 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6478 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6479 hw_breakpoint_update(cpu
, i
);
6483 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6486 ARMCPU
*cpu
= env_archcpu(env
);
6489 raw_write(env
, ri
, value
);
6490 hw_breakpoint_update(cpu
, i
);
6493 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6496 ARMCPU
*cpu
= env_archcpu(env
);
6499 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6502 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6503 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6505 raw_write(env
, ri
, value
);
6506 hw_breakpoint_update(cpu
, i
);
6509 static void define_debug_regs(ARMCPU
*cpu
)
6511 /* Define v7 and v8 architectural debug registers.
6512 * These are just dummy implementations for now.
6515 int wrps
, brps
, ctx_cmps
;
6518 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
6519 * use AArch32. Given that bit 15 is RES1, if the value is 0 then
6520 * the register must not exist for this cpu.
6522 if (cpu
->isar
.dbgdidr
!= 0) {
6523 ARMCPRegInfo dbgdidr
= {
6524 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0,
6525 .opc1
= 0, .opc2
= 0,
6526 .access
= PL0_R
, .accessfn
= access_tda
,
6527 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6529 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6532 /* Note that all these register fields hold "number of Xs minus 1". */
6533 brps
= arm_num_brps(cpu
);
6534 wrps
= arm_num_wrps(cpu
);
6535 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6537 assert(ctx_cmps
<= brps
);
6539 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6541 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6542 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6545 for (i
= 0; i
< brps
; i
++) {
6546 ARMCPRegInfo dbgregs
[] = {
6547 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
6548 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6549 .access
= PL1_RW
, .accessfn
= access_tda
,
6550 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6551 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6553 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
6554 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6555 .access
= PL1_RW
, .accessfn
= access_tda
,
6556 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6557 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6560 define_arm_cp_regs(cpu
, dbgregs
);
6563 for (i
= 0; i
< wrps
; i
++) {
6564 ARMCPRegInfo dbgregs
[] = {
6565 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
6566 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6567 .access
= PL1_RW
, .accessfn
= access_tda
,
6568 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6569 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6571 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
6572 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6573 .access
= PL1_RW
, .accessfn
= access_tda
,
6574 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6575 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6578 define_arm_cp_regs(cpu
, dbgregs
);
6582 static void define_pmu_regs(ARMCPU
*cpu
)
6585 * v7 performance monitor control register: same implementor
6586 * field as main ID register, and we implement four counters in
6587 * addition to the cycle count register.
6589 unsigned int i
, pmcrn
= PMCR_NUM_COUNTERS
;
6590 ARMCPRegInfo pmcr
= {
6591 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6593 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6594 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6595 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6596 .raw_writefn
= raw_write
,
6598 ARMCPRegInfo pmcr64
= {
6599 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6600 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6601 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6603 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6604 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
) |
6606 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6608 define_one_arm_cp_reg(cpu
, &pmcr
);
6609 define_one_arm_cp_reg(cpu
, &pmcr64
);
6610 for (i
= 0; i
< pmcrn
; i
++) {
6611 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6612 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6613 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6614 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6615 ARMCPRegInfo pmev_regs
[] = {
6616 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6617 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6618 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6619 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6620 .accessfn
= pmreg_access_xevcntr
},
6621 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6622 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6623 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6625 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6626 .raw_readfn
= pmevcntr_rawread
,
6627 .raw_writefn
= pmevcntr_rawwrite
},
6628 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6629 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6630 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6631 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6632 .accessfn
= pmreg_access
},
6633 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6634 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6635 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6637 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6638 .raw_writefn
= pmevtyper_rawwrite
},
6640 define_arm_cp_regs(cpu
, pmev_regs
);
6641 g_free(pmevcntr_name
);
6642 g_free(pmevcntr_el0_name
);
6643 g_free(pmevtyper_name
);
6644 g_free(pmevtyper_el0_name
);
6646 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6647 ARMCPRegInfo v81_pmu_regs
[] = {
6648 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6649 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6650 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6651 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6652 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6653 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6654 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6655 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6657 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6659 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6660 static const ARMCPRegInfo v84_pmmir
= {
6661 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6662 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6663 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6666 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6670 /* We don't know until after realize whether there's a GICv3
6671 * attached, and that is what registers the gicv3 sysregs.
6672 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6675 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6677 ARMCPU
*cpu
= env_archcpu(env
);
6678 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6680 if (env
->gicv3state
) {
6686 #ifndef CONFIG_USER_ONLY
6687 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6689 ARMCPU
*cpu
= env_archcpu(env
);
6690 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6692 if (env
->gicv3state
) {
6699 /* Shared logic between LORID and the rest of the LOR* registers.
6700 * Secure state exclusion has already been dealt with.
6702 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6703 const ARMCPRegInfo
*ri
, bool isread
)
6705 int el
= arm_current_el(env
);
6707 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6708 return CP_ACCESS_TRAP_EL2
;
6710 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6711 return CP_ACCESS_TRAP_EL3
;
6713 return CP_ACCESS_OK
;
6716 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6717 const ARMCPRegInfo
*ri
, bool isread
)
6719 if (arm_is_secure_below_el3(env
)) {
6720 /* Access denied in secure mode. */
6721 return CP_ACCESS_TRAP
;
6723 return access_lor_ns(env
, ri
, isread
);
6727 * A trivial implementation of ARMv8.1-LOR leaves all of these
6728 * registers fixed at 0, which indicates that there are zero
6729 * supported Limited Ordering regions.
6731 static const ARMCPRegInfo lor_reginfo
[] = {
6732 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6733 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6734 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6735 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6736 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6737 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6738 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6739 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6740 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6741 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6742 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6743 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6744 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6745 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6746 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6747 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6748 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6749 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6750 .access
= PL1_R
, .accessfn
= access_lor_ns
,
6751 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6754 #ifdef TARGET_AARCH64
6755 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6758 int el
= arm_current_el(env
);
6761 arm_feature(env
, ARM_FEATURE_EL2
) &&
6762 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6763 return CP_ACCESS_TRAP_EL2
;
6766 arm_feature(env
, ARM_FEATURE_EL3
) &&
6767 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6768 return CP_ACCESS_TRAP_EL3
;
6770 return CP_ACCESS_OK
;
6773 static const ARMCPRegInfo pauth_reginfo
[] = {
6774 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6775 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6776 .access
= PL1_RW
, .accessfn
= access_pauth
,
6777 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6778 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6779 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6780 .access
= PL1_RW
, .accessfn
= access_pauth
,
6781 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6782 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6783 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6784 .access
= PL1_RW
, .accessfn
= access_pauth
,
6785 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6786 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6787 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6788 .access
= PL1_RW
, .accessfn
= access_pauth
,
6789 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6790 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6791 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6792 .access
= PL1_RW
, .accessfn
= access_pauth
,
6793 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6794 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6795 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6796 .access
= PL1_RW
, .accessfn
= access_pauth
,
6797 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6798 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6799 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6800 .access
= PL1_RW
, .accessfn
= access_pauth
,
6801 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6802 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6803 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6804 .access
= PL1_RW
, .accessfn
= access_pauth
,
6805 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6806 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6807 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6808 .access
= PL1_RW
, .accessfn
= access_pauth
,
6809 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6810 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6811 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6812 .access
= PL1_RW
, .accessfn
= access_pauth
,
6813 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6816 static const ARMCPRegInfo tlbirange_reginfo
[] = {
6817 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
6818 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
6819 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6820 .writefn
= tlbi_aa64_rvae1is_write
},
6821 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
6822 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
6823 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6824 .writefn
= tlbi_aa64_rvae1is_write
},
6825 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
6826 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
6827 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6828 .writefn
= tlbi_aa64_rvae1is_write
},
6829 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
6830 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
6831 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6832 .writefn
= tlbi_aa64_rvae1is_write
},
6833 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
6834 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
6835 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6836 .writefn
= tlbi_aa64_rvae1is_write
},
6837 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
6838 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
6839 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6840 .writefn
= tlbi_aa64_rvae1is_write
},
6841 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
6842 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
6843 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6844 .writefn
= tlbi_aa64_rvae1is_write
},
6845 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
6846 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
6847 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6848 .writefn
= tlbi_aa64_rvae1is_write
},
6849 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
6850 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
6851 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6852 .writefn
= tlbi_aa64_rvae1_write
},
6853 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
6854 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
6855 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6856 .writefn
= tlbi_aa64_rvae1_write
},
6857 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
6858 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
6859 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6860 .writefn
= tlbi_aa64_rvae1_write
},
6861 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
6862 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
6863 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6864 .writefn
= tlbi_aa64_rvae1_write
},
6865 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
6866 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
6867 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6868 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
6869 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
6870 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6871 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
6872 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
6873 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6874 .writefn
= tlbi_aa64_rvae2is_write
},
6875 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
6876 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
6877 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6878 .writefn
= tlbi_aa64_rvae2is_write
},
6879 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
6880 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
6881 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6882 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
6883 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
6884 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6885 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
6886 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
6887 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6888 .writefn
= tlbi_aa64_rvae2is_write
},
6889 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
6890 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
6891 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6892 .writefn
= tlbi_aa64_rvae2is_write
},
6893 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
6894 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
6895 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6896 .writefn
= tlbi_aa64_rvae2_write
},
6897 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
6898 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
6899 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6900 .writefn
= tlbi_aa64_rvae2_write
},
6901 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
6902 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
6903 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6904 .writefn
= tlbi_aa64_rvae3is_write
},
6905 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
6906 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
6907 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6908 .writefn
= tlbi_aa64_rvae3is_write
},
6909 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
6910 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
6911 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6912 .writefn
= tlbi_aa64_rvae3is_write
},
6913 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
6914 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
6915 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6916 .writefn
= tlbi_aa64_rvae3is_write
},
6917 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
6918 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
6919 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6920 .writefn
= tlbi_aa64_rvae3_write
},
6921 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
6922 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
6923 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6924 .writefn
= tlbi_aa64_rvae3_write
},
6927 static const ARMCPRegInfo tlbios_reginfo
[] = {
6928 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
6929 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
6930 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6931 .writefn
= tlbi_aa64_vmalle1is_write
},
6932 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
6933 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
6934 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6935 .writefn
= tlbi_aa64_vae1is_write
},
6936 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
6937 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
6938 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6939 .writefn
= tlbi_aa64_vmalle1is_write
},
6940 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
6941 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
6942 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6943 .writefn
= tlbi_aa64_vae1is_write
},
6944 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
6945 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
6946 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6947 .writefn
= tlbi_aa64_vae1is_write
},
6948 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
6949 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
6950 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6951 .writefn
= tlbi_aa64_vae1is_write
},
6952 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
6953 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
6954 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6955 .writefn
= tlbi_aa64_alle2is_write
},
6956 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
6957 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
6958 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6959 .writefn
= tlbi_aa64_vae2is_write
},
6960 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
6961 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
6962 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
6963 .writefn
= tlbi_aa64_alle1is_write
},
6964 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
6965 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
6966 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6967 .writefn
= tlbi_aa64_vae2is_write
},
6968 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
6969 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
6970 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
6971 .writefn
= tlbi_aa64_alle1is_write
},
6972 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
6973 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
6974 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6975 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
6976 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
6977 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6978 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
6979 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
6980 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6981 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
6982 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
6983 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6984 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
6985 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
6986 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6987 .writefn
= tlbi_aa64_alle3is_write
},
6988 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
6989 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
6990 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6991 .writefn
= tlbi_aa64_vae3is_write
},
6992 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
6993 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
6994 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6995 .writefn
= tlbi_aa64_vae3is_write
},
6998 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7003 /* Success sets NZCV = 0000. */
7004 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7006 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7008 * ??? Failed, for unknown reasons in the crypto subsystem.
7009 * The best we can do is log the reason and return the
7010 * timed-out indication to the guest. There is no reason
7011 * we know to expect this failure to be transitory, so the
7012 * guest may well hang retrying the operation.
7014 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7015 ri
->name
, error_get_pretty(err
));
7018 env
->ZF
= 0; /* NZCF = 0100 */
7024 /* We do not support re-seeding, so the two registers operate the same. */
7025 static const ARMCPRegInfo rndr_reginfo
[] = {
7026 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7027 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7028 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7029 .access
= PL0_R
, .readfn
= rndr_readfn
},
7030 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7031 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7032 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7033 .access
= PL0_R
, .readfn
= rndr_readfn
},
7036 #ifndef CONFIG_USER_ONLY
7037 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7040 ARMCPU
*cpu
= env_archcpu(env
);
7041 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7042 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7043 uint64_t vaddr_in
= (uint64_t) value
;
7044 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7046 int mem_idx
= cpu_mmu_index(env
, false);
7048 /* This won't be crossing page boundaries */
7049 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7055 /* RCU lock is already being held */
7056 mr
= memory_region_from_host(haddr
, &offset
);
7059 memory_region_writeback(mr
, offset
, dline_size
);
7064 static const ARMCPRegInfo dcpop_reg
[] = {
7065 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7066 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7067 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7068 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7071 static const ARMCPRegInfo dcpodp_reg
[] = {
7072 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7073 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7074 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7075 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7077 #endif /*CONFIG_USER_ONLY*/
7079 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7082 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7083 return CP_ACCESS_TRAP_EL2
;
7086 return CP_ACCESS_OK
;
7089 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7092 int el
= arm_current_el(env
);
7094 if (el
< 2 && arm_is_el2_enabled(env
)) {
7095 uint64_t hcr
= arm_hcr_el2_eff(env
);
7096 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7097 return CP_ACCESS_TRAP_EL2
;
7101 arm_feature(env
, ARM_FEATURE_EL3
) &&
7102 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7103 return CP_ACCESS_TRAP_EL3
;
7105 return CP_ACCESS_OK
;
7108 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7110 return env
->pstate
& PSTATE_TCO
;
7113 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7115 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7118 static const ARMCPRegInfo mte_reginfo
[] = {
7119 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7120 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7121 .access
= PL1_RW
, .accessfn
= access_mte
,
7122 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7123 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7124 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7125 .access
= PL1_RW
, .accessfn
= access_mte
,
7126 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7127 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7128 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7129 .access
= PL2_RW
, .accessfn
= access_mte
,
7130 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7131 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7132 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7134 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7135 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7136 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7137 .access
= PL1_RW
, .accessfn
= access_mte
,
7138 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7139 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7140 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7141 .access
= PL1_RW
, .accessfn
= access_mte
,
7142 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7143 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7144 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7145 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7146 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7147 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7148 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7149 .type
= ARM_CP_NO_RAW
,
7150 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7151 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7152 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7153 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7154 .accessfn
= aa64_cacheop_poc_access
},
7155 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7156 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7157 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7158 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7159 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7160 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7161 .accessfn
= aa64_cacheop_poc_access
},
7162 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7163 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7164 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7165 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7166 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7167 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7168 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7169 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7170 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7171 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7172 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7173 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7174 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7175 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7176 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7179 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7180 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7181 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7182 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7185 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7186 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7187 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7188 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7189 .accessfn
= aa64_cacheop_poc_access
},
7190 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7191 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7192 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7193 .accessfn
= aa64_cacheop_poc_access
},
7194 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7195 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7196 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7197 .accessfn
= aa64_cacheop_poc_access
},
7198 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7199 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7200 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7201 .accessfn
= aa64_cacheop_poc_access
},
7202 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7203 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7204 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7205 .accessfn
= aa64_cacheop_poc_access
},
7206 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7207 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7208 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7209 .accessfn
= aa64_cacheop_poc_access
},
7210 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7211 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7212 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7213 .accessfn
= aa64_cacheop_poc_access
},
7214 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7215 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7216 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7217 .accessfn
= aa64_cacheop_poc_access
},
7218 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7219 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7220 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7221 #ifndef CONFIG_USER_ONLY
7222 /* Avoid overhead of an access check that always passes in user-mode */
7223 .accessfn
= aa64_zva_access
,
7226 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7227 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7228 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7229 #ifndef CONFIG_USER_ONLY
7230 /* Avoid overhead of an access check that always passes in user-mode */
7231 .accessfn
= aa64_zva_access
,
7236 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7239 uint64_t hcr
= arm_hcr_el2_eff(env
);
7240 int el
= arm_current_el(env
);
7242 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7243 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7244 if (hcr
& HCR_TGE
) {
7245 return CP_ACCESS_TRAP_EL2
;
7247 return CP_ACCESS_TRAP
;
7249 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7250 return CP_ACCESS_TRAP_EL2
;
7252 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7253 return CP_ACCESS_TRAP_EL2
;
7256 && arm_feature(env
, ARM_FEATURE_EL3
)
7257 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7258 return CP_ACCESS_TRAP_EL3
;
7260 return CP_ACCESS_OK
;
7263 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7264 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7265 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7266 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7267 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7268 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7269 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7270 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7271 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7272 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7273 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7274 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7275 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7276 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7277 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7279 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7281 #endif /* TARGET_AARCH64 */
7283 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7286 int el
= arm_current_el(env
);
7289 uint64_t sctlr
= arm_sctlr(env
, el
);
7290 if (!(sctlr
& SCTLR_EnRCTX
)) {
7291 return CP_ACCESS_TRAP
;
7293 } else if (el
== 1) {
7294 uint64_t hcr
= arm_hcr_el2_eff(env
);
7296 return CP_ACCESS_TRAP_EL2
;
7299 return CP_ACCESS_OK
;
7302 static const ARMCPRegInfo predinv_reginfo
[] = {
7303 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7304 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7305 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7306 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7307 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7308 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7309 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7310 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7311 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7313 * Note the AArch32 opcodes have a different OPC1.
7315 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7316 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7317 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7318 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7319 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7320 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7321 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7322 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7323 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7326 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7328 /* Read the high 32 bits of the current CCSIDR */
7329 return extract64(ccsidr_read(env
, ri
), 32, 32);
7332 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7333 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7334 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7336 .accessfn
= access_aa64_tid2
,
7337 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7340 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7343 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7344 return CP_ACCESS_TRAP_EL2
;
7347 return CP_ACCESS_OK
;
7350 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7353 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7354 return access_aa64_tid3(env
, ri
, isread
);
7357 return CP_ACCESS_OK
;
7360 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7363 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7364 return CP_ACCESS_TRAP_EL2
;
7367 return CP_ACCESS_OK
;
7370 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7371 const ARMCPRegInfo
*ri
, bool isread
)
7374 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7375 * in v7A, not in v8A.
7377 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7378 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7379 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7380 return CP_ACCESS_TRAP_EL2
;
7382 return CP_ACCESS_OK
;
7385 static const ARMCPRegInfo jazelle_regs
[] = {
7387 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7388 .access
= PL1_R
, .accessfn
= access_jazelle
,
7389 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7391 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7392 .accessfn
= access_joscr_jmcr
,
7393 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7395 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7396 .accessfn
= access_joscr_jmcr
,
7397 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7400 static const ARMCPRegInfo contextidr_el2
= {
7401 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7402 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7404 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7407 static const ARMCPRegInfo vhe_reginfo
[] = {
7408 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7409 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7410 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7411 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7412 #ifndef CONFIG_USER_ONLY
7413 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7414 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7416 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7417 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7418 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7419 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7420 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7421 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7422 .resetfn
= gt_hv_timer_reset
,
7423 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7424 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7426 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7428 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7429 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7430 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7431 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7432 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7433 .access
= PL2_RW
, .accessfn
= e2h_access
,
7434 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7435 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7436 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7437 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7438 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7439 .access
= PL2_RW
, .accessfn
= e2h_access
,
7440 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7441 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7442 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7443 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7444 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7445 .access
= PL2_RW
, .accessfn
= e2h_access
,
7446 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7447 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7448 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7449 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7450 .access
= PL2_RW
, .accessfn
= e2h_access
,
7451 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7452 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7453 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7454 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7455 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7456 .access
= PL2_RW
, .accessfn
= e2h_access
,
7457 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7458 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7459 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7460 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7461 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7462 .access
= PL2_RW
, .accessfn
= e2h_access
,
7463 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7467 #ifndef CONFIG_USER_ONLY
7468 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7469 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7470 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7471 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7472 .writefn
= ats_write64
},
7473 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7474 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7475 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7476 .writefn
= ats_write64
},
7479 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7480 { .name
= "ATS1CPRP",
7481 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7482 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7483 .writefn
= ats_write
},
7484 { .name
= "ATS1CPWP",
7485 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7486 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7487 .writefn
= ats_write
},
7492 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7493 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7494 * is non-zero, which is never for ARMv7, optionally in ARMv8
7495 * and mandatorily for ARMv8.2 and up.
7496 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7497 * implementation is RAZ/WI we can ignore this detail, as we
7500 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7501 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7502 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7503 .access
= PL1_RW
, .accessfn
= access_tacr
,
7504 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7505 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7506 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7507 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7511 void register_cp_regs_for_features(ARMCPU
*cpu
)
7513 /* Register all the coprocessor registers based on feature bits */
7514 CPUARMState
*env
= &cpu
->env
;
7515 if (arm_feature(env
, ARM_FEATURE_M
)) {
7516 /* M profile has no coprocessor registers */
7520 define_arm_cp_regs(cpu
, cp_reginfo
);
7521 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7522 /* Must go early as it is full of wildcards that may be
7523 * overridden by later definitions.
7525 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7528 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7529 /* The ID registers all have impdef reset values */
7530 ARMCPRegInfo v6_idregs
[] = {
7531 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7532 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7533 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7534 .accessfn
= access_aa32_tid3
,
7535 .resetvalue
= cpu
->isar
.id_pfr0
},
7536 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7537 * the value of the GIC field until after we define these regs.
7539 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7540 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7541 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7542 .accessfn
= access_aa32_tid3
,
7543 .readfn
= id_pfr1_read
,
7544 .writefn
= arm_cp_write_ignore
},
7545 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7546 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7547 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7548 .accessfn
= access_aa32_tid3
,
7549 .resetvalue
= cpu
->isar
.id_dfr0
},
7550 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7551 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7552 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7553 .accessfn
= access_aa32_tid3
,
7554 .resetvalue
= cpu
->id_afr0
},
7555 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7556 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7557 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7558 .accessfn
= access_aa32_tid3
,
7559 .resetvalue
= cpu
->isar
.id_mmfr0
},
7560 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7561 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7562 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7563 .accessfn
= access_aa32_tid3
,
7564 .resetvalue
= cpu
->isar
.id_mmfr1
},
7565 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7566 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7567 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7568 .accessfn
= access_aa32_tid3
,
7569 .resetvalue
= cpu
->isar
.id_mmfr2
},
7570 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7571 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7572 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7573 .accessfn
= access_aa32_tid3
,
7574 .resetvalue
= cpu
->isar
.id_mmfr3
},
7575 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7576 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7577 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7578 .accessfn
= access_aa32_tid3
,
7579 .resetvalue
= cpu
->isar
.id_isar0
},
7580 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7581 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7582 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7583 .accessfn
= access_aa32_tid3
,
7584 .resetvalue
= cpu
->isar
.id_isar1
},
7585 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7586 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7587 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7588 .accessfn
= access_aa32_tid3
,
7589 .resetvalue
= cpu
->isar
.id_isar2
},
7590 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7591 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7592 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7593 .accessfn
= access_aa32_tid3
,
7594 .resetvalue
= cpu
->isar
.id_isar3
},
7595 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7596 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7597 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7598 .accessfn
= access_aa32_tid3
,
7599 .resetvalue
= cpu
->isar
.id_isar4
},
7600 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7601 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7602 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7603 .accessfn
= access_aa32_tid3
,
7604 .resetvalue
= cpu
->isar
.id_isar5
},
7605 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7606 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7607 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7608 .accessfn
= access_aa32_tid3
,
7609 .resetvalue
= cpu
->isar
.id_mmfr4
},
7610 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7611 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7612 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7613 .accessfn
= access_aa32_tid3
,
7614 .resetvalue
= cpu
->isar
.id_isar6
},
7616 define_arm_cp_regs(cpu
, v6_idregs
);
7617 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7619 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7621 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7622 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7624 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7625 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7626 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7628 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7629 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7631 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7632 ARMCPRegInfo clidr
= {
7633 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7634 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7635 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7636 .accessfn
= access_aa64_tid2
,
7637 .resetvalue
= cpu
->clidr
7639 define_one_arm_cp_reg(cpu
, &clidr
);
7640 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7641 define_debug_regs(cpu
);
7642 define_pmu_regs(cpu
);
7644 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7646 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7647 /* AArch64 ID registers, which all have impdef reset values.
7648 * Note that within the ID register ranges the unused slots
7649 * must all RAZ, not UNDEF; future architecture versions may
7650 * define new registers here.
7652 ARMCPRegInfo v8_idregs
[] = {
7654 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7655 * emulation because we don't know the right value for the
7656 * GIC field until after we define these regs.
7658 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7659 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7661 #ifdef CONFIG_USER_ONLY
7662 .type
= ARM_CP_CONST
,
7663 .resetvalue
= cpu
->isar
.id_aa64pfr0
7665 .type
= ARM_CP_NO_RAW
,
7666 .accessfn
= access_aa64_tid3
,
7667 .readfn
= id_aa64pfr0_read
,
7668 .writefn
= arm_cp_write_ignore
7671 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7672 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7673 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7674 .accessfn
= access_aa64_tid3
,
7675 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7676 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7677 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7678 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7679 .accessfn
= access_aa64_tid3
,
7681 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7682 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7683 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7684 .accessfn
= access_aa64_tid3
,
7686 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7687 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7688 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7689 .accessfn
= access_aa64_tid3
,
7690 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
7691 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7692 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7693 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7694 .accessfn
= access_aa64_tid3
,
7696 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7697 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7698 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7699 .accessfn
= access_aa64_tid3
,
7701 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7702 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7703 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7704 .accessfn
= access_aa64_tid3
,
7706 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7707 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7708 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7709 .accessfn
= access_aa64_tid3
,
7710 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7711 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7712 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7713 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7714 .accessfn
= access_aa64_tid3
,
7715 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7716 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7717 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7718 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7719 .accessfn
= access_aa64_tid3
,
7721 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7722 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7723 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7724 .accessfn
= access_aa64_tid3
,
7726 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7727 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7728 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7729 .accessfn
= access_aa64_tid3
,
7730 .resetvalue
= cpu
->id_aa64afr0
},
7731 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7732 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7733 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7734 .accessfn
= access_aa64_tid3
,
7735 .resetvalue
= cpu
->id_aa64afr1
},
7736 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7737 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7738 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7739 .accessfn
= access_aa64_tid3
,
7741 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7742 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7743 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7744 .accessfn
= access_aa64_tid3
,
7746 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7747 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7748 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7749 .accessfn
= access_aa64_tid3
,
7750 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7751 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7752 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7753 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7754 .accessfn
= access_aa64_tid3
,
7755 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7756 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7757 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7758 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7759 .accessfn
= access_aa64_tid3
,
7761 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7762 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7763 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7764 .accessfn
= access_aa64_tid3
,
7766 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7767 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7768 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7769 .accessfn
= access_aa64_tid3
,
7771 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7772 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7773 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7774 .accessfn
= access_aa64_tid3
,
7776 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7777 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7778 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7779 .accessfn
= access_aa64_tid3
,
7781 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7782 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7783 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7784 .accessfn
= access_aa64_tid3
,
7786 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7787 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7788 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7789 .accessfn
= access_aa64_tid3
,
7790 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7791 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7792 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7793 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7794 .accessfn
= access_aa64_tid3
,
7795 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7796 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7797 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7798 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7799 .accessfn
= access_aa64_tid3
,
7800 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7801 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7802 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7803 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7804 .accessfn
= access_aa64_tid3
,
7806 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7807 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7808 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7809 .accessfn
= access_aa64_tid3
,
7811 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7812 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7813 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7814 .accessfn
= access_aa64_tid3
,
7816 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7817 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7818 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7819 .accessfn
= access_aa64_tid3
,
7821 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7822 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7823 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7824 .accessfn
= access_aa64_tid3
,
7826 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7827 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7828 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7829 .accessfn
= access_aa64_tid3
,
7830 .resetvalue
= cpu
->isar
.mvfr0
},
7831 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7832 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7833 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7834 .accessfn
= access_aa64_tid3
,
7835 .resetvalue
= cpu
->isar
.mvfr1
},
7836 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7837 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7838 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7839 .accessfn
= access_aa64_tid3
,
7840 .resetvalue
= cpu
->isar
.mvfr2
},
7841 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7842 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7843 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7844 .accessfn
= access_aa64_tid3
,
7846 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
7847 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7848 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7849 .accessfn
= access_aa64_tid3
,
7850 .resetvalue
= cpu
->isar
.id_pfr2
},
7851 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7852 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7853 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7854 .accessfn
= access_aa64_tid3
,
7856 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7857 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7858 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7859 .accessfn
= access_aa64_tid3
,
7861 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7862 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7863 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7864 .accessfn
= access_aa64_tid3
,
7866 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7867 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7868 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7869 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7870 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7871 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7872 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7873 .resetvalue
= cpu
->pmceid0
},
7874 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7875 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7876 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7877 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7878 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7879 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7880 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7881 .resetvalue
= cpu
->pmceid1
},
7883 #ifdef CONFIG_USER_ONLY
7884 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7885 { .name
= "ID_AA64PFR0_EL1",
7886 .exported_bits
= 0x000f000f00ff0000,
7887 .fixed_bits
= 0x0000000000000011 },
7888 { .name
= "ID_AA64PFR1_EL1",
7889 .exported_bits
= 0x00000000000000f0 },
7890 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7892 { .name
= "ID_AA64ZFR0_EL1" },
7893 { .name
= "ID_AA64MMFR0_EL1",
7894 .fixed_bits
= 0x00000000ff000000 },
7895 { .name
= "ID_AA64MMFR1_EL1" },
7896 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7898 { .name
= "ID_AA64DFR0_EL1",
7899 .fixed_bits
= 0x0000000000000006 },
7900 { .name
= "ID_AA64DFR1_EL1" },
7901 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7903 { .name
= "ID_AA64AFR*",
7905 { .name
= "ID_AA64ISAR0_EL1",
7906 .exported_bits
= 0x00fffffff0fffff0 },
7907 { .name
= "ID_AA64ISAR1_EL1",
7908 .exported_bits
= 0x000000f0ffffffff },
7909 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7912 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7914 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7915 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7916 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7917 ARMCPRegInfo rvbar
= {
7918 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7919 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7921 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7923 define_one_arm_cp_reg(cpu
, &rvbar
);
7925 define_arm_cp_regs(cpu
, v8_idregs
);
7926 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7930 * Register the base EL2 cpregs.
7931 * Pre v8, these registers are implemented only as part of the
7932 * Virtualization Extensions (EL2 present). Beginning with v8,
7933 * if EL2 is missing but EL3 is enabled, mostly these become
7934 * RES0 from EL3, with some specific exceptions.
7936 if (arm_feature(env
, ARM_FEATURE_EL2
)
7937 || (arm_feature(env
, ARM_FEATURE_EL3
)
7938 && arm_feature(env
, ARM_FEATURE_V8
))) {
7939 uint64_t vmpidr_def
= mpidr_read_val(env
);
7940 ARMCPRegInfo vpidr_regs
[] = {
7941 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7942 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7943 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7944 .resetvalue
= cpu
->midr
,
7945 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7946 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7947 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7948 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7949 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7950 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
7951 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7952 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7953 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7954 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7955 .resetvalue
= vmpidr_def
,
7956 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7957 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7958 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7959 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7960 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
7961 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
7962 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7964 define_arm_cp_regs(cpu
, vpidr_regs
);
7965 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7966 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7967 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7969 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
7970 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
7972 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7973 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7974 ARMCPRegInfo rvbar
= {
7975 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7976 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7978 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7980 define_one_arm_cp_reg(cpu
, &rvbar
);
7984 /* Register the base EL3 cpregs. */
7985 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7986 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7987 ARMCPRegInfo el3_regs
[] = {
7988 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7989 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7991 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7993 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7994 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7996 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7997 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7998 .resetvalue
= cpu
->reset_sctlr
},
8001 define_arm_cp_regs(cpu
, el3_regs
);
8003 /* The behaviour of NSACR is sufficiently various that we don't
8004 * try to describe it in a single reginfo:
8005 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8006 * reads as constant 0xc00 from NS EL1 and NS EL2
8007 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8008 * if v7 without EL3, register doesn't exist
8009 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8011 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8012 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8013 static const ARMCPRegInfo nsacr
= {
8014 .name
= "NSACR", .type
= ARM_CP_CONST
,
8015 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8016 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8019 define_one_arm_cp_reg(cpu
, &nsacr
);
8021 static const ARMCPRegInfo nsacr
= {
8023 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8024 .access
= PL3_RW
| PL1_R
,
8026 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8028 define_one_arm_cp_reg(cpu
, &nsacr
);
8031 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8032 static const ARMCPRegInfo nsacr
= {
8033 .name
= "NSACR", .type
= ARM_CP_CONST
,
8034 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8038 define_one_arm_cp_reg(cpu
, &nsacr
);
8042 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8043 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8044 /* PMSAv6 not implemented */
8045 assert(arm_feature(env
, ARM_FEATURE_V7
));
8046 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8047 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8049 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8052 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8053 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8054 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8055 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8056 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8059 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8060 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8062 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8063 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8065 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8066 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8068 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8069 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8071 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8072 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8074 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8075 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8077 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8078 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8080 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8081 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8083 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8084 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8086 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8087 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8089 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8090 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8092 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8093 define_arm_cp_regs(cpu
, jazelle_regs
);
8095 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
8096 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8097 * be read-only (ie write causes UNDEF exception).
8100 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8101 /* Pre-v8 MIDR space.
8102 * Note that the MIDR isn't a simple constant register because
8103 * of the TI925 behaviour where writes to another register can
8104 * cause the MIDR value to change.
8106 * Unimplemented registers in the c15 0 0 0 space default to
8107 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8108 * and friends override accordingly.
8111 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8112 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8113 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8114 .readfn
= midr_read
,
8115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8116 .type
= ARM_CP_OVERRIDE
},
8117 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8119 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8120 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8122 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8123 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8125 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8126 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8128 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8129 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8131 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8132 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8134 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8135 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8136 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8137 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8138 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8139 .readfn
= midr_read
},
8140 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
8141 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8142 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8143 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8144 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8145 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8146 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8147 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8148 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8150 .accessfn
= access_aa64_tid1
,
8151 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8153 ARMCPRegInfo id_cp_reginfo
[] = {
8154 /* These are common to v8 and pre-v8 */
8156 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8157 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8158 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8159 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8160 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8161 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8162 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8163 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8165 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8167 .accessfn
= access_aa32_tid1
,
8168 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8170 /* TLBTR is specific to VMSA */
8171 ARMCPRegInfo id_tlbtr_reginfo
= {
8173 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8175 .accessfn
= access_aa32_tid1
,
8176 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8178 /* MPUIR is specific to PMSA V6+ */
8179 ARMCPRegInfo id_mpuir_reginfo
= {
8181 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8182 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8183 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8185 static const ARMCPRegInfo crn0_wi_reginfo
= {
8186 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8187 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8188 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8190 #ifdef CONFIG_USER_ONLY
8191 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8192 { .name
= "MIDR_EL1",
8193 .exported_bits
= 0x00000000ffffffff },
8194 { .name
= "REVIDR_EL1" },
8196 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8198 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8199 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8201 /* Register the blanket "writes ignored" value first to cover the
8202 * whole space. Then update the specific ID registers to allow write
8203 * access, so that they ignore writes rather than causing them to
8206 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8207 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8208 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8210 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8211 id_cp_reginfo
[i
].access
= PL1_RW
;
8213 id_mpuir_reginfo
.access
= PL1_RW
;
8214 id_tlbtr_reginfo
.access
= PL1_RW
;
8216 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8217 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8219 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8221 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8222 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8223 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8224 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8225 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8229 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8230 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8231 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8232 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8233 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8235 #ifdef CONFIG_USER_ONLY
8236 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8237 { .name
= "MPIDR_EL1",
8238 .fixed_bits
= 0x0000000080000000 },
8240 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8242 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8245 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8246 ARMCPRegInfo auxcr_reginfo
[] = {
8247 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8248 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8249 .access
= PL1_RW
, .accessfn
= access_tacr
,
8250 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8251 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8252 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8253 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8255 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8256 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8257 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8260 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8261 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8262 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8266 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8268 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8269 * There are two flavours:
8270 * (1) older 32-bit only cores have a simple 32-bit CBAR
8271 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8272 * 32-bit register visible to AArch32 at a different encoding
8273 * to the "flavour 1" register and with the bits rearranged to
8274 * be able to squash a 64-bit address into the 32-bit view.
8275 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8276 * in future if we support AArch32-only configs of some of the
8277 * AArch64 cores we might need to add a specific feature flag
8278 * to indicate cores with "flavour 2" CBAR.
8280 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8281 /* 32 bit view is [31:18] 0...0 [43:32]. */
8282 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8283 | extract64(cpu
->reset_cbar
, 32, 12);
8284 ARMCPRegInfo cbar_reginfo
[] = {
8286 .type
= ARM_CP_CONST
,
8287 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8288 .access
= PL1_R
, .resetvalue
= cbar32
},
8289 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8290 .type
= ARM_CP_CONST
,
8291 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8292 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8294 /* We don't implement a r/w 64 bit CBAR currently */
8295 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8296 define_arm_cp_regs(cpu
, cbar_reginfo
);
8298 ARMCPRegInfo cbar
= {
8300 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8301 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8302 .fieldoffset
= offsetof(CPUARMState
,
8303 cp15
.c15_config_base_address
)
8305 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8306 cbar
.access
= PL1_R
;
8307 cbar
.fieldoffset
= 0;
8308 cbar
.type
= ARM_CP_CONST
;
8310 define_one_arm_cp_reg(cpu
, &cbar
);
8314 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8315 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
8316 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8317 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8318 .access
= PL1_RW
, .writefn
= vbar_write
,
8319 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8320 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8323 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8326 /* Generic registers whose values depend on the implementation */
8328 ARMCPRegInfo sctlr
= {
8329 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8330 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8331 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8332 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8333 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8334 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8335 .raw_writefn
= raw_write
,
8337 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8338 /* Normally we would always end the TB on an SCTLR write, but Linux
8339 * arch/arm/mach-pxa/sleep.S expects two instructions following
8340 * an MMU enable to execute from cache. Imitate this behaviour.
8342 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8344 define_one_arm_cp_reg(cpu
, &sctlr
);
8347 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8348 define_arm_cp_regs(cpu
, lor_reginfo
);
8350 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8351 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8353 #ifndef CONFIG_USER_ONLY
8354 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8355 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8357 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8358 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8361 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8362 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8365 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8366 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8368 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8369 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8371 if (cpu_isar_feature(any_ras
, cpu
)) {
8372 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
8375 if (cpu_isar_feature(aa64_vh
, cpu
) ||
8376 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
8377 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
8379 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8380 define_arm_cp_regs(cpu
, vhe_reginfo
);
8383 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8384 define_arm_cp_regs(cpu
, zcr_reginfo
);
8387 #ifdef TARGET_AARCH64
8388 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8389 define_arm_cp_regs(cpu
, pauth_reginfo
);
8391 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8392 define_arm_cp_regs(cpu
, rndr_reginfo
);
8394 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8395 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8397 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8398 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8400 #ifndef CONFIG_USER_ONLY
8401 /* Data Cache clean instructions up to PoP */
8402 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8403 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8405 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8406 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8409 #endif /*CONFIG_USER_ONLY*/
8412 * If full MTE is enabled, add all of the system registers.
8413 * If only "instructions available at EL0" are enabled,
8414 * then define only a RAZ/WI version of PSTATE.TCO.
8416 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8417 define_arm_cp_regs(cpu
, mte_reginfo
);
8418 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8419 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8420 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8421 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8424 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
8425 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
8429 if (cpu_isar_feature(any_predinv
, cpu
)) {
8430 define_arm_cp_regs(cpu
, predinv_reginfo
);
8433 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8434 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8437 #ifndef CONFIG_USER_ONLY
8439 * Register redirections and aliases must be done last,
8440 * after the registers from the other extensions have been defined.
8442 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8443 define_arm_vh_e2h_redirects_aliases(cpu
);
8448 /* Sort alphabetically by type name, except for "any". */
8449 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8451 ObjectClass
*class_a
= (ObjectClass
*)a
;
8452 ObjectClass
*class_b
= (ObjectClass
*)b
;
8453 const char *name_a
, *name_b
;
8455 name_a
= object_class_get_name(class_a
);
8456 name_b
= object_class_get_name(class_b
);
8457 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8459 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8462 return strcmp(name_a
, name_b
);
8466 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8468 ObjectClass
*oc
= data
;
8469 const char *typename
;
8472 typename
= object_class_get_name(oc
);
8473 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8474 qemu_printf(" %s\n", name
);
8478 void arm_cpu_list(void)
8482 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8483 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8484 qemu_printf("Available CPUs:\n");
8485 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8489 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8491 ObjectClass
*oc
= data
;
8492 CpuDefinitionInfoList
**cpu_list
= user_data
;
8493 CpuDefinitionInfo
*info
;
8494 const char *typename
;
8496 typename
= object_class_get_name(oc
);
8497 info
= g_malloc0(sizeof(*info
));
8498 info
->name
= g_strndup(typename
,
8499 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8500 info
->q_typename
= g_strdup(typename
);
8502 QAPI_LIST_PREPEND(*cpu_list
, info
);
8505 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8507 CpuDefinitionInfoList
*cpu_list
= NULL
;
8510 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8511 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8518 * Private utility function for define_one_arm_cp_reg_with_opaque():
8519 * add a single reginfo struct to the hash table.
8521 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8522 void *opaque
, CPState state
,
8523 CPSecureState secstate
,
8524 int crm
, int opc1
, int opc2
,
8527 CPUARMState
*env
= &cpu
->env
;
8530 bool is64
= r
->type
& ARM_CP_64BIT
;
8531 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
8537 case ARM_CP_STATE_AA32
:
8538 /* We assume it is a cp15 register if the .cp field is left unset. */
8539 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
8542 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
8544 case ARM_CP_STATE_AA64
:
8546 * To allow abbreviation of ARMCPRegInfo definitions, we treat
8547 * cp == 0 as equivalent to the value for "standard guest-visible
8548 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
8549 * in their AArch64 view (the .cp value may be non-zero for the
8550 * benefit of the AArch32 view).
8552 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8553 cp
= CP_REG_ARM64_SYSREG_CP
;
8555 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
8558 g_assert_not_reached();
8561 /* Overriding of an existing definition must be explicitly requested. */
8562 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8563 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
8565 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
8570 * Eliminate registers that are not present because the EL is missing.
8571 * Doing this here makes it easier to put all registers for a given
8572 * feature into the same ARMCPRegInfo array and define them all at once.
8575 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8577 * An EL2 register without EL2 but with EL3 is (usually) RES0.
8578 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
8580 int min_el
= ctz32(r
->access
) / 2;
8581 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
8582 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
8585 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
8588 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
8590 if ((r
->access
& max_el
) == 0) {
8595 /* Combine cpreg and name into one allocation. */
8596 name_len
= strlen(name
) + 1;
8597 r2
= g_malloc(sizeof(*r2
) + name_len
);
8599 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
8602 * Update fields to match the instantiation, overwiting wildcards
8603 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
8610 r2
->secure
= secstate
;
8612 r2
->opaque
= opaque
;
8616 /* This should not have been a very special register to begin. */
8617 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
8618 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
8620 * Set the special function to CONST, retaining the other flags.
8621 * This is important for e.g. ARM_CP_SVE so that we still
8622 * take the SVE trap if CPTR_EL3.EZ == 0.
8624 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
8626 * Usually, these registers become RES0, but there are a few
8627 * special cases like VPIDR_EL2 which have a constant non-zero
8628 * value with writes ignored.
8630 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
8634 * ARM_CP_CONST has precedence, so removing the callbacks and
8635 * offsets are not strictly necessary, but it is potentially
8636 * less confusing to debug later.
8640 r2
->raw_readfn
= NULL
;
8641 r2
->raw_writefn
= NULL
;
8643 r2
->fieldoffset
= 0;
8644 r2
->bank_fieldoffsets
[0] = 0;
8645 r2
->bank_fieldoffsets
[1] = 0;
8647 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
8651 * Register is banked (using both entries in array).
8652 * Overwriting fieldoffset as the array is only used to define
8653 * banked registers but later only fieldoffset is used.
8655 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8657 if (state
== ARM_CP_STATE_AA32
) {
8660 * If the register is banked then we don't need to migrate or
8661 * reset the 32-bit instance in certain cases:
8663 * 1) If the register has both 32-bit and 64-bit instances
8664 * then we can count on the 64-bit instance taking care
8665 * of the non-secure bank.
8666 * 2) If ARMv8 is enabled then we can count on a 64-bit
8667 * version taking care of the secure bank. This requires
8668 * that separate 32 and 64-bit definitions are provided.
8670 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8671 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
8672 r2
->type
|= ARM_CP_ALIAS
;
8674 } else if ((secstate
!= r
->secure
) && !ns
) {
8676 * The register is not banked so we only want to allow
8677 * migration of the non-secure instance.
8679 r2
->type
|= ARM_CP_ALIAS
;
8682 if (HOST_BIG_ENDIAN
&&
8683 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
8684 r2
->fieldoffset
+= sizeof(uint32_t);
8690 * By convention, for wildcarded registers only the first
8691 * entry is used for migration; the others are marked as
8692 * ALIAS so we don't try to transfer the register
8693 * multiple times. Special registers (ie NOP/WFI) are
8694 * never migratable and not even raw-accessible.
8696 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
8697 r2
->type
|= ARM_CP_NO_RAW
;
8699 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8700 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8701 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8702 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8706 * Check that raw accesses are either forbidden or handled. Note that
8707 * we can't assert this earlier because the setup of fieldoffset for
8708 * banked registers has to be done first.
8710 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8711 assert(!raw_accessors_invalid(r2
));
8714 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
8718 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8719 const ARMCPRegInfo
*r
, void *opaque
)
8721 /* Define implementations of coprocessor registers.
8722 * We store these in a hashtable because typically
8723 * there are less than 150 registers in a space which
8724 * is 16*16*16*8*8 = 262144 in size.
8725 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8726 * If a register is defined twice then the second definition is
8727 * used, so this can be used to define some generic registers and
8728 * then override them with implementation specific variations.
8729 * At least one of the original and the second definition should
8730 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8731 * against accidental use.
8733 * The state field defines whether the register is to be
8734 * visible in the AArch32 or AArch64 execution state. If the
8735 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8736 * reginfo structure for the AArch32 view, which sees the lower
8737 * 32 bits of the 64 bit register.
8739 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8740 * be wildcarded. AArch64 registers are always considered to be 64
8741 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8742 * the register, if any.
8744 int crm
, opc1
, opc2
;
8745 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8746 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8747 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8748 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8749 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8750 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8753 /* 64 bit registers have only CRm and Opc1 fields */
8754 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8755 /* op0 only exists in the AArch64 encodings */
8756 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8757 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8758 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8760 * This API is only for Arm's system coprocessors (14 and 15) or
8761 * (M-profile or v7A-and-earlier only) for implementation defined
8762 * coprocessors in the range 0..7. Our decode assumes this, since
8763 * 8..13 can be used for other insns including VFP and Neon. See
8764 * valid_cp() in translate.c. Assert here that we haven't tried
8765 * to use an invalid coprocessor number.
8768 case ARM_CP_STATE_BOTH
:
8769 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8774 case ARM_CP_STATE_AA32
:
8775 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8776 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8777 assert(r
->cp
>= 14 && r
->cp
<= 15);
8779 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8782 case ARM_CP_STATE_AA64
:
8783 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8786 g_assert_not_reached();
8788 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8789 * encodes a minimum access level for the register. We roll this
8790 * runtime check into our general permission check code, so check
8791 * here that the reginfo's specified permissions are strict enough
8792 * to encompass the generic architectural permission check.
8794 if (r
->state
!= ARM_CP_STATE_AA32
) {
8795 CPAccessRights mask
;
8798 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8799 mask
= PL0U_R
| PL1_RW
;
8819 /* min_EL EL1, secure mode only (we don't check the latter) */
8823 /* broken reginfo with out-of-range opc1 */
8824 g_assert_not_reached();
8826 /* assert our permissions are not too lax (stricter is fine) */
8827 assert((r
->access
& ~mask
) == 0);
8830 /* Check that the register definition has enough info to handle
8831 * reads and writes if they are permitted.
8833 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
8834 if (r
->access
& PL3_R
) {
8835 assert((r
->fieldoffset
||
8836 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8839 if (r
->access
& PL3_W
) {
8840 assert((r
->fieldoffset
||
8841 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8846 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8847 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8848 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8849 for (state
= ARM_CP_STATE_AA32
;
8850 state
<= ARM_CP_STATE_AA64
; state
++) {
8851 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8854 if (state
== ARM_CP_STATE_AA32
) {
8855 /* Under AArch32 CP registers can be common
8856 * (same for secure and non-secure world) or banked.
8860 switch (r
->secure
) {
8861 case ARM_CP_SECSTATE_S
:
8862 case ARM_CP_SECSTATE_NS
:
8863 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8864 r
->secure
, crm
, opc1
, opc2
,
8867 case ARM_CP_SECSTATE_BOTH
:
8868 name
= g_strdup_printf("%s_S", r
->name
);
8869 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8871 crm
, opc1
, opc2
, name
);
8873 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8875 crm
, opc1
, opc2
, r
->name
);
8878 g_assert_not_reached();
8881 /* AArch64 registers get mapped to non-secure instance
8883 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8885 crm
, opc1
, opc2
, r
->name
);
8893 /* Define a whole list of registers */
8894 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
8895 void *opaque
, size_t len
)
8898 for (i
= 0; i
< len
; ++i
) {
8899 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
8904 * Modify ARMCPRegInfo for access from userspace.
8906 * This is a data driven modification directed by
8907 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8908 * user-space cannot alter any values and dynamic values pertaining to
8909 * execution state are hidden from user space view anyway.
8911 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
8912 const ARMCPRegUserSpaceInfo
*mods
,
8915 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
8916 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
8917 GPatternSpec
*pat
= NULL
;
8920 pat
= g_pattern_spec_new(m
->name
);
8922 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
8923 ARMCPRegInfo
*r
= regs
+ ri
;
8925 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8926 r
->type
= ARM_CP_CONST
;
8930 } else if (strcmp(r
->name
, m
->name
) == 0) {
8931 r
->type
= ARM_CP_CONST
;
8933 r
->resetvalue
&= m
->exported_bits
;
8934 r
->resetvalue
|= m
->fixed_bits
;
8939 g_pattern_spec_free(pat
);
8944 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8946 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
8949 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8952 /* Helper coprocessor write function for write-ignore registers */
8955 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8957 /* Helper coprocessor write function for read-as-zero registers */
8961 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8963 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8966 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8968 /* Return true if it is not valid for us to switch to
8969 * this CPU mode (ie all the UNPREDICTABLE cases in
8970 * the ARM ARM CPSRWriteByInstr pseudocode).
8973 /* Changes to or from Hyp via MSR and CPS are illegal. */
8974 if (write_type
== CPSRWriteByInstr
&&
8975 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8976 mode
== ARM_CPU_MODE_HYP
)) {
8981 case ARM_CPU_MODE_USR
:
8983 case ARM_CPU_MODE_SYS
:
8984 case ARM_CPU_MODE_SVC
:
8985 case ARM_CPU_MODE_ABT
:
8986 case ARM_CPU_MODE_UND
:
8987 case ARM_CPU_MODE_IRQ
:
8988 case ARM_CPU_MODE_FIQ
:
8989 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8990 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8992 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8993 * and CPS are treated as illegal mode changes.
8995 if (write_type
== CPSRWriteByInstr
&&
8996 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8997 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9001 case ARM_CPU_MODE_HYP
:
9002 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9003 case ARM_CPU_MODE_MON
:
9004 return arm_current_el(env
) < 3;
9010 uint32_t cpsr_read(CPUARMState
*env
)
9013 ZF
= (env
->ZF
== 0);
9014 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9015 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9016 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9017 | ((env
->condexec_bits
& 0xfc) << 8)
9018 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9021 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9022 CPSRWriteType write_type
)
9024 uint32_t changed_daif
;
9025 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9026 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9028 if (mask
& CPSR_NZCV
) {
9029 env
->ZF
= (~val
) & CPSR_Z
;
9031 env
->CF
= (val
>> 29) & 1;
9032 env
->VF
= (val
<< 3) & 0x80000000;
9035 env
->QF
= ((val
& CPSR_Q
) != 0);
9037 env
->thumb
= ((val
& CPSR_T
) != 0);
9038 if (mask
& CPSR_IT_0_1
) {
9039 env
->condexec_bits
&= ~3;
9040 env
->condexec_bits
|= (val
>> 25) & 3;
9042 if (mask
& CPSR_IT_2_7
) {
9043 env
->condexec_bits
&= 3;
9044 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9046 if (mask
& CPSR_GE
) {
9047 env
->GE
= (val
>> 16) & 0xf;
9050 /* In a V7 implementation that includes the security extensions but does
9051 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9052 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9053 * bits respectively.
9055 * In a V8 implementation, it is permitted for privileged software to
9056 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9058 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9059 arm_feature(env
, ARM_FEATURE_EL3
) &&
9060 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9061 !arm_is_secure(env
)) {
9063 changed_daif
= (env
->daif
^ val
) & mask
;
9065 if (changed_daif
& CPSR_A
) {
9066 /* Check to see if we are allowed to change the masking of async
9067 * abort exceptions from a non-secure state.
9069 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9070 qemu_log_mask(LOG_GUEST_ERROR
,
9071 "Ignoring attempt to switch CPSR_A flag from "
9072 "non-secure world with SCR.AW bit clear\n");
9077 if (changed_daif
& CPSR_F
) {
9078 /* Check to see if we are allowed to change the masking of FIQ
9079 * exceptions from a non-secure state.
9081 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9082 qemu_log_mask(LOG_GUEST_ERROR
,
9083 "Ignoring attempt to switch CPSR_F flag from "
9084 "non-secure world with SCR.FW bit clear\n");
9088 /* Check whether non-maskable FIQ (NMFI) support is enabled.
9089 * If this bit is set software is not allowed to mask
9090 * FIQs, but is allowed to set CPSR_F to 0.
9092 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9094 qemu_log_mask(LOG_GUEST_ERROR
,
9095 "Ignoring attempt to enable CPSR_F flag "
9096 "(non-maskable FIQ [NMFI] support enabled)\n");
9102 env
->daif
&= ~(CPSR_AIF
& mask
);
9103 env
->daif
|= val
& CPSR_AIF
& mask
;
9105 if (write_type
!= CPSRWriteRaw
&&
9106 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9107 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9108 /* Note that we can only get here in USR mode if this is a
9109 * gdb stub write; for this case we follow the architectural
9110 * behaviour for guest writes in USR mode of ignoring an attempt
9111 * to switch mode. (Those are caught by translate.c for writes
9112 * triggered by guest instructions.)
9115 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9116 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9117 * v7, and has defined behaviour in v8:
9118 * + leave CPSR.M untouched
9119 * + allow changes to the other CPSR fields
9121 * For user changes via the GDB stub, we don't set PSTATE.IL,
9122 * as this would be unnecessarily harsh for a user error.
9125 if (write_type
!= CPSRWriteByGDBStub
&&
9126 arm_feature(env
, ARM_FEATURE_V8
)) {
9130 qemu_log_mask(LOG_GUEST_ERROR
,
9131 "Illegal AArch32 mode switch attempt from %s to %s\n",
9132 aarch32_mode_name(env
->uncached_cpsr
),
9133 aarch32_mode_name(val
));
9135 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9136 write_type
== CPSRWriteExceptionReturn
?
9137 "Exception return from AArch32" :
9138 "AArch32 mode switch from",
9139 aarch32_mode_name(env
->uncached_cpsr
),
9140 aarch32_mode_name(val
), env
->regs
[15]);
9141 switch_mode(env
, val
& CPSR_M
);
9144 mask
&= ~CACHED_CPSR_BITS
;
9145 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9146 if (rebuild_hflags
) {
9147 arm_rebuild_hflags(env
);
9151 /* Sign/zero extend */
9152 uint32_t HELPER(sxtb16
)(uint32_t x
)
9155 res
= (uint16_t)(int8_t)x
;
9156 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9160 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9163 * Take a division-by-zero exception if necessary; otherwise return
9164 * to get the usual non-trapping division behaviour (result of 0)
9166 if (arm_feature(env
, ARM_FEATURE_M
)
9167 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9168 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9172 uint32_t HELPER(uxtb16
)(uint32_t x
)
9175 res
= (uint16_t)(uint8_t)x
;
9176 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9180 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9183 handle_possible_div0_trap(env
, GETPC());
9186 if (num
== INT_MIN
&& den
== -1) {
9192 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9195 handle_possible_div0_trap(env
, GETPC());
9201 uint32_t HELPER(rbit
)(uint32_t x
)
9206 #ifdef CONFIG_USER_ONLY
9208 static void switch_mode(CPUARMState
*env
, int mode
)
9210 ARMCPU
*cpu
= env_archcpu(env
);
9212 if (mode
!= ARM_CPU_MODE_USR
) {
9213 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9217 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9218 uint32_t cur_el
, bool secure
)
9223 void aarch64_sync_64_to_32(CPUARMState
*env
)
9225 g_assert_not_reached();
9230 static void switch_mode(CPUARMState
*env
, int mode
)
9235 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9236 if (mode
== old_mode
)
9239 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9240 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9241 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9242 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9243 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9244 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9247 i
= bank_number(old_mode
);
9248 env
->banked_r13
[i
] = env
->regs
[13];
9249 env
->banked_spsr
[i
] = env
->spsr
;
9251 i
= bank_number(mode
);
9252 env
->regs
[13] = env
->banked_r13
[i
];
9253 env
->spsr
= env
->banked_spsr
[i
];
9255 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9256 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9259 /* Physical Interrupt Target EL Lookup Table
9261 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9263 * The below multi-dimensional table is used for looking up the target
9264 * exception level given numerous condition criteria. Specifically, the
9265 * target EL is based on SCR and HCR routing controls as well as the
9266 * currently executing EL and secure state.
9269 * target_el_table[2][2][2][2][2][4]
9270 * | | | | | +--- Current EL
9271 * | | | | +------ Non-secure(0)/Secure(1)
9272 * | | | +--------- HCR mask override
9273 * | | +------------ SCR exec state control
9274 * | +--------------- SCR mask override
9275 * +------------------ 32-bit(0)/64-bit(1) EL3
9277 * The table values are as such:
9281 * The ARM ARM target EL table includes entries indicating that an "exception
9282 * is not taken". The two cases where this is applicable are:
9283 * 1) An exception is taken from EL3 but the SCR does not have the exception
9285 * 2) An exception is taken from EL2 but the HCR does not have the exception
9287 * In these two cases, the below table contain a target of EL1. This value is
9288 * returned as it is expected that the consumer of the table data will check
9289 * for "target EL >= current EL" to ensure the exception is not taken.
9293 * BIT IRQ IMO Non-secure Secure
9294 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9296 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9297 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9298 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9299 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9300 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9301 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9302 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9303 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9304 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9305 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9306 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9307 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9308 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9309 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9310 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9311 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9312 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9316 * Determine the target EL for physical exceptions
9318 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9319 uint32_t cur_el
, bool secure
)
9321 CPUARMState
*env
= cs
->env_ptr
;
9326 /* Is the highest EL AArch64? */
9327 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9330 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9331 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9333 /* Either EL2 is the highest EL (and so the EL2 register width
9334 * is given by is64); or there is no EL2 or EL3, in which case
9335 * the value of 'rw' does not affect the table lookup anyway.
9340 hcr_el2
= arm_hcr_el2_eff(env
);
9343 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9344 hcr
= hcr_el2
& HCR_IMO
;
9347 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9348 hcr
= hcr_el2
& HCR_FMO
;
9351 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9352 hcr
= hcr_el2
& HCR_AMO
;
9357 * For these purposes, TGE and AMO/IMO/FMO both force the
9358 * interrupt to EL2. Fold TGE into the bit extracted above.
9360 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9362 /* Perform a table-lookup for the target EL given the current state */
9363 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9365 assert(target_el
> 0);
9370 void arm_log_exception(CPUState
*cs
)
9372 int idx
= cs
->exception_index
;
9374 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9375 const char *exc
= NULL
;
9376 static const char * const excnames
[] = {
9377 [EXCP_UDEF
] = "Undefined Instruction",
9379 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9380 [EXCP_DATA_ABORT
] = "Data Abort",
9383 [EXCP_BKPT
] = "Breakpoint",
9384 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9385 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9386 [EXCP_HVC
] = "Hypervisor Call",
9387 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9388 [EXCP_SMC
] = "Secure Monitor Call",
9389 [EXCP_VIRQ
] = "Virtual IRQ",
9390 [EXCP_VFIQ
] = "Virtual FIQ",
9391 [EXCP_SEMIHOST
] = "Semihosting call",
9392 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9393 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9394 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9395 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9396 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9397 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9398 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
9399 [EXCP_VSERR
] = "Virtual SERR",
9402 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9403 exc
= excnames
[idx
];
9408 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
9409 idx
, exc
, cs
->cpu_index
);
9414 * Function used to synchronize QEMU's AArch64 register set with AArch32
9415 * register set. This is necessary when switching between AArch32 and AArch64
9418 void aarch64_sync_32_to_64(CPUARMState
*env
)
9421 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9423 /* We can blanket copy R[0:7] to X[0:7] */
9424 for (i
= 0; i
< 8; i
++) {
9425 env
->xregs
[i
] = env
->regs
[i
];
9429 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9430 * Otherwise, they come from the banked user regs.
9432 if (mode
== ARM_CPU_MODE_FIQ
) {
9433 for (i
= 8; i
< 13; i
++) {
9434 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9437 for (i
= 8; i
< 13; i
++) {
9438 env
->xregs
[i
] = env
->regs
[i
];
9443 * Registers x13-x23 are the various mode SP and FP registers. Registers
9444 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9445 * from the mode banked register.
9447 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9448 env
->xregs
[13] = env
->regs
[13];
9449 env
->xregs
[14] = env
->regs
[14];
9451 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9452 /* HYP is an exception in that it is copied from r14 */
9453 if (mode
== ARM_CPU_MODE_HYP
) {
9454 env
->xregs
[14] = env
->regs
[14];
9456 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9460 if (mode
== ARM_CPU_MODE_HYP
) {
9461 env
->xregs
[15] = env
->regs
[13];
9463 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9466 if (mode
== ARM_CPU_MODE_IRQ
) {
9467 env
->xregs
[16] = env
->regs
[14];
9468 env
->xregs
[17] = env
->regs
[13];
9470 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9471 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9474 if (mode
== ARM_CPU_MODE_SVC
) {
9475 env
->xregs
[18] = env
->regs
[14];
9476 env
->xregs
[19] = env
->regs
[13];
9478 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9479 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9482 if (mode
== ARM_CPU_MODE_ABT
) {
9483 env
->xregs
[20] = env
->regs
[14];
9484 env
->xregs
[21] = env
->regs
[13];
9486 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9487 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9490 if (mode
== ARM_CPU_MODE_UND
) {
9491 env
->xregs
[22] = env
->regs
[14];
9492 env
->xregs
[23] = env
->regs
[13];
9494 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9495 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9499 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9500 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9501 * FIQ bank for r8-r14.
9503 if (mode
== ARM_CPU_MODE_FIQ
) {
9504 for (i
= 24; i
< 31; i
++) {
9505 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9508 for (i
= 24; i
< 29; i
++) {
9509 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9511 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9512 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9515 env
->pc
= env
->regs
[15];
9519 * Function used to synchronize QEMU's AArch32 register set with AArch64
9520 * register set. This is necessary when switching between AArch32 and AArch64
9523 void aarch64_sync_64_to_32(CPUARMState
*env
)
9526 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9528 /* We can blanket copy X[0:7] to R[0:7] */
9529 for (i
= 0; i
< 8; i
++) {
9530 env
->regs
[i
] = env
->xregs
[i
];
9534 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9535 * Otherwise, we copy x8-x12 into the banked user regs.
9537 if (mode
== ARM_CPU_MODE_FIQ
) {
9538 for (i
= 8; i
< 13; i
++) {
9539 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9542 for (i
= 8; i
< 13; i
++) {
9543 env
->regs
[i
] = env
->xregs
[i
];
9548 * Registers r13 & r14 depend on the current mode.
9549 * If we are in a given mode, we copy the corresponding x registers to r13
9550 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9553 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9554 env
->regs
[13] = env
->xregs
[13];
9555 env
->regs
[14] = env
->xregs
[14];
9557 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9560 * HYP is an exception in that it does not have its own banked r14 but
9561 * shares the USR r14
9563 if (mode
== ARM_CPU_MODE_HYP
) {
9564 env
->regs
[14] = env
->xregs
[14];
9566 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9570 if (mode
== ARM_CPU_MODE_HYP
) {
9571 env
->regs
[13] = env
->xregs
[15];
9573 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9576 if (mode
== ARM_CPU_MODE_IRQ
) {
9577 env
->regs
[14] = env
->xregs
[16];
9578 env
->regs
[13] = env
->xregs
[17];
9580 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9581 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9584 if (mode
== ARM_CPU_MODE_SVC
) {
9585 env
->regs
[14] = env
->xregs
[18];
9586 env
->regs
[13] = env
->xregs
[19];
9588 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9589 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9592 if (mode
== ARM_CPU_MODE_ABT
) {
9593 env
->regs
[14] = env
->xregs
[20];
9594 env
->regs
[13] = env
->xregs
[21];
9596 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9597 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9600 if (mode
== ARM_CPU_MODE_UND
) {
9601 env
->regs
[14] = env
->xregs
[22];
9602 env
->regs
[13] = env
->xregs
[23];
9604 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9605 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9608 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9609 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9610 * FIQ bank for r8-r14.
9612 if (mode
== ARM_CPU_MODE_FIQ
) {
9613 for (i
= 24; i
< 31; i
++) {
9614 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9617 for (i
= 24; i
< 29; i
++) {
9618 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9620 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9621 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9624 env
->regs
[15] = env
->pc
;
9627 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9628 uint32_t mask
, uint32_t offset
,
9633 /* Change the CPU state so as to actually take the exception. */
9634 switch_mode(env
, new_mode
);
9637 * For exceptions taken to AArch32 we must clear the SS bit in both
9638 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9640 env
->pstate
&= ~PSTATE_SS
;
9641 env
->spsr
= cpsr_read(env
);
9642 /* Clear IT bits. */
9643 env
->condexec_bits
= 0;
9644 /* Switch to the new mode, and to the correct instruction set. */
9645 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9647 /* This must be after mode switching. */
9648 new_el
= arm_current_el(env
);
9650 /* Set new mode endianness */
9651 env
->uncached_cpsr
&= ~CPSR_E
;
9652 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9653 env
->uncached_cpsr
|= CPSR_E
;
9655 /* J and IL must always be cleared for exception entry */
9656 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9659 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
9660 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
9661 env
->uncached_cpsr
|= CPSR_SSBS
;
9663 env
->uncached_cpsr
&= ~CPSR_SSBS
;
9667 if (new_mode
== ARM_CPU_MODE_HYP
) {
9668 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9669 env
->elr_el
[2] = env
->regs
[15];
9671 /* CPSR.PAN is normally preserved preserved unless... */
9672 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9675 if (!arm_is_secure_below_el3(env
)) {
9676 /* ... the target is EL3, from non-secure state. */
9677 env
->uncached_cpsr
&= ~CPSR_PAN
;
9680 /* ... the target is EL3, from secure state ... */
9683 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9684 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9685 env
->uncached_cpsr
|= CPSR_PAN
;
9691 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9692 * and we should just guard the thumb mode on V4
9694 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9696 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9698 env
->regs
[14] = env
->regs
[15] + offset
;
9700 env
->regs
[15] = newpc
;
9701 arm_rebuild_hflags(env
);
9704 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9707 * Handle exception entry to Hyp mode; this is sufficiently
9708 * different to entry to other AArch32 modes that we handle it
9711 * The vector table entry used is always the 0x14 Hyp mode entry point,
9712 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
9713 * The offset applied to the preferred return address is always zero
9714 * (see DDI0487C.a section G1.12.3).
9715 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9717 uint32_t addr
, mask
;
9718 ARMCPU
*cpu
= ARM_CPU(cs
);
9719 CPUARMState
*env
= &cpu
->env
;
9721 switch (cs
->exception_index
) {
9729 /* Fall through to prefetch abort. */
9730 case EXCP_PREFETCH_ABORT
:
9731 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9732 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9733 (uint32_t)env
->exception
.vaddress
);
9736 case EXCP_DATA_ABORT
:
9737 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9738 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9739 (uint32_t)env
->exception
.vaddress
);
9755 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9758 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9759 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9761 * QEMU syndrome values are v8-style. v7 has the IL bit
9762 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9763 * If this is a v7 CPU, squash the IL bit in those cases.
9765 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9766 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9767 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9768 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9769 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9772 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9775 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9780 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9783 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9786 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9790 addr
+= env
->cp15
.hvbar
;
9792 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9795 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9797 ARMCPU
*cpu
= ARM_CPU(cs
);
9798 CPUARMState
*env
= &cpu
->env
;
9805 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9806 switch (syn_get_ec(env
->exception
.syndrome
)) {
9808 case EC_BREAKPOINT_SAME_EL
:
9812 case EC_WATCHPOINT_SAME_EL
:
9818 case EC_VECTORCATCH
:
9827 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9830 if (env
->exception
.target_el
== 2) {
9831 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9835 switch (cs
->exception_index
) {
9837 new_mode
= ARM_CPU_MODE_UND
;
9846 new_mode
= ARM_CPU_MODE_SVC
;
9849 /* The PC already points to the next instruction. */
9853 /* Fall through to prefetch abort. */
9854 case EXCP_PREFETCH_ABORT
:
9855 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9856 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9857 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9858 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9859 new_mode
= ARM_CPU_MODE_ABT
;
9861 mask
= CPSR_A
| CPSR_I
;
9864 case EXCP_DATA_ABORT
:
9865 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9866 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9867 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9869 (uint32_t)env
->exception
.vaddress
);
9870 new_mode
= ARM_CPU_MODE_ABT
;
9872 mask
= CPSR_A
| CPSR_I
;
9876 new_mode
= ARM_CPU_MODE_IRQ
;
9878 /* Disable IRQ and imprecise data aborts. */
9879 mask
= CPSR_A
| CPSR_I
;
9881 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9882 /* IRQ routed to monitor mode */
9883 new_mode
= ARM_CPU_MODE_MON
;
9888 new_mode
= ARM_CPU_MODE_FIQ
;
9890 /* Disable FIQ, IRQ and imprecise data aborts. */
9891 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9892 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9893 /* FIQ routed to monitor mode */
9894 new_mode
= ARM_CPU_MODE_MON
;
9899 new_mode
= ARM_CPU_MODE_IRQ
;
9901 /* Disable IRQ and imprecise data aborts. */
9902 mask
= CPSR_A
| CPSR_I
;
9906 new_mode
= ARM_CPU_MODE_FIQ
;
9908 /* Disable FIQ, IRQ and imprecise data aborts. */
9909 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9915 * Note that this is reported as a data abort, but the DFAR
9916 * has an UNKNOWN value. Construct the SError syndrome from
9917 * AET and ExT fields.
9919 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
9921 if (extended_addresses_enabled(env
)) {
9922 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
9924 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
9926 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
9927 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9928 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
9929 env
->exception
.fsr
);
9931 new_mode
= ARM_CPU_MODE_ABT
;
9933 mask
= CPSR_A
| CPSR_I
;
9938 new_mode
= ARM_CPU_MODE_MON
;
9940 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9944 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9945 return; /* Never happens. Keep compiler happy. */
9948 if (new_mode
== ARM_CPU_MODE_MON
) {
9949 addr
+= env
->cp15
.mvbar
;
9950 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9951 /* High vectors. When enabled, base address cannot be remapped. */
9954 /* ARM v7 architectures provide a vector base address register to remap
9955 * the interrupt vector table.
9956 * This register is only followed in non-monitor mode, and is banked.
9957 * Note: only bits 31:5 are valid.
9959 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9962 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9963 env
->cp15
.scr_el3
&= ~SCR_NS
;
9966 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9969 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
9972 * Return the register number of the AArch64 view of the AArch32
9973 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9974 * be that of the AArch32 mode the exception came from.
9976 int mode
= env
->uncached_cpsr
& CPSR_M
;
9978 switch (aarch32_reg
) {
9982 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
9985 case ARM_CPU_MODE_USR
:
9986 case ARM_CPU_MODE_SYS
:
9988 case ARM_CPU_MODE_HYP
:
9990 case ARM_CPU_MODE_IRQ
:
9992 case ARM_CPU_MODE_SVC
:
9994 case ARM_CPU_MODE_ABT
:
9996 case ARM_CPU_MODE_UND
:
9998 case ARM_CPU_MODE_FIQ
:
10001 g_assert_not_reached();
10005 case ARM_CPU_MODE_USR
:
10006 case ARM_CPU_MODE_SYS
:
10007 case ARM_CPU_MODE_HYP
:
10009 case ARM_CPU_MODE_IRQ
:
10011 case ARM_CPU_MODE_SVC
:
10013 case ARM_CPU_MODE_ABT
:
10015 case ARM_CPU_MODE_UND
:
10017 case ARM_CPU_MODE_FIQ
:
10020 g_assert_not_reached();
10025 g_assert_not_reached();
10029 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10031 uint32_t ret
= cpsr_read(env
);
10033 /* Move DIT to the correct location for SPSR_ELx */
10034 if (ret
& CPSR_DIT
) {
10038 /* Merge PSTATE.SS into SPSR_ELx */
10039 ret
|= env
->pstate
& PSTATE_SS
;
10044 /* Handle exception entry to a target EL which is using AArch64 */
10045 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10047 ARMCPU
*cpu
= ARM_CPU(cs
);
10048 CPUARMState
*env
= &cpu
->env
;
10049 unsigned int new_el
= env
->exception
.target_el
;
10050 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10051 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10052 unsigned int old_mode
;
10053 unsigned int cur_el
= arm_current_el(env
);
10057 * Note that new_el can never be 0. If cur_el is 0, then
10058 * el0_a64 is is_a64(), else el0_a64 is ignored.
10060 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10062 if (cur_el
< new_el
) {
10063 /* Entry vector offset depends on whether the implemented EL
10064 * immediately lower than the target level is using AArch32 or AArch64
10071 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10074 hcr
= arm_hcr_el2_eff(env
);
10075 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10076 is_aa64
= (hcr
& HCR_RW
) != 0;
10081 is_aa64
= is_a64(env
);
10084 g_assert_not_reached();
10092 } else if (pstate_read(env
) & PSTATE_SP
) {
10096 switch (cs
->exception_index
) {
10097 case EXCP_PREFETCH_ABORT
:
10098 case EXCP_DATA_ABORT
:
10099 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10100 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10101 env
->cp15
.far_el
[new_el
]);
10107 case EXCP_HYP_TRAP
:
10109 switch (syn_get_ec(env
->exception
.syndrome
)) {
10110 case EC_ADVSIMDFPACCESSTRAP
:
10112 * QEMU internal FP/SIMD syndromes from AArch32 include the
10113 * TA and coproc fields which are only exposed if the exception
10114 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10115 * AArch64 format syndrome.
10117 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10119 case EC_CP14RTTRAP
:
10120 case EC_CP15RTTRAP
:
10121 case EC_CP14DTTRAP
:
10123 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10124 * the raw register field from the insn; when taking this to
10125 * AArch64 we must convert it to the AArch64 view of the register
10126 * number. Notice that we read a 4-bit AArch32 register number and
10127 * write back a 5-bit AArch64 one.
10129 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10130 rt
= aarch64_regnum(env
, rt
);
10131 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10134 case EC_CP15RRTTRAP
:
10135 case EC_CP14RRTTRAP
:
10136 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10137 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10138 rt
= aarch64_regnum(env
, rt
);
10139 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10141 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10142 rt
= aarch64_regnum(env
, rt
);
10143 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10147 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10159 /* Construct the SError syndrome from IDS and ISS fields. */
10160 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10161 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10164 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10168 old_mode
= pstate_read(env
);
10169 aarch64_save_sp(env
, arm_current_el(env
));
10170 env
->elr_el
[new_el
] = env
->pc
;
10172 old_mode
= cpsr_read_for_spsr_elx(env
);
10173 env
->elr_el
[new_el
] = env
->regs
[15];
10175 aarch64_sync_32_to_64(env
);
10177 env
->condexec_bits
= 0;
10179 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10181 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10182 env
->elr_el
[new_el
]);
10184 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10185 /* The value of PSTATE.PAN is normally preserved, except when ... */
10186 new_mode
|= old_mode
& PSTATE_PAN
;
10189 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10190 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10191 != (HCR_E2H
| HCR_TGE
)) {
10196 /* ... the target is EL1 ... */
10197 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10198 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10199 new_mode
|= PSTATE_PAN
;
10204 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10205 new_mode
|= PSTATE_TCO
;
10208 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10209 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10210 new_mode
|= PSTATE_SSBS
;
10212 new_mode
&= ~PSTATE_SSBS
;
10216 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10217 env
->aarch64
= true;
10218 aarch64_restore_sp(env
, new_el
);
10219 helper_rebuild_hflags_a64(env
, new_el
);
10223 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10224 new_el
, env
->pc
, pstate_read(env
));
10228 * Do semihosting call and set the appropriate return value. All the
10229 * permission and validity checks have been done at translate time.
10231 * We only see semihosting exceptions in TCG only as they are not
10232 * trapped to the hypervisor in KVM.
10235 static void handle_semihosting(CPUState
*cs
)
10237 ARMCPU
*cpu
= ARM_CPU(cs
);
10238 CPUARMState
*env
= &cpu
->env
;
10241 qemu_log_mask(CPU_LOG_INT
,
10242 "...handling as semihosting call 0x%" PRIx64
"\n",
10244 env
->xregs
[0] = do_common_semihosting(cs
);
10247 qemu_log_mask(CPU_LOG_INT
,
10248 "...handling as semihosting call 0x%x\n",
10250 env
->regs
[0] = do_common_semihosting(cs
);
10251 env
->regs
[15] += env
->thumb
? 2 : 4;
10256 /* Handle a CPU exception for A and R profile CPUs.
10257 * Do any appropriate logging, handle PSCI calls, and then hand off
10258 * to the AArch64-entry or AArch32-entry function depending on the
10259 * target exception level's register width.
10261 * Note: this is used for both TCG (as the do_interrupt tcg op),
10262 * and KVM to re-inject guest debug exceptions, and to
10263 * inject a Synchronous-External-Abort.
10265 void arm_cpu_do_interrupt(CPUState
*cs
)
10267 ARMCPU
*cpu
= ARM_CPU(cs
);
10268 CPUARMState
*env
= &cpu
->env
;
10269 unsigned int new_el
= env
->exception
.target_el
;
10271 assert(!arm_feature(env
, ARM_FEATURE_M
));
10273 arm_log_exception(cs
);
10274 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10276 if (qemu_loglevel_mask(CPU_LOG_INT
)
10277 && !excp_is_internal(cs
->exception_index
)) {
10278 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10279 syn_get_ec(env
->exception
.syndrome
),
10280 env
->exception
.syndrome
);
10283 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10284 arm_handle_psci_call(cpu
);
10285 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10290 * Semihosting semantics depend on the register width of the code
10291 * that caused the exception, not the target exception level, so
10292 * must be handled here.
10295 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10296 handle_semihosting(cs
);
10301 /* Hooks may change global state so BQL should be held, also the
10302 * BQL needs to be held for any modification of
10303 * cs->interrupt_request.
10305 g_assert(qemu_mutex_iothread_locked());
10307 arm_call_pre_el_change_hook(cpu
);
10309 assert(!excp_is_internal(cs
->exception_index
));
10310 if (arm_el_is_aa64(env
, new_el
)) {
10311 arm_cpu_do_interrupt_aarch64(cs
);
10313 arm_cpu_do_interrupt_aarch32(cs
);
10316 arm_call_el_change_hook(cpu
);
10318 if (!kvm_enabled()) {
10319 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10322 #endif /* !CONFIG_USER_ONLY */
10324 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10326 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10328 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10329 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10332 return env
->cp15
.sctlr_el
[el
];
10335 /* Return the SCTLR value which controls this address translation regime */
10336 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10338 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
10341 #ifndef CONFIG_USER_ONLY
10343 /* Return true if the specified stage of address translation is disabled */
10344 static inline bool regime_translation_disabled(CPUARMState
*env
,
10349 if (arm_feature(env
, ARM_FEATURE_M
)) {
10350 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
10351 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
10352 case R_V7M_MPU_CTRL_ENABLE_MASK
:
10353 /* Enabled, but not for HardFault and NMI */
10354 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
10355 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
10356 /* Enabled for all cases */
10360 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
10361 * we warned about that in armv7m_nvic.c when the guest set it.
10367 hcr_el2
= arm_hcr_el2_eff(env
);
10369 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10370 /* HCR.DC means HCR.VM behaves as 1 */
10371 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
10374 if (hcr_el2
& HCR_TGE
) {
10375 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10376 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
10381 if ((hcr_el2
& HCR_DC
) && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
10382 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10386 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
10389 static inline bool regime_translation_big_endian(CPUARMState
*env
,
10392 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
10395 /* Return the TTBR associated with this translation regime */
10396 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10399 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10400 return env
->cp15
.vttbr_el2
;
10402 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
10403 return env
->cp15
.vsttbr_el2
;
10406 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
10408 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
10412 #endif /* !CONFIG_USER_ONLY */
10414 /* Convert a possible stage1+2 MMU index into the appropriate
10415 * stage 1 MMU index
10417 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
10420 case ARMMMUIdx_SE10_0
:
10421 return ARMMMUIdx_Stage1_SE0
;
10422 case ARMMMUIdx_SE10_1
:
10423 return ARMMMUIdx_Stage1_SE1
;
10424 case ARMMMUIdx_SE10_1_PAN
:
10425 return ARMMMUIdx_Stage1_SE1_PAN
;
10426 case ARMMMUIdx_E10_0
:
10427 return ARMMMUIdx_Stage1_E0
;
10428 case ARMMMUIdx_E10_1
:
10429 return ARMMMUIdx_Stage1_E1
;
10430 case ARMMMUIdx_E10_1_PAN
:
10431 return ARMMMUIdx_Stage1_E1_PAN
;
10437 /* Return true if the translation regime is using LPAE format page tables */
10438 static inline bool regime_using_lpae_format(CPUARMState
*env
,
10441 int el
= regime_el(env
, mmu_idx
);
10442 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
10445 if (arm_feature(env
, ARM_FEATURE_LPAE
)
10446 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
10452 /* Returns true if the stage 1 translation regime is using LPAE format page
10453 * tables. Used when raising alignment exceptions, whose FSR changes depending
10454 * on whether the long or short descriptor format is in use. */
10455 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10457 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10459 return regime_using_lpae_format(env
, mmu_idx
);
10462 #ifndef CONFIG_USER_ONLY
10463 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10466 case ARMMMUIdx_SE10_0
:
10467 case ARMMMUIdx_E20_0
:
10468 case ARMMMUIdx_SE20_0
:
10469 case ARMMMUIdx_Stage1_E0
:
10470 case ARMMMUIdx_Stage1_SE0
:
10471 case ARMMMUIdx_MUser
:
10472 case ARMMMUIdx_MSUser
:
10473 case ARMMMUIdx_MUserNegPri
:
10474 case ARMMMUIdx_MSUserNegPri
:
10478 case ARMMMUIdx_E10_0
:
10479 case ARMMMUIdx_E10_1
:
10480 case ARMMMUIdx_E10_1_PAN
:
10481 g_assert_not_reached();
10485 /* Translate section/page access permissions to page
10486 * R/W protection flags
10488 * @env: CPUARMState
10489 * @mmu_idx: MMU index indicating required translation regime
10490 * @ap: The 3-bit access permissions (AP[2:0])
10491 * @domain_prot: The 2-bit domain access permissions
10493 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10494 int ap
, int domain_prot
)
10496 bool is_user
= regime_is_user(env
, mmu_idx
);
10498 if (domain_prot
== 3) {
10499 return PAGE_READ
| PAGE_WRITE
;
10504 if (arm_feature(env
, ARM_FEATURE_V7
)) {
10507 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
10509 return is_user
? 0 : PAGE_READ
;
10516 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10521 return PAGE_READ
| PAGE_WRITE
;
10524 return PAGE_READ
| PAGE_WRITE
;
10525 case 4: /* Reserved. */
10528 return is_user
? 0 : PAGE_READ
;
10532 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
10537 g_assert_not_reached();
10541 /* Translate section/page access permissions to page
10542 * R/W protection flags.
10544 * @ap: The 2-bit simple AP (AP[2:1])
10545 * @is_user: TRUE if accessing from PL0
10547 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
10551 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10553 return PAGE_READ
| PAGE_WRITE
;
10555 return is_user
? 0 : PAGE_READ
;
10559 g_assert_not_reached();
10564 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
10566 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
10569 /* Translate S2 section/page access permissions to protection flags
10571 * @env: CPUARMState
10572 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10573 * @xn: XN (execute-never) bits
10574 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
10576 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
10584 prot
|= PAGE_WRITE
;
10587 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
10605 g_assert_not_reached();
10608 if (!extract32(xn
, 1, 1)) {
10609 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
10617 /* Translate section/page access permissions to protection flags
10619 * @env: CPUARMState
10620 * @mmu_idx: MMU index indicating required translation regime
10621 * @is_aa64: TRUE if AArch64
10622 * @ap: The 2-bit simple AP (AP[2:1])
10623 * @ns: NS (non-secure) bit
10624 * @xn: XN (execute-never) bit
10625 * @pxn: PXN (privileged execute-never) bit
10627 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
10628 int ap
, int ns
, int xn
, int pxn
)
10630 bool is_user
= regime_is_user(env
, mmu_idx
);
10631 int prot_rw
, user_rw
;
10635 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
10636 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
10638 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
10642 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
10643 /* PAN forbids data accesses but doesn't affect insn fetch */
10646 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
10650 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
10654 /* TODO have_wxn should be replaced with
10655 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10656 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10657 * compatible processors have EL2, which is required for [U]WXN.
10659 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
10662 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
10666 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
10667 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
10669 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10670 switch (regime_el(env
, mmu_idx
)) {
10674 xn
= xn
|| !(user_rw
& PAGE_READ
);
10678 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
10680 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
10681 (uwxn
&& (user_rw
& PAGE_WRITE
));
10691 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
10694 return prot_rw
| PAGE_EXEC
;
10697 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10698 uint32_t *table
, uint32_t address
)
10700 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10701 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10703 if (address
& tcr
->mask
) {
10704 if (tcr
->raw_tcr
& TTBCR_PD1
) {
10705 /* Translation table walk disabled for TTBR1 */
10708 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
10710 if (tcr
->raw_tcr
& TTBCR_PD0
) {
10711 /* Translation table walk disabled for TTBR0 */
10714 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
10716 *table
|= (address
>> 18) & 0x3ffc;
10720 /* Translate a S1 pagetable walk through S2 if needed. */
10721 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10722 hwaddr addr
, bool *is_secure
,
10723 ARMMMUFaultInfo
*fi
)
10725 if (arm_mmu_idx_is_stage1_of_2(mmu_idx
) &&
10726 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
10727 target_ulong s2size
;
10731 ARMMMUIdx s2_mmu_idx
= *is_secure
? ARMMMUIdx_Stage2_S
10732 : ARMMMUIdx_Stage2
;
10733 ARMCacheAttrs cacheattrs
= {};
10734 MemTxAttrs txattrs
= {};
10736 ret
= get_phys_addr_lpae(env
, addr
, MMU_DATA_LOAD
, s2_mmu_idx
, false,
10737 &s2pa
, &txattrs
, &s2prot
, &s2size
, fi
,
10740 assert(fi
->type
!= ARMFault_None
);
10744 fi
->s1ns
= !*is_secure
;
10747 if ((arm_hcr_el2_eff(env
) & HCR_PTW
) &&
10748 (cacheattrs
.attrs
& 0xf0) == 0) {
10750 * PTW set and S1 walk touched S2 Device memory:
10751 * generate Permission fault.
10753 fi
->type
= ARMFault_Permission
;
10757 fi
->s1ns
= !*is_secure
;
10761 if (arm_is_secure_below_el3(env
)) {
10762 /* Check if page table walk is to secure or non-secure PA space. */
10764 *is_secure
= !(env
->cp15
.vstcr_el2
.raw_tcr
& VSTCR_SW
);
10766 *is_secure
= !(env
->cp15
.vtcr_el2
.raw_tcr
& VTCR_NSW
);
10769 assert(!*is_secure
);
10777 /* All loads done in the course of a page table walk go through here. */
10778 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10779 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10781 ARMCPU
*cpu
= ARM_CPU(cs
);
10782 CPUARMState
*env
= &cpu
->env
;
10783 MemTxAttrs attrs
= {};
10784 MemTxResult result
= MEMTX_OK
;
10788 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, &is_secure
, fi
);
10789 attrs
.secure
= is_secure
;
10790 as
= arm_addressspace(cs
, attrs
);
10794 if (regime_translation_big_endian(env
, mmu_idx
)) {
10795 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
10797 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
10799 if (result
== MEMTX_OK
) {
10802 fi
->type
= ARMFault_SyncExternalOnWalk
;
10803 fi
->ea
= arm_extabort_type(result
);
10807 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10808 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10810 ARMCPU
*cpu
= ARM_CPU(cs
);
10811 CPUARMState
*env
= &cpu
->env
;
10812 MemTxAttrs attrs
= {};
10813 MemTxResult result
= MEMTX_OK
;
10817 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, &is_secure
, fi
);
10818 attrs
.secure
= is_secure
;
10819 as
= arm_addressspace(cs
, attrs
);
10823 if (regime_translation_big_endian(env
, mmu_idx
)) {
10824 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
10826 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
10828 if (result
== MEMTX_OK
) {
10831 fi
->type
= ARMFault_SyncExternalOnWalk
;
10832 fi
->ea
= arm_extabort_type(result
);
10836 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
10837 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10838 hwaddr
*phys_ptr
, int *prot
,
10839 target_ulong
*page_size
,
10840 ARMMMUFaultInfo
*fi
)
10842 CPUState
*cs
= env_cpu(env
);
10853 /* Pagetable walk. */
10854 /* Lookup l1 descriptor. */
10855 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10856 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10857 fi
->type
= ARMFault_Translation
;
10860 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10862 if (fi
->type
!= ARMFault_None
) {
10866 domain
= (desc
>> 5) & 0x0f;
10867 if (regime_el(env
, mmu_idx
) == 1) {
10868 dacr
= env
->cp15
.dacr_ns
;
10870 dacr
= env
->cp15
.dacr_s
;
10872 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10874 /* Section translation fault. */
10875 fi
->type
= ARMFault_Translation
;
10881 if (domain_prot
== 0 || domain_prot
== 2) {
10882 fi
->type
= ARMFault_Domain
;
10887 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10888 ap
= (desc
>> 10) & 3;
10889 *page_size
= 1024 * 1024;
10891 /* Lookup l2 entry. */
10893 /* Coarse pagetable. */
10894 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10896 /* Fine pagetable. */
10897 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
10899 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10901 if (fi
->type
!= ARMFault_None
) {
10904 switch (desc
& 3) {
10905 case 0: /* Page translation fault. */
10906 fi
->type
= ARMFault_Translation
;
10908 case 1: /* 64k page. */
10909 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10910 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
10911 *page_size
= 0x10000;
10913 case 2: /* 4k page. */
10914 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10915 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
10916 *page_size
= 0x1000;
10918 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10920 /* ARMv6/XScale extended small page format */
10921 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
10922 || arm_feature(env
, ARM_FEATURE_V6
)) {
10923 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10924 *page_size
= 0x1000;
10926 /* UNPREDICTABLE in ARMv5; we choose to take a
10927 * page translation fault.
10929 fi
->type
= ARMFault_Translation
;
10933 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
10934 *page_size
= 0x400;
10936 ap
= (desc
>> 4) & 3;
10939 /* Never happens, but compiler isn't smart enough to tell. */
10940 g_assert_not_reached();
10943 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10944 *prot
|= *prot
? PAGE_EXEC
: 0;
10945 if (!(*prot
& (1 << access_type
))) {
10946 /* Access permission fault. */
10947 fi
->type
= ARMFault_Permission
;
10950 *phys_ptr
= phys_addr
;
10953 fi
->domain
= domain
;
10958 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
10959 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10960 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10961 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
10963 CPUState
*cs
= env_cpu(env
);
10964 ARMCPU
*cpu
= env_archcpu(env
);
10978 /* Pagetable walk. */
10979 /* Lookup l1 descriptor. */
10980 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10981 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10982 fi
->type
= ARMFault_Translation
;
10985 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10987 if (fi
->type
!= ARMFault_None
) {
10991 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
10992 /* Section translation fault, or attempt to use the encoding
10993 * which is Reserved on implementations without PXN.
10995 fi
->type
= ARMFault_Translation
;
10998 if ((type
== 1) || !(desc
& (1 << 18))) {
10999 /* Page or Section. */
11000 domain
= (desc
>> 5) & 0x0f;
11002 if (regime_el(env
, mmu_idx
) == 1) {
11003 dacr
= env
->cp15
.dacr_ns
;
11005 dacr
= env
->cp15
.dacr_s
;
11010 domain_prot
= (dacr
>> (domain
* 2)) & 3;
11011 if (domain_prot
== 0 || domain_prot
== 2) {
11012 /* Section or Page domain fault */
11013 fi
->type
= ARMFault_Domain
;
11017 if (desc
& (1 << 18)) {
11018 /* Supersection. */
11019 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
11020 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
11021 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
11022 *page_size
= 0x1000000;
11025 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
11026 *page_size
= 0x100000;
11028 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
11029 xn
= desc
& (1 << 4);
11031 ns
= extract32(desc
, 19, 1);
11033 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
11034 pxn
= (desc
>> 2) & 1;
11036 ns
= extract32(desc
, 3, 1);
11037 /* Lookup l2 entry. */
11038 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
11039 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
11041 if (fi
->type
!= ARMFault_None
) {
11044 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
11045 switch (desc
& 3) {
11046 case 0: /* Page translation fault. */
11047 fi
->type
= ARMFault_Translation
;
11049 case 1: /* 64k page. */
11050 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
11051 xn
= desc
& (1 << 15);
11052 *page_size
= 0x10000;
11054 case 2: case 3: /* 4k page. */
11055 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
11057 *page_size
= 0x1000;
11060 /* Never happens, but compiler isn't smart enough to tell. */
11061 g_assert_not_reached();
11064 if (domain_prot
== 3) {
11065 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11067 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
11070 if (xn
&& access_type
== MMU_INST_FETCH
) {
11071 fi
->type
= ARMFault_Permission
;
11075 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
11076 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
11077 /* The simplified model uses AP[0] as an access control bit. */
11078 if ((ap
& 1) == 0) {
11079 /* Access flag fault. */
11080 fi
->type
= ARMFault_AccessFlag
;
11083 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
11085 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
11087 if (*prot
&& !xn
) {
11088 *prot
|= PAGE_EXEC
;
11090 if (!(*prot
& (1 << access_type
))) {
11091 /* Access permission fault. */
11092 fi
->type
= ARMFault_Permission
;
11097 /* The NS bit will (as required by the architecture) have no effect if
11098 * the CPU doesn't support TZ or this is a non-secure translation
11099 * regime, because the attribute will already be non-secure.
11101 attrs
->secure
= false;
11103 *phys_ptr
= phys_addr
;
11106 fi
->domain
= domain
;
11112 * check_s2_mmu_setup
11114 * @is_aa64: True if the translation regime is in AArch64 state
11115 * @startlevel: Suggested starting level
11116 * @inputsize: Bitsize of IPAs
11117 * @stride: Page-table stride (See the ARM ARM)
11119 * Returns true if the suggested S2 translation parameters are OK and
11122 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
11123 int inputsize
, int stride
, int outputsize
)
11125 const int grainsize
= stride
+ 3;
11126 int startsizecheck
;
11129 * Negative levels are usually not allowed...
11130 * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
11131 * begins with level -1. Note that previous feature tests will have
11132 * eliminated this combination if it is not enabled.
11134 if (level
< (inputsize
== 52 && stride
== 9 ? -1 : 0)) {
11138 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
11139 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
11145 case 13: /* 64KB Pages. */
11146 if (level
== 0 || (level
== 1 && outputsize
<= 42)) {
11150 case 11: /* 16KB Pages. */
11151 if (level
== 0 || (level
== 1 && outputsize
<= 40)) {
11155 case 9: /* 4KB Pages. */
11156 if (level
== 0 && outputsize
<= 42) {
11161 g_assert_not_reached();
11164 /* Inputsize checks. */
11165 if (inputsize
> outputsize
&&
11166 (arm_el_is_aa64(&cpu
->env
, 1) || inputsize
> 40)) {
11167 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
11171 /* AArch32 only supports 4KB pages. Assert on that. */
11172 assert(stride
== 9);
11181 /* Translate from the 4-bit stage 2 representation of
11182 * memory attributes (without cache-allocation hints) to
11183 * the 8-bit representation of the stage 1 MAIR registers
11184 * (which includes allocation hints).
11186 * ref: shared/translation/attrs/S2AttrDecode()
11187 * .../S2ConvertAttrsHints()
11189 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
11191 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
11192 uint8_t loattr
= extract32(s2attrs
, 0, 2);
11193 uint8_t hihint
= 0, lohint
= 0;
11195 if (hiattr
!= 0) { /* normal memory */
11196 if (arm_hcr_el2_eff(env
) & HCR_CD
) { /* cache disabled */
11197 hiattr
= loattr
= 1; /* non-cacheable */
11199 if (hiattr
!= 1) { /* Write-through or write-back */
11200 hihint
= 3; /* RW allocate */
11202 if (loattr
!= 1) { /* Write-through or write-back */
11203 lohint
= 3; /* RW allocate */
11208 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
11210 #endif /* !CONFIG_USER_ONLY */
11212 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
11213 static const uint8_t pamax_map
[] = {
11223 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
11224 unsigned int arm_pamax(ARMCPU
*cpu
)
11226 unsigned int parange
=
11227 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
11230 * id_aa64mmfr0 is a read-only register so values outside of the
11231 * supported mappings can be considered an implementation error.
11233 assert(parange
< ARRAY_SIZE(pamax_map
));
11234 return pamax_map
[parange
];
11237 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11239 if (regime_has_2_ranges(mmu_idx
)) {
11240 return extract64(tcr
, 37, 2);
11241 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11242 return 0; /* VTCR_EL2 */
11244 /* Replicate the single TBI bit so we always have 2 bits. */
11245 return extract32(tcr
, 20, 1) * 3;
11249 static int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11251 if (regime_has_2_ranges(mmu_idx
)) {
11252 return extract64(tcr
, 51, 2);
11253 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11254 return 0; /* VTCR_EL2 */
11256 /* Replicate the single TBID bit so we always have 2 bits. */
11257 return extract32(tcr
, 29, 1) * 3;
11261 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11263 if (regime_has_2_ranges(mmu_idx
)) {
11264 return extract64(tcr
, 57, 2);
11266 /* Replicate the single TCMA bit so we always have 2 bits. */
11267 return extract32(tcr
, 30, 1) * 3;
11271 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11272 ARMMMUIdx mmu_idx
, bool data
)
11274 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11275 bool epd
, hpd
, using16k
, using64k
, tsz_oob
, ds
;
11276 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11277 ARMCPU
*cpu
= env_archcpu(env
);
11279 if (!regime_has_2_ranges(mmu_idx
)) {
11281 tsz
= extract32(tcr
, 0, 6);
11282 using64k
= extract32(tcr
, 14, 1);
11283 using16k
= extract32(tcr
, 15, 1);
11284 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11288 hpd
= extract32(tcr
, 24, 1);
11291 sh
= extract32(tcr
, 12, 2);
11292 ps
= extract32(tcr
, 16, 3);
11293 ds
= extract64(tcr
, 32, 1);
11296 * Bit 55 is always between the two regions, and is canonical for
11297 * determining if address tagging is enabled.
11299 select
= extract64(va
, 55, 1);
11301 tsz
= extract32(tcr
, 0, 6);
11302 epd
= extract32(tcr
, 7, 1);
11303 sh
= extract32(tcr
, 12, 2);
11304 using64k
= extract32(tcr
, 14, 1);
11305 using16k
= extract32(tcr
, 15, 1);
11306 hpd
= extract64(tcr
, 41, 1);
11308 int tg
= extract32(tcr
, 30, 2);
11309 using16k
= tg
== 1;
11310 using64k
= tg
== 3;
11311 tsz
= extract32(tcr
, 16, 6);
11312 epd
= extract32(tcr
, 23, 1);
11313 sh
= extract32(tcr
, 28, 2);
11314 hpd
= extract64(tcr
, 42, 1);
11316 ps
= extract64(tcr
, 32, 3);
11317 ds
= extract64(tcr
, 59, 1);
11320 if (cpu_isar_feature(aa64_st
, cpu
)) {
11321 max_tsz
= 48 - using64k
;
11327 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11328 * adjust the effective value of DS, as documented.
11332 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11338 case ARMMMUIdx_Stage2
:
11339 case ARMMMUIdx_Stage2_S
:
11341 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11343 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11348 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11350 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11359 if (tsz
> max_tsz
) {
11362 } else if (tsz
< min_tsz
) {
11369 /* Present TBI as a composite with TBID. */
11370 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11372 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11374 tbi
= (tbi
>> select
) & 1;
11376 return (ARMVAParameters
) {
11384 .using16k
= using16k
,
11385 .using64k
= using64k
,
11386 .tsz_oob
= tsz_oob
,
11391 #ifndef CONFIG_USER_ONLY
11392 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
11395 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11396 uint32_t el
= regime_el(env
, mmu_idx
);
11400 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
11402 if (mmu_idx
== ARMMMUIdx_Stage2
) {
11404 bool sext
= extract32(tcr
, 4, 1);
11405 bool sign
= extract32(tcr
, 3, 1);
11408 * If the sign-extend bit is not the same as t0sz[3], the result
11409 * is unpredictable. Flag this as a guest error.
11411 if (sign
!= sext
) {
11412 qemu_log_mask(LOG_GUEST_ERROR
,
11413 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
11415 tsz
= sextract32(tcr
, 0, 4) + 8;
11419 } else if (el
== 2) {
11421 tsz
= extract32(tcr
, 0, 3);
11423 hpd
= extract64(tcr
, 24, 1);
11426 int t0sz
= extract32(tcr
, 0, 3);
11427 int t1sz
= extract32(tcr
, 16, 3);
11430 select
= va
> (0xffffffffu
>> t0sz
);
11432 /* Note that we will detect errors later. */
11433 select
= va
>= ~(0xffffffffu
>> t1sz
);
11437 epd
= extract32(tcr
, 7, 1);
11438 hpd
= extract64(tcr
, 41, 1);
11441 epd
= extract32(tcr
, 23, 1);
11442 hpd
= extract64(tcr
, 42, 1);
11444 /* For aarch32, hpd0 is not enabled without t2e as well. */
11445 hpd
&= extract32(tcr
, 6, 1);
11448 return (ARMVAParameters
) {
11457 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
11459 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11460 * prot and page_size may not be filled in, and the populated fsr value provides
11461 * information on why the translation aborted, in the format of a long-format
11462 * DFSR/IFSR fault register, with the following caveats:
11463 * * the WnR bit is never set (the caller must do this).
11465 * @env: CPUARMState
11466 * @address: virtual address to get physical address for
11467 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
11468 * @mmu_idx: MMU index indicating required translation regime
11469 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
11470 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
11471 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
11472 * @phys_ptr: set to the physical address corresponding to the virtual address
11473 * @attrs: set to the memory transaction attributes to use
11474 * @prot: set to the permissions for the page containing phys_ptr
11475 * @page_size_ptr: set to the size of the page containing phys_ptr
11476 * @fi: set to fault info if the translation fails
11477 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11479 static bool get_phys_addr_lpae(CPUARMState
*env
, uint64_t address
,
11480 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11482 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
11483 target_ulong
*page_size_ptr
,
11484 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11486 ARMCPU
*cpu
= env_archcpu(env
);
11487 CPUState
*cs
= CPU(cpu
);
11488 /* Read an LPAE long-descriptor translation table. */
11489 ARMFaultType fault_type
= ARMFault_Translation
;
11491 ARMVAParameters param
;
11493 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
11494 uint32_t tableattrs
;
11495 target_ulong page_size
;
11498 int addrsize
, inputsize
, outputsize
;
11499 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
11500 int ap
, ns
, xn
, pxn
;
11501 uint32_t el
= regime_el(env
, mmu_idx
);
11502 uint64_t descaddrmask
;
11503 bool aarch64
= arm_el_is_aa64(env
, el
);
11504 bool guarded
= false;
11506 /* TODO: This code does not support shareability levels. */
11510 param
= aa64_va_parameters(env
, address
, mmu_idx
,
11511 access_type
!= MMU_INST_FETCH
);
11515 * If TxSZ is programmed to a value larger than the maximum,
11516 * or smaller than the effective minimum, it is IMPLEMENTATION
11517 * DEFINED whether we behave as if the field were programmed
11518 * within bounds, or if a level 0 Translation fault is generated.
11520 * With FEAT_LVA, fault on less than minimum becomes required,
11521 * so our choice is to always raise the fault.
11523 if (param
.tsz_oob
) {
11524 fault_type
= ARMFault_Translation
;
11528 addrsize
= 64 - 8 * param
.tbi
;
11529 inputsize
= 64 - param
.tsz
;
11532 * Bound PS by PARANGE to find the effective output address size.
11533 * ID_AA64MMFR0 is a read-only register so values outside of the
11534 * supported mappings can be considered an implementation error.
11536 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
11537 ps
= MIN(ps
, param
.ps
);
11538 assert(ps
< ARRAY_SIZE(pamax_map
));
11539 outputsize
= pamax_map
[ps
];
11541 param
= aa32_va_parameters(env
, address
, mmu_idx
);
11543 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
11544 inputsize
= addrsize
- param
.tsz
;
11549 * We determined the region when collecting the parameters, but we
11550 * have not yet validated that the address is valid for the region.
11551 * Extract the top bits and verify that they all match select.
11553 * For aa32, if inputsize == addrsize, then we have selected the
11554 * region by exclusion in aa32_va_parameters and there is no more
11555 * validation to do here.
11557 if (inputsize
< addrsize
) {
11558 target_ulong top_bits
= sextract64(address
, inputsize
,
11559 addrsize
- inputsize
);
11560 if (-top_bits
!= param
.select
) {
11561 /* The gap between the two regions is a Translation fault */
11562 fault_type
= ARMFault_Translation
;
11567 if (param
.using64k
) {
11569 } else if (param
.using16k
) {
11575 /* Note that QEMU ignores shareability and cacheability attributes,
11576 * so we don't need to do anything with the SH, ORGN, IRGN fields
11577 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11578 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11579 * implement any ASID-like capability so we can ignore it (instead
11580 * we will always flush the TLB any time the ASID is changed).
11582 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
11584 /* Here we should have set up all the parameters for the translation:
11585 * inputsize, ttbr, epd, stride, tbi
11589 /* Translation table walk disabled => Translation fault on TLB miss
11590 * Note: This is always 0 on 64-bit EL2 and EL3.
11595 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
11596 /* The starting level depends on the virtual address size (which can
11597 * be up to 48 bits) and the translation granule size. It indicates
11598 * the number of strides (stride bits at a time) needed to
11599 * consume the bits of the input address. In the pseudocode this is:
11600 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11601 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11602 * our 'stride + 3' and 'stride' is our 'stride'.
11603 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11604 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11605 * = 4 - (inputsize - 4) / stride;
11607 level
= 4 - (inputsize
- 4) / stride
;
11609 /* For stage 2 translations the starting level is specified by the
11610 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11612 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
11613 uint32_t sl2
= extract64(tcr
->raw_tcr
, 33, 1);
11614 uint32_t startlevel
;
11617 /* SL2 is RES0 unless DS=1 & 4kb granule. */
11618 if (param
.ds
&& stride
== 9 && sl2
) {
11621 fault_type
= ARMFault_Translation
;
11625 } else if (!aarch64
|| stride
== 9) {
11626 /* AArch32 or 4KB pages */
11627 startlevel
= 2 - sl0
;
11629 if (cpu_isar_feature(aa64_st
, cpu
)) {
11633 /* 16KB or 64KB pages */
11634 startlevel
= 3 - sl0
;
11637 /* Check that the starting level is valid. */
11638 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
11639 inputsize
, stride
, outputsize
);
11641 fault_type
= ARMFault_Translation
;
11644 level
= startlevel
;
11647 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
11648 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
11650 /* Now we can extract the actual base address from the TTBR */
11651 descaddr
= extract64(ttbr
, 0, 48);
11654 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
11656 * Otherwise, if the base address is out of range, raise AddressSizeFault.
11657 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
11658 * but we've just cleared the bits above 47, so simplify the test.
11660 if (outputsize
> 48) {
11661 descaddr
|= extract64(ttbr
, 2, 4) << 48;
11662 } else if (descaddr
>> outputsize
) {
11664 fault_type
= ARMFault_AddressSize
;
11669 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
11670 * and also to mask out CnP (bit 0) which could validly be non-zero.
11672 descaddr
&= ~indexmask
;
11675 * For AArch32, the address field in the descriptor goes up to bit 39
11676 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
11677 * or an AddressSize fault is raised. So for v8 we extract those SBZ
11678 * bits as part of the address, which will be checked via outputsize.
11679 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
11680 * the highest bits of a 52-bit output are placed elsewhere.
11683 descaddrmask
= MAKE_64BIT_MASK(0, 50);
11684 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
11685 descaddrmask
= MAKE_64BIT_MASK(0, 48);
11687 descaddrmask
= MAKE_64BIT_MASK(0, 40);
11689 descaddrmask
&= ~indexmask_grainsize
;
11691 /* Secure accesses start with the page table in secure memory and
11692 * can be downgraded to non-secure at any step. Non-secure accesses
11693 * remain non-secure. We implement this by just ORing in the NSTable/NS
11694 * bits at each step.
11696 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
11698 uint64_t descriptor
;
11701 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
11703 nstable
= extract32(tableattrs
, 4, 1);
11704 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
11705 if (fi
->type
!= ARMFault_None
) {
11709 if (!(descriptor
& 1) ||
11710 (!(descriptor
& 2) && (level
== 3))) {
11711 /* Invalid, or the Reserved level 3 encoding */
11715 descaddr
= descriptor
& descaddrmask
;
11718 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
11719 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
11720 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
11721 * raise AddressSizeFault.
11723 if (outputsize
> 48) {
11725 descaddr
|= extract64(descriptor
, 8, 2) << 50;
11727 descaddr
|= extract64(descriptor
, 12, 4) << 48;
11729 } else if (descaddr
>> outputsize
) {
11730 fault_type
= ARMFault_AddressSize
;
11734 if ((descriptor
& 2) && (level
< 3)) {
11735 /* Table entry. The top five bits are attributes which may
11736 * propagate down through lower levels of the table (and
11737 * which are all arranged so that 0 means "no effect", so
11738 * we can gather them up by ORing in the bits at each level).
11740 tableattrs
|= extract64(descriptor
, 59, 5);
11742 indexmask
= indexmask_grainsize
;
11746 * Block entry at level 1 or 2, or page entry at level 3.
11747 * These are basically the same thing, although the number
11748 * of bits we pull in from the vaddr varies. Note that although
11749 * descaddrmask masks enough of the low bits of the descriptor
11750 * to give a correct page or table address, the address field
11751 * in a block descriptor is smaller; so we need to explicitly
11752 * clear the lower bits here before ORing in the low vaddr bits.
11754 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
11755 descaddr
&= ~(page_size
- 1);
11756 descaddr
|= (address
& (page_size
- 1));
11757 /* Extract attributes from the descriptor */
11758 attrs
= extract64(descriptor
, 2, 10)
11759 | (extract64(descriptor
, 52, 12) << 10);
11761 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11762 /* Stage 2 table descriptors do not include any attribute fields */
11765 /* Merge in attributes from table descriptors */
11766 attrs
|= nstable
<< 3; /* NS */
11767 guarded
= extract64(descriptor
, 50, 1); /* GP */
11769 /* HPD disables all the table attributes except NSTable. */
11772 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
11773 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11774 * means "force PL1 access only", which means forcing AP[1] to 0.
11776 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
11777 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
11780 /* Here descaddr is the final physical address, and attributes
11781 * are all in attrs.
11783 fault_type
= ARMFault_AccessFlag
;
11784 if ((attrs
& (1 << 8)) == 0) {
11789 ap
= extract32(attrs
, 4, 2);
11791 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11792 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
11793 xn
= extract32(attrs
, 11, 2);
11794 *prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
11796 ns
= extract32(attrs
, 3, 1);
11797 xn
= extract32(attrs
, 12, 1);
11798 pxn
= extract32(attrs
, 11, 1);
11799 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
11802 fault_type
= ARMFault_Permission
;
11803 if (!(*prot
& (1 << access_type
))) {
11808 /* The NS bit will (as required by the architecture) have no effect if
11809 * the CPU doesn't support TZ or this is a non-secure translation
11810 * regime, because the attribute will already be non-secure.
11812 txattrs
->secure
= false;
11814 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11815 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
11816 arm_tlb_bti_gp(txattrs
) = true;
11819 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11820 cacheattrs
->attrs
= convert_stage2_attrs(env
, extract32(attrs
, 0, 4));
11822 /* Index into MAIR registers for cache attributes */
11823 uint8_t attrindx
= extract32(attrs
, 0, 3);
11824 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
11825 assert(attrindx
<= 7);
11826 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
11830 * For FEAT_LPA2 and effective DS, the SH field in the attributes
11831 * was re-purposed for output address bits. The SH attribute in
11832 * that case comes from TCR_ELx, which we extracted earlier.
11835 cacheattrs
->shareability
= param
.sh
;
11837 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
11840 *phys_ptr
= descaddr
;
11841 *page_size_ptr
= page_size
;
11845 fi
->type
= fault_type
;
11847 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11848 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
||
11849 mmu_idx
== ARMMMUIdx_Stage2_S
);
11850 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
11854 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
11856 int32_t address
, int *prot
)
11858 if (!arm_feature(env
, ARM_FEATURE_M
)) {
11859 *prot
= PAGE_READ
| PAGE_WRITE
;
11861 case 0xF0000000 ... 0xFFFFFFFF:
11862 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
11863 /* hivecs execing is ok */
11864 *prot
|= PAGE_EXEC
;
11867 case 0x00000000 ... 0x7FFFFFFF:
11868 *prot
|= PAGE_EXEC
;
11872 /* Default system address map for M profile cores.
11873 * The architecture specifies which regions are execute-never;
11874 * at the MPU level no other checks are defined.
11877 case 0x00000000 ... 0x1fffffff: /* ROM */
11878 case 0x20000000 ... 0x3fffffff: /* SRAM */
11879 case 0x60000000 ... 0x7fffffff: /* RAM */
11880 case 0x80000000 ... 0x9fffffff: /* RAM */
11881 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11883 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11884 case 0xa0000000 ... 0xbfffffff: /* Device */
11885 case 0xc0000000 ... 0xdfffffff: /* Device */
11886 case 0xe0000000 ... 0xffffffff: /* System */
11887 *prot
= PAGE_READ
| PAGE_WRITE
;
11890 g_assert_not_reached();
11895 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
11896 ARMMMUIdx mmu_idx
, bool is_user
)
11898 /* Return true if we should use the default memory map as a
11899 * "background" region if there are no hits against any MPU regions.
11901 CPUARMState
*env
= &cpu
->env
;
11907 if (arm_feature(env
, ARM_FEATURE_M
)) {
11908 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
11909 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
11911 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
11915 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
11917 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11918 return arm_feature(env
, ARM_FEATURE_M
) &&
11919 extract32(address
, 20, 12) == 0xe00;
11922 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
11924 /* True if address is in the M profile system region
11925 * 0xe0000000 - 0xffffffff
11927 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
11930 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
11931 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11932 hwaddr
*phys_ptr
, int *prot
,
11933 target_ulong
*page_size
,
11934 ARMMMUFaultInfo
*fi
)
11936 ARMCPU
*cpu
= env_archcpu(env
);
11938 bool is_user
= regime_is_user(env
, mmu_idx
);
11940 *phys_ptr
= address
;
11941 *page_size
= TARGET_PAGE_SIZE
;
11944 if (regime_translation_disabled(env
, mmu_idx
) ||
11945 m_is_ppb_region(env
, address
)) {
11946 /* MPU disabled or M profile PPB access: use default memory map.
11947 * The other case which uses the default memory map in the
11948 * v7M ARM ARM pseudocode is exception vector reads from the vector
11949 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11950 * which always does a direct read using address_space_ldl(), rather
11951 * than going via this function, so we don't need to check that here.
11953 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11954 } else { /* MPU enabled */
11955 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11956 /* region search */
11957 uint32_t base
= env
->pmsav7
.drbar
[n
];
11958 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
11960 bool srdis
= false;
11962 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
11967 qemu_log_mask(LOG_GUEST_ERROR
,
11968 "DRSR[%d]: Rsize field cannot be 0\n", n
);
11972 rmask
= (1ull << rsize
) - 1;
11974 if (base
& rmask
) {
11975 qemu_log_mask(LOG_GUEST_ERROR
,
11976 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
11977 "to DRSR region size, mask = 0x%" PRIx32
"\n",
11982 if (address
< base
|| address
> base
+ rmask
) {
11984 * Address not in this region. We must check whether the
11985 * region covers addresses in the same page as our address.
11986 * In that case we must not report a size that covers the
11987 * whole page for a subsequent hit against a different MPU
11988 * region or the background region, because it would result in
11989 * incorrect TLB hits for subsequent accesses to addresses that
11990 * are in this MPU region.
11992 if (ranges_overlap(base
, rmask
,
11993 address
& TARGET_PAGE_MASK
,
11994 TARGET_PAGE_SIZE
)) {
12000 /* Region matched */
12002 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
12004 uint32_t srdis_mask
;
12006 rsize
-= 3; /* sub region size (power of 2) */
12007 snd
= ((address
- base
) >> rsize
) & 0x7;
12008 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
12010 srdis_mask
= srdis
? 0x3 : 0x0;
12011 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
12012 /* This will check in groups of 2, 4 and then 8, whether
12013 * the subregion bits are consistent. rsize is incremented
12014 * back up to give the region size, considering consistent
12015 * adjacent subregions as one region. Stop testing if rsize
12016 * is already big enough for an entire QEMU page.
12018 int snd_rounded
= snd
& ~(i
- 1);
12019 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
12020 snd_rounded
+ 8, i
);
12021 if (srdis_mask
^ srdis_multi
) {
12024 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
12031 if (rsize
< TARGET_PAGE_BITS
) {
12032 *page_size
= 1 << rsize
;
12037 if (n
== -1) { /* no hits */
12038 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
12039 /* background fault */
12040 fi
->type
= ARMFault_Background
;
12043 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
12044 } else { /* a MPU hit! */
12045 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
12046 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
12048 if (m_is_system_region(env
, address
)) {
12049 /* System space is always execute never */
12053 if (is_user
) { /* User mode AP bit decoding */
12058 break; /* no access */
12060 *prot
|= PAGE_WRITE
;
12064 *prot
|= PAGE_READ
| PAGE_EXEC
;
12067 /* for v7M, same as 6; for R profile a reserved value */
12068 if (arm_feature(env
, ARM_FEATURE_M
)) {
12069 *prot
|= PAGE_READ
| PAGE_EXEC
;
12074 qemu_log_mask(LOG_GUEST_ERROR
,
12075 "DRACR[%d]: Bad value for AP bits: 0x%"
12076 PRIx32
"\n", n
, ap
);
12078 } else { /* Priv. mode AP bits decoding */
12081 break; /* no access */
12085 *prot
|= PAGE_WRITE
;
12089 *prot
|= PAGE_READ
| PAGE_EXEC
;
12092 /* for v7M, same as 6; for R profile a reserved value */
12093 if (arm_feature(env
, ARM_FEATURE_M
)) {
12094 *prot
|= PAGE_READ
| PAGE_EXEC
;
12099 qemu_log_mask(LOG_GUEST_ERROR
,
12100 "DRACR[%d]: Bad value for AP bits: 0x%"
12101 PRIx32
"\n", n
, ap
);
12105 /* execute never */
12107 *prot
&= ~PAGE_EXEC
;
12112 fi
->type
= ARMFault_Permission
;
12114 return !(*prot
& (1 << access_type
));
12117 static bool v8m_is_sau_exempt(CPUARMState
*env
,
12118 uint32_t address
, MMUAccessType access_type
)
12120 /* The architecture specifies that certain address ranges are
12121 * exempt from v8M SAU/IDAU checks.
12124 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
12125 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
12126 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
12127 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
12128 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
12129 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
12132 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
12133 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12134 V8M_SAttributes
*sattrs
)
12136 /* Look up the security attributes for this address. Compare the
12137 * pseudocode SecurityCheck() function.
12138 * We assume the caller has zero-initialized *sattrs.
12140 ARMCPU
*cpu
= env_archcpu(env
);
12142 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
12143 int idau_region
= IREGION_NOTVALID
;
12144 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
12145 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
12148 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
12149 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
12151 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
12155 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
12156 /* 0xf0000000..0xffffffff is always S for insn fetches */
12160 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
12161 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
12165 if (idau_region
!= IREGION_NOTVALID
) {
12166 sattrs
->irvalid
= true;
12167 sattrs
->iregion
= idau_region
;
12170 switch (env
->sau
.ctrl
& 3) {
12171 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
12173 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
12176 default: /* SAU.ENABLE == 1 */
12177 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
12178 if (env
->sau
.rlar
[r
] & 1) {
12179 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
12180 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
12182 if (base
<= address
&& limit
>= address
) {
12183 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
12184 sattrs
->subpage
= true;
12186 if (sattrs
->srvalid
) {
12187 /* If we hit in more than one region then we must report
12188 * as Secure, not NS-Callable, with no valid region
12191 sattrs
->ns
= false;
12192 sattrs
->nsc
= false;
12193 sattrs
->sregion
= 0;
12194 sattrs
->srvalid
= false;
12197 if (env
->sau
.rlar
[r
] & 2) {
12198 sattrs
->nsc
= true;
12202 sattrs
->srvalid
= true;
12203 sattrs
->sregion
= r
;
12207 * Address not in this region. We must check whether the
12208 * region covers addresses in the same page as our address.
12209 * In that case we must not report a size that covers the
12210 * whole page for a subsequent hit against a different MPU
12211 * region or the background region, because it would result
12212 * in incorrect TLB hits for subsequent accesses to
12213 * addresses that are in this MPU region.
12215 if (limit
>= base
&&
12216 ranges_overlap(base
, limit
- base
+ 1,
12218 TARGET_PAGE_SIZE
)) {
12219 sattrs
->subpage
= true;
12228 * The IDAU will override the SAU lookup results if it specifies
12229 * higher security than the SAU does.
12232 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
12233 sattrs
->ns
= false;
12234 sattrs
->nsc
= idau_nsc
;
12239 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
12240 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12241 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
12242 int *prot
, bool *is_subpage
,
12243 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
12245 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
12246 * that a full phys-to-virt translation does).
12247 * mregion is (if not NULL) set to the region number which matched,
12248 * or -1 if no region number is returned (MPU off, address did not
12249 * hit a region, address hit in multiple regions).
12250 * We set is_subpage to true if the region hit doesn't cover the
12251 * entire TARGET_PAGE the address is within.
12253 ARMCPU
*cpu
= env_archcpu(env
);
12254 bool is_user
= regime_is_user(env
, mmu_idx
);
12255 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
12257 int matchregion
= -1;
12259 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
12260 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
12262 *is_subpage
= false;
12263 *phys_ptr
= address
;
12269 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
12270 * was an exception vector read from the vector table (which is always
12271 * done using the default system address map), because those accesses
12272 * are done in arm_v7m_load_vector(), which always does a direct
12273 * read using address_space_ldl(), rather than going via this function.
12275 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
12277 } else if (m_is_ppb_region(env
, address
)) {
12280 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
12284 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
12285 /* region search */
12286 /* Note that the base address is bits [31:5] from the register
12287 * with bits [4:0] all zeroes, but the limit address is bits
12288 * [31:5] from the register with bits [4:0] all ones.
12290 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
12291 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
12293 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
12294 /* Region disabled */
12298 if (address
< base
|| address
> limit
) {
12300 * Address not in this region. We must check whether the
12301 * region covers addresses in the same page as our address.
12302 * In that case we must not report a size that covers the
12303 * whole page for a subsequent hit against a different MPU
12304 * region or the background region, because it would result in
12305 * incorrect TLB hits for subsequent accesses to addresses that
12306 * are in this MPU region.
12308 if (limit
>= base
&&
12309 ranges_overlap(base
, limit
- base
+ 1,
12311 TARGET_PAGE_SIZE
)) {
12312 *is_subpage
= true;
12317 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
12318 *is_subpage
= true;
12321 if (matchregion
!= -1) {
12322 /* Multiple regions match -- always a failure (unlike
12323 * PMSAv7 where highest-numbered-region wins)
12325 fi
->type
= ARMFault_Permission
;
12336 /* background fault */
12337 fi
->type
= ARMFault_Background
;
12341 if (matchregion
== -1) {
12342 /* hit using the background region */
12343 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
12345 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
12346 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
12349 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
12350 pxn
= extract32(env
->pmsav8
.rlar
[secure
][matchregion
], 4, 1);
12353 if (m_is_system_region(env
, address
)) {
12354 /* System space is always execute never */
12358 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
12359 if (*prot
&& !xn
&& !(pxn
&& !is_user
)) {
12360 *prot
|= PAGE_EXEC
;
12362 /* We don't need to look the attribute up in the MAIR0/MAIR1
12363 * registers because that only tells us about cacheability.
12366 *mregion
= matchregion
;
12370 fi
->type
= ARMFault_Permission
;
12372 return !(*prot
& (1 << access_type
));
12376 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
12377 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12378 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
12379 int *prot
, target_ulong
*page_size
,
12380 ARMMMUFaultInfo
*fi
)
12382 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
12383 V8M_SAttributes sattrs
= {};
12385 bool mpu_is_subpage
;
12387 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
12388 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
12389 if (access_type
== MMU_INST_FETCH
) {
12390 /* Instruction fetches always use the MMU bank and the
12391 * transaction attribute determined by the fetch address,
12392 * regardless of CPU state. This is painful for QEMU
12393 * to handle, because it would mean we need to encode
12394 * into the mmu_idx not just the (user, negpri) information
12395 * for the current security state but also that for the
12396 * other security state, which would balloon the number
12397 * of mmu_idx values needed alarmingly.
12398 * Fortunately we can avoid this because it's not actually
12399 * possible to arbitrarily execute code from memory with
12400 * the wrong security attribute: it will always generate
12401 * an exception of some kind or another, apart from the
12402 * special case of an NS CPU executing an SG instruction
12403 * in S&NSC memory. So we always just fail the translation
12404 * here and sort things out in the exception handler
12405 * (including possibly emulating an SG instruction).
12407 if (sattrs
.ns
!= !secure
) {
12409 fi
->type
= ARMFault_QEMU_NSCExec
;
12411 fi
->type
= ARMFault_QEMU_SFault
;
12413 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
12414 *phys_ptr
= address
;
12419 /* For data accesses we always use the MMU bank indicated
12420 * by the current CPU state, but the security attributes
12421 * might downgrade a secure access to nonsecure.
12424 txattrs
->secure
= false;
12425 } else if (!secure
) {
12426 /* NS access to S memory must fault.
12427 * Architecturally we should first check whether the
12428 * MPU information for this address indicates that we
12429 * are doing an unaligned access to Device memory, which
12430 * should generate a UsageFault instead. QEMU does not
12431 * currently check for that kind of unaligned access though.
12432 * If we added it we would need to do so as a special case
12433 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
12435 fi
->type
= ARMFault_QEMU_SFault
;
12436 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
12437 *phys_ptr
= address
;
12444 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
12445 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
12446 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
12450 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
12451 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12452 hwaddr
*phys_ptr
, int *prot
,
12453 ARMMMUFaultInfo
*fi
)
12458 bool is_user
= regime_is_user(env
, mmu_idx
);
12460 if (regime_translation_disabled(env
, mmu_idx
)) {
12461 /* MPU disabled. */
12462 *phys_ptr
= address
;
12463 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12467 *phys_ptr
= address
;
12468 for (n
= 7; n
>= 0; n
--) {
12469 base
= env
->cp15
.c6_region
[n
];
12470 if ((base
& 1) == 0) {
12473 mask
= 1 << ((base
>> 1) & 0x1f);
12474 /* Keep this shift separate from the above to avoid an
12475 (undefined) << 32. */
12476 mask
= (mask
<< 1) - 1;
12477 if (((base
^ address
) & ~mask
) == 0) {
12482 fi
->type
= ARMFault_Background
;
12486 if (access_type
== MMU_INST_FETCH
) {
12487 mask
= env
->cp15
.pmsav5_insn_ap
;
12489 mask
= env
->cp15
.pmsav5_data_ap
;
12491 mask
= (mask
>> (n
* 4)) & 0xf;
12494 fi
->type
= ARMFault_Permission
;
12499 fi
->type
= ARMFault_Permission
;
12503 *prot
= PAGE_READ
| PAGE_WRITE
;
12508 *prot
|= PAGE_WRITE
;
12512 *prot
= PAGE_READ
| PAGE_WRITE
;
12516 fi
->type
= ARMFault_Permission
;
12526 /* Bad permission. */
12527 fi
->type
= ARMFault_Permission
;
12531 *prot
|= PAGE_EXEC
;
12535 /* Combine either inner or outer cacheability attributes for normal
12536 * memory, according to table D4-42 and pseudocode procedure
12537 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
12539 * NB: only stage 1 includes allocation hints (RW bits), leading to
12542 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
12544 if (s1
== 4 || s2
== 4) {
12545 /* non-cacheable has precedence */
12547 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
12548 /* stage 1 write-through takes precedence */
12550 } else if (extract32(s2
, 2, 2) == 2) {
12551 /* stage 2 write-through takes precedence, but the allocation hint
12552 * is still taken from stage 1
12554 return (2 << 2) | extract32(s1
, 0, 2);
12555 } else { /* write-back */
12560 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
12561 * and CombineS1S2Desc()
12563 * @s1: Attributes from stage 1 walk
12564 * @s2: Attributes from stage 2 walk
12566 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
12568 uint8_t s1lo
, s2lo
, s1hi
, s2hi
;
12570 bool tagged
= false;
12572 if (s1
.attrs
== 0xf0) {
12577 s1lo
= extract32(s1
.attrs
, 0, 4);
12578 s2lo
= extract32(s2
.attrs
, 0, 4);
12579 s1hi
= extract32(s1
.attrs
, 4, 4);
12580 s2hi
= extract32(s2
.attrs
, 4, 4);
12582 /* Combine shareability attributes (table D4-43) */
12583 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
12584 /* if either are outer-shareable, the result is outer-shareable */
12585 ret
.shareability
= 2;
12586 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
12587 /* if either are inner-shareable, the result is inner-shareable */
12588 ret
.shareability
= 3;
12590 /* both non-shareable */
12591 ret
.shareability
= 0;
12594 /* Combine memory type and cacheability attributes */
12595 if (s1hi
== 0 || s2hi
== 0) {
12596 /* Device has precedence over normal */
12597 if (s1lo
== 0 || s2lo
== 0) {
12598 /* nGnRnE has precedence over anything */
12600 } else if (s1lo
== 4 || s2lo
== 4) {
12601 /* non-Reordering has precedence over Reordering */
12602 ret
.attrs
= 4; /* nGnRE */
12603 } else if (s1lo
== 8 || s2lo
== 8) {
12604 /* non-Gathering has precedence over Gathering */
12605 ret
.attrs
= 8; /* nGRE */
12607 ret
.attrs
= 0xc; /* GRE */
12610 /* Any location for which the resultant memory type is any
12611 * type of Device memory is always treated as Outer Shareable.
12613 ret
.shareability
= 2;
12614 } else { /* Normal memory */
12615 /* Outer/inner cacheability combine independently */
12616 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
12617 | combine_cacheattr_nibble(s1lo
, s2lo
);
12619 if (ret
.attrs
== 0x44) {
12620 /* Any location for which the resultant memory type is Normal
12621 * Inner Non-cacheable, Outer Non-cacheable is always treated
12622 * as Outer Shareable.
12624 ret
.shareability
= 2;
12628 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
12629 if (tagged
&& ret
.attrs
== 0xff) {
12637 /* get_phys_addr - get the physical address for this virtual address
12639 * Find the physical address corresponding to the given virtual address,
12640 * by doing a translation table walk on MMU based systems or using the
12641 * MPU state on MPU based systems.
12643 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12644 * prot and page_size may not be filled in, and the populated fsr value provides
12645 * information on why the translation aborted, in the format of a
12646 * DFSR/IFSR fault register, with the following caveats:
12647 * * we honour the short vs long DFSR format differences.
12648 * * the WnR bit is never set (the caller must do this).
12649 * * for PSMAv5 based systems we don't bother to return a full FSR format
12652 * @env: CPUARMState
12653 * @address: virtual address to get physical address for
12654 * @access_type: 0 for read, 1 for write, 2 for execute
12655 * @mmu_idx: MMU index indicating required translation regime
12656 * @phys_ptr: set to the physical address corresponding to the virtual address
12657 * @attrs: set to the memory transaction attributes to use
12658 * @prot: set to the permissions for the page containing phys_ptr
12659 * @page_size: set to the size of the page containing phys_ptr
12660 * @fi: set to fault info if the translation fails
12661 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
12663 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
12664 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12665 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
12666 target_ulong
*page_size
,
12667 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
12669 ARMMMUIdx s1_mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12671 if (mmu_idx
!= s1_mmu_idx
) {
12672 /* Call ourselves recursively to do the stage 1 and then stage 2
12673 * translations if mmu_idx is a two-stage regime.
12675 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
12680 ARMCacheAttrs cacheattrs2
= {};
12681 ARMMMUIdx s2_mmu_idx
;
12684 ret
= get_phys_addr(env
, address
, access_type
, s1_mmu_idx
, &ipa
,
12685 attrs
, prot
, page_size
, fi
, cacheattrs
);
12687 /* If S1 fails or S2 is disabled, return early. */
12688 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
12693 ipa_secure
= attrs
->secure
;
12694 if (arm_is_secure_below_el3(env
)) {
12696 attrs
->secure
= !(env
->cp15
.vstcr_el2
.raw_tcr
& VSTCR_SW
);
12698 attrs
->secure
= !(env
->cp15
.vtcr_el2
.raw_tcr
& VTCR_NSW
);
12701 assert(!ipa_secure
);
12704 s2_mmu_idx
= attrs
->secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
12705 is_el0
= mmu_idx
== ARMMMUIdx_E10_0
|| mmu_idx
== ARMMMUIdx_SE10_0
;
12707 /* S1 is done. Now do S2 translation. */
12708 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, s2_mmu_idx
, is_el0
,
12709 phys_ptr
, attrs
, &s2_prot
,
12710 page_size
, fi
, &cacheattrs2
);
12712 /* Combine the S1 and S2 perms. */
12715 /* If S2 fails, return early. */
12720 /* Combine the S1 and S2 cache attributes. */
12721 if (arm_hcr_el2_eff(env
) & HCR_DC
) {
12723 * HCR.DC forces the first stage attributes to
12724 * Normal Non-Shareable,
12725 * Inner Write-Back Read-Allocate Write-Allocate,
12726 * Outer Write-Back Read-Allocate Write-Allocate.
12727 * Do not overwrite Tagged within attrs.
12729 if (cacheattrs
->attrs
!= 0xf0) {
12730 cacheattrs
->attrs
= 0xff;
12732 cacheattrs
->shareability
= 0;
12734 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
12736 /* Check if IPA translates to secure or non-secure PA space. */
12737 if (arm_is_secure_below_el3(env
)) {
12740 !(env
->cp15
.vstcr_el2
.raw_tcr
& (VSTCR_SA
| VSTCR_SW
));
12743 !((env
->cp15
.vtcr_el2
.raw_tcr
& (VTCR_NSA
| VTCR_NSW
))
12744 || (env
->cp15
.vstcr_el2
.raw_tcr
& (VSTCR_SA
| VSTCR_SW
)));
12750 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12752 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12756 /* The page table entries may downgrade secure to non-secure, but
12757 * cannot upgrade an non-secure translation regime's attributes
12760 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
12761 attrs
->user
= regime_is_user(env
, mmu_idx
);
12763 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12764 * In v7 and earlier it affects all stage 1 translations.
12766 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
12767 && !arm_feature(env
, ARM_FEATURE_V8
)) {
12768 if (regime_el(env
, mmu_idx
) == 3) {
12769 address
+= env
->cp15
.fcseidr_s
;
12771 address
+= env
->cp15
.fcseidr_ns
;
12775 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
12777 *page_size
= TARGET_PAGE_SIZE
;
12779 if (arm_feature(env
, ARM_FEATURE_V8
)) {
12781 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
12782 phys_ptr
, attrs
, prot
, page_size
, fi
);
12783 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
12785 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
12786 phys_ptr
, prot
, page_size
, fi
);
12789 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
12790 phys_ptr
, prot
, fi
);
12792 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
12793 " mmu_idx %u -> %s (prot %c%c%c)\n",
12794 access_type
== MMU_DATA_LOAD
? "reading" :
12795 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
12796 (uint32_t)address
, mmu_idx
,
12797 ret
? "Miss" : "Hit",
12798 *prot
& PAGE_READ
? 'r' : '-',
12799 *prot
& PAGE_WRITE
? 'w' : '-',
12800 *prot
& PAGE_EXEC
? 'x' : '-');
12805 /* Definitely a real MMU, not an MPU */
12807 if (regime_translation_disabled(env
, mmu_idx
)) {
12812 * MMU disabled. S1 addresses within aa64 translation regimes are
12813 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
12815 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
12816 int r_el
= regime_el(env
, mmu_idx
);
12817 if (arm_el_is_aa64(env
, r_el
)) {
12818 int pamax
= arm_pamax(env_archcpu(env
));
12819 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
].raw_tcr
;
12822 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12823 if (access_type
== MMU_INST_FETCH
) {
12824 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12826 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
12827 addrtop
= (tbi
? 55 : 63);
12829 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
12830 fi
->type
= ARMFault_AddressSize
;
12832 fi
->stage2
= false;
12837 * When TBI is disabled, we've just validated that all of the
12838 * bits above PAMax are zero, so logically we only need to
12839 * clear the top byte for TBI. But it's clearer to follow
12840 * the pseudocode set of addrdesc.paddress.
12842 address
= extract64(address
, 0, 52);
12845 *phys_ptr
= address
;
12846 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12847 *page_size
= TARGET_PAGE_SIZE
;
12849 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
12850 hcr
= arm_hcr_el2_eff(env
);
12851 cacheattrs
->shareability
= 0;
12852 if (hcr
& HCR_DC
) {
12853 if (hcr
& HCR_DCT
) {
12854 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
12856 memattr
= 0xff; /* Normal, WB, RWA */
12858 } else if (access_type
== MMU_INST_FETCH
) {
12859 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
12860 memattr
= 0xee; /* Normal, WT, RA, NT */
12862 memattr
= 0x44; /* Normal, NC, No */
12864 cacheattrs
->shareability
= 2; /* outer sharable */
12866 memattr
= 0x00; /* Device, nGnRnE */
12868 cacheattrs
->attrs
= memattr
;
12872 if (regime_using_lpae_format(env
, mmu_idx
)) {
12873 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, false,
12874 phys_ptr
, attrs
, prot
, page_size
,
12876 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
12877 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
12878 phys_ptr
, attrs
, prot
, page_size
, fi
);
12880 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
12881 phys_ptr
, prot
, page_size
, fi
);
12885 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
12888 ARMCPU
*cpu
= ARM_CPU(cs
);
12889 CPUARMState
*env
= &cpu
->env
;
12891 target_ulong page_size
;
12894 ARMMMUFaultInfo fi
= {};
12895 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
12896 ARMCacheAttrs cacheattrs
= {};
12898 *attrs
= (MemTxAttrs
) {};
12900 ret
= get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &phys_addr
,
12901 attrs
, &prot
, &page_size
, &fi
, &cacheattrs
);
12911 /* Note that signed overflow is undefined in C. The following routines are
12912 careful to use unsigned types where modulo arithmetic is required.
12913 Failure to do so _will_ break on newer gcc. */
12915 /* Signed saturating arithmetic. */
12917 /* Perform 16-bit signed saturating addition. */
12918 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
12923 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
12932 /* Perform 8-bit signed saturating addition. */
12933 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
12938 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
12947 /* Perform 16-bit signed saturating subtraction. */
12948 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
12953 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
12962 /* Perform 8-bit signed saturating subtraction. */
12963 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
12968 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
12977 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12978 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12979 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12980 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12983 #include "op_addsub.h"
12985 /* Unsigned saturating arithmetic. */
12986 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
12995 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
13003 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
13012 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
13020 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
13021 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
13022 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
13023 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
13026 #include "op_addsub.h"
13028 /* Signed modulo arithmetic. */
13029 #define SARITH16(a, b, n, op) do { \
13031 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
13032 RESULT(sum, n, 16); \
13034 ge |= 3 << (n * 2); \
13037 #define SARITH8(a, b, n, op) do { \
13039 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
13040 RESULT(sum, n, 8); \
13046 #define ADD16(a, b, n) SARITH16(a, b, n, +)
13047 #define SUB16(a, b, n) SARITH16(a, b, n, -)
13048 #define ADD8(a, b, n) SARITH8(a, b, n, +)
13049 #define SUB8(a, b, n) SARITH8(a, b, n, -)
13053 #include "op_addsub.h"
13055 /* Unsigned modulo arithmetic. */
13056 #define ADD16(a, b, n) do { \
13058 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
13059 RESULT(sum, n, 16); \
13060 if ((sum >> 16) == 1) \
13061 ge |= 3 << (n * 2); \
13064 #define ADD8(a, b, n) do { \
13066 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
13067 RESULT(sum, n, 8); \
13068 if ((sum >> 8) == 1) \
13072 #define SUB16(a, b, n) do { \
13074 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
13075 RESULT(sum, n, 16); \
13076 if ((sum >> 16) == 0) \
13077 ge |= 3 << (n * 2); \
13080 #define SUB8(a, b, n) do { \
13082 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
13083 RESULT(sum, n, 8); \
13084 if ((sum >> 8) == 0) \
13091 #include "op_addsub.h"
13093 /* Halved signed arithmetic. */
13094 #define ADD16(a, b, n) \
13095 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
13096 #define SUB16(a, b, n) \
13097 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
13098 #define ADD8(a, b, n) \
13099 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
13100 #define SUB8(a, b, n) \
13101 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
13104 #include "op_addsub.h"
13106 /* Halved unsigned arithmetic. */
13107 #define ADD16(a, b, n) \
13108 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
13109 #define SUB16(a, b, n) \
13110 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
13111 #define ADD8(a, b, n) \
13112 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
13113 #define SUB8(a, b, n) \
13114 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
13117 #include "op_addsub.h"
13119 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
13127 /* Unsigned sum of absolute byte differences. */
13128 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
13131 sum
= do_usad(a
, b
);
13132 sum
+= do_usad(a
>> 8, b
>> 8);
13133 sum
+= do_usad(a
>> 16, b
>> 16);
13134 sum
+= do_usad(a
>> 24, b
>> 24);
13138 /* For ARMv6 SEL instruction. */
13139 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
13151 mask
|= 0xff000000;
13152 return (a
& mask
) | (b
& ~mask
);
13156 * The upper bytes of val (above the number specified by 'bytes') must have
13157 * been zeroed out by the caller.
13159 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13163 stl_le_p(buf
, val
);
13165 /* zlib crc32 converts the accumulator and output to one's complement. */
13166 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
13169 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13173 stl_le_p(buf
, val
);
13175 /* Linux crc32c converts the output to one's complement. */
13176 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
13179 /* Return the exception level to which FP-disabled exceptions should
13180 * be taken, or 0 if FP is enabled.
13182 int fp_exception_el(CPUARMState
*env
, int cur_el
)
13184 #ifndef CONFIG_USER_ONLY
13187 /* CPACR and the CPTR registers don't exist before v6, so FP is
13188 * always accessible
13190 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
13194 if (arm_feature(env
, ARM_FEATURE_M
)) {
13195 /* CPACR can cause a NOCP UsageFault taken to current security state */
13196 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
13200 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
13201 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
13202 /* FP insns cause a NOCP UsageFault taken to Secure */
13210 hcr_el2
= arm_hcr_el2_eff(env
);
13212 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
13213 * 0, 2 : trap EL0 and EL1/PL1 accesses
13214 * 1 : trap only EL0 accesses
13215 * 3 : trap no accesses
13216 * This register is ignored if E2H+TGE are both set.
13218 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
13219 int fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
13224 if (cur_el
== 0 || cur_el
== 1) {
13225 /* Trap to PL1, which might be EL1 or EL3 */
13226 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
13231 if (cur_el
== 3 && !is_a64(env
)) {
13232 /* Secure PL1 running at EL3 */
13247 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
13248 * to control non-secure access to the FPU. It doesn't have any
13249 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
13251 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
13252 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
13253 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
13254 /* FP insns act as UNDEF */
13255 return cur_el
== 2 ? 2 : 1;
13260 * CPTR_EL2 is present in v7VE or v8, and changes format
13261 * with HCR_EL2.E2H (regardless of TGE).
13264 if (hcr_el2
& HCR_E2H
) {
13265 /* Check CPTR_EL2.FPEN. */
13266 switch (extract32(env
->cp15
.cptr_el
[2], 20, 2)) {
13268 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
13276 } else if (arm_is_el2_enabled(env
)) {
13277 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
13283 /* CPTR_EL3 : present in v8 */
13284 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
13285 /* Trap all FP ops to EL3 */
13292 /* Return the exception level we're running at if this is our mmu_idx */
13293 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
13295 if (mmu_idx
& ARM_MMU_IDX_M
) {
13296 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
13300 case ARMMMUIdx_E10_0
:
13301 case ARMMMUIdx_E20_0
:
13302 case ARMMMUIdx_SE10_0
:
13303 case ARMMMUIdx_SE20_0
:
13305 case ARMMMUIdx_E10_1
:
13306 case ARMMMUIdx_E10_1_PAN
:
13307 case ARMMMUIdx_SE10_1
:
13308 case ARMMMUIdx_SE10_1_PAN
:
13311 case ARMMMUIdx_E20_2
:
13312 case ARMMMUIdx_E20_2_PAN
:
13313 case ARMMMUIdx_SE2
:
13314 case ARMMMUIdx_SE20_2
:
13315 case ARMMMUIdx_SE20_2_PAN
:
13317 case ARMMMUIdx_SE3
:
13320 g_assert_not_reached();
13325 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
13327 g_assert_not_reached();
13331 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
13336 if (arm_feature(env
, ARM_FEATURE_M
)) {
13337 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
13340 /* See ARM pseudo-function ELIsInHost. */
13343 hcr
= arm_hcr_el2_eff(env
);
13344 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
13345 idx
= ARMMMUIdx_E20_0
;
13347 idx
= ARMMMUIdx_E10_0
;
13351 if (env
->pstate
& PSTATE_PAN
) {
13352 idx
= ARMMMUIdx_E10_1_PAN
;
13354 idx
= ARMMMUIdx_E10_1
;
13358 /* Note that TGE does not apply at EL2. */
13359 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
13360 if (env
->pstate
& PSTATE_PAN
) {
13361 idx
= ARMMMUIdx_E20_2_PAN
;
13363 idx
= ARMMMUIdx_E20_2
;
13366 idx
= ARMMMUIdx_E2
;
13370 return ARMMMUIdx_SE3
;
13372 g_assert_not_reached();
13375 if (arm_is_secure_below_el3(env
)) {
13376 idx
&= ~ARM_MMU_IDX_A_NS
;
13382 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
13384 return arm_mmu_idx_el(env
, arm_current_el(env
));
13387 #ifndef CONFIG_USER_ONLY
13388 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
13390 return stage_1_mmu_idx(arm_mmu_idx(env
));
13394 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
13396 CPUARMTBFlags flags
)
13398 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
13399 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
13401 if (arm_singlestep_active(env
)) {
13402 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
13407 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
13409 CPUARMTBFlags flags
)
13411 bool sctlr_b
= arm_sctlr_b(env
);
13414 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
13416 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
13417 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
13419 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
13421 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
13424 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
13427 CPUARMTBFlags flags
= {};
13428 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
13430 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
13431 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
13432 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
13435 if (arm_v7m_is_handler_mode(env
)) {
13436 DP_TBFLAG_M32(flags
, HANDLER
, 1);
13440 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
13441 * is suppressing them because the requested execution priority
13444 if (arm_feature(env
, ARM_FEATURE_V8
) &&
13445 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
13446 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
13447 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
13450 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
13453 static CPUARMTBFlags
rebuild_hflags_aprofile(CPUARMState
*env
)
13455 CPUARMTBFlags flags
= {};
13457 DP_TBFLAG_ANY(flags
, DEBUG_TARGET_EL
, arm_debug_target_el(env
));
13461 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
13464 CPUARMTBFlags flags
= rebuild_hflags_aprofile(env
);
13465 int el
= arm_current_el(env
);
13467 if (arm_sctlr(env
, el
) & SCTLR_A
) {
13468 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
13471 if (arm_el_is_aa64(env
, 1)) {
13472 DP_TBFLAG_A32(flags
, VFPEN
, 1);
13475 if (el
< 2 && env
->cp15
.hstr_el2
&&
13476 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
13477 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
13480 if (env
->uncached_cpsr
& CPSR_IL
) {
13481 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
13484 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
13487 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
13490 CPUARMTBFlags flags
= rebuild_hflags_aprofile(env
);
13491 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
13492 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
13496 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
13498 /* Get control bits for tagged addresses. */
13499 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
13500 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
13502 DP_TBFLAG_A64(flags
, TBII
, tbii
);
13503 DP_TBFLAG_A64(flags
, TBID
, tbid
);
13505 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
13506 int sve_el
= sve_exception_el(env
, el
);
13510 * If SVE is disabled, but FP is enabled,
13511 * then the effective len is 0.
13513 if (sve_el
!= 0 && fp_el
== 0) {
13516 zcr_len
= sve_zcr_len_for_el(env
, el
);
13518 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
13519 DP_TBFLAG_A64(flags
, ZCR_LEN
, zcr_len
);
13522 sctlr
= regime_sctlr(env
, stage1
);
13524 if (sctlr
& SCTLR_A
) {
13525 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
13528 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
13529 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
13532 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
13534 * In order to save space in flags, we record only whether
13535 * pauth is "inactive", meaning all insns are implemented as
13536 * a nop, or "active" when some action must be performed.
13537 * The decision of which action to take is left to a helper.
13539 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
13540 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
13544 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
13545 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
13546 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
13547 DP_TBFLAG_A64(flags
, BT
, 1);
13551 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
13552 if (!(env
->pstate
& PSTATE_UAO
)) {
13554 case ARMMMUIdx_E10_1
:
13555 case ARMMMUIdx_E10_1_PAN
:
13556 case ARMMMUIdx_SE10_1
:
13557 case ARMMMUIdx_SE10_1_PAN
:
13558 /* TODO: ARMv8.3-NV */
13559 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
13561 case ARMMMUIdx_E20_2
:
13562 case ARMMMUIdx_E20_2_PAN
:
13563 case ARMMMUIdx_SE20_2
:
13564 case ARMMMUIdx_SE20_2_PAN
:
13566 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
13567 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
13569 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
13570 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
13578 if (env
->pstate
& PSTATE_IL
) {
13579 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
13582 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
13584 * Set MTE_ACTIVE if any access may be Checked, and leave clear
13585 * if all accesses must be Unchecked:
13586 * 1) If no TBI, then there are no tags in the address to check,
13587 * 2) If Tag Check Override, then all accesses are Unchecked,
13588 * 3) If Tag Check Fail == 0, then Checked access have no effect,
13589 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
13591 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
13592 DP_TBFLAG_A64(flags
, ATA
, 1);
13594 && !(env
->pstate
& PSTATE_TCO
)
13595 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
13596 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
13599 /* And again for unprivileged accesses, if required. */
13600 if (EX_TBFLAG_A64(flags
, UNPRIV
)
13602 && !(env
->pstate
& PSTATE_TCO
)
13603 && (sctlr
& SCTLR_TCF0
)
13604 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
13605 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
13607 /* Cache TCMA as well as TBI. */
13608 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
13611 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
13614 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
13616 int el
= arm_current_el(env
);
13617 int fp_el
= fp_exception_el(env
, el
);
13618 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13621 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
13622 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
13623 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13625 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13629 void arm_rebuild_hflags(CPUARMState
*env
)
13631 env
->hflags
= rebuild_hflags_internal(env
);
13635 * If we have triggered a EL state change we can't rely on the
13636 * translator having passed it to us, we need to recompute.
13638 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
13640 int el
= arm_current_el(env
);
13641 int fp_el
= fp_exception_el(env
, el
);
13642 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13644 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13647 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
13649 int fp_el
= fp_exception_el(env
, el
);
13650 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13652 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13656 * If we have triggered a EL state change we can't rely on the
13657 * translator having passed it to us, we need to recompute.
13659 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
13661 int el
= arm_current_el(env
);
13662 int fp_el
= fp_exception_el(env
, el
);
13663 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13664 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13667 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
13669 int fp_el
= fp_exception_el(env
, el
);
13670 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13672 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13675 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
13677 int fp_el
= fp_exception_el(env
, el
);
13678 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13680 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
13683 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
13685 #ifdef CONFIG_DEBUG_TCG
13686 CPUARMTBFlags c
= env
->hflags
;
13687 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
13689 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
13690 fprintf(stderr
, "TCG hflags mismatch "
13691 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
13692 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
13693 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
13699 static bool mve_no_pred(CPUARMState
*env
)
13702 * Return true if there is definitely no predication of MVE
13703 * instructions by VPR or LTPSIZE. (Returning false even if there
13704 * isn't any predication is OK; generated code will just be
13706 * If the CPU does not implement MVE then this TB flag is always 0.
13708 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
13709 * logic in gen_update_fp_context() needs to be updated to match.
13711 * We do not include the effect of the ECI bits here -- they are
13712 * tracked in other TB flags. This simplifies the logic for
13713 * "when did we emit code that changes the MVE_NO_PRED TB flag
13714 * and thus need to end the TB?".
13716 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
13719 if (env
->v7m
.vpr
) {
13722 if (env
->v7m
.ltpsize
< 4) {
13728 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
13729 target_ulong
*cs_base
, uint32_t *pflags
)
13731 CPUARMTBFlags flags
;
13733 assert_hflags_rebuild_correctly(env
);
13734 flags
= env
->hflags
;
13736 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
13738 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
13739 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
13742 *pc
= env
->regs
[15];
13744 if (arm_feature(env
, ARM_FEATURE_M
)) {
13745 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
13746 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
13747 != env
->v7m
.secure
) {
13748 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
13751 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
13752 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
13753 (env
->v7m
.secure
&&
13754 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
13756 * ASPEN is set, but FPCA/SFPA indicate that there is no
13757 * active FP context; we must create a new FP context before
13758 * executing any FP insn.
13760 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
13763 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
13764 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
13765 DP_TBFLAG_M32(flags
, LSPACT
, 1);
13768 if (mve_no_pred(env
)) {
13769 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
13773 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
13774 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
13776 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
13777 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
13779 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
13780 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
13782 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
13783 DP_TBFLAG_A32(flags
, VFPEN
, 1);
13787 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
13788 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
13792 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13793 * states defined in the ARM ARM for software singlestep:
13794 * SS_ACTIVE PSTATE.SS State
13795 * 0 x Inactive (the TB flag for SS is always 0)
13796 * 1 0 Active-pending
13797 * 1 1 Active-not-pending
13798 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
13800 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
13801 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
13804 *pflags
= flags
.flags
;
13805 *cs_base
= flags
.flags2
;
13808 #ifdef TARGET_AARCH64
13810 * The manual says that when SVE is enabled and VQ is widened the
13811 * implementation is allowed to zero the previously inaccessible
13812 * portion of the registers. The corollary to that is that when
13813 * SVE is enabled and VQ is narrowed we are also allowed to zero
13814 * the now inaccessible portion of the registers.
13816 * The intent of this is that no predicate bit beyond VQ is ever set.
13817 * Which means that some operations on predicate registers themselves
13818 * may operate on full uint64_t or even unrolled across the maximum
13819 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13820 * may well be cheaper than conditionals to restrict the operation
13821 * to the relevant portion of a uint16_t[16].
13823 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
13828 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
13829 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
13831 /* Zap the high bits of the zregs. */
13832 for (i
= 0; i
< 32; i
++) {
13833 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
13836 /* Zap the high bits of the pregs and ffr. */
13839 pmask
= ~(-1ULL << (16 * (vq
& 3)));
13841 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
13842 for (i
= 0; i
< 17; ++i
) {
13843 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
13850 * Notice a change in SVE vector size when changing EL.
13852 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
13853 int new_el
, bool el0_a64
)
13855 ARMCPU
*cpu
= env_archcpu(env
);
13856 int old_len
, new_len
;
13857 bool old_a64
, new_a64
;
13859 /* Nothing to do if no SVE. */
13860 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
13864 /* Nothing to do if FP is disabled in either EL. */
13865 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
13870 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13871 * at ELx, or not available because the EL is in AArch32 state, then
13872 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13873 * has an effective value of 0".
13875 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13876 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13877 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13878 * we already have the correct register contents when encountering the
13879 * vq0->vq0 transition between EL0->EL1.
13881 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
13882 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
13883 ? sve_zcr_len_for_el(env
, old_el
) : 0);
13884 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
13885 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
13886 ? sve_zcr_len_for_el(env
, new_el
) : 0);
13888 /* When changing vector length, clear inaccessible state. */
13889 if (new_len
< old_len
) {
13890 aarch64_sve_narrow_vq(env
, new_len
+ 1);