4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
16 #include "qemu/timer.h"
17 #include "qemu/bitops.h"
18 #include "qemu/crc32c.h"
19 #include "qemu/qemu-print.h"
20 #include "exec/exec-all.h"
21 #include <zlib.h> /* For crc32 */
23 #include "sysemu/cpu-timers.h"
24 #include "sysemu/kvm.h"
25 #include "qapi/qapi-commands-machine-target.h"
26 #include "qapi/error.h"
27 #include "qemu/guest-random.h"
29 #include "semihosting/common-semi.h"
33 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
35 static void switch_mode(CPUARMState
*env
, int mode
);
37 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
39 assert(ri
->fieldoffset
);
40 if (cpreg_field_is_64bit(ri
)) {
41 return CPREG_FIELD64(env
, ri
);
43 return CPREG_FIELD32(env
, ri
);
47 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
49 assert(ri
->fieldoffset
);
50 if (cpreg_field_is_64bit(ri
)) {
51 CPREG_FIELD64(env
, ri
) = value
;
53 CPREG_FIELD32(env
, ri
) = value
;
57 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
59 return (char *)env
+ ri
->fieldoffset
;
62 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
64 /* Raw read of a coprocessor register (as needed for migration, etc). */
65 if (ri
->type
& ARM_CP_CONST
) {
66 return ri
->resetvalue
;
67 } else if (ri
->raw_readfn
) {
68 return ri
->raw_readfn(env
, ri
);
69 } else if (ri
->readfn
) {
70 return ri
->readfn(env
, ri
);
72 return raw_read(env
, ri
);
76 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
80 * Raw write of a coprocessor register (as needed for migration, etc).
81 * Note that constant registers are treated as write-ignored; the
82 * caller should check for success by whether a readback gives the
85 if (ri
->type
& ARM_CP_CONST
) {
87 } else if (ri
->raw_writefn
) {
88 ri
->raw_writefn(env
, ri
, v
);
89 } else if (ri
->writefn
) {
90 ri
->writefn(env
, ri
, v
);
92 raw_write(env
, ri
, v
);
96 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
99 * Return true if the regdef would cause an assertion if you called
100 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
101 * program bug for it not to have the NO_RAW flag).
102 * NB that returning false here doesn't necessarily mean that calling
103 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
104 * read/write access functions which are safe for raw use" from "has
105 * read/write access functions which have side effects but has forgotten
106 * to provide raw access functions".
107 * The tests here line up with the conditions in read/write_raw_cp_reg()
108 * and assertions in raw_read()/raw_write().
110 if ((ri
->type
& ARM_CP_CONST
) ||
112 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
118 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
120 /* Write the coprocessor state from cpu->env to the (index,value) list. */
124 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
125 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
126 const ARMCPRegInfo
*ri
;
129 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
134 if (ri
->type
& ARM_CP_NO_RAW
) {
138 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
141 * Only sync if the previous list->cpustate sync succeeded.
142 * Rather than tracking the success/failure state for every
143 * item in the list, we just recheck "does the raw write we must
144 * have made in write_list_to_cpustate() read back OK" here.
146 uint64_t oldval
= cpu
->cpreg_values
[i
];
148 if (oldval
== newval
) {
152 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
153 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
157 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
159 cpu
->cpreg_values
[i
] = newval
;
164 bool write_list_to_cpustate(ARMCPU
*cpu
)
169 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
170 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
171 uint64_t v
= cpu
->cpreg_values
[i
];
172 const ARMCPRegInfo
*ri
;
174 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
179 if (ri
->type
& ARM_CP_NO_RAW
) {
183 * Write value and confirm it reads back as written
184 * (to catch read-only registers and partially read-only
185 * registers where the incoming migration value doesn't match)
187 write_raw_cp_reg(&cpu
->env
, ri
, v
);
188 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
195 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
197 ARMCPU
*cpu
= opaque
;
198 uint32_t regidx
= (uintptr_t)key
;
199 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
201 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
202 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
203 /* The value array need not be initialized at this point */
204 cpu
->cpreg_array_len
++;
208 static void count_cpreg(gpointer key
, gpointer opaque
)
210 ARMCPU
*cpu
= opaque
;
211 const ARMCPRegInfo
*ri
;
213 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
215 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
216 cpu
->cpreg_array_len
++;
220 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
222 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
223 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
234 void init_cpreg_list(ARMCPU
*cpu
)
237 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
238 * Note that we require cpreg_tuples[] to be sorted by key ID.
243 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
244 keys
= g_list_sort(keys
, cpreg_key_compare
);
246 cpu
->cpreg_array_len
= 0;
248 g_list_foreach(keys
, count_cpreg
, cpu
);
250 arraylen
= cpu
->cpreg_array_len
;
251 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
252 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
256 cpu
->cpreg_array_len
= 0;
258 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
260 assert(cpu
->cpreg_array_len
== arraylen
);
266 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
268 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
269 const ARMCPRegInfo
*ri
,
272 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
273 arm_is_secure_below_el3(env
)) {
274 return CP_ACCESS_TRAP_UNCATEGORIZED
;
280 * Some secure-only AArch32 registers trap to EL3 if used from
281 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
282 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
283 * We assume that the .access field is set to PL1_RW.
285 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
286 const ARMCPRegInfo
*ri
,
289 if (arm_current_el(env
) == 3) {
292 if (arm_is_secure_below_el3(env
)) {
293 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
294 return CP_ACCESS_TRAP_EL2
;
296 return CP_ACCESS_TRAP_EL3
;
298 /* This will be EL1 NS and EL2 NS, which just UNDEF */
299 return CP_ACCESS_TRAP_UNCATEGORIZED
;
303 * Check for traps to performance monitor registers, which are controlled
304 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
306 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
309 int el
= arm_current_el(env
);
310 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
312 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
313 return CP_ACCESS_TRAP_EL2
;
315 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
316 return CP_ACCESS_TRAP_EL3
;
321 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
322 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
325 if (arm_current_el(env
) == 1) {
326 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
327 if (arm_hcr_el2_eff(env
) & trap
) {
328 return CP_ACCESS_TRAP_EL2
;
334 /* Check for traps from EL1 due to HCR_EL2.TSW. */
335 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
338 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
339 return CP_ACCESS_TRAP_EL2
;
344 /* Check for traps from EL1 due to HCR_EL2.TACR. */
345 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
348 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
349 return CP_ACCESS_TRAP_EL2
;
354 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
355 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
358 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
359 return CP_ACCESS_TRAP_EL2
;
364 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
365 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
368 if (arm_current_el(env
) == 1 &&
369 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
370 return CP_ACCESS_TRAP_EL2
;
375 #ifdef TARGET_AARCH64
376 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
377 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
380 if (arm_current_el(env
) == 1 &&
381 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
382 return CP_ACCESS_TRAP_EL2
;
388 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
390 ARMCPU
*cpu
= env_archcpu(env
);
392 raw_write(env
, ri
, value
);
393 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
396 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
398 ARMCPU
*cpu
= env_archcpu(env
);
400 if (raw_read(env
, ri
) != value
) {
402 * Unlike real hardware the qemu TLB uses virtual addresses,
403 * not modified virtual addresses, so this causes a TLB flush.
406 raw_write(env
, ri
, value
);
410 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
413 ARMCPU
*cpu
= env_archcpu(env
);
415 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
416 && !extended_addresses_enabled(env
)) {
418 * For VMSA (when not using the LPAE long descriptor page table
419 * format) this register includes the ASID, so do a TLB flush.
420 * For PMSA it is purely a process ID and no action is needed.
424 raw_write(env
, ri
, value
);
427 static int alle1_tlbmask(CPUARMState
*env
)
430 * Note that the 'ALL' scope must invalidate both stage 1 and
431 * stage 2 translations, whereas most other scopes only invalidate
432 * stage 1 translations.
434 return (ARMMMUIdxBit_E10_1
|
435 ARMMMUIdxBit_E10_1_PAN
|
437 ARMMMUIdxBit_Stage2
|
438 ARMMMUIdxBit_Stage2_S
);
442 /* IS variants of TLB operations must affect all cores */
443 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
446 CPUState
*cs
= env_cpu(env
);
448 tlb_flush_all_cpus_synced(cs
);
451 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
454 CPUState
*cs
= env_cpu(env
);
456 tlb_flush_all_cpus_synced(cs
);
459 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
462 CPUState
*cs
= env_cpu(env
);
464 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
467 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
470 CPUState
*cs
= env_cpu(env
);
472 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
476 * Non-IS variants of TLB operations are upgraded to
477 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
478 * force broadcast of these operations.
480 static bool tlb_force_broadcast(CPUARMState
*env
)
482 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
485 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 /* Invalidate all (TLBIALL) */
489 CPUState
*cs
= env_cpu(env
);
491 if (tlb_force_broadcast(env
)) {
492 tlb_flush_all_cpus_synced(cs
);
498 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
502 CPUState
*cs
= env_cpu(env
);
504 value
&= TARGET_PAGE_MASK
;
505 if (tlb_force_broadcast(env
)) {
506 tlb_flush_page_all_cpus_synced(cs
, value
);
508 tlb_flush_page(cs
, value
);
512 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 /* Invalidate by ASID (TLBIASID) */
516 CPUState
*cs
= env_cpu(env
);
518 if (tlb_force_broadcast(env
)) {
519 tlb_flush_all_cpus_synced(cs
);
525 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
529 CPUState
*cs
= env_cpu(env
);
531 value
&= TARGET_PAGE_MASK
;
532 if (tlb_force_broadcast(env
)) {
533 tlb_flush_page_all_cpus_synced(cs
, value
);
535 tlb_flush_page(cs
, value
);
539 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
542 CPUState
*cs
= env_cpu(env
);
544 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
547 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
550 CPUState
*cs
= env_cpu(env
);
552 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
556 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
559 CPUState
*cs
= env_cpu(env
);
561 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
564 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 CPUState
*cs
= env_cpu(env
);
569 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
572 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
575 CPUState
*cs
= env_cpu(env
);
576 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
578 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
581 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
584 CPUState
*cs
= env_cpu(env
);
585 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
587 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
591 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
594 CPUState
*cs
= env_cpu(env
);
595 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
597 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
600 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
603 CPUState
*cs
= env_cpu(env
);
604 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
606 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
609 static const ARMCPRegInfo cp_reginfo
[] = {
611 * Define the secure and non-secure FCSE identifier CP registers
612 * separately because there is no secure bank in V8 (no _EL3). This allows
613 * the secure register to be properly reset and migrated. There is also no
614 * v8 EL1 version of the register so the non-secure instance stands alone.
617 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
618 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
619 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
620 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
621 { .name
= "FCSEIDR_S",
622 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
623 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
624 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
625 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
627 * Define the secure and non-secure context identifier CP registers
628 * separately because there is no secure bank in V8 (no _EL3). This allows
629 * the secure register to be properly reset and migrated. In the
630 * non-secure case, the 32-bit register will have reset and migration
631 * disabled during registration as it is handled by the 64-bit instance.
633 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
634 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
635 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
636 .fgt
= FGT_CONTEXTIDR_EL1
,
637 .secure
= ARM_CP_SECSTATE_NS
,
638 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
639 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
640 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
641 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
642 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
643 .secure
= ARM_CP_SECSTATE_S
,
644 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
645 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
648 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
650 * NB: Some of these registers exist in v8 but with more precise
651 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
653 /* MMU Domain access control / MPU write buffer control */
655 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
656 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
657 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
658 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
659 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
661 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
662 * For v6 and v5, these mappings are overly broad.
664 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
665 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
666 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
667 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
668 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
669 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
670 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
671 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
672 /* Cache maintenance ops; some of this space may be overridden later. */
673 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
674 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
675 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
678 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
680 * Not all pre-v6 cores implemented this WFI, so this is slightly
683 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
684 .access
= PL1_W
, .type
= ARM_CP_WFI
},
687 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
689 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
690 * is UNPREDICTABLE; we choose to NOP as most implementations do).
692 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
693 .access
= PL1_W
, .type
= ARM_CP_WFI
},
695 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
696 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
697 * OMAPCP will override this space.
699 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
700 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
702 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
703 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
705 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
706 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
707 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
710 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
711 * implementing it as RAZ means the "debug architecture version" bits
712 * will read as a reserved value, which should cause Linux to not try
713 * to use the debug hardware.
715 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
716 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
718 * MMU TLB control. Note that the wildcarding means we cover not just
719 * the unified TLB ops but also the dside/iside/inner-shareable variants.
721 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
722 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
723 .type
= ARM_CP_NO_RAW
},
724 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
725 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
726 .type
= ARM_CP_NO_RAW
},
727 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
728 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
729 .type
= ARM_CP_NO_RAW
},
730 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
731 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
732 .type
= ARM_CP_NO_RAW
},
733 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
734 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
735 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
736 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
739 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
744 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
745 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
747 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
748 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
749 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
751 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
752 /* VFP coprocessor: cp10 & cp11 [23:20] */
753 mask
|= R_CPACR_ASEDIS_MASK
|
754 R_CPACR_D32DIS_MASK
|
758 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
759 /* ASEDIS [31] bit is RAO/WI */
760 value
|= R_CPACR_ASEDIS_MASK
;
764 * VFPv3 and upwards with NEON implement 32 double precision
765 * registers (D0-D31).
767 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
768 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
769 value
|= R_CPACR_D32DIS_MASK
;
776 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
777 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
779 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
780 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
781 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
782 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
785 env
->cp15
.cpacr_el1
= value
;
788 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
791 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
792 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
794 uint64_t value
= env
->cp15
.cpacr_el1
;
796 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
797 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
798 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
804 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
807 * Call cpacr_write() so that we reset with the correct RAO bits set
808 * for our CPU features.
810 cpacr_write(env
, ri
, 0);
813 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
816 if (arm_feature(env
, ARM_FEATURE_V8
)) {
817 /* Check if CPACR accesses are to be trapped to EL2 */
818 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
819 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
820 return CP_ACCESS_TRAP_EL2
;
821 /* Check if CPACR accesses are to be trapped to EL3 */
822 } else if (arm_current_el(env
) < 3 &&
823 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
824 return CP_ACCESS_TRAP_EL3
;
831 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
834 /* Check if CPTR accesses are set to trap to EL3 */
835 if (arm_current_el(env
) == 2 &&
836 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
837 return CP_ACCESS_TRAP_EL3
;
843 static const ARMCPRegInfo v6_cp_reginfo
[] = {
844 /* prefetch by MVA in v6, NOP in v7 */
845 { .name
= "MVA_prefetch",
846 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
847 .access
= PL1_W
, .type
= ARM_CP_NOP
},
849 * We need to break the TB after ISB to execute self-modifying code
850 * correctly and also to take any pending interrupts immediately.
851 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
853 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
854 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
855 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
856 .access
= PL0_W
, .type
= ARM_CP_NOP
},
857 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
858 .access
= PL0_W
, .type
= ARM_CP_NOP
},
859 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
860 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
861 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
862 offsetof(CPUARMState
, cp15
.ifar_ns
) },
865 * Watchpoint Fault Address Register : should actually only be present
866 * for 1136, 1176, 11MPCore.
868 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
869 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
870 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
871 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
872 .fgt
= FGT_CPACR_EL1
,
873 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
874 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
877 typedef struct pm_event
{
878 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
879 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
880 bool (*supported
)(CPUARMState
*);
882 * Retrieve the current count of the underlying event. The programmed
883 * counters hold a difference from the return value from this function
885 uint64_t (*get_count
)(CPUARMState
*);
887 * Return how many nanoseconds it will take (at a minimum) for count events
888 * to occur. A negative value indicates the counter will never overflow, or
889 * that the counter has otherwise arranged for the overflow bit to be set
890 * and the PMU interrupt to be raised on overflow.
892 int64_t (*ns_per_count
)(uint64_t);
895 static bool event_always_supported(CPUARMState
*env
)
900 static uint64_t swinc_get_count(CPUARMState
*env
)
903 * SW_INCR events are written directly to the pmevcntr's by writes to
904 * PMSWINC, so there is no underlying count maintained by the PMU itself
909 static int64_t swinc_ns_per(uint64_t ignored
)
915 * Return the underlying cycle count for the PMU cycle counters. If we're in
916 * usermode, simply return 0.
918 static uint64_t cycles_get_count(CPUARMState
*env
)
920 #ifndef CONFIG_USER_ONLY
921 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
922 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
924 return cpu_get_host_ticks();
928 #ifndef CONFIG_USER_ONLY
929 static int64_t cycles_ns_per(uint64_t cycles
)
931 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
934 static bool instructions_supported(CPUARMState
*env
)
936 return icount_enabled() == 1; /* Precise instruction counting */
939 static uint64_t instructions_get_count(CPUARMState
*env
)
941 return (uint64_t)icount_get_raw();
944 static int64_t instructions_ns_per(uint64_t icount
)
946 return icount_to_ns((int64_t)icount
);
950 static bool pmuv3p1_events_supported(CPUARMState
*env
)
952 /* For events which are supported in any v8.1 PMU */
953 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
956 static bool pmuv3p4_events_supported(CPUARMState
*env
)
958 /* For events which are supported in any v8.1 PMU */
959 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
962 static uint64_t zero_event_get_count(CPUARMState
*env
)
964 /* For events which on QEMU never fire, so their count is always zero */
968 static int64_t zero_event_ns_per(uint64_t cycles
)
970 /* An event which never fires can never overflow */
974 static const pm_event pm_events
[] = {
975 { .number
= 0x000, /* SW_INCR */
976 .supported
= event_always_supported
,
977 .get_count
= swinc_get_count
,
978 .ns_per_count
= swinc_ns_per
,
980 #ifndef CONFIG_USER_ONLY
981 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
982 .supported
= instructions_supported
,
983 .get_count
= instructions_get_count
,
984 .ns_per_count
= instructions_ns_per
,
986 { .number
= 0x011, /* CPU_CYCLES, Cycle */
987 .supported
= event_always_supported
,
988 .get_count
= cycles_get_count
,
989 .ns_per_count
= cycles_ns_per
,
992 { .number
= 0x023, /* STALL_FRONTEND */
993 .supported
= pmuv3p1_events_supported
,
994 .get_count
= zero_event_get_count
,
995 .ns_per_count
= zero_event_ns_per
,
997 { .number
= 0x024, /* STALL_BACKEND */
998 .supported
= pmuv3p1_events_supported
,
999 .get_count
= zero_event_get_count
,
1000 .ns_per_count
= zero_event_ns_per
,
1002 { .number
= 0x03c, /* STALL */
1003 .supported
= pmuv3p4_events_supported
,
1004 .get_count
= zero_event_get_count
,
1005 .ns_per_count
= zero_event_ns_per
,
1010 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1011 * events (i.e. the statistical profiling extension), this implementation
1012 * should first be updated to something sparse instead of the current
1013 * supported_event_map[] array.
1015 #define MAX_EVENT_ID 0x3c
1016 #define UNSUPPORTED_EVENT UINT16_MAX
1017 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1020 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1021 * of ARM event numbers to indices in our pm_events array.
1023 * Note: Events in the 0x40XX range are not currently supported.
1025 void pmu_init(ARMCPU
*cpu
)
1030 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1033 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1034 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1039 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1040 const pm_event
*cnt
= &pm_events
[i
];
1041 assert(cnt
->number
<= MAX_EVENT_ID
);
1042 /* We do not currently support events in the 0x40xx range */
1043 assert(cnt
->number
<= 0x3f);
1045 if (cnt
->supported(&cpu
->env
)) {
1046 supported_event_map
[cnt
->number
] = i
;
1047 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1048 if (cnt
->number
& 0x20) {
1049 cpu
->pmceid1
|= event_mask
;
1051 cpu
->pmceid0
|= event_mask
;
1058 * Check at runtime whether a PMU event is supported for the current machine
1060 static bool event_supported(uint16_t number
)
1062 if (number
> MAX_EVENT_ID
) {
1065 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1068 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1072 * Performance monitor registers user accessibility is controlled
1073 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1074 * trapping to EL2 or EL3 for other accesses.
1076 int el
= arm_current_el(env
);
1077 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1079 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1080 return CP_ACCESS_TRAP
;
1082 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1083 return CP_ACCESS_TRAP_EL2
;
1085 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1086 return CP_ACCESS_TRAP_EL3
;
1089 return CP_ACCESS_OK
;
1092 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1093 const ARMCPRegInfo
*ri
,
1096 /* ER: event counter read trap control */
1097 if (arm_feature(env
, ARM_FEATURE_V8
)
1098 && arm_current_el(env
) == 0
1099 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1101 return CP_ACCESS_OK
;
1104 return pmreg_access(env
, ri
, isread
);
1107 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1108 const ARMCPRegInfo
*ri
,
1111 /* SW: software increment write trap control */
1112 if (arm_feature(env
, ARM_FEATURE_V8
)
1113 && arm_current_el(env
) == 0
1114 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1116 return CP_ACCESS_OK
;
1119 return pmreg_access(env
, ri
, isread
);
1122 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1123 const ARMCPRegInfo
*ri
,
1126 /* ER: event counter read trap control */
1127 if (arm_feature(env
, ARM_FEATURE_V8
)
1128 && arm_current_el(env
) == 0
1129 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1130 return CP_ACCESS_OK
;
1133 return pmreg_access(env
, ri
, isread
);
1136 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1137 const ARMCPRegInfo
*ri
,
1140 /* CR: cycle counter read trap control */
1141 if (arm_feature(env
, ARM_FEATURE_V8
)
1142 && arm_current_el(env
) == 0
1143 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1145 return CP_ACCESS_OK
;
1148 return pmreg_access(env
, ri
, isread
);
1152 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1153 * We use these to decide whether we need to wrap a write to MDCR_EL2
1154 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1156 #define MDCR_EL2_PMU_ENABLE_BITS \
1157 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1158 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1161 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1162 * the current EL, security state, and register configuration.
1164 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1167 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1168 bool enabled
, prohibited
= false, filtered
;
1169 bool secure
= arm_is_secure(env
);
1170 int el
= arm_current_el(env
);
1171 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1172 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1174 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1178 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1179 (counter
< hpmn
|| counter
== 31)) {
1180 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1182 e
= mdcr_el2
& MDCR_HPME
;
1184 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1186 /* Is event counting prohibited? */
1187 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1188 prohibited
= mdcr_el2
& MDCR_HPMD
;
1191 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1194 if (counter
== 31) {
1196 * The cycle counter defaults to running. PMCR.DP says "disable
1197 * the cycle counter when event counting is prohibited".
1198 * Some MDCR bits disable the cycle counter specifically.
1200 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1201 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1203 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1206 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1211 if (counter
== 31) {
1212 filter
= env
->cp15
.pmccfiltr_el0
;
1214 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1217 p
= filter
& PMXEVTYPER_P
;
1218 u
= filter
& PMXEVTYPER_U
;
1219 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1220 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1221 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1222 m
= arm_el_is_aa64(env
, 1) &&
1223 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1226 filtered
= secure
? u
: u
!= nsu
;
1227 } else if (el
== 1) {
1228 filtered
= secure
? p
: p
!= nsk
;
1229 } else if (el
== 2) {
1235 if (counter
!= 31) {
1237 * If not checking PMCCNTR, ensure the counter is setup to an event we
1240 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1241 if (!event_supported(event
)) {
1246 return enabled
&& !prohibited
&& !filtered
;
1249 static void pmu_update_irq(CPUARMState
*env
)
1251 ARMCPU
*cpu
= env_archcpu(env
);
1252 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1253 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1256 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1259 * Return true if the clock divider is enabled and the cycle counter
1260 * is supposed to tick only once every 64 clock cycles. This is
1261 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1262 * (64-bit) cycle counter PMCR.D has no effect.
1264 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1267 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1269 /* Return true if the specified event counter is configured to be 64 bit */
1271 /* This isn't intended to be used with the cycle counter */
1272 assert(counter
< 31);
1274 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1278 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1280 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1281 * current security state, so we don't use arm_mdcr_el2_eff() here.
1283 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1284 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1286 if (hpmn
!= 0 && counter
>= hpmn
) {
1290 return env
->cp15
.c9_pmcr
& PMCRLP
;
1294 * Ensure c15_ccnt is the guest-visible count so that operations such as
1295 * enabling/disabling the counter or filtering, modifying the count itself,
1296 * etc. can be done logically. This is essentially a no-op if the counter is
1297 * not enabled at the time of the call.
1299 static void pmccntr_op_start(CPUARMState
*env
)
1301 uint64_t cycles
= cycles_get_count(env
);
1303 if (pmu_counter_enabled(env
, 31)) {
1304 uint64_t eff_cycles
= cycles
;
1305 if (pmccntr_clockdiv_enabled(env
)) {
1309 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1311 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1312 1ull << 63 : 1ull << 31;
1313 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1314 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1315 pmu_update_irq(env
);
1318 env
->cp15
.c15_ccnt
= new_pmccntr
;
1320 env
->cp15
.c15_ccnt_delta
= cycles
;
1324 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1325 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1328 static void pmccntr_op_finish(CPUARMState
*env
)
1330 if (pmu_counter_enabled(env
, 31)) {
1331 #ifndef CONFIG_USER_ONLY
1332 /* Calculate when the counter will next overflow */
1333 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1334 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1335 remaining_cycles
= (uint32_t)remaining_cycles
;
1337 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1339 if (overflow_in
> 0) {
1340 int64_t overflow_at
;
1342 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1343 overflow_in
, &overflow_at
)) {
1344 ARMCPU
*cpu
= env_archcpu(env
);
1345 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1350 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1351 if (pmccntr_clockdiv_enabled(env
)) {
1354 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1358 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1361 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1363 if (event_supported(event
)) {
1364 uint16_t event_idx
= supported_event_map
[event
];
1365 count
= pm_events
[event_idx
].get_count(env
);
1368 if (pmu_counter_enabled(env
, counter
)) {
1369 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1370 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1371 1ULL << 63 : 1ULL << 31;
1373 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1374 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1375 pmu_update_irq(env
);
1377 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1379 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1382 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1384 if (pmu_counter_enabled(env
, counter
)) {
1385 #ifndef CONFIG_USER_ONLY
1386 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1387 uint16_t event_idx
= supported_event_map
[event
];
1388 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1389 int64_t overflow_in
;
1391 if (!pmevcntr_is_64_bit(env
, counter
)) {
1392 delta
= (uint32_t)delta
;
1394 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1396 if (overflow_in
> 0) {
1397 int64_t overflow_at
;
1399 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1400 overflow_in
, &overflow_at
)) {
1401 ARMCPU
*cpu
= env_archcpu(env
);
1402 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1407 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1408 env
->cp15
.c14_pmevcntr
[counter
];
1412 void pmu_op_start(CPUARMState
*env
)
1415 pmccntr_op_start(env
);
1416 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1417 pmevcntr_op_start(env
, i
);
1421 void pmu_op_finish(CPUARMState
*env
)
1424 pmccntr_op_finish(env
);
1425 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1426 pmevcntr_op_finish(env
, i
);
1430 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1432 pmu_op_start(&cpu
->env
);
1435 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1437 pmu_op_finish(&cpu
->env
);
1440 void arm_pmu_timer_cb(void *opaque
)
1442 ARMCPU
*cpu
= opaque
;
1445 * Update all the counter values based on the current underlying counts,
1446 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1447 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1448 * counter may expire.
1450 pmu_op_start(&cpu
->env
);
1451 pmu_op_finish(&cpu
->env
);
1454 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1459 if (value
& PMCRC
) {
1460 /* The counter has been reset */
1461 env
->cp15
.c15_ccnt
= 0;
1464 if (value
& PMCRP
) {
1466 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1467 env
->cp15
.c14_pmevcntr
[i
] = 0;
1471 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1472 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1477 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1481 uint64_t overflow_mask
, new_pmswinc
;
1483 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1484 /* Increment a counter's count iff: */
1485 if ((value
& (1 << i
)) && /* counter's bit is set */
1486 /* counter is enabled and not filtered */
1487 pmu_counter_enabled(env
, i
) &&
1488 /* counter is SW_INCR */
1489 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1490 pmevcntr_op_start(env
, i
);
1493 * Detect if this write causes an overflow since we can't predict
1494 * PMSWINC overflows like we can for other events
1496 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1498 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1499 1ULL << 63 : 1ULL << 31;
1501 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1502 env
->cp15
.c9_pmovsr
|= (1 << i
);
1503 pmu_update_irq(env
);
1506 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1508 pmevcntr_op_finish(env
, i
);
1513 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1516 pmccntr_op_start(env
);
1517 ret
= env
->cp15
.c15_ccnt
;
1518 pmccntr_op_finish(env
);
1522 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1526 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1527 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1528 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1531 env
->cp15
.c9_pmselr
= value
& 0x1f;
1534 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1537 pmccntr_op_start(env
);
1538 env
->cp15
.c15_ccnt
= value
;
1539 pmccntr_op_finish(env
);
1542 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1545 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1547 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1550 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1553 pmccntr_op_start(env
);
1554 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1555 pmccntr_op_finish(env
);
1558 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1561 pmccntr_op_start(env
);
1562 /* M is not accessible from AArch32 */
1563 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1564 (value
& PMCCFILTR
);
1565 pmccntr_op_finish(env
);
1568 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1570 /* M is not visible in AArch32 */
1571 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1574 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1578 value
&= pmu_counter_mask(env
);
1579 env
->cp15
.c9_pmcnten
|= value
;
1583 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1587 value
&= pmu_counter_mask(env
);
1588 env
->cp15
.c9_pmcnten
&= ~value
;
1592 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1595 value
&= pmu_counter_mask(env
);
1596 env
->cp15
.c9_pmovsr
&= ~value
;
1597 pmu_update_irq(env
);
1600 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1603 value
&= pmu_counter_mask(env
);
1604 env
->cp15
.c9_pmovsr
|= value
;
1605 pmu_update_irq(env
);
1608 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1609 uint64_t value
, const uint8_t counter
)
1611 if (counter
== 31) {
1612 pmccfiltr_write(env
, ri
, value
);
1613 } else if (counter
< pmu_num_counters(env
)) {
1614 pmevcntr_op_start(env
, counter
);
1617 * If this counter's event type is changing, store the current
1618 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1619 * pmevcntr_op_finish has the correct baseline when it converts back to
1622 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1623 PMXEVTYPER_EVTCOUNT
;
1624 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1625 if (old_event
!= new_event
) {
1627 if (event_supported(new_event
)) {
1628 uint16_t event_idx
= supported_event_map
[new_event
];
1629 count
= pm_events
[event_idx
].get_count(env
);
1631 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1634 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1635 pmevcntr_op_finish(env
, counter
);
1638 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1639 * PMSELR value is equal to or greater than the number of implemented
1640 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1644 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1645 const uint8_t counter
)
1647 if (counter
== 31) {
1648 return env
->cp15
.pmccfiltr_el0
;
1649 } else if (counter
< pmu_num_counters(env
)) {
1650 return env
->cp15
.c14_pmevtyper
[counter
];
1653 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1654 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1660 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1663 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1664 pmevtyper_write(env
, ri
, value
, counter
);
1667 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1670 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1671 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1674 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1675 * pmu_op_finish calls when loading saved state for a migration. Because
1676 * we're potentially updating the type of event here, the value written to
1677 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1678 * different counter type. Therefore, we need to set this value to the
1679 * current count for the counter type we're writing so that pmu_op_finish
1680 * has the correct count for its calculation.
1682 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1683 if (event_supported(event
)) {
1684 uint16_t event_idx
= supported_event_map
[event
];
1685 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1686 pm_events
[event_idx
].get_count(env
);
1690 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1692 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1693 return pmevtyper_read(env
, ri
, counter
);
1696 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1699 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1702 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1704 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1707 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1708 uint64_t value
, uint8_t counter
)
1710 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1711 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1712 value
&= MAKE_64BIT_MASK(0, 32);
1714 if (counter
< pmu_num_counters(env
)) {
1715 pmevcntr_op_start(env
, counter
);
1716 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1717 pmevcntr_op_finish(env
, counter
);
1720 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1721 * are CONSTRAINED UNPREDICTABLE.
1725 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 if (counter
< pmu_num_counters(env
)) {
1730 pmevcntr_op_start(env
, counter
);
1731 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1732 pmevcntr_op_finish(env
, counter
);
1733 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1734 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1735 ret
&= MAKE_64BIT_MASK(0, 32);
1740 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1741 * are CONSTRAINED UNPREDICTABLE.
1747 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1750 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1751 pmevcntr_write(env
, ri
, value
, counter
);
1754 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1756 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1757 return pmevcntr_read(env
, ri
, counter
);
1760 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1763 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1764 assert(counter
< pmu_num_counters(env
));
1765 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1766 pmevcntr_write(env
, ri
, value
, counter
);
1769 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1771 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1772 assert(counter
< pmu_num_counters(env
));
1773 return env
->cp15
.c14_pmevcntr
[counter
];
1776 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1779 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1782 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1784 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1787 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1790 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1791 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1793 env
->cp15
.c9_pmuserenr
= value
& 1;
1797 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1800 /* We have no event counters so only the C bit can be changed */
1801 value
&= pmu_counter_mask(env
);
1802 env
->cp15
.c9_pminten
|= value
;
1803 pmu_update_irq(env
);
1806 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1809 value
&= pmu_counter_mask(env
);
1810 env
->cp15
.c9_pminten
&= ~value
;
1811 pmu_update_irq(env
);
1814 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1818 * Note that even though the AArch64 view of this register has bits
1819 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1820 * architectural requirements for bits which are RES0 only in some
1821 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1822 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1824 raw_write(env
, ri
, value
& ~0x1FULL
);
1827 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1829 /* Begin with base v8.0 state. */
1830 uint64_t valid_mask
= 0x3fff;
1831 ARMCPU
*cpu
= env_archcpu(env
);
1835 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1836 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1837 * Instead, choose the format based on the mode of EL3.
1839 if (arm_el_is_aa64(env
, 3)) {
1840 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1841 valid_mask
&= ~SCR_NET
; /* RES0 */
1843 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1844 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1845 value
|= SCR_RW
; /* RAO/WI */
1847 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1848 valid_mask
|= SCR_TERR
;
1850 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1851 valid_mask
|= SCR_TLOR
;
1853 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1854 valid_mask
|= SCR_API
| SCR_APK
;
1856 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1857 valid_mask
|= SCR_EEL2
;
1859 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1860 valid_mask
|= SCR_ATA
;
1862 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1863 valid_mask
|= SCR_ENSCXT
;
1865 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1866 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1868 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1869 valid_mask
|= SCR_ENTP2
;
1871 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1872 valid_mask
|= SCR_HXEN
;
1874 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1875 valid_mask
|= SCR_FGTEN
;
1878 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1879 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1880 valid_mask
|= SCR_TERR
;
1884 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1885 valid_mask
&= ~SCR_HCE
;
1888 * On ARMv7, SMD (or SCD as it is called in v7) is only
1889 * supported if EL2 exists. The bit is UNK/SBZP when
1890 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1891 * when EL2 is unavailable.
1892 * On ARMv8, this bit is always available.
1894 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1895 !arm_feature(env
, ARM_FEATURE_V8
)) {
1896 valid_mask
&= ~SCR_SMD
;
1900 /* Clear all-context RES0 bits. */
1901 value
&= valid_mask
;
1902 changed
= env
->cp15
.scr_el3
^ value
;
1903 env
->cp15
.scr_el3
= value
;
1906 * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
1907 * we must invalidate all TLBs below EL3.
1909 if (changed
& SCR_NS
) {
1910 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1911 ARMMMUIdxBit_E20_0
|
1912 ARMMMUIdxBit_E10_1
|
1913 ARMMMUIdxBit_E20_2
|
1914 ARMMMUIdxBit_E10_1_PAN
|
1915 ARMMMUIdxBit_E20_2_PAN
|
1920 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1923 * scr_write will set the RES1 bits on an AArch64-only CPU.
1924 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1926 scr_write(env
, ri
, 0);
1929 static CPAccessResult
access_tid4(CPUARMState
*env
,
1930 const ARMCPRegInfo
*ri
,
1933 if (arm_current_el(env
) == 1 &&
1934 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1935 return CP_ACCESS_TRAP_EL2
;
1938 return CP_ACCESS_OK
;
1941 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1943 ARMCPU
*cpu
= env_archcpu(env
);
1946 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1949 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1950 ri
->secure
& ARM_CP_SECSTATE_S
);
1952 return cpu
->ccsidr
[index
];
1955 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1958 raw_write(env
, ri
, value
& 0xf);
1961 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1963 CPUState
*cs
= env_cpu(env
);
1964 bool el1
= arm_current_el(env
) == 1;
1965 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1968 if (hcr_el2
& HCR_IMO
) {
1969 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1973 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1978 if (hcr_el2
& HCR_FMO
) {
1979 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1983 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1988 if (hcr_el2
& HCR_AMO
) {
1989 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1997 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2000 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2001 return CP_ACCESS_TRAP_EL2
;
2004 return CP_ACCESS_OK
;
2007 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2010 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2011 return access_aa64_tid1(env
, ri
, isread
);
2014 return CP_ACCESS_OK
;
2017 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2018 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2019 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2020 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2022 * Performance monitors are implementation defined in v7,
2023 * but with an ARM recommended set of registers, which we
2026 * Performance registers fall into three categories:
2027 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2028 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2029 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2030 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2031 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2033 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2034 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2035 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2036 .writefn
= pmcntenset_write
,
2037 .accessfn
= pmreg_access
,
2039 .raw_writefn
= raw_write
},
2040 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2041 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2042 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2045 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2046 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2048 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2049 .accessfn
= pmreg_access
,
2051 .writefn
= pmcntenclr_write
,
2052 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2053 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2054 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2055 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2057 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2058 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2059 .writefn
= pmcntenclr_write
},
2060 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2061 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2062 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2063 .accessfn
= pmreg_access
,
2065 .writefn
= pmovsr_write
,
2066 .raw_writefn
= raw_write
},
2067 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2068 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2069 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2071 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2072 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2073 .writefn
= pmovsr_write
,
2074 .raw_writefn
= raw_write
},
2075 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2076 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2077 .fgt
= FGT_PMSWINC_EL0
,
2078 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2079 .writefn
= pmswinc_write
},
2080 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2081 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2082 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2083 .fgt
= FGT_PMSWINC_EL0
,
2084 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2085 .writefn
= pmswinc_write
},
2086 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2087 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2088 .fgt
= FGT_PMSELR_EL0
,
2089 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2090 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2091 .raw_writefn
= raw_write
},
2092 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2093 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2094 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2095 .fgt
= FGT_PMSELR_EL0
,
2096 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2097 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2098 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2099 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2100 .fgt
= FGT_PMCCNTR_EL0
,
2101 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2102 .accessfn
= pmreg_access_ccntr
},
2103 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2104 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2105 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2106 .fgt
= FGT_PMCCNTR_EL0
,
2108 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2109 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2110 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2111 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2112 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2113 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2114 .fgt
= FGT_PMCCFILTR_EL0
,
2115 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2117 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2118 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2119 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2120 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2121 .fgt
= FGT_PMCCFILTR_EL0
,
2123 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2125 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2126 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2127 .accessfn
= pmreg_access
,
2128 .fgt
= FGT_PMEVTYPERN_EL0
,
2129 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2130 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2131 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2132 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2133 .accessfn
= pmreg_access
,
2134 .fgt
= FGT_PMEVTYPERN_EL0
,
2135 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2136 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2137 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2138 .accessfn
= pmreg_access_xevcntr
,
2139 .fgt
= FGT_PMEVCNTRN_EL0
,
2140 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2141 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2142 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2143 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2144 .accessfn
= pmreg_access_xevcntr
,
2145 .fgt
= FGT_PMEVCNTRN_EL0
,
2146 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2147 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2148 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2149 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2151 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2152 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2153 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2154 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2155 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2157 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2158 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2159 .access
= PL1_RW
, .accessfn
= access_tpm
,
2161 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2162 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2164 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2165 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2166 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2167 .access
= PL1_RW
, .accessfn
= access_tpm
,
2170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2171 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2172 .resetvalue
= 0x0 },
2173 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2174 .access
= PL1_RW
, .accessfn
= access_tpm
,
2176 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2177 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2178 .writefn
= pmintenclr_write
, },
2179 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2180 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2181 .access
= PL1_RW
, .accessfn
= access_tpm
,
2183 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2184 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2185 .writefn
= pmintenclr_write
},
2186 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2187 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2189 .accessfn
= access_tid4
,
2190 .fgt
= FGT_CCSIDR_EL1
,
2191 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2192 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2193 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2195 .accessfn
= access_tid4
,
2196 .fgt
= FGT_CSSELR_EL1
,
2197 .writefn
= csselr_write
, .resetvalue
= 0,
2198 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2199 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2201 * Auxiliary ID register: this actually has an IMPDEF value but for now
2202 * just RAZ for all cores:
2204 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2205 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2206 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2207 .accessfn
= access_aa64_tid1
,
2208 .fgt
= FGT_AIDR_EL1
,
2211 * Auxiliary fault status registers: these also are IMPDEF, and we
2212 * choose to RAZ/WI for all cores.
2214 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2215 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2216 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2217 .fgt
= FGT_AFSR0_EL1
,
2218 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2219 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2220 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2221 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2222 .fgt
= FGT_AFSR1_EL1
,
2223 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2225 * MAIR can just read-as-written because we don't implement caches
2226 * and so don't need to care about memory attributes.
2228 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2229 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2230 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2231 .fgt
= FGT_MAIR_EL1
,
2232 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2234 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2235 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2236 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2239 * For non-long-descriptor page tables these are PRRR and NMRR;
2240 * regardless they still act as reads-as-written for QEMU.
2243 * MAIR0/1 are defined separately from their 64-bit counterpart which
2244 * allows them to assign the correct fieldoffset based on the endianness
2245 * handled in the field definitions.
2247 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2248 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2249 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2250 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2251 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2252 .resetfn
= arm_cp_reset_ignore
},
2253 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2254 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2255 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2256 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2257 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2258 .resetfn
= arm_cp_reset_ignore
},
2259 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2260 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2262 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2263 /* 32 bit ITLB invalidates */
2264 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2265 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2266 .writefn
= tlbiall_write
},
2267 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2268 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2269 .writefn
= tlbimva_write
},
2270 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2271 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2272 .writefn
= tlbiasid_write
},
2273 /* 32 bit DTLB invalidates */
2274 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2275 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2276 .writefn
= tlbiall_write
},
2277 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2278 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2279 .writefn
= tlbimva_write
},
2280 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2281 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2282 .writefn
= tlbiasid_write
},
2283 /* 32 bit TLB invalidates */
2284 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2285 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2286 .writefn
= tlbiall_write
},
2287 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2288 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2289 .writefn
= tlbimva_write
},
2290 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2291 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2292 .writefn
= tlbiasid_write
},
2293 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2294 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2295 .writefn
= tlbimvaa_write
},
2298 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2299 /* 32 bit TLB invalidates, Inner Shareable */
2300 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2301 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2302 .writefn
= tlbiall_is_write
},
2303 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2304 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2305 .writefn
= tlbimva_is_write
},
2306 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2307 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2308 .writefn
= tlbiasid_is_write
},
2309 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2310 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2311 .writefn
= tlbimvaa_is_write
},
2314 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2315 /* PMOVSSET is not implemented in v7 before v7ve */
2316 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2317 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2319 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2320 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2321 .writefn
= pmovsset_write
,
2322 .raw_writefn
= raw_write
},
2323 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2324 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2325 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2327 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2328 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2329 .writefn
= pmovsset_write
,
2330 .raw_writefn
= raw_write
},
2333 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2340 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2344 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2345 * at all, so we don't need to check whether we're v8A.
2347 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2348 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2349 return CP_ACCESS_TRAP_EL2
;
2351 return CP_ACCESS_OK
;
2354 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2357 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2358 return CP_ACCESS_TRAP
;
2360 return teecr_access(env
, ri
, isread
);
2363 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2364 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2365 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2367 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2368 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2369 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2370 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2373 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2374 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2375 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2377 .fgt
= FGT_TPIDR_EL0
,
2378 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2379 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2381 .fgt
= FGT_TPIDR_EL0
,
2382 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2383 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2384 .resetfn
= arm_cp_reset_ignore
},
2385 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2386 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2387 .access
= PL0_R
| PL1_W
,
2388 .fgt
= FGT_TPIDRRO_EL0
,
2389 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2391 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2392 .access
= PL0_R
| PL1_W
,
2393 .fgt
= FGT_TPIDRRO_EL0
,
2394 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2395 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2396 .resetfn
= arm_cp_reset_ignore
},
2397 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2398 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2400 .fgt
= FGT_TPIDR_EL1
,
2401 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2402 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2404 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2405 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2409 #ifndef CONFIG_USER_ONLY
2411 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2415 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2416 * Writable only at the highest implemented exception level.
2418 int el
= arm_current_el(env
);
2424 hcr
= arm_hcr_el2_eff(env
);
2425 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2426 cntkctl
= env
->cp15
.cnthctl_el2
;
2428 cntkctl
= env
->cp15
.c14_cntkctl
;
2430 if (!extract32(cntkctl
, 0, 2)) {
2431 return CP_ACCESS_TRAP
;
2435 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2436 arm_is_secure_below_el3(env
)) {
2437 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2438 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2446 if (!isread
&& el
< arm_highest_el(env
)) {
2447 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2450 return CP_ACCESS_OK
;
2453 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2456 unsigned int cur_el
= arm_current_el(env
);
2457 bool has_el2
= arm_is_el2_enabled(env
);
2458 uint64_t hcr
= arm_hcr_el2_eff(env
);
2462 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2463 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2464 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2465 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2468 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2469 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2470 return CP_ACCESS_TRAP
;
2473 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2474 if (hcr
& HCR_E2H
) {
2475 if (timeridx
== GTIMER_PHYS
&&
2476 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2477 return CP_ACCESS_TRAP_EL2
;
2480 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2481 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2482 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2483 return CP_ACCESS_TRAP_EL2
;
2489 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2490 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2492 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2493 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2494 return CP_ACCESS_TRAP_EL2
;
2498 return CP_ACCESS_OK
;
2501 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2504 unsigned int cur_el
= arm_current_el(env
);
2505 bool has_el2
= arm_is_el2_enabled(env
);
2506 uint64_t hcr
= arm_hcr_el2_eff(env
);
2510 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2511 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2512 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2513 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2517 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2518 * EL0 if EL0[PV]TEN is zero.
2520 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2521 return CP_ACCESS_TRAP
;
2526 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2527 if (hcr
& HCR_E2H
) {
2528 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2529 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2530 return CP_ACCESS_TRAP_EL2
;
2533 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2534 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2535 return CP_ACCESS_TRAP_EL2
;
2541 return CP_ACCESS_OK
;
2544 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2545 const ARMCPRegInfo
*ri
,
2548 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2551 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2552 const ARMCPRegInfo
*ri
,
2555 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2558 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2561 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2564 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2567 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2570 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2571 const ARMCPRegInfo
*ri
,
2575 * The AArch64 register view of the secure physical timer is
2576 * always accessible from EL3, and configurably accessible from
2579 switch (arm_current_el(env
)) {
2581 if (!arm_is_secure(env
)) {
2582 return CP_ACCESS_TRAP
;
2584 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2585 return CP_ACCESS_TRAP_EL3
;
2587 return CP_ACCESS_OK
;
2590 return CP_ACCESS_TRAP
;
2592 return CP_ACCESS_OK
;
2594 g_assert_not_reached();
2598 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2600 ARMCPU
*cpu
= env_archcpu(env
);
2602 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2605 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2607 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2611 * Timer enabled: calculate and set current ISTATUS, irq, and
2612 * reset timer to when ISTATUS next has to change
2614 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2615 cpu
->env
.cp15
.cntvoff_el2
: 0;
2616 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2617 /* Note that this must be unsigned 64 bit arithmetic: */
2618 int istatus
= count
- offset
>= gt
->cval
;
2622 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2624 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2625 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2628 /* Next transition is when count rolls back over to zero */
2629 nexttick
= UINT64_MAX
;
2631 /* Next transition is when we hit cval */
2632 nexttick
= gt
->cval
+ offset
;
2635 * Note that the desired next expiry time might be beyond the
2636 * signed-64-bit range of a QEMUTimer -- in this case we just
2637 * set the timer for as far in the future as possible. When the
2638 * timer expires we will reset the timer for any remaining period.
2640 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2641 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2643 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2645 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2647 /* Timer disabled: ISTATUS and timer output always clear */
2649 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2650 timer_del(cpu
->gt_timer
[timeridx
]);
2651 trace_arm_gt_recalc_disabled(timeridx
);
2655 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2658 ARMCPU
*cpu
= env_archcpu(env
);
2660 timer_del(cpu
->gt_timer
[timeridx
]);
2663 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2665 return gt_get_countervalue(env
);
2668 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2672 switch (arm_current_el(env
)) {
2674 hcr
= arm_hcr_el2_eff(env
);
2675 if (hcr
& HCR_E2H
) {
2680 hcr
= arm_hcr_el2_eff(env
);
2681 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2687 return env
->cp15
.cntvoff_el2
;
2690 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2692 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2695 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2699 trace_arm_gt_cval_write(timeridx
, value
);
2700 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2701 gt_recalc_timer(env_archcpu(env
), timeridx
);
2704 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2707 uint64_t offset
= 0;
2711 case GTIMER_HYPVIRT
:
2712 offset
= gt_virt_cnt_offset(env
);
2716 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2717 (gt_get_countervalue(env
) - offset
));
2720 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2724 uint64_t offset
= 0;
2728 case GTIMER_HYPVIRT
:
2729 offset
= gt_virt_cnt_offset(env
);
2733 trace_arm_gt_tval_write(timeridx
, value
);
2734 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2735 sextract64(value
, 0, 32);
2736 gt_recalc_timer(env_archcpu(env
), timeridx
);
2739 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2743 ARMCPU
*cpu
= env_archcpu(env
);
2744 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2746 trace_arm_gt_ctl_write(timeridx
, value
);
2747 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2748 if ((oldval
^ value
) & 1) {
2749 /* Enable toggled */
2750 gt_recalc_timer(cpu
, timeridx
);
2751 } else if ((oldval
^ value
) & 2) {
2753 * IMASK toggled: don't need to recalculate,
2754 * just set the interrupt line based on ISTATUS
2756 int irqstate
= (oldval
& 4) && !(value
& 2);
2758 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2759 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2763 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2765 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2768 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2771 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2774 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2776 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2779 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2782 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2785 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2788 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2791 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2793 switch (arm_mmu_idx(env
)) {
2794 case ARMMMUIdx_E20_0
:
2795 case ARMMMUIdx_E20_2
:
2796 case ARMMMUIdx_E20_2_PAN
:
2803 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2805 switch (arm_mmu_idx(env
)) {
2806 case ARMMMUIdx_E20_0
:
2807 case ARMMMUIdx_E20_2
:
2808 case ARMMMUIdx_E20_2_PAN
:
2809 return GTIMER_HYPVIRT
;
2815 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2816 const ARMCPRegInfo
*ri
)
2818 int timeridx
= gt_phys_redir_timeridx(env
);
2819 return env
->cp15
.c14_timer
[timeridx
].cval
;
2822 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2825 int timeridx
= gt_phys_redir_timeridx(env
);
2826 gt_cval_write(env
, ri
, timeridx
, value
);
2829 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2830 const ARMCPRegInfo
*ri
)
2832 int timeridx
= gt_phys_redir_timeridx(env
);
2833 return gt_tval_read(env
, ri
, timeridx
);
2836 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2839 int timeridx
= gt_phys_redir_timeridx(env
);
2840 gt_tval_write(env
, ri
, timeridx
, value
);
2843 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2844 const ARMCPRegInfo
*ri
)
2846 int timeridx
= gt_phys_redir_timeridx(env
);
2847 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2850 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2853 int timeridx
= gt_phys_redir_timeridx(env
);
2854 gt_ctl_write(env
, ri
, timeridx
, value
);
2857 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2859 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2862 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2865 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2868 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2870 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2873 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2876 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2879 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2882 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2885 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2888 ARMCPU
*cpu
= env_archcpu(env
);
2890 trace_arm_gt_cntvoff_write(value
);
2891 raw_write(env
, ri
, value
);
2892 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2895 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2896 const ARMCPRegInfo
*ri
)
2898 int timeridx
= gt_virt_redir_timeridx(env
);
2899 return env
->cp15
.c14_timer
[timeridx
].cval
;
2902 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2905 int timeridx
= gt_virt_redir_timeridx(env
);
2906 gt_cval_write(env
, ri
, timeridx
, value
);
2909 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2910 const ARMCPRegInfo
*ri
)
2912 int timeridx
= gt_virt_redir_timeridx(env
);
2913 return gt_tval_read(env
, ri
, timeridx
);
2916 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2919 int timeridx
= gt_virt_redir_timeridx(env
);
2920 gt_tval_write(env
, ri
, timeridx
, value
);
2923 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2924 const ARMCPRegInfo
*ri
)
2926 int timeridx
= gt_virt_redir_timeridx(env
);
2927 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2930 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2933 int timeridx
= gt_virt_redir_timeridx(env
);
2934 gt_ctl_write(env
, ri
, timeridx
, value
);
2937 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2939 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2942 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2945 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2948 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2950 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2953 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2956 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2959 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2962 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2965 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2967 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2970 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2973 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2976 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2978 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2981 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2984 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2987 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2990 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2993 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2995 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2998 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3001 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3004 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3006 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3009 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3012 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3015 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3018 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3021 void arm_gt_ptimer_cb(void *opaque
)
3023 ARMCPU
*cpu
= opaque
;
3025 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3028 void arm_gt_vtimer_cb(void *opaque
)
3030 ARMCPU
*cpu
= opaque
;
3032 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3035 void arm_gt_htimer_cb(void *opaque
)
3037 ARMCPU
*cpu
= opaque
;
3039 gt_recalc_timer(cpu
, GTIMER_HYP
);
3042 void arm_gt_stimer_cb(void *opaque
)
3044 ARMCPU
*cpu
= opaque
;
3046 gt_recalc_timer(cpu
, GTIMER_SEC
);
3049 void arm_gt_hvtimer_cb(void *opaque
)
3051 ARMCPU
*cpu
= opaque
;
3053 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3056 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3058 ARMCPU
*cpu
= env_archcpu(env
);
3060 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3063 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3065 * Note that CNTFRQ is purely reads-as-written for the benefit
3066 * of software; writing it doesn't actually change the timer frequency.
3067 * Our reset value matches the fixed frequency we implement the timer at.
3069 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3070 .type
= ARM_CP_ALIAS
,
3071 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3072 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3074 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3075 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3076 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3077 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3078 .resetfn
= arm_gt_cntfrq_reset
,
3080 /* overall control: mostly access permissions */
3081 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3082 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3087 /* per-timer control */
3088 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3089 .secure
= ARM_CP_SECSTATE_NS
,
3090 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3091 .accessfn
= gt_ptimer_access
,
3092 .fieldoffset
= offsetoflow32(CPUARMState
,
3093 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3094 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3095 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3097 { .name
= "CNTP_CTL_S",
3098 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3099 .secure
= ARM_CP_SECSTATE_S
,
3100 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3101 .accessfn
= gt_ptimer_access
,
3102 .fieldoffset
= offsetoflow32(CPUARMState
,
3103 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3104 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3106 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3107 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3108 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3109 .accessfn
= gt_ptimer_access
,
3110 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3112 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3113 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3115 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3116 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3117 .accessfn
= gt_vtimer_access
,
3118 .fieldoffset
= offsetoflow32(CPUARMState
,
3119 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3120 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3121 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3123 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3124 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3125 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3126 .accessfn
= gt_vtimer_access
,
3127 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3129 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3130 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3132 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3133 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3134 .secure
= ARM_CP_SECSTATE_NS
,
3135 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3136 .accessfn
= gt_ptimer_access
,
3137 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3139 { .name
= "CNTP_TVAL_S",
3140 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3141 .secure
= ARM_CP_SECSTATE_S
,
3142 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3143 .accessfn
= gt_ptimer_access
,
3144 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3146 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3147 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3148 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3149 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3150 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3152 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3153 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3154 .accessfn
= gt_vtimer_access
,
3155 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3157 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3158 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3159 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3160 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3161 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3163 /* The counter itself */
3164 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3165 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3166 .accessfn
= gt_pct_access
,
3167 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3169 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3170 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3171 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3172 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3174 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3175 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3176 .accessfn
= gt_vct_access
,
3177 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3179 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3180 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3181 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3182 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3184 /* Comparison value, indicating when the timer goes off */
3185 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3186 .secure
= ARM_CP_SECSTATE_NS
,
3188 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3189 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3190 .accessfn
= gt_ptimer_access
,
3191 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3192 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3194 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3195 .secure
= ARM_CP_SECSTATE_S
,
3197 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3198 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3199 .accessfn
= gt_ptimer_access
,
3200 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3202 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3203 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3206 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3207 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3208 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3209 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3211 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3213 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3214 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3215 .accessfn
= gt_vtimer_access
,
3216 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3217 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3219 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3220 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3223 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3224 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3225 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3226 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3229 * Secure timer -- this is actually restricted to only EL3
3230 * and configurably Secure-EL1 via the accessfn.
3232 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3233 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3234 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3235 .accessfn
= gt_stimer_access
,
3236 .readfn
= gt_sec_tval_read
,
3237 .writefn
= gt_sec_tval_write
,
3238 .resetfn
= gt_sec_timer_reset
,
3240 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3241 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3242 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3243 .accessfn
= gt_stimer_access
,
3244 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3246 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3248 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3249 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3250 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3251 .accessfn
= gt_stimer_access
,
3252 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3253 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3257 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3260 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3261 return CP_ACCESS_TRAP
;
3263 return CP_ACCESS_OK
;
3269 * In user-mode most of the generic timer registers are inaccessible
3270 * however modern kernels (4.12+) allow access to cntvct_el0
3273 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3275 ARMCPU
*cpu
= env_archcpu(env
);
3278 * Currently we have no support for QEMUTimer in linux-user so we
3279 * can't call gt_get_countervalue(env), instead we directly
3280 * call the lower level functions.
3282 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3285 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3286 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3287 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3288 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3289 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3290 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3292 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3293 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3294 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3295 .readfn
= gt_virt_cnt_read
,
3301 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3303 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3304 raw_write(env
, ri
, value
);
3305 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3306 raw_write(env
, ri
, value
& 0xfffff6ff);
3308 raw_write(env
, ri
, value
& 0xfffff1ff);
3312 #ifndef CONFIG_USER_ONLY
3313 /* get_phys_addr() isn't present for user-mode-only targets */
3315 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3320 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3321 * Secure EL1 (which can only happen if EL3 is AArch64).
3322 * They are simply UNDEF if executed from NS EL1.
3323 * They function normally from EL2 or EL3.
3325 if (arm_current_el(env
) == 1) {
3326 if (arm_is_secure_below_el3(env
)) {
3327 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3328 return CP_ACCESS_TRAP_EL2
;
3330 return CP_ACCESS_TRAP_EL3
;
3332 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3335 return CP_ACCESS_OK
;
3339 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3340 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3345 bool format64
= false;
3346 ARMMMUFaultInfo fi
= {};
3347 GetPhysAddrResult res
= {};
3349 ret
= get_phys_addr_with_secure(env
, value
, access_type
, mmu_idx
,
3350 is_secure
, &res
, &fi
);
3353 * ATS operations only do S1 or S1+S2 translations, so we never
3354 * have to deal with the ARMCacheAttrs format for S2 only.
3356 assert(!res
.cacheattrs
.is_s2_format
);
3360 * Some kinds of translation fault must cause exceptions rather
3361 * than being reported in the PAR.
3363 int current_el
= arm_current_el(env
);
3365 uint32_t syn
, fsr
, fsc
;
3366 bool take_exc
= false;
3368 if (fi
.s1ptw
&& current_el
== 1
3369 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3371 * Synchronous stage 2 fault on an access made as part of the
3372 * translation table walk for AT S1E0* or AT S1E1* insn
3373 * executed from NS EL1. If this is a synchronous external abort
3374 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3375 * to EL3. Otherwise the fault is taken as an exception to EL2,
3376 * and HPFAR_EL2 holds the faulting IPA.
3378 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3379 (env
->cp15
.scr_el3
& SCR_EA
)) {
3382 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3383 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3384 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3389 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3391 * Synchronous external aborts during a translation table walk
3392 * are taken as Data Abort exceptions.
3395 if (current_el
== 3) {
3401 target_el
= exception_target_el(env
);
3407 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3408 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3409 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3410 fsr
= arm_fi_to_lfsc(&fi
);
3411 fsc
= extract32(fsr
, 0, 6);
3413 fsr
= arm_fi_to_sfsc(&fi
);
3417 * Report exception with ESR indicating a fault due to a
3418 * translation table walk for a cache maintenance instruction.
3420 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3421 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3422 env
->exception
.vaddress
= value
;
3423 env
->exception
.fsr
= fsr
;
3424 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3430 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3433 * * TTBCR.EAE determines whether the result is returned using the
3434 * 32-bit or the 64-bit PAR format
3435 * * Instructions executed in Hyp mode always use the 64bit format
3437 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3438 * * The Non-secure TTBCR.EAE bit is set to 1
3439 * * The implementation includes EL2, and the value of HCR.VM is 1
3441 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3443 * ATS1Hx always uses the 64bit format.
3445 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3447 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3448 if (mmu_idx
== ARMMMUIdx_E10_0
||
3449 mmu_idx
== ARMMMUIdx_E10_1
||
3450 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3451 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3453 format64
|= arm_current_el(env
) == 2;
3459 /* Create a 64-bit PAR */
3460 par64
= (1 << 11); /* LPAE bit always set */
3462 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3463 if (!res
.f
.attrs
.secure
) {
3464 par64
|= (1 << 9); /* NS */
3466 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3467 par64
|= res
.cacheattrs
.shareability
<< 7; /* SH */
3469 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3472 par64
|= (fsr
& 0x3f) << 1; /* FS */
3474 par64
|= (1 << 9); /* S */
3477 par64
|= (1 << 8); /* PTW */
3482 * fsr is a DFSR/IFSR value for the short descriptor
3483 * translation table format (with WnR always clear).
3484 * Convert it to a 32-bit PAR.
3487 /* We do not set any attribute bits in the PAR */
3488 if (res
.f
.lg_page_size
== 24
3489 && arm_feature(env
, ARM_FEATURE_V7
)) {
3490 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3492 par64
= res
.f
.phys_addr
& 0xfffff000;
3494 if (!res
.f
.attrs
.secure
) {
3495 par64
|= (1 << 9); /* NS */
3498 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3500 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3501 ((fsr
& 0xf) << 1) | 1;
3506 #endif /* CONFIG_TCG */
3508 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3511 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3514 int el
= arm_current_el(env
);
3515 bool secure
= arm_is_secure_below_el3(env
);
3517 switch (ri
->opc2
& 6) {
3519 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3522 mmu_idx
= ARMMMUIdx_E3
;
3526 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3529 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3530 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3532 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3536 g_assert_not_reached();
3540 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3543 mmu_idx
= ARMMMUIdx_E10_0
;
3547 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3548 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3551 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3554 g_assert_not_reached();
3558 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3559 mmu_idx
= ARMMMUIdx_E10_1
;
3563 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3564 mmu_idx
= ARMMMUIdx_E10_0
;
3568 g_assert_not_reached();
3571 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, secure
);
3573 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3575 /* Handled by hardware accelerator. */
3576 g_assert_not_reached();
3577 #endif /* CONFIG_TCG */
3580 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3584 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3587 /* There is no SecureEL2 for AArch32. */
3588 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
, false);
3590 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3592 /* Handled by hardware accelerator. */
3593 g_assert_not_reached();
3594 #endif /* CONFIG_TCG */
3597 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3600 if (arm_current_el(env
) == 3 &&
3601 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3602 return CP_ACCESS_TRAP
;
3604 return CP_ACCESS_OK
;
3607 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3611 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3613 int secure
= arm_is_secure_below_el3(env
);
3614 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3615 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3617 switch (ri
->opc2
& 6) {
3620 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3621 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3622 mmu_idx
= regime_e20
?
3623 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3625 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3628 case 4: /* AT S1E2R, AT S1E2W */
3629 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3631 case 6: /* AT S1E3R, AT S1E3W */
3632 mmu_idx
= ARMMMUIdx_E3
;
3636 g_assert_not_reached();
3639 case 2: /* AT S1E0R, AT S1E0W */
3640 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3642 case 4: /* AT S12E1R, AT S12E1W */
3643 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3645 case 6: /* AT S12E0R, AT S12E0W */
3646 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3649 g_assert_not_reached();
3652 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3655 /* Handled by hardware accelerator. */
3656 g_assert_not_reached();
3657 #endif /* CONFIG_TCG */
3661 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3662 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3663 .access
= PL1_RW
, .resetvalue
= 0,
3664 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3665 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3666 .writefn
= par_write
},
3667 #ifndef CONFIG_USER_ONLY
3668 /* This underdecoding is safe because the reginfo is NO_RAW. */
3669 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3670 .access
= PL1_W
, .accessfn
= ats_access
,
3671 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3675 /* Return basic MPU access permission bits. */
3676 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3683 for (i
= 0; i
< 16; i
+= 2) {
3684 ret
|= (val
>> i
) & mask
;
3690 /* Pad basic MPU access permission bits to extended format. */
3691 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3698 for (i
= 0; i
< 16; i
+= 2) {
3699 ret
|= (val
& mask
) << i
;
3705 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3708 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3711 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3713 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3716 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3719 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3722 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3724 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3727 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3729 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3735 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3739 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3742 ARMCPU
*cpu
= env_archcpu(env
);
3743 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3749 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3750 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3754 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3757 ARMCPU
*cpu
= env_archcpu(env
);
3758 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3760 if (value
>= nrgs
) {
3761 qemu_log_mask(LOG_GUEST_ERROR
,
3762 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3763 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3767 raw_write(env
, ri
, value
);
3770 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3773 ARMCPU
*cpu
= env_archcpu(env
);
3775 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3776 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3779 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3781 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3784 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3787 ARMCPU
*cpu
= env_archcpu(env
);
3789 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3790 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3793 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3795 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3798 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3801 ARMCPU
*cpu
= env_archcpu(env
);
3804 * Ignore writes that would select not implemented region.
3805 * This is architecturally UNPREDICTABLE.
3807 if (value
>= cpu
->pmsav7_dregion
) {
3811 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3814 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3817 ARMCPU
*cpu
= env_archcpu(env
);
3819 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3820 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3823 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3825 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3828 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3831 ARMCPU
*cpu
= env_archcpu(env
);
3833 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3834 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3837 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3839 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3842 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3847 ARMCPU
*cpu
= env_archcpu(env
);
3849 /* Ignore writes to unimplemented regions */
3850 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3851 value
&= MAKE_64BIT_MASK(0, rmax
);
3853 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3855 /* Register alias is only valid for first 32 indexes */
3856 for (n
= 0; n
< rmax
; ++n
) {
3857 bit
= extract32(value
, n
, 1);
3858 env
->pmsav8
.hprlar
[n
] = deposit32(
3859 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3863 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3866 uint32_t result
= 0x0;
3867 ARMCPU
*cpu
= env_archcpu(env
);
3869 /* Register alias is only valid for first 32 indexes */
3870 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3871 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3872 result
|= (0x1 << n
);
3878 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3881 ARMCPU
*cpu
= env_archcpu(env
);
3884 * Ignore writes that would select not implemented region.
3885 * This is architecturally UNPREDICTABLE.
3887 if (value
>= cpu
->pmsav8r_hdregion
) {
3891 env
->pmsav8
.hprselr
= value
;
3894 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3897 ARMCPU
*cpu
= env_archcpu(env
);
3898 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3899 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3901 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3904 if (index
>= cpu
->pmsav8r_hdregion
) {
3907 if (ri
->opc2
& 0x1) {
3908 env
->pmsav8
.hprlar
[index
] = value
;
3910 env
->pmsav8
.hprbar
[index
] = value
;
3913 if (index
>= cpu
->pmsav7_dregion
) {
3916 if (ri
->opc2
& 0x1) {
3917 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
3919 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
3924 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3926 ARMCPU
*cpu
= env_archcpu(env
);
3927 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3928 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3931 if (index
>= cpu
->pmsav8r_hdregion
) {
3934 if (ri
->opc2
& 0x1) {
3935 return env
->pmsav8
.hprlar
[index
];
3937 return env
->pmsav8
.hprbar
[index
];
3940 if (index
>= cpu
->pmsav7_dregion
) {
3943 if (ri
->opc2
& 0x1) {
3944 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
3946 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
3951 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
3953 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
3954 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3955 .accessfn
= access_tvm_trvm
,
3956 .readfn
= prbar_read
, .writefn
= prbar_write
},
3958 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
3959 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3960 .accessfn
= access_tvm_trvm
,
3961 .readfn
= prlar_read
, .writefn
= prlar_write
},
3962 { .name
= "PRSELR", .resetvalue
= 0,
3963 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
3964 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3965 .writefn
= prselr_write
,
3966 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
3967 { .name
= "HPRBAR", .resetvalue
= 0,
3968 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
3969 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3970 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
3972 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
3973 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3974 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
3975 { .name
= "HPRSELR", .resetvalue
= 0,
3976 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
3978 .writefn
= hprselr_write
,
3979 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
3981 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
3982 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3983 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
3986 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3988 * Reset for all these registers is handled in arm_cpu_reset(),
3989 * because the PMSAv7 is also used by M-profile CPUs, which do
3990 * not register cpregs but still need the state to be reset.
3992 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3993 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3994 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3995 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3996 .resetfn
= arm_cp_reset_ignore
},
3997 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3998 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3999 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4000 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4001 .resetfn
= arm_cp_reset_ignore
},
4002 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4003 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4004 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4005 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4006 .resetfn
= arm_cp_reset_ignore
},
4007 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4009 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4010 .writefn
= pmsav7_rgnr_write
,
4011 .resetfn
= arm_cp_reset_ignore
},
4014 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4015 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4016 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4017 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4018 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4019 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4020 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4021 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4022 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4023 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4025 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4027 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4029 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4031 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4033 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4034 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4036 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4037 /* Protection region base and size registers */
4038 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4039 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4040 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4041 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4042 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4043 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4044 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4045 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4046 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4047 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4048 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4049 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4050 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4051 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4052 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4053 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4054 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4055 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4056 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4057 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4058 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4059 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4060 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4061 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4064 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4067 ARMCPU
*cpu
= env_archcpu(env
);
4069 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4070 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4072 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4073 * using Long-descriptor translation table format
4075 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4076 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4078 * In an implementation that includes the Security Extensions
4079 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4080 * Short-descriptor translation table format.
4082 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4088 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4090 * With LPAE the TTBCR could result in a change of ASID
4091 * via the TTBCR.A1 bit, so do a TLB flush.
4093 tlb_flush(CPU(cpu
));
4095 raw_write(env
, ri
, value
);
4098 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4101 ARMCPU
*cpu
= env_archcpu(env
);
4103 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4104 tlb_flush(CPU(cpu
));
4105 raw_write(env
, ri
, value
);
4108 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4111 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4112 if (cpreg_field_is_64bit(ri
) &&
4113 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4114 ARMCPU
*cpu
= env_archcpu(env
);
4115 tlb_flush(CPU(cpu
));
4117 raw_write(env
, ri
, value
);
4120 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4124 * If we are running with E2&0 regime, then an ASID is active.
4125 * Flush if that might be changing. Note we're not checking
4126 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4127 * holds the active ASID, only checking the field that might.
4129 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4130 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4131 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4132 ARMMMUIdxBit_E20_2_PAN
|
4134 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4136 raw_write(env
, ri
, value
);
4139 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4142 ARMCPU
*cpu
= env_archcpu(env
);
4143 CPUState
*cs
= CPU(cpu
);
4146 * A change in VMID to the stage2 page table (Stage2) invalidates
4147 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4149 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4150 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4152 raw_write(env
, ri
, value
);
4155 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4156 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4157 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4158 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4159 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4160 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4161 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4162 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4163 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4164 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4165 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4166 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4167 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4168 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4169 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4170 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4172 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4176 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4177 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4178 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4179 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4181 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4182 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4183 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4184 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4185 .fgt
= FGT_TTBR0_EL1
,
4186 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4187 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4188 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4189 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4190 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4191 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4192 .fgt
= FGT_TTBR1_EL1
,
4193 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4194 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4195 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4196 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4197 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4198 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4200 .writefn
= vmsa_tcr_el12_write
,
4201 .raw_writefn
= raw_write
,
4203 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4204 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4205 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4206 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4207 .raw_writefn
= raw_write
,
4208 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4209 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4213 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4214 * qemu tlbs nor adjusting cached masks.
4216 static const ARMCPRegInfo ttbcr2_reginfo
= {
4217 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4218 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4219 .type
= ARM_CP_ALIAS
,
4220 .bank_fieldoffsets
= {
4221 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4222 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4226 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4229 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4230 /* The OS_TYPE bit in this register changes the reported CPUID! */
4231 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4232 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4235 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4238 env
->cp15
.c15_threadid
= value
& 0xffff;
4241 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4244 /* Wait-for-interrupt (deprecated) */
4245 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4248 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4252 * On OMAP there are registers indicating the max/min index of dcache lines
4253 * containing a dirty line; cache flush operations have to reset these.
4255 env
->cp15
.c15_i_max
= 0x000;
4256 env
->cp15
.c15_i_min
= 0xff0;
4259 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4260 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4261 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4262 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4264 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4265 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4266 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4268 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4269 .writefn
= omap_ticonfig_write
},
4270 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4272 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4273 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4274 .access
= PL1_RW
, .resetvalue
= 0xff0,
4275 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4276 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4279 .writefn
= omap_threadid_write
},
4280 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4281 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4282 .type
= ARM_CP_NO_RAW
,
4283 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4285 * TODO: Peripheral port remap register:
4286 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4287 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4290 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4291 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4292 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4293 .writefn
= omap_cachemaint_write
},
4294 { .name
= "C9", .cp
= 15, .crn
= 9,
4295 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4296 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4299 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4302 env
->cp15
.c15_cpar
= value
& 0x3fff;
4305 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4306 { .name
= "XSCALE_CPAR",
4307 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4308 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4309 .writefn
= xscale_cpar_write
, },
4310 { .name
= "XSCALE_AUXCR",
4311 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4312 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4315 * XScale specific cache-lockdown: since we have no cache we NOP these
4316 * and hope the guest does not really rely on cache behaviour.
4318 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4319 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4320 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4321 { .name
= "XSCALE_UNLOCK_ICACHE",
4322 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4323 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4324 { .name
= "XSCALE_DCACHE_LOCK",
4325 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4326 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4327 { .name
= "XSCALE_UNLOCK_DCACHE",
4328 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4329 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4332 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4334 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4335 * implementation of this implementation-defined space.
4336 * Ideally this should eventually disappear in favour of actually
4337 * implementing the correct behaviour for all cores.
4339 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4340 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4342 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4346 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4347 /* Cache status: RAZ because we have no cache so it's always clean */
4348 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4349 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4353 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4354 /* We never have a block transfer operation in progress */
4355 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4356 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4358 /* The cache ops themselves: these all NOP for QEMU */
4359 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4360 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4361 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4362 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4363 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4364 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4365 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4366 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4367 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4368 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4369 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4370 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4373 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4375 * The cache test-and-clean instructions always return (1 << 30)
4376 * to indicate that there are no dirty cache lines.
4378 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4379 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4380 .resetvalue
= (1 << 30) },
4381 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4382 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4383 .resetvalue
= (1 << 30) },
4386 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4387 /* Ignore ReadBuffer accesses */
4388 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4389 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4390 .access
= PL1_RW
, .resetvalue
= 0,
4391 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4394 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4396 unsigned int cur_el
= arm_current_el(env
);
4398 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4399 return env
->cp15
.vpidr_el2
;
4401 return raw_read(env
, ri
);
4404 static uint64_t mpidr_read_val(CPUARMState
*env
)
4406 ARMCPU
*cpu
= env_archcpu(env
);
4407 uint64_t mpidr
= cpu
->mp_affinity
;
4409 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4410 mpidr
|= (1U << 31);
4412 * Cores which are uniprocessor (non-coherent)
4413 * but still implement the MP extensions set
4414 * bit 30. (For instance, Cortex-R5).
4416 if (cpu
->mp_is_up
) {
4417 mpidr
|= (1u << 30);
4423 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4425 unsigned int cur_el
= arm_current_el(env
);
4427 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4428 return env
->cp15
.vmpidr_el2
;
4430 return mpidr_read_val(env
);
4433 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4435 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4436 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4437 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4438 .fgt
= FGT_AMAIR_EL1
,
4439 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4440 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4441 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4442 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4443 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4444 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4445 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4446 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4447 offsetof(CPUARMState
, cp15
.par_ns
)} },
4448 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4449 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4450 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4451 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4452 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4453 .writefn
= vmsa_ttbr_write
, },
4454 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4455 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4456 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4457 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4458 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4459 .writefn
= vmsa_ttbr_write
, },
4462 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4464 return vfp_get_fpcr(env
);
4467 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4470 vfp_set_fpcr(env
, value
);
4473 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4475 return vfp_get_fpsr(env
);
4478 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4481 vfp_set_fpsr(env
, value
);
4484 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4487 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4488 return CP_ACCESS_TRAP
;
4490 return CP_ACCESS_OK
;
4493 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4496 env
->daif
= value
& PSTATE_DAIF
;
4499 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4501 return env
->pstate
& PSTATE_PAN
;
4504 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4507 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4510 static const ARMCPRegInfo pan_reginfo
= {
4511 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4512 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4513 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4514 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4517 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4519 return env
->pstate
& PSTATE_UAO
;
4522 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4525 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4528 static const ARMCPRegInfo uao_reginfo
= {
4529 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4530 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4531 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4532 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4535 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4537 return env
->pstate
& PSTATE_DIT
;
4540 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4543 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4546 static const ARMCPRegInfo dit_reginfo
= {
4547 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4548 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4549 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4550 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4553 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4555 return env
->pstate
& PSTATE_SSBS
;
4558 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4561 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4564 static const ARMCPRegInfo ssbs_reginfo
= {
4565 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4566 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4567 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4568 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4571 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4572 const ARMCPRegInfo
*ri
,
4575 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4576 switch (arm_current_el(env
)) {
4578 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4579 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4580 return CP_ACCESS_TRAP
;
4584 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4585 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4586 return CP_ACCESS_TRAP_EL2
;
4590 return CP_ACCESS_OK
;
4593 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4595 /* Cache invalidate/clean to Point of Unification... */
4596 switch (arm_current_el(env
)) {
4598 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4599 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4600 return CP_ACCESS_TRAP
;
4604 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4605 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4606 return CP_ACCESS_TRAP_EL2
;
4610 return CP_ACCESS_OK
;
4613 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4616 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4619 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4622 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4626 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4627 * Page D4-1736 (DDI0487A.b)
4630 static int vae1_tlbmask(CPUARMState
*env
)
4632 uint64_t hcr
= arm_hcr_el2_eff(env
);
4635 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4636 mask
= ARMMMUIdxBit_E20_2
|
4637 ARMMMUIdxBit_E20_2_PAN
|
4640 mask
= ARMMMUIdxBit_E10_1
|
4641 ARMMMUIdxBit_E10_1_PAN
|
4647 /* Return 56 if TBI is enabled, 64 otherwise. */
4648 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4651 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4652 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4653 int select
= extract64(addr
, 55, 1);
4655 return (tbi
>> select
) & 1 ? 56 : 64;
4658 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4660 uint64_t hcr
= arm_hcr_el2_eff(env
);
4663 /* Only the regime of the mmu_idx below is significant. */
4664 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4665 mmu_idx
= ARMMMUIdx_E20_0
;
4667 mmu_idx
= ARMMMUIdx_E10_0
;
4670 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4673 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4676 CPUState
*cs
= env_cpu(env
);
4677 int mask
= vae1_tlbmask(env
);
4679 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4682 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4685 CPUState
*cs
= env_cpu(env
);
4686 int mask
= vae1_tlbmask(env
);
4688 if (tlb_force_broadcast(env
)) {
4689 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4691 tlb_flush_by_mmuidx(cs
, mask
);
4695 static int e2_tlbmask(CPUARMState
*env
)
4697 return (ARMMMUIdxBit_E20_0
|
4698 ARMMMUIdxBit_E20_2
|
4699 ARMMMUIdxBit_E20_2_PAN
|
4703 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4706 CPUState
*cs
= env_cpu(env
);
4707 int mask
= alle1_tlbmask(env
);
4709 tlb_flush_by_mmuidx(cs
, mask
);
4712 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4715 CPUState
*cs
= env_cpu(env
);
4716 int mask
= e2_tlbmask(env
);
4718 tlb_flush_by_mmuidx(cs
, mask
);
4721 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4724 ARMCPU
*cpu
= env_archcpu(env
);
4725 CPUState
*cs
= CPU(cpu
);
4727 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4730 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4733 CPUState
*cs
= env_cpu(env
);
4734 int mask
= alle1_tlbmask(env
);
4736 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4739 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4742 CPUState
*cs
= env_cpu(env
);
4743 int mask
= e2_tlbmask(env
);
4745 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4748 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4751 CPUState
*cs
= env_cpu(env
);
4753 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4756 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4760 * Invalidate by VA, EL2
4761 * Currently handles both VAE2 and VALE2, since we don't support
4762 * flush-last-level-only.
4764 CPUState
*cs
= env_cpu(env
);
4765 int mask
= e2_tlbmask(env
);
4766 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4768 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4771 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4775 * Invalidate by VA, EL3
4776 * Currently handles both VAE3 and VALE3, since we don't support
4777 * flush-last-level-only.
4779 ARMCPU
*cpu
= env_archcpu(env
);
4780 CPUState
*cs
= CPU(cpu
);
4781 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4783 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4786 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4789 CPUState
*cs
= env_cpu(env
);
4790 int mask
= vae1_tlbmask(env
);
4791 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4792 int bits
= vae1_tlbbits(env
, pageaddr
);
4794 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4797 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4801 * Invalidate by VA, EL1&0 (AArch64 version).
4802 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4803 * since we don't support flush-for-specific-ASID-only or
4804 * flush-last-level-only.
4806 CPUState
*cs
= env_cpu(env
);
4807 int mask
= vae1_tlbmask(env
);
4808 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4809 int bits
= vae1_tlbbits(env
, pageaddr
);
4811 if (tlb_force_broadcast(env
)) {
4812 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4814 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4818 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4821 CPUState
*cs
= env_cpu(env
);
4822 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4823 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E2
, pageaddr
);
4825 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4826 ARMMMUIdxBit_E2
, bits
);
4829 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4832 CPUState
*cs
= env_cpu(env
);
4833 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4834 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4836 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4837 ARMMMUIdxBit_E3
, bits
);
4840 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4843 * The MSB of value is the NS field, which only applies if SEL2
4844 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4847 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4848 && arm_is_secure_below_el3(env
)
4849 ? ARMMMUIdxBit_Stage2_S
4850 : ARMMMUIdxBit_Stage2
);
4853 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4856 CPUState
*cs
= env_cpu(env
);
4857 int mask
= ipas2e1_tlbmask(env
, value
);
4858 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4860 if (tlb_force_broadcast(env
)) {
4861 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4863 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4867 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4870 CPUState
*cs
= env_cpu(env
);
4871 int mask
= ipas2e1_tlbmask(env
, value
);
4872 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4874 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4877 #ifdef TARGET_AARCH64
4883 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
4886 * Note that the TLBI range TG field encoding differs from both
4887 * TG0 and TG1 encodings.
4901 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4904 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4905 /* Extract one bit to represent the va selector in use. */
4906 uint64_t select
= sextract64(value
, 36, 1);
4907 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4908 TLBIRange ret
= { };
4909 ARMGranuleSize gran
;
4911 page_size_granule
= extract64(value
, 46, 2);
4912 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
4914 /* The granule encoded in value must match the granule in use. */
4915 if (gran
!= param
.gran
) {
4916 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4921 page_shift
= arm_granule_bits(gran
);
4922 num
= extract64(value
, 39, 5);
4923 scale
= extract64(value
, 44, 2);
4924 exponent
= (5 * scale
) + 1;
4926 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4929 ret
.base
= sextract64(value
, 0, 37);
4931 ret
.base
= extract64(value
, 0, 37);
4935 * With DS=1, BaseADDR is always shifted 16 so that it is able
4936 * to address all 52 va bits. The input address is perforce
4937 * aligned on a 64k boundary regardless of translation granule.
4941 ret
.base
<<= page_shift
;
4946 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4947 int idxmap
, bool synced
)
4949 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4953 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4954 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4957 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4963 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4964 range
.length
, idxmap
, bits
);
4968 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4969 const ARMCPRegInfo
*ri
,
4973 * Invalidate by VA range, EL1&0.
4974 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4975 * since we don't support flush-for-specific-ASID-only or
4976 * flush-last-level-only.
4979 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4980 tlb_force_broadcast(env
));
4983 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4984 const ARMCPRegInfo
*ri
,
4988 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4989 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4990 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4991 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4992 * shareable specific flushes.
4995 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4998 static int vae2_tlbmask(CPUARMState
*env
)
5000 return ARMMMUIdxBit_E2
;
5003 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5004 const ARMCPRegInfo
*ri
,
5008 * Invalidate by VA range, EL2.
5009 * Currently handles all of RVAE2 and RVALE2,
5010 * since we don't support flush-for-specific-ASID-only or
5011 * flush-last-level-only.
5014 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5015 tlb_force_broadcast(env
));
5020 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5021 const ARMCPRegInfo
*ri
,
5025 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5026 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5027 * since we don't support flush-for-specific-ASID-only,
5028 * flush-last-level-only or inner/outer shareable specific flushes.
5031 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5035 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5036 const ARMCPRegInfo
*ri
,
5040 * Invalidate by VA range, EL3.
5041 * Currently handles all of RVAE3 and RVALE3,
5042 * since we don't support flush-for-specific-ASID-only or
5043 * flush-last-level-only.
5046 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5049 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5050 const ARMCPRegInfo
*ri
,
5054 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5055 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5056 * since we don't support flush-for-specific-ASID-only,
5057 * flush-last-level-only or inner/outer specific flushes.
5060 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5063 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5066 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5067 tlb_force_broadcast(env
));
5070 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5071 const ARMCPRegInfo
*ri
,
5074 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5078 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5081 int cur_el
= arm_current_el(env
);
5084 uint64_t hcr
= arm_hcr_el2_eff(env
);
5087 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5088 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5089 return CP_ACCESS_TRAP_EL2
;
5092 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5093 return CP_ACCESS_TRAP
;
5095 if (hcr
& HCR_TDZ
) {
5096 return CP_ACCESS_TRAP_EL2
;
5099 } else if (hcr
& HCR_TDZ
) {
5100 return CP_ACCESS_TRAP_EL2
;
5103 return CP_ACCESS_OK
;
5106 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5108 ARMCPU
*cpu
= env_archcpu(env
);
5109 int dzp_bit
= 1 << 4;
5111 /* DZP indicates whether DC ZVA access is allowed */
5112 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5115 return cpu
->dcz_blocksize
| dzp_bit
;
5118 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5121 if (!(env
->pstate
& PSTATE_SP
)) {
5123 * Access to SP_EL0 is undefined if it's being used as
5124 * the stack pointer.
5126 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5128 return CP_ACCESS_OK
;
5131 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5133 return env
->pstate
& PSTATE_SP
;
5136 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5138 update_spsel(env
, val
);
5141 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5144 ARMCPU
*cpu
= env_archcpu(env
);
5146 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5147 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5151 /* ??? Lots of these bits are not implemented. */
5153 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5154 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5155 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5157 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5158 SCTLR_ATA0
| SCTLR_ATA
);
5162 if (raw_read(env
, ri
) == value
) {
5164 * Skip the TLB flush if nothing actually changed; Linux likes
5165 * to do a lot of pointless SCTLR writes.
5170 raw_write(env
, ri
, value
);
5172 /* This may enable/disable the MMU, so do a TLB flush. */
5173 tlb_flush(CPU(cpu
));
5175 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5177 * Normally we would always end the TB on an SCTLR write; see the
5178 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5179 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5180 * of hflags from the translator, so do it here.
5182 arm_rebuild_hflags(env
);
5186 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5190 * Some MDCR_EL3 bits affect whether PMU counters are running:
5191 * if we are trying to change any of those then we must
5192 * bracket this update with PMU start/finish calls.
5194 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5199 env
->cp15
.mdcr_el3
= value
;
5205 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5208 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5209 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5212 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5216 * Some MDCR_EL2 bits affect whether PMU counters are running:
5217 * if we are trying to change any of those then we must
5218 * bracket this update with PMU start/finish calls.
5220 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5225 env
->cp15
.mdcr_el2
= value
;
5231 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5233 * Minimal set of EL0-visible registers. This will need to be expanded
5234 * significantly for system emulation of AArch64 CPUs.
5236 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5237 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5238 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5239 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5240 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5241 .type
= ARM_CP_NO_RAW
,
5242 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5243 .fieldoffset
= offsetof(CPUARMState
, daif
),
5244 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5245 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5246 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5247 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5248 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5249 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5250 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5251 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5252 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5253 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5254 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5255 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5256 .fgt
= FGT_DCZID_EL0
,
5257 .readfn
= aa64_dczid_read
},
5258 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5259 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5260 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5261 #ifndef CONFIG_USER_ONLY
5262 /* Avoid overhead of an access check that always passes in user-mode */
5263 .accessfn
= aa64_zva_access
,
5267 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5268 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5269 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5270 /* Cache ops: all NOPs since we don't emulate caches */
5271 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5272 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5273 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5274 .fgt
= FGT_ICIALLUIS
,
5275 .accessfn
= access_ticab
},
5276 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5277 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5278 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5280 .accessfn
= access_tocu
},
5281 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5282 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5283 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5285 .accessfn
= access_tocu
},
5286 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5287 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5288 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5290 .type
= ARM_CP_NOP
},
5291 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5292 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5294 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5295 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5296 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5297 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5299 .accessfn
= aa64_cacheop_poc_access
},
5300 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5301 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5303 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5304 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5305 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5306 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5308 .accessfn
= access_tocu
},
5309 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5310 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5311 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5313 .accessfn
= aa64_cacheop_poc_access
},
5314 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5315 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5317 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5318 /* TLBI operations */
5319 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5320 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5321 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5322 .fgt
= FGT_TLBIVMALLE1IS
,
5323 .writefn
= tlbi_aa64_vmalle1is_write
},
5324 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5325 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5326 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5327 .fgt
= FGT_TLBIVAE1IS
,
5328 .writefn
= tlbi_aa64_vae1is_write
},
5329 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5330 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5331 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5332 .fgt
= FGT_TLBIASIDE1IS
,
5333 .writefn
= tlbi_aa64_vmalle1is_write
},
5334 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5335 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5336 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5337 .fgt
= FGT_TLBIVAAE1IS
,
5338 .writefn
= tlbi_aa64_vae1is_write
},
5339 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5340 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5341 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5342 .fgt
= FGT_TLBIVALE1IS
,
5343 .writefn
= tlbi_aa64_vae1is_write
},
5344 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5345 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5346 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5347 .fgt
= FGT_TLBIVAALE1IS
,
5348 .writefn
= tlbi_aa64_vae1is_write
},
5349 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5350 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5351 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5352 .fgt
= FGT_TLBIVMALLE1
,
5353 .writefn
= tlbi_aa64_vmalle1_write
},
5354 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5355 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5356 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5357 .fgt
= FGT_TLBIVAE1
,
5358 .writefn
= tlbi_aa64_vae1_write
},
5359 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5360 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5361 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5362 .fgt
= FGT_TLBIASIDE1
,
5363 .writefn
= tlbi_aa64_vmalle1_write
},
5364 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5365 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5366 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5367 .fgt
= FGT_TLBIVAAE1
,
5368 .writefn
= tlbi_aa64_vae1_write
},
5369 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5370 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5371 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5372 .fgt
= FGT_TLBIVALE1
,
5373 .writefn
= tlbi_aa64_vae1_write
},
5374 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5375 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5376 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5377 .fgt
= FGT_TLBIVAALE1
,
5378 .writefn
= tlbi_aa64_vae1_write
},
5379 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5380 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5381 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5382 .writefn
= tlbi_aa64_ipas2e1is_write
},
5383 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5384 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5385 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5386 .writefn
= tlbi_aa64_ipas2e1is_write
},
5387 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5388 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5389 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5390 .writefn
= tlbi_aa64_alle1is_write
},
5391 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5392 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5393 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5394 .writefn
= tlbi_aa64_alle1is_write
},
5395 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5396 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5397 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5398 .writefn
= tlbi_aa64_ipas2e1_write
},
5399 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5400 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5401 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5402 .writefn
= tlbi_aa64_ipas2e1_write
},
5403 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5404 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5405 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5406 .writefn
= tlbi_aa64_alle1_write
},
5407 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5408 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5409 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5410 .writefn
= tlbi_aa64_alle1is_write
},
5411 #ifndef CONFIG_USER_ONLY
5412 /* 64 bit address translation operations */
5413 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5414 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5415 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5417 .writefn
= ats_write64
},
5418 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5419 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5420 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5422 .writefn
= ats_write64
},
5423 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5424 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5425 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5427 .writefn
= ats_write64
},
5428 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5429 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5430 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5432 .writefn
= ats_write64
},
5433 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5434 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5435 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5436 .writefn
= ats_write64
},
5437 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5438 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5439 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5440 .writefn
= ats_write64
},
5441 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5442 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5443 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5444 .writefn
= ats_write64
},
5445 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5446 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5447 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5448 .writefn
= ats_write64
},
5449 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5450 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5451 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5452 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5453 .writefn
= ats_write64
},
5454 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5455 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5456 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5457 .writefn
= ats_write64
},
5458 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5459 .type
= ARM_CP_ALIAS
,
5460 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5461 .access
= PL1_RW
, .resetvalue
= 0,
5463 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5464 .writefn
= par_write
},
5466 /* TLB invalidate last level of translation table walk */
5467 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5468 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5469 .writefn
= tlbimva_is_write
},
5470 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5471 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5472 .writefn
= tlbimvaa_is_write
},
5473 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5474 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5475 .writefn
= tlbimva_write
},
5476 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5477 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5478 .writefn
= tlbimvaa_write
},
5479 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5480 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5481 .writefn
= tlbimva_hyp_write
},
5482 { .name
= "TLBIMVALHIS",
5483 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5484 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5485 .writefn
= tlbimva_hyp_is_write
},
5486 { .name
= "TLBIIPAS2",
5487 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5488 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5489 .writefn
= tlbiipas2_hyp_write
},
5490 { .name
= "TLBIIPAS2IS",
5491 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5492 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5493 .writefn
= tlbiipas2is_hyp_write
},
5494 { .name
= "TLBIIPAS2L",
5495 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5496 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5497 .writefn
= tlbiipas2_hyp_write
},
5498 { .name
= "TLBIIPAS2LIS",
5499 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5500 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5501 .writefn
= tlbiipas2is_hyp_write
},
5502 /* 32 bit cache operations */
5503 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5504 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5505 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5506 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5507 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5508 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5509 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5510 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5511 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5512 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5513 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5514 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5515 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5516 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5517 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5518 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5519 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5520 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5521 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5522 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5523 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5524 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5525 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5526 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5527 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5528 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5529 /* MMU Domain access control / MPU write buffer control */
5530 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5531 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5532 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5533 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5534 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5535 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5536 .type
= ARM_CP_ALIAS
,
5537 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5539 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5540 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5541 .type
= ARM_CP_ALIAS
,
5542 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5544 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5546 * We rely on the access checks not allowing the guest to write to the
5547 * state field when SPSel indicates that it's being used as the stack
5550 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5551 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5552 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5553 .type
= ARM_CP_ALIAS
,
5554 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5555 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5556 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5557 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5558 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5559 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5560 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5561 .type
= ARM_CP_NO_RAW
,
5562 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5563 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5564 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5566 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5567 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5568 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5569 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5570 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5571 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5572 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5573 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5574 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5575 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5576 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5577 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5578 .type
= ARM_CP_ALIAS
,
5579 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5581 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5582 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5583 .type
= ARM_CP_ALIAS
,
5584 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5586 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5587 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5588 .type
= ARM_CP_ALIAS
,
5589 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5591 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5592 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5593 .type
= ARM_CP_ALIAS
,
5594 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5596 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5597 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5599 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5602 .writefn
= mdcr_el3_write
,
5603 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5604 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5605 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5606 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5607 .writefn
= sdcr_write
,
5608 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5611 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5613 ARMCPU
*cpu
= env_archcpu(env
);
5615 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5616 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5618 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5621 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5622 valid_mask
&= ~HCR_HCD
;
5623 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5625 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5626 * However, if we're using the SMC PSCI conduit then QEMU is
5627 * effectively acting like EL3 firmware and so the guest at
5628 * EL2 should retain the ability to prevent EL1 from being
5629 * able to make SMC calls into the ersatz firmware, so in
5630 * that case HCR.TSC should be read/write.
5632 valid_mask
&= ~HCR_TSC
;
5635 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5636 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5637 valid_mask
|= HCR_E2H
;
5639 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5640 valid_mask
|= HCR_TERR
| HCR_TEA
;
5642 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5643 valid_mask
|= HCR_TLOR
;
5645 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5646 valid_mask
|= HCR_API
| HCR_APK
;
5648 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5649 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5651 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5652 valid_mask
|= HCR_ENSCXT
;
5654 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5655 valid_mask
|= HCR_FWB
;
5659 if (cpu_isar_feature(any_evt
, cpu
)) {
5660 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5661 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5662 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5665 /* Clear RES0 bits. */
5666 value
&= valid_mask
;
5669 * These bits change the MMU setup:
5670 * HCR_VM enables stage 2 translation
5671 * HCR_PTW forbids certain page-table setups
5672 * HCR_DC disables stage1 and enables stage2 translation
5673 * HCR_DCT enables tagging on (disabled) stage1 translation
5674 * HCR_FWB changes the interpretation of stage2 descriptor bits
5676 if ((env
->cp15
.hcr_el2
^ value
) &
5677 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5678 tlb_flush(CPU(cpu
));
5680 env
->cp15
.hcr_el2
= value
;
5683 * Updates to VI and VF require us to update the status of
5684 * virtual interrupts, which are the logical OR of these bits
5685 * and the state of the input lines from the GIC. (This requires
5686 * that we have the iothread lock, which is done by marking the
5687 * reginfo structs as ARM_CP_IO.)
5688 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5689 * possible for it to be taken immediately, because VIRQ and
5690 * VFIQ are masked unless running at EL0 or EL1, and HCR
5691 * can only be written at EL2.
5693 g_assert(qemu_mutex_iothread_locked());
5694 arm_cpu_update_virq(cpu
);
5695 arm_cpu_update_vfiq(cpu
);
5696 arm_cpu_update_vserr(cpu
);
5699 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5701 do_hcr_write(env
, value
, 0);
5704 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5707 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5708 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5709 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5712 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5715 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5716 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5717 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5721 * Return the effective value of HCR_EL2, at the given security state.
5722 * Bits that are not included here:
5723 * RW (read from SCR_EL3.RW as needed)
5725 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, bool secure
)
5727 uint64_t ret
= env
->cp15
.hcr_el2
;
5729 if (!arm_is_el2_enabled_secstate(env
, secure
)) {
5731 * "This register has no effect if EL2 is not enabled in the
5732 * current Security state". This is ARMv8.4-SecEL2 speak for
5733 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5735 * Prior to that, the language was "In an implementation that
5736 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5737 * as if this field is 0 for all purposes other than a direct
5738 * read or write access of HCR_EL2". With lots of enumeration
5739 * on a per-field basis. In current QEMU, this is condition
5740 * is arm_is_secure_below_el3.
5742 * Since the v8.4 language applies to the entire register, and
5743 * appears to be backward compatible, use that.
5749 * For a cpu that supports both aarch64 and aarch32, we can set bits
5750 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5751 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5753 if (!arm_el_is_aa64(env
, 2)) {
5754 uint64_t aa32_valid
;
5757 * These bits are up-to-date as of ARMv8.6.
5758 * For HCR, it's easiest to list just the 2 bits that are invalid.
5759 * For HCR2, list those that are valid.
5761 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5762 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5763 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5767 if (ret
& HCR_TGE
) {
5768 /* These bits are up-to-date as of ARMv8.6. */
5769 if (ret
& HCR_E2H
) {
5770 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5771 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5772 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5773 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5774 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5775 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5777 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5779 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5780 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5781 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5788 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5790 return arm_hcr_el2_eff_secstate(env
, arm_is_secure_below_el3(env
));
5794 * Corresponds to ARM pseudocode function ELIsInHost().
5796 bool el_is_in_host(CPUARMState
*env
, int el
)
5801 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5802 * Perform the simplest bit tests first, and validate EL2 afterward.
5805 return false; /* EL1 or EL3 */
5809 * Note that hcr_write() checks isar_feature_aa64_vh(),
5810 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5812 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5813 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5817 /* TGE and/or E2H set: double check those bits are currently legal. */
5818 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5821 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5824 uint64_t valid_mask
= 0;
5826 /* No features adding bits to HCRX are implemented. */
5828 /* Clear RES0 bits. */
5829 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5832 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5835 if (arm_current_el(env
) < 3
5836 && arm_feature(env
, ARM_FEATURE_EL3
)
5837 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5838 return CP_ACCESS_TRAP_EL3
;
5840 return CP_ACCESS_OK
;
5843 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5844 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5845 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5846 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5847 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5850 /* Return the effective value of HCRX_EL2. */
5851 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5854 * The bits in this register behave as 0 for all purposes other than
5855 * direct reads of the register if:
5856 * - EL2 is not enabled in the current security state,
5857 * - SCR_EL3.HXEn is 0.
5859 if (!arm_is_el2_enabled(env
)
5860 || (arm_feature(env
, ARM_FEATURE_EL3
)
5861 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5864 return env
->cp15
.hcrx_el2
;
5867 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5871 * For A-profile AArch32 EL3, if NSACR.CP10
5872 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5874 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5875 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5876 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5877 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5879 env
->cp15
.cptr_el
[2] = value
;
5882 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5885 * For A-profile AArch32 EL3, if NSACR.CP10
5886 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5888 uint64_t value
= env
->cp15
.cptr_el
[2];
5890 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5891 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5892 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5897 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5898 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5900 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5901 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5902 .writefn
= hcr_write
},
5903 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5904 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5905 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5906 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5907 .writefn
= hcr_writelow
},
5908 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5909 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5910 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5911 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5912 .type
= ARM_CP_ALIAS
,
5913 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5915 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5916 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5917 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5918 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5919 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5920 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5921 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5922 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5923 .type
= ARM_CP_ALIAS
,
5924 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5926 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5927 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5928 .type
= ARM_CP_ALIAS
,
5929 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5931 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5932 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5933 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5934 .access
= PL2_RW
, .writefn
= vbar_write
,
5935 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5937 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5938 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5939 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5940 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5941 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5942 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5943 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5944 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5945 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5946 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5947 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5948 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5950 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5951 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5952 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5953 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5954 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5955 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5956 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5958 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5959 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5960 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5961 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5963 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5964 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5965 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5967 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5968 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5969 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5971 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5972 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5973 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5974 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5975 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5976 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5977 .type
= ARM_CP_ALIAS
,
5978 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5979 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
5980 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5981 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5983 /* no .writefn needed as this can't cause an ASID change */
5984 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5985 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5986 .cp
= 15, .opc1
= 6, .crm
= 2,
5987 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5988 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5989 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5990 .writefn
= vttbr_write
},
5991 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5992 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5993 .access
= PL2_RW
, .writefn
= vttbr_write
,
5994 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5995 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5996 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5997 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5998 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5999 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6000 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6001 .access
= PL2_RW
, .resetvalue
= 0,
6002 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6003 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6004 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6005 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
6006 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6007 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6008 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6009 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6010 { .name
= "TLBIALLNSNH",
6011 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6012 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6013 .writefn
= tlbiall_nsnh_write
},
6014 { .name
= "TLBIALLNSNHIS",
6015 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6016 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6017 .writefn
= tlbiall_nsnh_is_write
},
6018 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6019 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6020 .writefn
= tlbiall_hyp_write
},
6021 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6022 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6023 .writefn
= tlbiall_hyp_is_write
},
6024 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6025 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6026 .writefn
= tlbimva_hyp_write
},
6027 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6028 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6029 .writefn
= tlbimva_hyp_is_write
},
6030 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6031 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6032 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6033 .writefn
= tlbi_aa64_alle2_write
},
6034 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6035 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6036 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6037 .writefn
= tlbi_aa64_vae2_write
},
6038 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6039 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6040 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6041 .writefn
= tlbi_aa64_vae2_write
},
6042 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6043 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6044 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6045 .writefn
= tlbi_aa64_alle2is_write
},
6046 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6047 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6048 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6049 .writefn
= tlbi_aa64_vae2is_write
},
6050 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6051 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6052 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6053 .writefn
= tlbi_aa64_vae2is_write
},
6054 #ifndef CONFIG_USER_ONLY
6056 * Unlike the other EL2-related AT operations, these must
6057 * UNDEF from EL3 if EL2 is not implemented, which is why we
6058 * define them here rather than with the rest of the AT ops.
6060 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6061 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6062 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6063 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6064 .writefn
= ats_write64
},
6065 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6066 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6067 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6068 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6069 .writefn
= ats_write64
},
6071 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6072 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6073 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6074 * to behave as if SCR.NS was 1.
6076 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6078 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6079 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6081 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6082 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6083 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6085 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6086 * reset values as IMPDEF. We choose to reset to 3 to comply with
6087 * both ARMv7 and ARMv8.
6089 .access
= PL2_RW
, .resetvalue
= 3,
6090 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6091 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6092 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6093 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6094 .writefn
= gt_cntvoff_write
,
6095 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6096 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6097 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6098 .writefn
= gt_cntvoff_write
,
6099 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6100 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6101 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6102 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6103 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6104 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6105 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6107 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6108 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6109 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6110 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6111 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6112 .resetfn
= gt_hyp_timer_reset
,
6113 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6114 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6116 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6120 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6122 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6123 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6124 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6125 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6126 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6127 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6129 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6130 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6131 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6133 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6136 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6137 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6138 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6139 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6141 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6142 .writefn
= hcr_writehigh
},
6145 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6148 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6149 return CP_ACCESS_OK
;
6151 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6154 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6155 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6156 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6157 .access
= PL2_RW
, .accessfn
= sel2_access
,
6158 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6159 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6160 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6161 .access
= PL2_RW
, .accessfn
= sel2_access
,
6162 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6165 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6169 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6170 * At Secure EL1 it traps to EL3 or EL2.
6172 if (arm_current_el(env
) == 3) {
6173 return CP_ACCESS_OK
;
6175 if (arm_is_secure_below_el3(env
)) {
6176 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6177 return CP_ACCESS_TRAP_EL2
;
6179 return CP_ACCESS_TRAP_EL3
;
6181 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6183 return CP_ACCESS_OK
;
6185 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6188 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6189 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6190 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6191 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6192 .resetfn
= scr_reset
, .writefn
= scr_write
},
6193 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6194 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6195 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6196 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6197 .writefn
= scr_write
},
6198 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6199 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6200 .access
= PL3_RW
, .resetvalue
= 0,
6201 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6203 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6204 .access
= PL3_RW
, .resetvalue
= 0,
6205 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6206 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6207 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6208 .writefn
= vbar_write
, .resetvalue
= 0,
6209 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6210 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6211 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6212 .access
= PL3_RW
, .resetvalue
= 0,
6213 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6214 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6215 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6217 /* no .writefn needed as this can't cause an ASID change */
6219 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6220 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6221 .type
= ARM_CP_ALIAS
,
6222 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6224 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6225 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6226 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6227 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6228 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6229 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6230 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6231 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6232 .type
= ARM_CP_ALIAS
,
6233 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6235 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6236 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6237 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6238 .access
= PL3_RW
, .writefn
= vbar_write
,
6239 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6241 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6242 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6243 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6244 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6245 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6246 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6247 .access
= PL3_RW
, .resetvalue
= 0,
6248 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6249 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6250 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6251 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6253 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6254 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6255 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6257 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6258 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6259 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6261 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6262 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6263 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6264 .writefn
= tlbi_aa64_alle3is_write
},
6265 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6266 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6267 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6268 .writefn
= tlbi_aa64_vae3is_write
},
6269 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6270 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6271 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6272 .writefn
= tlbi_aa64_vae3is_write
},
6273 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6274 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6275 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6276 .writefn
= tlbi_aa64_alle3_write
},
6277 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6278 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6279 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6280 .writefn
= tlbi_aa64_vae3_write
},
6281 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6282 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6283 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6284 .writefn
= tlbi_aa64_vae3_write
},
6287 #ifndef CONFIG_USER_ONLY
6288 /* Test if system register redirection is to occur in the current state. */
6289 static bool redirect_for_e2h(CPUARMState
*env
)
6291 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6294 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6298 if (redirect_for_e2h(env
)) {
6299 /* Switch to the saved EL2 version of the register. */
6301 readfn
= ri
->readfn
;
6303 readfn
= ri
->orig_readfn
;
6305 if (readfn
== NULL
) {
6308 return readfn(env
, ri
);
6311 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6316 if (redirect_for_e2h(env
)) {
6317 /* Switch to the saved EL2 version of the register. */
6319 writefn
= ri
->writefn
;
6321 writefn
= ri
->orig_writefn
;
6323 if (writefn
== NULL
) {
6324 writefn
= raw_write
;
6326 writefn(env
, ri
, value
);
6329 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6332 uint32_t src_key
, dst_key
, new_key
;
6333 const char *src_name
, *dst_name
, *new_name
;
6334 bool (*feature
)(const ARMISARegisters
*id
);
6337 #define K(op0, op1, crn, crm, op2) \
6338 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6340 static const struct E2HAlias aliases
[] = {
6341 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6342 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6343 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6344 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6345 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6346 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6347 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6348 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6349 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6350 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6351 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6352 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6353 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6354 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6355 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6356 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6357 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6358 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6359 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6360 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6361 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6362 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6363 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6364 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6365 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6366 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6367 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6368 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6369 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6370 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6371 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6372 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6375 * Note that redirection of ZCR is mentioned in the description
6376 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6377 * not in the summary table.
6379 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6380 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6381 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6382 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6384 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6385 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6387 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6388 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6389 isar_feature_aa64_scxtnum
},
6391 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6392 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6398 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6399 const struct E2HAlias
*a
= &aliases
[i
];
6400 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6403 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6407 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6408 (gpointer
)(uintptr_t)a
->src_key
);
6409 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6410 (gpointer
)(uintptr_t)a
->dst_key
);
6411 g_assert(src_reg
!= NULL
);
6412 g_assert(dst_reg
!= NULL
);
6414 /* Cross-compare names to detect typos in the keys. */
6415 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6416 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6418 /* None of the core system registers use opaque; we will. */
6419 g_assert(src_reg
->opaque
== NULL
);
6421 /* Create alias before redirection so we dup the right data. */
6422 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6424 new_reg
->name
= a
->new_name
;
6425 new_reg
->type
|= ARM_CP_ALIAS
;
6426 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6427 new_reg
->access
&= PL2_RW
| PL3_RW
;
6429 ok
= g_hash_table_insert(cpu
->cp_regs
,
6430 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6433 src_reg
->opaque
= dst_reg
;
6434 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6435 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6436 if (!src_reg
->raw_readfn
) {
6437 src_reg
->raw_readfn
= raw_read
;
6439 if (!src_reg
->raw_writefn
) {
6440 src_reg
->raw_writefn
= raw_write
;
6442 src_reg
->readfn
= el2_e2h_read
;
6443 src_reg
->writefn
= el2_e2h_write
;
6448 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6451 int cur_el
= arm_current_el(env
);
6454 uint64_t hcr
= arm_hcr_el2_eff(env
);
6457 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6458 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6459 return CP_ACCESS_TRAP_EL2
;
6462 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6463 return CP_ACCESS_TRAP
;
6465 if (hcr
& HCR_TID2
) {
6466 return CP_ACCESS_TRAP_EL2
;
6469 } else if (hcr
& HCR_TID2
) {
6470 return CP_ACCESS_TRAP_EL2
;
6474 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6475 return CP_ACCESS_TRAP_EL2
;
6478 return CP_ACCESS_OK
;
6482 * Check for traps to RAS registers, which are controlled
6483 * by HCR_EL2.TERR and SCR_EL3.TERR.
6485 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6488 int el
= arm_current_el(env
);
6490 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6491 return CP_ACCESS_TRAP_EL2
;
6493 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6494 return CP_ACCESS_TRAP_EL3
;
6496 return CP_ACCESS_OK
;
6499 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6501 int el
= arm_current_el(env
);
6503 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6504 return env
->cp15
.vdisr_el2
;
6506 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6507 return 0; /* RAZ/WI */
6509 return env
->cp15
.disr_el1
;
6512 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6514 int el
= arm_current_el(env
);
6516 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6517 env
->cp15
.vdisr_el2
= val
;
6520 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6521 return; /* RAZ/WI */
6523 env
->cp15
.disr_el1
= val
;
6527 * Minimal RAS implementation with no Error Records.
6528 * Which means that all of the Error Record registers:
6536 * ERXPFGCDN_EL1 (RASv1p1)
6537 * ERXPFGCTL_EL1 (RASv1p1)
6538 * ERXPFGF_EL1 (RASv1p1)
6542 * may generate UNDEFINED, which is the effect we get by not
6543 * listing them at all.
6545 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6546 * is higher priority than FGT-to-EL2 so we do not need to list them
6547 * in order to check for an FGT.
6549 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6550 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6551 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6552 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6553 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6554 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6555 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6556 .access
= PL1_R
, .accessfn
= access_terr
,
6557 .fgt
= FGT_ERRIDR_EL1
,
6558 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6559 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6560 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6561 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6562 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6563 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6564 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6568 * Return the exception level to which exceptions should be taken
6569 * via SVEAccessTrap. This excludes the check for whether the exception
6570 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6571 * be found by testing 0 < fp_exception_el < sve_exception_el.
6573 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6574 * pseudocode does *not* separate out the FP trap checks, but has them
6575 * all in one function.
6577 int sve_exception_el(CPUARMState
*env
, int el
)
6579 #ifndef CONFIG_USER_ONLY
6580 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6581 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6593 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6594 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6595 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6596 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6598 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6607 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6613 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6614 if (arm_feature(env
, ARM_FEATURE_EL3
)
6615 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6623 * Return the exception level to which exceptions should be taken for SME.
6624 * C.f. the ARM pseudocode function CheckSMEAccess.
6626 int sme_exception_el(CPUARMState
*env
, int el
)
6628 #ifndef CONFIG_USER_ONLY
6629 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6630 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6642 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6643 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6644 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6645 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6647 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6656 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6662 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6663 if (arm_feature(env
, ARM_FEATURE_EL3
)
6664 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6671 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
6672 static bool sme_fa64(CPUARMState
*env
, int el
)
6674 if (!cpu_isar_feature(aa64_sme_fa64
, env_archcpu(env
))) {
6678 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6679 if (!FIELD_EX64(env
->vfp
.smcr_el
[1], SMCR
, FA64
)) {
6683 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6684 if (!FIELD_EX64(env
->vfp
.smcr_el
[2], SMCR
, FA64
)) {
6688 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6689 if (!FIELD_EX64(env
->vfp
.smcr_el
[3], SMCR
, FA64
)) {
6698 * Given that SVE is enabled, return the vector length for EL.
6700 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6702 ARMCPU
*cpu
= env_archcpu(env
);
6703 uint64_t *cr
= env
->vfp
.zcr_el
;
6704 uint32_t map
= cpu
->sve_vq
.map
;
6705 uint32_t len
= ARM_MAX_VQ
- 1;
6708 cr
= env
->vfp
.smcr_el
;
6709 map
= cpu
->sme_vq
.map
;
6712 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6713 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6715 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6716 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6718 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6719 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6722 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6724 return 31 - clz32(map
);
6727 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6729 return ctz32(cpu
->sme_vq
.map
);
6732 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6734 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6737 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6740 int cur_el
= arm_current_el(env
);
6741 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6744 /* Bits other than [3:0] are RAZ/WI. */
6745 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6746 raw_write(env
, ri
, value
& 0xf);
6749 * Because we arrived here, we know both FP and SVE are enabled;
6750 * otherwise we would have trapped access to the ZCR_ELn register.
6752 new_len
= sve_vqm1_for_el(env
, cur_el
);
6753 if (new_len
< old_len
) {
6754 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6758 static const ARMCPRegInfo zcr_reginfo
[] = {
6759 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6760 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6761 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6762 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6763 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6764 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6765 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6766 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6767 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6768 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6769 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6770 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6771 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6772 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6773 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6776 #ifdef TARGET_AARCH64
6777 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6780 int el
= arm_current_el(env
);
6783 uint64_t sctlr
= arm_sctlr(env
, el
);
6784 if (!(sctlr
& SCTLR_EnTP2
)) {
6785 return CP_ACCESS_TRAP
;
6788 /* TODO: FEAT_FGT */
6790 && arm_feature(env
, ARM_FEATURE_EL3
)
6791 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6792 return CP_ACCESS_TRAP_EL3
;
6794 return CP_ACCESS_OK
;
6797 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6800 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6801 if (arm_current_el(env
) < 3
6802 && arm_feature(env
, ARM_FEATURE_EL3
)
6803 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6804 return CP_ACCESS_TRAP_EL3
;
6806 return CP_ACCESS_OK
;
6810 static void arm_reset_sve_state(CPUARMState
*env
)
6812 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
6813 /* Recall that FFR is stored as pregs[16]. */
6814 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
6815 vfp_set_fpcr(env
, 0x0800009f);
6818 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
6820 uint64_t change
= (env
->svcr
^ new) & mask
;
6825 env
->svcr
^= change
;
6827 if (change
& R_SVCR_SM_MASK
) {
6828 arm_reset_sve_state(env
);
6834 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
6835 * on enable: while disabled, the storage is inaccessible and the
6836 * value does not matter. We're not saving the storage in vmstate
6837 * when disabled either.
6839 if (change
& new & R_SVCR_ZA_MASK
) {
6840 memset(env
->zarray
, 0, sizeof(env
->zarray
));
6843 arm_rebuild_hflags(env
);
6846 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6849 aarch64_set_svcr(env
, value
, -1);
6852 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6855 int cur_el
= arm_current_el(env
);
6856 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6859 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6860 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6861 raw_write(env
, ri
, value
);
6864 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
6865 * when SVL is widened (old values kept, or zeros). Choose to keep the
6866 * current values for simplicity. But for QEMU internals, we must still
6867 * apply the narrower SVL to the Zregs and Pregs -- see the comment
6868 * above aarch64_sve_narrow_vq.
6870 new_len
= sve_vqm1_for_el(env
, cur_el
);
6871 if (new_len
< old_len
) {
6872 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6876 static const ARMCPRegInfo sme_reginfo
[] = {
6877 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
6878 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
6879 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
6880 .fgt
= FGT_NTPIDR2_EL0
,
6881 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
6882 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
6883 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
6884 .access
= PL0_RW
, .type
= ARM_CP_SME
,
6885 .fieldoffset
= offsetof(CPUARMState
, svcr
),
6886 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
6887 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
6888 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
6889 .access
= PL1_RW
, .type
= ARM_CP_SME
,
6890 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
6891 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6892 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
6893 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
6894 .access
= PL2_RW
, .type
= ARM_CP_SME
,
6895 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
6896 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6897 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
6898 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
6899 .access
= PL3_RW
, .type
= ARM_CP_SME
,
6900 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
6901 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6902 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
6903 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
6904 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
6906 * IMPLEMENTOR = 0 (software)
6907 * REVISION = 0 (implementation defined)
6908 * SMPS = 0 (no streaming execution priority in QEMU)
6909 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
6911 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
6913 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
6915 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
6916 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
6917 .access
= PL1_RW
, .accessfn
= access_esm
,
6918 .fgt
= FGT_NSMPRI_EL1
,
6919 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6920 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
6921 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
6922 .access
= PL2_RW
, .accessfn
= access_esm
,
6923 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6925 #endif /* TARGET_AARCH64 */
6927 static void define_pmu_regs(ARMCPU
*cpu
)
6930 * v7 performance monitor control register: same implementor
6931 * field as main ID register, and we implement four counters in
6932 * addition to the cycle count register.
6934 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6935 ARMCPRegInfo pmcr
= {
6936 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6938 .fgt
= FGT_PMCR_EL0
,
6939 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6940 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6941 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6942 .raw_writefn
= raw_write
,
6944 ARMCPRegInfo pmcr64
= {
6945 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6946 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6947 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6948 .fgt
= FGT_PMCR_EL0
,
6950 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6951 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6952 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6955 define_one_arm_cp_reg(cpu
, &pmcr
);
6956 define_one_arm_cp_reg(cpu
, &pmcr64
);
6957 for (i
= 0; i
< pmcrn
; i
++) {
6958 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6959 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6960 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6961 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6962 ARMCPRegInfo pmev_regs
[] = {
6963 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6964 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6965 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6966 .fgt
= FGT_PMEVCNTRN_EL0
,
6967 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6968 .accessfn
= pmreg_access_xevcntr
},
6969 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6970 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6971 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6973 .fgt
= FGT_PMEVCNTRN_EL0
,
6974 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6975 .raw_readfn
= pmevcntr_rawread
,
6976 .raw_writefn
= pmevcntr_rawwrite
},
6977 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6978 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6979 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6980 .fgt
= FGT_PMEVTYPERN_EL0
,
6981 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6982 .accessfn
= pmreg_access
},
6983 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6984 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6985 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6986 .fgt
= FGT_PMEVTYPERN_EL0
,
6988 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6989 .raw_writefn
= pmevtyper_rawwrite
},
6991 define_arm_cp_regs(cpu
, pmev_regs
);
6992 g_free(pmevcntr_name
);
6993 g_free(pmevcntr_el0_name
);
6994 g_free(pmevtyper_name
);
6995 g_free(pmevtyper_el0_name
);
6997 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
6998 ARMCPRegInfo v81_pmu_regs
[] = {
6999 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7000 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7001 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7002 .fgt
= FGT_PMCEIDN_EL0
,
7003 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7004 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7005 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7006 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7007 .fgt
= FGT_PMCEIDN_EL0
,
7008 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7010 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7012 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7013 static const ARMCPRegInfo v84_pmmir
= {
7014 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7015 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7016 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7017 .fgt
= FGT_PMMIR_EL1
,
7020 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7025 * We don't know until after realize whether there's a GICv3
7026 * attached, and that is what registers the gicv3 sysregs.
7027 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7030 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7032 ARMCPU
*cpu
= env_archcpu(env
);
7033 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7035 if (env
->gicv3state
) {
7041 #ifndef CONFIG_USER_ONLY
7042 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7044 ARMCPU
*cpu
= env_archcpu(env
);
7045 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7047 if (env
->gicv3state
) {
7055 * Shared logic between LORID and the rest of the LOR* registers.
7056 * Secure state exclusion has already been dealt with.
7058 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7059 const ARMCPRegInfo
*ri
, bool isread
)
7061 int el
= arm_current_el(env
);
7063 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7064 return CP_ACCESS_TRAP_EL2
;
7066 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7067 return CP_ACCESS_TRAP_EL3
;
7069 return CP_ACCESS_OK
;
7072 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7073 const ARMCPRegInfo
*ri
, bool isread
)
7075 if (arm_is_secure_below_el3(env
)) {
7076 /* Access denied in secure mode. */
7077 return CP_ACCESS_TRAP
;
7079 return access_lor_ns(env
, ri
, isread
);
7083 * A trivial implementation of ARMv8.1-LOR leaves all of these
7084 * registers fixed at 0, which indicates that there are zero
7085 * supported Limited Ordering regions.
7087 static const ARMCPRegInfo lor_reginfo
[] = {
7088 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7089 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7090 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7091 .fgt
= FGT_LORSA_EL1
,
7092 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7093 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7094 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7095 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7096 .fgt
= FGT_LOREA_EL1
,
7097 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7098 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7099 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7100 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7101 .fgt
= FGT_LORN_EL1
,
7102 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7103 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7104 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7105 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7106 .fgt
= FGT_LORC_EL1
,
7107 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7108 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7109 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7110 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7111 .fgt
= FGT_LORID_EL1
,
7112 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7115 #ifdef TARGET_AARCH64
7116 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7119 int el
= arm_current_el(env
);
7122 arm_is_el2_enabled(env
) &&
7123 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7124 return CP_ACCESS_TRAP_EL2
;
7127 arm_feature(env
, ARM_FEATURE_EL3
) &&
7128 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7129 return CP_ACCESS_TRAP_EL3
;
7131 return CP_ACCESS_OK
;
7134 static const ARMCPRegInfo pauth_reginfo
[] = {
7135 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7136 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7137 .access
= PL1_RW
, .accessfn
= access_pauth
,
7139 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7140 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7141 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7142 .access
= PL1_RW
, .accessfn
= access_pauth
,
7144 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7145 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7146 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7147 .access
= PL1_RW
, .accessfn
= access_pauth
,
7149 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7150 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7151 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7152 .access
= PL1_RW
, .accessfn
= access_pauth
,
7154 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7155 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7156 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7157 .access
= PL1_RW
, .accessfn
= access_pauth
,
7159 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7160 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7161 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7162 .access
= PL1_RW
, .accessfn
= access_pauth
,
7164 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7165 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7166 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7167 .access
= PL1_RW
, .accessfn
= access_pauth
,
7169 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7170 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7171 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7172 .access
= PL1_RW
, .accessfn
= access_pauth
,
7174 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7175 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7176 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7177 .access
= PL1_RW
, .accessfn
= access_pauth
,
7179 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7180 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7181 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7182 .access
= PL1_RW
, .accessfn
= access_pauth
,
7184 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7187 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7188 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7189 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7190 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7191 .fgt
= FGT_TLBIRVAE1IS
,
7192 .writefn
= tlbi_aa64_rvae1is_write
},
7193 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7194 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7195 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7196 .fgt
= FGT_TLBIRVAAE1IS
,
7197 .writefn
= tlbi_aa64_rvae1is_write
},
7198 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7199 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7200 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7201 .fgt
= FGT_TLBIRVALE1IS
,
7202 .writefn
= tlbi_aa64_rvae1is_write
},
7203 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7204 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7205 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7206 .fgt
= FGT_TLBIRVAALE1IS
,
7207 .writefn
= tlbi_aa64_rvae1is_write
},
7208 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7209 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7210 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7211 .fgt
= FGT_TLBIRVAE1OS
,
7212 .writefn
= tlbi_aa64_rvae1is_write
},
7213 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7214 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7215 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7216 .fgt
= FGT_TLBIRVAAE1OS
,
7217 .writefn
= tlbi_aa64_rvae1is_write
},
7218 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7219 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7220 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7221 .fgt
= FGT_TLBIRVALE1OS
,
7222 .writefn
= tlbi_aa64_rvae1is_write
},
7223 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7224 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7225 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7226 .fgt
= FGT_TLBIRVAALE1OS
,
7227 .writefn
= tlbi_aa64_rvae1is_write
},
7228 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7229 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7230 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7231 .fgt
= FGT_TLBIRVAE1
,
7232 .writefn
= tlbi_aa64_rvae1_write
},
7233 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7234 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7235 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7236 .fgt
= FGT_TLBIRVAAE1
,
7237 .writefn
= tlbi_aa64_rvae1_write
},
7238 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7239 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7240 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7241 .fgt
= FGT_TLBIRVALE1
,
7242 .writefn
= tlbi_aa64_rvae1_write
},
7243 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7244 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7245 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7246 .fgt
= FGT_TLBIRVAALE1
,
7247 .writefn
= tlbi_aa64_rvae1_write
},
7248 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7249 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7250 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7251 .writefn
= tlbi_aa64_ripas2e1is_write
},
7252 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7253 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7254 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7255 .writefn
= tlbi_aa64_ripas2e1is_write
},
7256 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7257 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7258 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7259 .writefn
= tlbi_aa64_rvae2is_write
},
7260 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7261 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7262 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7263 .writefn
= tlbi_aa64_rvae2is_write
},
7264 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7265 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7266 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7267 .writefn
= tlbi_aa64_ripas2e1_write
},
7268 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7269 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7270 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7271 .writefn
= tlbi_aa64_ripas2e1_write
},
7272 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7273 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7274 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7275 .writefn
= tlbi_aa64_rvae2is_write
},
7276 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7277 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7278 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7279 .writefn
= tlbi_aa64_rvae2is_write
},
7280 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7281 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7282 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7283 .writefn
= tlbi_aa64_rvae2_write
},
7284 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7285 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7286 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7287 .writefn
= tlbi_aa64_rvae2_write
},
7288 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7289 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7290 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7291 .writefn
= tlbi_aa64_rvae3is_write
},
7292 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7293 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7294 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7295 .writefn
= tlbi_aa64_rvae3is_write
},
7296 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7297 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7298 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7299 .writefn
= tlbi_aa64_rvae3is_write
},
7300 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7301 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7302 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7303 .writefn
= tlbi_aa64_rvae3is_write
},
7304 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7305 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7306 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7307 .writefn
= tlbi_aa64_rvae3_write
},
7308 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7309 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7310 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7311 .writefn
= tlbi_aa64_rvae3_write
},
7314 static const ARMCPRegInfo tlbios_reginfo
[] = {
7315 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7316 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7317 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7318 .fgt
= FGT_TLBIVMALLE1OS
,
7319 .writefn
= tlbi_aa64_vmalle1is_write
},
7320 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7321 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7322 .fgt
= FGT_TLBIVAE1OS
,
7323 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7324 .writefn
= tlbi_aa64_vae1is_write
},
7325 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7326 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7327 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7328 .fgt
= FGT_TLBIASIDE1OS
,
7329 .writefn
= tlbi_aa64_vmalle1is_write
},
7330 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7331 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7332 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7333 .fgt
= FGT_TLBIVAAE1OS
,
7334 .writefn
= tlbi_aa64_vae1is_write
},
7335 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7336 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7337 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7338 .fgt
= FGT_TLBIVALE1OS
,
7339 .writefn
= tlbi_aa64_vae1is_write
},
7340 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7341 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7342 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7343 .fgt
= FGT_TLBIVAALE1OS
,
7344 .writefn
= tlbi_aa64_vae1is_write
},
7345 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7346 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7347 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7348 .writefn
= tlbi_aa64_alle2is_write
},
7349 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7350 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7351 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7352 .writefn
= tlbi_aa64_vae2is_write
},
7353 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7354 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7355 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7356 .writefn
= tlbi_aa64_alle1is_write
},
7357 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7358 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7359 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7360 .writefn
= tlbi_aa64_vae2is_write
},
7361 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7362 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7363 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7364 .writefn
= tlbi_aa64_alle1is_write
},
7365 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7366 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7367 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7368 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7369 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7370 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7371 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7372 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7373 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7374 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7375 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7376 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7377 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7378 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7379 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7380 .writefn
= tlbi_aa64_alle3is_write
},
7381 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7382 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7383 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7384 .writefn
= tlbi_aa64_vae3is_write
},
7385 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7386 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7387 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7388 .writefn
= tlbi_aa64_vae3is_write
},
7391 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7396 /* Success sets NZCV = 0000. */
7397 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7399 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7401 * ??? Failed, for unknown reasons in the crypto subsystem.
7402 * The best we can do is log the reason and return the
7403 * timed-out indication to the guest. There is no reason
7404 * we know to expect this failure to be transitory, so the
7405 * guest may well hang retrying the operation.
7407 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7408 ri
->name
, error_get_pretty(err
));
7411 env
->ZF
= 0; /* NZCF = 0100 */
7417 /* We do not support re-seeding, so the two registers operate the same. */
7418 static const ARMCPRegInfo rndr_reginfo
[] = {
7419 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7420 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7421 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7422 .access
= PL0_R
, .readfn
= rndr_readfn
},
7423 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7424 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7425 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7426 .access
= PL0_R
, .readfn
= rndr_readfn
},
7429 #ifndef CONFIG_USER_ONLY
7430 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7433 ARMCPU
*cpu
= env_archcpu(env
);
7434 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7435 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7436 uint64_t vaddr_in
= (uint64_t) value
;
7437 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7439 int mem_idx
= cpu_mmu_index(env
, false);
7441 /* This won't be crossing page boundaries */
7442 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7448 /* RCU lock is already being held */
7449 mr
= memory_region_from_host(haddr
, &offset
);
7452 memory_region_writeback(mr
, offset
, dline_size
);
7457 static const ARMCPRegInfo dcpop_reg
[] = {
7458 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7459 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7460 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7462 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7465 static const ARMCPRegInfo dcpodp_reg
[] = {
7466 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7467 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7468 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7470 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7472 #endif /*CONFIG_USER_ONLY*/
7474 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7477 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7478 return CP_ACCESS_TRAP_EL2
;
7481 return CP_ACCESS_OK
;
7484 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7487 int el
= arm_current_el(env
);
7489 if (el
< 2 && arm_is_el2_enabled(env
)) {
7490 uint64_t hcr
= arm_hcr_el2_eff(env
);
7491 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7492 return CP_ACCESS_TRAP_EL2
;
7496 arm_feature(env
, ARM_FEATURE_EL3
) &&
7497 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7498 return CP_ACCESS_TRAP_EL3
;
7500 return CP_ACCESS_OK
;
7503 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7505 return env
->pstate
& PSTATE_TCO
;
7508 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7510 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7513 static const ARMCPRegInfo mte_reginfo
[] = {
7514 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7515 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7516 .access
= PL1_RW
, .accessfn
= access_mte
,
7517 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7518 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7519 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7520 .access
= PL1_RW
, .accessfn
= access_mte
,
7521 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7522 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7523 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7524 .access
= PL2_RW
, .accessfn
= access_mte
,
7525 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7526 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7527 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7529 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7530 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7531 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7532 .access
= PL1_RW
, .accessfn
= access_mte
,
7533 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7534 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7535 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7536 .access
= PL1_RW
, .accessfn
= access_mte
,
7537 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7538 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7539 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7540 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7541 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7542 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7543 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7544 .type
= ARM_CP_NO_RAW
,
7545 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7546 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7547 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7548 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7550 .accessfn
= aa64_cacheop_poc_access
},
7551 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7552 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7554 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7555 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7556 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7557 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7559 .accessfn
= aa64_cacheop_poc_access
},
7560 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7561 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7563 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7564 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7565 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7567 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7568 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7569 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7571 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7572 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7573 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7575 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7576 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7577 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7579 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7582 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7583 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7584 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7585 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7588 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7589 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7590 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7591 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7593 .accessfn
= aa64_cacheop_poc_access
},
7594 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7595 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7596 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7598 .accessfn
= aa64_cacheop_poc_access
},
7599 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7600 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7601 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7603 .accessfn
= aa64_cacheop_poc_access
},
7604 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7605 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7606 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7608 .accessfn
= aa64_cacheop_poc_access
},
7609 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7610 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7611 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7613 .accessfn
= aa64_cacheop_poc_access
},
7614 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7615 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7616 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7618 .accessfn
= aa64_cacheop_poc_access
},
7619 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7620 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7621 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7623 .accessfn
= aa64_cacheop_poc_access
},
7624 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7625 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7626 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7628 .accessfn
= aa64_cacheop_poc_access
},
7629 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7630 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7631 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7632 #ifndef CONFIG_USER_ONLY
7633 /* Avoid overhead of an access check that always passes in user-mode */
7634 .accessfn
= aa64_zva_access
,
7638 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7639 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7640 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7641 #ifndef CONFIG_USER_ONLY
7642 /* Avoid overhead of an access check that always passes in user-mode */
7643 .accessfn
= aa64_zva_access
,
7649 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7652 uint64_t hcr
= arm_hcr_el2_eff(env
);
7653 int el
= arm_current_el(env
);
7655 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7656 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7657 if (hcr
& HCR_TGE
) {
7658 return CP_ACCESS_TRAP_EL2
;
7660 return CP_ACCESS_TRAP
;
7662 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7663 return CP_ACCESS_TRAP_EL2
;
7665 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7666 return CP_ACCESS_TRAP_EL2
;
7669 && arm_feature(env
, ARM_FEATURE_EL3
)
7670 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7671 return CP_ACCESS_TRAP_EL3
;
7673 return CP_ACCESS_OK
;
7676 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7677 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7678 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7679 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7680 .fgt
= FGT_SCXTNUM_EL0
,
7681 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7682 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7683 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7684 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7685 .fgt
= FGT_SCXTNUM_EL1
,
7686 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7687 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7688 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7689 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7690 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7691 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7692 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7694 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7697 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7700 if (arm_current_el(env
) == 2 &&
7701 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
7702 return CP_ACCESS_TRAP_EL3
;
7704 return CP_ACCESS_OK
;
7707 static const ARMCPRegInfo fgt_reginfo
[] = {
7708 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7709 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
7710 .access
= PL2_RW
, .accessfn
= access_fgt
,
7711 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
7712 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7713 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
7714 .access
= PL2_RW
, .accessfn
= access_fgt
,
7715 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
7716 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7717 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
7718 .access
= PL2_RW
, .accessfn
= access_fgt
,
7719 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
7720 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7721 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
7722 .access
= PL2_RW
, .accessfn
= access_fgt
,
7723 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
7724 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
7725 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
7726 .access
= PL2_RW
, .accessfn
= access_fgt
,
7727 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
7729 #endif /* TARGET_AARCH64 */
7731 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7734 int el
= arm_current_el(env
);
7737 uint64_t sctlr
= arm_sctlr(env
, el
);
7738 if (!(sctlr
& SCTLR_EnRCTX
)) {
7739 return CP_ACCESS_TRAP
;
7741 } else if (el
== 1) {
7742 uint64_t hcr
= arm_hcr_el2_eff(env
);
7744 return CP_ACCESS_TRAP_EL2
;
7747 return CP_ACCESS_OK
;
7750 static const ARMCPRegInfo predinv_reginfo
[] = {
7751 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7752 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7754 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7755 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7756 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7758 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7759 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7760 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7762 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7764 * Note the AArch32 opcodes have a different OPC1.
7766 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7767 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7769 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7770 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7771 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7773 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7774 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7775 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7777 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7780 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7782 /* Read the high 32 bits of the current CCSIDR */
7783 return extract64(ccsidr_read(env
, ri
), 32, 32);
7786 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7787 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7788 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7790 .accessfn
= access_tid4
,
7791 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7794 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7797 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7798 return CP_ACCESS_TRAP_EL2
;
7801 return CP_ACCESS_OK
;
7804 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7807 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7808 return access_aa64_tid3(env
, ri
, isread
);
7811 return CP_ACCESS_OK
;
7814 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7817 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7818 return CP_ACCESS_TRAP_EL2
;
7821 return CP_ACCESS_OK
;
7824 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7825 const ARMCPRegInfo
*ri
, bool isread
)
7828 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7829 * in v7A, not in v8A.
7831 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7832 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7833 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7834 return CP_ACCESS_TRAP_EL2
;
7836 return CP_ACCESS_OK
;
7839 static const ARMCPRegInfo jazelle_regs
[] = {
7841 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7842 .access
= PL1_R
, .accessfn
= access_jazelle
,
7843 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7845 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7846 .accessfn
= access_joscr_jmcr
,
7847 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7849 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7850 .accessfn
= access_joscr_jmcr
,
7851 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7854 static const ARMCPRegInfo contextidr_el2
= {
7855 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7856 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7858 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7861 static const ARMCPRegInfo vhe_reginfo
[] = {
7862 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7863 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7864 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7865 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7866 #ifndef CONFIG_USER_ONLY
7867 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7868 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7870 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7871 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7872 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7873 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7874 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7875 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7876 .resetfn
= gt_hv_timer_reset
,
7877 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7878 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7880 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7882 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7883 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7884 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7885 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7886 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7887 .access
= PL2_RW
, .accessfn
= e2h_access
,
7888 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7889 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7890 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7891 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7892 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7893 .access
= PL2_RW
, .accessfn
= e2h_access
,
7894 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7895 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7896 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7897 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7898 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7899 .access
= PL2_RW
, .accessfn
= e2h_access
,
7900 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7901 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7902 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7903 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7904 .access
= PL2_RW
, .accessfn
= e2h_access
,
7905 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7906 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7907 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7908 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7909 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7910 .access
= PL2_RW
, .accessfn
= e2h_access
,
7911 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7912 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7913 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7914 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7915 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7916 .access
= PL2_RW
, .accessfn
= e2h_access
,
7917 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7921 #ifndef CONFIG_USER_ONLY
7922 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7923 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
7924 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7925 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7926 .fgt
= FGT_ATS1E1RP
,
7927 .writefn
= ats_write64
},
7928 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
7929 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7930 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7931 .fgt
= FGT_ATS1E1WP
,
7932 .writefn
= ats_write64
},
7935 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7936 { .name
= "ATS1CPRP",
7937 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7938 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7939 .writefn
= ats_write
},
7940 { .name
= "ATS1CPWP",
7941 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7942 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7943 .writefn
= ats_write
},
7948 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7949 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7950 * is non-zero, which is never for ARMv7, optionally in ARMv8
7951 * and mandatorily for ARMv8.2 and up.
7952 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7953 * implementation is RAZ/WI we can ignore this detail, as we
7956 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7957 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7958 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7959 .access
= PL1_RW
, .accessfn
= access_tacr
,
7960 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7961 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7962 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7963 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7967 void register_cp_regs_for_features(ARMCPU
*cpu
)
7969 /* Register all the coprocessor registers based on feature bits */
7970 CPUARMState
*env
= &cpu
->env
;
7971 if (arm_feature(env
, ARM_FEATURE_M
)) {
7972 /* M profile has no coprocessor registers */
7976 define_arm_cp_regs(cpu
, cp_reginfo
);
7977 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7979 * Must go early as it is full of wildcards that may be
7980 * overridden by later definitions.
7982 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7985 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7986 /* The ID registers all have impdef reset values */
7987 ARMCPRegInfo v6_idregs
[] = {
7988 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7989 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7990 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7991 .accessfn
= access_aa32_tid3
,
7992 .resetvalue
= cpu
->isar
.id_pfr0
},
7994 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7995 * the value of the GIC field until after we define these regs.
7997 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7998 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7999 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8000 .accessfn
= access_aa32_tid3
,
8001 .readfn
= id_pfr1_read
,
8002 .writefn
= arm_cp_write_ignore
},
8003 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8004 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8005 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8006 .accessfn
= access_aa32_tid3
,
8007 .resetvalue
= cpu
->isar
.id_dfr0
},
8008 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8009 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8010 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8011 .accessfn
= access_aa32_tid3
,
8012 .resetvalue
= cpu
->id_afr0
},
8013 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8014 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8015 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8016 .accessfn
= access_aa32_tid3
,
8017 .resetvalue
= cpu
->isar
.id_mmfr0
},
8018 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8019 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8020 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8021 .accessfn
= access_aa32_tid3
,
8022 .resetvalue
= cpu
->isar
.id_mmfr1
},
8023 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8024 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8025 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8026 .accessfn
= access_aa32_tid3
,
8027 .resetvalue
= cpu
->isar
.id_mmfr2
},
8028 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8029 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8030 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8031 .accessfn
= access_aa32_tid3
,
8032 .resetvalue
= cpu
->isar
.id_mmfr3
},
8033 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8034 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8035 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8036 .accessfn
= access_aa32_tid3
,
8037 .resetvalue
= cpu
->isar
.id_isar0
},
8038 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8039 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8040 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8041 .accessfn
= access_aa32_tid3
,
8042 .resetvalue
= cpu
->isar
.id_isar1
},
8043 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8044 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8045 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8046 .accessfn
= access_aa32_tid3
,
8047 .resetvalue
= cpu
->isar
.id_isar2
},
8048 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8049 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8050 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8051 .accessfn
= access_aa32_tid3
,
8052 .resetvalue
= cpu
->isar
.id_isar3
},
8053 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8056 .accessfn
= access_aa32_tid3
,
8057 .resetvalue
= cpu
->isar
.id_isar4
},
8058 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8059 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8060 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8061 .accessfn
= access_aa32_tid3
,
8062 .resetvalue
= cpu
->isar
.id_isar5
},
8063 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8064 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8065 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8066 .accessfn
= access_aa32_tid3
,
8067 .resetvalue
= cpu
->isar
.id_mmfr4
},
8068 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8069 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8070 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8071 .accessfn
= access_aa32_tid3
,
8072 .resetvalue
= cpu
->isar
.id_isar6
},
8074 define_arm_cp_regs(cpu
, v6_idregs
);
8075 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8077 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8079 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8080 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8082 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8083 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8084 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8086 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8087 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8089 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8090 ARMCPRegInfo clidr
= {
8091 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8092 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8093 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8094 .accessfn
= access_tid4
,
8095 .fgt
= FGT_CLIDR_EL1
,
8096 .resetvalue
= cpu
->clidr
8098 define_one_arm_cp_reg(cpu
, &clidr
);
8099 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8100 define_debug_regs(cpu
);
8101 define_pmu_regs(cpu
);
8103 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8105 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8107 * v8 ID registers, which all have impdef reset values.
8108 * Note that within the ID register ranges the unused slots
8109 * must all RAZ, not UNDEF; future architecture versions may
8110 * define new registers here.
8111 * ID registers which are AArch64 views of the AArch32 ID registers
8112 * which already existed in v6 and v7 are handled elsewhere,
8116 ARMCPRegInfo v8_idregs
[] = {
8118 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8119 * emulation because we don't know the right value for the
8120 * GIC field until after we define these regs.
8122 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8123 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8125 #ifdef CONFIG_USER_ONLY
8126 .type
= ARM_CP_CONST
,
8127 .resetvalue
= cpu
->isar
.id_aa64pfr0
8129 .type
= ARM_CP_NO_RAW
,
8130 .accessfn
= access_aa64_tid3
,
8131 .readfn
= id_aa64pfr0_read
,
8132 .writefn
= arm_cp_write_ignore
8135 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8136 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8137 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8138 .accessfn
= access_aa64_tid3
,
8139 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8140 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8141 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8142 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8143 .accessfn
= access_aa64_tid3
,
8145 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8146 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8147 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8148 .accessfn
= access_aa64_tid3
,
8150 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8151 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8152 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8153 .accessfn
= access_aa64_tid3
,
8154 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8155 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8156 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8157 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8158 .accessfn
= access_aa64_tid3
,
8159 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8160 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8161 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8162 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8163 .accessfn
= access_aa64_tid3
,
8165 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8166 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8167 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8168 .accessfn
= access_aa64_tid3
,
8170 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8171 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8172 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8173 .accessfn
= access_aa64_tid3
,
8174 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8175 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8176 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8177 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8178 .accessfn
= access_aa64_tid3
,
8179 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8180 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8181 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8182 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8183 .accessfn
= access_aa64_tid3
,
8185 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8186 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8187 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8188 .accessfn
= access_aa64_tid3
,
8190 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8191 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8192 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8193 .accessfn
= access_aa64_tid3
,
8194 .resetvalue
= cpu
->id_aa64afr0
},
8195 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8196 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8197 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8198 .accessfn
= access_aa64_tid3
,
8199 .resetvalue
= cpu
->id_aa64afr1
},
8200 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8201 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8202 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8203 .accessfn
= access_aa64_tid3
,
8205 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8206 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8207 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8208 .accessfn
= access_aa64_tid3
,
8210 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8211 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8212 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8213 .accessfn
= access_aa64_tid3
,
8214 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8215 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8216 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8217 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8218 .accessfn
= access_aa64_tid3
,
8219 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8220 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8221 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8222 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8223 .accessfn
= access_aa64_tid3
,
8225 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8226 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8227 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8228 .accessfn
= access_aa64_tid3
,
8230 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8231 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8232 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8233 .accessfn
= access_aa64_tid3
,
8235 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8236 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8237 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8238 .accessfn
= access_aa64_tid3
,
8240 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8241 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8242 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8243 .accessfn
= access_aa64_tid3
,
8245 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8246 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8247 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8248 .accessfn
= access_aa64_tid3
,
8250 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8251 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8252 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8253 .accessfn
= access_aa64_tid3
,
8254 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8255 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8256 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8257 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8258 .accessfn
= access_aa64_tid3
,
8259 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8260 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8261 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8262 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8263 .accessfn
= access_aa64_tid3
,
8264 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8265 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8266 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8267 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8268 .accessfn
= access_aa64_tid3
,
8270 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8271 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8272 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8273 .accessfn
= access_aa64_tid3
,
8275 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8276 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8277 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8278 .accessfn
= access_aa64_tid3
,
8280 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8281 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8282 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8283 .accessfn
= access_aa64_tid3
,
8285 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8286 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8287 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8288 .accessfn
= access_aa64_tid3
,
8290 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8291 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8292 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8293 .accessfn
= access_aa64_tid3
,
8294 .resetvalue
= cpu
->isar
.mvfr0
},
8295 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8296 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8297 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8298 .accessfn
= access_aa64_tid3
,
8299 .resetvalue
= cpu
->isar
.mvfr1
},
8300 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8301 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8302 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8303 .accessfn
= access_aa64_tid3
,
8304 .resetvalue
= cpu
->isar
.mvfr2
},
8306 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8307 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8308 * as RAZ, since it is in the "reserved for future ID
8309 * registers, RAZ" part of the AArch32 encoding space.
8311 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8312 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8313 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8314 .accessfn
= access_aa64_tid3
,
8316 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8317 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8318 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8319 .accessfn
= access_aa64_tid3
,
8321 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8322 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8323 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8324 .accessfn
= access_aa64_tid3
,
8327 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8328 * they're also RAZ for AArch64, and in v8 are gradually
8329 * being filled with AArch64-view-of-AArch32-ID-register
8330 * for new ID registers.
8332 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8333 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8334 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8335 .accessfn
= access_aa64_tid3
,
8337 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8338 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8339 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8340 .accessfn
= access_aa64_tid3
,
8341 .resetvalue
= cpu
->isar
.id_pfr2
},
8342 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8343 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8344 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8345 .accessfn
= access_aa64_tid3
,
8346 .resetvalue
= cpu
->isar
.id_dfr1
},
8347 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8348 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8349 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8350 .accessfn
= access_aa64_tid3
,
8351 .resetvalue
= cpu
->isar
.id_mmfr5
},
8352 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8353 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8354 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8355 .accessfn
= access_aa64_tid3
,
8357 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8358 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8359 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8360 .fgt
= FGT_PMCEIDN_EL0
,
8361 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8362 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8363 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8364 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8365 .fgt
= FGT_PMCEIDN_EL0
,
8366 .resetvalue
= cpu
->pmceid0
},
8367 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8368 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8369 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8370 .fgt
= FGT_PMCEIDN_EL0
,
8371 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8372 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8373 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8374 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8375 .fgt
= FGT_PMCEIDN_EL0
,
8376 .resetvalue
= cpu
->pmceid1
},
8378 #ifdef CONFIG_USER_ONLY
8379 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8380 { .name
= "ID_AA64PFR0_EL1",
8381 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8382 R_ID_AA64PFR0_ADVSIMD_MASK
|
8383 R_ID_AA64PFR0_SVE_MASK
|
8384 R_ID_AA64PFR0_DIT_MASK
,
8385 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8386 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8387 { .name
= "ID_AA64PFR1_EL1",
8388 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8389 R_ID_AA64PFR1_SSBS_MASK
|
8390 R_ID_AA64PFR1_MTE_MASK
|
8391 R_ID_AA64PFR1_SME_MASK
},
8392 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8394 { .name
= "ID_AA64ZFR0_EL1",
8395 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8396 R_ID_AA64ZFR0_AES_MASK
|
8397 R_ID_AA64ZFR0_BITPERM_MASK
|
8398 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8399 R_ID_AA64ZFR0_SHA3_MASK
|
8400 R_ID_AA64ZFR0_SM4_MASK
|
8401 R_ID_AA64ZFR0_I8MM_MASK
|
8402 R_ID_AA64ZFR0_F32MM_MASK
|
8403 R_ID_AA64ZFR0_F64MM_MASK
},
8404 { .name
= "ID_AA64SMFR0_EL1",
8405 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8406 R_ID_AA64SMFR0_B16F32_MASK
|
8407 R_ID_AA64SMFR0_F16F32_MASK
|
8408 R_ID_AA64SMFR0_I8I32_MASK
|
8409 R_ID_AA64SMFR0_F64F64_MASK
|
8410 R_ID_AA64SMFR0_I16I64_MASK
|
8411 R_ID_AA64SMFR0_FA64_MASK
},
8412 { .name
= "ID_AA64MMFR0_EL1",
8413 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8414 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8415 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8416 { .name
= "ID_AA64MMFR1_EL1",
8417 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8418 { .name
= "ID_AA64MMFR2_EL1",
8419 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8420 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8422 { .name
= "ID_AA64DFR0_EL1",
8423 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8424 { .name
= "ID_AA64DFR1_EL1" },
8425 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8427 { .name
= "ID_AA64AFR*",
8429 { .name
= "ID_AA64ISAR0_EL1",
8430 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8431 R_ID_AA64ISAR0_SHA1_MASK
|
8432 R_ID_AA64ISAR0_SHA2_MASK
|
8433 R_ID_AA64ISAR0_CRC32_MASK
|
8434 R_ID_AA64ISAR0_ATOMIC_MASK
|
8435 R_ID_AA64ISAR0_RDM_MASK
|
8436 R_ID_AA64ISAR0_SHA3_MASK
|
8437 R_ID_AA64ISAR0_SM3_MASK
|
8438 R_ID_AA64ISAR0_SM4_MASK
|
8439 R_ID_AA64ISAR0_DP_MASK
|
8440 R_ID_AA64ISAR0_FHM_MASK
|
8441 R_ID_AA64ISAR0_TS_MASK
|
8442 R_ID_AA64ISAR0_RNDR_MASK
},
8443 { .name
= "ID_AA64ISAR1_EL1",
8444 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8445 R_ID_AA64ISAR1_APA_MASK
|
8446 R_ID_AA64ISAR1_API_MASK
|
8447 R_ID_AA64ISAR1_JSCVT_MASK
|
8448 R_ID_AA64ISAR1_FCMA_MASK
|
8449 R_ID_AA64ISAR1_LRCPC_MASK
|
8450 R_ID_AA64ISAR1_GPA_MASK
|
8451 R_ID_AA64ISAR1_GPI_MASK
|
8452 R_ID_AA64ISAR1_FRINTTS_MASK
|
8453 R_ID_AA64ISAR1_SB_MASK
|
8454 R_ID_AA64ISAR1_BF16_MASK
|
8455 R_ID_AA64ISAR1_DGH_MASK
|
8456 R_ID_AA64ISAR1_I8MM_MASK
},
8457 { .name
= "ID_AA64ISAR2_EL1",
8458 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8459 R_ID_AA64ISAR2_RPRES_MASK
|
8460 R_ID_AA64ISAR2_GPA3_MASK
|
8461 R_ID_AA64ISAR2_APA3_MASK
},
8462 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8465 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8467 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
8468 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8469 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8470 ARMCPRegInfo rvbar
= {
8471 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8472 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8474 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8476 define_one_arm_cp_reg(cpu
, &rvbar
);
8478 define_arm_cp_regs(cpu
, v8_idregs
);
8479 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8481 for (i
= 4; i
< 16; i
++) {
8483 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8484 * For pre-v8 cores there are RAZ patterns for these in
8485 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8486 * v8 extends the "must RAZ" part of the ID register space
8487 * to also cover c0, 0, c{8-15}, {0-7}.
8488 * These are STATE_AA32 because in the AArch64 sysreg space
8489 * c4-c7 is where the AArch64 ID registers live (and we've
8490 * already defined those in v8_idregs[]), and c8-c15 are not
8491 * "must RAZ" for AArch64.
8493 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8494 ARMCPRegInfo v8_aa32_raz_idregs
= {
8496 .state
= ARM_CP_STATE_AA32
,
8497 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8498 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8499 .accessfn
= access_aa64_tid3
,
8501 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8506 * Register the base EL2 cpregs.
8507 * Pre v8, these registers are implemented only as part of the
8508 * Virtualization Extensions (EL2 present). Beginning with v8,
8509 * if EL2 is missing but EL3 is enabled, mostly these become
8510 * RES0 from EL3, with some specific exceptions.
8512 if (arm_feature(env
, ARM_FEATURE_EL2
)
8513 || (arm_feature(env
, ARM_FEATURE_EL3
)
8514 && arm_feature(env
, ARM_FEATURE_V8
))) {
8515 uint64_t vmpidr_def
= mpidr_read_val(env
);
8516 ARMCPRegInfo vpidr_regs
[] = {
8517 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8518 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8519 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8520 .resetvalue
= cpu
->midr
,
8521 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8522 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8523 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8524 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8525 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8526 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8527 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8528 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8529 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8530 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8531 .resetvalue
= vmpidr_def
,
8532 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8533 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8534 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8535 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8536 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8537 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8538 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8541 * The only field of MDCR_EL2 that has a defined architectural reset
8542 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8544 ARMCPRegInfo mdcr_el2
= {
8545 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8546 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8547 .writefn
= mdcr_el2_write
,
8548 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8549 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8551 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8552 define_arm_cp_regs(cpu
, vpidr_regs
);
8553 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8554 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8555 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8557 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8558 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8560 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
8561 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8562 ARMCPRegInfo rvbar
[] = {
8564 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8565 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8567 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8569 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8570 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8572 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8575 define_arm_cp_regs(cpu
, rvbar
);
8579 /* Register the base EL3 cpregs. */
8580 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8581 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8582 ARMCPRegInfo el3_regs
[] = {
8583 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8584 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8586 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8588 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8589 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8591 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8592 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8593 .resetvalue
= cpu
->reset_sctlr
},
8596 define_arm_cp_regs(cpu
, el3_regs
);
8599 * The behaviour of NSACR is sufficiently various that we don't
8600 * try to describe it in a single reginfo:
8601 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8602 * reads as constant 0xc00 from NS EL1 and NS EL2
8603 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8604 * if v7 without EL3, register doesn't exist
8605 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8607 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8608 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8609 static const ARMCPRegInfo nsacr
= {
8610 .name
= "NSACR", .type
= ARM_CP_CONST
,
8611 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8612 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8615 define_one_arm_cp_reg(cpu
, &nsacr
);
8617 static const ARMCPRegInfo nsacr
= {
8619 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8620 .access
= PL3_RW
| PL1_R
,
8622 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8624 define_one_arm_cp_reg(cpu
, &nsacr
);
8627 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8628 static const ARMCPRegInfo nsacr
= {
8629 .name
= "NSACR", .type
= ARM_CP_CONST
,
8630 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8634 define_one_arm_cp_reg(cpu
, &nsacr
);
8638 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8639 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8640 /* PMSAv6 not implemented */
8641 assert(arm_feature(env
, ARM_FEATURE_V7
));
8642 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8643 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8645 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8648 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8649 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8650 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8651 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8652 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8655 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8656 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8658 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8659 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8661 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8662 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8664 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8665 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8667 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8668 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8670 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8671 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8673 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8674 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8676 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8677 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8679 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8680 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8682 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8683 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8685 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8686 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8688 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8689 define_arm_cp_regs(cpu
, jazelle_regs
);
8692 * Slightly awkwardly, the OMAP and StrongARM cores need all of
8693 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8694 * be read-only (ie write causes UNDEF exception).
8697 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8699 * Pre-v8 MIDR space.
8700 * Note that the MIDR isn't a simple constant register because
8701 * of the TI925 behaviour where writes to another register can
8702 * cause the MIDR value to change.
8704 * Unimplemented registers in the c15 0 0 0 space default to
8705 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8706 * and friends override accordingly.
8709 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8710 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8711 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8712 .readfn
= midr_read
,
8713 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8714 .type
= ARM_CP_OVERRIDE
},
8715 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8717 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8718 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8720 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8721 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8723 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8724 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8726 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8727 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8729 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8730 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8732 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8733 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8734 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8735 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8736 .fgt
= FGT_MIDR_EL1
,
8737 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8738 .readfn
= midr_read
},
8739 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
8740 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8741 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8742 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8743 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8744 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8746 .accessfn
= access_aa64_tid1
,
8747 .fgt
= FGT_REVIDR_EL1
,
8748 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8750 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
8751 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8752 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8753 .access
= PL1_R
, .resetvalue
= cpu
->midr
8755 ARMCPRegInfo id_cp_reginfo
[] = {
8756 /* These are common to v8 and pre-v8 */
8758 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8759 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8760 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8761 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8762 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8763 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8765 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8766 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8768 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8770 .accessfn
= access_aa32_tid1
,
8771 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8773 /* TLBTR is specific to VMSA */
8774 ARMCPRegInfo id_tlbtr_reginfo
= {
8776 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8778 .accessfn
= access_aa32_tid1
,
8779 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8781 /* MPUIR is specific to PMSA V6+ */
8782 ARMCPRegInfo id_mpuir_reginfo
= {
8784 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8785 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8786 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8788 /* HMPUIR is specific to PMSA V8 */
8789 ARMCPRegInfo id_hmpuir_reginfo
= {
8791 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
8792 .access
= PL2_R
, .type
= ARM_CP_CONST
,
8793 .resetvalue
= cpu
->pmsav8r_hdregion
8795 static const ARMCPRegInfo crn0_wi_reginfo
= {
8796 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8797 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8798 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8800 #ifdef CONFIG_USER_ONLY
8801 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8802 { .name
= "MIDR_EL1",
8803 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
8804 R_MIDR_EL1_PARTNUM_MASK
|
8805 R_MIDR_EL1_ARCHITECTURE_MASK
|
8806 R_MIDR_EL1_VARIANT_MASK
|
8807 R_MIDR_EL1_IMPLEMENTER_MASK
},
8808 { .name
= "REVIDR_EL1" },
8810 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8812 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8813 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8816 * Register the blanket "writes ignored" value first to cover the
8817 * whole space. Then update the specific ID registers to allow write
8818 * access, so that they ignore writes rather than causing them to
8821 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8822 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8823 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8825 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8826 id_cp_reginfo
[i
].access
= PL1_RW
;
8828 id_mpuir_reginfo
.access
= PL1_RW
;
8829 id_tlbtr_reginfo
.access
= PL1_RW
;
8831 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8832 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8833 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8834 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
8837 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8839 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8840 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8841 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8842 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
8843 arm_feature(env
, ARM_FEATURE_V8
)) {
8847 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8848 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
8849 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
8851 /* Register alias is only valid for first 32 indexes */
8852 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
8853 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
8854 uint8_t opc1
= extract32(i
, 4, 1);
8855 uint8_t opc2
= extract32(i
, 0, 1) << 2;
8857 tmp_string
= g_strdup_printf("PRBAR%u", i
);
8858 ARMCPRegInfo tmp_prbarn_reginfo
= {
8859 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
8860 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8861 .access
= PL1_RW
, .resetvalue
= 0,
8862 .accessfn
= access_tvm_trvm
,
8863 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8865 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
8868 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
8869 tmp_string
= g_strdup_printf("PRLAR%u", i
);
8870 ARMCPRegInfo tmp_prlarn_reginfo
= {
8871 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
8872 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8873 .access
= PL1_RW
, .resetvalue
= 0,
8874 .accessfn
= access_tvm_trvm
,
8875 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8877 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
8881 /* Register alias is only valid for first 32 indexes */
8882 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
8883 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
8884 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
8885 uint8_t opc2
= extract32(i
, 0, 1) << 2;
8887 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
8888 ARMCPRegInfo tmp_hprbarn_reginfo
= {
8890 .type
= ARM_CP_NO_RAW
,
8891 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8892 .access
= PL2_RW
, .resetvalue
= 0,
8893 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8895 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
8898 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
8899 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
8900 ARMCPRegInfo tmp_hprlarn_reginfo
= {
8902 .type
= ARM_CP_NO_RAW
,
8903 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8904 .access
= PL2_RW
, .resetvalue
= 0,
8905 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8907 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
8910 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8911 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8915 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8916 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8917 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8918 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8919 .fgt
= FGT_MPIDR_EL1
,
8920 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8922 #ifdef CONFIG_USER_ONLY
8923 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8924 { .name
= "MPIDR_EL1",
8925 .fixed_bits
= 0x0000000080000000 },
8927 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8929 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8932 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8933 ARMCPRegInfo auxcr_reginfo
[] = {
8934 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8935 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8936 .access
= PL1_RW
, .accessfn
= access_tacr
,
8937 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8938 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8939 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8940 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8942 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8943 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8944 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8947 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8948 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8949 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8953 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8955 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8956 * There are two flavours:
8957 * (1) older 32-bit only cores have a simple 32-bit CBAR
8958 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8959 * 32-bit register visible to AArch32 at a different encoding
8960 * to the "flavour 1" register and with the bits rearranged to
8961 * be able to squash a 64-bit address into the 32-bit view.
8962 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8963 * in future if we support AArch32-only configs of some of the
8964 * AArch64 cores we might need to add a specific feature flag
8965 * to indicate cores with "flavour 2" CBAR.
8967 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8968 /* 32 bit view is [31:18] 0...0 [43:32]. */
8969 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8970 | extract64(cpu
->reset_cbar
, 32, 12);
8971 ARMCPRegInfo cbar_reginfo
[] = {
8973 .type
= ARM_CP_CONST
,
8974 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8975 .access
= PL1_R
, .resetvalue
= cbar32
},
8976 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8977 .type
= ARM_CP_CONST
,
8978 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8979 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8981 /* We don't implement a r/w 64 bit CBAR currently */
8982 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8983 define_arm_cp_regs(cpu
, cbar_reginfo
);
8985 ARMCPRegInfo cbar
= {
8987 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8988 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8989 .fieldoffset
= offsetof(CPUARMState
,
8990 cp15
.c15_config_base_address
)
8992 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8993 cbar
.access
= PL1_R
;
8994 cbar
.fieldoffset
= 0;
8995 cbar
.type
= ARM_CP_CONST
;
8997 define_one_arm_cp_reg(cpu
, &cbar
);
9001 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9002 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9003 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9004 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9005 .access
= PL1_RW
, .writefn
= vbar_write
,
9006 .fgt
= FGT_VBAR_EL1
,
9007 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9008 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9011 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9014 /* Generic registers whose values depend on the implementation */
9016 ARMCPRegInfo sctlr
= {
9017 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9018 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9019 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9020 .fgt
= FGT_SCTLR_EL1
,
9021 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9022 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9023 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9024 .raw_writefn
= raw_write
,
9026 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9028 * Normally we would always end the TB on an SCTLR write, but Linux
9029 * arch/arm/mach-pxa/sleep.S expects two instructions following
9030 * an MMU enable to execute from cache. Imitate this behaviour.
9032 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9034 define_one_arm_cp_reg(cpu
, &sctlr
);
9036 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9037 arm_feature(env
, ARM_FEATURE_V8
)) {
9038 ARMCPRegInfo vsctlr
= {
9039 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9040 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9041 .access
= PL2_RW
, .resetvalue
= 0x0,
9042 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9044 define_one_arm_cp_reg(cpu
, &vsctlr
);
9048 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9049 define_arm_cp_regs(cpu
, lor_reginfo
);
9051 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9052 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9054 #ifndef CONFIG_USER_ONLY
9055 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9056 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9058 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9059 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9062 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9063 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9066 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9067 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9069 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9070 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9072 if (cpu_isar_feature(any_ras
, cpu
)) {
9073 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9076 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9077 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9078 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9080 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9081 define_arm_cp_regs(cpu
, vhe_reginfo
);
9084 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9085 define_arm_cp_regs(cpu
, zcr_reginfo
);
9088 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9089 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9092 #ifdef TARGET_AARCH64
9093 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9094 define_arm_cp_regs(cpu
, sme_reginfo
);
9096 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9097 define_arm_cp_regs(cpu
, pauth_reginfo
);
9099 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9100 define_arm_cp_regs(cpu
, rndr_reginfo
);
9102 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9103 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9105 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9106 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9108 #ifndef CONFIG_USER_ONLY
9109 /* Data Cache clean instructions up to PoP */
9110 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9111 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9113 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9114 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9117 #endif /*CONFIG_USER_ONLY*/
9120 * If full MTE is enabled, add all of the system registers.
9121 * If only "instructions available at EL0" are enabled,
9122 * then define only a RAZ/WI version of PSTATE.TCO.
9124 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9125 define_arm_cp_regs(cpu
, mte_reginfo
);
9126 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9127 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9128 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9129 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9132 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9133 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9136 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9137 define_arm_cp_regs(cpu
, fgt_reginfo
);
9141 if (cpu_isar_feature(any_predinv
, cpu
)) {
9142 define_arm_cp_regs(cpu
, predinv_reginfo
);
9145 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9146 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9149 #ifndef CONFIG_USER_ONLY
9151 * Register redirections and aliases must be done last,
9152 * after the registers from the other extensions have been defined.
9154 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9155 define_arm_vh_e2h_redirects_aliases(cpu
);
9160 /* Sort alphabetically by type name, except for "any". */
9161 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
9163 ObjectClass
*class_a
= (ObjectClass
*)a
;
9164 ObjectClass
*class_b
= (ObjectClass
*)b
;
9165 const char *name_a
, *name_b
;
9167 name_a
= object_class_get_name(class_a
);
9168 name_b
= object_class_get_name(class_b
);
9169 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
9171 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
9174 return strcmp(name_a
, name_b
);
9178 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
9180 ObjectClass
*oc
= data
;
9181 CPUClass
*cc
= CPU_CLASS(oc
);
9182 const char *typename
;
9185 typename
= object_class_get_name(oc
);
9186 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9187 if (cc
->deprecation_note
) {
9188 qemu_printf(" %s (deprecated)\n", name
);
9190 qemu_printf(" %s\n", name
);
9195 void arm_cpu_list(void)
9199 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9200 list
= g_slist_sort(list
, arm_cpu_list_compare
);
9201 qemu_printf("Available CPUs:\n");
9202 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
9206 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
9208 ObjectClass
*oc
= data
;
9209 CpuDefinitionInfoList
**cpu_list
= user_data
;
9210 CpuDefinitionInfo
*info
;
9211 const char *typename
;
9213 typename
= object_class_get_name(oc
);
9214 info
= g_malloc0(sizeof(*info
));
9215 info
->name
= g_strndup(typename
,
9216 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9217 info
->q_typename
= g_strdup(typename
);
9219 QAPI_LIST_PREPEND(*cpu_list
, info
);
9222 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
9224 CpuDefinitionInfoList
*cpu_list
= NULL
;
9227 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9228 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
9235 * Private utility function for define_one_arm_cp_reg_with_opaque():
9236 * add a single reginfo struct to the hash table.
9238 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9239 void *opaque
, CPState state
,
9240 CPSecureState secstate
,
9241 int crm
, int opc1
, int opc2
,
9244 CPUARMState
*env
= &cpu
->env
;
9247 bool is64
= r
->type
& ARM_CP_64BIT
;
9248 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9254 case ARM_CP_STATE_AA32
:
9255 /* We assume it is a cp15 register if the .cp field is left unset. */
9256 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9259 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9261 case ARM_CP_STATE_AA64
:
9263 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9264 * cp == 0 as equivalent to the value for "standard guest-visible
9265 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9266 * in their AArch64 view (the .cp value may be non-zero for the
9267 * benefit of the AArch32 view).
9269 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9270 cp
= CP_REG_ARM64_SYSREG_CP
;
9272 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9275 g_assert_not_reached();
9278 /* Overriding of an existing definition must be explicitly requested. */
9279 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9280 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9282 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9287 * Eliminate registers that are not present because the EL is missing.
9288 * Doing this here makes it easier to put all registers for a given
9289 * feature into the same ARMCPRegInfo array and define them all at once.
9292 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9294 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9295 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9297 int min_el
= ctz32(r
->access
) / 2;
9298 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9299 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9302 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9305 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9307 if ((r
->access
& max_el
) == 0) {
9312 /* Combine cpreg and name into one allocation. */
9313 name_len
= strlen(name
) + 1;
9314 r2
= g_malloc(sizeof(*r2
) + name_len
);
9316 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9319 * Update fields to match the instantiation, overwiting wildcards
9320 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9327 r2
->secure
= secstate
;
9329 r2
->opaque
= opaque
;
9333 /* This should not have been a very special register to begin. */
9334 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9335 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9337 * Set the special function to CONST, retaining the other flags.
9338 * This is important for e.g. ARM_CP_SVE so that we still
9339 * take the SVE trap if CPTR_EL3.EZ == 0.
9341 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9343 * Usually, these registers become RES0, but there are a few
9344 * special cases like VPIDR_EL2 which have a constant non-zero
9345 * value with writes ignored.
9347 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9351 * ARM_CP_CONST has precedence, so removing the callbacks and
9352 * offsets are not strictly necessary, but it is potentially
9353 * less confusing to debug later.
9357 r2
->raw_readfn
= NULL
;
9358 r2
->raw_writefn
= NULL
;
9360 r2
->fieldoffset
= 0;
9361 r2
->bank_fieldoffsets
[0] = 0;
9362 r2
->bank_fieldoffsets
[1] = 0;
9364 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9368 * Register is banked (using both entries in array).
9369 * Overwriting fieldoffset as the array is only used to define
9370 * banked registers but later only fieldoffset is used.
9372 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9374 if (state
== ARM_CP_STATE_AA32
) {
9377 * If the register is banked then we don't need to migrate or
9378 * reset the 32-bit instance in certain cases:
9380 * 1) If the register has both 32-bit and 64-bit instances
9381 * then we can count on the 64-bit instance taking care
9382 * of the non-secure bank.
9383 * 2) If ARMv8 is enabled then we can count on a 64-bit
9384 * version taking care of the secure bank. This requires
9385 * that separate 32 and 64-bit definitions are provided.
9387 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9388 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9389 r2
->type
|= ARM_CP_ALIAS
;
9391 } else if ((secstate
!= r
->secure
) && !ns
) {
9393 * The register is not banked so we only want to allow
9394 * migration of the non-secure instance.
9396 r2
->type
|= ARM_CP_ALIAS
;
9399 if (HOST_BIG_ENDIAN
&&
9400 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9401 r2
->fieldoffset
+= sizeof(uint32_t);
9407 * By convention, for wildcarded registers only the first
9408 * entry is used for migration; the others are marked as
9409 * ALIAS so we don't try to transfer the register
9410 * multiple times. Special registers (ie NOP/WFI) are
9411 * never migratable and not even raw-accessible.
9413 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9414 r2
->type
|= ARM_CP_NO_RAW
;
9416 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9417 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9418 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9419 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9423 * Check that raw accesses are either forbidden or handled. Note that
9424 * we can't assert this earlier because the setup of fieldoffset for
9425 * banked registers has to be done first.
9427 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9428 assert(!raw_accessors_invalid(r2
));
9431 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9435 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9436 const ARMCPRegInfo
*r
, void *opaque
)
9439 * Define implementations of coprocessor registers.
9440 * We store these in a hashtable because typically
9441 * there are less than 150 registers in a space which
9442 * is 16*16*16*8*8 = 262144 in size.
9443 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9444 * If a register is defined twice then the second definition is
9445 * used, so this can be used to define some generic registers and
9446 * then override them with implementation specific variations.
9447 * At least one of the original and the second definition should
9448 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9449 * against accidental use.
9451 * The state field defines whether the register is to be
9452 * visible in the AArch32 or AArch64 execution state. If the
9453 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9454 * reginfo structure for the AArch32 view, which sees the lower
9455 * 32 bits of the 64 bit register.
9457 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9458 * be wildcarded. AArch64 registers are always considered to be 64
9459 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9460 * the register, if any.
9462 int crm
, opc1
, opc2
;
9463 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9464 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9465 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9466 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9467 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9468 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9471 /* 64 bit registers have only CRm and Opc1 fields */
9472 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9473 /* op0 only exists in the AArch64 encodings */
9474 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9475 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9476 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9478 * This API is only for Arm's system coprocessors (14 and 15) or
9479 * (M-profile or v7A-and-earlier only) for implementation defined
9480 * coprocessors in the range 0..7. Our decode assumes this, since
9481 * 8..13 can be used for other insns including VFP and Neon. See
9482 * valid_cp() in translate.c. Assert here that we haven't tried
9483 * to use an invalid coprocessor number.
9486 case ARM_CP_STATE_BOTH
:
9487 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9492 case ARM_CP_STATE_AA32
:
9493 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9494 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9495 assert(r
->cp
>= 14 && r
->cp
<= 15);
9497 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9500 case ARM_CP_STATE_AA64
:
9501 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9504 g_assert_not_reached();
9507 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9508 * encodes a minimum access level for the register. We roll this
9509 * runtime check into our general permission check code, so check
9510 * here that the reginfo's specified permissions are strict enough
9511 * to encompass the generic architectural permission check.
9513 if (r
->state
!= ARM_CP_STATE_AA32
) {
9514 CPAccessRights mask
;
9517 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9518 mask
= PL0U_R
| PL1_RW
;
9538 /* min_EL EL1, secure mode only (we don't check the latter) */
9542 /* broken reginfo with out-of-range opc1 */
9543 g_assert_not_reached();
9545 /* assert our permissions are not too lax (stricter is fine) */
9546 assert((r
->access
& ~mask
) == 0);
9550 * Check that the register definition has enough info to handle
9551 * reads and writes if they are permitted.
9553 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9554 if (r
->access
& PL3_R
) {
9555 assert((r
->fieldoffset
||
9556 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9559 if (r
->access
& PL3_W
) {
9560 assert((r
->fieldoffset
||
9561 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9566 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9567 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9568 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9569 for (state
= ARM_CP_STATE_AA32
;
9570 state
<= ARM_CP_STATE_AA64
; state
++) {
9571 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9574 if (state
== ARM_CP_STATE_AA32
) {
9576 * Under AArch32 CP registers can be common
9577 * (same for secure and non-secure world) or banked.
9581 switch (r
->secure
) {
9582 case ARM_CP_SECSTATE_S
:
9583 case ARM_CP_SECSTATE_NS
:
9584 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9585 r
->secure
, crm
, opc1
, opc2
,
9588 case ARM_CP_SECSTATE_BOTH
:
9589 name
= g_strdup_printf("%s_S", r
->name
);
9590 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9592 crm
, opc1
, opc2
, name
);
9594 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9596 crm
, opc1
, opc2
, r
->name
);
9599 g_assert_not_reached();
9603 * AArch64 registers get mapped to non-secure instance
9606 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9608 crm
, opc1
, opc2
, r
->name
);
9616 /* Define a whole list of registers */
9617 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
9618 void *opaque
, size_t len
)
9621 for (i
= 0; i
< len
; ++i
) {
9622 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
9627 * Modify ARMCPRegInfo for access from userspace.
9629 * This is a data driven modification directed by
9630 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9631 * user-space cannot alter any values and dynamic values pertaining to
9632 * execution state are hidden from user space view anyway.
9634 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
9635 const ARMCPRegUserSpaceInfo
*mods
,
9638 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9639 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9640 GPatternSpec
*pat
= NULL
;
9643 pat
= g_pattern_spec_new(m
->name
);
9645 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9646 ARMCPRegInfo
*r
= regs
+ ri
;
9648 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9649 r
->type
= ARM_CP_CONST
;
9653 } else if (strcmp(r
->name
, m
->name
) == 0) {
9654 r
->type
= ARM_CP_CONST
;
9656 r
->resetvalue
&= m
->exported_bits
;
9657 r
->resetvalue
|= m
->fixed_bits
;
9662 g_pattern_spec_free(pat
);
9667 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9669 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9672 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9675 /* Helper coprocessor write function for write-ignore registers */
9678 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9680 /* Helper coprocessor write function for read-as-zero registers */
9684 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9686 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9689 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9692 * Return true if it is not valid for us to switch to
9693 * this CPU mode (ie all the UNPREDICTABLE cases in
9694 * the ARM ARM CPSRWriteByInstr pseudocode).
9697 /* Changes to or from Hyp via MSR and CPS are illegal. */
9698 if (write_type
== CPSRWriteByInstr
&&
9699 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9700 mode
== ARM_CPU_MODE_HYP
)) {
9705 case ARM_CPU_MODE_USR
:
9707 case ARM_CPU_MODE_SYS
:
9708 case ARM_CPU_MODE_SVC
:
9709 case ARM_CPU_MODE_ABT
:
9710 case ARM_CPU_MODE_UND
:
9711 case ARM_CPU_MODE_IRQ
:
9712 case ARM_CPU_MODE_FIQ
:
9714 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
9715 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9718 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9719 * and CPS are treated as illegal mode changes.
9721 if (write_type
== CPSRWriteByInstr
&&
9722 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9723 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9727 case ARM_CPU_MODE_HYP
:
9728 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9729 case ARM_CPU_MODE_MON
:
9730 return arm_current_el(env
) < 3;
9736 uint32_t cpsr_read(CPUARMState
*env
)
9739 ZF
= (env
->ZF
== 0);
9740 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9741 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9742 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9743 | ((env
->condexec_bits
& 0xfc) << 8)
9744 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9747 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9748 CPSRWriteType write_type
)
9750 uint32_t changed_daif
;
9751 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9752 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9754 if (mask
& CPSR_NZCV
) {
9755 env
->ZF
= (~val
) & CPSR_Z
;
9757 env
->CF
= (val
>> 29) & 1;
9758 env
->VF
= (val
<< 3) & 0x80000000;
9760 if (mask
& CPSR_Q
) {
9761 env
->QF
= ((val
& CPSR_Q
) != 0);
9763 if (mask
& CPSR_T
) {
9764 env
->thumb
= ((val
& CPSR_T
) != 0);
9766 if (mask
& CPSR_IT_0_1
) {
9767 env
->condexec_bits
&= ~3;
9768 env
->condexec_bits
|= (val
>> 25) & 3;
9770 if (mask
& CPSR_IT_2_7
) {
9771 env
->condexec_bits
&= 3;
9772 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9774 if (mask
& CPSR_GE
) {
9775 env
->GE
= (val
>> 16) & 0xf;
9779 * In a V7 implementation that includes the security extensions but does
9780 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9781 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9782 * bits respectively.
9784 * In a V8 implementation, it is permitted for privileged software to
9785 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9787 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9788 arm_feature(env
, ARM_FEATURE_EL3
) &&
9789 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9790 !arm_is_secure(env
)) {
9792 changed_daif
= (env
->daif
^ val
) & mask
;
9794 if (changed_daif
& CPSR_A
) {
9796 * Check to see if we are allowed to change the masking of async
9797 * abort exceptions from a non-secure state.
9799 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9800 qemu_log_mask(LOG_GUEST_ERROR
,
9801 "Ignoring attempt to switch CPSR_A flag from "
9802 "non-secure world with SCR.AW bit clear\n");
9807 if (changed_daif
& CPSR_F
) {
9809 * Check to see if we are allowed to change the masking of FIQ
9810 * exceptions from a non-secure state.
9812 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9813 qemu_log_mask(LOG_GUEST_ERROR
,
9814 "Ignoring attempt to switch CPSR_F flag from "
9815 "non-secure world with SCR.FW bit clear\n");
9820 * Check whether non-maskable FIQ (NMFI) support is enabled.
9821 * If this bit is set software is not allowed to mask
9822 * FIQs, but is allowed to set CPSR_F to 0.
9824 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9826 qemu_log_mask(LOG_GUEST_ERROR
,
9827 "Ignoring attempt to enable CPSR_F flag "
9828 "(non-maskable FIQ [NMFI] support enabled)\n");
9834 env
->daif
&= ~(CPSR_AIF
& mask
);
9835 env
->daif
|= val
& CPSR_AIF
& mask
;
9837 if (write_type
!= CPSRWriteRaw
&&
9838 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9839 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9841 * Note that we can only get here in USR mode if this is a
9842 * gdb stub write; for this case we follow the architectural
9843 * behaviour for guest writes in USR mode of ignoring an attempt
9844 * to switch mode. (Those are caught by translate.c for writes
9845 * triggered by guest instructions.)
9848 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9850 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9851 * v7, and has defined behaviour in v8:
9852 * + leave CPSR.M untouched
9853 * + allow changes to the other CPSR fields
9855 * For user changes via the GDB stub, we don't set PSTATE.IL,
9856 * as this would be unnecessarily harsh for a user error.
9859 if (write_type
!= CPSRWriteByGDBStub
&&
9860 arm_feature(env
, ARM_FEATURE_V8
)) {
9864 qemu_log_mask(LOG_GUEST_ERROR
,
9865 "Illegal AArch32 mode switch attempt from %s to %s\n",
9866 aarch32_mode_name(env
->uncached_cpsr
),
9867 aarch32_mode_name(val
));
9869 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9870 write_type
== CPSRWriteExceptionReturn
?
9871 "Exception return from AArch32" :
9872 "AArch32 mode switch from",
9873 aarch32_mode_name(env
->uncached_cpsr
),
9874 aarch32_mode_name(val
), env
->regs
[15]);
9875 switch_mode(env
, val
& CPSR_M
);
9878 mask
&= ~CACHED_CPSR_BITS
;
9879 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9880 if (rebuild_hflags
) {
9881 arm_rebuild_hflags(env
);
9885 /* Sign/zero extend */
9886 uint32_t HELPER(sxtb16
)(uint32_t x
)
9889 res
= (uint16_t)(int8_t)x
;
9890 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9894 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9897 * Take a division-by-zero exception if necessary; otherwise return
9898 * to get the usual non-trapping division behaviour (result of 0)
9900 if (arm_feature(env
, ARM_FEATURE_M
)
9901 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9902 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9906 uint32_t HELPER(uxtb16
)(uint32_t x
)
9909 res
= (uint16_t)(uint8_t)x
;
9910 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9914 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9917 handle_possible_div0_trap(env
, GETPC());
9920 if (num
== INT_MIN
&& den
== -1) {
9926 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9929 handle_possible_div0_trap(env
, GETPC());
9935 uint32_t HELPER(rbit
)(uint32_t x
)
9940 #ifdef CONFIG_USER_ONLY
9942 static void switch_mode(CPUARMState
*env
, int mode
)
9944 ARMCPU
*cpu
= env_archcpu(env
);
9946 if (mode
!= ARM_CPU_MODE_USR
) {
9947 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9951 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9952 uint32_t cur_el
, bool secure
)
9957 void aarch64_sync_64_to_32(CPUARMState
*env
)
9959 g_assert_not_reached();
9964 static void switch_mode(CPUARMState
*env
, int mode
)
9969 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9970 if (mode
== old_mode
) {
9974 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9975 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9976 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9977 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9978 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9979 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9982 i
= bank_number(old_mode
);
9983 env
->banked_r13
[i
] = env
->regs
[13];
9984 env
->banked_spsr
[i
] = env
->spsr
;
9986 i
= bank_number(mode
);
9987 env
->regs
[13] = env
->banked_r13
[i
];
9988 env
->spsr
= env
->banked_spsr
[i
];
9990 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9991 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9995 * Physical Interrupt Target EL Lookup Table
9997 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9999 * The below multi-dimensional table is used for looking up the target
10000 * exception level given numerous condition criteria. Specifically, the
10001 * target EL is based on SCR and HCR routing controls as well as the
10002 * currently executing EL and secure state.
10005 * target_el_table[2][2][2][2][2][4]
10006 * | | | | | +--- Current EL
10007 * | | | | +------ Non-secure(0)/Secure(1)
10008 * | | | +--------- HCR mask override
10009 * | | +------------ SCR exec state control
10010 * | +--------------- SCR mask override
10011 * +------------------ 32-bit(0)/64-bit(1) EL3
10013 * The table values are as such:
10015 * -1 = Cannot occur
10017 * The ARM ARM target EL table includes entries indicating that an "exception
10018 * is not taken". The two cases where this is applicable are:
10019 * 1) An exception is taken from EL3 but the SCR does not have the exception
10021 * 2) An exception is taken from EL2 but the HCR does not have the exception
10023 * In these two cases, the below table contain a target of EL1. This value is
10024 * returned as it is expected that the consumer of the table data will check
10025 * for "target EL >= current EL" to ensure the exception is not taken.
10029 * BIT IRQ IMO Non-secure Secure
10030 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10032 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10033 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10034 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10035 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10036 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10037 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10038 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10039 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10040 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10041 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10042 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10043 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10044 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10045 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10046 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10047 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10048 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10052 * Determine the target EL for physical exceptions
10054 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10055 uint32_t cur_el
, bool secure
)
10057 CPUARMState
*env
= cs
->env_ptr
;
10062 /* Is the highest EL AArch64? */
10063 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10066 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10067 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10070 * Either EL2 is the highest EL (and so the EL2 register width
10071 * is given by is64); or there is no EL2 or EL3, in which case
10072 * the value of 'rw' does not affect the table lookup anyway.
10077 hcr_el2
= arm_hcr_el2_eff(env
);
10078 switch (excp_idx
) {
10080 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10081 hcr
= hcr_el2
& HCR_IMO
;
10084 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10085 hcr
= hcr_el2
& HCR_FMO
;
10088 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10089 hcr
= hcr_el2
& HCR_AMO
;
10094 * For these purposes, TGE and AMO/IMO/FMO both force the
10095 * interrupt to EL2. Fold TGE into the bit extracted above.
10097 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10099 /* Perform a table-lookup for the target EL given the current state */
10100 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10102 assert(target_el
> 0);
10107 void arm_log_exception(CPUState
*cs
)
10109 int idx
= cs
->exception_index
;
10111 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10112 const char *exc
= NULL
;
10113 static const char * const excnames
[] = {
10114 [EXCP_UDEF
] = "Undefined Instruction",
10115 [EXCP_SWI
] = "SVC",
10116 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10117 [EXCP_DATA_ABORT
] = "Data Abort",
10118 [EXCP_IRQ
] = "IRQ",
10119 [EXCP_FIQ
] = "FIQ",
10120 [EXCP_BKPT
] = "Breakpoint",
10121 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10122 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10123 [EXCP_HVC
] = "Hypervisor Call",
10124 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10125 [EXCP_SMC
] = "Secure Monitor Call",
10126 [EXCP_VIRQ
] = "Virtual IRQ",
10127 [EXCP_VFIQ
] = "Virtual FIQ",
10128 [EXCP_SEMIHOST
] = "Semihosting call",
10129 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10130 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10131 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10132 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10133 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10134 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10135 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10136 [EXCP_VSERR
] = "Virtual SERR",
10139 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10140 exc
= excnames
[idx
];
10145 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10146 idx
, exc
, cs
->cpu_index
);
10151 * Function used to synchronize QEMU's AArch64 register set with AArch32
10152 * register set. This is necessary when switching between AArch32 and AArch64
10155 void aarch64_sync_32_to_64(CPUARMState
*env
)
10158 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10160 /* We can blanket copy R[0:7] to X[0:7] */
10161 for (i
= 0; i
< 8; i
++) {
10162 env
->xregs
[i
] = env
->regs
[i
];
10166 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10167 * Otherwise, they come from the banked user regs.
10169 if (mode
== ARM_CPU_MODE_FIQ
) {
10170 for (i
= 8; i
< 13; i
++) {
10171 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10174 for (i
= 8; i
< 13; i
++) {
10175 env
->xregs
[i
] = env
->regs
[i
];
10180 * Registers x13-x23 are the various mode SP and FP registers. Registers
10181 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10182 * from the mode banked register.
10184 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10185 env
->xregs
[13] = env
->regs
[13];
10186 env
->xregs
[14] = env
->regs
[14];
10188 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10189 /* HYP is an exception in that it is copied from r14 */
10190 if (mode
== ARM_CPU_MODE_HYP
) {
10191 env
->xregs
[14] = env
->regs
[14];
10193 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10197 if (mode
== ARM_CPU_MODE_HYP
) {
10198 env
->xregs
[15] = env
->regs
[13];
10200 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10203 if (mode
== ARM_CPU_MODE_IRQ
) {
10204 env
->xregs
[16] = env
->regs
[14];
10205 env
->xregs
[17] = env
->regs
[13];
10207 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10208 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10211 if (mode
== ARM_CPU_MODE_SVC
) {
10212 env
->xregs
[18] = env
->regs
[14];
10213 env
->xregs
[19] = env
->regs
[13];
10215 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10216 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10219 if (mode
== ARM_CPU_MODE_ABT
) {
10220 env
->xregs
[20] = env
->regs
[14];
10221 env
->xregs
[21] = env
->regs
[13];
10223 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10224 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10227 if (mode
== ARM_CPU_MODE_UND
) {
10228 env
->xregs
[22] = env
->regs
[14];
10229 env
->xregs
[23] = env
->regs
[13];
10231 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10232 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10236 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10237 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10238 * FIQ bank for r8-r14.
10240 if (mode
== ARM_CPU_MODE_FIQ
) {
10241 for (i
= 24; i
< 31; i
++) {
10242 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10245 for (i
= 24; i
< 29; i
++) {
10246 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10248 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10249 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10252 env
->pc
= env
->regs
[15];
10256 * Function used to synchronize QEMU's AArch32 register set with AArch64
10257 * register set. This is necessary when switching between AArch32 and AArch64
10260 void aarch64_sync_64_to_32(CPUARMState
*env
)
10263 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10265 /* We can blanket copy X[0:7] to R[0:7] */
10266 for (i
= 0; i
< 8; i
++) {
10267 env
->regs
[i
] = env
->xregs
[i
];
10271 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10272 * Otherwise, we copy x8-x12 into the banked user regs.
10274 if (mode
== ARM_CPU_MODE_FIQ
) {
10275 for (i
= 8; i
< 13; i
++) {
10276 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10279 for (i
= 8; i
< 13; i
++) {
10280 env
->regs
[i
] = env
->xregs
[i
];
10285 * Registers r13 & r14 depend on the current mode.
10286 * If we are in a given mode, we copy the corresponding x registers to r13
10287 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10290 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10291 env
->regs
[13] = env
->xregs
[13];
10292 env
->regs
[14] = env
->xregs
[14];
10294 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10297 * HYP is an exception in that it does not have its own banked r14 but
10298 * shares the USR r14
10300 if (mode
== ARM_CPU_MODE_HYP
) {
10301 env
->regs
[14] = env
->xregs
[14];
10303 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10307 if (mode
== ARM_CPU_MODE_HYP
) {
10308 env
->regs
[13] = env
->xregs
[15];
10310 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10313 if (mode
== ARM_CPU_MODE_IRQ
) {
10314 env
->regs
[14] = env
->xregs
[16];
10315 env
->regs
[13] = env
->xregs
[17];
10317 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10318 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10321 if (mode
== ARM_CPU_MODE_SVC
) {
10322 env
->regs
[14] = env
->xregs
[18];
10323 env
->regs
[13] = env
->xregs
[19];
10325 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10326 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10329 if (mode
== ARM_CPU_MODE_ABT
) {
10330 env
->regs
[14] = env
->xregs
[20];
10331 env
->regs
[13] = env
->xregs
[21];
10333 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10334 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10337 if (mode
== ARM_CPU_MODE_UND
) {
10338 env
->regs
[14] = env
->xregs
[22];
10339 env
->regs
[13] = env
->xregs
[23];
10341 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10342 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10346 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10347 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10348 * FIQ bank for r8-r14.
10350 if (mode
== ARM_CPU_MODE_FIQ
) {
10351 for (i
= 24; i
< 31; i
++) {
10352 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10355 for (i
= 24; i
< 29; i
++) {
10356 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10358 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10359 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10362 env
->regs
[15] = env
->pc
;
10365 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10366 uint32_t mask
, uint32_t offset
,
10371 /* Change the CPU state so as to actually take the exception. */
10372 switch_mode(env
, new_mode
);
10375 * For exceptions taken to AArch32 we must clear the SS bit in both
10376 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10378 env
->pstate
&= ~PSTATE_SS
;
10379 env
->spsr
= cpsr_read(env
);
10380 /* Clear IT bits. */
10381 env
->condexec_bits
= 0;
10382 /* Switch to the new mode, and to the correct instruction set. */
10383 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10385 /* This must be after mode switching. */
10386 new_el
= arm_current_el(env
);
10388 /* Set new mode endianness */
10389 env
->uncached_cpsr
&= ~CPSR_E
;
10390 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10391 env
->uncached_cpsr
|= CPSR_E
;
10393 /* J and IL must always be cleared for exception entry */
10394 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10397 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10398 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10399 env
->uncached_cpsr
|= CPSR_SSBS
;
10401 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10405 if (new_mode
== ARM_CPU_MODE_HYP
) {
10406 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10407 env
->elr_el
[2] = env
->regs
[15];
10409 /* CPSR.PAN is normally preserved preserved unless... */
10410 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10413 if (!arm_is_secure_below_el3(env
)) {
10414 /* ... the target is EL3, from non-secure state. */
10415 env
->uncached_cpsr
&= ~CPSR_PAN
;
10418 /* ... the target is EL3, from secure state ... */
10421 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10422 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10423 env
->uncached_cpsr
|= CPSR_PAN
;
10429 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10430 * and we should just guard the thumb mode on V4
10432 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10434 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10436 env
->regs
[14] = env
->regs
[15] + offset
;
10438 env
->regs
[15] = newpc
;
10439 arm_rebuild_hflags(env
);
10442 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10445 * Handle exception entry to Hyp mode; this is sufficiently
10446 * different to entry to other AArch32 modes that we handle it
10449 * The vector table entry used is always the 0x14 Hyp mode entry point,
10450 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10451 * The offset applied to the preferred return address is always zero
10452 * (see DDI0487C.a section G1.12.3).
10453 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10455 uint32_t addr
, mask
;
10456 ARMCPU
*cpu
= ARM_CPU(cs
);
10457 CPUARMState
*env
= &cpu
->env
;
10459 switch (cs
->exception_index
) {
10467 /* Fall through to prefetch abort. */
10468 case EXCP_PREFETCH_ABORT
:
10469 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10470 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10471 (uint32_t)env
->exception
.vaddress
);
10474 case EXCP_DATA_ABORT
:
10475 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10476 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10477 (uint32_t)env
->exception
.vaddress
);
10489 case EXCP_HYP_TRAP
:
10493 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10496 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10497 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10499 * QEMU syndrome values are v8-style. v7 has the IL bit
10500 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10501 * If this is a v7 CPU, squash the IL bit in those cases.
10503 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10504 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10505 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10506 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10507 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10510 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10513 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10518 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10521 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10524 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10528 addr
+= env
->cp15
.hvbar
;
10530 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10533 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10535 ARMCPU
*cpu
= ARM_CPU(cs
);
10536 CPUARMState
*env
= &cpu
->env
;
10543 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10544 switch (syn_get_ec(env
->exception
.syndrome
)) {
10545 case EC_BREAKPOINT
:
10546 case EC_BREAKPOINT_SAME_EL
:
10549 case EC_WATCHPOINT
:
10550 case EC_WATCHPOINT_SAME_EL
:
10556 case EC_VECTORCATCH
:
10565 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10568 if (env
->exception
.target_el
== 2) {
10569 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10573 switch (cs
->exception_index
) {
10575 new_mode
= ARM_CPU_MODE_UND
;
10585 new_mode
= ARM_CPU_MODE_SVC
;
10588 /* The PC already points to the next instruction. */
10592 /* Fall through to prefetch abort. */
10593 case EXCP_PREFETCH_ABORT
:
10594 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10595 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10596 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10597 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10598 new_mode
= ARM_CPU_MODE_ABT
;
10600 mask
= CPSR_A
| CPSR_I
;
10603 case EXCP_DATA_ABORT
:
10604 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10605 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10606 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10607 env
->exception
.fsr
,
10608 (uint32_t)env
->exception
.vaddress
);
10609 new_mode
= ARM_CPU_MODE_ABT
;
10611 mask
= CPSR_A
| CPSR_I
;
10615 new_mode
= ARM_CPU_MODE_IRQ
;
10617 /* Disable IRQ and imprecise data aborts. */
10618 mask
= CPSR_A
| CPSR_I
;
10620 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10621 /* IRQ routed to monitor mode */
10622 new_mode
= ARM_CPU_MODE_MON
;
10627 new_mode
= ARM_CPU_MODE_FIQ
;
10629 /* Disable FIQ, IRQ and imprecise data aborts. */
10630 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10631 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10632 /* FIQ routed to monitor mode */
10633 new_mode
= ARM_CPU_MODE_MON
;
10638 new_mode
= ARM_CPU_MODE_IRQ
;
10640 /* Disable IRQ and imprecise data aborts. */
10641 mask
= CPSR_A
| CPSR_I
;
10645 new_mode
= ARM_CPU_MODE_FIQ
;
10647 /* Disable FIQ, IRQ and imprecise data aborts. */
10648 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10654 * Note that this is reported as a data abort, but the DFAR
10655 * has an UNKNOWN value. Construct the SError syndrome from
10656 * AET and ExT fields.
10658 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10660 if (extended_addresses_enabled(env
)) {
10661 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10663 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10665 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10666 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10667 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10668 env
->exception
.fsr
);
10670 new_mode
= ARM_CPU_MODE_ABT
;
10672 mask
= CPSR_A
| CPSR_I
;
10677 new_mode
= ARM_CPU_MODE_MON
;
10679 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10683 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10684 return; /* Never happens. Keep compiler happy. */
10687 if (new_mode
== ARM_CPU_MODE_MON
) {
10688 addr
+= env
->cp15
.mvbar
;
10689 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10690 /* High vectors. When enabled, base address cannot be remapped. */
10691 addr
+= 0xffff0000;
10694 * ARM v7 architectures provide a vector base address register to remap
10695 * the interrupt vector table.
10696 * This register is only followed in non-monitor mode, and is banked.
10697 * Note: only bits 31:5 are valid.
10699 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10702 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10703 env
->cp15
.scr_el3
&= ~SCR_NS
;
10706 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10709 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10712 * Return the register number of the AArch64 view of the AArch32
10713 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10714 * be that of the AArch32 mode the exception came from.
10716 int mode
= env
->uncached_cpsr
& CPSR_M
;
10718 switch (aarch32_reg
) {
10720 return aarch32_reg
;
10722 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10725 case ARM_CPU_MODE_USR
:
10726 case ARM_CPU_MODE_SYS
:
10728 case ARM_CPU_MODE_HYP
:
10730 case ARM_CPU_MODE_IRQ
:
10732 case ARM_CPU_MODE_SVC
:
10734 case ARM_CPU_MODE_ABT
:
10736 case ARM_CPU_MODE_UND
:
10738 case ARM_CPU_MODE_FIQ
:
10741 g_assert_not_reached();
10745 case ARM_CPU_MODE_USR
:
10746 case ARM_CPU_MODE_SYS
:
10747 case ARM_CPU_MODE_HYP
:
10749 case ARM_CPU_MODE_IRQ
:
10751 case ARM_CPU_MODE_SVC
:
10753 case ARM_CPU_MODE_ABT
:
10755 case ARM_CPU_MODE_UND
:
10757 case ARM_CPU_MODE_FIQ
:
10760 g_assert_not_reached();
10765 g_assert_not_reached();
10769 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10771 uint32_t ret
= cpsr_read(env
);
10773 /* Move DIT to the correct location for SPSR_ELx */
10774 if (ret
& CPSR_DIT
) {
10778 /* Merge PSTATE.SS into SPSR_ELx */
10779 ret
|= env
->pstate
& PSTATE_SS
;
10784 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
10786 /* Return true if this syndrome value is a synchronous external abort */
10787 switch (syn_get_ec(syndrome
)) {
10789 case EC_INSNABORT_SAME_EL
:
10791 case EC_DATAABORT_SAME_EL
:
10792 /* Look at fault status code for all the synchronous ext abort cases */
10793 switch (syndrome
& 0x3f) {
10809 /* Handle exception entry to a target EL which is using AArch64 */
10810 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10812 ARMCPU
*cpu
= ARM_CPU(cs
);
10813 CPUARMState
*env
= &cpu
->env
;
10814 unsigned int new_el
= env
->exception
.target_el
;
10815 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10816 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10817 unsigned int old_mode
;
10818 unsigned int cur_el
= arm_current_el(env
);
10822 * Note that new_el can never be 0. If cur_el is 0, then
10823 * el0_a64 is is_a64(), else el0_a64 is ignored.
10825 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10827 if (cur_el
< new_el
) {
10829 * Entry vector offset depends on whether the implemented EL
10830 * immediately lower than the target level is using AArch32 or AArch64
10837 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10840 hcr
= arm_hcr_el2_eff(env
);
10841 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10842 is_aa64
= (hcr
& HCR_RW
) != 0;
10847 is_aa64
= is_a64(env
);
10850 g_assert_not_reached();
10858 } else if (pstate_read(env
) & PSTATE_SP
) {
10862 switch (cs
->exception_index
) {
10863 case EXCP_PREFETCH_ABORT
:
10864 case EXCP_DATA_ABORT
:
10866 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
10867 * to be taken to the SError vector entrypoint.
10869 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
10870 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
10873 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10874 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10875 env
->cp15
.far_el
[new_el
]);
10881 case EXCP_HYP_TRAP
:
10883 switch (syn_get_ec(env
->exception
.syndrome
)) {
10884 case EC_ADVSIMDFPACCESSTRAP
:
10886 * QEMU internal FP/SIMD syndromes from AArch32 include the
10887 * TA and coproc fields which are only exposed if the exception
10888 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10889 * AArch64 format syndrome.
10891 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10893 case EC_CP14RTTRAP
:
10894 case EC_CP15RTTRAP
:
10895 case EC_CP14DTTRAP
:
10897 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10898 * the raw register field from the insn; when taking this to
10899 * AArch64 we must convert it to the AArch64 view of the register
10900 * number. Notice that we read a 4-bit AArch32 register number and
10901 * write back a 5-bit AArch64 one.
10903 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10904 rt
= aarch64_regnum(env
, rt
);
10905 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10908 case EC_CP15RRTTRAP
:
10909 case EC_CP14RRTTRAP
:
10910 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10911 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10912 rt
= aarch64_regnum(env
, rt
);
10913 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10915 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10916 rt
= aarch64_regnum(env
, rt
);
10917 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10921 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10933 /* Construct the SError syndrome from IDS and ISS fields. */
10934 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10935 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10938 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10942 old_mode
= pstate_read(env
);
10943 aarch64_save_sp(env
, arm_current_el(env
));
10944 env
->elr_el
[new_el
] = env
->pc
;
10946 old_mode
= cpsr_read_for_spsr_elx(env
);
10947 env
->elr_el
[new_el
] = env
->regs
[15];
10949 aarch64_sync_32_to_64(env
);
10951 env
->condexec_bits
= 0;
10953 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10955 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10956 env
->elr_el
[new_el
]);
10958 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10959 /* The value of PSTATE.PAN is normally preserved, except when ... */
10960 new_mode
|= old_mode
& PSTATE_PAN
;
10963 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10964 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10965 != (HCR_E2H
| HCR_TGE
)) {
10970 /* ... the target is EL1 ... */
10971 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10972 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10973 new_mode
|= PSTATE_PAN
;
10978 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10979 new_mode
|= PSTATE_TCO
;
10982 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10983 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10984 new_mode
|= PSTATE_SSBS
;
10986 new_mode
&= ~PSTATE_SSBS
;
10990 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10991 env
->aarch64
= true;
10992 aarch64_restore_sp(env
, new_el
);
10993 helper_rebuild_hflags_a64(env
, new_el
);
10997 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10998 new_el
, env
->pc
, pstate_read(env
));
11002 * Do semihosting call and set the appropriate return value. All the
11003 * permission and validity checks have been done at translate time.
11005 * We only see semihosting exceptions in TCG only as they are not
11006 * trapped to the hypervisor in KVM.
11009 static void handle_semihosting(CPUState
*cs
)
11011 ARMCPU
*cpu
= ARM_CPU(cs
);
11012 CPUARMState
*env
= &cpu
->env
;
11015 qemu_log_mask(CPU_LOG_INT
,
11016 "...handling as semihosting call 0x%" PRIx64
"\n",
11018 do_common_semihosting(cs
);
11021 qemu_log_mask(CPU_LOG_INT
,
11022 "...handling as semihosting call 0x%x\n",
11024 do_common_semihosting(cs
);
11025 env
->regs
[15] += env
->thumb
? 2 : 4;
11031 * Handle a CPU exception for A and R profile CPUs.
11032 * Do any appropriate logging, handle PSCI calls, and then hand off
11033 * to the AArch64-entry or AArch32-entry function depending on the
11034 * target exception level's register width.
11036 * Note: this is used for both TCG (as the do_interrupt tcg op),
11037 * and KVM to re-inject guest debug exceptions, and to
11038 * inject a Synchronous-External-Abort.
11040 void arm_cpu_do_interrupt(CPUState
*cs
)
11042 ARMCPU
*cpu
= ARM_CPU(cs
);
11043 CPUARMState
*env
= &cpu
->env
;
11044 unsigned int new_el
= env
->exception
.target_el
;
11046 assert(!arm_feature(env
, ARM_FEATURE_M
));
11048 arm_log_exception(cs
);
11049 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11051 if (qemu_loglevel_mask(CPU_LOG_INT
)
11052 && !excp_is_internal(cs
->exception_index
)) {
11053 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11054 syn_get_ec(env
->exception
.syndrome
),
11055 env
->exception
.syndrome
);
11058 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
11059 arm_handle_psci_call(cpu
);
11060 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11065 * Semihosting semantics depend on the register width of the code
11066 * that caused the exception, not the target exception level, so
11067 * must be handled here.
11070 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11071 handle_semihosting(cs
);
11077 * Hooks may change global state so BQL should be held, also the
11078 * BQL needs to be held for any modification of
11079 * cs->interrupt_request.
11081 g_assert(qemu_mutex_iothread_locked());
11083 arm_call_pre_el_change_hook(cpu
);
11085 assert(!excp_is_internal(cs
->exception_index
));
11086 if (arm_el_is_aa64(env
, new_el
)) {
11087 arm_cpu_do_interrupt_aarch64(cs
);
11089 arm_cpu_do_interrupt_aarch32(cs
);
11092 arm_call_el_change_hook(cpu
);
11094 if (!kvm_enabled()) {
11095 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11098 #endif /* !CONFIG_USER_ONLY */
11100 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11102 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11104 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11105 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11107 return env
->cp15
.sctlr_el
[el
];
11110 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11112 if (regime_has_2_ranges(mmu_idx
)) {
11113 return extract64(tcr
, 37, 2);
11114 } else if (regime_is_stage2(mmu_idx
)) {
11115 return 0; /* VTCR_EL2 */
11117 /* Replicate the single TBI bit so we always have 2 bits. */
11118 return extract32(tcr
, 20, 1) * 3;
11122 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11124 if (regime_has_2_ranges(mmu_idx
)) {
11125 return extract64(tcr
, 51, 2);
11126 } else if (regime_is_stage2(mmu_idx
)) {
11127 return 0; /* VTCR_EL2 */
11129 /* Replicate the single TBID bit so we always have 2 bits. */
11130 return extract32(tcr
, 29, 1) * 3;
11134 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11136 if (regime_has_2_ranges(mmu_idx
)) {
11137 return extract64(tcr
, 57, 2);
11139 /* Replicate the single TCMA bit so we always have 2 bits. */
11140 return extract32(tcr
, 30, 1) * 3;
11144 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11154 return GranInvalid
;
11158 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11168 return GranInvalid
;
11172 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11174 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11175 : cpu_isar_feature(aa64_tgran4
, cpu
);
11178 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11180 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11181 : cpu_isar_feature(aa64_tgran16
, cpu
);
11184 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11186 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11187 : cpu_isar_feature(aa64_tgran64
, cpu
);
11190 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11195 if (have4k(cpu
, stage2
)) {
11200 if (have16k(cpu
, stage2
)) {
11205 if (have64k(cpu
, stage2
)) {
11213 * If the guest selects a granule size that isn't implemented,
11214 * the architecture requires that we behave as if it selected one
11215 * that is (with an IMPDEF choice of which one to pick). We choose
11216 * to implement the smallest supported granule size.
11218 if (have4k(cpu
, stage2
)) {
11221 if (have16k(cpu
, stage2
)) {
11224 assert(have64k(cpu
, stage2
));
11228 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11229 ARMMMUIdx mmu_idx
, bool data
)
11231 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11232 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11233 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11234 ARMGranuleSize gran
;
11235 ARMCPU
*cpu
= env_archcpu(env
);
11236 bool stage2
= regime_is_stage2(mmu_idx
);
11238 if (!regime_has_2_ranges(mmu_idx
)) {
11240 tsz
= extract32(tcr
, 0, 6);
11241 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11246 hpd
= extract32(tcr
, 24, 1);
11249 sh
= extract32(tcr
, 12, 2);
11250 ps
= extract32(tcr
, 16, 3);
11251 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11252 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11253 ds
= extract64(tcr
, 32, 1);
11258 * Bit 55 is always between the two regions, and is canonical for
11259 * determining if address tagging is enabled.
11261 select
= extract64(va
, 55, 1);
11263 tsz
= extract32(tcr
, 0, 6);
11264 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11265 epd
= extract32(tcr
, 7, 1);
11266 sh
= extract32(tcr
, 12, 2);
11267 hpd
= extract64(tcr
, 41, 1);
11268 e0pd
= extract64(tcr
, 55, 1);
11270 tsz
= extract32(tcr
, 16, 6);
11271 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11272 epd
= extract32(tcr
, 23, 1);
11273 sh
= extract32(tcr
, 28, 2);
11274 hpd
= extract64(tcr
, 42, 1);
11275 e0pd
= extract64(tcr
, 56, 1);
11277 ps
= extract64(tcr
, 32, 3);
11278 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11279 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11280 ds
= extract64(tcr
, 59, 1);
11282 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11283 regime_is_user(env
, mmu_idx
)) {
11288 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11290 if (cpu_isar_feature(aa64_st
, cpu
)) {
11291 max_tsz
= 48 - (gran
== Gran64K
);
11297 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11298 * adjust the effective value of DS, as documented.
11301 if (gran
== Gran64K
) {
11302 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11307 if (regime_is_stage2(mmu_idx
)) {
11308 if (gran
== Gran16K
) {
11309 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11311 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11314 if (gran
== Gran16K
) {
11315 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11317 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11325 if (tsz
> max_tsz
) {
11328 } else if (tsz
< min_tsz
) {
11335 /* Present TBI as a composite with TBID. */
11336 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11338 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11340 tbi
= (tbi
>> select
) & 1;
11342 return (ARMVAParameters
) {
11350 .tsz_oob
= tsz_oob
,
11359 * Note that signed overflow is undefined in C. The following routines are
11360 * careful to use unsigned types where modulo arithmetic is required.
11361 * Failure to do so _will_ break on newer gcc.
11364 /* Signed saturating arithmetic. */
11366 /* Perform 16-bit signed saturating addition. */
11367 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11372 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11382 /* Perform 8-bit signed saturating addition. */
11383 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11388 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11398 /* Perform 16-bit signed saturating subtraction. */
11399 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11404 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11414 /* Perform 8-bit signed saturating subtraction. */
11415 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11420 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11430 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11431 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11432 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11433 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11436 #include "op_addsub.h"
11438 /* Unsigned saturating arithmetic. */
11439 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11449 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11458 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11468 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11477 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11478 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11479 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11480 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11483 #include "op_addsub.h"
11485 /* Signed modulo arithmetic. */
11486 #define SARITH16(a, b, n, op) do { \
11488 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11489 RESULT(sum, n, 16); \
11491 ge |= 3 << (n * 2); \
11494 #define SARITH8(a, b, n, op) do { \
11496 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11497 RESULT(sum, n, 8); \
11503 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11504 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11505 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11506 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11510 #include "op_addsub.h"
11512 /* Unsigned modulo arithmetic. */
11513 #define ADD16(a, b, n) do { \
11515 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11516 RESULT(sum, n, 16); \
11517 if ((sum >> 16) == 1) \
11518 ge |= 3 << (n * 2); \
11521 #define ADD8(a, b, n) do { \
11523 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11524 RESULT(sum, n, 8); \
11525 if ((sum >> 8) == 1) \
11529 #define SUB16(a, b, n) do { \
11531 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11532 RESULT(sum, n, 16); \
11533 if ((sum >> 16) == 0) \
11534 ge |= 3 << (n * 2); \
11537 #define SUB8(a, b, n) do { \
11539 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11540 RESULT(sum, n, 8); \
11541 if ((sum >> 8) == 0) \
11548 #include "op_addsub.h"
11550 /* Halved signed arithmetic. */
11551 #define ADD16(a, b, n) \
11552 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11553 #define SUB16(a, b, n) \
11554 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11555 #define ADD8(a, b, n) \
11556 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11557 #define SUB8(a, b, n) \
11558 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11561 #include "op_addsub.h"
11563 /* Halved unsigned arithmetic. */
11564 #define ADD16(a, b, n) \
11565 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11566 #define SUB16(a, b, n) \
11567 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11568 #define ADD8(a, b, n) \
11569 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11570 #define SUB8(a, b, n) \
11571 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11574 #include "op_addsub.h"
11576 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11585 /* Unsigned sum of absolute byte differences. */
11586 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11589 sum
= do_usad(a
, b
);
11590 sum
+= do_usad(a
>> 8, b
>> 8);
11591 sum
+= do_usad(a
>> 16, b
>> 16);
11592 sum
+= do_usad(a
>> 24, b
>> 24);
11596 /* For ARMv6 SEL instruction. */
11597 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11612 mask
|= 0xff000000;
11614 return (a
& mask
) | (b
& ~mask
);
11619 * The upper bytes of val (above the number specified by 'bytes') must have
11620 * been zeroed out by the caller.
11622 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11626 stl_le_p(buf
, val
);
11628 /* zlib crc32 converts the accumulator and output to one's complement. */
11629 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11632 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11636 stl_le_p(buf
, val
);
11638 /* Linux crc32c converts the output to one's complement. */
11639 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11643 * Return the exception level to which FP-disabled exceptions should
11644 * be taken, or 0 if FP is enabled.
11646 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11648 #ifndef CONFIG_USER_ONLY
11652 * CPACR and the CPTR registers don't exist before v6, so FP is
11653 * always accessible
11655 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11659 if (arm_feature(env
, ARM_FEATURE_M
)) {
11660 /* CPACR can cause a NOCP UsageFault taken to current security state */
11661 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11665 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11666 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11667 /* FP insns cause a NOCP UsageFault taken to Secure */
11675 hcr_el2
= arm_hcr_el2_eff(env
);
11678 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11679 * 0, 2 : trap EL0 and EL1/PL1 accesses
11680 * 1 : trap only EL0 accesses
11681 * 3 : trap no accesses
11682 * This register is ignored if E2H+TGE are both set.
11684 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11685 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
11695 /* Trap from Secure PL0 or PL1 to Secure PL1. */
11696 if (!arm_el_is_aa64(env
, 3)
11697 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
11708 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11709 * to control non-secure access to the FPU. It doesn't have any
11710 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11712 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11713 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11714 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11715 /* FP insns act as UNDEF */
11716 return cur_el
== 2 ? 2 : 1;
11721 * CPTR_EL2 is present in v7VE or v8, and changes format
11722 * with HCR_EL2.E2H (regardless of TGE).
11725 if (hcr_el2
& HCR_E2H
) {
11726 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
11728 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
11736 } else if (arm_is_el2_enabled(env
)) {
11737 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
11743 /* CPTR_EL3 : present in v8 */
11744 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
11745 /* Trap all FP ops to EL3 */
11752 /* Return the exception level we're running at if this is our mmu_idx */
11753 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
11755 if (mmu_idx
& ARM_MMU_IDX_M
) {
11756 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
11760 case ARMMMUIdx_E10_0
:
11761 case ARMMMUIdx_E20_0
:
11763 case ARMMMUIdx_E10_1
:
11764 case ARMMMUIdx_E10_1_PAN
:
11767 case ARMMMUIdx_E20_2
:
11768 case ARMMMUIdx_E20_2_PAN
:
11773 g_assert_not_reached();
11778 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11780 g_assert_not_reached();
11784 static bool arm_pan_enabled(CPUARMState
*env
)
11787 return env
->pstate
& PSTATE_PAN
;
11789 return env
->uncached_cpsr
& CPSR_PAN
;
11793 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11798 if (arm_feature(env
, ARM_FEATURE_M
)) {
11799 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11802 /* See ARM pseudo-function ELIsInHost. */
11805 hcr
= arm_hcr_el2_eff(env
);
11806 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
11807 idx
= ARMMMUIdx_E20_0
;
11809 idx
= ARMMMUIdx_E10_0
;
11813 if (arm_pan_enabled(env
)) {
11814 idx
= ARMMMUIdx_E10_1_PAN
;
11816 idx
= ARMMMUIdx_E10_1
;
11820 /* Note that TGE does not apply at EL2. */
11821 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
11822 if (arm_pan_enabled(env
)) {
11823 idx
= ARMMMUIdx_E20_2_PAN
;
11825 idx
= ARMMMUIdx_E20_2
;
11828 idx
= ARMMMUIdx_E2
;
11832 return ARMMMUIdx_E3
;
11834 g_assert_not_reached();
11840 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11842 return arm_mmu_idx_el(env
, arm_current_el(env
));
11845 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11847 CPUARMTBFlags flags
)
11849 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
11850 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
11852 if (arm_singlestep_active(env
)) {
11853 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
11859 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11861 CPUARMTBFlags flags
)
11863 bool sctlr_b
= arm_sctlr_b(env
);
11866 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
11868 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11869 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11871 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
11873 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11876 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11879 CPUARMTBFlags flags
= {};
11880 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
11882 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
11883 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
11884 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11887 if (arm_v7m_is_handler_mode(env
)) {
11888 DP_TBFLAG_M32(flags
, HANDLER
, 1);
11892 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11893 * is suppressing them because the requested execution priority
11896 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11897 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11898 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11899 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
11902 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && env
->v7m
.secure
) {
11903 DP_TBFLAG_M32(flags
, SECURE
, 1);
11906 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11909 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11912 CPUARMTBFlags flags
= {};
11913 int el
= arm_current_el(env
);
11915 if (arm_sctlr(env
, el
) & SCTLR_A
) {
11916 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11919 if (arm_el_is_aa64(env
, 1)) {
11920 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11923 if (el
< 2 && env
->cp15
.hstr_el2
&& arm_is_el2_enabled(env
) &&
11924 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11925 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
11928 if (arm_fgt_active(env
, el
)) {
11929 DP_TBFLAG_ANY(flags
, FGT_ACTIVE
, 1);
11932 if (env
->uncached_cpsr
& CPSR_IL
) {
11933 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11937 * The SME exception we are testing for is raised via
11938 * AArch64.CheckFPAdvSIMDEnabled(), as called from
11939 * AArch32.CheckAdvSIMDOrFPEnabled().
11942 && FIELD_EX64(env
->svcr
, SVCR
, SM
)
11943 && (!arm_is_el2_enabled(env
)
11944 || (arm_el_is_aa64(env
, 2) && !(env
->cp15
.hcr_el2
& HCR_TGE
)))
11945 && arm_el_is_aa64(env
, 1)
11946 && !sme_fa64(env
, el
)) {
11947 DP_TBFLAG_A32(flags
, SME_TRAP_NONSTREAMING
, 1);
11950 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11953 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11956 CPUARMTBFlags flags
= {};
11957 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11958 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11962 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
11964 /* Get control bits for tagged addresses. */
11965 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11966 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11968 DP_TBFLAG_A64(flags
, TBII
, tbii
);
11969 DP_TBFLAG_A64(flags
, TBID
, tbid
);
11971 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11972 int sve_el
= sve_exception_el(env
, el
);
11975 * If either FP or SVE are disabled, translator does not need len.
11976 * If SVE EL > FP EL, FP exception has precedence, and translator
11977 * does not need SVE EL. Save potential re-translations by forcing
11978 * the unneeded data to zero.
11981 if (sve_el
> fp_el
) {
11984 } else if (sve_el
== 0) {
11985 DP_TBFLAG_A64(flags
, VL
, sve_vqm1_for_el(env
, el
));
11987 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
11989 if (cpu_isar_feature(aa64_sme
, env_archcpu(env
))) {
11990 int sme_el
= sme_exception_el(env
, el
);
11991 bool sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
11993 DP_TBFLAG_A64(flags
, SMEEXC_EL
, sme_el
);
11995 /* Similarly, do not compute SVL if SME is disabled. */
11996 int svl
= sve_vqm1_for_el_sm(env
, el
, true);
11997 DP_TBFLAG_A64(flags
, SVL
, svl
);
11999 /* If SVE is disabled, we will not have set VL above. */
12000 DP_TBFLAG_A64(flags
, VL
, svl
);
12004 DP_TBFLAG_A64(flags
, PSTATE_SM
, 1);
12005 DP_TBFLAG_A64(flags
, SME_TRAP_NONSTREAMING
, !sme_fa64(env
, el
));
12007 DP_TBFLAG_A64(flags
, PSTATE_ZA
, FIELD_EX64(env
->svcr
, SVCR
, ZA
));
12010 sctlr
= regime_sctlr(env
, stage1
);
12012 if (sctlr
& SCTLR_A
) {
12013 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
12016 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
12017 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
12020 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
12022 * In order to save space in flags, we record only whether
12023 * pauth is "inactive", meaning all insns are implemented as
12024 * a nop, or "active" when some action must be performed.
12025 * The decision of which action to take is left to a helper.
12027 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
12028 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
12032 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12033 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12034 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
12035 DP_TBFLAG_A64(flags
, BT
, 1);
12039 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12040 if (!(env
->pstate
& PSTATE_UAO
)) {
12042 case ARMMMUIdx_E10_1
:
12043 case ARMMMUIdx_E10_1_PAN
:
12044 /* TODO: ARMv8.3-NV */
12045 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
12047 case ARMMMUIdx_E20_2
:
12048 case ARMMMUIdx_E20_2_PAN
:
12050 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12051 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12053 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
12054 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
12062 if (env
->pstate
& PSTATE_IL
) {
12063 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
12066 if (arm_fgt_active(env
, el
)) {
12067 DP_TBFLAG_ANY(flags
, FGT_ACTIVE
, 1);
12068 if (FIELD_EX64(env
->cp15
.fgt_exec
[FGTREG_HFGITR
], HFGITR_EL2
, ERET
)) {
12069 DP_TBFLAG_A64(flags
, FGT_ERET
, 1);
12073 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
12075 * Set MTE_ACTIVE if any access may be Checked, and leave clear
12076 * if all accesses must be Unchecked:
12077 * 1) If no TBI, then there are no tags in the address to check,
12078 * 2) If Tag Check Override, then all accesses are Unchecked,
12079 * 3) If Tag Check Fail == 0, then Checked access have no effect,
12080 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
12082 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
12083 DP_TBFLAG_A64(flags
, ATA
, 1);
12085 && !(env
->pstate
& PSTATE_TCO
)
12086 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
12087 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
12090 /* And again for unprivileged accesses, if required. */
12091 if (EX_TBFLAG_A64(flags
, UNPRIV
)
12093 && !(env
->pstate
& PSTATE_TCO
)
12094 && (sctlr
& SCTLR_TCF0
)
12095 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
12096 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
12098 /* Cache TCMA as well as TBI. */
12099 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
12102 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12105 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
12107 int el
= arm_current_el(env
);
12108 int fp_el
= fp_exception_el(env
, el
);
12109 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12112 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12113 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
12114 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12116 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12120 void arm_rebuild_hflags(CPUARMState
*env
)
12122 env
->hflags
= rebuild_hflags_internal(env
);
12126 * If we have triggered a EL state change we can't rely on the
12127 * translator having passed it to us, we need to recompute.
12129 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
12131 int el
= arm_current_el(env
);
12132 int fp_el
= fp_exception_el(env
, el
);
12133 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12135 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12138 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
12140 int fp_el
= fp_exception_el(env
, el
);
12141 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12143 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12147 * If we have triggered a EL state change we can't rely on the
12148 * translator having passed it to us, we need to recompute.
12150 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
12152 int el
= arm_current_el(env
);
12153 int fp_el
= fp_exception_el(env
, el
);
12154 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12155 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12158 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
12160 int fp_el
= fp_exception_el(env
, el
);
12161 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12163 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12166 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
12168 int fp_el
= fp_exception_el(env
, el
);
12169 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12171 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12174 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
12176 #ifdef CONFIG_DEBUG_TCG
12177 CPUARMTBFlags c
= env
->hflags
;
12178 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
12180 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
12181 fprintf(stderr
, "TCG hflags mismatch "
12182 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
12183 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
12184 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
12190 static bool mve_no_pred(CPUARMState
*env
)
12193 * Return true if there is definitely no predication of MVE
12194 * instructions by VPR or LTPSIZE. (Returning false even if there
12195 * isn't any predication is OK; generated code will just be
12197 * If the CPU does not implement MVE then this TB flag is always 0.
12199 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12200 * logic in gen_update_fp_context() needs to be updated to match.
12202 * We do not include the effect of the ECI bits here -- they are
12203 * tracked in other TB flags. This simplifies the logic for
12204 * "when did we emit code that changes the MVE_NO_PRED TB flag
12205 * and thus need to end the TB?".
12207 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12210 if (env
->v7m
.vpr
) {
12213 if (env
->v7m
.ltpsize
< 4) {
12219 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12220 target_ulong
*cs_base
, uint32_t *pflags
)
12222 CPUARMTBFlags flags
;
12224 assert_hflags_rebuild_correctly(env
);
12225 flags
= env
->hflags
;
12227 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12229 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12230 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12233 *pc
= env
->regs
[15];
12235 if (arm_feature(env
, ARM_FEATURE_M
)) {
12236 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12237 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12238 != env
->v7m
.secure
) {
12239 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12242 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12243 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12244 (env
->v7m
.secure
&&
12245 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12247 * ASPEN is set, but FPCA/SFPA indicate that there is no
12248 * active FP context; we must create a new FP context before
12249 * executing any FP insn.
12251 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12254 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12255 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12256 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12259 if (mve_no_pred(env
)) {
12260 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12264 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12265 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12267 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12268 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12270 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12271 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12273 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12274 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12278 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12279 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12283 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12284 * states defined in the ARM ARM for software singlestep:
12285 * SS_ACTIVE PSTATE.SS State
12286 * 0 x Inactive (the TB flag for SS is always 0)
12287 * 1 0 Active-pending
12288 * 1 1 Active-not-pending
12289 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12291 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12292 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12295 *pflags
= flags
.flags
;
12296 *cs_base
= flags
.flags2
;
12299 #ifdef TARGET_AARCH64
12301 * The manual says that when SVE is enabled and VQ is widened the
12302 * implementation is allowed to zero the previously inaccessible
12303 * portion of the registers. The corollary to that is that when
12304 * SVE is enabled and VQ is narrowed we are also allowed to zero
12305 * the now inaccessible portion of the registers.
12307 * The intent of this is that no predicate bit beyond VQ is ever set.
12308 * Which means that some operations on predicate registers themselves
12309 * may operate on full uint64_t or even unrolled across the maximum
12310 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12311 * may well be cheaper than conditionals to restrict the operation
12312 * to the relevant portion of a uint16_t[16].
12314 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12319 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12320 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12322 /* Zap the high bits of the zregs. */
12323 for (i
= 0; i
< 32; i
++) {
12324 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12327 /* Zap the high bits of the pregs and ffr. */
12330 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12332 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12333 for (i
= 0; i
< 17; ++i
) {
12334 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12340 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12345 exc_el
= sme_exception_el(env
, el
);
12347 exc_el
= sve_exception_el(env
, el
);
12350 return 0; /* disabled */
12352 return sve_vqm1_for_el_sm(env
, el
, sm
);
12356 * Notice a change in SVE vector size when changing EL.
12358 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12359 int new_el
, bool el0_a64
)
12361 ARMCPU
*cpu
= env_archcpu(env
);
12362 int old_len
, new_len
;
12363 bool old_a64
, new_a64
, sm
;
12365 /* Nothing to do if no SVE. */
12366 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12370 /* Nothing to do if FP is disabled in either EL. */
12371 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12375 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12376 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12379 * Both AArch64.TakeException and AArch64.ExceptionReturn
12380 * invoke ResetSVEState when taking an exception from, or
12381 * returning to, AArch32 state when PSTATE.SM is enabled.
12383 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12384 if (old_a64
!= new_a64
&& sm
) {
12385 arm_reset_sve_state(env
);
12390 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12391 * at ELx, or not available because the EL is in AArch32 state, then
12392 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12393 * has an effective value of 0".
12395 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12396 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12397 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12398 * we already have the correct register contents when encountering the
12399 * vq0->vq0 transition between EL0->EL1.
12401 old_len
= new_len
= 0;
12403 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12406 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12409 /* When changing vector length, clear inaccessible state. */
12410 if (new_len
< old_len
) {
12411 aarch64_sve_narrow_vq(env
, new_len
+ 1);