4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/tcg.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
35 #include "exec/cpu_ldst.h"
38 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
40 #ifndef CONFIG_USER_ONLY
42 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
43 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
44 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
45 target_ulong
*page_size_ptr
,
46 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
49 static void switch_mode(CPUARMState
*env
, int mode
);
51 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
53 ARMCPU
*cpu
= env_archcpu(env
);
54 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
56 /* VFP data registers are always little-endian. */
58 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
61 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
62 /* Aliases for Q regs. */
65 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
67 stq_le_p(buf
+ 8, q
[1]);
71 switch (reg
- nregs
) {
72 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
73 case 1: stl_p(buf
, vfp_get_fpscr(env
)); return 4;
74 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
79 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
81 ARMCPU
*cpu
= env_archcpu(env
);
82 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
85 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
88 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
91 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
93 q
[1] = ldq_le_p(buf
+ 8);
97 switch (reg
- nregs
) {
98 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
99 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
100 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
105 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
109 /* 128 bit FP register */
111 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
113 stq_le_p(buf
+ 8, q
[1]);
118 stl_p(buf
, vfp_get_fpsr(env
));
122 stl_p(buf
, vfp_get_fpcr(env
));
129 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
133 /* 128 bit FP register */
135 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
136 q
[0] = ldq_le_p(buf
);
137 q
[1] = ldq_le_p(buf
+ 8);
142 vfp_set_fpsr(env
, ldl_p(buf
));
146 vfp_set_fpcr(env
, ldl_p(buf
));
153 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
155 assert(ri
->fieldoffset
);
156 if (cpreg_field_is_64bit(ri
)) {
157 return CPREG_FIELD64(env
, ri
);
159 return CPREG_FIELD32(env
, ri
);
163 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
166 assert(ri
->fieldoffset
);
167 if (cpreg_field_is_64bit(ri
)) {
168 CPREG_FIELD64(env
, ri
) = value
;
170 CPREG_FIELD32(env
, ri
) = value
;
174 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
176 return (char *)env
+ ri
->fieldoffset
;
179 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
181 /* Raw read of a coprocessor register (as needed for migration, etc). */
182 if (ri
->type
& ARM_CP_CONST
) {
183 return ri
->resetvalue
;
184 } else if (ri
->raw_readfn
) {
185 return ri
->raw_readfn(env
, ri
);
186 } else if (ri
->readfn
) {
187 return ri
->readfn(env
, ri
);
189 return raw_read(env
, ri
);
193 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
196 /* Raw write of a coprocessor register (as needed for migration, etc).
197 * Note that constant registers are treated as write-ignored; the
198 * caller should check for success by whether a readback gives the
201 if (ri
->type
& ARM_CP_CONST
) {
203 } else if (ri
->raw_writefn
) {
204 ri
->raw_writefn(env
, ri
, v
);
205 } else if (ri
->writefn
) {
206 ri
->writefn(env
, ri
, v
);
208 raw_write(env
, ri
, v
);
212 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
214 ARMCPU
*cpu
= env_archcpu(env
);
215 const ARMCPRegInfo
*ri
;
218 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
219 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
221 if (cpreg_field_is_64bit(ri
)) {
222 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
224 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
230 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
235 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
237 /* Return true if the regdef would cause an assertion if you called
238 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
239 * program bug for it not to have the NO_RAW flag).
240 * NB that returning false here doesn't necessarily mean that calling
241 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
242 * read/write access functions which are safe for raw use" from "has
243 * read/write access functions which have side effects but has forgotten
244 * to provide raw access functions".
245 * The tests here line up with the conditions in read/write_raw_cp_reg()
246 * and assertions in raw_read()/raw_write().
248 if ((ri
->type
& ARM_CP_CONST
) ||
250 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
256 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
258 /* Write the coprocessor state from cpu->env to the (index,value) list. */
262 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
263 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
264 const ARMCPRegInfo
*ri
;
267 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
272 if (ri
->type
& ARM_CP_NO_RAW
) {
276 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
279 * Only sync if the previous list->cpustate sync succeeded.
280 * Rather than tracking the success/failure state for every
281 * item in the list, we just recheck "does the raw write we must
282 * have made in write_list_to_cpustate() read back OK" here.
284 uint64_t oldval
= cpu
->cpreg_values
[i
];
286 if (oldval
== newval
) {
290 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
291 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
295 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
297 cpu
->cpreg_values
[i
] = newval
;
302 bool write_list_to_cpustate(ARMCPU
*cpu
)
307 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
308 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
309 uint64_t v
= cpu
->cpreg_values
[i
];
310 const ARMCPRegInfo
*ri
;
312 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
317 if (ri
->type
& ARM_CP_NO_RAW
) {
320 /* Write value and confirm it reads back as written
321 * (to catch read-only registers and partially read-only
322 * registers where the incoming migration value doesn't match)
324 write_raw_cp_reg(&cpu
->env
, ri
, v
);
325 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
332 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
334 ARMCPU
*cpu
= opaque
;
336 const ARMCPRegInfo
*ri
;
338 regidx
= *(uint32_t *)key
;
339 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
341 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
342 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
343 /* The value array need not be initialized at this point */
344 cpu
->cpreg_array_len
++;
348 static void count_cpreg(gpointer key
, gpointer opaque
)
350 ARMCPU
*cpu
= opaque
;
352 const ARMCPRegInfo
*ri
;
354 regidx
= *(uint32_t *)key
;
355 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
357 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
358 cpu
->cpreg_array_len
++;
362 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
364 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
365 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
376 void init_cpreg_list(ARMCPU
*cpu
)
378 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
379 * Note that we require cpreg_tuples[] to be sorted by key ID.
384 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
385 keys
= g_list_sort(keys
, cpreg_key_compare
);
387 cpu
->cpreg_array_len
= 0;
389 g_list_foreach(keys
, count_cpreg
, cpu
);
391 arraylen
= cpu
->cpreg_array_len
;
392 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
393 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
394 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
395 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
396 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
397 cpu
->cpreg_array_len
= 0;
399 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
401 assert(cpu
->cpreg_array_len
== arraylen
);
407 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
408 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
410 * access_el3_aa32ns: Used to check AArch32 register views.
411 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
413 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
414 const ARMCPRegInfo
*ri
,
417 bool secure
= arm_is_secure_below_el3(env
);
419 assert(!arm_el_is_aa64(env
, 3));
421 return CP_ACCESS_TRAP_UNCATEGORIZED
;
426 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
427 const ARMCPRegInfo
*ri
,
430 if (!arm_el_is_aa64(env
, 3)) {
431 return access_el3_aa32ns(env
, ri
, isread
);
436 /* Some secure-only AArch32 registers trap to EL3 if used from
437 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
438 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
439 * We assume that the .access field is set to PL1_RW.
441 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
442 const ARMCPRegInfo
*ri
,
445 if (arm_current_el(env
) == 3) {
448 if (arm_is_secure_below_el3(env
)) {
449 return CP_ACCESS_TRAP_EL3
;
451 /* This will be EL1 NS and EL2 NS, which just UNDEF */
452 return CP_ACCESS_TRAP_UNCATEGORIZED
;
455 /* Check for traps to "powerdown debug" registers, which are controlled
458 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
461 int el
= arm_current_el(env
);
462 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
463 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
464 (arm_hcr_el2_eff(env
) & HCR_TGE
);
466 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
467 return CP_ACCESS_TRAP_EL2
;
469 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
470 return CP_ACCESS_TRAP_EL3
;
475 /* Check for traps to "debug ROM" registers, which are controlled
476 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
478 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
481 int el
= arm_current_el(env
);
482 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
483 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
484 (arm_hcr_el2_eff(env
) & HCR_TGE
);
486 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
487 return CP_ACCESS_TRAP_EL2
;
489 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
490 return CP_ACCESS_TRAP_EL3
;
495 /* Check for traps to general debug registers, which are controlled
496 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
498 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 int el
= arm_current_el(env
);
502 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
503 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
504 (arm_hcr_el2_eff(env
) & HCR_TGE
);
506 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
507 return CP_ACCESS_TRAP_EL2
;
509 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
510 return CP_ACCESS_TRAP_EL3
;
515 /* Check for traps to performance monitor registers, which are controlled
516 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
518 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
521 int el
= arm_current_el(env
);
523 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
524 && !arm_is_secure_below_el3(env
)) {
525 return CP_ACCESS_TRAP_EL2
;
527 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
528 return CP_ACCESS_TRAP_EL3
;
533 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
535 ARMCPU
*cpu
= env_archcpu(env
);
537 raw_write(env
, ri
, value
);
538 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
541 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
543 ARMCPU
*cpu
= env_archcpu(env
);
545 if (raw_read(env
, ri
) != value
) {
546 /* Unlike real hardware the qemu TLB uses virtual addresses,
547 * not modified virtual addresses, so this causes a TLB flush.
550 raw_write(env
, ri
, value
);
554 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
557 ARMCPU
*cpu
= env_archcpu(env
);
559 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
560 && !extended_addresses_enabled(env
)) {
561 /* For VMSA (when not using the LPAE long descriptor page table
562 * format) this register includes the ASID, so do a TLB flush.
563 * For PMSA it is purely a process ID and no action is needed.
567 raw_write(env
, ri
, value
);
570 /* IS variants of TLB operations must affect all cores */
571 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
574 CPUState
*cs
= env_cpu(env
);
576 tlb_flush_all_cpus_synced(cs
);
579 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
582 CPUState
*cs
= env_cpu(env
);
584 tlb_flush_all_cpus_synced(cs
);
587 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
590 CPUState
*cs
= env_cpu(env
);
592 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
595 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
598 CPUState
*cs
= env_cpu(env
);
600 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
604 * Non-IS variants of TLB operations are upgraded to
605 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
606 * force broadcast of these operations.
608 static bool tlb_force_broadcast(CPUARMState
*env
)
610 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
611 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
614 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
617 /* Invalidate all (TLBIALL) */
618 CPUState
*cs
= env_cpu(env
);
620 if (tlb_force_broadcast(env
)) {
621 tlb_flush_all_cpus_synced(cs
);
627 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
630 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
631 CPUState
*cs
= env_cpu(env
);
633 value
&= TARGET_PAGE_MASK
;
634 if (tlb_force_broadcast(env
)) {
635 tlb_flush_page_all_cpus_synced(cs
, value
);
637 tlb_flush_page(cs
, value
);
641 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
644 /* Invalidate by ASID (TLBIASID) */
645 CPUState
*cs
= env_cpu(env
);
647 if (tlb_force_broadcast(env
)) {
648 tlb_flush_all_cpus_synced(cs
);
654 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
657 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
658 CPUState
*cs
= env_cpu(env
);
660 value
&= TARGET_PAGE_MASK
;
661 if (tlb_force_broadcast(env
)) {
662 tlb_flush_page_all_cpus_synced(cs
, value
);
664 tlb_flush_page(cs
, value
);
668 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
671 CPUState
*cs
= env_cpu(env
);
673 tlb_flush_by_mmuidx(cs
,
675 ARMMMUIdxBit_E10_1_PAN
|
677 ARMMMUIdxBit_Stage2
);
680 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
683 CPUState
*cs
= env_cpu(env
);
685 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
687 ARMMMUIdxBit_E10_1_PAN
|
689 ARMMMUIdxBit_Stage2
);
692 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
695 /* Invalidate by IPA. This has to invalidate any structures that
696 * contain only stage 2 translation information, but does not need
697 * to apply to structures that contain combined stage 1 and stage 2
698 * translation information.
699 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
701 CPUState
*cs
= env_cpu(env
);
704 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
708 pageaddr
= sextract64(value
<< 12, 0, 40);
710 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
713 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
716 CPUState
*cs
= env_cpu(env
);
719 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
723 pageaddr
= sextract64(value
<< 12, 0, 40);
725 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
726 ARMMMUIdxBit_Stage2
);
729 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
732 CPUState
*cs
= env_cpu(env
);
734 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
737 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
740 CPUState
*cs
= env_cpu(env
);
742 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
745 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
748 CPUState
*cs
= env_cpu(env
);
749 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
751 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
754 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
757 CPUState
*cs
= env_cpu(env
);
758 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
760 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
764 static const ARMCPRegInfo cp_reginfo
[] = {
765 /* Define the secure and non-secure FCSE identifier CP registers
766 * separately because there is no secure bank in V8 (no _EL3). This allows
767 * the secure register to be properly reset and migrated. There is also no
768 * v8 EL1 version of the register so the non-secure instance stands alone.
771 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
772 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
773 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
774 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
775 { .name
= "FCSEIDR_S",
776 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
777 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
778 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
779 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
780 /* Define the secure and non-secure context identifier CP registers
781 * separately because there is no secure bank in V8 (no _EL3). This allows
782 * the secure register to be properly reset and migrated. In the
783 * non-secure case, the 32-bit register will have reset and migration
784 * disabled during registration as it is handled by the 64-bit instance.
786 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
787 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
788 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
789 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
790 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
791 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
792 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
793 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
794 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
795 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
799 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
800 /* NB: Some of these registers exist in v8 but with more precise
801 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
803 /* MMU Domain access control / MPU write buffer control */
805 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
806 .access
= PL1_RW
, .resetvalue
= 0,
807 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
808 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
809 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
810 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
811 * For v6 and v5, these mappings are overly broad.
813 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
814 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
815 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
816 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
817 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
818 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
819 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
820 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
821 /* Cache maintenance ops; some of this space may be overridden later. */
822 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
823 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
824 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
828 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
829 /* Not all pre-v6 cores implemented this WFI, so this is slightly
832 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
833 .access
= PL1_W
, .type
= ARM_CP_WFI
},
837 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
838 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
839 * is UNPREDICTABLE; we choose to NOP as most implementations do).
841 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
842 .access
= PL1_W
, .type
= ARM_CP_WFI
},
843 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
844 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
845 * OMAPCP will override this space.
847 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
848 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
850 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
851 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
853 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
854 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
855 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
857 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
858 * implementing it as RAZ means the "debug architecture version" bits
859 * will read as a reserved value, which should cause Linux to not try
860 * to use the debug hardware.
862 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
863 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
864 /* MMU TLB control. Note that the wildcarding means we cover not just
865 * the unified TLB ops but also the dside/iside/inner-shareable variants.
867 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
868 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
869 .type
= ARM_CP_NO_RAW
},
870 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
871 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
872 .type
= ARM_CP_NO_RAW
},
873 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
874 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
875 .type
= ARM_CP_NO_RAW
},
876 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
877 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
878 .type
= ARM_CP_NO_RAW
},
879 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
880 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
881 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
882 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
886 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
891 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
892 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
893 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
894 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
895 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
897 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
898 /* VFP coprocessor: cp10 & cp11 [23:20] */
899 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
901 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
902 /* ASEDIS [31] bit is RAO/WI */
906 /* VFPv3 and upwards with NEON implement 32 double precision
907 * registers (D0-D31).
909 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
910 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
918 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
919 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
921 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
922 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
923 value
&= ~(0xf << 20);
924 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
927 env
->cp15
.cpacr_el1
= value
;
930 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
933 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
934 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
936 uint64_t value
= env
->cp15
.cpacr_el1
;
938 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
939 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
940 value
&= ~(0xf << 20);
946 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 /* Call cpacr_write() so that we reset with the correct RAO bits set
949 * for our CPU features.
951 cpacr_write(env
, ri
, 0);
954 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
957 if (arm_feature(env
, ARM_FEATURE_V8
)) {
958 /* Check if CPACR accesses are to be trapped to EL2 */
959 if (arm_current_el(env
) == 1 &&
960 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
961 return CP_ACCESS_TRAP_EL2
;
962 /* Check if CPACR accesses are to be trapped to EL3 */
963 } else if (arm_current_el(env
) < 3 &&
964 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
965 return CP_ACCESS_TRAP_EL3
;
972 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
975 /* Check if CPTR accesses are set to trap to EL3 */
976 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
977 return CP_ACCESS_TRAP_EL3
;
983 static const ARMCPRegInfo v6_cp_reginfo
[] = {
984 /* prefetch by MVA in v6, NOP in v7 */
985 { .name
= "MVA_prefetch",
986 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
987 .access
= PL1_W
, .type
= ARM_CP_NOP
},
988 /* We need to break the TB after ISB to execute self-modifying code
989 * correctly and also to take any pending interrupts immediately.
990 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
992 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
993 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
994 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
995 .access
= PL0_W
, .type
= ARM_CP_NOP
},
996 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
997 .access
= PL0_W
, .type
= ARM_CP_NOP
},
998 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1001 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1003 /* Watchpoint Fault Address Register : should actually only be present
1004 * for 1136, 1176, 11MPCore.
1006 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1007 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1008 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1009 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1010 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1011 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1015 /* Definitions for the PMU registers */
1016 #define PMCRN_MASK 0xf800
1017 #define PMCRN_SHIFT 11
1026 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1027 * which can be written as 1 to trigger behaviour but which stay RAZ).
1029 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1031 #define PMXEVTYPER_P 0x80000000
1032 #define PMXEVTYPER_U 0x40000000
1033 #define PMXEVTYPER_NSK 0x20000000
1034 #define PMXEVTYPER_NSU 0x10000000
1035 #define PMXEVTYPER_NSH 0x08000000
1036 #define PMXEVTYPER_M 0x04000000
1037 #define PMXEVTYPER_MT 0x02000000
1038 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1039 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1040 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1041 PMXEVTYPER_M | PMXEVTYPER_MT | \
1042 PMXEVTYPER_EVTCOUNT)
1044 #define PMCCFILTR 0xf8000000
1045 #define PMCCFILTR_M PMXEVTYPER_M
1046 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1048 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1050 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1053 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1054 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1056 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1059 typedef struct pm_event
{
1060 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1061 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1062 bool (*supported
)(CPUARMState
*);
1064 * Retrieve the current count of the underlying event. The programmed
1065 * counters hold a difference from the return value from this function
1067 uint64_t (*get_count
)(CPUARMState
*);
1069 * Return how many nanoseconds it will take (at a minimum) for count events
1070 * to occur. A negative value indicates the counter will never overflow, or
1071 * that the counter has otherwise arranged for the overflow bit to be set
1072 * and the PMU interrupt to be raised on overflow.
1074 int64_t (*ns_per_count
)(uint64_t);
1077 static bool event_always_supported(CPUARMState
*env
)
1082 static uint64_t swinc_get_count(CPUARMState
*env
)
1085 * SW_INCR events are written directly to the pmevcntr's by writes to
1086 * PMSWINC, so there is no underlying count maintained by the PMU itself
1091 static int64_t swinc_ns_per(uint64_t ignored
)
1097 * Return the underlying cycle count for the PMU cycle counters. If we're in
1098 * usermode, simply return 0.
1100 static uint64_t cycles_get_count(CPUARMState
*env
)
1102 #ifndef CONFIG_USER_ONLY
1103 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1104 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1106 return cpu_get_host_ticks();
1110 #ifndef CONFIG_USER_ONLY
1111 static int64_t cycles_ns_per(uint64_t cycles
)
1113 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1116 static bool instructions_supported(CPUARMState
*env
)
1118 return use_icount
== 1 /* Precise instruction counting */;
1121 static uint64_t instructions_get_count(CPUARMState
*env
)
1123 return (uint64_t)cpu_get_icount_raw();
1126 static int64_t instructions_ns_per(uint64_t icount
)
1128 return cpu_icount_to_ns((int64_t)icount
);
1132 static bool pmu_8_1_events_supported(CPUARMState
*env
)
1134 /* For events which are supported in any v8.1 PMU */
1135 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
1138 static bool pmu_8_4_events_supported(CPUARMState
*env
)
1140 /* For events which are supported in any v8.1 PMU */
1141 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
1144 static uint64_t zero_event_get_count(CPUARMState
*env
)
1146 /* For events which on QEMU never fire, so their count is always zero */
1150 static int64_t zero_event_ns_per(uint64_t cycles
)
1152 /* An event which never fires can never overflow */
1156 static const pm_event pm_events
[] = {
1157 { .number
= 0x000, /* SW_INCR */
1158 .supported
= event_always_supported
,
1159 .get_count
= swinc_get_count
,
1160 .ns_per_count
= swinc_ns_per
,
1162 #ifndef CONFIG_USER_ONLY
1163 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1164 .supported
= instructions_supported
,
1165 .get_count
= instructions_get_count
,
1166 .ns_per_count
= instructions_ns_per
,
1168 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1169 .supported
= event_always_supported
,
1170 .get_count
= cycles_get_count
,
1171 .ns_per_count
= cycles_ns_per
,
1174 { .number
= 0x023, /* STALL_FRONTEND */
1175 .supported
= pmu_8_1_events_supported
,
1176 .get_count
= zero_event_get_count
,
1177 .ns_per_count
= zero_event_ns_per
,
1179 { .number
= 0x024, /* STALL_BACKEND */
1180 .supported
= pmu_8_1_events_supported
,
1181 .get_count
= zero_event_get_count
,
1182 .ns_per_count
= zero_event_ns_per
,
1184 { .number
= 0x03c, /* STALL */
1185 .supported
= pmu_8_4_events_supported
,
1186 .get_count
= zero_event_get_count
,
1187 .ns_per_count
= zero_event_ns_per
,
1192 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1193 * events (i.e. the statistical profiling extension), this implementation
1194 * should first be updated to something sparse instead of the current
1195 * supported_event_map[] array.
1197 #define MAX_EVENT_ID 0x3c
1198 #define UNSUPPORTED_EVENT UINT16_MAX
1199 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1202 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1203 * of ARM event numbers to indices in our pm_events array.
1205 * Note: Events in the 0x40XX range are not currently supported.
1207 void pmu_init(ARMCPU
*cpu
)
1212 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1215 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1216 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1221 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1222 const pm_event
*cnt
= &pm_events
[i
];
1223 assert(cnt
->number
<= MAX_EVENT_ID
);
1224 /* We do not currently support events in the 0x40xx range */
1225 assert(cnt
->number
<= 0x3f);
1227 if (cnt
->supported(&cpu
->env
)) {
1228 supported_event_map
[cnt
->number
] = i
;
1229 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1230 if (cnt
->number
& 0x20) {
1231 cpu
->pmceid1
|= event_mask
;
1233 cpu
->pmceid0
|= event_mask
;
1240 * Check at runtime whether a PMU event is supported for the current machine
1242 static bool event_supported(uint16_t number
)
1244 if (number
> MAX_EVENT_ID
) {
1247 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1250 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1253 /* Performance monitor registers user accessibility is controlled
1254 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1255 * trapping to EL2 or EL3 for other accesses.
1257 int el
= arm_current_el(env
);
1259 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1260 return CP_ACCESS_TRAP
;
1262 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1263 && !arm_is_secure_below_el3(env
)) {
1264 return CP_ACCESS_TRAP_EL2
;
1266 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1267 return CP_ACCESS_TRAP_EL3
;
1270 return CP_ACCESS_OK
;
1273 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1274 const ARMCPRegInfo
*ri
,
1277 /* ER: event counter read trap control */
1278 if (arm_feature(env
, ARM_FEATURE_V8
)
1279 && arm_current_el(env
) == 0
1280 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1282 return CP_ACCESS_OK
;
1285 return pmreg_access(env
, ri
, isread
);
1288 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1289 const ARMCPRegInfo
*ri
,
1292 /* SW: software increment write trap control */
1293 if (arm_feature(env
, ARM_FEATURE_V8
)
1294 && arm_current_el(env
) == 0
1295 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1297 return CP_ACCESS_OK
;
1300 return pmreg_access(env
, ri
, isread
);
1303 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1304 const ARMCPRegInfo
*ri
,
1307 /* ER: event counter read trap control */
1308 if (arm_feature(env
, ARM_FEATURE_V8
)
1309 && arm_current_el(env
) == 0
1310 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1311 return CP_ACCESS_OK
;
1314 return pmreg_access(env
, ri
, isread
);
1317 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1318 const ARMCPRegInfo
*ri
,
1321 /* CR: cycle counter read trap control */
1322 if (arm_feature(env
, ARM_FEATURE_V8
)
1323 && arm_current_el(env
) == 0
1324 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1326 return CP_ACCESS_OK
;
1329 return pmreg_access(env
, ri
, isread
);
1332 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1333 * the current EL, security state, and register configuration.
1335 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1338 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1339 bool enabled
, prohibited
, filtered
;
1340 bool secure
= arm_is_secure(env
);
1341 int el
= arm_current_el(env
);
1342 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1344 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1348 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1349 (counter
< hpmn
|| counter
== 31)) {
1350 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1352 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1354 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1357 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1358 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1363 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1364 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1367 if (prohibited
&& counter
== 31) {
1368 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1371 if (counter
== 31) {
1372 filter
= env
->cp15
.pmccfiltr_el0
;
1374 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1377 p
= filter
& PMXEVTYPER_P
;
1378 u
= filter
& PMXEVTYPER_U
;
1379 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1380 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1381 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1382 m
= arm_el_is_aa64(env
, 1) &&
1383 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1386 filtered
= secure
? u
: u
!= nsu
;
1387 } else if (el
== 1) {
1388 filtered
= secure
? p
: p
!= nsk
;
1389 } else if (el
== 2) {
1395 if (counter
!= 31) {
1397 * If not checking PMCCNTR, ensure the counter is setup to an event we
1400 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1401 if (!event_supported(event
)) {
1406 return enabled
&& !prohibited
&& !filtered
;
1409 static void pmu_update_irq(CPUARMState
*env
)
1411 ARMCPU
*cpu
= env_archcpu(env
);
1412 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1413 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1417 * Ensure c15_ccnt is the guest-visible count so that operations such as
1418 * enabling/disabling the counter or filtering, modifying the count itself,
1419 * etc. can be done logically. This is essentially a no-op if the counter is
1420 * not enabled at the time of the call.
1422 static void pmccntr_op_start(CPUARMState
*env
)
1424 uint64_t cycles
= cycles_get_count(env
);
1426 if (pmu_counter_enabled(env
, 31)) {
1427 uint64_t eff_cycles
= cycles
;
1428 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1429 /* Increment once every 64 processor clock cycles */
1433 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1435 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1436 1ull << 63 : 1ull << 31;
1437 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1438 env
->cp15
.c9_pmovsr
|= (1 << 31);
1439 pmu_update_irq(env
);
1442 env
->cp15
.c15_ccnt
= new_pmccntr
;
1444 env
->cp15
.c15_ccnt_delta
= cycles
;
1448 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1449 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1452 static void pmccntr_op_finish(CPUARMState
*env
)
1454 if (pmu_counter_enabled(env
, 31)) {
1455 #ifndef CONFIG_USER_ONLY
1456 /* Calculate when the counter will next overflow */
1457 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1458 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1459 remaining_cycles
= (uint32_t)remaining_cycles
;
1461 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1463 if (overflow_in
> 0) {
1464 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1466 ARMCPU
*cpu
= env_archcpu(env
);
1467 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1471 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1472 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1473 /* Increment once every 64 processor clock cycles */
1476 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1480 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1483 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1485 if (event_supported(event
)) {
1486 uint16_t event_idx
= supported_event_map
[event
];
1487 count
= pm_events
[event_idx
].get_count(env
);
1490 if (pmu_counter_enabled(env
, counter
)) {
1491 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1493 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1494 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1495 pmu_update_irq(env
);
1497 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1499 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1502 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1504 if (pmu_counter_enabled(env
, counter
)) {
1505 #ifndef CONFIG_USER_ONLY
1506 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1507 uint16_t event_idx
= supported_event_map
[event
];
1508 uint64_t delta
= UINT32_MAX
-
1509 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1510 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1512 if (overflow_in
> 0) {
1513 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1515 ARMCPU
*cpu
= env_archcpu(env
);
1516 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1520 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1521 env
->cp15
.c14_pmevcntr
[counter
];
1525 void pmu_op_start(CPUARMState
*env
)
1528 pmccntr_op_start(env
);
1529 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1530 pmevcntr_op_start(env
, i
);
1534 void pmu_op_finish(CPUARMState
*env
)
1537 pmccntr_op_finish(env
);
1538 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1539 pmevcntr_op_finish(env
, i
);
1543 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1545 pmu_op_start(&cpu
->env
);
1548 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1550 pmu_op_finish(&cpu
->env
);
1553 void arm_pmu_timer_cb(void *opaque
)
1555 ARMCPU
*cpu
= opaque
;
1558 * Update all the counter values based on the current underlying counts,
1559 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1560 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1561 * counter may expire.
1563 pmu_op_start(&cpu
->env
);
1564 pmu_op_finish(&cpu
->env
);
1567 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1572 if (value
& PMCRC
) {
1573 /* The counter has been reset */
1574 env
->cp15
.c15_ccnt
= 0;
1577 if (value
& PMCRP
) {
1579 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1580 env
->cp15
.c14_pmevcntr
[i
] = 0;
1584 env
->cp15
.c9_pmcr
&= ~PMCR_WRITEABLE_MASK
;
1585 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITEABLE_MASK
);
1590 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1594 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1595 /* Increment a counter's count iff: */
1596 if ((value
& (1 << i
)) && /* counter's bit is set */
1597 /* counter is enabled and not filtered */
1598 pmu_counter_enabled(env
, i
) &&
1599 /* counter is SW_INCR */
1600 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1601 pmevcntr_op_start(env
, i
);
1604 * Detect if this write causes an overflow since we can't predict
1605 * PMSWINC overflows like we can for other events
1607 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1609 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1610 env
->cp15
.c9_pmovsr
|= (1 << i
);
1611 pmu_update_irq(env
);
1614 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1616 pmevcntr_op_finish(env
, i
);
1621 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1624 pmccntr_op_start(env
);
1625 ret
= env
->cp15
.c15_ccnt
;
1626 pmccntr_op_finish(env
);
1630 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1633 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1634 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1635 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1638 env
->cp15
.c9_pmselr
= value
& 0x1f;
1641 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1644 pmccntr_op_start(env
);
1645 env
->cp15
.c15_ccnt
= value
;
1646 pmccntr_op_finish(env
);
1649 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1652 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1654 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1657 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1660 pmccntr_op_start(env
);
1661 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1662 pmccntr_op_finish(env
);
1665 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1668 pmccntr_op_start(env
);
1669 /* M is not accessible from AArch32 */
1670 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1671 (value
& PMCCFILTR
);
1672 pmccntr_op_finish(env
);
1675 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1677 /* M is not visible in AArch32 */
1678 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1681 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1684 value
&= pmu_counter_mask(env
);
1685 env
->cp15
.c9_pmcnten
|= value
;
1688 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1691 value
&= pmu_counter_mask(env
);
1692 env
->cp15
.c9_pmcnten
&= ~value
;
1695 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1698 value
&= pmu_counter_mask(env
);
1699 env
->cp15
.c9_pmovsr
&= ~value
;
1700 pmu_update_irq(env
);
1703 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1706 value
&= pmu_counter_mask(env
);
1707 env
->cp15
.c9_pmovsr
|= value
;
1708 pmu_update_irq(env
);
1711 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1712 uint64_t value
, const uint8_t counter
)
1714 if (counter
== 31) {
1715 pmccfiltr_write(env
, ri
, value
);
1716 } else if (counter
< pmu_num_counters(env
)) {
1717 pmevcntr_op_start(env
, counter
);
1720 * If this counter's event type is changing, store the current
1721 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1722 * pmevcntr_op_finish has the correct baseline when it converts back to
1725 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1726 PMXEVTYPER_EVTCOUNT
;
1727 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1728 if (old_event
!= new_event
) {
1730 if (event_supported(new_event
)) {
1731 uint16_t event_idx
= supported_event_map
[new_event
];
1732 count
= pm_events
[event_idx
].get_count(env
);
1734 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1737 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1738 pmevcntr_op_finish(env
, counter
);
1740 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1741 * PMSELR value is equal to or greater than the number of implemented
1742 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1746 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1747 const uint8_t counter
)
1749 if (counter
== 31) {
1750 return env
->cp15
.pmccfiltr_el0
;
1751 } else if (counter
< pmu_num_counters(env
)) {
1752 return env
->cp15
.c14_pmevtyper
[counter
];
1755 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1756 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1762 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1765 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1766 pmevtyper_write(env
, ri
, value
, counter
);
1769 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1772 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1773 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1776 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1777 * pmu_op_finish calls when loading saved state for a migration. Because
1778 * we're potentially updating the type of event here, the value written to
1779 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1780 * different counter type. Therefore, we need to set this value to the
1781 * current count for the counter type we're writing so that pmu_op_finish
1782 * has the correct count for its calculation.
1784 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1785 if (event_supported(event
)) {
1786 uint16_t event_idx
= supported_event_map
[event
];
1787 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1788 pm_events
[event_idx
].get_count(env
);
1792 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1794 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1795 return pmevtyper_read(env
, ri
, counter
);
1798 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1801 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1804 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1806 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1809 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1810 uint64_t value
, uint8_t counter
)
1812 if (counter
< pmu_num_counters(env
)) {
1813 pmevcntr_op_start(env
, counter
);
1814 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1815 pmevcntr_op_finish(env
, counter
);
1818 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1819 * are CONSTRAINED UNPREDICTABLE.
1823 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1826 if (counter
< pmu_num_counters(env
)) {
1828 pmevcntr_op_start(env
, counter
);
1829 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1830 pmevcntr_op_finish(env
, counter
);
1833 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1834 * are CONSTRAINED UNPREDICTABLE. */
1839 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1842 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1843 pmevcntr_write(env
, ri
, value
, counter
);
1846 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1848 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1849 return pmevcntr_read(env
, ri
, counter
);
1852 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1855 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1856 assert(counter
< pmu_num_counters(env
));
1857 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1858 pmevcntr_write(env
, ri
, value
, counter
);
1861 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1863 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1864 assert(counter
< pmu_num_counters(env
));
1865 return env
->cp15
.c14_pmevcntr
[counter
];
1868 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1871 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1874 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1876 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1879 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1882 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1883 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1885 env
->cp15
.c9_pmuserenr
= value
& 1;
1889 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1892 /* We have no event counters so only the C bit can be changed */
1893 value
&= pmu_counter_mask(env
);
1894 env
->cp15
.c9_pminten
|= value
;
1895 pmu_update_irq(env
);
1898 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1901 value
&= pmu_counter_mask(env
);
1902 env
->cp15
.c9_pminten
&= ~value
;
1903 pmu_update_irq(env
);
1906 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1909 /* Note that even though the AArch64 view of this register has bits
1910 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1911 * architectural requirements for bits which are RES0 only in some
1912 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1913 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1915 raw_write(env
, ri
, value
& ~0x1FULL
);
1918 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1920 /* Begin with base v8.0 state. */
1921 uint32_t valid_mask
= 0x3fff;
1922 ARMCPU
*cpu
= env_archcpu(env
);
1924 if (arm_el_is_aa64(env
, 3)) {
1925 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1926 valid_mask
&= ~SCR_NET
;
1928 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1931 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1932 valid_mask
&= ~SCR_HCE
;
1934 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1935 * supported if EL2 exists. The bit is UNK/SBZP when
1936 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1937 * when EL2 is unavailable.
1938 * On ARMv8, this bit is always available.
1940 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1941 !arm_feature(env
, ARM_FEATURE_V8
)) {
1942 valid_mask
&= ~SCR_SMD
;
1945 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1946 valid_mask
|= SCR_TLOR
;
1948 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1949 valid_mask
|= SCR_API
| SCR_APK
;
1952 /* Clear all-context RES0 bits. */
1953 value
&= valid_mask
;
1954 raw_write(env
, ri
, value
);
1957 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1958 const ARMCPRegInfo
*ri
,
1961 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1962 return CP_ACCESS_TRAP_EL2
;
1965 return CP_ACCESS_OK
;
1968 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1970 ARMCPU
*cpu
= env_archcpu(env
);
1972 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1975 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1976 ri
->secure
& ARM_CP_SECSTATE_S
);
1978 return cpu
->ccsidr
[index
];
1981 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1984 raw_write(env
, ri
, value
& 0xf);
1987 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1989 CPUState
*cs
= env_cpu(env
);
1990 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
1992 bool allow_virt
= (arm_current_el(env
) == 1 &&
1993 (!arm_is_secure_below_el3(env
) ||
1994 (env
->cp15
.scr_el3
& SCR_EEL2
)));
1996 if (allow_virt
&& (hcr_el2
& HCR_IMO
)) {
1997 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2001 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2006 if (allow_virt
&& (hcr_el2
& HCR_FMO
)) {
2007 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2011 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2016 /* External aborts are not possible in QEMU so A bit is always clear */
2020 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2023 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2024 return CP_ACCESS_TRAP_EL2
;
2027 return CP_ACCESS_OK
;
2030 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2033 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2034 return access_aa64_tid1(env
, ri
, isread
);
2037 return CP_ACCESS_OK
;
2040 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2041 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2042 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2043 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2044 /* Performance monitors are implementation defined in v7,
2045 * but with an ARM recommended set of registers, which we
2048 * Performance registers fall into three categories:
2049 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2050 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2051 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2052 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2053 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2055 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2056 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2057 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2058 .writefn
= pmcntenset_write
,
2059 .accessfn
= pmreg_access
,
2060 .raw_writefn
= raw_write
},
2061 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
2062 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2063 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2064 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2065 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2066 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2068 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2069 .accessfn
= pmreg_access
,
2070 .writefn
= pmcntenclr_write
,
2071 .type
= ARM_CP_ALIAS
},
2072 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2073 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2074 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2075 .type
= ARM_CP_ALIAS
,
2076 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2077 .writefn
= pmcntenclr_write
},
2078 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2079 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2080 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2081 .accessfn
= pmreg_access
,
2082 .writefn
= pmovsr_write
,
2083 .raw_writefn
= raw_write
},
2084 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2085 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2086 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2087 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2088 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2089 .writefn
= pmovsr_write
,
2090 .raw_writefn
= raw_write
},
2091 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2092 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2093 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2094 .writefn
= pmswinc_write
},
2095 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2096 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2097 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2098 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2099 .writefn
= pmswinc_write
},
2100 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2101 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2102 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2103 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2104 .raw_writefn
= raw_write
},
2105 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2106 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2107 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2108 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2109 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2110 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2111 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2112 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2113 .accessfn
= pmreg_access_ccntr
},
2114 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2115 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2116 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2119 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2120 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2121 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2122 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2123 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2124 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2126 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2127 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2128 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2129 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2131 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2133 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2134 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2135 .accessfn
= pmreg_access
,
2136 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2137 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2138 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2139 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2140 .accessfn
= pmreg_access
,
2141 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2142 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2143 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2144 .accessfn
= pmreg_access_xevcntr
,
2145 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2146 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2147 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2148 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2149 .accessfn
= pmreg_access_xevcntr
,
2150 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2151 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2152 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2153 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2155 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2156 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2157 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2158 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2159 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2161 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2162 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2163 .access
= PL1_RW
, .accessfn
= access_tpm
,
2164 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2165 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2167 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2168 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2169 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2170 .access
= PL1_RW
, .accessfn
= access_tpm
,
2172 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2173 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2174 .resetvalue
= 0x0 },
2175 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2176 .access
= PL1_RW
, .accessfn
= access_tpm
,
2177 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2178 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2179 .writefn
= pmintenclr_write
, },
2180 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2181 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2182 .access
= PL1_RW
, .accessfn
= access_tpm
,
2183 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2184 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2185 .writefn
= pmintenclr_write
},
2186 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2187 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2189 .accessfn
= access_aa64_tid2
,
2190 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2191 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2192 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2194 .accessfn
= access_aa64_tid2
,
2195 .writefn
= csselr_write
, .resetvalue
= 0,
2196 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2197 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2198 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2199 * just RAZ for all cores:
2201 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2202 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2203 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2204 .accessfn
= access_aa64_tid1
,
2206 /* Auxiliary fault status registers: these also are IMPDEF, and we
2207 * choose to RAZ/WI for all cores.
2209 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2210 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2211 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2212 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2213 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2214 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2215 /* MAIR can just read-as-written because we don't implement caches
2216 * and so don't need to care about memory attributes.
2218 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2219 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2220 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2222 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2223 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2224 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2226 /* For non-long-descriptor page tables these are PRRR and NMRR;
2227 * regardless they still act as reads-as-written for QEMU.
2229 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2230 * allows them to assign the correct fieldoffset based on the endianness
2231 * handled in the field definitions.
2233 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2234 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
2235 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2236 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2237 .resetfn
= arm_cp_reset_ignore
},
2238 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2239 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
2240 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2241 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2242 .resetfn
= arm_cp_reset_ignore
},
2243 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2244 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2245 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2246 /* 32 bit ITLB invalidates */
2247 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2248 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2249 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2250 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2251 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2252 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2253 /* 32 bit DTLB invalidates */
2254 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2255 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2256 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2257 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2258 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2259 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2260 /* 32 bit TLB invalidates */
2261 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2262 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2263 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2264 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2265 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2266 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2267 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2268 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2272 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2273 /* 32 bit TLB invalidates, Inner Shareable */
2274 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2275 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
2276 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2277 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2278 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2279 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2280 .writefn
= tlbiasid_is_write
},
2281 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2282 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2283 .writefn
= tlbimvaa_is_write
},
2287 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2288 /* PMOVSSET is not implemented in v7 before v7ve */
2289 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2290 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2291 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2292 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2293 .writefn
= pmovsset_write
,
2294 .raw_writefn
= raw_write
},
2295 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2296 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2297 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2298 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2299 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2300 .writefn
= pmovsset_write
,
2301 .raw_writefn
= raw_write
},
2305 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2312 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2315 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2316 return CP_ACCESS_TRAP
;
2318 return CP_ACCESS_OK
;
2321 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2322 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2323 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2325 .writefn
= teecr_write
},
2326 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2327 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2328 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2332 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2333 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2334 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2336 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2337 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2339 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2340 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2341 .resetfn
= arm_cp_reset_ignore
},
2342 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2343 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2344 .access
= PL0_R
|PL1_W
,
2345 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2347 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2348 .access
= PL0_R
|PL1_W
,
2349 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2350 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2351 .resetfn
= arm_cp_reset_ignore
},
2352 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2353 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2355 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2356 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2358 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2359 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2364 #ifndef CONFIG_USER_ONLY
2366 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2369 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2370 * Writable only at the highest implemented exception level.
2372 int el
= arm_current_el(env
);
2378 hcr
= arm_hcr_el2_eff(env
);
2379 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2380 cntkctl
= env
->cp15
.cnthctl_el2
;
2382 cntkctl
= env
->cp15
.c14_cntkctl
;
2384 if (!extract32(cntkctl
, 0, 2)) {
2385 return CP_ACCESS_TRAP
;
2389 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2390 arm_is_secure_below_el3(env
)) {
2391 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2392 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2400 if (!isread
&& el
< arm_highest_el(env
)) {
2401 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2404 return CP_ACCESS_OK
;
2407 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2410 unsigned int cur_el
= arm_current_el(env
);
2411 bool secure
= arm_is_secure(env
);
2412 uint64_t hcr
= arm_hcr_el2_eff(env
);
2416 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2417 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2418 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2419 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2422 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2423 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2424 return CP_ACCESS_TRAP
;
2427 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2428 if (hcr
& HCR_E2H
) {
2429 if (timeridx
== GTIMER_PHYS
&&
2430 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2431 return CP_ACCESS_TRAP_EL2
;
2434 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2435 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2436 timeridx
== GTIMER_PHYS
&& !secure
&&
2437 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2438 return CP_ACCESS_TRAP_EL2
;
2444 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2445 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2446 timeridx
== GTIMER_PHYS
&& !secure
&&
2448 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2449 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2450 return CP_ACCESS_TRAP_EL2
;
2454 return CP_ACCESS_OK
;
2457 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2460 unsigned int cur_el
= arm_current_el(env
);
2461 bool secure
= arm_is_secure(env
);
2462 uint64_t hcr
= arm_hcr_el2_eff(env
);
2466 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2467 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2468 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2469 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2473 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2474 * EL0 if EL0[PV]TEN is zero.
2476 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2477 return CP_ACCESS_TRAP
;
2482 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2483 timeridx
== GTIMER_PHYS
&& !secure
) {
2484 if (hcr
& HCR_E2H
) {
2485 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2486 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2487 return CP_ACCESS_TRAP_EL2
;
2490 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2491 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2492 return CP_ACCESS_TRAP_EL2
;
2498 return CP_ACCESS_OK
;
2501 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2502 const ARMCPRegInfo
*ri
,
2505 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2508 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2509 const ARMCPRegInfo
*ri
,
2512 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2515 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2518 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2521 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2524 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2527 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2528 const ARMCPRegInfo
*ri
,
2531 /* The AArch64 register view of the secure physical timer is
2532 * always accessible from EL3, and configurably accessible from
2535 switch (arm_current_el(env
)) {
2537 if (!arm_is_secure(env
)) {
2538 return CP_ACCESS_TRAP
;
2540 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2541 return CP_ACCESS_TRAP_EL3
;
2543 return CP_ACCESS_OK
;
2546 return CP_ACCESS_TRAP
;
2548 return CP_ACCESS_OK
;
2550 g_assert_not_reached();
2554 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2556 ARMCPU
*cpu
= env_archcpu(env
);
2558 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2561 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2563 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2566 /* Timer enabled: calculate and set current ISTATUS, irq, and
2567 * reset timer to when ISTATUS next has to change
2569 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2570 cpu
->env
.cp15
.cntvoff_el2
: 0;
2571 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2572 /* Note that this must be unsigned 64 bit arithmetic: */
2573 int istatus
= count
- offset
>= gt
->cval
;
2577 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2579 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2580 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2583 /* Next transition is when count rolls back over to zero */
2584 nexttick
= UINT64_MAX
;
2586 /* Next transition is when we hit cval */
2587 nexttick
= gt
->cval
+ offset
;
2589 /* Note that the desired next expiry time might be beyond the
2590 * signed-64-bit range of a QEMUTimer -- in this case we just
2591 * set the timer for as far in the future as possible. When the
2592 * timer expires we will reset the timer for any remaining period.
2594 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2595 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2597 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2599 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2601 /* Timer disabled: ISTATUS and timer output always clear */
2603 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2604 timer_del(cpu
->gt_timer
[timeridx
]);
2605 trace_arm_gt_recalc_disabled(timeridx
);
2609 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2612 ARMCPU
*cpu
= env_archcpu(env
);
2614 timer_del(cpu
->gt_timer
[timeridx
]);
2617 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2619 return gt_get_countervalue(env
);
2622 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2626 switch (arm_current_el(env
)) {
2628 hcr
= arm_hcr_el2_eff(env
);
2629 if (hcr
& HCR_E2H
) {
2634 hcr
= arm_hcr_el2_eff(env
);
2635 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2641 return env
->cp15
.cntvoff_el2
;
2644 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2646 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2649 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2653 trace_arm_gt_cval_write(timeridx
, value
);
2654 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2655 gt_recalc_timer(env_archcpu(env
), timeridx
);
2658 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2661 uint64_t offset
= 0;
2665 case GTIMER_HYPVIRT
:
2666 offset
= gt_virt_cnt_offset(env
);
2670 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2671 (gt_get_countervalue(env
) - offset
));
2674 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2678 uint64_t offset
= 0;
2682 case GTIMER_HYPVIRT
:
2683 offset
= gt_virt_cnt_offset(env
);
2687 trace_arm_gt_tval_write(timeridx
, value
);
2688 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2689 sextract64(value
, 0, 32);
2690 gt_recalc_timer(env_archcpu(env
), timeridx
);
2693 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2697 ARMCPU
*cpu
= env_archcpu(env
);
2698 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2700 trace_arm_gt_ctl_write(timeridx
, value
);
2701 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2702 if ((oldval
^ value
) & 1) {
2703 /* Enable toggled */
2704 gt_recalc_timer(cpu
, timeridx
);
2705 } else if ((oldval
^ value
) & 2) {
2706 /* IMASK toggled: don't need to recalculate,
2707 * just set the interrupt line based on ISTATUS
2709 int irqstate
= (oldval
& 4) && !(value
& 2);
2711 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2712 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2716 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2718 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2721 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2724 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2727 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2729 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2732 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2735 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2738 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2741 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2744 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2746 switch (arm_mmu_idx(env
)) {
2747 case ARMMMUIdx_E20_0
:
2748 case ARMMMUIdx_E20_2
:
2749 case ARMMMUIdx_E20_2_PAN
:
2756 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2758 switch (arm_mmu_idx(env
)) {
2759 case ARMMMUIdx_E20_0
:
2760 case ARMMMUIdx_E20_2
:
2761 case ARMMMUIdx_E20_2_PAN
:
2762 return GTIMER_HYPVIRT
;
2768 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2769 const ARMCPRegInfo
*ri
)
2771 int timeridx
= gt_phys_redir_timeridx(env
);
2772 return env
->cp15
.c14_timer
[timeridx
].cval
;
2775 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2778 int timeridx
= gt_phys_redir_timeridx(env
);
2779 gt_cval_write(env
, ri
, timeridx
, value
);
2782 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2783 const ARMCPRegInfo
*ri
)
2785 int timeridx
= gt_phys_redir_timeridx(env
);
2786 return gt_tval_read(env
, ri
, timeridx
);
2789 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2792 int timeridx
= gt_phys_redir_timeridx(env
);
2793 gt_tval_write(env
, ri
, timeridx
, value
);
2796 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2797 const ARMCPRegInfo
*ri
)
2799 int timeridx
= gt_phys_redir_timeridx(env
);
2800 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2803 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2806 int timeridx
= gt_phys_redir_timeridx(env
);
2807 gt_ctl_write(env
, ri
, timeridx
, value
);
2810 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2812 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2815 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2818 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2821 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2823 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2826 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2829 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2832 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2835 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2838 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2841 ARMCPU
*cpu
= env_archcpu(env
);
2843 trace_arm_gt_cntvoff_write(value
);
2844 raw_write(env
, ri
, value
);
2845 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2848 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2849 const ARMCPRegInfo
*ri
)
2851 int timeridx
= gt_virt_redir_timeridx(env
);
2852 return env
->cp15
.c14_timer
[timeridx
].cval
;
2855 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2858 int timeridx
= gt_virt_redir_timeridx(env
);
2859 gt_cval_write(env
, ri
, timeridx
, value
);
2862 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2863 const ARMCPRegInfo
*ri
)
2865 int timeridx
= gt_virt_redir_timeridx(env
);
2866 return gt_tval_read(env
, ri
, timeridx
);
2869 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2872 int timeridx
= gt_virt_redir_timeridx(env
);
2873 gt_tval_write(env
, ri
, timeridx
, value
);
2876 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2877 const ARMCPRegInfo
*ri
)
2879 int timeridx
= gt_virt_redir_timeridx(env
);
2880 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2883 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2886 int timeridx
= gt_virt_redir_timeridx(env
);
2887 gt_ctl_write(env
, ri
, timeridx
, value
);
2890 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2892 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2895 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2898 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2901 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2903 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2906 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2909 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2912 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2915 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2918 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2920 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2923 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2926 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2929 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2931 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2934 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2937 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2940 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2943 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2946 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2948 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2951 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2954 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2957 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2959 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2962 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2965 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2968 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2971 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2974 void arm_gt_ptimer_cb(void *opaque
)
2976 ARMCPU
*cpu
= opaque
;
2978 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2981 void arm_gt_vtimer_cb(void *opaque
)
2983 ARMCPU
*cpu
= opaque
;
2985 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2988 void arm_gt_htimer_cb(void *opaque
)
2990 ARMCPU
*cpu
= opaque
;
2992 gt_recalc_timer(cpu
, GTIMER_HYP
);
2995 void arm_gt_stimer_cb(void *opaque
)
2997 ARMCPU
*cpu
= opaque
;
2999 gt_recalc_timer(cpu
, GTIMER_SEC
);
3002 void arm_gt_hvtimer_cb(void *opaque
)
3004 ARMCPU
*cpu
= opaque
;
3006 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3009 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3011 ARMCPU
*cpu
= env_archcpu(env
);
3013 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3016 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3017 /* Note that CNTFRQ is purely reads-as-written for the benefit
3018 * of software; writing it doesn't actually change the timer frequency.
3019 * Our reset value matches the fixed frequency we implement the timer at.
3021 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3022 .type
= ARM_CP_ALIAS
,
3023 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3024 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3026 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3027 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3028 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3029 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3030 .resetfn
= arm_gt_cntfrq_reset
,
3032 /* overall control: mostly access permissions */
3033 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3034 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3036 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3039 /* per-timer control */
3040 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3041 .secure
= ARM_CP_SECSTATE_NS
,
3042 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3043 .accessfn
= gt_ptimer_access
,
3044 .fieldoffset
= offsetoflow32(CPUARMState
,
3045 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3046 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3047 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3049 { .name
= "CNTP_CTL_S",
3050 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3051 .secure
= ARM_CP_SECSTATE_S
,
3052 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3053 .accessfn
= gt_ptimer_access
,
3054 .fieldoffset
= offsetoflow32(CPUARMState
,
3055 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3056 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3058 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3059 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3060 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3061 .accessfn
= gt_ptimer_access
,
3062 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3064 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3065 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3067 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3068 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3069 .accessfn
= gt_vtimer_access
,
3070 .fieldoffset
= offsetoflow32(CPUARMState
,
3071 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3072 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3073 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3075 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3076 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3077 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3078 .accessfn
= gt_vtimer_access
,
3079 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3081 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3082 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3084 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3085 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3086 .secure
= ARM_CP_SECSTATE_NS
,
3087 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3088 .accessfn
= gt_ptimer_access
,
3089 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3091 { .name
= "CNTP_TVAL_S",
3092 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3093 .secure
= ARM_CP_SECSTATE_S
,
3094 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3095 .accessfn
= gt_ptimer_access
,
3096 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3098 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3099 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3100 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3101 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3102 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3104 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3105 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3106 .accessfn
= gt_vtimer_access
,
3107 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3109 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3110 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3111 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3112 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3113 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3115 /* The counter itself */
3116 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3117 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3118 .accessfn
= gt_pct_access
,
3119 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3121 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3122 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3123 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3124 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3126 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3127 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3128 .accessfn
= gt_vct_access
,
3129 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3131 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3132 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3133 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3134 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3136 /* Comparison value, indicating when the timer goes off */
3137 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3138 .secure
= ARM_CP_SECSTATE_NS
,
3140 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3141 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3142 .accessfn
= gt_ptimer_access
,
3143 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3144 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3146 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3147 .secure
= ARM_CP_SECSTATE_S
,
3149 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3150 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3151 .accessfn
= gt_ptimer_access
,
3152 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3154 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3155 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3158 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3159 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3160 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3161 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3163 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3165 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3166 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3167 .accessfn
= gt_vtimer_access
,
3168 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3169 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3171 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3172 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3175 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3176 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3177 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3178 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3180 /* Secure timer -- this is actually restricted to only EL3
3181 * and configurably Secure-EL1 via the accessfn.
3183 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3184 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3185 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3186 .accessfn
= gt_stimer_access
,
3187 .readfn
= gt_sec_tval_read
,
3188 .writefn
= gt_sec_tval_write
,
3189 .resetfn
= gt_sec_timer_reset
,
3191 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3192 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3193 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3194 .accessfn
= gt_stimer_access
,
3195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3197 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3199 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3200 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3201 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3202 .accessfn
= gt_stimer_access
,
3203 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3204 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3209 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3212 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3213 return CP_ACCESS_TRAP
;
3215 return CP_ACCESS_OK
;
3220 /* In user-mode most of the generic timer registers are inaccessible
3221 * however modern kernels (4.12+) allow access to cntvct_el0
3224 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3226 ARMCPU
*cpu
= env_archcpu(env
);
3228 /* Currently we have no support for QEMUTimer in linux-user so we
3229 * can't call gt_get_countervalue(env), instead we directly
3230 * call the lower level functions.
3232 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3235 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3236 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3238 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3239 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3240 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3242 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3243 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3244 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3245 .readfn
= gt_virt_cnt_read
,
3252 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3254 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3255 raw_write(env
, ri
, value
);
3256 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3257 raw_write(env
, ri
, value
& 0xfffff6ff);
3259 raw_write(env
, ri
, value
& 0xfffff1ff);
3263 #ifndef CONFIG_USER_ONLY
3264 /* get_phys_addr() isn't present for user-mode-only targets */
3266 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3270 /* The ATS12NSO* operations must trap to EL3 if executed in
3271 * Secure EL1 (which can only happen if EL3 is AArch64).
3272 * They are simply UNDEF if executed from NS EL1.
3273 * They function normally from EL2 or EL3.
3275 if (arm_current_el(env
) == 1) {
3276 if (arm_is_secure_below_el3(env
)) {
3277 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3279 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3282 return CP_ACCESS_OK
;
3285 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3286 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3289 target_ulong page_size
;
3293 bool format64
= false;
3294 MemTxAttrs attrs
= {};
3295 ARMMMUFaultInfo fi
= {};
3296 ARMCacheAttrs cacheattrs
= {};
3298 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3299 &prot
, &page_size
, &fi
, &cacheattrs
);
3303 * Some kinds of translation fault must cause exceptions rather
3304 * than being reported in the PAR.
3306 int current_el
= arm_current_el(env
);
3308 uint32_t syn
, fsr
, fsc
;
3309 bool take_exc
= false;
3311 if (fi
.s1ptw
&& current_el
== 1 && !arm_is_secure(env
)
3312 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3314 * Synchronous stage 2 fault on an access made as part of the
3315 * translation table walk for AT S1E0* or AT S1E1* insn
3316 * executed from NS EL1. If this is a synchronous external abort
3317 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3318 * to EL3. Otherwise the fault is taken as an exception to EL2,
3319 * and HPFAR_EL2 holds the faulting IPA.
3321 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3322 (env
->cp15
.scr_el3
& SCR_EA
)) {
3325 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3329 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3331 * Synchronous external aborts during a translation table walk
3332 * are taken as Data Abort exceptions.
3335 if (current_el
== 3) {
3341 target_el
= exception_target_el(env
);
3347 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3348 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3349 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3350 fsr
= arm_fi_to_lfsc(&fi
);
3351 fsc
= extract32(fsr
, 0, 6);
3353 fsr
= arm_fi_to_sfsc(&fi
);
3357 * Report exception with ESR indicating a fault due to a
3358 * translation table walk for a cache maintenance instruction.
3360 syn
= syn_data_abort_no_iss(current_el
== target_el
,
3361 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3362 env
->exception
.vaddress
= value
;
3363 env
->exception
.fsr
= fsr
;
3364 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3370 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3373 * * TTBCR.EAE determines whether the result is returned using the
3374 * 32-bit or the 64-bit PAR format
3375 * * Instructions executed in Hyp mode always use the 64bit format
3377 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3378 * * The Non-secure TTBCR.EAE bit is set to 1
3379 * * The implementation includes EL2, and the value of HCR.VM is 1
3381 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3383 * ATS1Hx always uses the 64bit format.
3385 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3387 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3388 if (mmu_idx
== ARMMMUIdx_E10_0
||
3389 mmu_idx
== ARMMMUIdx_E10_1
||
3390 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3391 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3393 format64
|= arm_current_el(env
) == 2;
3399 /* Create a 64-bit PAR */
3400 par64
= (1 << 11); /* LPAE bit always set */
3402 par64
|= phys_addr
& ~0xfffULL
;
3403 if (!attrs
.secure
) {
3404 par64
|= (1 << 9); /* NS */
3406 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3407 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3409 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3412 par64
|= (fsr
& 0x3f) << 1; /* FS */
3414 par64
|= (1 << 9); /* S */
3417 par64
|= (1 << 8); /* PTW */
3421 /* fsr is a DFSR/IFSR value for the short descriptor
3422 * translation table format (with WnR always clear).
3423 * Convert it to a 32-bit PAR.
3426 /* We do not set any attribute bits in the PAR */
3427 if (page_size
== (1 << 24)
3428 && arm_feature(env
, ARM_FEATURE_V7
)) {
3429 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3431 par64
= phys_addr
& 0xfffff000;
3433 if (!attrs
.secure
) {
3434 par64
|= (1 << 9); /* NS */
3437 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3439 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3440 ((fsr
& 0xf) << 1) | 1;
3446 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3448 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3451 int el
= arm_current_el(env
);
3452 bool secure
= arm_is_secure_below_el3(env
);
3454 switch (ri
->opc2
& 6) {
3456 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3459 mmu_idx
= ARMMMUIdx_SE3
;
3462 g_assert(!secure
); /* TODO: ARMv8.4-SecEL2 */
3465 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3466 mmu_idx
= (secure
? ARMMMUIdx_SE10_1_PAN
3467 : ARMMMUIdx_Stage1_E1_PAN
);
3469 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_Stage1_E1
;
3473 g_assert_not_reached();
3477 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3480 mmu_idx
= ARMMMUIdx_SE10_0
;
3483 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3486 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_Stage1_E0
;
3489 g_assert_not_reached();
3493 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3494 mmu_idx
= ARMMMUIdx_E10_1
;
3497 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3498 mmu_idx
= ARMMMUIdx_E10_0
;
3501 g_assert_not_reached();
3504 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3506 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3509 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3512 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3515 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3517 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3520 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3523 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3524 return CP_ACCESS_TRAP
;
3526 return CP_ACCESS_OK
;
3529 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3532 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3534 int secure
= arm_is_secure_below_el3(env
);
3536 switch (ri
->opc2
& 6) {
3539 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3540 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3541 mmu_idx
= (secure
? ARMMMUIdx_SE10_1_PAN
3542 : ARMMMUIdx_Stage1_E1_PAN
);
3544 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_Stage1_E1
;
3547 case 4: /* AT S1E2R, AT S1E2W */
3548 mmu_idx
= ARMMMUIdx_E2
;
3550 case 6: /* AT S1E3R, AT S1E3W */
3551 mmu_idx
= ARMMMUIdx_SE3
;
3554 g_assert_not_reached();
3557 case 2: /* AT S1E0R, AT S1E0W */
3558 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_Stage1_E0
;
3560 case 4: /* AT S12E1R, AT S12E1W */
3561 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3563 case 6: /* AT S12E0R, AT S12E0W */
3564 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3567 g_assert_not_reached();
3570 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3574 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3575 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3576 .access
= PL1_RW
, .resetvalue
= 0,
3577 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3578 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3579 .writefn
= par_write
},
3580 #ifndef CONFIG_USER_ONLY
3581 /* This underdecoding is safe because the reginfo is NO_RAW. */
3582 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3583 .access
= PL1_W
, .accessfn
= ats_access
,
3584 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3589 /* Return basic MPU access permission bits. */
3590 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3597 for (i
= 0; i
< 16; i
+= 2) {
3598 ret
|= (val
>> i
) & mask
;
3604 /* Pad basic MPU access permission bits to extended format. */
3605 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3612 for (i
= 0; i
< 16; i
+= 2) {
3613 ret
|= (val
& mask
) << i
;
3619 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3622 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3625 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3627 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3630 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3633 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3636 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3638 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3641 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3643 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3649 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3653 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3656 ARMCPU
*cpu
= env_archcpu(env
);
3657 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3663 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3664 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3668 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3671 ARMCPU
*cpu
= env_archcpu(env
);
3672 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3674 if (value
>= nrgs
) {
3675 qemu_log_mask(LOG_GUEST_ERROR
,
3676 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3677 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3681 raw_write(env
, ri
, value
);
3684 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3685 /* Reset for all these registers is handled in arm_cpu_reset(),
3686 * because the PMSAv7 is also used by M-profile CPUs, which do
3687 * not register cpregs but still need the state to be reset.
3689 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3690 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3691 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3692 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3693 .resetfn
= arm_cp_reset_ignore
},
3694 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3695 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3696 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3697 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3698 .resetfn
= arm_cp_reset_ignore
},
3699 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3700 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3701 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3702 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3703 .resetfn
= arm_cp_reset_ignore
},
3704 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3706 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3707 .writefn
= pmsav7_rgnr_write
,
3708 .resetfn
= arm_cp_reset_ignore
},
3712 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3713 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3714 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3715 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3716 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3717 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3718 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3719 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3720 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3721 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3723 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3725 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3727 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3729 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3731 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3732 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3734 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3735 /* Protection region base and size registers */
3736 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3737 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3738 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3739 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3740 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3741 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3742 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3743 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3744 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3745 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3746 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3747 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3748 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3749 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3750 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3751 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3752 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3753 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3754 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3755 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3756 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3757 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3758 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3759 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3763 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3766 TCR
*tcr
= raw_ptr(env
, ri
);
3767 int maskshift
= extract32(value
, 0, 3);
3769 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3770 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3771 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3772 * using Long-desciptor translation table format */
3773 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3774 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3775 /* In an implementation that includes the Security Extensions
3776 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3777 * Short-descriptor translation table format.
3779 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3785 /* Update the masks corresponding to the TCR bank being written
3786 * Note that we always calculate mask and base_mask, but
3787 * they are only used for short-descriptor tables (ie if EAE is 0);
3788 * for long-descriptor tables the TCR fields are used differently
3789 * and the mask and base_mask values are meaningless.
3791 tcr
->raw_tcr
= value
;
3792 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3793 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3796 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3799 ARMCPU
*cpu
= env_archcpu(env
);
3800 TCR
*tcr
= raw_ptr(env
, ri
);
3802 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3803 /* With LPAE the TTBCR could result in a change of ASID
3804 * via the TTBCR.A1 bit, so do a TLB flush.
3806 tlb_flush(CPU(cpu
));
3808 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3809 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3810 vmsa_ttbcr_raw_write(env
, ri
, value
);
3813 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3815 TCR
*tcr
= raw_ptr(env
, ri
);
3817 /* Reset both the TCR as well as the masks corresponding to the bank of
3818 * the TCR being reset.
3822 tcr
->base_mask
= 0xffffc000u
;
3825 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3828 ARMCPU
*cpu
= env_archcpu(env
);
3829 TCR
*tcr
= raw_ptr(env
, ri
);
3831 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3832 tlb_flush(CPU(cpu
));
3833 tcr
->raw_tcr
= value
;
3836 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3839 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3840 if (cpreg_field_is_64bit(ri
) &&
3841 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3842 ARMCPU
*cpu
= env_archcpu(env
);
3843 tlb_flush(CPU(cpu
));
3845 raw_write(env
, ri
, value
);
3848 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3852 * If we are running with E2&0 regime, then an ASID is active.
3853 * Flush if that might be changing. Note we're not checking
3854 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3855 * holds the active ASID, only checking the field that might.
3857 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3858 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3859 tlb_flush_by_mmuidx(env_cpu(env
),
3860 ARMMMUIdxBit_E20_2
|
3861 ARMMMUIdxBit_E20_2_PAN
|
3862 ARMMMUIdxBit_E20_0
);
3864 raw_write(env
, ri
, value
);
3867 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3870 ARMCPU
*cpu
= env_archcpu(env
);
3871 CPUState
*cs
= CPU(cpu
);
3874 * A change in VMID to the stage2 page table (Stage2) invalidates
3875 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3877 if (raw_read(env
, ri
) != value
) {
3878 tlb_flush_by_mmuidx(cs
,
3879 ARMMMUIdxBit_E10_1
|
3880 ARMMMUIdxBit_E10_1_PAN
|
3881 ARMMMUIdxBit_E10_0
|
3882 ARMMMUIdxBit_Stage2
);
3883 raw_write(env
, ri
, value
);
3887 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3888 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3889 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3890 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3891 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3892 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3893 .access
= PL1_RW
, .resetvalue
= 0,
3894 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3895 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3896 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3897 .access
= PL1_RW
, .resetvalue
= 0,
3898 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3899 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3900 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3901 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3902 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3907 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3908 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3909 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3911 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3912 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3913 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3914 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3915 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3916 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3917 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3918 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3919 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3920 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3921 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3922 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3923 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3924 .access
= PL1_RW
, .writefn
= vmsa_tcr_el12_write
,
3925 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3926 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3927 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3928 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3929 .raw_writefn
= vmsa_ttbcr_raw_write
,
3930 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3931 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3935 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3936 * qemu tlbs nor adjusting cached masks.
3938 static const ARMCPRegInfo ttbcr2_reginfo
= {
3939 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3940 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3941 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3942 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
3945 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3948 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3949 /* The OS_TYPE bit in this register changes the reported CPUID! */
3950 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3951 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3954 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3957 env
->cp15
.c15_threadid
= value
& 0xffff;
3960 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3963 /* Wait-for-interrupt (deprecated) */
3964 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3967 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3970 /* On OMAP there are registers indicating the max/min index of dcache lines
3971 * containing a dirty line; cache flush operations have to reset these.
3973 env
->cp15
.c15_i_max
= 0x000;
3974 env
->cp15
.c15_i_min
= 0xff0;
3977 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3978 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3979 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3980 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3982 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3983 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3984 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3986 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3987 .writefn
= omap_ticonfig_write
},
3988 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3990 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3991 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3992 .access
= PL1_RW
, .resetvalue
= 0xff0,
3993 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3994 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3996 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3997 .writefn
= omap_threadid_write
},
3998 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3999 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4000 .type
= ARM_CP_NO_RAW
,
4001 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4002 /* TODO: Peripheral port remap register:
4003 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4004 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4007 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4008 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4009 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4010 .writefn
= omap_cachemaint_write
},
4011 { .name
= "C9", .cp
= 15, .crn
= 9,
4012 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4013 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4017 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4020 env
->cp15
.c15_cpar
= value
& 0x3fff;
4023 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4024 { .name
= "XSCALE_CPAR",
4025 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4026 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4027 .writefn
= xscale_cpar_write
, },
4028 { .name
= "XSCALE_AUXCR",
4029 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4030 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4032 /* XScale specific cache-lockdown: since we have no cache we NOP these
4033 * and hope the guest does not really rely on cache behaviour.
4035 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4036 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4037 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4038 { .name
= "XSCALE_UNLOCK_ICACHE",
4039 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4040 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4041 { .name
= "XSCALE_DCACHE_LOCK",
4042 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4043 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4044 { .name
= "XSCALE_UNLOCK_DCACHE",
4045 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4046 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4050 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4051 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4052 * implementation of this implementation-defined space.
4053 * Ideally this should eventually disappear in favour of actually
4054 * implementing the correct behaviour for all cores.
4056 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4057 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4059 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4064 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4065 /* Cache status: RAZ because we have no cache so it's always clean */
4066 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4067 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4072 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4073 /* We never have a a block transfer operation in progress */
4074 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4075 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4077 /* The cache ops themselves: these all NOP for QEMU */
4078 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4079 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4080 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4081 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4082 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4083 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4084 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4085 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4086 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4087 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4088 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4089 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4093 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4094 /* The cache test-and-clean instructions always return (1 << 30)
4095 * to indicate that there are no dirty cache lines.
4097 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4098 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4099 .resetvalue
= (1 << 30) },
4100 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4101 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4102 .resetvalue
= (1 << 30) },
4106 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4107 /* Ignore ReadBuffer accesses */
4108 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4109 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4110 .access
= PL1_RW
, .resetvalue
= 0,
4111 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4115 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4117 ARMCPU
*cpu
= env_archcpu(env
);
4118 unsigned int cur_el
= arm_current_el(env
);
4119 bool secure
= arm_is_secure(env
);
4121 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
4122 return env
->cp15
.vpidr_el2
;
4124 return raw_read(env
, ri
);
4127 static uint64_t mpidr_read_val(CPUARMState
*env
)
4129 ARMCPU
*cpu
= env_archcpu(env
);
4130 uint64_t mpidr
= cpu
->mp_affinity
;
4132 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4133 mpidr
|= (1U << 31);
4134 /* Cores which are uniprocessor (non-coherent)
4135 * but still implement the MP extensions set
4136 * bit 30. (For instance, Cortex-R5).
4138 if (cpu
->mp_is_up
) {
4139 mpidr
|= (1u << 30);
4145 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4147 unsigned int cur_el
= arm_current_el(env
);
4148 bool secure
= arm_is_secure(env
);
4150 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
4151 return env
->cp15
.vmpidr_el2
;
4153 return mpidr_read_val(env
);
4156 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4158 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4159 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4160 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
4162 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4163 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4164 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
4166 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4167 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4168 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4169 offsetof(CPUARMState
, cp15
.par_ns
)} },
4170 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4171 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4172 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4173 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4174 .writefn
= vmsa_ttbr_write
, },
4175 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4176 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4177 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4178 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4179 .writefn
= vmsa_ttbr_write
, },
4183 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4185 return vfp_get_fpcr(env
);
4188 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4191 vfp_set_fpcr(env
, value
);
4194 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4196 return vfp_get_fpsr(env
);
4199 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4202 vfp_set_fpsr(env
, value
);
4205 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4208 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4209 return CP_ACCESS_TRAP
;
4211 return CP_ACCESS_OK
;
4214 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4217 env
->daif
= value
& PSTATE_DAIF
;
4220 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4222 return env
->pstate
& PSTATE_PAN
;
4225 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4228 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4231 static const ARMCPRegInfo pan_reginfo
= {
4232 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4233 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4234 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4235 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4238 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4240 return env
->pstate
& PSTATE_UAO
;
4243 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4246 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4249 static const ARMCPRegInfo uao_reginfo
= {
4250 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4251 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4252 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4253 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4256 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
4257 const ARMCPRegInfo
*ri
,
4260 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
4261 * SCTLR_EL1.UCI is set.
4263 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4264 return CP_ACCESS_TRAP
;
4266 return CP_ACCESS_OK
;
4269 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4270 * Page D4-1736 (DDI0487A.b)
4273 static int vae1_tlbmask(CPUARMState
*env
)
4275 /* Since we exclude secure first, we may read HCR_EL2 directly. */
4276 if (arm_is_secure_below_el3(env
)) {
4277 return ARMMMUIdxBit_SE10_1
|
4278 ARMMMUIdxBit_SE10_1_PAN
|
4279 ARMMMUIdxBit_SE10_0
;
4280 } else if ((env
->cp15
.hcr_el2
& (HCR_E2H
| HCR_TGE
))
4281 == (HCR_E2H
| HCR_TGE
)) {
4282 return ARMMMUIdxBit_E20_2
|
4283 ARMMMUIdxBit_E20_2_PAN
|
4286 return ARMMMUIdxBit_E10_1
|
4287 ARMMMUIdxBit_E10_1_PAN
|
4292 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4295 CPUState
*cs
= env_cpu(env
);
4296 int mask
= vae1_tlbmask(env
);
4298 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4301 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4304 CPUState
*cs
= env_cpu(env
);
4305 int mask
= vae1_tlbmask(env
);
4307 if (tlb_force_broadcast(env
)) {
4308 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4310 tlb_flush_by_mmuidx(cs
, mask
);
4314 static int alle1_tlbmask(CPUARMState
*env
)
4317 * Note that the 'ALL' scope must invalidate both stage 1 and
4318 * stage 2 translations, whereas most other scopes only invalidate
4319 * stage 1 translations.
4321 if (arm_is_secure_below_el3(env
)) {
4322 return ARMMMUIdxBit_SE10_1
|
4323 ARMMMUIdxBit_SE10_1_PAN
|
4324 ARMMMUIdxBit_SE10_0
;
4325 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4326 return ARMMMUIdxBit_E10_1
|
4327 ARMMMUIdxBit_E10_1_PAN
|
4328 ARMMMUIdxBit_E10_0
|
4329 ARMMMUIdxBit_Stage2
;
4331 return ARMMMUIdxBit_E10_1
|
4332 ARMMMUIdxBit_E10_1_PAN
|
4337 static int e2_tlbmask(CPUARMState
*env
)
4339 /* TODO: ARMv8.4-SecEL2 */
4340 return ARMMMUIdxBit_E20_0
|
4341 ARMMMUIdxBit_E20_2
|
4342 ARMMMUIdxBit_E20_2_PAN
|
4346 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4349 CPUState
*cs
= env_cpu(env
);
4350 int mask
= alle1_tlbmask(env
);
4352 tlb_flush_by_mmuidx(cs
, mask
);
4355 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4358 CPUState
*cs
= env_cpu(env
);
4359 int mask
= e2_tlbmask(env
);
4361 tlb_flush_by_mmuidx(cs
, mask
);
4364 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4367 ARMCPU
*cpu
= env_archcpu(env
);
4368 CPUState
*cs
= CPU(cpu
);
4370 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4373 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4376 CPUState
*cs
= env_cpu(env
);
4377 int mask
= alle1_tlbmask(env
);
4379 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4382 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4385 CPUState
*cs
= env_cpu(env
);
4386 int mask
= e2_tlbmask(env
);
4388 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4391 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4394 CPUState
*cs
= env_cpu(env
);
4396 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4399 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4402 /* Invalidate by VA, EL2
4403 * Currently handles both VAE2 and VALE2, since we don't support
4404 * flush-last-level-only.
4406 CPUState
*cs
= env_cpu(env
);
4407 int mask
= e2_tlbmask(env
);
4408 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4410 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4413 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4416 /* Invalidate by VA, EL3
4417 * Currently handles both VAE3 and VALE3, since we don't support
4418 * flush-last-level-only.
4420 ARMCPU
*cpu
= env_archcpu(env
);
4421 CPUState
*cs
= CPU(cpu
);
4422 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4424 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4427 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4430 CPUState
*cs
= env_cpu(env
);
4431 int mask
= vae1_tlbmask(env
);
4432 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4434 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4437 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4440 /* Invalidate by VA, EL1&0 (AArch64 version).
4441 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4442 * since we don't support flush-for-specific-ASID-only or
4443 * flush-last-level-only.
4445 CPUState
*cs
= env_cpu(env
);
4446 int mask
= vae1_tlbmask(env
);
4447 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4449 if (tlb_force_broadcast(env
)) {
4450 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4452 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4456 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4459 CPUState
*cs
= env_cpu(env
);
4460 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4462 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4466 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4469 CPUState
*cs
= env_cpu(env
);
4470 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4472 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4476 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4479 /* Invalidate by IPA. This has to invalidate any structures that
4480 * contain only stage 2 translation information, but does not need
4481 * to apply to structures that contain combined stage 1 and stage 2
4482 * translation information.
4483 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
4485 ARMCPU
*cpu
= env_archcpu(env
);
4486 CPUState
*cs
= CPU(cpu
);
4489 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4493 pageaddr
= sextract64(value
<< 12, 0, 48);
4495 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
4498 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4501 CPUState
*cs
= env_cpu(env
);
4504 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4508 pageaddr
= sextract64(value
<< 12, 0, 48);
4510 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4511 ARMMMUIdxBit_Stage2
);
4514 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4517 int cur_el
= arm_current_el(env
);
4520 uint64_t hcr
= arm_hcr_el2_eff(env
);
4523 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4524 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4525 return CP_ACCESS_TRAP_EL2
;
4528 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4529 return CP_ACCESS_TRAP
;
4531 if (hcr
& HCR_TDZ
) {
4532 return CP_ACCESS_TRAP_EL2
;
4535 } else if (hcr
& HCR_TDZ
) {
4536 return CP_ACCESS_TRAP_EL2
;
4539 return CP_ACCESS_OK
;
4542 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4544 ARMCPU
*cpu
= env_archcpu(env
);
4545 int dzp_bit
= 1 << 4;
4547 /* DZP indicates whether DC ZVA access is allowed */
4548 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4551 return cpu
->dcz_blocksize
| dzp_bit
;
4554 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4557 if (!(env
->pstate
& PSTATE_SP
)) {
4558 /* Access to SP_EL0 is undefined if it's being used as
4559 * the stack pointer.
4561 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4563 return CP_ACCESS_OK
;
4566 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4568 return env
->pstate
& PSTATE_SP
;
4571 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4573 update_spsel(env
, val
);
4576 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4579 ARMCPU
*cpu
= env_archcpu(env
);
4581 if (raw_read(env
, ri
) == value
) {
4582 /* Skip the TLB flush if nothing actually changed; Linux likes
4583 * to do a lot of pointless SCTLR writes.
4588 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4589 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4593 raw_write(env
, ri
, value
);
4594 /* ??? Lots of these bits are not implemented. */
4595 /* This may enable/disable the MMU, so do a TLB flush. */
4596 tlb_flush(CPU(cpu
));
4598 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4600 * Normally we would always end the TB on an SCTLR write; see the
4601 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4602 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4603 * of hflags from the translator, so do it here.
4605 arm_rebuild_hflags(env
);
4609 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4612 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4613 return CP_ACCESS_TRAP_FP_EL2
;
4615 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4616 return CP_ACCESS_TRAP_FP_EL3
;
4618 return CP_ACCESS_OK
;
4621 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4624 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4627 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4628 /* Minimal set of EL0-visible registers. This will need to be expanded
4629 * significantly for system emulation of AArch64 CPUs.
4631 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4632 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4633 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4634 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4635 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4636 .type
= ARM_CP_NO_RAW
,
4637 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4638 .fieldoffset
= offsetof(CPUARMState
, daif
),
4639 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4640 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4641 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4642 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4643 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4644 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4645 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4646 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4647 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4648 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4649 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4650 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4651 .readfn
= aa64_dczid_read
},
4652 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4653 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4654 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4655 #ifndef CONFIG_USER_ONLY
4656 /* Avoid overhead of an access check that always passes in user-mode */
4657 .accessfn
= aa64_zva_access
,
4660 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4661 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4662 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4663 /* Cache ops: all NOPs since we don't emulate caches */
4664 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4665 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4666 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4667 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4668 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4669 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4670 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4671 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4672 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4673 .accessfn
= aa64_cacheop_access
},
4674 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4675 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4676 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4677 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4678 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4679 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4680 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4681 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4682 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4683 .accessfn
= aa64_cacheop_access
},
4684 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4685 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4686 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4687 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4688 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4689 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4690 .accessfn
= aa64_cacheop_access
},
4691 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4692 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4693 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4694 .accessfn
= aa64_cacheop_access
},
4695 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4696 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4697 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4698 /* TLBI operations */
4699 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4700 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4701 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4702 .writefn
= tlbi_aa64_vmalle1is_write
},
4703 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4704 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4705 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4706 .writefn
= tlbi_aa64_vae1is_write
},
4707 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4708 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4709 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4710 .writefn
= tlbi_aa64_vmalle1is_write
},
4711 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4712 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4713 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4714 .writefn
= tlbi_aa64_vae1is_write
},
4715 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4716 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4717 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4718 .writefn
= tlbi_aa64_vae1is_write
},
4719 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4720 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4721 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4722 .writefn
= tlbi_aa64_vae1is_write
},
4723 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4724 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4725 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4726 .writefn
= tlbi_aa64_vmalle1_write
},
4727 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4728 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4729 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4730 .writefn
= tlbi_aa64_vae1_write
},
4731 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4732 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4733 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4734 .writefn
= tlbi_aa64_vmalle1_write
},
4735 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4736 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4737 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4738 .writefn
= tlbi_aa64_vae1_write
},
4739 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4740 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4741 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4742 .writefn
= tlbi_aa64_vae1_write
},
4743 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4744 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4745 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4746 .writefn
= tlbi_aa64_vae1_write
},
4747 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4748 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4749 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4750 .writefn
= tlbi_aa64_ipas2e1is_write
},
4751 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4752 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4753 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4754 .writefn
= tlbi_aa64_ipas2e1is_write
},
4755 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4756 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4757 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4758 .writefn
= tlbi_aa64_alle1is_write
},
4759 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4760 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4761 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4762 .writefn
= tlbi_aa64_alle1is_write
},
4763 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4764 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4765 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4766 .writefn
= tlbi_aa64_ipas2e1_write
},
4767 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4768 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4769 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4770 .writefn
= tlbi_aa64_ipas2e1_write
},
4771 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4772 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4773 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4774 .writefn
= tlbi_aa64_alle1_write
},
4775 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4776 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4777 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4778 .writefn
= tlbi_aa64_alle1is_write
},
4779 #ifndef CONFIG_USER_ONLY
4780 /* 64 bit address translation operations */
4781 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4782 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4783 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4784 .writefn
= ats_write64
},
4785 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4786 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4787 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4788 .writefn
= ats_write64
},
4789 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4790 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4791 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4792 .writefn
= ats_write64
},
4793 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4794 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4795 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4796 .writefn
= ats_write64
},
4797 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4798 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4799 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4800 .writefn
= ats_write64
},
4801 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4802 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4803 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4804 .writefn
= ats_write64
},
4805 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4806 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4807 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4808 .writefn
= ats_write64
},
4809 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4810 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4811 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4812 .writefn
= ats_write64
},
4813 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4814 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4815 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4816 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4817 .writefn
= ats_write64
},
4818 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4819 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4820 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4821 .writefn
= ats_write64
},
4822 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4823 .type
= ARM_CP_ALIAS
,
4824 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4825 .access
= PL1_RW
, .resetvalue
= 0,
4826 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4827 .writefn
= par_write
},
4829 /* TLB invalidate last level of translation table walk */
4830 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4831 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
4832 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4833 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
4834 .writefn
= tlbimvaa_is_write
},
4835 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4836 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
4837 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4838 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
4839 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4840 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4841 .writefn
= tlbimva_hyp_write
},
4842 { .name
= "TLBIMVALHIS",
4843 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4844 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4845 .writefn
= tlbimva_hyp_is_write
},
4846 { .name
= "TLBIIPAS2",
4847 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4848 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4849 .writefn
= tlbiipas2_write
},
4850 { .name
= "TLBIIPAS2IS",
4851 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4852 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4853 .writefn
= tlbiipas2_is_write
},
4854 { .name
= "TLBIIPAS2L",
4855 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4856 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4857 .writefn
= tlbiipas2_write
},
4858 { .name
= "TLBIIPAS2LIS",
4859 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4860 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4861 .writefn
= tlbiipas2_is_write
},
4862 /* 32 bit cache operations */
4863 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4864 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4865 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4866 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4867 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4868 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4869 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4870 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4871 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4872 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4873 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4874 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4875 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4876 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4877 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4878 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4879 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4880 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4881 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4882 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4883 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4884 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4885 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4886 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4887 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4888 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4889 /* MMU Domain access control / MPU write buffer control */
4890 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4891 .access
= PL1_RW
, .resetvalue
= 0,
4892 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4893 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4894 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4895 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4896 .type
= ARM_CP_ALIAS
,
4897 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4899 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4900 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4901 .type
= ARM_CP_ALIAS
,
4902 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4904 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4905 /* We rely on the access checks not allowing the guest to write to the
4906 * state field when SPSel indicates that it's being used as the stack
4909 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4910 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4911 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
4912 .type
= ARM_CP_ALIAS
,
4913 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
4914 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
4915 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
4916 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4917 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
4918 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
4919 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
4920 .type
= ARM_CP_NO_RAW
,
4921 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
4922 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
4923 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
4924 .type
= ARM_CP_ALIAS
,
4925 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
4926 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
4927 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
4928 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
4929 .access
= PL2_RW
, .resetvalue
= 0,
4930 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4931 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
4932 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
4933 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
4934 .access
= PL2_RW
, .resetvalue
= 0,
4935 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
4936 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
4937 .type
= ARM_CP_ALIAS
,
4938 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
4940 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
4941 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
4942 .type
= ARM_CP_ALIAS
,
4943 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
4945 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
4946 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
4947 .type
= ARM_CP_ALIAS
,
4948 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
4950 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
4951 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
4952 .type
= ARM_CP_ALIAS
,
4953 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
4955 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
4956 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
4957 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
4959 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
4960 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
4961 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
4962 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4963 .writefn
= sdcr_write
,
4964 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
4968 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4969 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
4970 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4971 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4973 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
4974 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4975 .type
= ARM_CP_NO_RAW
,
4976 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4978 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4979 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4980 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4981 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4982 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4983 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4985 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4986 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4987 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4988 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4989 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4990 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4991 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4993 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4994 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4995 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4996 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4997 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4998 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5000 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5001 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5002 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5004 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5005 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5006 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5008 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5009 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5010 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5012 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5013 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5014 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5015 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5016 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5017 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5018 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5019 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5020 .cp
= 15, .opc1
= 6, .crm
= 2,
5021 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5022 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
5023 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5024 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5025 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5026 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5027 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5028 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5029 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5030 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5031 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5032 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5033 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5034 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5035 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5036 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5038 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5039 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5040 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5041 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5042 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5043 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5044 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5045 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5047 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5048 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5049 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5050 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5051 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5053 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5054 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5055 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5056 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5057 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5058 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5059 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5060 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5061 .access
= PL2_RW
, .accessfn
= access_tda
,
5062 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5063 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5064 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5065 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5066 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5067 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5068 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5069 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5070 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5071 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5072 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5073 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5074 .type
= ARM_CP_CONST
,
5075 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5076 .access
= PL2_RW
, .resetvalue
= 0 },
5080 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5081 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
5082 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5083 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5085 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5089 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5091 ARMCPU
*cpu
= env_archcpu(env
);
5092 /* Begin with bits defined in base ARMv8.0. */
5093 uint64_t valid_mask
= MAKE_64BIT_MASK(0, 34);
5095 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5096 valid_mask
&= ~HCR_HCD
;
5097 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5098 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5099 * However, if we're using the SMC PSCI conduit then QEMU is
5100 * effectively acting like EL3 firmware and so the guest at
5101 * EL2 should retain the ability to prevent EL1 from being
5102 * able to make SMC calls into the ersatz firmware, so in
5103 * that case HCR.TSC should be read/write.
5105 valid_mask
&= ~HCR_TSC
;
5107 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5108 valid_mask
|= HCR_E2H
;
5110 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5111 valid_mask
|= HCR_TLOR
;
5113 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5114 valid_mask
|= HCR_API
| HCR_APK
;
5117 /* Clear RES0 bits. */
5118 value
&= valid_mask
;
5120 /* These bits change the MMU setup:
5121 * HCR_VM enables stage 2 translation
5122 * HCR_PTW forbids certain page-table setups
5123 * HCR_DC Disables stage1 and enables stage2 translation
5125 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
5126 tlb_flush(CPU(cpu
));
5128 env
->cp15
.hcr_el2
= value
;
5131 * Updates to VI and VF require us to update the status of
5132 * virtual interrupts, which are the logical OR of these bits
5133 * and the state of the input lines from the GIC. (This requires
5134 * that we have the iothread lock, which is done by marking the
5135 * reginfo structs as ARM_CP_IO.)
5136 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5137 * possible for it to be taken immediately, because VIRQ and
5138 * VFIQ are masked unless running at EL0 or EL1, and HCR
5139 * can only be written at EL2.
5141 g_assert(qemu_mutex_iothread_locked());
5142 arm_cpu_update_virq(cpu
);
5143 arm_cpu_update_vfiq(cpu
);
5146 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5149 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5150 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5151 hcr_write(env
, NULL
, value
);
5154 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5157 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5158 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5159 hcr_write(env
, NULL
, value
);
5163 * Return the effective value of HCR_EL2.
5164 * Bits that are not included here:
5165 * RW (read from SCR_EL3.RW as needed)
5167 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5169 uint64_t ret
= env
->cp15
.hcr_el2
;
5171 if (arm_is_secure_below_el3(env
)) {
5173 * "This register has no effect if EL2 is not enabled in the
5174 * current Security state". This is ARMv8.4-SecEL2 speak for
5175 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5177 * Prior to that, the language was "In an implementation that
5178 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5179 * as if this field is 0 for all purposes other than a direct
5180 * read or write access of HCR_EL2". With lots of enumeration
5181 * on a per-field basis. In current QEMU, this is condition
5182 * is arm_is_secure_below_el3.
5184 * Since the v8.4 language applies to the entire register, and
5185 * appears to be backward compatible, use that.
5188 } else if (ret
& HCR_TGE
) {
5189 /* These bits are up-to-date as of ARMv8.4. */
5190 if (ret
& HCR_E2H
) {
5191 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5192 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5193 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5194 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
);
5196 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5198 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5199 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5200 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5207 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5211 * For A-profile AArch32 EL3, if NSACR.CP10
5212 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5214 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5215 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5216 value
&= ~(0x3 << 10);
5217 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
5219 env
->cp15
.cptr_el
[2] = value
;
5222 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5225 * For A-profile AArch32 EL3, if NSACR.CP10
5226 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5228 uint64_t value
= env
->cp15
.cptr_el
[2];
5230 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5231 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5237 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5238 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5240 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5241 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5242 .writefn
= hcr_write
},
5243 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5244 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5245 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5246 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5247 .writefn
= hcr_writelow
},
5248 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5249 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5250 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5251 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5252 .type
= ARM_CP_ALIAS
,
5253 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5255 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5256 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5257 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5258 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5259 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5260 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5261 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5262 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5263 .type
= ARM_CP_ALIAS
,
5264 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5266 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5267 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5268 .type
= ARM_CP_ALIAS
,
5269 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5271 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5272 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5273 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5274 .access
= PL2_RW
, .writefn
= vbar_write
,
5275 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5277 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5278 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5279 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5280 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5281 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5282 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5283 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5284 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5285 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5286 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5287 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5288 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5290 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5291 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5292 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5293 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5294 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5295 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5296 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5298 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5299 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5300 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5301 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5303 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5304 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5305 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5307 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5308 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5309 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5311 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5312 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5313 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5314 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5315 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5316 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5317 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5318 .type
= ARM_CP_ALIAS
,
5319 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5320 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5321 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5322 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5324 /* no .writefn needed as this can't cause an ASID change;
5325 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5327 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5328 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5329 .cp
= 15, .opc1
= 6, .crm
= 2,
5330 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5331 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5332 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5333 .writefn
= vttbr_write
},
5334 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5335 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5336 .access
= PL2_RW
, .writefn
= vttbr_write
,
5337 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5338 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5339 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5340 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5341 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5342 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5343 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5344 .access
= PL2_RW
, .resetvalue
= 0,
5345 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5346 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5347 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5348 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5349 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5350 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5351 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5352 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5353 { .name
= "TLBIALLNSNH",
5354 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5355 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5356 .writefn
= tlbiall_nsnh_write
},
5357 { .name
= "TLBIALLNSNHIS",
5358 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5359 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5360 .writefn
= tlbiall_nsnh_is_write
},
5361 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5362 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5363 .writefn
= tlbiall_hyp_write
},
5364 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5365 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5366 .writefn
= tlbiall_hyp_is_write
},
5367 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5368 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5369 .writefn
= tlbimva_hyp_write
},
5370 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5371 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5372 .writefn
= tlbimva_hyp_is_write
},
5373 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5374 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5375 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5376 .writefn
= tlbi_aa64_alle2_write
},
5377 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5378 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5379 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5380 .writefn
= tlbi_aa64_vae2_write
},
5381 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5382 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5383 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5384 .writefn
= tlbi_aa64_vae2_write
},
5385 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5386 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5387 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5388 .writefn
= tlbi_aa64_alle2is_write
},
5389 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5390 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5391 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5392 .writefn
= tlbi_aa64_vae2is_write
},
5393 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5394 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5395 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5396 .writefn
= tlbi_aa64_vae2is_write
},
5397 #ifndef CONFIG_USER_ONLY
5398 /* Unlike the other EL2-related AT operations, these must
5399 * UNDEF from EL3 if EL2 is not implemented, which is why we
5400 * define them here rather than with the rest of the AT ops.
5402 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5403 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5404 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5405 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5406 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5407 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5408 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5409 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5410 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5411 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5412 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5413 * to behave as if SCR.NS was 1.
5415 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5417 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5418 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5420 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5421 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5422 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5423 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5424 * reset values as IMPDEF. We choose to reset to 3 to comply with
5425 * both ARMv7 and ARMv8.
5427 .access
= PL2_RW
, .resetvalue
= 3,
5428 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5429 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5430 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5431 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5432 .writefn
= gt_cntvoff_write
,
5433 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5434 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5435 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5436 .writefn
= gt_cntvoff_write
,
5437 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5438 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5439 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5440 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5441 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5442 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5443 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5444 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5445 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5446 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5447 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5448 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5449 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5450 .resetfn
= gt_hyp_timer_reset
,
5451 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5452 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5454 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5456 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5458 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5460 /* The only field of MDCR_EL2 that has a defined architectural reset value
5461 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5462 * don't implement any PMU event counters, so using zero as a reset
5463 * value for MDCR_EL2 is okay
5465 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5466 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5467 .access
= PL2_RW
, .resetvalue
= 0,
5468 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5469 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5470 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5471 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5472 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5473 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5474 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5476 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5477 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5478 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5480 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5484 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5485 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5486 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5487 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5489 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5490 .writefn
= hcr_writehigh
},
5494 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5497 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5498 * At Secure EL1 it traps to EL3.
5500 if (arm_current_el(env
) == 3) {
5501 return CP_ACCESS_OK
;
5503 if (arm_is_secure_below_el3(env
)) {
5504 return CP_ACCESS_TRAP_EL3
;
5506 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5508 return CP_ACCESS_OK
;
5510 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5513 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5514 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5515 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5516 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5517 .resetvalue
= 0, .writefn
= scr_write
},
5518 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5519 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5520 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5521 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5522 .writefn
= scr_write
},
5523 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5524 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5525 .access
= PL3_RW
, .resetvalue
= 0,
5526 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5528 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5529 .access
= PL3_RW
, .resetvalue
= 0,
5530 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5531 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5532 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5533 .writefn
= vbar_write
, .resetvalue
= 0,
5534 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5535 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5536 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5537 .access
= PL3_RW
, .resetvalue
= 0,
5538 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5539 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5540 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5542 /* no .writefn needed as this can't cause an ASID change;
5543 * we must provide a .raw_writefn and .resetfn because we handle
5544 * reset and migration for the AArch32 TTBCR(S), which might be
5545 * using mask and base_mask.
5547 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5548 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5549 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5550 .type
= ARM_CP_ALIAS
,
5551 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5553 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5554 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5555 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5556 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5557 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5558 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5559 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5560 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5561 .type
= ARM_CP_ALIAS
,
5562 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5564 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5565 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5566 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5567 .access
= PL3_RW
, .writefn
= vbar_write
,
5568 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5570 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5571 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5572 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5573 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5574 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5575 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5576 .access
= PL3_RW
, .resetvalue
= 0,
5577 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5578 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5579 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5580 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5582 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5583 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5584 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5586 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5587 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5588 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5590 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5591 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5592 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5593 .writefn
= tlbi_aa64_alle3is_write
},
5594 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5595 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5596 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5597 .writefn
= tlbi_aa64_vae3is_write
},
5598 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5599 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5600 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5601 .writefn
= tlbi_aa64_vae3is_write
},
5602 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5603 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5604 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5605 .writefn
= tlbi_aa64_alle3_write
},
5606 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5607 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5608 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5609 .writefn
= tlbi_aa64_vae3_write
},
5610 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5611 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5612 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5613 .writefn
= tlbi_aa64_vae3_write
},
5617 #ifndef CONFIG_USER_ONLY
5618 /* Test if system register redirection is to occur in the current state. */
5619 static bool redirect_for_e2h(CPUARMState
*env
)
5621 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5624 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5628 if (redirect_for_e2h(env
)) {
5629 /* Switch to the saved EL2 version of the register. */
5631 readfn
= ri
->readfn
;
5633 readfn
= ri
->orig_readfn
;
5635 if (readfn
== NULL
) {
5638 return readfn(env
, ri
);
5641 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5646 if (redirect_for_e2h(env
)) {
5647 /* Switch to the saved EL2 version of the register. */
5649 writefn
= ri
->writefn
;
5651 writefn
= ri
->orig_writefn
;
5653 if (writefn
== NULL
) {
5654 writefn
= raw_write
;
5656 writefn(env
, ri
, value
);
5659 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5662 uint32_t src_key
, dst_key
, new_key
;
5663 const char *src_name
, *dst_name
, *new_name
;
5664 bool (*feature
)(const ARMISARegisters
*id
);
5667 #define K(op0, op1, crn, crm, op2) \
5668 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5670 static const struct E2HAlias aliases
[] = {
5671 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5672 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5673 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5674 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5675 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5676 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5677 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5678 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5679 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5680 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5681 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5682 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5683 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5684 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5685 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5686 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5687 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5688 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5689 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5690 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5691 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5692 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5693 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5694 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5695 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5696 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5697 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5698 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5699 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5700 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5701 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5702 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5705 * Note that redirection of ZCR is mentioned in the description
5706 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5707 * not in the summary table.
5709 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5710 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5712 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5713 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5719 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5720 const struct E2HAlias
*a
= &aliases
[i
];
5721 ARMCPRegInfo
*src_reg
, *dst_reg
;
5723 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5727 src_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->src_key
);
5728 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->dst_key
);
5729 g_assert(src_reg
!= NULL
);
5730 g_assert(dst_reg
!= NULL
);
5732 /* Cross-compare names to detect typos in the keys. */
5733 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5734 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5736 /* None of the core system registers use opaque; we will. */
5737 g_assert(src_reg
->opaque
== NULL
);
5739 /* Create alias before redirection so we dup the right data. */
5741 ARMCPRegInfo
*new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5742 uint32_t *new_key
= g_memdup(&a
->new_key
, sizeof(uint32_t));
5745 new_reg
->name
= a
->new_name
;
5746 new_reg
->type
|= ARM_CP_ALIAS
;
5747 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5748 new_reg
->access
&= PL2_RW
| PL3_RW
;
5750 ok
= g_hash_table_insert(cpu
->cp_regs
, new_key
, new_reg
);
5754 src_reg
->opaque
= dst_reg
;
5755 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5756 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5757 if (!src_reg
->raw_readfn
) {
5758 src_reg
->raw_readfn
= raw_read
;
5760 if (!src_reg
->raw_writefn
) {
5761 src_reg
->raw_writefn
= raw_write
;
5763 src_reg
->readfn
= el2_e2h_read
;
5764 src_reg
->writefn
= el2_e2h_write
;
5769 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5772 int cur_el
= arm_current_el(env
);
5775 uint64_t hcr
= arm_hcr_el2_eff(env
);
5778 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5779 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5780 return CP_ACCESS_TRAP_EL2
;
5783 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5784 return CP_ACCESS_TRAP
;
5786 if (hcr
& HCR_TID2
) {
5787 return CP_ACCESS_TRAP_EL2
;
5790 } else if (hcr
& HCR_TID2
) {
5791 return CP_ACCESS_TRAP_EL2
;
5795 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5796 return CP_ACCESS_TRAP_EL2
;
5799 return CP_ACCESS_OK
;
5802 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5805 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5806 * read via a bit in OSLSR_EL1.
5810 if (ri
->state
== ARM_CP_STATE_AA32
) {
5811 oslock
= (value
== 0xC5ACCE55);
5816 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5819 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5820 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5821 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5822 * unlike DBGDRAR it is never accessible from EL0.
5823 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5826 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5827 .access
= PL0_R
, .accessfn
= access_tdra
,
5828 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5829 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5830 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5831 .access
= PL1_R
, .accessfn
= access_tdra
,
5832 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5833 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5834 .access
= PL0_R
, .accessfn
= access_tdra
,
5835 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5836 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5837 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5838 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5839 .access
= PL1_RW
, .accessfn
= access_tda
,
5840 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5842 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5843 * We don't implement the configurable EL0 access.
5845 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
5846 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5847 .type
= ARM_CP_ALIAS
,
5848 .access
= PL1_R
, .accessfn
= access_tda
,
5849 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5850 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5851 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5852 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5853 .accessfn
= access_tdosa
,
5854 .writefn
= oslar_write
},
5855 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5856 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5857 .access
= PL1_R
, .resetvalue
= 10,
5858 .accessfn
= access_tdosa
,
5859 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5860 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5861 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5862 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5863 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5864 .type
= ARM_CP_NOP
},
5865 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5866 * implement vector catch debug events yet.
5869 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5870 .access
= PL1_RW
, .accessfn
= access_tda
,
5871 .type
= ARM_CP_NOP
},
5872 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5873 * to save and restore a 32-bit guest's DBGVCR)
5875 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5876 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5877 .access
= PL2_RW
, .accessfn
= access_tda
,
5878 .type
= ARM_CP_NOP
},
5879 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5880 * Channel but Linux may try to access this register. The 32-bit
5881 * alias is DBGDCCINT.
5883 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5884 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5885 .access
= PL1_RW
, .accessfn
= access_tda
,
5886 .type
= ARM_CP_NOP
},
5890 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
5891 /* 64 bit access versions of the (dummy) debug registers */
5892 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
5893 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5894 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
5895 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5899 /* Return the exception level to which exceptions should be taken
5900 * via SVEAccessTrap. If an exception should be routed through
5901 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5902 * take care of raising that exception.
5903 * C.f. the ARM pseudocode function CheckSVEEnabled.
5905 int sve_exception_el(CPUARMState
*env
, int el
)
5907 #ifndef CONFIG_USER_ONLY
5908 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
5910 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
5911 bool disabled
= false;
5913 /* The CPACR.ZEN controls traps to EL1:
5914 * 0, 2 : trap EL0 and EL1 accesses
5915 * 1 : trap only EL0 accesses
5916 * 3 : trap no accesses
5918 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
5920 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
5925 return hcr_el2
& HCR_TGE
? 2 : 1;
5928 /* Check CPACR.FPEN. */
5929 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
5931 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
5939 /* CPTR_EL2. Since TZ and TFP are positive,
5940 * they will be zero when EL2 is not present.
5942 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
5943 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
5946 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
5951 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5952 if (arm_feature(env
, ARM_FEATURE_EL3
)
5953 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
5960 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
5964 end_len
= start_len
&= 0xf;
5965 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
5966 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
5967 assert(end_len
< start_len
);
5973 * Given that SVE is enabled, return the vector length for EL.
5975 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
5977 ARMCPU
*cpu
= env_archcpu(env
);
5978 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
5981 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
5983 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
5984 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
5986 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5987 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
5990 return sve_zcr_get_valid_len(cpu
, zcr_len
);
5993 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5996 int cur_el
= arm_current_el(env
);
5997 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
6000 /* Bits other than [3:0] are RAZ/WI. */
6001 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6002 raw_write(env
, ri
, value
& 0xf);
6005 * Because we arrived here, we know both FP and SVE are enabled;
6006 * otherwise we would have trapped access to the ZCR_ELn register.
6008 new_len
= sve_zcr_len_for_el(env
, cur_el
);
6009 if (new_len
< old_len
) {
6010 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6014 static const ARMCPRegInfo zcr_el1_reginfo
= {
6015 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6016 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6017 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6018 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6019 .writefn
= zcr_write
, .raw_writefn
= raw_write
6022 static const ARMCPRegInfo zcr_el2_reginfo
= {
6023 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6024 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6025 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6026 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6027 .writefn
= zcr_write
, .raw_writefn
= raw_write
6030 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
6031 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6032 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6033 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6034 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
6037 static const ARMCPRegInfo zcr_el3_reginfo
= {
6038 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6039 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6040 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6041 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6042 .writefn
= zcr_write
, .raw_writefn
= raw_write
6045 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6047 CPUARMState
*env
= &cpu
->env
;
6049 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6050 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6052 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6054 if (env
->cpu_watchpoint
[n
]) {
6055 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6056 env
->cpu_watchpoint
[n
] = NULL
;
6059 if (!extract64(wcr
, 0, 1)) {
6060 /* E bit clear : watchpoint disabled */
6064 switch (extract64(wcr
, 3, 2)) {
6066 /* LSC 00 is reserved and must behave as if the wp is disabled */
6069 flags
|= BP_MEM_READ
;
6072 flags
|= BP_MEM_WRITE
;
6075 flags
|= BP_MEM_ACCESS
;
6079 /* Attempts to use both MASK and BAS fields simultaneously are
6080 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6081 * thus generating a watchpoint for every byte in the masked region.
6083 mask
= extract64(wcr
, 24, 4);
6084 if (mask
== 1 || mask
== 2) {
6085 /* Reserved values of MASK; we must act as if the mask value was
6086 * some non-reserved value, or as if the watchpoint were disabled.
6087 * We choose the latter.
6091 /* Watchpoint covers an aligned area up to 2GB in size */
6093 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6094 * whether the watchpoint fires when the unmasked bits match; we opt
6095 * to generate the exceptions.
6099 /* Watchpoint covers bytes defined by the byte address select bits */
6100 int bas
= extract64(wcr
, 5, 8);
6104 /* This must act as if the watchpoint is disabled */
6108 if (extract64(wvr
, 2, 1)) {
6109 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6110 * ignored, and BAS[3:0] define which bytes to watch.
6114 /* The BAS bits are supposed to be programmed to indicate a contiguous
6115 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6116 * we fire for each byte in the word/doubleword addressed by the WVR.
6117 * We choose to ignore any non-zero bits after the first range of 1s.
6119 basstart
= ctz32(bas
);
6120 len
= cto32(bas
>> basstart
);
6124 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6125 &env
->cpu_watchpoint
[n
]);
6128 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6131 CPUARMState
*env
= &cpu
->env
;
6133 /* Completely clear out existing QEMU watchpoints and our array, to
6134 * avoid possible stale entries following migration load.
6136 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6137 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6139 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6140 hw_watchpoint_update(cpu
, i
);
6144 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6147 ARMCPU
*cpu
= env_archcpu(env
);
6150 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6151 * register reads and behaves as if values written are sign extended.
6152 * Bits [1:0] are RES0.
6154 value
= sextract64(value
, 0, 49) & ~3ULL;
6156 raw_write(env
, ri
, value
);
6157 hw_watchpoint_update(cpu
, i
);
6160 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6163 ARMCPU
*cpu
= env_archcpu(env
);
6166 raw_write(env
, ri
, value
);
6167 hw_watchpoint_update(cpu
, i
);
6170 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6172 CPUARMState
*env
= &cpu
->env
;
6173 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6174 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6179 if (env
->cpu_breakpoint
[n
]) {
6180 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6181 env
->cpu_breakpoint
[n
] = NULL
;
6184 if (!extract64(bcr
, 0, 1)) {
6185 /* E bit clear : watchpoint disabled */
6189 bt
= extract64(bcr
, 20, 4);
6192 case 4: /* unlinked address mismatch (reserved if AArch64) */
6193 case 5: /* linked address mismatch (reserved if AArch64) */
6194 qemu_log_mask(LOG_UNIMP
,
6195 "arm: address mismatch breakpoint types not implemented\n");
6197 case 0: /* unlinked address match */
6198 case 1: /* linked address match */
6200 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6201 * we behave as if the register was sign extended. Bits [1:0] are
6202 * RES0. The BAS field is used to allow setting breakpoints on 16
6203 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6204 * a bp will fire if the addresses covered by the bp and the addresses
6205 * covered by the insn overlap but the insn doesn't start at the
6206 * start of the bp address range. We choose to require the insn and
6207 * the bp to have the same address. The constraints on writing to
6208 * BAS enforced in dbgbcr_write mean we have only four cases:
6209 * 0b0000 => no breakpoint
6210 * 0b0011 => breakpoint on addr
6211 * 0b1100 => breakpoint on addr + 2
6212 * 0b1111 => breakpoint on addr
6213 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6215 int bas
= extract64(bcr
, 5, 4);
6216 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
6225 case 2: /* unlinked context ID match */
6226 case 8: /* unlinked VMID match (reserved if no EL2) */
6227 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6228 qemu_log_mask(LOG_UNIMP
,
6229 "arm: unlinked context breakpoint types not implemented\n");
6231 case 9: /* linked VMID match (reserved if no EL2) */
6232 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6233 case 3: /* linked context ID match */
6235 /* We must generate no events for Linked context matches (unless
6236 * they are linked to by some other bp/wp, which is handled in
6237 * updates for the linking bp/wp). We choose to also generate no events
6238 * for reserved values.
6243 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6246 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6249 CPUARMState
*env
= &cpu
->env
;
6251 /* Completely clear out existing QEMU breakpoints and our array, to
6252 * avoid possible stale entries following migration load.
6254 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6255 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6257 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6258 hw_breakpoint_update(cpu
, i
);
6262 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6265 ARMCPU
*cpu
= env_archcpu(env
);
6268 raw_write(env
, ri
, value
);
6269 hw_breakpoint_update(cpu
, i
);
6272 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6275 ARMCPU
*cpu
= env_archcpu(env
);
6278 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6281 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6282 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6284 raw_write(env
, ri
, value
);
6285 hw_breakpoint_update(cpu
, i
);
6288 static void define_debug_regs(ARMCPU
*cpu
)
6290 /* Define v7 and v8 architectural debug registers.
6291 * These are just dummy implementations for now.
6294 int wrps
, brps
, ctx_cmps
;
6295 ARMCPRegInfo dbgdidr
= {
6296 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
6297 .access
= PL0_R
, .accessfn
= access_tda
,
6298 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6301 /* Note that all these register fields hold "number of Xs minus 1". */
6302 brps
= arm_num_brps(cpu
);
6303 wrps
= arm_num_wrps(cpu
);
6304 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6306 assert(ctx_cmps
<= brps
);
6308 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6309 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6311 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6312 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6315 for (i
= 0; i
< brps
; i
++) {
6316 ARMCPRegInfo dbgregs
[] = {
6317 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
6318 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6319 .access
= PL1_RW
, .accessfn
= access_tda
,
6320 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6321 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6323 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
6324 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6325 .access
= PL1_RW
, .accessfn
= access_tda
,
6326 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6327 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6331 define_arm_cp_regs(cpu
, dbgregs
);
6334 for (i
= 0; i
< wrps
; i
++) {
6335 ARMCPRegInfo dbgregs
[] = {
6336 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
6337 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6338 .access
= PL1_RW
, .accessfn
= access_tda
,
6339 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6340 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6342 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
6343 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6344 .access
= PL1_RW
, .accessfn
= access_tda
,
6345 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6346 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6350 define_arm_cp_regs(cpu
, dbgregs
);
6354 static void define_pmu_regs(ARMCPU
*cpu
)
6357 * v7 performance monitor control register: same implementor
6358 * field as main ID register, and we implement four counters in
6359 * addition to the cycle count register.
6361 unsigned int i
, pmcrn
= 4;
6362 ARMCPRegInfo pmcr
= {
6363 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6365 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6366 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6367 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6368 .raw_writefn
= raw_write
,
6370 ARMCPRegInfo pmcr64
= {
6371 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6372 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6373 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6375 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6376 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
) |
6378 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6380 define_one_arm_cp_reg(cpu
, &pmcr
);
6381 define_one_arm_cp_reg(cpu
, &pmcr64
);
6382 for (i
= 0; i
< pmcrn
; i
++) {
6383 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6384 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6385 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6386 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6387 ARMCPRegInfo pmev_regs
[] = {
6388 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6389 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6390 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6391 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6392 .accessfn
= pmreg_access
},
6393 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6394 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6395 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6397 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6398 .raw_readfn
= pmevcntr_rawread
,
6399 .raw_writefn
= pmevcntr_rawwrite
},
6400 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6401 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6402 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6403 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6404 .accessfn
= pmreg_access
},
6405 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6406 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6407 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6409 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6410 .raw_writefn
= pmevtyper_rawwrite
},
6413 define_arm_cp_regs(cpu
, pmev_regs
);
6414 g_free(pmevcntr_name
);
6415 g_free(pmevcntr_el0_name
);
6416 g_free(pmevtyper_name
);
6417 g_free(pmevtyper_el0_name
);
6419 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6420 ARMCPRegInfo v81_pmu_regs
[] = {
6421 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6422 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6423 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6424 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6425 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6426 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6427 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6428 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6431 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6433 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6434 static const ARMCPRegInfo v84_pmmir
= {
6435 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6436 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6437 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6440 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6444 /* We don't know until after realize whether there's a GICv3
6445 * attached, and that is what registers the gicv3 sysregs.
6446 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6449 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6451 ARMCPU
*cpu
= env_archcpu(env
);
6452 uint64_t pfr1
= cpu
->id_pfr1
;
6454 if (env
->gicv3state
) {
6460 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6462 ARMCPU
*cpu
= env_archcpu(env
);
6463 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6465 if (env
->gicv3state
) {
6471 /* Shared logic between LORID and the rest of the LOR* registers.
6472 * Secure state has already been delt with.
6474 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
6476 int el
= arm_current_el(env
);
6478 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6479 return CP_ACCESS_TRAP_EL2
;
6481 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6482 return CP_ACCESS_TRAP_EL3
;
6484 return CP_ACCESS_OK
;
6487 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6490 if (arm_is_secure_below_el3(env
)) {
6491 /* Access ok in secure mode. */
6492 return CP_ACCESS_OK
;
6494 return access_lor_ns(env
);
6497 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6498 const ARMCPRegInfo
*ri
, bool isread
)
6500 if (arm_is_secure_below_el3(env
)) {
6501 /* Access denied in secure mode. */
6502 return CP_ACCESS_TRAP
;
6504 return access_lor_ns(env
);
6508 * A trivial implementation of ARMv8.1-LOR leaves all of these
6509 * registers fixed at 0, which indicates that there are zero
6510 * supported Limited Ordering regions.
6512 static const ARMCPRegInfo lor_reginfo
[] = {
6513 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6514 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6515 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6516 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6517 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6518 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6519 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6520 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6521 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6522 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6523 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6524 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6525 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6526 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6527 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6528 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6529 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6530 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6531 .access
= PL1_R
, .accessfn
= access_lorid
,
6532 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6536 #ifdef TARGET_AARCH64
6537 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6540 int el
= arm_current_el(env
);
6543 arm_feature(env
, ARM_FEATURE_EL2
) &&
6544 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6545 return CP_ACCESS_TRAP_EL2
;
6548 arm_feature(env
, ARM_FEATURE_EL3
) &&
6549 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6550 return CP_ACCESS_TRAP_EL3
;
6552 return CP_ACCESS_OK
;
6555 static const ARMCPRegInfo pauth_reginfo
[] = {
6556 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6557 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6558 .access
= PL1_RW
, .accessfn
= access_pauth
,
6559 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6560 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6561 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6562 .access
= PL1_RW
, .accessfn
= access_pauth
,
6563 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6564 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6565 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6566 .access
= PL1_RW
, .accessfn
= access_pauth
,
6567 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6568 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6569 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6570 .access
= PL1_RW
, .accessfn
= access_pauth
,
6571 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6572 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6573 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6574 .access
= PL1_RW
, .accessfn
= access_pauth
,
6575 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6576 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6577 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6578 .access
= PL1_RW
, .accessfn
= access_pauth
,
6579 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6580 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6581 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6582 .access
= PL1_RW
, .accessfn
= access_pauth
,
6583 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6584 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6585 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6586 .access
= PL1_RW
, .accessfn
= access_pauth
,
6587 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6588 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6589 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6590 .access
= PL1_RW
, .accessfn
= access_pauth
,
6591 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6592 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6593 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6594 .access
= PL1_RW
, .accessfn
= access_pauth
,
6595 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6599 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6604 /* Success sets NZCV = 0000. */
6605 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
6607 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
6609 * ??? Failed, for unknown reasons in the crypto subsystem.
6610 * The best we can do is log the reason and return the
6611 * timed-out indication to the guest. There is no reason
6612 * we know to expect this failure to be transitory, so the
6613 * guest may well hang retrying the operation.
6615 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
6616 ri
->name
, error_get_pretty(err
));
6619 env
->ZF
= 0; /* NZCF = 0100 */
6625 /* We do not support re-seeding, so the two registers operate the same. */
6626 static const ARMCPRegInfo rndr_reginfo
[] = {
6627 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
6628 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6629 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
6630 .access
= PL0_R
, .readfn
= rndr_readfn
},
6631 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
6632 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6633 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
6634 .access
= PL0_R
, .readfn
= rndr_readfn
},
6638 #ifndef CONFIG_USER_ONLY
6639 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
6642 ARMCPU
*cpu
= env_archcpu(env
);
6643 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6644 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
6645 uint64_t vaddr_in
= (uint64_t) value
;
6646 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
6648 int mem_idx
= cpu_mmu_index(env
, false);
6650 /* This won't be crossing page boundaries */
6651 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
6657 /* RCU lock is already being held */
6658 mr
= memory_region_from_host(haddr
, &offset
);
6661 memory_region_do_writeback(mr
, offset
, dline_size
);
6666 static const ARMCPRegInfo dcpop_reg
[] = {
6667 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
6668 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
6669 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6670 .accessfn
= aa64_cacheop_access
, .writefn
= dccvap_writefn
},
6674 static const ARMCPRegInfo dcpodp_reg
[] = {
6675 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
6676 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
6677 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6678 .accessfn
= aa64_cacheop_access
, .writefn
= dccvap_writefn
},
6681 #endif /*CONFIG_USER_ONLY*/
6685 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6688 int el
= arm_current_el(env
);
6691 uint64_t sctlr
= arm_sctlr(env
, el
);
6692 if (!(sctlr
& SCTLR_EnRCTX
)) {
6693 return CP_ACCESS_TRAP
;
6695 } else if (el
== 1) {
6696 uint64_t hcr
= arm_hcr_el2_eff(env
);
6698 return CP_ACCESS_TRAP_EL2
;
6701 return CP_ACCESS_OK
;
6704 static const ARMCPRegInfo predinv_reginfo
[] = {
6705 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
6706 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
6707 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6708 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
6709 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
6710 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6711 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
6712 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
6713 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6715 * Note the AArch32 opcodes have a different OPC1.
6717 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
6718 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
6719 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6720 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
6721 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
6722 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6723 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
6724 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
6725 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6729 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6731 /* Read the high 32 bits of the current CCSIDR */
6732 return extract64(ccsidr_read(env
, ri
), 32, 32);
6735 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
6736 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
6737 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
6739 .accessfn
= access_aa64_tid2
,
6740 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
6744 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6747 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
6748 return CP_ACCESS_TRAP_EL2
;
6751 return CP_ACCESS_OK
;
6754 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6757 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6758 return access_aa64_tid3(env
, ri
, isread
);
6761 return CP_ACCESS_OK
;
6764 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6767 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
6768 return CP_ACCESS_TRAP_EL2
;
6771 return CP_ACCESS_OK
;
6774 static const ARMCPRegInfo jazelle_regs
[] = {
6776 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
6777 .access
= PL1_R
, .accessfn
= access_jazelle
,
6778 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6780 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
6781 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6783 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
6784 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6788 static const ARMCPRegInfo vhe_reginfo
[] = {
6789 { .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6790 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
6792 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2]) },
6793 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
6794 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
6795 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
6796 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
6797 #ifndef CONFIG_USER_ONLY
6798 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6799 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
6801 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
6802 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6803 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
6804 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6805 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
6806 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6807 .resetfn
= gt_hv_timer_reset
,
6808 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
6809 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6811 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
6813 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
6814 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
6815 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
6816 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
6817 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6818 .access
= PL2_RW
, .accessfn
= e2h_access
,
6819 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
6820 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
6821 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
6822 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
6823 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6824 .access
= PL2_RW
, .accessfn
= e2h_access
,
6825 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
6826 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
6827 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6828 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
6829 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
6830 .access
= PL2_RW
, .accessfn
= e2h_access
,
6831 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
6832 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6833 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
6834 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
6835 .access
= PL2_RW
, .accessfn
= e2h_access
,
6836 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
6837 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6838 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
6839 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6840 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
6841 .access
= PL2_RW
, .accessfn
= e2h_access
,
6842 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
6843 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6844 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
6845 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6846 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
6847 .access
= PL2_RW
, .accessfn
= e2h_access
,
6848 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
6853 #ifndef CONFIG_USER_ONLY
6854 static const ARMCPRegInfo ats1e1_reginfo
[] = {
6855 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
6856 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
6857 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
6858 .writefn
= ats_write64
},
6859 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
6860 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
6861 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
6862 .writefn
= ats_write64
},
6866 static const ARMCPRegInfo ats1cp_reginfo
[] = {
6867 { .name
= "ATS1CPRP",
6868 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
6869 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
6870 .writefn
= ats_write
},
6871 { .name
= "ATS1CPWP",
6872 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
6873 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
6874 .writefn
= ats_write
},
6880 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
6881 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
6882 * is non-zero, which is never for ARMv7, optionally in ARMv8
6883 * and mandatorily for ARMv8.2 and up.
6884 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
6885 * implementation is RAZ/WI we can ignore this detail, as we
6888 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
6889 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
6890 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
6891 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
6893 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
6894 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
6895 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6900 void register_cp_regs_for_features(ARMCPU
*cpu
)
6902 /* Register all the coprocessor registers based on feature bits */
6903 CPUARMState
*env
= &cpu
->env
;
6904 if (arm_feature(env
, ARM_FEATURE_M
)) {
6905 /* M profile has no coprocessor registers */
6909 define_arm_cp_regs(cpu
, cp_reginfo
);
6910 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
6911 /* Must go early as it is full of wildcards that may be
6912 * overridden by later definitions.
6914 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
6917 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6918 /* The ID registers all have impdef reset values */
6919 ARMCPRegInfo v6_idregs
[] = {
6920 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
6921 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6922 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6923 .accessfn
= access_aa32_tid3
,
6924 .resetvalue
= cpu
->id_pfr0
},
6925 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
6926 * the value of the GIC field until after we define these regs.
6928 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
6929 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
6930 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6931 .accessfn
= access_aa32_tid3
,
6932 .readfn
= id_pfr1_read
,
6933 .writefn
= arm_cp_write_ignore
},
6934 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
6935 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
6936 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6937 .accessfn
= access_aa32_tid3
,
6938 .resetvalue
= cpu
->isar
.id_dfr0
},
6939 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
6940 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
6941 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6942 .accessfn
= access_aa32_tid3
,
6943 .resetvalue
= cpu
->id_afr0
},
6944 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
6945 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
6946 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6947 .accessfn
= access_aa32_tid3
,
6948 .resetvalue
= cpu
->isar
.id_mmfr0
},
6949 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
6950 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
6951 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6952 .accessfn
= access_aa32_tid3
,
6953 .resetvalue
= cpu
->isar
.id_mmfr1
},
6954 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
6955 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
6956 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6957 .accessfn
= access_aa32_tid3
,
6958 .resetvalue
= cpu
->isar
.id_mmfr2
},
6959 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
6960 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
6961 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6962 .accessfn
= access_aa32_tid3
,
6963 .resetvalue
= cpu
->isar
.id_mmfr3
},
6964 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
6965 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6966 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6967 .accessfn
= access_aa32_tid3
,
6968 .resetvalue
= cpu
->isar
.id_isar0
},
6969 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
6970 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
6971 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6972 .accessfn
= access_aa32_tid3
,
6973 .resetvalue
= cpu
->isar
.id_isar1
},
6974 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
6975 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6976 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6977 .accessfn
= access_aa32_tid3
,
6978 .resetvalue
= cpu
->isar
.id_isar2
},
6979 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
6980 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
6981 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6982 .accessfn
= access_aa32_tid3
,
6983 .resetvalue
= cpu
->isar
.id_isar3
},
6984 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
6985 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
6986 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6987 .accessfn
= access_aa32_tid3
,
6988 .resetvalue
= cpu
->isar
.id_isar4
},
6989 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
6990 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
6991 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6992 .accessfn
= access_aa32_tid3
,
6993 .resetvalue
= cpu
->isar
.id_isar5
},
6994 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
6995 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
6996 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6997 .accessfn
= access_aa32_tid3
,
6998 .resetvalue
= cpu
->isar
.id_mmfr4
},
6999 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7000 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7001 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7002 .accessfn
= access_aa32_tid3
,
7003 .resetvalue
= cpu
->isar
.id_isar6
},
7006 define_arm_cp_regs(cpu
, v6_idregs
);
7007 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7009 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7011 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7012 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7014 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7015 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7016 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7018 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7019 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7021 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7022 ARMCPRegInfo clidr
= {
7023 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7024 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7025 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7026 .accessfn
= access_aa64_tid2
,
7027 .resetvalue
= cpu
->clidr
7029 define_one_arm_cp_reg(cpu
, &clidr
);
7030 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7031 define_debug_regs(cpu
);
7032 define_pmu_regs(cpu
);
7034 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7036 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7037 /* AArch64 ID registers, which all have impdef reset values.
7038 * Note that within the ID register ranges the unused slots
7039 * must all RAZ, not UNDEF; future architecture versions may
7040 * define new registers here.
7042 ARMCPRegInfo v8_idregs
[] = {
7043 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
7044 * know the right value for the GIC field until after we
7045 * define these regs.
7047 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7048 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7049 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7050 .accessfn
= access_aa64_tid3
,
7051 .readfn
= id_aa64pfr0_read
,
7052 .writefn
= arm_cp_write_ignore
},
7053 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7056 .accessfn
= access_aa64_tid3
,
7057 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7058 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7059 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7060 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7061 .accessfn
= access_aa64_tid3
,
7063 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7064 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7065 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7066 .accessfn
= access_aa64_tid3
,
7068 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7069 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7070 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7071 .accessfn
= access_aa64_tid3
,
7072 /* At present, only SVEver == 0 is defined anyway. */
7074 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7075 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7076 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7077 .accessfn
= access_aa64_tid3
,
7079 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7080 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7081 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7082 .accessfn
= access_aa64_tid3
,
7084 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7085 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7086 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7087 .accessfn
= access_aa64_tid3
,
7089 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7090 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7091 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7092 .accessfn
= access_aa64_tid3
,
7093 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7094 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7095 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7096 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7097 .accessfn
= access_aa64_tid3
,
7098 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7099 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7100 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7101 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7102 .accessfn
= access_aa64_tid3
,
7104 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7105 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7106 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7107 .accessfn
= access_aa64_tid3
,
7109 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7110 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7111 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7112 .accessfn
= access_aa64_tid3
,
7113 .resetvalue
= cpu
->id_aa64afr0
},
7114 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7115 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7116 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7117 .accessfn
= access_aa64_tid3
,
7118 .resetvalue
= cpu
->id_aa64afr1
},
7119 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7120 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7121 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7122 .accessfn
= access_aa64_tid3
,
7124 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7125 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7126 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7127 .accessfn
= access_aa64_tid3
,
7129 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7130 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7131 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7132 .accessfn
= access_aa64_tid3
,
7133 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7134 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7135 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7136 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7137 .accessfn
= access_aa64_tid3
,
7138 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7139 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7140 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7141 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7142 .accessfn
= access_aa64_tid3
,
7144 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7145 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7146 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7147 .accessfn
= access_aa64_tid3
,
7149 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7150 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7151 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7152 .accessfn
= access_aa64_tid3
,
7154 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7155 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7156 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7157 .accessfn
= access_aa64_tid3
,
7159 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7160 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7161 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7162 .accessfn
= access_aa64_tid3
,
7164 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7165 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7166 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7167 .accessfn
= access_aa64_tid3
,
7169 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7170 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7171 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7172 .accessfn
= access_aa64_tid3
,
7173 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7174 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7175 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7176 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7177 .accessfn
= access_aa64_tid3
,
7178 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7179 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7180 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7181 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7182 .accessfn
= access_aa64_tid3
,
7183 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7184 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7185 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7186 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7187 .accessfn
= access_aa64_tid3
,
7189 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7190 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7191 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7192 .accessfn
= access_aa64_tid3
,
7194 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7195 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7196 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7197 .accessfn
= access_aa64_tid3
,
7199 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7200 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7201 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7202 .accessfn
= access_aa64_tid3
,
7204 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7205 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7206 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7207 .accessfn
= access_aa64_tid3
,
7209 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7210 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7211 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7212 .accessfn
= access_aa64_tid3
,
7213 .resetvalue
= cpu
->isar
.mvfr0
},
7214 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7215 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7216 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7217 .accessfn
= access_aa64_tid3
,
7218 .resetvalue
= cpu
->isar
.mvfr1
},
7219 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7220 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7221 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7222 .accessfn
= access_aa64_tid3
,
7223 .resetvalue
= cpu
->isar
.mvfr2
},
7224 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7225 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7226 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7227 .accessfn
= access_aa64_tid3
,
7229 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7230 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7231 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7232 .accessfn
= access_aa64_tid3
,
7234 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7235 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7236 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7237 .accessfn
= access_aa64_tid3
,
7239 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7240 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7241 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7242 .accessfn
= access_aa64_tid3
,
7244 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7245 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7246 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7247 .accessfn
= access_aa64_tid3
,
7249 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7250 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7251 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7252 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7253 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7254 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7255 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7256 .resetvalue
= cpu
->pmceid0
},
7257 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7258 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7259 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7260 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7261 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7262 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7263 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7264 .resetvalue
= cpu
->pmceid1
},
7267 #ifdef CONFIG_USER_ONLY
7268 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7269 { .name
= "ID_AA64PFR0_EL1",
7270 .exported_bits
= 0x000f000f00ff0000,
7271 .fixed_bits
= 0x0000000000000011 },
7272 { .name
= "ID_AA64PFR1_EL1",
7273 .exported_bits
= 0x00000000000000f0 },
7274 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7276 { .name
= "ID_AA64ZFR0_EL1" },
7277 { .name
= "ID_AA64MMFR0_EL1",
7278 .fixed_bits
= 0x00000000ff000000 },
7279 { .name
= "ID_AA64MMFR1_EL1" },
7280 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7282 { .name
= "ID_AA64DFR0_EL1",
7283 .fixed_bits
= 0x0000000000000006 },
7284 { .name
= "ID_AA64DFR1_EL1" },
7285 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7287 { .name
= "ID_AA64AFR*",
7289 { .name
= "ID_AA64ISAR0_EL1",
7290 .exported_bits
= 0x00fffffff0fffff0 },
7291 { .name
= "ID_AA64ISAR1_EL1",
7292 .exported_bits
= 0x000000f0ffffffff },
7293 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7295 REGUSERINFO_SENTINEL
7297 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7299 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7300 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7301 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7302 ARMCPRegInfo rvbar
= {
7303 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7304 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7305 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
7307 define_one_arm_cp_reg(cpu
, &rvbar
);
7309 define_arm_cp_regs(cpu
, v8_idregs
);
7310 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7312 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7313 uint64_t vmpidr_def
= mpidr_read_val(env
);
7314 ARMCPRegInfo vpidr_regs
[] = {
7315 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7316 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7317 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7318 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
7319 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7320 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7321 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7322 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7323 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7324 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7325 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7326 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7327 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
7328 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7329 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7330 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7332 .resetvalue
= vmpidr_def
,
7333 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7336 define_arm_cp_regs(cpu
, vpidr_regs
);
7337 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7338 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7339 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7341 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7342 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7343 ARMCPRegInfo rvbar
= {
7344 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7345 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7346 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
7348 define_one_arm_cp_reg(cpu
, &rvbar
);
7351 /* If EL2 is missing but higher ELs are enabled, we need to
7352 * register the no_el2 reginfos.
7354 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7355 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7356 * of MIDR_EL1 and MPIDR_EL1.
7358 ARMCPRegInfo vpidr_regs
[] = {
7359 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7360 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7361 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
7362 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
7363 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7364 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7365 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7366 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
7367 .type
= ARM_CP_NO_RAW
,
7368 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
7371 define_arm_cp_regs(cpu
, vpidr_regs
);
7372 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
7373 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7374 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
7378 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7379 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7380 ARMCPRegInfo el3_regs
[] = {
7381 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7382 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7383 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
7384 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7385 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7387 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7388 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7389 .resetvalue
= cpu
->reset_sctlr
},
7393 define_arm_cp_regs(cpu
, el3_regs
);
7395 /* The behaviour of NSACR is sufficiently various that we don't
7396 * try to describe it in a single reginfo:
7397 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7398 * reads as constant 0xc00 from NS EL1 and NS EL2
7399 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7400 * if v7 without EL3, register doesn't exist
7401 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7403 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7404 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7405 ARMCPRegInfo nsacr
= {
7406 .name
= "NSACR", .type
= ARM_CP_CONST
,
7407 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7408 .access
= PL1_RW
, .accessfn
= nsacr_access
,
7411 define_one_arm_cp_reg(cpu
, &nsacr
);
7413 ARMCPRegInfo nsacr
= {
7415 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7416 .access
= PL3_RW
| PL1_R
,
7418 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
7420 define_one_arm_cp_reg(cpu
, &nsacr
);
7423 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7424 ARMCPRegInfo nsacr
= {
7425 .name
= "NSACR", .type
= ARM_CP_CONST
,
7426 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7430 define_one_arm_cp_reg(cpu
, &nsacr
);
7434 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
7435 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7436 /* PMSAv6 not implemented */
7437 assert(arm_feature(env
, ARM_FEATURE_V7
));
7438 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7439 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
7441 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
7444 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7445 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
7446 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7447 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
7448 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
7451 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
7452 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
7454 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
7455 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
7457 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
7458 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
7460 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
7461 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
7463 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
7464 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
7466 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
7467 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
7469 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
7470 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
7472 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7473 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
7475 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7476 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
7478 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
7479 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
7481 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
7482 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
7484 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
7485 define_arm_cp_regs(cpu
, jazelle_regs
);
7487 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7488 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7489 * be read-only (ie write causes UNDEF exception).
7492 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
7493 /* Pre-v8 MIDR space.
7494 * Note that the MIDR isn't a simple constant register because
7495 * of the TI925 behaviour where writes to another register can
7496 * cause the MIDR value to change.
7498 * Unimplemented registers in the c15 0 0 0 space default to
7499 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7500 * and friends override accordingly.
7503 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
7504 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
7505 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
7506 .readfn
= midr_read
,
7507 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7508 .type
= ARM_CP_OVERRIDE
},
7509 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7511 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
7512 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7514 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
7515 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7517 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
7518 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7520 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
7521 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7523 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
7524 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7527 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
7528 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7529 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
7530 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
7531 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7532 .readfn
= midr_read
},
7533 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7534 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7535 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7536 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7537 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7538 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
7539 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7540 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7541 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
7543 .accessfn
= access_aa64_tid1
,
7544 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
7547 ARMCPRegInfo id_cp_reginfo
[] = {
7548 /* These are common to v8 and pre-v8 */
7550 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
7551 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
7552 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7553 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
7554 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
7555 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
7556 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7557 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7559 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
7561 .accessfn
= access_aa32_tid1
,
7562 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7565 /* TLBTR is specific to VMSA */
7566 ARMCPRegInfo id_tlbtr_reginfo
= {
7568 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
7570 .accessfn
= access_aa32_tid1
,
7571 .type
= ARM_CP_CONST
, .resetvalue
= 0,
7573 /* MPUIR is specific to PMSA V6+ */
7574 ARMCPRegInfo id_mpuir_reginfo
= {
7576 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7577 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7578 .resetvalue
= cpu
->pmsav7_dregion
<< 8
7580 ARMCPRegInfo crn0_wi_reginfo
= {
7581 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
7582 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
7583 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
7585 #ifdef CONFIG_USER_ONLY
7586 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
7587 { .name
= "MIDR_EL1",
7588 .exported_bits
= 0x00000000ffffffff },
7589 { .name
= "REVIDR_EL1" },
7590 REGUSERINFO_SENTINEL
7592 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
7594 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
7595 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7597 /* Register the blanket "writes ignored" value first to cover the
7598 * whole space. Then update the specific ID registers to allow write
7599 * access, so that they ignore writes rather than causing them to
7602 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
7603 for (r
= id_pre_v8_midr_cp_reginfo
;
7604 r
->type
!= ARM_CP_SENTINEL
; r
++) {
7607 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7610 id_mpuir_reginfo
.access
= PL1_RW
;
7611 id_tlbtr_reginfo
.access
= PL1_RW
;
7613 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7614 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
7616 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
7618 define_arm_cp_regs(cpu
, id_cp_reginfo
);
7619 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
7620 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
7621 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
7622 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
7626 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
7627 ARMCPRegInfo mpidr_cp_reginfo
[] = {
7628 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7629 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
7630 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
7633 #ifdef CONFIG_USER_ONLY
7634 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
7635 { .name
= "MPIDR_EL1",
7636 .fixed_bits
= 0x0000000080000000 },
7637 REGUSERINFO_SENTINEL
7639 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
7641 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
7644 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
7645 ARMCPRegInfo auxcr_reginfo
[] = {
7646 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
7647 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
7648 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
7649 .resetvalue
= cpu
->reset_auxcr
},
7650 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
7651 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
7652 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7654 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7655 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
7656 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
7660 define_arm_cp_regs(cpu
, auxcr_reginfo
);
7661 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
7662 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
7666 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
7668 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
7669 * There are two flavours:
7670 * (1) older 32-bit only cores have a simple 32-bit CBAR
7671 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
7672 * 32-bit register visible to AArch32 at a different encoding
7673 * to the "flavour 1" register and with the bits rearranged to
7674 * be able to squash a 64-bit address into the 32-bit view.
7675 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
7676 * in future if we support AArch32-only configs of some of the
7677 * AArch64 cores we might need to add a specific feature flag
7678 * to indicate cores with "flavour 2" CBAR.
7680 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7681 /* 32 bit view is [31:18] 0...0 [43:32]. */
7682 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
7683 | extract64(cpu
->reset_cbar
, 32, 12);
7684 ARMCPRegInfo cbar_reginfo
[] = {
7686 .type
= ARM_CP_CONST
,
7687 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
7688 .access
= PL1_R
, .resetvalue
= cbar32
},
7689 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7690 .type
= ARM_CP_CONST
,
7691 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
7692 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
7695 /* We don't implement a r/w 64 bit CBAR currently */
7696 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
7697 define_arm_cp_regs(cpu
, cbar_reginfo
);
7699 ARMCPRegInfo cbar
= {
7701 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
7702 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
7703 .fieldoffset
= offsetof(CPUARMState
,
7704 cp15
.c15_config_base_address
)
7706 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
7707 cbar
.access
= PL1_R
;
7708 cbar
.fieldoffset
= 0;
7709 cbar
.type
= ARM_CP_CONST
;
7711 define_one_arm_cp_reg(cpu
, &cbar
);
7715 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
7716 ARMCPRegInfo vbar_cp_reginfo
[] = {
7717 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
7718 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
7719 .access
= PL1_RW
, .writefn
= vbar_write
,
7720 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
7721 offsetof(CPUARMState
, cp15
.vbar_ns
) },
7725 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
7728 /* Generic registers whose values depend on the implementation */
7730 ARMCPRegInfo sctlr
= {
7731 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
7732 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
7734 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
7735 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
7736 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
7737 .raw_writefn
= raw_write
,
7739 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7740 /* Normally we would always end the TB on an SCTLR write, but Linux
7741 * arch/arm/mach-pxa/sleep.S expects two instructions following
7742 * an MMU enable to execute from cache. Imitate this behaviour.
7744 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
7746 define_one_arm_cp_reg(cpu
, &sctlr
);
7749 if (cpu_isar_feature(aa64_lor
, cpu
)) {
7750 define_arm_cp_regs(cpu
, lor_reginfo
);
7752 if (cpu_isar_feature(aa64_pan
, cpu
)) {
7753 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
7755 #ifndef CONFIG_USER_ONLY
7756 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
7757 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
7759 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
7760 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
7763 if (cpu_isar_feature(aa64_uao
, cpu
)) {
7764 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
7767 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
7768 define_arm_cp_regs(cpu
, vhe_reginfo
);
7771 if (cpu_isar_feature(aa64_sve
, cpu
)) {
7772 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
7773 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7774 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
7776 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
7778 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7779 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
7783 #ifdef TARGET_AARCH64
7784 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
7785 define_arm_cp_regs(cpu
, pauth_reginfo
);
7787 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
7788 define_arm_cp_regs(cpu
, rndr_reginfo
);
7790 #ifndef CONFIG_USER_ONLY
7791 /* Data Cache clean instructions up to PoP */
7792 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
7793 define_one_arm_cp_reg(cpu
, dcpop_reg
);
7795 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
7796 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
7799 #endif /*CONFIG_USER_ONLY*/
7802 if (cpu_isar_feature(any_predinv
, cpu
)) {
7803 define_arm_cp_regs(cpu
, predinv_reginfo
);
7806 if (cpu_isar_feature(any_ccidx
, cpu
)) {
7807 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
7810 #ifndef CONFIG_USER_ONLY
7812 * Register redirections and aliases must be done last,
7813 * after the registers from the other extensions have been defined.
7815 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
7816 define_arm_vh_e2h_redirects_aliases(cpu
);
7821 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
7823 CPUState
*cs
= CPU(cpu
);
7824 CPUARMState
*env
= &cpu
->env
;
7826 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7827 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
7828 aarch64_fpu_gdb_set_reg
,
7829 34, "aarch64-fpu.xml", 0);
7830 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
7831 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7832 51, "arm-neon.xml", 0);
7833 } else if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
7834 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7835 35, "arm-vfp3.xml", 0);
7836 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
7837 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7838 19, "arm-vfp.xml", 0);
7840 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
7841 arm_gen_dynamic_xml(cs
),
7842 "system-registers.xml", 0);
7845 /* Sort alphabetically by type name, except for "any". */
7846 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
7848 ObjectClass
*class_a
= (ObjectClass
*)a
;
7849 ObjectClass
*class_b
= (ObjectClass
*)b
;
7850 const char *name_a
, *name_b
;
7852 name_a
= object_class_get_name(class_a
);
7853 name_b
= object_class_get_name(class_b
);
7854 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
7856 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
7859 return strcmp(name_a
, name_b
);
7863 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
7865 ObjectClass
*oc
= data
;
7866 const char *typename
;
7869 typename
= object_class_get_name(oc
);
7870 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
7871 qemu_printf(" %s\n", name
);
7875 void arm_cpu_list(void)
7879 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7880 list
= g_slist_sort(list
, arm_cpu_list_compare
);
7881 qemu_printf("Available CPUs:\n");
7882 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
7886 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
7888 ObjectClass
*oc
= data
;
7889 CpuDefinitionInfoList
**cpu_list
= user_data
;
7890 CpuDefinitionInfoList
*entry
;
7891 CpuDefinitionInfo
*info
;
7892 const char *typename
;
7894 typename
= object_class_get_name(oc
);
7895 info
= g_malloc0(sizeof(*info
));
7896 info
->name
= g_strndup(typename
,
7897 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
7898 info
->q_typename
= g_strdup(typename
);
7900 entry
= g_malloc0(sizeof(*entry
));
7901 entry
->value
= info
;
7902 entry
->next
= *cpu_list
;
7906 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
7908 CpuDefinitionInfoList
*cpu_list
= NULL
;
7911 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7912 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
7918 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
7919 void *opaque
, int state
, int secstate
,
7920 int crm
, int opc1
, int opc2
,
7923 /* Private utility function for define_one_arm_cp_reg_with_opaque():
7924 * add a single reginfo struct to the hash table.
7926 uint32_t *key
= g_new(uint32_t, 1);
7927 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
7928 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
7929 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
7931 r2
->name
= g_strdup(name
);
7932 /* Reset the secure state to the specific incoming state. This is
7933 * necessary as the register may have been defined with both states.
7935 r2
->secure
= secstate
;
7937 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7938 /* Register is banked (using both entries in array).
7939 * Overwriting fieldoffset as the array is only used to define
7940 * banked registers but later only fieldoffset is used.
7942 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
7945 if (state
== ARM_CP_STATE_AA32
) {
7946 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7947 /* If the register is banked then we don't need to migrate or
7948 * reset the 32-bit instance in certain cases:
7950 * 1) If the register has both 32-bit and 64-bit instances then we
7951 * can count on the 64-bit instance taking care of the
7953 * 2) If ARMv8 is enabled then we can count on a 64-bit version
7954 * taking care of the secure bank. This requires that separate
7955 * 32 and 64-bit definitions are provided.
7957 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
7958 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
7959 r2
->type
|= ARM_CP_ALIAS
;
7961 } else if ((secstate
!= r
->secure
) && !ns
) {
7962 /* The register is not banked so we only want to allow migration of
7963 * the non-secure instance.
7965 r2
->type
|= ARM_CP_ALIAS
;
7968 if (r
->state
== ARM_CP_STATE_BOTH
) {
7969 /* We assume it is a cp15 register if the .cp field is left unset.
7975 #ifdef HOST_WORDS_BIGENDIAN
7976 if (r2
->fieldoffset
) {
7977 r2
->fieldoffset
+= sizeof(uint32_t);
7982 if (state
== ARM_CP_STATE_AA64
) {
7983 /* To allow abbreviation of ARMCPRegInfo
7984 * definitions, we treat cp == 0 as equivalent to
7985 * the value for "standard guest-visible sysreg".
7986 * STATE_BOTH definitions are also always "standard
7987 * sysreg" in their AArch64 view (the .cp value may
7988 * be non-zero for the benefit of the AArch32 view).
7990 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
7991 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
7993 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
7994 r2
->opc0
, opc1
, opc2
);
7996 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
7999 r2
->opaque
= opaque
;
8001 /* reginfo passed to helpers is correct for the actual access,
8002 * and is never ARM_CP_STATE_BOTH:
8005 /* Make sure reginfo passed to helpers for wildcarded regs
8006 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8011 /* By convention, for wildcarded registers only the first
8012 * entry is used for migration; the others are marked as
8013 * ALIAS so we don't try to transfer the register
8014 * multiple times. Special registers (ie NOP/WFI) are
8015 * never migratable and not even raw-accessible.
8017 if ((r
->type
& ARM_CP_SPECIAL
)) {
8018 r2
->type
|= ARM_CP_NO_RAW
;
8020 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8021 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8022 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8023 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8026 /* Check that raw accesses are either forbidden or handled. Note that
8027 * we can't assert this earlier because the setup of fieldoffset for
8028 * banked registers has to be done first.
8030 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8031 assert(!raw_accessors_invalid(r2
));
8034 /* Overriding of an existing definition must be explicitly
8037 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8038 ARMCPRegInfo
*oldreg
;
8039 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
8040 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
8041 fprintf(stderr
, "Register redefined: cp=%d %d bit "
8042 "crn=%d crm=%d opc1=%d opc2=%d, "
8043 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
8044 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
8045 oldreg
->name
, r2
->name
);
8046 g_assert_not_reached();
8049 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
8053 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8054 const ARMCPRegInfo
*r
, void *opaque
)
8056 /* Define implementations of coprocessor registers.
8057 * We store these in a hashtable because typically
8058 * there are less than 150 registers in a space which
8059 * is 16*16*16*8*8 = 262144 in size.
8060 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8061 * If a register is defined twice then the second definition is
8062 * used, so this can be used to define some generic registers and
8063 * then override them with implementation specific variations.
8064 * At least one of the original and the second definition should
8065 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8066 * against accidental use.
8068 * The state field defines whether the register is to be
8069 * visible in the AArch32 or AArch64 execution state. If the
8070 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8071 * reginfo structure for the AArch32 view, which sees the lower
8072 * 32 bits of the 64 bit register.
8074 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8075 * be wildcarded. AArch64 registers are always considered to be 64
8076 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8077 * the register, if any.
8079 int crm
, opc1
, opc2
, state
;
8080 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8081 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8082 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8083 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8084 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8085 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8086 /* 64 bit registers have only CRm and Opc1 fields */
8087 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8088 /* op0 only exists in the AArch64 encodings */
8089 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8090 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8091 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8092 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8093 * encodes a minimum access level for the register. We roll this
8094 * runtime check into our general permission check code, so check
8095 * here that the reginfo's specified permissions are strict enough
8096 * to encompass the generic architectural permission check.
8098 if (r
->state
!= ARM_CP_STATE_AA32
) {
8102 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8103 mask
= PL0U_R
| PL1_RW
;
8123 /* min_EL EL1, secure mode only (we don't check the latter) */
8127 /* broken reginfo with out-of-range opc1 */
8131 /* assert our permissions are not too lax (stricter is fine) */
8132 assert((r
->access
& ~mask
) == 0);
8135 /* Check that the register definition has enough info to handle
8136 * reads and writes if they are permitted.
8138 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
8139 if (r
->access
& PL3_R
) {
8140 assert((r
->fieldoffset
||
8141 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8144 if (r
->access
& PL3_W
) {
8145 assert((r
->fieldoffset
||
8146 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8150 /* Bad type field probably means missing sentinel at end of reg list */
8151 assert(cptype_valid(r
->type
));
8152 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8153 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8154 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8155 for (state
= ARM_CP_STATE_AA32
;
8156 state
<= ARM_CP_STATE_AA64
; state
++) {
8157 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8160 if (state
== ARM_CP_STATE_AA32
) {
8161 /* Under AArch32 CP registers can be common
8162 * (same for secure and non-secure world) or banked.
8166 switch (r
->secure
) {
8167 case ARM_CP_SECSTATE_S
:
8168 case ARM_CP_SECSTATE_NS
:
8169 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8170 r
->secure
, crm
, opc1
, opc2
,
8174 name
= g_strdup_printf("%s_S", r
->name
);
8175 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8177 crm
, opc1
, opc2
, name
);
8179 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8181 crm
, opc1
, opc2
, r
->name
);
8185 /* AArch64 registers get mapped to non-secure instance
8187 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8189 crm
, opc1
, opc2
, r
->name
);
8197 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
8198 const ARMCPRegInfo
*regs
, void *opaque
)
8200 /* Define a whole list of registers */
8201 const ARMCPRegInfo
*r
;
8202 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8203 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
8208 * Modify ARMCPRegInfo for access from userspace.
8210 * This is a data driven modification directed by
8211 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8212 * user-space cannot alter any values and dynamic values pertaining to
8213 * execution state are hidden from user space view anyway.
8215 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
8217 const ARMCPRegUserSpaceInfo
*m
;
8220 for (m
= mods
; m
->name
; m
++) {
8221 GPatternSpec
*pat
= NULL
;
8223 pat
= g_pattern_spec_new(m
->name
);
8225 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8226 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8227 r
->type
= ARM_CP_CONST
;
8231 } else if (strcmp(r
->name
, m
->name
) == 0) {
8232 r
->type
= ARM_CP_CONST
;
8234 r
->resetvalue
&= m
->exported_bits
;
8235 r
->resetvalue
|= m
->fixed_bits
;
8240 g_pattern_spec_free(pat
);
8245 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8247 return g_hash_table_lookup(cpregs
, &encoded_cp
);
8250 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8253 /* Helper coprocessor write function for write-ignore registers */
8256 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8258 /* Helper coprocessor write function for read-as-zero registers */
8262 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8264 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8267 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8269 /* Return true if it is not valid for us to switch to
8270 * this CPU mode (ie all the UNPREDICTABLE cases in
8271 * the ARM ARM CPSRWriteByInstr pseudocode).
8274 /* Changes to or from Hyp via MSR and CPS are illegal. */
8275 if (write_type
== CPSRWriteByInstr
&&
8276 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8277 mode
== ARM_CPU_MODE_HYP
)) {
8282 case ARM_CPU_MODE_USR
:
8284 case ARM_CPU_MODE_SYS
:
8285 case ARM_CPU_MODE_SVC
:
8286 case ARM_CPU_MODE_ABT
:
8287 case ARM_CPU_MODE_UND
:
8288 case ARM_CPU_MODE_IRQ
:
8289 case ARM_CPU_MODE_FIQ
:
8290 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8291 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8293 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8294 * and CPS are treated as illegal mode changes.
8296 if (write_type
== CPSRWriteByInstr
&&
8297 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8298 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
8302 case ARM_CPU_MODE_HYP
:
8303 return !arm_feature(env
, ARM_FEATURE_EL2
)
8304 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
8305 case ARM_CPU_MODE_MON
:
8306 return arm_current_el(env
) < 3;
8312 uint32_t cpsr_read(CPUARMState
*env
)
8315 ZF
= (env
->ZF
== 0);
8316 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
8317 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
8318 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
8319 | ((env
->condexec_bits
& 0xfc) << 8)
8320 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
8323 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
8324 CPSRWriteType write_type
)
8326 uint32_t changed_daif
;
8328 if (mask
& CPSR_NZCV
) {
8329 env
->ZF
= (~val
) & CPSR_Z
;
8331 env
->CF
= (val
>> 29) & 1;
8332 env
->VF
= (val
<< 3) & 0x80000000;
8335 env
->QF
= ((val
& CPSR_Q
) != 0);
8337 env
->thumb
= ((val
& CPSR_T
) != 0);
8338 if (mask
& CPSR_IT_0_1
) {
8339 env
->condexec_bits
&= ~3;
8340 env
->condexec_bits
|= (val
>> 25) & 3;
8342 if (mask
& CPSR_IT_2_7
) {
8343 env
->condexec_bits
&= 3;
8344 env
->condexec_bits
|= (val
>> 8) & 0xfc;
8346 if (mask
& CPSR_GE
) {
8347 env
->GE
= (val
>> 16) & 0xf;
8350 /* In a V7 implementation that includes the security extensions but does
8351 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8352 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8353 * bits respectively.
8355 * In a V8 implementation, it is permitted for privileged software to
8356 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8358 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
8359 arm_feature(env
, ARM_FEATURE_EL3
) &&
8360 !arm_feature(env
, ARM_FEATURE_EL2
) &&
8361 !arm_is_secure(env
)) {
8363 changed_daif
= (env
->daif
^ val
) & mask
;
8365 if (changed_daif
& CPSR_A
) {
8366 /* Check to see if we are allowed to change the masking of async
8367 * abort exceptions from a non-secure state.
8369 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
8370 qemu_log_mask(LOG_GUEST_ERROR
,
8371 "Ignoring attempt to switch CPSR_A flag from "
8372 "non-secure world with SCR.AW bit clear\n");
8377 if (changed_daif
& CPSR_F
) {
8378 /* Check to see if we are allowed to change the masking of FIQ
8379 * exceptions from a non-secure state.
8381 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
8382 qemu_log_mask(LOG_GUEST_ERROR
,
8383 "Ignoring attempt to switch CPSR_F flag from "
8384 "non-secure world with SCR.FW bit clear\n");
8388 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8389 * If this bit is set software is not allowed to mask
8390 * FIQs, but is allowed to set CPSR_F to 0.
8392 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
8394 qemu_log_mask(LOG_GUEST_ERROR
,
8395 "Ignoring attempt to enable CPSR_F flag "
8396 "(non-maskable FIQ [NMFI] support enabled)\n");
8402 env
->daif
&= ~(CPSR_AIF
& mask
);
8403 env
->daif
|= val
& CPSR_AIF
& mask
;
8405 if (write_type
!= CPSRWriteRaw
&&
8406 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
8407 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
8408 /* Note that we can only get here in USR mode if this is a
8409 * gdb stub write; for this case we follow the architectural
8410 * behaviour for guest writes in USR mode of ignoring an attempt
8411 * to switch mode. (Those are caught by translate.c for writes
8412 * triggered by guest instructions.)
8415 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
8416 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8417 * v7, and has defined behaviour in v8:
8418 * + leave CPSR.M untouched
8419 * + allow changes to the other CPSR fields
8421 * For user changes via the GDB stub, we don't set PSTATE.IL,
8422 * as this would be unnecessarily harsh for a user error.
8425 if (write_type
!= CPSRWriteByGDBStub
&&
8426 arm_feature(env
, ARM_FEATURE_V8
)) {
8430 qemu_log_mask(LOG_GUEST_ERROR
,
8431 "Illegal AArch32 mode switch attempt from %s to %s\n",
8432 aarch32_mode_name(env
->uncached_cpsr
),
8433 aarch32_mode_name(val
));
8435 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
8436 write_type
== CPSRWriteExceptionReturn
?
8437 "Exception return from AArch32" :
8438 "AArch32 mode switch from",
8439 aarch32_mode_name(env
->uncached_cpsr
),
8440 aarch32_mode_name(val
), env
->regs
[15]);
8441 switch_mode(env
, val
& CPSR_M
);
8444 mask
&= ~CACHED_CPSR_BITS
;
8445 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
8448 /* Sign/zero extend */
8449 uint32_t HELPER(sxtb16
)(uint32_t x
)
8452 res
= (uint16_t)(int8_t)x
;
8453 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
8457 uint32_t HELPER(uxtb16
)(uint32_t x
)
8460 res
= (uint16_t)(uint8_t)x
;
8461 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
8465 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
8469 if (num
== INT_MIN
&& den
== -1)
8474 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
8481 uint32_t HELPER(rbit
)(uint32_t x
)
8486 #ifdef CONFIG_USER_ONLY
8488 static void switch_mode(CPUARMState
*env
, int mode
)
8490 ARMCPU
*cpu
= env_archcpu(env
);
8492 if (mode
!= ARM_CPU_MODE_USR
) {
8493 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
8497 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8498 uint32_t cur_el
, bool secure
)
8503 void aarch64_sync_64_to_32(CPUARMState
*env
)
8505 g_assert_not_reached();
8510 static void switch_mode(CPUARMState
*env
, int mode
)
8515 old_mode
= env
->uncached_cpsr
& CPSR_M
;
8516 if (mode
== old_mode
)
8519 if (old_mode
== ARM_CPU_MODE_FIQ
) {
8520 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8521 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
8522 } else if (mode
== ARM_CPU_MODE_FIQ
) {
8523 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8524 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
8527 i
= bank_number(old_mode
);
8528 env
->banked_r13
[i
] = env
->regs
[13];
8529 env
->banked_spsr
[i
] = env
->spsr
;
8531 i
= bank_number(mode
);
8532 env
->regs
[13] = env
->banked_r13
[i
];
8533 env
->spsr
= env
->banked_spsr
[i
];
8535 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
8536 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
8539 /* Physical Interrupt Target EL Lookup Table
8541 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
8543 * The below multi-dimensional table is used for looking up the target
8544 * exception level given numerous condition criteria. Specifically, the
8545 * target EL is based on SCR and HCR routing controls as well as the
8546 * currently executing EL and secure state.
8549 * target_el_table[2][2][2][2][2][4]
8550 * | | | | | +--- Current EL
8551 * | | | | +------ Non-secure(0)/Secure(1)
8552 * | | | +--------- HCR mask override
8553 * | | +------------ SCR exec state control
8554 * | +--------------- SCR mask override
8555 * +------------------ 32-bit(0)/64-bit(1) EL3
8557 * The table values are as such:
8561 * The ARM ARM target EL table includes entries indicating that an "exception
8562 * is not taken". The two cases where this is applicable are:
8563 * 1) An exception is taken from EL3 but the SCR does not have the exception
8565 * 2) An exception is taken from EL2 but the HCR does not have the exception
8567 * In these two cases, the below table contain a target of EL1. This value is
8568 * returned as it is expected that the consumer of the table data will check
8569 * for "target EL >= current EL" to ensure the exception is not taken.
8573 * BIT IRQ IMO Non-secure Secure
8574 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
8576 static const int8_t target_el_table
[2][2][2][2][2][4] = {
8577 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8578 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
8579 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8580 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
8581 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8582 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
8583 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8584 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
8585 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
8586 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
8587 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
8588 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
8589 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8590 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
8591 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8592 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
8596 * Determine the target EL for physical exceptions
8598 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8599 uint32_t cur_el
, bool secure
)
8601 CPUARMState
*env
= cs
->env_ptr
;
8606 /* Is the highest EL AArch64? */
8607 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
8610 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8611 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
8613 /* Either EL2 is the highest EL (and so the EL2 register width
8614 * is given by is64); or there is no EL2 or EL3, in which case
8615 * the value of 'rw' does not affect the table lookup anyway.
8620 hcr_el2
= arm_hcr_el2_eff(env
);
8623 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
8624 hcr
= hcr_el2
& HCR_IMO
;
8627 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
8628 hcr
= hcr_el2
& HCR_FMO
;
8631 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
8632 hcr
= hcr_el2
& HCR_AMO
;
8637 * For these purposes, TGE and AMO/IMO/FMO both force the
8638 * interrupt to EL2. Fold TGE into the bit extracted above.
8640 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
8642 /* Perform a table-lookup for the target EL given the current state */
8643 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
8645 assert(target_el
> 0);
8650 void arm_log_exception(int idx
)
8652 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
8653 const char *exc
= NULL
;
8654 static const char * const excnames
[] = {
8655 [EXCP_UDEF
] = "Undefined Instruction",
8657 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
8658 [EXCP_DATA_ABORT
] = "Data Abort",
8661 [EXCP_BKPT
] = "Breakpoint",
8662 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
8663 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
8664 [EXCP_HVC
] = "Hypervisor Call",
8665 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
8666 [EXCP_SMC
] = "Secure Monitor Call",
8667 [EXCP_VIRQ
] = "Virtual IRQ",
8668 [EXCP_VFIQ
] = "Virtual FIQ",
8669 [EXCP_SEMIHOST
] = "Semihosting call",
8670 [EXCP_NOCP
] = "v7M NOCP UsageFault",
8671 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
8672 [EXCP_STKOF
] = "v8M STKOF UsageFault",
8673 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
8674 [EXCP_LSERR
] = "v8M LSERR UsageFault",
8675 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
8678 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
8679 exc
= excnames
[idx
];
8684 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
8689 * Function used to synchronize QEMU's AArch64 register set with AArch32
8690 * register set. This is necessary when switching between AArch32 and AArch64
8693 void aarch64_sync_32_to_64(CPUARMState
*env
)
8696 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8698 /* We can blanket copy R[0:7] to X[0:7] */
8699 for (i
= 0; i
< 8; i
++) {
8700 env
->xregs
[i
] = env
->regs
[i
];
8704 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
8705 * Otherwise, they come from the banked user regs.
8707 if (mode
== ARM_CPU_MODE_FIQ
) {
8708 for (i
= 8; i
< 13; i
++) {
8709 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
8712 for (i
= 8; i
< 13; i
++) {
8713 env
->xregs
[i
] = env
->regs
[i
];
8718 * Registers x13-x23 are the various mode SP and FP registers. Registers
8719 * r13 and r14 are only copied if we are in that mode, otherwise we copy
8720 * from the mode banked register.
8722 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8723 env
->xregs
[13] = env
->regs
[13];
8724 env
->xregs
[14] = env
->regs
[14];
8726 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
8727 /* HYP is an exception in that it is copied from r14 */
8728 if (mode
== ARM_CPU_MODE_HYP
) {
8729 env
->xregs
[14] = env
->regs
[14];
8731 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
8735 if (mode
== ARM_CPU_MODE_HYP
) {
8736 env
->xregs
[15] = env
->regs
[13];
8738 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
8741 if (mode
== ARM_CPU_MODE_IRQ
) {
8742 env
->xregs
[16] = env
->regs
[14];
8743 env
->xregs
[17] = env
->regs
[13];
8745 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
8746 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
8749 if (mode
== ARM_CPU_MODE_SVC
) {
8750 env
->xregs
[18] = env
->regs
[14];
8751 env
->xregs
[19] = env
->regs
[13];
8753 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
8754 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
8757 if (mode
== ARM_CPU_MODE_ABT
) {
8758 env
->xregs
[20] = env
->regs
[14];
8759 env
->xregs
[21] = env
->regs
[13];
8761 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
8762 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
8765 if (mode
== ARM_CPU_MODE_UND
) {
8766 env
->xregs
[22] = env
->regs
[14];
8767 env
->xregs
[23] = env
->regs
[13];
8769 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
8770 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
8774 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8775 * mode, then we can copy from r8-r14. Otherwise, we copy from the
8776 * FIQ bank for r8-r14.
8778 if (mode
== ARM_CPU_MODE_FIQ
) {
8779 for (i
= 24; i
< 31; i
++) {
8780 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
8783 for (i
= 24; i
< 29; i
++) {
8784 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
8786 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
8787 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
8790 env
->pc
= env
->regs
[15];
8794 * Function used to synchronize QEMU's AArch32 register set with AArch64
8795 * register set. This is necessary when switching between AArch32 and AArch64
8798 void aarch64_sync_64_to_32(CPUARMState
*env
)
8801 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8803 /* We can blanket copy X[0:7] to R[0:7] */
8804 for (i
= 0; i
< 8; i
++) {
8805 env
->regs
[i
] = env
->xregs
[i
];
8809 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
8810 * Otherwise, we copy x8-x12 into the banked user regs.
8812 if (mode
== ARM_CPU_MODE_FIQ
) {
8813 for (i
= 8; i
< 13; i
++) {
8814 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
8817 for (i
= 8; i
< 13; i
++) {
8818 env
->regs
[i
] = env
->xregs
[i
];
8823 * Registers r13 & r14 depend on the current mode.
8824 * If we are in a given mode, we copy the corresponding x registers to r13
8825 * and r14. Otherwise, we copy the x register to the banked r13 and r14
8828 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8829 env
->regs
[13] = env
->xregs
[13];
8830 env
->regs
[14] = env
->xregs
[14];
8832 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
8835 * HYP is an exception in that it does not have its own banked r14 but
8836 * shares the USR r14
8838 if (mode
== ARM_CPU_MODE_HYP
) {
8839 env
->regs
[14] = env
->xregs
[14];
8841 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
8845 if (mode
== ARM_CPU_MODE_HYP
) {
8846 env
->regs
[13] = env
->xregs
[15];
8848 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
8851 if (mode
== ARM_CPU_MODE_IRQ
) {
8852 env
->regs
[14] = env
->xregs
[16];
8853 env
->regs
[13] = env
->xregs
[17];
8855 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
8856 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
8859 if (mode
== ARM_CPU_MODE_SVC
) {
8860 env
->regs
[14] = env
->xregs
[18];
8861 env
->regs
[13] = env
->xregs
[19];
8863 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
8864 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
8867 if (mode
== ARM_CPU_MODE_ABT
) {
8868 env
->regs
[14] = env
->xregs
[20];
8869 env
->regs
[13] = env
->xregs
[21];
8871 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
8872 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
8875 if (mode
== ARM_CPU_MODE_UND
) {
8876 env
->regs
[14] = env
->xregs
[22];
8877 env
->regs
[13] = env
->xregs
[23];
8879 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
8880 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
8883 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8884 * mode, then we can copy to r8-r14. Otherwise, we copy to the
8885 * FIQ bank for r8-r14.
8887 if (mode
== ARM_CPU_MODE_FIQ
) {
8888 for (i
= 24; i
< 31; i
++) {
8889 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
8892 for (i
= 24; i
< 29; i
++) {
8893 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
8895 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
8896 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
8899 env
->regs
[15] = env
->pc
;
8902 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
8903 uint32_t mask
, uint32_t offset
,
8908 /* Change the CPU state so as to actually take the exception. */
8909 switch_mode(env
, new_mode
);
8910 new_el
= arm_current_el(env
);
8913 * For exceptions taken to AArch32 we must clear the SS bit in both
8914 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8916 env
->uncached_cpsr
&= ~PSTATE_SS
;
8917 env
->spsr
= cpsr_read(env
);
8918 /* Clear IT bits. */
8919 env
->condexec_bits
= 0;
8920 /* Switch to the new mode, and to the correct instruction set. */
8921 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8922 /* Set new mode endianness */
8923 env
->uncached_cpsr
&= ~CPSR_E
;
8924 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
8925 env
->uncached_cpsr
|= CPSR_E
;
8927 /* J and IL must always be cleared for exception entry */
8928 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
8931 if (new_mode
== ARM_CPU_MODE_HYP
) {
8932 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
8933 env
->elr_el
[2] = env
->regs
[15];
8935 /* CPSR.PAN is normally preserved preserved unless... */
8936 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
8939 if (!arm_is_secure_below_el3(env
)) {
8940 /* ... the target is EL3, from non-secure state. */
8941 env
->uncached_cpsr
&= ~CPSR_PAN
;
8944 /* ... the target is EL3, from secure state ... */
8947 /* ... the target is EL1 and SCTLR.SPAN is 0. */
8948 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
8949 env
->uncached_cpsr
|= CPSR_PAN
;
8955 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8956 * and we should just guard the thumb mode on V4
8958 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8960 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8962 env
->regs
[14] = env
->regs
[15] + offset
;
8964 env
->regs
[15] = newpc
;
8965 arm_rebuild_hflags(env
);
8968 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
8971 * Handle exception entry to Hyp mode; this is sufficiently
8972 * different to entry to other AArch32 modes that we handle it
8975 * The vector table entry used is always the 0x14 Hyp mode entry point,
8976 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8977 * The offset applied to the preferred return address is always zero
8978 * (see DDI0487C.a section G1.12.3).
8979 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8981 uint32_t addr
, mask
;
8982 ARMCPU
*cpu
= ARM_CPU(cs
);
8983 CPUARMState
*env
= &cpu
->env
;
8985 switch (cs
->exception_index
) {
8993 /* Fall through to prefetch abort. */
8994 case EXCP_PREFETCH_ABORT
:
8995 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
8996 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
8997 (uint32_t)env
->exception
.vaddress
);
9000 case EXCP_DATA_ABORT
:
9001 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9002 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9003 (uint32_t)env
->exception
.vaddress
);
9019 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9022 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9023 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9025 * QEMU syndrome values are v8-style. v7 has the IL bit
9026 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9027 * If this is a v7 CPU, squash the IL bit in those cases.
9029 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9030 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9031 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9032 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9033 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9036 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9039 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9044 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9047 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9050 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9054 addr
+= env
->cp15
.hvbar
;
9056 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9059 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9061 ARMCPU
*cpu
= ARM_CPU(cs
);
9062 CPUARMState
*env
= &cpu
->env
;
9069 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9070 switch (syn_get_ec(env
->exception
.syndrome
)) {
9072 case EC_BREAKPOINT_SAME_EL
:
9076 case EC_WATCHPOINT_SAME_EL
:
9082 case EC_VECTORCATCH
:
9091 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9094 if (env
->exception
.target_el
== 2) {
9095 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9099 switch (cs
->exception_index
) {
9101 new_mode
= ARM_CPU_MODE_UND
;
9110 new_mode
= ARM_CPU_MODE_SVC
;
9113 /* The PC already points to the next instruction. */
9117 /* Fall through to prefetch abort. */
9118 case EXCP_PREFETCH_ABORT
:
9119 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9120 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9121 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9122 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9123 new_mode
= ARM_CPU_MODE_ABT
;
9125 mask
= CPSR_A
| CPSR_I
;
9128 case EXCP_DATA_ABORT
:
9129 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9130 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9131 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9133 (uint32_t)env
->exception
.vaddress
);
9134 new_mode
= ARM_CPU_MODE_ABT
;
9136 mask
= CPSR_A
| CPSR_I
;
9140 new_mode
= ARM_CPU_MODE_IRQ
;
9142 /* Disable IRQ and imprecise data aborts. */
9143 mask
= CPSR_A
| CPSR_I
;
9145 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9146 /* IRQ routed to monitor mode */
9147 new_mode
= ARM_CPU_MODE_MON
;
9152 new_mode
= ARM_CPU_MODE_FIQ
;
9154 /* Disable FIQ, IRQ and imprecise data aborts. */
9155 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9156 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9157 /* FIQ routed to monitor mode */
9158 new_mode
= ARM_CPU_MODE_MON
;
9163 new_mode
= ARM_CPU_MODE_IRQ
;
9165 /* Disable IRQ and imprecise data aborts. */
9166 mask
= CPSR_A
| CPSR_I
;
9170 new_mode
= ARM_CPU_MODE_FIQ
;
9172 /* Disable FIQ, IRQ and imprecise data aborts. */
9173 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9177 new_mode
= ARM_CPU_MODE_MON
;
9179 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9183 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9184 return; /* Never happens. Keep compiler happy. */
9187 if (new_mode
== ARM_CPU_MODE_MON
) {
9188 addr
+= env
->cp15
.mvbar
;
9189 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9190 /* High vectors. When enabled, base address cannot be remapped. */
9193 /* ARM v7 architectures provide a vector base address register to remap
9194 * the interrupt vector table.
9195 * This register is only followed in non-monitor mode, and is banked.
9196 * Note: only bits 31:5 are valid.
9198 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9201 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9202 env
->cp15
.scr_el3
&= ~SCR_NS
;
9205 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9208 /* Handle exception entry to a target EL which is using AArch64 */
9209 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9211 ARMCPU
*cpu
= ARM_CPU(cs
);
9212 CPUARMState
*env
= &cpu
->env
;
9213 unsigned int new_el
= env
->exception
.target_el
;
9214 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9215 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9216 unsigned int old_mode
;
9217 unsigned int cur_el
= arm_current_el(env
);
9220 * Note that new_el can never be 0. If cur_el is 0, then
9221 * el0_a64 is is_a64(), else el0_a64 is ignored.
9223 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9225 if (cur_el
< new_el
) {
9226 /* Entry vector offset depends on whether the implemented EL
9227 * immediately lower than the target level is using AArch32 or AArch64
9234 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9237 hcr
= arm_hcr_el2_eff(env
);
9238 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
9239 is_aa64
= (hcr
& HCR_RW
) != 0;
9244 is_aa64
= is_a64(env
);
9247 g_assert_not_reached();
9255 } else if (pstate_read(env
) & PSTATE_SP
) {
9259 switch (cs
->exception_index
) {
9260 case EXCP_PREFETCH_ABORT
:
9261 case EXCP_DATA_ABORT
:
9262 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
9263 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
9264 env
->cp15
.far_el
[new_el
]);
9272 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
9274 * QEMU internal FP/SIMD syndromes from AArch32 include the
9275 * TA and coproc fields which are only exposed if the exception
9276 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9277 * AArch64 format syndrome.
9279 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
9281 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9292 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9296 old_mode
= pstate_read(env
);
9297 aarch64_save_sp(env
, arm_current_el(env
));
9298 env
->elr_el
[new_el
] = env
->pc
;
9300 old_mode
= cpsr_read(env
);
9301 env
->elr_el
[new_el
] = env
->regs
[15];
9303 aarch64_sync_32_to_64(env
);
9305 env
->condexec_bits
= 0;
9307 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
9309 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
9310 env
->elr_el
[new_el
]);
9312 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9313 /* The value of PSTATE.PAN is normally preserved, except when ... */
9314 new_mode
|= old_mode
& PSTATE_PAN
;
9317 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9318 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
9319 != (HCR_E2H
| HCR_TGE
)) {
9324 /* ... the target is EL1 ... */
9325 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9326 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
9327 new_mode
|= PSTATE_PAN
;
9333 pstate_write(env
, PSTATE_DAIF
| new_mode
);
9335 aarch64_restore_sp(env
, new_el
);
9336 helper_rebuild_hflags_a64(env
, new_el
);
9340 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
9341 new_el
, env
->pc
, pstate_read(env
));
9345 * Do semihosting call and set the appropriate return value. All the
9346 * permission and validity checks have been done at translate time.
9348 * We only see semihosting exceptions in TCG only as they are not
9349 * trapped to the hypervisor in KVM.
9352 static void handle_semihosting(CPUState
*cs
)
9354 ARMCPU
*cpu
= ARM_CPU(cs
);
9355 CPUARMState
*env
= &cpu
->env
;
9358 qemu_log_mask(CPU_LOG_INT
,
9359 "...handling as semihosting call 0x%" PRIx64
"\n",
9361 env
->xregs
[0] = do_arm_semihosting(env
);
9364 qemu_log_mask(CPU_LOG_INT
,
9365 "...handling as semihosting call 0x%x\n",
9367 env
->regs
[0] = do_arm_semihosting(env
);
9368 env
->regs
[15] += env
->thumb
? 2 : 4;
9373 /* Handle a CPU exception for A and R profile CPUs.
9374 * Do any appropriate logging, handle PSCI calls, and then hand off
9375 * to the AArch64-entry or AArch32-entry function depending on the
9376 * target exception level's register width.
9378 void arm_cpu_do_interrupt(CPUState
*cs
)
9380 ARMCPU
*cpu
= ARM_CPU(cs
);
9381 CPUARMState
*env
= &cpu
->env
;
9382 unsigned int new_el
= env
->exception
.target_el
;
9384 assert(!arm_feature(env
, ARM_FEATURE_M
));
9386 arm_log_exception(cs
->exception_index
);
9387 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
9389 if (qemu_loglevel_mask(CPU_LOG_INT
)
9390 && !excp_is_internal(cs
->exception_index
)) {
9391 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
9392 syn_get_ec(env
->exception
.syndrome
),
9393 env
->exception
.syndrome
);
9396 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
9397 arm_handle_psci_call(cpu
);
9398 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
9403 * Semihosting semantics depend on the register width of the code
9404 * that caused the exception, not the target exception level, so
9405 * must be handled here.
9408 if (cs
->exception_index
== EXCP_SEMIHOST
) {
9409 handle_semihosting(cs
);
9414 /* Hooks may change global state so BQL should be held, also the
9415 * BQL needs to be held for any modification of
9416 * cs->interrupt_request.
9418 g_assert(qemu_mutex_iothread_locked());
9420 arm_call_pre_el_change_hook(cpu
);
9422 assert(!excp_is_internal(cs
->exception_index
));
9423 if (arm_el_is_aa64(env
, new_el
)) {
9424 arm_cpu_do_interrupt_aarch64(cs
);
9426 arm_cpu_do_interrupt_aarch32(cs
);
9429 arm_call_el_change_hook(cpu
);
9431 if (!kvm_enabled()) {
9432 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
9435 #endif /* !CONFIG_USER_ONLY */
9437 /* Return the exception level which controls this address translation regime */
9438 static uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9441 case ARMMMUIdx_E20_0
:
9442 case ARMMMUIdx_E20_2
:
9443 case ARMMMUIdx_E20_2_PAN
:
9444 case ARMMMUIdx_Stage2
:
9449 case ARMMMUIdx_SE10_0
:
9450 return arm_el_is_aa64(env
, 3) ? 1 : 3;
9451 case ARMMMUIdx_SE10_1
:
9452 case ARMMMUIdx_SE10_1_PAN
:
9453 case ARMMMUIdx_Stage1_E0
:
9454 case ARMMMUIdx_Stage1_E1
:
9455 case ARMMMUIdx_Stage1_E1_PAN
:
9456 case ARMMMUIdx_E10_0
:
9457 case ARMMMUIdx_E10_1
:
9458 case ARMMMUIdx_E10_1_PAN
:
9459 case ARMMMUIdx_MPrivNegPri
:
9460 case ARMMMUIdx_MUserNegPri
:
9461 case ARMMMUIdx_MPriv
:
9462 case ARMMMUIdx_MUser
:
9463 case ARMMMUIdx_MSPrivNegPri
:
9464 case ARMMMUIdx_MSUserNegPri
:
9465 case ARMMMUIdx_MSPriv
:
9466 case ARMMMUIdx_MSUser
:
9469 g_assert_not_reached();
9473 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
9475 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
9477 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
9478 el
= (mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1);
9480 return env
->cp15
.sctlr_el
[el
];
9483 /* Return the SCTLR value which controls this address translation regime */
9484 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9486 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
9489 #ifndef CONFIG_USER_ONLY
9491 /* Return true if the specified stage of address translation is disabled */
9492 static inline bool regime_translation_disabled(CPUARMState
*env
,
9495 if (arm_feature(env
, ARM_FEATURE_M
)) {
9496 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
9497 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
9498 case R_V7M_MPU_CTRL_ENABLE_MASK
:
9499 /* Enabled, but not for HardFault and NMI */
9500 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
9501 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
9502 /* Enabled for all cases */
9506 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9507 * we warned about that in armv7m_nvic.c when the guest set it.
9513 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9514 /* HCR.DC means HCR.VM behaves as 1 */
9515 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
9518 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
9519 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
9520 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
9525 if ((env
->cp15
.hcr_el2
& HCR_DC
) && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
9526 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
9530 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
9533 static inline bool regime_translation_big_endian(CPUARMState
*env
,
9536 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
9539 /* Return the TTBR associated with this translation regime */
9540 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9543 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9544 return env
->cp15
.vttbr_el2
;
9547 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
9549 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
9553 #endif /* !CONFIG_USER_ONLY */
9555 /* Return the TCR controlling this translation regime */
9556 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9558 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9559 return &env
->cp15
.vtcr_el2
;
9561 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
9564 /* Convert a possible stage1+2 MMU index into the appropriate
9567 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
9570 case ARMMMUIdx_E10_0
:
9571 return ARMMMUIdx_Stage1_E0
;
9572 case ARMMMUIdx_E10_1
:
9573 return ARMMMUIdx_Stage1_E1
;
9574 case ARMMMUIdx_E10_1_PAN
:
9575 return ARMMMUIdx_Stage1_E1_PAN
;
9581 /* Return true if the translation regime is using LPAE format page tables */
9582 static inline bool regime_using_lpae_format(CPUARMState
*env
,
9585 int el
= regime_el(env
, mmu_idx
);
9586 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
9589 if (arm_feature(env
, ARM_FEATURE_LPAE
)
9590 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
9596 /* Returns true if the stage 1 translation regime is using LPAE format page
9597 * tables. Used when raising alignment exceptions, whose FSR changes depending
9598 * on whether the long or short descriptor format is in use. */
9599 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9601 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
9603 return regime_using_lpae_format(env
, mmu_idx
);
9606 #ifndef CONFIG_USER_ONLY
9607 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9610 case ARMMMUIdx_SE10_0
:
9611 case ARMMMUIdx_E20_0
:
9612 case ARMMMUIdx_Stage1_E0
:
9613 case ARMMMUIdx_MUser
:
9614 case ARMMMUIdx_MSUser
:
9615 case ARMMMUIdx_MUserNegPri
:
9616 case ARMMMUIdx_MSUserNegPri
:
9620 case ARMMMUIdx_E10_0
:
9621 case ARMMMUIdx_E10_1
:
9622 case ARMMMUIdx_E10_1_PAN
:
9623 g_assert_not_reached();
9627 /* Translate section/page access permissions to page
9628 * R/W protection flags
9631 * @mmu_idx: MMU index indicating required translation regime
9632 * @ap: The 3-bit access permissions (AP[2:0])
9633 * @domain_prot: The 2-bit domain access permissions
9635 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9636 int ap
, int domain_prot
)
9638 bool is_user
= regime_is_user(env
, mmu_idx
);
9640 if (domain_prot
== 3) {
9641 return PAGE_READ
| PAGE_WRITE
;
9646 if (arm_feature(env
, ARM_FEATURE_V7
)) {
9649 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
9651 return is_user
? 0 : PAGE_READ
;
9658 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9663 return PAGE_READ
| PAGE_WRITE
;
9666 return PAGE_READ
| PAGE_WRITE
;
9667 case 4: /* Reserved. */
9670 return is_user
? 0 : PAGE_READ
;
9674 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
9679 g_assert_not_reached();
9683 /* Translate section/page access permissions to page
9684 * R/W protection flags.
9686 * @ap: The 2-bit simple AP (AP[2:1])
9687 * @is_user: TRUE if accessing from PL0
9689 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
9693 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9695 return PAGE_READ
| PAGE_WRITE
;
9697 return is_user
? 0 : PAGE_READ
;
9701 g_assert_not_reached();
9706 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
9708 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
9711 /* Translate S2 section/page access permissions to protection flags
9714 * @s2ap: The 2-bit stage2 access permissions (S2AP)
9715 * @xn: XN (execute-never) bit
9717 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
9728 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
9735 /* Translate section/page access permissions to protection flags
9738 * @mmu_idx: MMU index indicating required translation regime
9739 * @is_aa64: TRUE if AArch64
9740 * @ap: The 2-bit simple AP (AP[2:1])
9741 * @ns: NS (non-secure) bit
9742 * @xn: XN (execute-never) bit
9743 * @pxn: PXN (privileged execute-never) bit
9745 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
9746 int ap
, int ns
, int xn
, int pxn
)
9748 bool is_user
= regime_is_user(env
, mmu_idx
);
9749 int prot_rw
, user_rw
;
9753 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
9755 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
9759 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
9762 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
9765 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
9769 /* TODO have_wxn should be replaced with
9770 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
9771 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
9772 * compatible processors have EL2, which is required for [U]WXN.
9774 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
9777 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
9781 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
9782 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
9784 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9785 switch (regime_el(env
, mmu_idx
)) {
9789 xn
= xn
|| !(user_rw
& PAGE_READ
);
9793 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
9795 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
9796 (uwxn
&& (user_rw
& PAGE_WRITE
));
9806 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
9809 return prot_rw
| PAGE_EXEC
;
9812 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9813 uint32_t *table
, uint32_t address
)
9815 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
9816 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9818 if (address
& tcr
->mask
) {
9819 if (tcr
->raw_tcr
& TTBCR_PD1
) {
9820 /* Translation table walk disabled for TTBR1 */
9823 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
9825 if (tcr
->raw_tcr
& TTBCR_PD0
) {
9826 /* Translation table walk disabled for TTBR0 */
9829 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
9831 *table
|= (address
>> 18) & 0x3ffc;
9835 /* Translate a S1 pagetable walk through S2 if needed. */
9836 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9837 hwaddr addr
, MemTxAttrs txattrs
,
9838 ARMMMUFaultInfo
*fi
)
9840 if (arm_mmu_idx_is_stage1_of_2(mmu_idx
) &&
9841 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
9842 target_ulong s2size
;
9846 ARMCacheAttrs cacheattrs
= {};
9847 ARMCacheAttrs
*pcacheattrs
= NULL
;
9849 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
9851 * PTW means we must fault if this S1 walk touches S2 Device
9852 * memory; otherwise we don't care about the attributes and can
9853 * save the S2 translation the effort of computing them.
9855 pcacheattrs
= &cacheattrs
;
9858 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_Stage2
, &s2pa
,
9859 &txattrs
, &s2prot
, &s2size
, fi
, pcacheattrs
);
9861 assert(fi
->type
!= ARMFault_None
);
9867 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
9868 /* Access was to Device memory: generate Permission fault */
9869 fi
->type
= ARMFault_Permission
;
9880 /* All loads done in the course of a page table walk go through here. */
9881 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9882 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9884 ARMCPU
*cpu
= ARM_CPU(cs
);
9885 CPUARMState
*env
= &cpu
->env
;
9886 MemTxAttrs attrs
= {};
9887 MemTxResult result
= MEMTX_OK
;
9891 attrs
.secure
= is_secure
;
9892 as
= arm_addressspace(cs
, attrs
);
9893 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9897 if (regime_translation_big_endian(env
, mmu_idx
)) {
9898 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
9900 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
9902 if (result
== MEMTX_OK
) {
9905 fi
->type
= ARMFault_SyncExternalOnWalk
;
9906 fi
->ea
= arm_extabort_type(result
);
9910 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9911 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9913 ARMCPU
*cpu
= ARM_CPU(cs
);
9914 CPUARMState
*env
= &cpu
->env
;
9915 MemTxAttrs attrs
= {};
9916 MemTxResult result
= MEMTX_OK
;
9920 attrs
.secure
= is_secure
;
9921 as
= arm_addressspace(cs
, attrs
);
9922 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9926 if (regime_translation_big_endian(env
, mmu_idx
)) {
9927 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
9929 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
9931 if (result
== MEMTX_OK
) {
9934 fi
->type
= ARMFault_SyncExternalOnWalk
;
9935 fi
->ea
= arm_extabort_type(result
);
9939 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
9940 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9941 hwaddr
*phys_ptr
, int *prot
,
9942 target_ulong
*page_size
,
9943 ARMMMUFaultInfo
*fi
)
9945 CPUState
*cs
= env_cpu(env
);
9956 /* Pagetable walk. */
9957 /* Lookup l1 descriptor. */
9958 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9959 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9960 fi
->type
= ARMFault_Translation
;
9963 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9965 if (fi
->type
!= ARMFault_None
) {
9969 domain
= (desc
>> 5) & 0x0f;
9970 if (regime_el(env
, mmu_idx
) == 1) {
9971 dacr
= env
->cp15
.dacr_ns
;
9973 dacr
= env
->cp15
.dacr_s
;
9975 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9977 /* Section translation fault. */
9978 fi
->type
= ARMFault_Translation
;
9984 if (domain_prot
== 0 || domain_prot
== 2) {
9985 fi
->type
= ARMFault_Domain
;
9990 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9991 ap
= (desc
>> 10) & 3;
9992 *page_size
= 1024 * 1024;
9994 /* Lookup l2 entry. */
9996 /* Coarse pagetable. */
9997 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9999 /* Fine pagetable. */
10000 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
10002 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10004 if (fi
->type
!= ARMFault_None
) {
10007 switch (desc
& 3) {
10008 case 0: /* Page translation fault. */
10009 fi
->type
= ARMFault_Translation
;
10011 case 1: /* 64k page. */
10012 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10013 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
10014 *page_size
= 0x10000;
10016 case 2: /* 4k page. */
10017 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10018 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
10019 *page_size
= 0x1000;
10021 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10023 /* ARMv6/XScale extended small page format */
10024 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
10025 || arm_feature(env
, ARM_FEATURE_V6
)) {
10026 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10027 *page_size
= 0x1000;
10029 /* UNPREDICTABLE in ARMv5; we choose to take a
10030 * page translation fault.
10032 fi
->type
= ARMFault_Translation
;
10036 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
10037 *page_size
= 0x400;
10039 ap
= (desc
>> 4) & 3;
10042 /* Never happens, but compiler isn't smart enough to tell. */
10046 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10047 *prot
|= *prot
? PAGE_EXEC
: 0;
10048 if (!(*prot
& (1 << access_type
))) {
10049 /* Access permission fault. */
10050 fi
->type
= ARMFault_Permission
;
10053 *phys_ptr
= phys_addr
;
10056 fi
->domain
= domain
;
10061 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
10062 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10063 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10064 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
10066 CPUState
*cs
= env_cpu(env
);
10080 /* Pagetable walk. */
10081 /* Lookup l1 descriptor. */
10082 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10083 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10084 fi
->type
= ARMFault_Translation
;
10087 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10089 if (fi
->type
!= ARMFault_None
) {
10093 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
10094 /* Section translation fault, or attempt to use the encoding
10095 * which is Reserved on implementations without PXN.
10097 fi
->type
= ARMFault_Translation
;
10100 if ((type
== 1) || !(desc
& (1 << 18))) {
10101 /* Page or Section. */
10102 domain
= (desc
>> 5) & 0x0f;
10104 if (regime_el(env
, mmu_idx
) == 1) {
10105 dacr
= env
->cp15
.dacr_ns
;
10107 dacr
= env
->cp15
.dacr_s
;
10112 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10113 if (domain_prot
== 0 || domain_prot
== 2) {
10114 /* Section or Page domain fault */
10115 fi
->type
= ARMFault_Domain
;
10119 if (desc
& (1 << 18)) {
10120 /* Supersection. */
10121 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
10122 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
10123 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
10124 *page_size
= 0x1000000;
10127 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10128 *page_size
= 0x100000;
10130 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
10131 xn
= desc
& (1 << 4);
10133 ns
= extract32(desc
, 19, 1);
10135 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
10136 pxn
= (desc
>> 2) & 1;
10138 ns
= extract32(desc
, 3, 1);
10139 /* Lookup l2 entry. */
10140 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10141 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10143 if (fi
->type
!= ARMFault_None
) {
10146 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
10147 switch (desc
& 3) {
10148 case 0: /* Page translation fault. */
10149 fi
->type
= ARMFault_Translation
;
10151 case 1: /* 64k page. */
10152 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10153 xn
= desc
& (1 << 15);
10154 *page_size
= 0x10000;
10156 case 2: case 3: /* 4k page. */
10157 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10159 *page_size
= 0x1000;
10162 /* Never happens, but compiler isn't smart enough to tell. */
10166 if (domain_prot
== 3) {
10167 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10169 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
10172 if (xn
&& access_type
== MMU_INST_FETCH
) {
10173 fi
->type
= ARMFault_Permission
;
10177 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
10178 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
10179 /* The simplified model uses AP[0] as an access control bit. */
10180 if ((ap
& 1) == 0) {
10181 /* Access flag fault. */
10182 fi
->type
= ARMFault_AccessFlag
;
10185 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
10187 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10189 if (*prot
&& !xn
) {
10190 *prot
|= PAGE_EXEC
;
10192 if (!(*prot
& (1 << access_type
))) {
10193 /* Access permission fault. */
10194 fi
->type
= ARMFault_Permission
;
10199 /* The NS bit will (as required by the architecture) have no effect if
10200 * the CPU doesn't support TZ or this is a non-secure translation
10201 * regime, because the attribute will already be non-secure.
10203 attrs
->secure
= false;
10205 *phys_ptr
= phys_addr
;
10208 fi
->domain
= domain
;
10214 * check_s2_mmu_setup
10216 * @is_aa64: True if the translation regime is in AArch64 state
10217 * @startlevel: Suggested starting level
10218 * @inputsize: Bitsize of IPAs
10219 * @stride: Page-table stride (See the ARM ARM)
10221 * Returns true if the suggested S2 translation parameters are OK and
10224 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
10225 int inputsize
, int stride
)
10227 const int grainsize
= stride
+ 3;
10228 int startsizecheck
;
10230 /* Negative levels are never allowed. */
10235 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
10236 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
10241 CPUARMState
*env
= &cpu
->env
;
10242 unsigned int pamax
= arm_pamax(cpu
);
10245 case 13: /* 64KB Pages. */
10246 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
10250 case 11: /* 16KB Pages. */
10251 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
10255 case 9: /* 4KB Pages. */
10256 if (level
== 0 && pamax
<= 42) {
10261 g_assert_not_reached();
10264 /* Inputsize checks. */
10265 if (inputsize
> pamax
&&
10266 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
10267 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10271 /* AArch32 only supports 4KB pages. Assert on that. */
10272 assert(stride
== 9);
10281 /* Translate from the 4-bit stage 2 representation of
10282 * memory attributes (without cache-allocation hints) to
10283 * the 8-bit representation of the stage 1 MAIR registers
10284 * (which includes allocation hints).
10286 * ref: shared/translation/attrs/S2AttrDecode()
10287 * .../S2ConvertAttrsHints()
10289 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
10291 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
10292 uint8_t loattr
= extract32(s2attrs
, 0, 2);
10293 uint8_t hihint
= 0, lohint
= 0;
10295 if (hiattr
!= 0) { /* normal memory */
10296 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
10297 hiattr
= loattr
= 1; /* non-cacheable */
10299 if (hiattr
!= 1) { /* Write-through or write-back */
10300 hihint
= 3; /* RW allocate */
10302 if (loattr
!= 1) { /* Write-through or write-back */
10303 lohint
= 3; /* RW allocate */
10308 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
10310 #endif /* !CONFIG_USER_ONLY */
10312 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10314 if (regime_has_2_ranges(mmu_idx
)) {
10315 return extract64(tcr
, 37, 2);
10316 } else if (mmu_idx
== ARMMMUIdx_Stage2
) {
10317 return 0; /* VTCR_EL2 */
10319 return extract32(tcr
, 20, 1);
10323 static int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10325 if (regime_has_2_ranges(mmu_idx
)) {
10326 return extract64(tcr
, 51, 2);
10327 } else if (mmu_idx
== ARMMMUIdx_Stage2
) {
10328 return 0; /* VTCR_EL2 */
10330 return extract32(tcr
, 29, 1);
10334 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10335 ARMMMUIdx mmu_idx
, bool data
)
10337 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10338 bool epd
, hpd
, using16k
, using64k
;
10339 int select
, tsz
, tbi
;
10341 if (!regime_has_2_ranges(mmu_idx
)) {
10343 tsz
= extract32(tcr
, 0, 6);
10344 using64k
= extract32(tcr
, 14, 1);
10345 using16k
= extract32(tcr
, 15, 1);
10346 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10350 hpd
= extract32(tcr
, 24, 1);
10355 * Bit 55 is always between the two regions, and is canonical for
10356 * determining if address tagging is enabled.
10358 select
= extract64(va
, 55, 1);
10360 tsz
= extract32(tcr
, 0, 6);
10361 epd
= extract32(tcr
, 7, 1);
10362 using64k
= extract32(tcr
, 14, 1);
10363 using16k
= extract32(tcr
, 15, 1);
10364 hpd
= extract64(tcr
, 41, 1);
10366 int tg
= extract32(tcr
, 30, 2);
10367 using16k
= tg
== 1;
10368 using64k
= tg
== 3;
10369 tsz
= extract32(tcr
, 16, 6);
10370 epd
= extract32(tcr
, 23, 1);
10371 hpd
= extract64(tcr
, 42, 1);
10374 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
10375 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
10377 /* Present TBI as a composite with TBID. */
10378 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10380 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10382 tbi
= (tbi
>> select
) & 1;
10384 return (ARMVAParameters
) {
10390 .using16k
= using16k
,
10391 .using64k
= using64k
,
10395 #ifndef CONFIG_USER_ONLY
10396 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
10399 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10400 uint32_t el
= regime_el(env
, mmu_idx
);
10404 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10406 bool sext
= extract32(tcr
, 4, 1);
10407 bool sign
= extract32(tcr
, 3, 1);
10410 * If the sign-extend bit is not the same as t0sz[3], the result
10411 * is unpredictable. Flag this as a guest error.
10413 if (sign
!= sext
) {
10414 qemu_log_mask(LOG_GUEST_ERROR
,
10415 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10417 tsz
= sextract32(tcr
, 0, 4) + 8;
10421 } else if (el
== 2) {
10423 tsz
= extract32(tcr
, 0, 3);
10425 hpd
= extract64(tcr
, 24, 1);
10428 int t0sz
= extract32(tcr
, 0, 3);
10429 int t1sz
= extract32(tcr
, 16, 3);
10432 select
= va
> (0xffffffffu
>> t0sz
);
10434 /* Note that we will detect errors later. */
10435 select
= va
>= ~(0xffffffffu
>> t1sz
);
10439 epd
= extract32(tcr
, 7, 1);
10440 hpd
= extract64(tcr
, 41, 1);
10443 epd
= extract32(tcr
, 23, 1);
10444 hpd
= extract64(tcr
, 42, 1);
10446 /* For aarch32, hpd0 is not enabled without t2e as well. */
10447 hpd
&= extract32(tcr
, 6, 1);
10450 return (ARMVAParameters
) {
10458 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
10459 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10460 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
10461 target_ulong
*page_size_ptr
,
10462 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10464 ARMCPU
*cpu
= env_archcpu(env
);
10465 CPUState
*cs
= CPU(cpu
);
10466 /* Read an LPAE long-descriptor translation table. */
10467 ARMFaultType fault_type
= ARMFault_Translation
;
10469 ARMVAParameters param
;
10471 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
10472 uint32_t tableattrs
;
10473 target_ulong page_size
;
10476 int addrsize
, inputsize
;
10477 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10478 int ap
, ns
, xn
, pxn
;
10479 uint32_t el
= regime_el(env
, mmu_idx
);
10480 uint64_t descaddrmask
;
10481 bool aarch64
= arm_el_is_aa64(env
, el
);
10482 bool guarded
= false;
10485 * This code does not handle the different format TCR for VTCR_EL2.
10486 * This code also does not support shareability levels.
10487 * Attribute and permission bit handling should also be checked when adding
10488 * support for those page table walks.
10491 param
= aa64_va_parameters(env
, address
, mmu_idx
,
10492 access_type
!= MMU_INST_FETCH
);
10494 addrsize
= 64 - 8 * param
.tbi
;
10495 inputsize
= 64 - param
.tsz
;
10497 param
= aa32_va_parameters(env
, address
, mmu_idx
);
10499 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
10500 inputsize
= addrsize
- param
.tsz
;
10504 * We determined the region when collecting the parameters, but we
10505 * have not yet validated that the address is valid for the region.
10506 * Extract the top bits and verify that they all match select.
10508 * For aa32, if inputsize == addrsize, then we have selected the
10509 * region by exclusion in aa32_va_parameters and there is no more
10510 * validation to do here.
10512 if (inputsize
< addrsize
) {
10513 target_ulong top_bits
= sextract64(address
, inputsize
,
10514 addrsize
- inputsize
);
10515 if (-top_bits
!= param
.select
) {
10516 /* The gap between the two regions is a Translation fault */
10517 fault_type
= ARMFault_Translation
;
10522 if (param
.using64k
) {
10524 } else if (param
.using16k
) {
10530 /* Note that QEMU ignores shareability and cacheability attributes,
10531 * so we don't need to do anything with the SH, ORGN, IRGN fields
10532 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
10533 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
10534 * implement any ASID-like capability so we can ignore it (instead
10535 * we will always flush the TLB any time the ASID is changed).
10537 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
10539 /* Here we should have set up all the parameters for the translation:
10540 * inputsize, ttbr, epd, stride, tbi
10544 /* Translation table walk disabled => Translation fault on TLB miss
10545 * Note: This is always 0 on 64-bit EL2 and EL3.
10550 if (mmu_idx
!= ARMMMUIdx_Stage2
) {
10551 /* The starting level depends on the virtual address size (which can
10552 * be up to 48 bits) and the translation granule size. It indicates
10553 * the number of strides (stride bits at a time) needed to
10554 * consume the bits of the input address. In the pseudocode this is:
10555 * level = 4 - RoundUp((inputsize - grainsize) / stride)
10556 * where their 'inputsize' is our 'inputsize', 'grainsize' is
10557 * our 'stride + 3' and 'stride' is our 'stride'.
10558 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
10559 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
10560 * = 4 - (inputsize - 4) / stride;
10562 level
= 4 - (inputsize
- 4) / stride
;
10564 /* For stage 2 translations the starting level is specified by the
10565 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
10567 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
10568 uint32_t startlevel
;
10571 if (!aarch64
|| stride
== 9) {
10572 /* AArch32 or 4KB pages */
10573 startlevel
= 2 - sl0
;
10575 /* 16KB or 64KB pages */
10576 startlevel
= 3 - sl0
;
10579 /* Check that the starting level is valid. */
10580 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
10581 inputsize
, stride
);
10583 fault_type
= ARMFault_Translation
;
10586 level
= startlevel
;
10589 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
10590 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
10592 /* Now we can extract the actual base address from the TTBR */
10593 descaddr
= extract64(ttbr
, 0, 48);
10594 descaddr
&= ~indexmask
;
10596 /* The address field in the descriptor goes up to bit 39 for ARMv7
10597 * but up to bit 47 for ARMv8, but we use the descaddrmask
10598 * up to bit 39 for AArch32, because we don't need other bits in that case
10599 * to construct next descriptor address (anyway they should be all zeroes).
10601 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
10602 ~indexmask_grainsize
;
10604 /* Secure accesses start with the page table in secure memory and
10605 * can be downgraded to non-secure at any step. Non-secure accesses
10606 * remain non-secure. We implement this by just ORing in the NSTable/NS
10607 * bits at each step.
10609 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
10611 uint64_t descriptor
;
10614 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
10616 nstable
= extract32(tableattrs
, 4, 1);
10617 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
10618 if (fi
->type
!= ARMFault_None
) {
10622 if (!(descriptor
& 1) ||
10623 (!(descriptor
& 2) && (level
== 3))) {
10624 /* Invalid, or the Reserved level 3 encoding */
10627 descaddr
= descriptor
& descaddrmask
;
10629 if ((descriptor
& 2) && (level
< 3)) {
10630 /* Table entry. The top five bits are attributes which may
10631 * propagate down through lower levels of the table (and
10632 * which are all arranged so that 0 means "no effect", so
10633 * we can gather them up by ORing in the bits at each level).
10635 tableattrs
|= extract64(descriptor
, 59, 5);
10637 indexmask
= indexmask_grainsize
;
10640 /* Block entry at level 1 or 2, or page entry at level 3.
10641 * These are basically the same thing, although the number
10642 * of bits we pull in from the vaddr varies.
10644 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
10645 descaddr
|= (address
& (page_size
- 1));
10646 /* Extract attributes from the descriptor */
10647 attrs
= extract64(descriptor
, 2, 10)
10648 | (extract64(descriptor
, 52, 12) << 10);
10650 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10651 /* Stage 2 table descriptors do not include any attribute fields */
10654 /* Merge in attributes from table descriptors */
10655 attrs
|= nstable
<< 3; /* NS */
10656 guarded
= extract64(descriptor
, 50, 1); /* GP */
10658 /* HPD disables all the table attributes except NSTable. */
10661 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
10662 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
10663 * means "force PL1 access only", which means forcing AP[1] to 0.
10665 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
10666 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
10669 /* Here descaddr is the final physical address, and attributes
10670 * are all in attrs.
10672 fault_type
= ARMFault_AccessFlag
;
10673 if ((attrs
& (1 << 8)) == 0) {
10678 ap
= extract32(attrs
, 4, 2);
10679 xn
= extract32(attrs
, 12, 1);
10681 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10683 *prot
= get_S2prot(env
, ap
, xn
);
10685 ns
= extract32(attrs
, 3, 1);
10686 pxn
= extract32(attrs
, 11, 1);
10687 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
10690 fault_type
= ARMFault_Permission
;
10691 if (!(*prot
& (1 << access_type
))) {
10696 /* The NS bit will (as required by the architecture) have no effect if
10697 * the CPU doesn't support TZ or this is a non-secure translation
10698 * regime, because the attribute will already be non-secure.
10700 txattrs
->secure
= false;
10702 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
10703 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
10704 txattrs
->target_tlb_bit0
= true;
10707 if (cacheattrs
!= NULL
) {
10708 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10709 cacheattrs
->attrs
= convert_stage2_attrs(env
,
10710 extract32(attrs
, 0, 4));
10712 /* Index into MAIR registers for cache attributes */
10713 uint8_t attrindx
= extract32(attrs
, 0, 3);
10714 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
10715 assert(attrindx
<= 7);
10716 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
10718 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
10721 *phys_ptr
= descaddr
;
10722 *page_size_ptr
= page_size
;
10726 fi
->type
= fault_type
;
10728 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
10729 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
);
10733 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
10735 int32_t address
, int *prot
)
10737 if (!arm_feature(env
, ARM_FEATURE_M
)) {
10738 *prot
= PAGE_READ
| PAGE_WRITE
;
10740 case 0xF0000000 ... 0xFFFFFFFF:
10741 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
10742 /* hivecs execing is ok */
10743 *prot
|= PAGE_EXEC
;
10746 case 0x00000000 ... 0x7FFFFFFF:
10747 *prot
|= PAGE_EXEC
;
10751 /* Default system address map for M profile cores.
10752 * The architecture specifies which regions are execute-never;
10753 * at the MPU level no other checks are defined.
10756 case 0x00000000 ... 0x1fffffff: /* ROM */
10757 case 0x20000000 ... 0x3fffffff: /* SRAM */
10758 case 0x60000000 ... 0x7fffffff: /* RAM */
10759 case 0x80000000 ... 0x9fffffff: /* RAM */
10760 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10762 case 0x40000000 ... 0x5fffffff: /* Peripheral */
10763 case 0xa0000000 ... 0xbfffffff: /* Device */
10764 case 0xc0000000 ... 0xdfffffff: /* Device */
10765 case 0xe0000000 ... 0xffffffff: /* System */
10766 *prot
= PAGE_READ
| PAGE_WRITE
;
10769 g_assert_not_reached();
10774 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
10775 ARMMMUIdx mmu_idx
, bool is_user
)
10777 /* Return true if we should use the default memory map as a
10778 * "background" region if there are no hits against any MPU regions.
10780 CPUARMState
*env
= &cpu
->env
;
10786 if (arm_feature(env
, ARM_FEATURE_M
)) {
10787 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
10788 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
10790 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
10794 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
10796 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
10797 return arm_feature(env
, ARM_FEATURE_M
) &&
10798 extract32(address
, 20, 12) == 0xe00;
10801 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
10803 /* True if address is in the M profile system region
10804 * 0xe0000000 - 0xffffffff
10806 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
10809 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
10810 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10811 hwaddr
*phys_ptr
, int *prot
,
10812 target_ulong
*page_size
,
10813 ARMMMUFaultInfo
*fi
)
10815 ARMCPU
*cpu
= env_archcpu(env
);
10817 bool is_user
= regime_is_user(env
, mmu_idx
);
10819 *phys_ptr
= address
;
10820 *page_size
= TARGET_PAGE_SIZE
;
10823 if (regime_translation_disabled(env
, mmu_idx
) ||
10824 m_is_ppb_region(env
, address
)) {
10825 /* MPU disabled or M profile PPB access: use default memory map.
10826 * The other case which uses the default memory map in the
10827 * v7M ARM ARM pseudocode is exception vector reads from the vector
10828 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
10829 * which always does a direct read using address_space_ldl(), rather
10830 * than going via this function, so we don't need to check that here.
10832 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10833 } else { /* MPU enabled */
10834 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10835 /* region search */
10836 uint32_t base
= env
->pmsav7
.drbar
[n
];
10837 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
10839 bool srdis
= false;
10841 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
10846 qemu_log_mask(LOG_GUEST_ERROR
,
10847 "DRSR[%d]: Rsize field cannot be 0\n", n
);
10851 rmask
= (1ull << rsize
) - 1;
10853 if (base
& rmask
) {
10854 qemu_log_mask(LOG_GUEST_ERROR
,
10855 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
10856 "to DRSR region size, mask = 0x%" PRIx32
"\n",
10861 if (address
< base
|| address
> base
+ rmask
) {
10863 * Address not in this region. We must check whether the
10864 * region covers addresses in the same page as our address.
10865 * In that case we must not report a size that covers the
10866 * whole page for a subsequent hit against a different MPU
10867 * region or the background region, because it would result in
10868 * incorrect TLB hits for subsequent accesses to addresses that
10869 * are in this MPU region.
10871 if (ranges_overlap(base
, rmask
,
10872 address
& TARGET_PAGE_MASK
,
10873 TARGET_PAGE_SIZE
)) {
10879 /* Region matched */
10881 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
10883 uint32_t srdis_mask
;
10885 rsize
-= 3; /* sub region size (power of 2) */
10886 snd
= ((address
- base
) >> rsize
) & 0x7;
10887 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
10889 srdis_mask
= srdis
? 0x3 : 0x0;
10890 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
10891 /* This will check in groups of 2, 4 and then 8, whether
10892 * the subregion bits are consistent. rsize is incremented
10893 * back up to give the region size, considering consistent
10894 * adjacent subregions as one region. Stop testing if rsize
10895 * is already big enough for an entire QEMU page.
10897 int snd_rounded
= snd
& ~(i
- 1);
10898 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
10899 snd_rounded
+ 8, i
);
10900 if (srdis_mask
^ srdis_multi
) {
10903 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
10910 if (rsize
< TARGET_PAGE_BITS
) {
10911 *page_size
= 1 << rsize
;
10916 if (n
== -1) { /* no hits */
10917 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10918 /* background fault */
10919 fi
->type
= ARMFault_Background
;
10922 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10923 } else { /* a MPU hit! */
10924 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
10925 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
10927 if (m_is_system_region(env
, address
)) {
10928 /* System space is always execute never */
10932 if (is_user
) { /* User mode AP bit decoding */
10937 break; /* no access */
10939 *prot
|= PAGE_WRITE
;
10943 *prot
|= PAGE_READ
| PAGE_EXEC
;
10946 /* for v7M, same as 6; for R profile a reserved value */
10947 if (arm_feature(env
, ARM_FEATURE_M
)) {
10948 *prot
|= PAGE_READ
| PAGE_EXEC
;
10953 qemu_log_mask(LOG_GUEST_ERROR
,
10954 "DRACR[%d]: Bad value for AP bits: 0x%"
10955 PRIx32
"\n", n
, ap
);
10957 } else { /* Priv. mode AP bits decoding */
10960 break; /* no access */
10964 *prot
|= PAGE_WRITE
;
10968 *prot
|= PAGE_READ
| PAGE_EXEC
;
10971 /* for v7M, same as 6; for R profile a reserved value */
10972 if (arm_feature(env
, ARM_FEATURE_M
)) {
10973 *prot
|= PAGE_READ
| PAGE_EXEC
;
10978 qemu_log_mask(LOG_GUEST_ERROR
,
10979 "DRACR[%d]: Bad value for AP bits: 0x%"
10980 PRIx32
"\n", n
, ap
);
10984 /* execute never */
10986 *prot
&= ~PAGE_EXEC
;
10991 fi
->type
= ARMFault_Permission
;
10993 return !(*prot
& (1 << access_type
));
10996 static bool v8m_is_sau_exempt(CPUARMState
*env
,
10997 uint32_t address
, MMUAccessType access_type
)
10999 /* The architecture specifies that certain address ranges are
11000 * exempt from v8M SAU/IDAU checks.
11003 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
11004 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
11005 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
11006 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
11007 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
11008 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
11011 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
11012 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11013 V8M_SAttributes
*sattrs
)
11015 /* Look up the security attributes for this address. Compare the
11016 * pseudocode SecurityCheck() function.
11017 * We assume the caller has zero-initialized *sattrs.
11019 ARMCPU
*cpu
= env_archcpu(env
);
11021 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
11022 int idau_region
= IREGION_NOTVALID
;
11023 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11024 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11027 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
11028 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
11030 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
11034 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
11035 /* 0xf0000000..0xffffffff is always S for insn fetches */
11039 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
11040 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
11044 if (idau_region
!= IREGION_NOTVALID
) {
11045 sattrs
->irvalid
= true;
11046 sattrs
->iregion
= idau_region
;
11049 switch (env
->sau
.ctrl
& 3) {
11050 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11052 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11055 default: /* SAU.ENABLE == 1 */
11056 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
11057 if (env
->sau
.rlar
[r
] & 1) {
11058 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
11059 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
11061 if (base
<= address
&& limit
>= address
) {
11062 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11063 sattrs
->subpage
= true;
11065 if (sattrs
->srvalid
) {
11066 /* If we hit in more than one region then we must report
11067 * as Secure, not NS-Callable, with no valid region
11070 sattrs
->ns
= false;
11071 sattrs
->nsc
= false;
11072 sattrs
->sregion
= 0;
11073 sattrs
->srvalid
= false;
11076 if (env
->sau
.rlar
[r
] & 2) {
11077 sattrs
->nsc
= true;
11081 sattrs
->srvalid
= true;
11082 sattrs
->sregion
= r
;
11086 * Address not in this region. We must check whether the
11087 * region covers addresses in the same page as our address.
11088 * In that case we must not report a size that covers the
11089 * whole page for a subsequent hit against a different MPU
11090 * region or the background region, because it would result
11091 * in incorrect TLB hits for subsequent accesses to
11092 * addresses that are in this MPU region.
11094 if (limit
>= base
&&
11095 ranges_overlap(base
, limit
- base
+ 1,
11097 TARGET_PAGE_SIZE
)) {
11098 sattrs
->subpage
= true;
11107 * The IDAU will override the SAU lookup results if it specifies
11108 * higher security than the SAU does.
11111 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
11112 sattrs
->ns
= false;
11113 sattrs
->nsc
= idau_nsc
;
11118 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
11119 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11120 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11121 int *prot
, bool *is_subpage
,
11122 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
11124 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11125 * that a full phys-to-virt translation does).
11126 * mregion is (if not NULL) set to the region number which matched,
11127 * or -1 if no region number is returned (MPU off, address did not
11128 * hit a region, address hit in multiple regions).
11129 * We set is_subpage to true if the region hit doesn't cover the
11130 * entire TARGET_PAGE the address is within.
11132 ARMCPU
*cpu
= env_archcpu(env
);
11133 bool is_user
= regime_is_user(env
, mmu_idx
);
11134 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11136 int matchregion
= -1;
11138 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11139 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11141 *is_subpage
= false;
11142 *phys_ptr
= address
;
11148 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11149 * was an exception vector read from the vector table (which is always
11150 * done using the default system address map), because those accesses
11151 * are done in arm_v7m_load_vector(), which always does a direct
11152 * read using address_space_ldl(), rather than going via this function.
11154 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
11156 } else if (m_is_ppb_region(env
, address
)) {
11159 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11163 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11164 /* region search */
11165 /* Note that the base address is bits [31:5] from the register
11166 * with bits [4:0] all zeroes, but the limit address is bits
11167 * [31:5] from the register with bits [4:0] all ones.
11169 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
11170 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
11172 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
11173 /* Region disabled */
11177 if (address
< base
|| address
> limit
) {
11179 * Address not in this region. We must check whether the
11180 * region covers addresses in the same page as our address.
11181 * In that case we must not report a size that covers the
11182 * whole page for a subsequent hit against a different MPU
11183 * region or the background region, because it would result in
11184 * incorrect TLB hits for subsequent accesses to addresses that
11185 * are in this MPU region.
11187 if (limit
>= base
&&
11188 ranges_overlap(base
, limit
- base
+ 1,
11190 TARGET_PAGE_SIZE
)) {
11191 *is_subpage
= true;
11196 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11197 *is_subpage
= true;
11200 if (matchregion
!= -1) {
11201 /* Multiple regions match -- always a failure (unlike
11202 * PMSAv7 where highest-numbered-region wins)
11204 fi
->type
= ARMFault_Permission
;
11215 /* background fault */
11216 fi
->type
= ARMFault_Background
;
11220 if (matchregion
== -1) {
11221 /* hit using the background region */
11222 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11224 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
11225 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
11227 if (m_is_system_region(env
, address
)) {
11228 /* System space is always execute never */
11232 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
11233 if (*prot
&& !xn
) {
11234 *prot
|= PAGE_EXEC
;
11236 /* We don't need to look the attribute up in the MAIR0/MAIR1
11237 * registers because that only tells us about cacheability.
11240 *mregion
= matchregion
;
11244 fi
->type
= ARMFault_Permission
;
11246 return !(*prot
& (1 << access_type
));
11250 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
11251 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11252 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11253 int *prot
, target_ulong
*page_size
,
11254 ARMMMUFaultInfo
*fi
)
11256 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11257 V8M_SAttributes sattrs
= {};
11259 bool mpu_is_subpage
;
11261 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11262 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
11263 if (access_type
== MMU_INST_FETCH
) {
11264 /* Instruction fetches always use the MMU bank and the
11265 * transaction attribute determined by the fetch address,
11266 * regardless of CPU state. This is painful for QEMU
11267 * to handle, because it would mean we need to encode
11268 * into the mmu_idx not just the (user, negpri) information
11269 * for the current security state but also that for the
11270 * other security state, which would balloon the number
11271 * of mmu_idx values needed alarmingly.
11272 * Fortunately we can avoid this because it's not actually
11273 * possible to arbitrarily execute code from memory with
11274 * the wrong security attribute: it will always generate
11275 * an exception of some kind or another, apart from the
11276 * special case of an NS CPU executing an SG instruction
11277 * in S&NSC memory. So we always just fail the translation
11278 * here and sort things out in the exception handler
11279 * (including possibly emulating an SG instruction).
11281 if (sattrs
.ns
!= !secure
) {
11283 fi
->type
= ARMFault_QEMU_NSCExec
;
11285 fi
->type
= ARMFault_QEMU_SFault
;
11287 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11288 *phys_ptr
= address
;
11293 /* For data accesses we always use the MMU bank indicated
11294 * by the current CPU state, but the security attributes
11295 * might downgrade a secure access to nonsecure.
11298 txattrs
->secure
= false;
11299 } else if (!secure
) {
11300 /* NS access to S memory must fault.
11301 * Architecturally we should first check whether the
11302 * MPU information for this address indicates that we
11303 * are doing an unaligned access to Device memory, which
11304 * should generate a UsageFault instead. QEMU does not
11305 * currently check for that kind of unaligned access though.
11306 * If we added it we would need to do so as a special case
11307 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11309 fi
->type
= ARMFault_QEMU_SFault
;
11310 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11311 *phys_ptr
= address
;
11318 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
11319 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
11320 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
11324 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
11325 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11326 hwaddr
*phys_ptr
, int *prot
,
11327 ARMMMUFaultInfo
*fi
)
11332 bool is_user
= regime_is_user(env
, mmu_idx
);
11334 if (regime_translation_disabled(env
, mmu_idx
)) {
11335 /* MPU disabled. */
11336 *phys_ptr
= address
;
11337 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11341 *phys_ptr
= address
;
11342 for (n
= 7; n
>= 0; n
--) {
11343 base
= env
->cp15
.c6_region
[n
];
11344 if ((base
& 1) == 0) {
11347 mask
= 1 << ((base
>> 1) & 0x1f);
11348 /* Keep this shift separate from the above to avoid an
11349 (undefined) << 32. */
11350 mask
= (mask
<< 1) - 1;
11351 if (((base
^ address
) & ~mask
) == 0) {
11356 fi
->type
= ARMFault_Background
;
11360 if (access_type
== MMU_INST_FETCH
) {
11361 mask
= env
->cp15
.pmsav5_insn_ap
;
11363 mask
= env
->cp15
.pmsav5_data_ap
;
11365 mask
= (mask
>> (n
* 4)) & 0xf;
11368 fi
->type
= ARMFault_Permission
;
11373 fi
->type
= ARMFault_Permission
;
11377 *prot
= PAGE_READ
| PAGE_WRITE
;
11382 *prot
|= PAGE_WRITE
;
11386 *prot
= PAGE_READ
| PAGE_WRITE
;
11390 fi
->type
= ARMFault_Permission
;
11400 /* Bad permission. */
11401 fi
->type
= ARMFault_Permission
;
11405 *prot
|= PAGE_EXEC
;
11409 /* Combine either inner or outer cacheability attributes for normal
11410 * memory, according to table D4-42 and pseudocode procedure
11411 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11413 * NB: only stage 1 includes allocation hints (RW bits), leading to
11416 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
11418 if (s1
== 4 || s2
== 4) {
11419 /* non-cacheable has precedence */
11421 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
11422 /* stage 1 write-through takes precedence */
11424 } else if (extract32(s2
, 2, 2) == 2) {
11425 /* stage 2 write-through takes precedence, but the allocation hint
11426 * is still taken from stage 1
11428 return (2 << 2) | extract32(s1
, 0, 2);
11429 } else { /* write-back */
11434 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11435 * and CombineS1S2Desc()
11437 * @s1: Attributes from stage 1 walk
11438 * @s2: Attributes from stage 2 walk
11440 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
11442 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
11443 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
11446 /* Combine shareability attributes (table D4-43) */
11447 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
11448 /* if either are outer-shareable, the result is outer-shareable */
11449 ret
.shareability
= 2;
11450 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
11451 /* if either are inner-shareable, the result is inner-shareable */
11452 ret
.shareability
= 3;
11454 /* both non-shareable */
11455 ret
.shareability
= 0;
11458 /* Combine memory type and cacheability attributes */
11459 if (s1hi
== 0 || s2hi
== 0) {
11460 /* Device has precedence over normal */
11461 if (s1lo
== 0 || s2lo
== 0) {
11462 /* nGnRnE has precedence over anything */
11464 } else if (s1lo
== 4 || s2lo
== 4) {
11465 /* non-Reordering has precedence over Reordering */
11466 ret
.attrs
= 4; /* nGnRE */
11467 } else if (s1lo
== 8 || s2lo
== 8) {
11468 /* non-Gathering has precedence over Gathering */
11469 ret
.attrs
= 8; /* nGRE */
11471 ret
.attrs
= 0xc; /* GRE */
11474 /* Any location for which the resultant memory type is any
11475 * type of Device memory is always treated as Outer Shareable.
11477 ret
.shareability
= 2;
11478 } else { /* Normal memory */
11479 /* Outer/inner cacheability combine independently */
11480 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
11481 | combine_cacheattr_nibble(s1lo
, s2lo
);
11483 if (ret
.attrs
== 0x44) {
11484 /* Any location for which the resultant memory type is Normal
11485 * Inner Non-cacheable, Outer Non-cacheable is always treated
11486 * as Outer Shareable.
11488 ret
.shareability
= 2;
11496 /* get_phys_addr - get the physical address for this virtual address
11498 * Find the physical address corresponding to the given virtual address,
11499 * by doing a translation table walk on MMU based systems or using the
11500 * MPU state on MPU based systems.
11502 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11503 * prot and page_size may not be filled in, and the populated fsr value provides
11504 * information on why the translation aborted, in the format of a
11505 * DFSR/IFSR fault register, with the following caveats:
11506 * * we honour the short vs long DFSR format differences.
11507 * * the WnR bit is never set (the caller must do this).
11508 * * for PSMAv5 based systems we don't bother to return a full FSR format
11511 * @env: CPUARMState
11512 * @address: virtual address to get physical address for
11513 * @access_type: 0 for read, 1 for write, 2 for execute
11514 * @mmu_idx: MMU index indicating required translation regime
11515 * @phys_ptr: set to the physical address corresponding to the virtual address
11516 * @attrs: set to the memory transaction attributes to use
11517 * @prot: set to the permissions for the page containing phys_ptr
11518 * @page_size: set to the size of the page containing phys_ptr
11519 * @fi: set to fault info if the translation fails
11520 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11522 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
11523 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11524 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
11525 target_ulong
*page_size
,
11526 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11528 if (mmu_idx
== ARMMMUIdx_E10_0
||
11529 mmu_idx
== ARMMMUIdx_E10_1
||
11530 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
11531 /* Call ourselves recursively to do the stage 1 and then stage 2
11534 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
11538 ARMCacheAttrs cacheattrs2
= {};
11540 ret
= get_phys_addr(env
, address
, access_type
,
11541 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
11542 prot
, page_size
, fi
, cacheattrs
);
11544 /* If S1 fails or S2 is disabled, return early. */
11545 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
11550 /* S1 is done. Now do S2 translation. */
11551 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_Stage2
,
11552 phys_ptr
, attrs
, &s2_prot
,
11554 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
11556 /* Combine the S1 and S2 perms. */
11559 /* Combine the S1 and S2 cache attributes, if needed */
11560 if (!ret
&& cacheattrs
!= NULL
) {
11561 if (env
->cp15
.hcr_el2
& HCR_DC
) {
11563 * HCR.DC forces the first stage attributes to
11564 * Normal Non-Shareable,
11565 * Inner Write-Back Read-Allocate Write-Allocate,
11566 * Outer Write-Back Read-Allocate Write-Allocate.
11568 cacheattrs
->attrs
= 0xff;
11569 cacheattrs
->shareability
= 0;
11571 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
11577 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
11579 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
11583 /* The page table entries may downgrade secure to non-secure, but
11584 * cannot upgrade an non-secure translation regime's attributes
11587 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
11588 attrs
->user
= regime_is_user(env
, mmu_idx
);
11590 /* Fast Context Switch Extension. This doesn't exist at all in v8.
11591 * In v7 and earlier it affects all stage 1 translations.
11593 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
11594 && !arm_feature(env
, ARM_FEATURE_V8
)) {
11595 if (regime_el(env
, mmu_idx
) == 3) {
11596 address
+= env
->cp15
.fcseidr_s
;
11598 address
+= env
->cp15
.fcseidr_ns
;
11602 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
11604 *page_size
= TARGET_PAGE_SIZE
;
11606 if (arm_feature(env
, ARM_FEATURE_V8
)) {
11608 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
11609 phys_ptr
, attrs
, prot
, page_size
, fi
);
11610 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
11612 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
11613 phys_ptr
, prot
, page_size
, fi
);
11616 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
11617 phys_ptr
, prot
, fi
);
11619 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
11620 " mmu_idx %u -> %s (prot %c%c%c)\n",
11621 access_type
== MMU_DATA_LOAD
? "reading" :
11622 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
11623 (uint32_t)address
, mmu_idx
,
11624 ret
? "Miss" : "Hit",
11625 *prot
& PAGE_READ
? 'r' : '-',
11626 *prot
& PAGE_WRITE
? 'w' : '-',
11627 *prot
& PAGE_EXEC
? 'x' : '-');
11632 /* Definitely a real MMU, not an MPU */
11634 if (regime_translation_disabled(env
, mmu_idx
)) {
11635 /* MMU disabled. */
11636 *phys_ptr
= address
;
11637 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11638 *page_size
= TARGET_PAGE_SIZE
;
11642 if (regime_using_lpae_format(env
, mmu_idx
)) {
11643 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
11644 phys_ptr
, attrs
, prot
, page_size
,
11646 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
11647 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
11648 phys_ptr
, attrs
, prot
, page_size
, fi
);
11650 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
11651 phys_ptr
, prot
, page_size
, fi
);
11655 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
11658 ARMCPU
*cpu
= ARM_CPU(cs
);
11659 CPUARMState
*env
= &cpu
->env
;
11661 target_ulong page_size
;
11664 ARMMMUFaultInfo fi
= {};
11665 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
11667 *attrs
= (MemTxAttrs
) {};
11669 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
11670 attrs
, &prot
, &page_size
, &fi
, NULL
);
11680 /* Note that signed overflow is undefined in C. The following routines are
11681 careful to use unsigned types where modulo arithmetic is required.
11682 Failure to do so _will_ break on newer gcc. */
11684 /* Signed saturating arithmetic. */
11686 /* Perform 16-bit signed saturating addition. */
11687 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11692 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11701 /* Perform 8-bit signed saturating addition. */
11702 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11707 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11716 /* Perform 16-bit signed saturating subtraction. */
11717 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11722 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11731 /* Perform 8-bit signed saturating subtraction. */
11732 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11737 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11746 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11747 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11748 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11749 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11752 #include "op_addsub.h"
11754 /* Unsigned saturating arithmetic. */
11755 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11764 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11772 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11781 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11789 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11790 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11791 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11792 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11795 #include "op_addsub.h"
11797 /* Signed modulo arithmetic. */
11798 #define SARITH16(a, b, n, op) do { \
11800 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11801 RESULT(sum, n, 16); \
11803 ge |= 3 << (n * 2); \
11806 #define SARITH8(a, b, n, op) do { \
11808 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11809 RESULT(sum, n, 8); \
11815 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11816 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11817 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11818 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11822 #include "op_addsub.h"
11824 /* Unsigned modulo arithmetic. */
11825 #define ADD16(a, b, n) do { \
11827 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11828 RESULT(sum, n, 16); \
11829 if ((sum >> 16) == 1) \
11830 ge |= 3 << (n * 2); \
11833 #define ADD8(a, b, n) do { \
11835 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11836 RESULT(sum, n, 8); \
11837 if ((sum >> 8) == 1) \
11841 #define SUB16(a, b, n) do { \
11843 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11844 RESULT(sum, n, 16); \
11845 if ((sum >> 16) == 0) \
11846 ge |= 3 << (n * 2); \
11849 #define SUB8(a, b, n) do { \
11851 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11852 RESULT(sum, n, 8); \
11853 if ((sum >> 8) == 0) \
11860 #include "op_addsub.h"
11862 /* Halved signed arithmetic. */
11863 #define ADD16(a, b, n) \
11864 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11865 #define SUB16(a, b, n) \
11866 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11867 #define ADD8(a, b, n) \
11868 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11869 #define SUB8(a, b, n) \
11870 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11873 #include "op_addsub.h"
11875 /* Halved unsigned arithmetic. */
11876 #define ADD16(a, b, n) \
11877 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11878 #define SUB16(a, b, n) \
11879 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11880 #define ADD8(a, b, n) \
11881 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11882 #define SUB8(a, b, n) \
11883 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11886 #include "op_addsub.h"
11888 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11896 /* Unsigned sum of absolute byte differences. */
11897 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11900 sum
= do_usad(a
, b
);
11901 sum
+= do_usad(a
>> 8, b
>> 8);
11902 sum
+= do_usad(a
>> 16, b
>>16);
11903 sum
+= do_usad(a
>> 24, b
>> 24);
11907 /* For ARMv6 SEL instruction. */
11908 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11920 mask
|= 0xff000000;
11921 return (a
& mask
) | (b
& ~mask
);
11925 * The upper bytes of val (above the number specified by 'bytes') must have
11926 * been zeroed out by the caller.
11928 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11932 stl_le_p(buf
, val
);
11934 /* zlib crc32 converts the accumulator and output to one's complement. */
11935 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11938 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11942 stl_le_p(buf
, val
);
11944 /* Linux crc32c converts the output to one's complement. */
11945 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11948 /* Return the exception level to which FP-disabled exceptions should
11949 * be taken, or 0 if FP is enabled.
11951 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11953 #ifndef CONFIG_USER_ONLY
11954 /* CPACR and the CPTR registers don't exist before v6, so FP is
11955 * always accessible
11957 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11961 if (arm_feature(env
, ARM_FEATURE_M
)) {
11962 /* CPACR can cause a NOCP UsageFault taken to current security state */
11963 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11967 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11968 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11969 /* FP insns cause a NOCP UsageFault taken to Secure */
11977 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11978 * 0, 2 : trap EL0 and EL1/PL1 accesses
11979 * 1 : trap only EL0 accesses
11980 * 3 : trap no accesses
11981 * This register is ignored if E2H+TGE are both set.
11983 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11984 int fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
11989 if (cur_el
== 0 || cur_el
== 1) {
11990 /* Trap to PL1, which might be EL1 or EL3 */
11991 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
11996 if (cur_el
== 3 && !is_a64(env
)) {
11997 /* Secure PL1 running at EL3 */
12012 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12013 * to control non-secure access to the FPU. It doesn't have any
12014 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12016 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12017 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12018 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12019 /* FP insns act as UNDEF */
12020 return cur_el
== 2 ? 2 : 1;
12024 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12025 * check because zero bits in the registers mean "don't trap".
12028 /* CPTR_EL2 : present in v7VE or v8 */
12029 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
12030 && !arm_is_secure_below_el3(env
)) {
12031 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12035 /* CPTR_EL3 : present in v8 */
12036 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
12037 /* Trap all FP ops to EL3 */
12044 /* Return the exception level we're running at if this is our mmu_idx */
12045 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12047 if (mmu_idx
& ARM_MMU_IDX_M
) {
12048 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12052 case ARMMMUIdx_E10_0
:
12053 case ARMMMUIdx_E20_0
:
12054 case ARMMMUIdx_SE10_0
:
12056 case ARMMMUIdx_E10_1
:
12057 case ARMMMUIdx_E10_1_PAN
:
12058 case ARMMMUIdx_SE10_1
:
12059 case ARMMMUIdx_SE10_1_PAN
:
12062 case ARMMMUIdx_E20_2
:
12063 case ARMMMUIdx_E20_2_PAN
:
12065 case ARMMMUIdx_SE3
:
12068 g_assert_not_reached();
12073 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12075 g_assert_not_reached();
12079 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12081 if (arm_feature(env
, ARM_FEATURE_M
)) {
12082 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12085 /* See ARM pseudo-function ELIsInHost. */
12088 if (arm_is_secure_below_el3(env
)) {
12089 return ARMMMUIdx_SE10_0
;
12091 if ((env
->cp15
.hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)
12092 && arm_el_is_aa64(env
, 2)) {
12093 return ARMMMUIdx_E20_0
;
12095 return ARMMMUIdx_E10_0
;
12097 if (arm_is_secure_below_el3(env
)) {
12098 if (env
->pstate
& PSTATE_PAN
) {
12099 return ARMMMUIdx_SE10_1_PAN
;
12101 return ARMMMUIdx_SE10_1
;
12103 if (env
->pstate
& PSTATE_PAN
) {
12104 return ARMMMUIdx_E10_1_PAN
;
12106 return ARMMMUIdx_E10_1
;
12108 /* TODO: ARMv8.4-SecEL2 */
12109 /* Note that TGE does not apply at EL2. */
12110 if ((env
->cp15
.hcr_el2
& HCR_E2H
) && arm_el_is_aa64(env
, 2)) {
12111 if (env
->pstate
& PSTATE_PAN
) {
12112 return ARMMMUIdx_E20_2_PAN
;
12114 return ARMMMUIdx_E20_2
;
12116 return ARMMMUIdx_E2
;
12118 return ARMMMUIdx_SE3
;
12120 g_assert_not_reached();
12124 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12126 return arm_mmu_idx_el(env
, arm_current_el(env
));
12129 int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
12131 return arm_to_core_mmu_idx(arm_mmu_idx(env
));
12134 #ifndef CONFIG_USER_ONLY
12135 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
12137 return stage_1_mmu_idx(arm_mmu_idx(env
));
12141 static uint32_t rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
12142 ARMMMUIdx mmu_idx
, uint32_t flags
)
12144 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
12145 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
,
12146 arm_to_core_mmu_idx(mmu_idx
));
12148 if (arm_singlestep_active(env
)) {
12149 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
12154 static uint32_t rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
12155 ARMMMUIdx mmu_idx
, uint32_t flags
)
12157 bool sctlr_b
= arm_sctlr_b(env
);
12160 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, 1);
12162 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
12163 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
12165 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
12167 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12170 static uint32_t rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
12173 uint32_t flags
= 0;
12175 if (arm_v7m_is_handler_mode(env
)) {
12176 flags
= FIELD_DP32(flags
, TBFLAG_M32
, HANDLER
, 1);
12180 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
12181 * is suppressing them because the requested execution priority
12184 if (arm_feature(env
, ARM_FEATURE_V8
) &&
12185 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
12186 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
12187 flags
= FIELD_DP32(flags
, TBFLAG_M32
, STACKCHECK
, 1);
12190 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12193 static uint32_t rebuild_hflags_aprofile(CPUARMState
*env
)
12197 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
,
12198 arm_debug_target_el(env
));
12202 static uint32_t rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
12205 uint32_t flags
= rebuild_hflags_aprofile(env
);
12207 if (arm_el_is_aa64(env
, 1)) {
12208 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12211 if (arm_current_el(env
) < 2 && env
->cp15
.hstr_el2
&&
12212 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12213 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HSTR_ACTIVE
, 1);
12216 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12219 static uint32_t rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
12222 uint32_t flags
= rebuild_hflags_aprofile(env
);
12223 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
12224 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
12228 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
12230 /* Get control bits for tagged addresses. */
12231 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12232 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12234 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
12235 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
12237 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
12238 int sve_el
= sve_exception_el(env
, el
);
12242 * If SVE is disabled, but FP is enabled,
12243 * then the effective len is 0.
12245 if (sve_el
!= 0 && fp_el
== 0) {
12248 zcr_len
= sve_zcr_len_for_el(env
, el
);
12250 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
12251 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
12254 sctlr
= regime_sctlr(env
, stage1
);
12256 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
12257 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
12260 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
12262 * In order to save space in flags, we record only whether
12263 * pauth is "inactive", meaning all insns are implemented as
12264 * a nop, or "active" when some action must be performed.
12265 * The decision of which action to take is left to a helper.
12267 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
12268 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
12272 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12273 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12274 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
12275 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
12279 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12280 if (!(env
->pstate
& PSTATE_UAO
)) {
12282 case ARMMMUIdx_E10_1
:
12283 case ARMMMUIdx_E10_1_PAN
:
12284 case ARMMMUIdx_SE10_1
:
12285 case ARMMMUIdx_SE10_1_PAN
:
12286 /* TODO: ARMv8.3-NV */
12287 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
12289 case ARMMMUIdx_E20_2
:
12290 case ARMMMUIdx_E20_2_PAN
:
12291 /* TODO: ARMv8.4-SecEL2 */
12293 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12294 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12296 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
12297 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
12305 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12308 static uint32_t rebuild_hflags_internal(CPUARMState
*env
)
12310 int el
= arm_current_el(env
);
12311 int fp_el
= fp_exception_el(env
, el
);
12312 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12315 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12316 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
12317 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12319 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12323 void arm_rebuild_hflags(CPUARMState
*env
)
12325 env
->hflags
= rebuild_hflags_internal(env
);
12328 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
12330 int fp_el
= fp_exception_el(env
, el
);
12331 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12333 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12337 * If we have triggered a EL state change we can't rely on the
12338 * translator having passed it too us, we need to recompute.
12340 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
12342 int el
= arm_current_el(env
);
12343 int fp_el
= fp_exception_el(env
, el
);
12344 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12345 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12348 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
12350 int fp_el
= fp_exception_el(env
, el
);
12351 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12353 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12356 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
12358 int fp_el
= fp_exception_el(env
, el
);
12359 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12361 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12364 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
12366 #ifdef CONFIG_DEBUG_TCG
12367 uint32_t env_flags_current
= env
->hflags
;
12368 uint32_t env_flags_rebuilt
= rebuild_hflags_internal(env
);
12370 if (unlikely(env_flags_current
!= env_flags_rebuilt
)) {
12371 fprintf(stderr
, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
12372 env_flags_current
, env_flags_rebuilt
);
12378 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12379 target_ulong
*cs_base
, uint32_t *pflags
)
12381 uint32_t flags
= env
->hflags
;
12382 uint32_t pstate_for_ss
;
12385 assert_hflags_rebuild_correctly(env
);
12387 if (FIELD_EX32(flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
12389 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12390 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
12392 pstate_for_ss
= env
->pstate
;
12394 *pc
= env
->regs
[15];
12396 if (arm_feature(env
, ARM_FEATURE_M
)) {
12397 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12398 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12399 != env
->v7m
.secure
) {
12400 flags
= FIELD_DP32(flags
, TBFLAG_M32
, FPCCR_S_WRONG
, 1);
12403 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12404 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12405 (env
->v7m
.secure
&&
12406 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12408 * ASPEN is set, but FPCA/SFPA indicate that there is no
12409 * active FP context; we must create a new FP context before
12410 * executing any FP insn.
12412 flags
= FIELD_DP32(flags
, TBFLAG_M32
, NEW_FP_CTXT_NEEDED
, 1);
12415 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12416 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12417 flags
= FIELD_DP32(flags
, TBFLAG_M32
, LSPACT
, 1);
12421 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12422 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12424 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12425 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
12426 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12428 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
,
12430 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
,
12431 env
->vfp
.vec_stride
);
12433 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12434 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12438 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, THUMB
, env
->thumb
);
12439 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, CONDEXEC
, env
->condexec_bits
);
12440 pstate_for_ss
= env
->uncached_cpsr
;
12444 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12445 * states defined in the ARM ARM for software singlestep:
12446 * SS_ACTIVE PSTATE.SS State
12447 * 0 x Inactive (the TB flag for SS is always 0)
12448 * 1 0 Active-pending
12449 * 1 1 Active-not-pending
12450 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
12452 if (FIELD_EX32(flags
, TBFLAG_ANY
, SS_ACTIVE
) &&
12453 (pstate_for_ss
& PSTATE_SS
)) {
12454 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
12460 #ifdef TARGET_AARCH64
12462 * The manual says that when SVE is enabled and VQ is widened the
12463 * implementation is allowed to zero the previously inaccessible
12464 * portion of the registers. The corollary to that is that when
12465 * SVE is enabled and VQ is narrowed we are also allowed to zero
12466 * the now inaccessible portion of the registers.
12468 * The intent of this is that no predicate bit beyond VQ is ever set.
12469 * Which means that some operations on predicate registers themselves
12470 * may operate on full uint64_t or even unrolled across the maximum
12471 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12472 * may well be cheaper than conditionals to restrict the operation
12473 * to the relevant portion of a uint16_t[16].
12475 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12480 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12481 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12483 /* Zap the high bits of the zregs. */
12484 for (i
= 0; i
< 32; i
++) {
12485 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12488 /* Zap the high bits of the pregs and ffr. */
12491 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12493 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12494 for (i
= 0; i
< 17; ++i
) {
12495 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12502 * Notice a change in SVE vector size when changing EL.
12504 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12505 int new_el
, bool el0_a64
)
12507 ARMCPU
*cpu
= env_archcpu(env
);
12508 int old_len
, new_len
;
12509 bool old_a64
, new_a64
;
12511 /* Nothing to do if no SVE. */
12512 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12516 /* Nothing to do if FP is disabled in either EL. */
12517 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12522 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12523 * at ELx, or not available because the EL is in AArch32 state, then
12524 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12525 * has an effective value of 0".
12527 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12528 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12529 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12530 * we already have the correct register contents when encountering the
12531 * vq0->vq0 transition between EL0->EL1.
12533 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12534 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
12535 ? sve_zcr_len_for_el(env
, old_el
) : 0);
12536 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12537 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
12538 ? sve_zcr_len_for_el(env
, new_el
) : 0);
12540 /* When changing vector length, clear inaccessible state. */
12541 if (new_len
< old_len
) {
12542 aarch64_sve_narrow_vq(env
, new_len
+ 1);