4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
16 #include "qemu/timer.h"
17 #include "qemu/bitops.h"
18 #include "qemu/crc32c.h"
19 #include "qemu/qemu-print.h"
20 #include "exec/exec-all.h"
21 #include <zlib.h> /* For crc32 */
23 #include "sysemu/cpu-timers.h"
24 #include "sysemu/kvm.h"
25 #include "qapi/qapi-commands-machine-target.h"
26 #include "qapi/error.h"
27 #include "qemu/guest-random.h"
29 #include "semihosting/common-semi.h"
33 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
35 static void switch_mode(CPUARMState
*env
, int mode
);
37 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
39 assert(ri
->fieldoffset
);
40 if (cpreg_field_is_64bit(ri
)) {
41 return CPREG_FIELD64(env
, ri
);
43 return CPREG_FIELD32(env
, ri
);
47 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
49 assert(ri
->fieldoffset
);
50 if (cpreg_field_is_64bit(ri
)) {
51 CPREG_FIELD64(env
, ri
) = value
;
53 CPREG_FIELD32(env
, ri
) = value
;
57 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
59 return (char *)env
+ ri
->fieldoffset
;
62 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
64 /* Raw read of a coprocessor register (as needed for migration, etc). */
65 if (ri
->type
& ARM_CP_CONST
) {
66 return ri
->resetvalue
;
67 } else if (ri
->raw_readfn
) {
68 return ri
->raw_readfn(env
, ri
);
69 } else if (ri
->readfn
) {
70 return ri
->readfn(env
, ri
);
72 return raw_read(env
, ri
);
76 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
80 * Raw write of a coprocessor register (as needed for migration, etc).
81 * Note that constant registers are treated as write-ignored; the
82 * caller should check for success by whether a readback gives the
85 if (ri
->type
& ARM_CP_CONST
) {
87 } else if (ri
->raw_writefn
) {
88 ri
->raw_writefn(env
, ri
, v
);
89 } else if (ri
->writefn
) {
90 ri
->writefn(env
, ri
, v
);
92 raw_write(env
, ri
, v
);
96 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
99 * Return true if the regdef would cause an assertion if you called
100 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
101 * program bug for it not to have the NO_RAW flag).
102 * NB that returning false here doesn't necessarily mean that calling
103 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
104 * read/write access functions which are safe for raw use" from "has
105 * read/write access functions which have side effects but has forgotten
106 * to provide raw access functions".
107 * The tests here line up with the conditions in read/write_raw_cp_reg()
108 * and assertions in raw_read()/raw_write().
110 if ((ri
->type
& ARM_CP_CONST
) ||
112 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
118 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
120 /* Write the coprocessor state from cpu->env to the (index,value) list. */
124 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
125 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
126 const ARMCPRegInfo
*ri
;
129 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
134 if (ri
->type
& ARM_CP_NO_RAW
) {
138 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
141 * Only sync if the previous list->cpustate sync succeeded.
142 * Rather than tracking the success/failure state for every
143 * item in the list, we just recheck "does the raw write we must
144 * have made in write_list_to_cpustate() read back OK" here.
146 uint64_t oldval
= cpu
->cpreg_values
[i
];
148 if (oldval
== newval
) {
152 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
153 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
157 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
159 cpu
->cpreg_values
[i
] = newval
;
164 bool write_list_to_cpustate(ARMCPU
*cpu
)
169 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
170 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
171 uint64_t v
= cpu
->cpreg_values
[i
];
172 const ARMCPRegInfo
*ri
;
174 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
179 if (ri
->type
& ARM_CP_NO_RAW
) {
183 * Write value and confirm it reads back as written
184 * (to catch read-only registers and partially read-only
185 * registers where the incoming migration value doesn't match)
187 write_raw_cp_reg(&cpu
->env
, ri
, v
);
188 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
195 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
197 ARMCPU
*cpu
= opaque
;
198 uint32_t regidx
= (uintptr_t)key
;
199 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
201 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
202 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
203 /* The value array need not be initialized at this point */
204 cpu
->cpreg_array_len
++;
208 static void count_cpreg(gpointer key
, gpointer opaque
)
210 ARMCPU
*cpu
= opaque
;
211 const ARMCPRegInfo
*ri
;
213 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
215 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
216 cpu
->cpreg_array_len
++;
220 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
222 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
223 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
234 void init_cpreg_list(ARMCPU
*cpu
)
237 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
238 * Note that we require cpreg_tuples[] to be sorted by key ID.
243 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
244 keys
= g_list_sort(keys
, cpreg_key_compare
);
246 cpu
->cpreg_array_len
= 0;
248 g_list_foreach(keys
, count_cpreg
, cpu
);
250 arraylen
= cpu
->cpreg_array_len
;
251 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
252 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
256 cpu
->cpreg_array_len
= 0;
258 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
260 assert(cpu
->cpreg_array_len
== arraylen
);
266 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
268 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
269 const ARMCPRegInfo
*ri
,
272 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
273 arm_is_secure_below_el3(env
)) {
274 return CP_ACCESS_TRAP_UNCATEGORIZED
;
280 * Some secure-only AArch32 registers trap to EL3 if used from
281 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
282 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
283 * We assume that the .access field is set to PL1_RW.
285 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
286 const ARMCPRegInfo
*ri
,
289 if (arm_current_el(env
) == 3) {
292 if (arm_is_secure_below_el3(env
)) {
293 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
294 return CP_ACCESS_TRAP_EL2
;
296 return CP_ACCESS_TRAP_EL3
;
298 /* This will be EL1 NS and EL2 NS, which just UNDEF */
299 return CP_ACCESS_TRAP_UNCATEGORIZED
;
303 * Check for traps to performance monitor registers, which are controlled
304 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
306 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
309 int el
= arm_current_el(env
);
310 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
312 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
313 return CP_ACCESS_TRAP_EL2
;
315 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
316 return CP_ACCESS_TRAP_EL3
;
321 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
322 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
325 if (arm_current_el(env
) == 1) {
326 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
327 if (arm_hcr_el2_eff(env
) & trap
) {
328 return CP_ACCESS_TRAP_EL2
;
334 /* Check for traps from EL1 due to HCR_EL2.TSW. */
335 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
338 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
339 return CP_ACCESS_TRAP_EL2
;
344 /* Check for traps from EL1 due to HCR_EL2.TACR. */
345 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
348 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
349 return CP_ACCESS_TRAP_EL2
;
354 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
355 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
358 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
359 return CP_ACCESS_TRAP_EL2
;
364 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
365 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
368 if (arm_current_el(env
) == 1 &&
369 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
370 return CP_ACCESS_TRAP_EL2
;
375 #ifdef TARGET_AARCH64
376 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
377 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
380 if (arm_current_el(env
) == 1 &&
381 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
382 return CP_ACCESS_TRAP_EL2
;
388 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
390 ARMCPU
*cpu
= env_archcpu(env
);
392 raw_write(env
, ri
, value
);
393 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
396 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
398 ARMCPU
*cpu
= env_archcpu(env
);
400 if (raw_read(env
, ri
) != value
) {
402 * Unlike real hardware the qemu TLB uses virtual addresses,
403 * not modified virtual addresses, so this causes a TLB flush.
406 raw_write(env
, ri
, value
);
410 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
413 ARMCPU
*cpu
= env_archcpu(env
);
415 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
416 && !extended_addresses_enabled(env
)) {
418 * For VMSA (when not using the LPAE long descriptor page table
419 * format) this register includes the ASID, so do a TLB flush.
420 * For PMSA it is purely a process ID and no action is needed.
424 raw_write(env
, ri
, value
);
427 static int alle1_tlbmask(CPUARMState
*env
)
430 * Note that the 'ALL' scope must invalidate both stage 1 and
431 * stage 2 translations, whereas most other scopes only invalidate
432 * stage 1 translations.
434 return (ARMMMUIdxBit_E10_1
|
435 ARMMMUIdxBit_E10_1_PAN
|
437 ARMMMUIdxBit_Stage2
|
438 ARMMMUIdxBit_Stage2_S
);
442 /* IS variants of TLB operations must affect all cores */
443 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
446 CPUState
*cs
= env_cpu(env
);
448 tlb_flush_all_cpus_synced(cs
);
451 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
454 CPUState
*cs
= env_cpu(env
);
456 tlb_flush_all_cpus_synced(cs
);
459 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
462 CPUState
*cs
= env_cpu(env
);
464 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
467 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
470 CPUState
*cs
= env_cpu(env
);
472 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
476 * Non-IS variants of TLB operations are upgraded to
477 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
478 * force broadcast of these operations.
480 static bool tlb_force_broadcast(CPUARMState
*env
)
482 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
485 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 /* Invalidate all (TLBIALL) */
489 CPUState
*cs
= env_cpu(env
);
491 if (tlb_force_broadcast(env
)) {
492 tlb_flush_all_cpus_synced(cs
);
498 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
502 CPUState
*cs
= env_cpu(env
);
504 value
&= TARGET_PAGE_MASK
;
505 if (tlb_force_broadcast(env
)) {
506 tlb_flush_page_all_cpus_synced(cs
, value
);
508 tlb_flush_page(cs
, value
);
512 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 /* Invalidate by ASID (TLBIASID) */
516 CPUState
*cs
= env_cpu(env
);
518 if (tlb_force_broadcast(env
)) {
519 tlb_flush_all_cpus_synced(cs
);
525 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
529 CPUState
*cs
= env_cpu(env
);
531 value
&= TARGET_PAGE_MASK
;
532 if (tlb_force_broadcast(env
)) {
533 tlb_flush_page_all_cpus_synced(cs
, value
);
535 tlb_flush_page(cs
, value
);
539 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
542 CPUState
*cs
= env_cpu(env
);
544 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
547 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
550 CPUState
*cs
= env_cpu(env
);
552 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
556 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
559 CPUState
*cs
= env_cpu(env
);
561 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
564 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 CPUState
*cs
= env_cpu(env
);
569 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
572 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
575 CPUState
*cs
= env_cpu(env
);
576 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
578 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
581 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
584 CPUState
*cs
= env_cpu(env
);
585 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
587 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
591 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
594 CPUState
*cs
= env_cpu(env
);
595 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
597 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
600 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
603 CPUState
*cs
= env_cpu(env
);
604 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
606 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
609 static const ARMCPRegInfo cp_reginfo
[] = {
611 * Define the secure and non-secure FCSE identifier CP registers
612 * separately because there is no secure bank in V8 (no _EL3). This allows
613 * the secure register to be properly reset and migrated. There is also no
614 * v8 EL1 version of the register so the non-secure instance stands alone.
617 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
618 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
619 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
620 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
621 { .name
= "FCSEIDR_S",
622 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
623 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
624 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
625 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
627 * Define the secure and non-secure context identifier CP registers
628 * separately because there is no secure bank in V8 (no _EL3). This allows
629 * the secure register to be properly reset and migrated. In the
630 * non-secure case, the 32-bit register will have reset and migration
631 * disabled during registration as it is handled by the 64-bit instance.
633 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
634 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
635 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
636 .fgt
= FGT_CONTEXTIDR_EL1
,
637 .secure
= ARM_CP_SECSTATE_NS
,
638 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
639 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
640 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
641 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
642 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
643 .secure
= ARM_CP_SECSTATE_S
,
644 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
645 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
648 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
650 * NB: Some of these registers exist in v8 but with more precise
651 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
653 /* MMU Domain access control / MPU write buffer control */
655 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
656 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
657 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
658 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
659 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
661 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
662 * For v6 and v5, these mappings are overly broad.
664 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
665 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
666 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
667 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
668 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
669 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
670 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
671 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
672 /* Cache maintenance ops; some of this space may be overridden later. */
673 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
674 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
675 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
678 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
680 * Not all pre-v6 cores implemented this WFI, so this is slightly
683 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
684 .access
= PL1_W
, .type
= ARM_CP_WFI
},
687 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
689 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
690 * is UNPREDICTABLE; we choose to NOP as most implementations do).
692 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
693 .access
= PL1_W
, .type
= ARM_CP_WFI
},
695 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
696 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
697 * OMAPCP will override this space.
699 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
700 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
702 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
703 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
705 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
706 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
707 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
710 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
711 * implementing it as RAZ means the "debug architecture version" bits
712 * will read as a reserved value, which should cause Linux to not try
713 * to use the debug hardware.
715 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
716 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
718 * MMU TLB control. Note that the wildcarding means we cover not just
719 * the unified TLB ops but also the dside/iside/inner-shareable variants.
721 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
722 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
723 .type
= ARM_CP_NO_RAW
},
724 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
725 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
726 .type
= ARM_CP_NO_RAW
},
727 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
728 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
729 .type
= ARM_CP_NO_RAW
},
730 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
731 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
732 .type
= ARM_CP_NO_RAW
},
733 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
734 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
735 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
736 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
739 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
744 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
745 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
747 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
748 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
749 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
751 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
752 /* VFP coprocessor: cp10 & cp11 [23:20] */
753 mask
|= R_CPACR_ASEDIS_MASK
|
754 R_CPACR_D32DIS_MASK
|
758 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
759 /* ASEDIS [31] bit is RAO/WI */
760 value
|= R_CPACR_ASEDIS_MASK
;
764 * VFPv3 and upwards with NEON implement 32 double precision
765 * registers (D0-D31).
767 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
768 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
769 value
|= R_CPACR_D32DIS_MASK
;
776 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
777 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
779 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
780 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
781 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
782 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
785 env
->cp15
.cpacr_el1
= value
;
788 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
791 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
792 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
794 uint64_t value
= env
->cp15
.cpacr_el1
;
796 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
797 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
798 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
804 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
807 * Call cpacr_write() so that we reset with the correct RAO bits set
808 * for our CPU features.
810 cpacr_write(env
, ri
, 0);
813 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
816 if (arm_feature(env
, ARM_FEATURE_V8
)) {
817 /* Check if CPACR accesses are to be trapped to EL2 */
818 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
819 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
820 return CP_ACCESS_TRAP_EL2
;
821 /* Check if CPACR accesses are to be trapped to EL3 */
822 } else if (arm_current_el(env
) < 3 &&
823 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
824 return CP_ACCESS_TRAP_EL3
;
831 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
834 /* Check if CPTR accesses are set to trap to EL3 */
835 if (arm_current_el(env
) == 2 &&
836 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
837 return CP_ACCESS_TRAP_EL3
;
843 static const ARMCPRegInfo v6_cp_reginfo
[] = {
844 /* prefetch by MVA in v6, NOP in v7 */
845 { .name
= "MVA_prefetch",
846 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
847 .access
= PL1_W
, .type
= ARM_CP_NOP
},
849 * We need to break the TB after ISB to execute self-modifying code
850 * correctly and also to take any pending interrupts immediately.
851 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
853 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
854 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
855 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
856 .access
= PL0_W
, .type
= ARM_CP_NOP
},
857 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
858 .access
= PL0_W
, .type
= ARM_CP_NOP
},
859 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
860 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
861 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
862 offsetof(CPUARMState
, cp15
.ifar_ns
) },
865 * Watchpoint Fault Address Register : should actually only be present
866 * for 1136, 1176, 11MPCore.
868 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
869 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
870 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
871 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
872 .fgt
= FGT_CPACR_EL1
,
873 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
874 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
877 typedef struct pm_event
{
878 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
879 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
880 bool (*supported
)(CPUARMState
*);
882 * Retrieve the current count of the underlying event. The programmed
883 * counters hold a difference from the return value from this function
885 uint64_t (*get_count
)(CPUARMState
*);
887 * Return how many nanoseconds it will take (at a minimum) for count events
888 * to occur. A negative value indicates the counter will never overflow, or
889 * that the counter has otherwise arranged for the overflow bit to be set
890 * and the PMU interrupt to be raised on overflow.
892 int64_t (*ns_per_count
)(uint64_t);
895 static bool event_always_supported(CPUARMState
*env
)
900 static uint64_t swinc_get_count(CPUARMState
*env
)
903 * SW_INCR events are written directly to the pmevcntr's by writes to
904 * PMSWINC, so there is no underlying count maintained by the PMU itself
909 static int64_t swinc_ns_per(uint64_t ignored
)
915 * Return the underlying cycle count for the PMU cycle counters. If we're in
916 * usermode, simply return 0.
918 static uint64_t cycles_get_count(CPUARMState
*env
)
920 #ifndef CONFIG_USER_ONLY
921 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
922 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
924 return cpu_get_host_ticks();
928 #ifndef CONFIG_USER_ONLY
929 static int64_t cycles_ns_per(uint64_t cycles
)
931 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
934 static bool instructions_supported(CPUARMState
*env
)
936 return icount_enabled() == 1; /* Precise instruction counting */
939 static uint64_t instructions_get_count(CPUARMState
*env
)
941 return (uint64_t)icount_get_raw();
944 static int64_t instructions_ns_per(uint64_t icount
)
946 return icount_to_ns((int64_t)icount
);
950 static bool pmuv3p1_events_supported(CPUARMState
*env
)
952 /* For events which are supported in any v8.1 PMU */
953 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
956 static bool pmuv3p4_events_supported(CPUARMState
*env
)
958 /* For events which are supported in any v8.1 PMU */
959 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
962 static uint64_t zero_event_get_count(CPUARMState
*env
)
964 /* For events which on QEMU never fire, so their count is always zero */
968 static int64_t zero_event_ns_per(uint64_t cycles
)
970 /* An event which never fires can never overflow */
974 static const pm_event pm_events
[] = {
975 { .number
= 0x000, /* SW_INCR */
976 .supported
= event_always_supported
,
977 .get_count
= swinc_get_count
,
978 .ns_per_count
= swinc_ns_per
,
980 #ifndef CONFIG_USER_ONLY
981 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
982 .supported
= instructions_supported
,
983 .get_count
= instructions_get_count
,
984 .ns_per_count
= instructions_ns_per
,
986 { .number
= 0x011, /* CPU_CYCLES, Cycle */
987 .supported
= event_always_supported
,
988 .get_count
= cycles_get_count
,
989 .ns_per_count
= cycles_ns_per
,
992 { .number
= 0x023, /* STALL_FRONTEND */
993 .supported
= pmuv3p1_events_supported
,
994 .get_count
= zero_event_get_count
,
995 .ns_per_count
= zero_event_ns_per
,
997 { .number
= 0x024, /* STALL_BACKEND */
998 .supported
= pmuv3p1_events_supported
,
999 .get_count
= zero_event_get_count
,
1000 .ns_per_count
= zero_event_ns_per
,
1002 { .number
= 0x03c, /* STALL */
1003 .supported
= pmuv3p4_events_supported
,
1004 .get_count
= zero_event_get_count
,
1005 .ns_per_count
= zero_event_ns_per
,
1010 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1011 * events (i.e. the statistical profiling extension), this implementation
1012 * should first be updated to something sparse instead of the current
1013 * supported_event_map[] array.
1015 #define MAX_EVENT_ID 0x3c
1016 #define UNSUPPORTED_EVENT UINT16_MAX
1017 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1020 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1021 * of ARM event numbers to indices in our pm_events array.
1023 * Note: Events in the 0x40XX range are not currently supported.
1025 void pmu_init(ARMCPU
*cpu
)
1030 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1033 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1034 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1039 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1040 const pm_event
*cnt
= &pm_events
[i
];
1041 assert(cnt
->number
<= MAX_EVENT_ID
);
1042 /* We do not currently support events in the 0x40xx range */
1043 assert(cnt
->number
<= 0x3f);
1045 if (cnt
->supported(&cpu
->env
)) {
1046 supported_event_map
[cnt
->number
] = i
;
1047 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1048 if (cnt
->number
& 0x20) {
1049 cpu
->pmceid1
|= event_mask
;
1051 cpu
->pmceid0
|= event_mask
;
1058 * Check at runtime whether a PMU event is supported for the current machine
1060 static bool event_supported(uint16_t number
)
1062 if (number
> MAX_EVENT_ID
) {
1065 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1068 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1072 * Performance monitor registers user accessibility is controlled
1073 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1074 * trapping to EL2 or EL3 for other accesses.
1076 int el
= arm_current_el(env
);
1077 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1079 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1080 return CP_ACCESS_TRAP
;
1082 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1083 return CP_ACCESS_TRAP_EL2
;
1085 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1086 return CP_ACCESS_TRAP_EL3
;
1089 return CP_ACCESS_OK
;
1092 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1093 const ARMCPRegInfo
*ri
,
1096 /* ER: event counter read trap control */
1097 if (arm_feature(env
, ARM_FEATURE_V8
)
1098 && arm_current_el(env
) == 0
1099 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1101 return CP_ACCESS_OK
;
1104 return pmreg_access(env
, ri
, isread
);
1107 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1108 const ARMCPRegInfo
*ri
,
1111 /* SW: software increment write trap control */
1112 if (arm_feature(env
, ARM_FEATURE_V8
)
1113 && arm_current_el(env
) == 0
1114 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1116 return CP_ACCESS_OK
;
1119 return pmreg_access(env
, ri
, isread
);
1122 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1123 const ARMCPRegInfo
*ri
,
1126 /* ER: event counter read trap control */
1127 if (arm_feature(env
, ARM_FEATURE_V8
)
1128 && arm_current_el(env
) == 0
1129 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1130 return CP_ACCESS_OK
;
1133 return pmreg_access(env
, ri
, isread
);
1136 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1137 const ARMCPRegInfo
*ri
,
1140 /* CR: cycle counter read trap control */
1141 if (arm_feature(env
, ARM_FEATURE_V8
)
1142 && arm_current_el(env
) == 0
1143 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1145 return CP_ACCESS_OK
;
1148 return pmreg_access(env
, ri
, isread
);
1152 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1153 * We use these to decide whether we need to wrap a write to MDCR_EL2
1154 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1156 #define MDCR_EL2_PMU_ENABLE_BITS \
1157 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1158 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1161 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1162 * the current EL, security state, and register configuration.
1164 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1167 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1168 bool enabled
, prohibited
= false, filtered
;
1169 bool secure
= arm_is_secure(env
);
1170 int el
= arm_current_el(env
);
1171 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1172 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1174 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1178 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1179 (counter
< hpmn
|| counter
== 31)) {
1180 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1182 e
= mdcr_el2
& MDCR_HPME
;
1184 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1186 /* Is event counting prohibited? */
1187 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1188 prohibited
= mdcr_el2
& MDCR_HPMD
;
1191 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1194 if (counter
== 31) {
1196 * The cycle counter defaults to running. PMCR.DP says "disable
1197 * the cycle counter when event counting is prohibited".
1198 * Some MDCR bits disable the cycle counter specifically.
1200 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1201 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1203 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1206 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1211 if (counter
== 31) {
1212 filter
= env
->cp15
.pmccfiltr_el0
;
1214 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1217 p
= filter
& PMXEVTYPER_P
;
1218 u
= filter
& PMXEVTYPER_U
;
1219 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1220 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1221 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1222 m
= arm_el_is_aa64(env
, 1) &&
1223 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1226 filtered
= secure
? u
: u
!= nsu
;
1227 } else if (el
== 1) {
1228 filtered
= secure
? p
: p
!= nsk
;
1229 } else if (el
== 2) {
1235 if (counter
!= 31) {
1237 * If not checking PMCCNTR, ensure the counter is setup to an event we
1240 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1241 if (!event_supported(event
)) {
1246 return enabled
&& !prohibited
&& !filtered
;
1249 static void pmu_update_irq(CPUARMState
*env
)
1251 ARMCPU
*cpu
= env_archcpu(env
);
1252 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1253 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1256 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1259 * Return true if the clock divider is enabled and the cycle counter
1260 * is supposed to tick only once every 64 clock cycles. This is
1261 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1262 * (64-bit) cycle counter PMCR.D has no effect.
1264 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1267 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1269 /* Return true if the specified event counter is configured to be 64 bit */
1271 /* This isn't intended to be used with the cycle counter */
1272 assert(counter
< 31);
1274 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1278 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1280 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1281 * current security state, so we don't use arm_mdcr_el2_eff() here.
1283 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1284 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1286 if (hpmn
!= 0 && counter
>= hpmn
) {
1290 return env
->cp15
.c9_pmcr
& PMCRLP
;
1294 * Ensure c15_ccnt is the guest-visible count so that operations such as
1295 * enabling/disabling the counter or filtering, modifying the count itself,
1296 * etc. can be done logically. This is essentially a no-op if the counter is
1297 * not enabled at the time of the call.
1299 static void pmccntr_op_start(CPUARMState
*env
)
1301 uint64_t cycles
= cycles_get_count(env
);
1303 if (pmu_counter_enabled(env
, 31)) {
1304 uint64_t eff_cycles
= cycles
;
1305 if (pmccntr_clockdiv_enabled(env
)) {
1309 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1311 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1312 1ull << 63 : 1ull << 31;
1313 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1314 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1315 pmu_update_irq(env
);
1318 env
->cp15
.c15_ccnt
= new_pmccntr
;
1320 env
->cp15
.c15_ccnt_delta
= cycles
;
1324 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1325 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1328 static void pmccntr_op_finish(CPUARMState
*env
)
1330 if (pmu_counter_enabled(env
, 31)) {
1331 #ifndef CONFIG_USER_ONLY
1332 /* Calculate when the counter will next overflow */
1333 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1334 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1335 remaining_cycles
= (uint32_t)remaining_cycles
;
1337 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1339 if (overflow_in
> 0) {
1340 int64_t overflow_at
;
1342 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1343 overflow_in
, &overflow_at
)) {
1344 ARMCPU
*cpu
= env_archcpu(env
);
1345 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1350 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1351 if (pmccntr_clockdiv_enabled(env
)) {
1354 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1358 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1361 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1363 if (event_supported(event
)) {
1364 uint16_t event_idx
= supported_event_map
[event
];
1365 count
= pm_events
[event_idx
].get_count(env
);
1368 if (pmu_counter_enabled(env
, counter
)) {
1369 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1370 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1371 1ULL << 63 : 1ULL << 31;
1373 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1374 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1375 pmu_update_irq(env
);
1377 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1379 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1382 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1384 if (pmu_counter_enabled(env
, counter
)) {
1385 #ifndef CONFIG_USER_ONLY
1386 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1387 uint16_t event_idx
= supported_event_map
[event
];
1388 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1389 int64_t overflow_in
;
1391 if (!pmevcntr_is_64_bit(env
, counter
)) {
1392 delta
= (uint32_t)delta
;
1394 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1396 if (overflow_in
> 0) {
1397 int64_t overflow_at
;
1399 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1400 overflow_in
, &overflow_at
)) {
1401 ARMCPU
*cpu
= env_archcpu(env
);
1402 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1407 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1408 env
->cp15
.c14_pmevcntr
[counter
];
1412 void pmu_op_start(CPUARMState
*env
)
1415 pmccntr_op_start(env
);
1416 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1417 pmevcntr_op_start(env
, i
);
1421 void pmu_op_finish(CPUARMState
*env
)
1424 pmccntr_op_finish(env
);
1425 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1426 pmevcntr_op_finish(env
, i
);
1430 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1432 pmu_op_start(&cpu
->env
);
1435 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1437 pmu_op_finish(&cpu
->env
);
1440 void arm_pmu_timer_cb(void *opaque
)
1442 ARMCPU
*cpu
= opaque
;
1445 * Update all the counter values based on the current underlying counts,
1446 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1447 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1448 * counter may expire.
1450 pmu_op_start(&cpu
->env
);
1451 pmu_op_finish(&cpu
->env
);
1454 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1459 if (value
& PMCRC
) {
1460 /* The counter has been reset */
1461 env
->cp15
.c15_ccnt
= 0;
1464 if (value
& PMCRP
) {
1466 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1467 env
->cp15
.c14_pmevcntr
[i
] = 0;
1471 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1472 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1477 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1481 uint64_t overflow_mask
, new_pmswinc
;
1483 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1484 /* Increment a counter's count iff: */
1485 if ((value
& (1 << i
)) && /* counter's bit is set */
1486 /* counter is enabled and not filtered */
1487 pmu_counter_enabled(env
, i
) &&
1488 /* counter is SW_INCR */
1489 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1490 pmevcntr_op_start(env
, i
);
1493 * Detect if this write causes an overflow since we can't predict
1494 * PMSWINC overflows like we can for other events
1496 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1498 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1499 1ULL << 63 : 1ULL << 31;
1501 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1502 env
->cp15
.c9_pmovsr
|= (1 << i
);
1503 pmu_update_irq(env
);
1506 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1508 pmevcntr_op_finish(env
, i
);
1513 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1516 pmccntr_op_start(env
);
1517 ret
= env
->cp15
.c15_ccnt
;
1518 pmccntr_op_finish(env
);
1522 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1526 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1527 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1528 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1531 env
->cp15
.c9_pmselr
= value
& 0x1f;
1534 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1537 pmccntr_op_start(env
);
1538 env
->cp15
.c15_ccnt
= value
;
1539 pmccntr_op_finish(env
);
1542 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1545 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1547 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1550 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1553 pmccntr_op_start(env
);
1554 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1555 pmccntr_op_finish(env
);
1558 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1561 pmccntr_op_start(env
);
1562 /* M is not accessible from AArch32 */
1563 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1564 (value
& PMCCFILTR
);
1565 pmccntr_op_finish(env
);
1568 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1570 /* M is not visible in AArch32 */
1571 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1574 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1578 value
&= pmu_counter_mask(env
);
1579 env
->cp15
.c9_pmcnten
|= value
;
1583 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1587 value
&= pmu_counter_mask(env
);
1588 env
->cp15
.c9_pmcnten
&= ~value
;
1592 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1595 value
&= pmu_counter_mask(env
);
1596 env
->cp15
.c9_pmovsr
&= ~value
;
1597 pmu_update_irq(env
);
1600 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1603 value
&= pmu_counter_mask(env
);
1604 env
->cp15
.c9_pmovsr
|= value
;
1605 pmu_update_irq(env
);
1608 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1609 uint64_t value
, const uint8_t counter
)
1611 if (counter
== 31) {
1612 pmccfiltr_write(env
, ri
, value
);
1613 } else if (counter
< pmu_num_counters(env
)) {
1614 pmevcntr_op_start(env
, counter
);
1617 * If this counter's event type is changing, store the current
1618 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1619 * pmevcntr_op_finish has the correct baseline when it converts back to
1622 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1623 PMXEVTYPER_EVTCOUNT
;
1624 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1625 if (old_event
!= new_event
) {
1627 if (event_supported(new_event
)) {
1628 uint16_t event_idx
= supported_event_map
[new_event
];
1629 count
= pm_events
[event_idx
].get_count(env
);
1631 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1634 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1635 pmevcntr_op_finish(env
, counter
);
1638 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1639 * PMSELR value is equal to or greater than the number of implemented
1640 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1644 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1645 const uint8_t counter
)
1647 if (counter
== 31) {
1648 return env
->cp15
.pmccfiltr_el0
;
1649 } else if (counter
< pmu_num_counters(env
)) {
1650 return env
->cp15
.c14_pmevtyper
[counter
];
1653 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1654 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1660 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1663 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1664 pmevtyper_write(env
, ri
, value
, counter
);
1667 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1670 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1671 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1674 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1675 * pmu_op_finish calls when loading saved state for a migration. Because
1676 * we're potentially updating the type of event here, the value written to
1677 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1678 * different counter type. Therefore, we need to set this value to the
1679 * current count for the counter type we're writing so that pmu_op_finish
1680 * has the correct count for its calculation.
1682 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1683 if (event_supported(event
)) {
1684 uint16_t event_idx
= supported_event_map
[event
];
1685 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1686 pm_events
[event_idx
].get_count(env
);
1690 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1692 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1693 return pmevtyper_read(env
, ri
, counter
);
1696 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1699 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1702 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1704 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1707 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1708 uint64_t value
, uint8_t counter
)
1710 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1711 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1712 value
&= MAKE_64BIT_MASK(0, 32);
1714 if (counter
< pmu_num_counters(env
)) {
1715 pmevcntr_op_start(env
, counter
);
1716 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1717 pmevcntr_op_finish(env
, counter
);
1720 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1721 * are CONSTRAINED UNPREDICTABLE.
1725 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 if (counter
< pmu_num_counters(env
)) {
1730 pmevcntr_op_start(env
, counter
);
1731 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1732 pmevcntr_op_finish(env
, counter
);
1733 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1734 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1735 ret
&= MAKE_64BIT_MASK(0, 32);
1740 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1741 * are CONSTRAINED UNPREDICTABLE.
1747 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1750 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1751 pmevcntr_write(env
, ri
, value
, counter
);
1754 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1756 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1757 return pmevcntr_read(env
, ri
, counter
);
1760 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1763 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1764 assert(counter
< pmu_num_counters(env
));
1765 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1766 pmevcntr_write(env
, ri
, value
, counter
);
1769 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1771 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1772 assert(counter
< pmu_num_counters(env
));
1773 return env
->cp15
.c14_pmevcntr
[counter
];
1776 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1779 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1782 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1784 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1787 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1790 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1791 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1793 env
->cp15
.c9_pmuserenr
= value
& 1;
1797 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1800 /* We have no event counters so only the C bit can be changed */
1801 value
&= pmu_counter_mask(env
);
1802 env
->cp15
.c9_pminten
|= value
;
1803 pmu_update_irq(env
);
1806 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1809 value
&= pmu_counter_mask(env
);
1810 env
->cp15
.c9_pminten
&= ~value
;
1811 pmu_update_irq(env
);
1814 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1818 * Note that even though the AArch64 view of this register has bits
1819 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1820 * architectural requirements for bits which are RES0 only in some
1821 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1822 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1824 raw_write(env
, ri
, value
& ~0x1FULL
);
1827 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1829 /* Begin with base v8.0 state. */
1830 uint64_t valid_mask
= 0x3fff;
1831 ARMCPU
*cpu
= env_archcpu(env
);
1835 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1836 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1837 * Instead, choose the format based on the mode of EL3.
1839 if (arm_el_is_aa64(env
, 3)) {
1840 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1841 valid_mask
&= ~SCR_NET
; /* RES0 */
1843 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1844 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1845 value
|= SCR_RW
; /* RAO/WI */
1847 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1848 valid_mask
|= SCR_TERR
;
1850 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1851 valid_mask
|= SCR_TLOR
;
1853 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1854 valid_mask
|= SCR_API
| SCR_APK
;
1856 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1857 valid_mask
|= SCR_EEL2
;
1859 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1860 valid_mask
|= SCR_ATA
;
1862 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1863 valid_mask
|= SCR_ENSCXT
;
1865 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1866 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1868 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1869 valid_mask
|= SCR_ENTP2
;
1871 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1872 valid_mask
|= SCR_HXEN
;
1874 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1875 valid_mask
|= SCR_FGTEN
;
1878 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1879 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1880 valid_mask
|= SCR_TERR
;
1884 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1885 valid_mask
&= ~SCR_HCE
;
1888 * On ARMv7, SMD (or SCD as it is called in v7) is only
1889 * supported if EL2 exists. The bit is UNK/SBZP when
1890 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1891 * when EL2 is unavailable.
1892 * On ARMv8, this bit is always available.
1894 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1895 !arm_feature(env
, ARM_FEATURE_V8
)) {
1896 valid_mask
&= ~SCR_SMD
;
1900 /* Clear all-context RES0 bits. */
1901 value
&= valid_mask
;
1902 changed
= env
->cp15
.scr_el3
^ value
;
1903 env
->cp15
.scr_el3
= value
;
1906 * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
1907 * we must invalidate all TLBs below EL3.
1909 if (changed
& SCR_NS
) {
1910 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1911 ARMMMUIdxBit_E20_0
|
1912 ARMMMUIdxBit_E10_1
|
1913 ARMMMUIdxBit_E20_2
|
1914 ARMMMUIdxBit_E10_1_PAN
|
1915 ARMMMUIdxBit_E20_2_PAN
|
1920 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1923 * scr_write will set the RES1 bits on an AArch64-only CPU.
1924 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1926 scr_write(env
, ri
, 0);
1929 static CPAccessResult
access_tid4(CPUARMState
*env
,
1930 const ARMCPRegInfo
*ri
,
1933 if (arm_current_el(env
) == 1 &&
1934 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1935 return CP_ACCESS_TRAP_EL2
;
1938 return CP_ACCESS_OK
;
1941 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1943 ARMCPU
*cpu
= env_archcpu(env
);
1946 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1949 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1950 ri
->secure
& ARM_CP_SECSTATE_S
);
1952 return cpu
->ccsidr
[index
];
1955 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1958 raw_write(env
, ri
, value
& 0xf);
1961 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1963 CPUState
*cs
= env_cpu(env
);
1964 bool el1
= arm_current_el(env
) == 1;
1965 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1968 if (hcr_el2
& HCR_IMO
) {
1969 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1973 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1978 if (hcr_el2
& HCR_FMO
) {
1979 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1983 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1988 if (hcr_el2
& HCR_AMO
) {
1989 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1997 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2000 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2001 return CP_ACCESS_TRAP_EL2
;
2004 return CP_ACCESS_OK
;
2007 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2010 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2011 return access_aa64_tid1(env
, ri
, isread
);
2014 return CP_ACCESS_OK
;
2017 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2018 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2019 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2020 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2022 * Performance monitors are implementation defined in v7,
2023 * but with an ARM recommended set of registers, which we
2026 * Performance registers fall into three categories:
2027 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2028 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2029 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2030 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2031 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2033 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2034 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2035 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2036 .writefn
= pmcntenset_write
,
2037 .accessfn
= pmreg_access
,
2038 .raw_writefn
= raw_write
},
2039 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2040 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2041 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2042 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2043 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2044 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2046 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2047 .accessfn
= pmreg_access
,
2048 .writefn
= pmcntenclr_write
,
2049 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2050 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2051 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2052 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2053 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2054 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2055 .writefn
= pmcntenclr_write
},
2056 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2057 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2058 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2059 .accessfn
= pmreg_access
,
2060 .writefn
= pmovsr_write
,
2061 .raw_writefn
= raw_write
},
2062 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2063 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2064 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2065 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2066 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2067 .writefn
= pmovsr_write
,
2068 .raw_writefn
= raw_write
},
2069 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2070 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2071 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2072 .writefn
= pmswinc_write
},
2073 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2074 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2075 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2076 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2077 .writefn
= pmswinc_write
},
2078 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2079 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2080 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2081 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2082 .raw_writefn
= raw_write
},
2083 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2084 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2085 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2086 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2087 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2088 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2089 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2090 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2091 .accessfn
= pmreg_access_ccntr
},
2092 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2093 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2094 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2096 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2097 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2098 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2099 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2100 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2101 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2102 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2104 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2105 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2106 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2107 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2109 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2111 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2112 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2113 .accessfn
= pmreg_access
,
2114 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2115 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2116 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2117 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2118 .accessfn
= pmreg_access
,
2119 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2120 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2121 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2122 .accessfn
= pmreg_access_xevcntr
,
2123 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2124 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2125 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2126 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2127 .accessfn
= pmreg_access_xevcntr
,
2128 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2129 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2130 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2131 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2133 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2134 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2135 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2136 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2137 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2139 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2140 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2141 .access
= PL1_RW
, .accessfn
= access_tpm
,
2142 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2143 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2145 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2146 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2147 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2148 .access
= PL1_RW
, .accessfn
= access_tpm
,
2150 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2151 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2152 .resetvalue
= 0x0 },
2153 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2154 .access
= PL1_RW
, .accessfn
= access_tpm
,
2155 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2156 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2157 .writefn
= pmintenclr_write
, },
2158 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2159 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2160 .access
= PL1_RW
, .accessfn
= access_tpm
,
2161 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2162 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2163 .writefn
= pmintenclr_write
},
2164 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2165 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2167 .accessfn
= access_tid4
,
2168 .fgt
= FGT_CCSIDR_EL1
,
2169 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2170 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2171 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2173 .accessfn
= access_tid4
,
2174 .fgt
= FGT_CSSELR_EL1
,
2175 .writefn
= csselr_write
, .resetvalue
= 0,
2176 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2177 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2179 * Auxiliary ID register: this actually has an IMPDEF value but for now
2180 * just RAZ for all cores:
2182 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2183 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2184 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2185 .accessfn
= access_aa64_tid1
,
2186 .fgt
= FGT_AIDR_EL1
,
2189 * Auxiliary fault status registers: these also are IMPDEF, and we
2190 * choose to RAZ/WI for all cores.
2192 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2193 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2194 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2195 .fgt
= FGT_AFSR0_EL1
,
2196 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2197 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2198 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2199 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2200 .fgt
= FGT_AFSR1_EL1
,
2201 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2203 * MAIR can just read-as-written because we don't implement caches
2204 * and so don't need to care about memory attributes.
2206 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2207 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2208 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2209 .fgt
= FGT_MAIR_EL1
,
2210 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2212 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2213 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2214 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2217 * For non-long-descriptor page tables these are PRRR and NMRR;
2218 * regardless they still act as reads-as-written for QEMU.
2221 * MAIR0/1 are defined separately from their 64-bit counterpart which
2222 * allows them to assign the correct fieldoffset based on the endianness
2223 * handled in the field definitions.
2225 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2226 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2227 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2228 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2229 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2230 .resetfn
= arm_cp_reset_ignore
},
2231 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2232 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2233 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2234 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2235 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2236 .resetfn
= arm_cp_reset_ignore
},
2237 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2238 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2240 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2241 /* 32 bit ITLB invalidates */
2242 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2243 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2244 .writefn
= tlbiall_write
},
2245 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2246 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2247 .writefn
= tlbimva_write
},
2248 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2249 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2250 .writefn
= tlbiasid_write
},
2251 /* 32 bit DTLB invalidates */
2252 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2253 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2254 .writefn
= tlbiall_write
},
2255 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2256 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2257 .writefn
= tlbimva_write
},
2258 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2259 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2260 .writefn
= tlbiasid_write
},
2261 /* 32 bit TLB invalidates */
2262 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2263 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2264 .writefn
= tlbiall_write
},
2265 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2266 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2267 .writefn
= tlbimva_write
},
2268 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2269 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2270 .writefn
= tlbiasid_write
},
2271 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2272 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2273 .writefn
= tlbimvaa_write
},
2276 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2277 /* 32 bit TLB invalidates, Inner Shareable */
2278 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2279 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2280 .writefn
= tlbiall_is_write
},
2281 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2282 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2283 .writefn
= tlbimva_is_write
},
2284 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2285 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2286 .writefn
= tlbiasid_is_write
},
2287 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2288 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2289 .writefn
= tlbimvaa_is_write
},
2292 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2293 /* PMOVSSET is not implemented in v7 before v7ve */
2294 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2295 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2296 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2297 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2298 .writefn
= pmovsset_write
,
2299 .raw_writefn
= raw_write
},
2300 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2301 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2302 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2303 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2305 .writefn
= pmovsset_write
,
2306 .raw_writefn
= raw_write
},
2309 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2316 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2320 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2321 * at all, so we don't need to check whether we're v8A.
2323 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2324 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2325 return CP_ACCESS_TRAP_EL2
;
2327 return CP_ACCESS_OK
;
2330 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2333 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2334 return CP_ACCESS_TRAP
;
2336 return teecr_access(env
, ri
, isread
);
2339 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2340 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2341 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2343 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2344 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2345 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2346 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2349 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2350 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2351 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2353 .fgt
= FGT_TPIDR_EL0
,
2354 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2355 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2357 .fgt
= FGT_TPIDR_EL0
,
2358 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2359 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2360 .resetfn
= arm_cp_reset_ignore
},
2361 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2362 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2363 .access
= PL0_R
| PL1_W
,
2364 .fgt
= FGT_TPIDRRO_EL0
,
2365 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2367 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2368 .access
= PL0_R
| PL1_W
,
2369 .fgt
= FGT_TPIDRRO_EL0
,
2370 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2371 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2372 .resetfn
= arm_cp_reset_ignore
},
2373 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2374 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2376 .fgt
= FGT_TPIDR_EL1
,
2377 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2378 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2380 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2381 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2385 #ifndef CONFIG_USER_ONLY
2387 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2391 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2392 * Writable only at the highest implemented exception level.
2394 int el
= arm_current_el(env
);
2400 hcr
= arm_hcr_el2_eff(env
);
2401 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2402 cntkctl
= env
->cp15
.cnthctl_el2
;
2404 cntkctl
= env
->cp15
.c14_cntkctl
;
2406 if (!extract32(cntkctl
, 0, 2)) {
2407 return CP_ACCESS_TRAP
;
2411 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2412 arm_is_secure_below_el3(env
)) {
2413 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2414 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2422 if (!isread
&& el
< arm_highest_el(env
)) {
2423 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2426 return CP_ACCESS_OK
;
2429 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2432 unsigned int cur_el
= arm_current_el(env
);
2433 bool has_el2
= arm_is_el2_enabled(env
);
2434 uint64_t hcr
= arm_hcr_el2_eff(env
);
2438 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2439 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2440 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2441 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2444 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2445 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2446 return CP_ACCESS_TRAP
;
2449 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2450 if (hcr
& HCR_E2H
) {
2451 if (timeridx
== GTIMER_PHYS
&&
2452 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2453 return CP_ACCESS_TRAP_EL2
;
2456 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2457 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2458 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2459 return CP_ACCESS_TRAP_EL2
;
2465 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2466 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2468 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2469 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2470 return CP_ACCESS_TRAP_EL2
;
2474 return CP_ACCESS_OK
;
2477 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2480 unsigned int cur_el
= arm_current_el(env
);
2481 bool has_el2
= arm_is_el2_enabled(env
);
2482 uint64_t hcr
= arm_hcr_el2_eff(env
);
2486 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2487 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2488 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2489 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2493 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2494 * EL0 if EL0[PV]TEN is zero.
2496 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2497 return CP_ACCESS_TRAP
;
2502 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2503 if (hcr
& HCR_E2H
) {
2504 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2505 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2506 return CP_ACCESS_TRAP_EL2
;
2509 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2510 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2511 return CP_ACCESS_TRAP_EL2
;
2517 return CP_ACCESS_OK
;
2520 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2521 const ARMCPRegInfo
*ri
,
2524 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2527 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2528 const ARMCPRegInfo
*ri
,
2531 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2534 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2537 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2540 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2543 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2546 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2547 const ARMCPRegInfo
*ri
,
2551 * The AArch64 register view of the secure physical timer is
2552 * always accessible from EL3, and configurably accessible from
2555 switch (arm_current_el(env
)) {
2557 if (!arm_is_secure(env
)) {
2558 return CP_ACCESS_TRAP
;
2560 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2561 return CP_ACCESS_TRAP_EL3
;
2563 return CP_ACCESS_OK
;
2566 return CP_ACCESS_TRAP
;
2568 return CP_ACCESS_OK
;
2570 g_assert_not_reached();
2574 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2576 ARMCPU
*cpu
= env_archcpu(env
);
2578 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2581 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2583 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2587 * Timer enabled: calculate and set current ISTATUS, irq, and
2588 * reset timer to when ISTATUS next has to change
2590 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2591 cpu
->env
.cp15
.cntvoff_el2
: 0;
2592 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2593 /* Note that this must be unsigned 64 bit arithmetic: */
2594 int istatus
= count
- offset
>= gt
->cval
;
2598 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2600 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2601 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2604 /* Next transition is when count rolls back over to zero */
2605 nexttick
= UINT64_MAX
;
2607 /* Next transition is when we hit cval */
2608 nexttick
= gt
->cval
+ offset
;
2611 * Note that the desired next expiry time might be beyond the
2612 * signed-64-bit range of a QEMUTimer -- in this case we just
2613 * set the timer for as far in the future as possible. When the
2614 * timer expires we will reset the timer for any remaining period.
2616 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2617 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2619 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2621 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2623 /* Timer disabled: ISTATUS and timer output always clear */
2625 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2626 timer_del(cpu
->gt_timer
[timeridx
]);
2627 trace_arm_gt_recalc_disabled(timeridx
);
2631 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2634 ARMCPU
*cpu
= env_archcpu(env
);
2636 timer_del(cpu
->gt_timer
[timeridx
]);
2639 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2641 return gt_get_countervalue(env
);
2644 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2648 switch (arm_current_el(env
)) {
2650 hcr
= arm_hcr_el2_eff(env
);
2651 if (hcr
& HCR_E2H
) {
2656 hcr
= arm_hcr_el2_eff(env
);
2657 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2663 return env
->cp15
.cntvoff_el2
;
2666 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2668 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2671 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2675 trace_arm_gt_cval_write(timeridx
, value
);
2676 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2677 gt_recalc_timer(env_archcpu(env
), timeridx
);
2680 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2683 uint64_t offset
= 0;
2687 case GTIMER_HYPVIRT
:
2688 offset
= gt_virt_cnt_offset(env
);
2692 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2693 (gt_get_countervalue(env
) - offset
));
2696 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2700 uint64_t offset
= 0;
2704 case GTIMER_HYPVIRT
:
2705 offset
= gt_virt_cnt_offset(env
);
2709 trace_arm_gt_tval_write(timeridx
, value
);
2710 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2711 sextract64(value
, 0, 32);
2712 gt_recalc_timer(env_archcpu(env
), timeridx
);
2715 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2719 ARMCPU
*cpu
= env_archcpu(env
);
2720 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2722 trace_arm_gt_ctl_write(timeridx
, value
);
2723 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2724 if ((oldval
^ value
) & 1) {
2725 /* Enable toggled */
2726 gt_recalc_timer(cpu
, timeridx
);
2727 } else if ((oldval
^ value
) & 2) {
2729 * IMASK toggled: don't need to recalculate,
2730 * just set the interrupt line based on ISTATUS
2732 int irqstate
= (oldval
& 4) && !(value
& 2);
2734 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2735 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2739 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2741 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2744 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2747 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2750 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2752 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2755 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2758 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2761 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2764 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2767 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2769 switch (arm_mmu_idx(env
)) {
2770 case ARMMMUIdx_E20_0
:
2771 case ARMMMUIdx_E20_2
:
2772 case ARMMMUIdx_E20_2_PAN
:
2779 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2781 switch (arm_mmu_idx(env
)) {
2782 case ARMMMUIdx_E20_0
:
2783 case ARMMMUIdx_E20_2
:
2784 case ARMMMUIdx_E20_2_PAN
:
2785 return GTIMER_HYPVIRT
;
2791 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2792 const ARMCPRegInfo
*ri
)
2794 int timeridx
= gt_phys_redir_timeridx(env
);
2795 return env
->cp15
.c14_timer
[timeridx
].cval
;
2798 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2801 int timeridx
= gt_phys_redir_timeridx(env
);
2802 gt_cval_write(env
, ri
, timeridx
, value
);
2805 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2806 const ARMCPRegInfo
*ri
)
2808 int timeridx
= gt_phys_redir_timeridx(env
);
2809 return gt_tval_read(env
, ri
, timeridx
);
2812 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2815 int timeridx
= gt_phys_redir_timeridx(env
);
2816 gt_tval_write(env
, ri
, timeridx
, value
);
2819 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2820 const ARMCPRegInfo
*ri
)
2822 int timeridx
= gt_phys_redir_timeridx(env
);
2823 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2826 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2829 int timeridx
= gt_phys_redir_timeridx(env
);
2830 gt_ctl_write(env
, ri
, timeridx
, value
);
2833 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2835 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2838 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2841 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2844 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2846 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2849 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2852 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2855 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2858 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2861 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2864 ARMCPU
*cpu
= env_archcpu(env
);
2866 trace_arm_gt_cntvoff_write(value
);
2867 raw_write(env
, ri
, value
);
2868 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2871 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2872 const ARMCPRegInfo
*ri
)
2874 int timeridx
= gt_virt_redir_timeridx(env
);
2875 return env
->cp15
.c14_timer
[timeridx
].cval
;
2878 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2881 int timeridx
= gt_virt_redir_timeridx(env
);
2882 gt_cval_write(env
, ri
, timeridx
, value
);
2885 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2886 const ARMCPRegInfo
*ri
)
2888 int timeridx
= gt_virt_redir_timeridx(env
);
2889 return gt_tval_read(env
, ri
, timeridx
);
2892 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2895 int timeridx
= gt_virt_redir_timeridx(env
);
2896 gt_tval_write(env
, ri
, timeridx
, value
);
2899 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2900 const ARMCPRegInfo
*ri
)
2902 int timeridx
= gt_virt_redir_timeridx(env
);
2903 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2906 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2909 int timeridx
= gt_virt_redir_timeridx(env
);
2910 gt_ctl_write(env
, ri
, timeridx
, value
);
2913 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2915 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2918 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2921 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2924 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2926 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2929 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2932 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2935 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2938 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2941 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2943 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2946 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2949 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2952 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2954 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2957 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2960 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2963 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2966 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2969 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2971 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2974 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2977 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2980 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2982 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2985 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2988 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2991 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2994 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2997 void arm_gt_ptimer_cb(void *opaque
)
2999 ARMCPU
*cpu
= opaque
;
3001 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3004 void arm_gt_vtimer_cb(void *opaque
)
3006 ARMCPU
*cpu
= opaque
;
3008 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3011 void arm_gt_htimer_cb(void *opaque
)
3013 ARMCPU
*cpu
= opaque
;
3015 gt_recalc_timer(cpu
, GTIMER_HYP
);
3018 void arm_gt_stimer_cb(void *opaque
)
3020 ARMCPU
*cpu
= opaque
;
3022 gt_recalc_timer(cpu
, GTIMER_SEC
);
3025 void arm_gt_hvtimer_cb(void *opaque
)
3027 ARMCPU
*cpu
= opaque
;
3029 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3032 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3034 ARMCPU
*cpu
= env_archcpu(env
);
3036 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3039 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3041 * Note that CNTFRQ is purely reads-as-written for the benefit
3042 * of software; writing it doesn't actually change the timer frequency.
3043 * Our reset value matches the fixed frequency we implement the timer at.
3045 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3046 .type
= ARM_CP_ALIAS
,
3047 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3048 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3050 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3051 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3052 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3053 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3054 .resetfn
= arm_gt_cntfrq_reset
,
3056 /* overall control: mostly access permissions */
3057 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3058 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3060 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3063 /* per-timer control */
3064 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3065 .secure
= ARM_CP_SECSTATE_NS
,
3066 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3067 .accessfn
= gt_ptimer_access
,
3068 .fieldoffset
= offsetoflow32(CPUARMState
,
3069 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3070 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3071 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3073 { .name
= "CNTP_CTL_S",
3074 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3075 .secure
= ARM_CP_SECSTATE_S
,
3076 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3077 .accessfn
= gt_ptimer_access
,
3078 .fieldoffset
= offsetoflow32(CPUARMState
,
3079 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3080 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3082 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3083 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3084 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3085 .accessfn
= gt_ptimer_access
,
3086 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3088 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3089 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3091 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3092 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3093 .accessfn
= gt_vtimer_access
,
3094 .fieldoffset
= offsetoflow32(CPUARMState
,
3095 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3096 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3097 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3099 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3100 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3101 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3102 .accessfn
= gt_vtimer_access
,
3103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3105 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3106 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3108 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3109 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3110 .secure
= ARM_CP_SECSTATE_NS
,
3111 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3112 .accessfn
= gt_ptimer_access
,
3113 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3115 { .name
= "CNTP_TVAL_S",
3116 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3117 .secure
= ARM_CP_SECSTATE_S
,
3118 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3119 .accessfn
= gt_ptimer_access
,
3120 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3122 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3123 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3124 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3125 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3126 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3128 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3129 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3130 .accessfn
= gt_vtimer_access
,
3131 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3133 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3134 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3135 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3136 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3137 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3139 /* The counter itself */
3140 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3141 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3142 .accessfn
= gt_pct_access
,
3143 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3145 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3146 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3147 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3148 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3150 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3151 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3152 .accessfn
= gt_vct_access
,
3153 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3155 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3156 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3157 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3158 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3160 /* Comparison value, indicating when the timer goes off */
3161 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3162 .secure
= ARM_CP_SECSTATE_NS
,
3164 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3165 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3166 .accessfn
= gt_ptimer_access
,
3167 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3168 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3170 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3171 .secure
= ARM_CP_SECSTATE_S
,
3173 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3174 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3175 .accessfn
= gt_ptimer_access
,
3176 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3178 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3179 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3182 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3183 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3184 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3185 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3187 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3189 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3190 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3191 .accessfn
= gt_vtimer_access
,
3192 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3193 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3195 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3196 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3199 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3200 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3201 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3202 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3205 * Secure timer -- this is actually restricted to only EL3
3206 * and configurably Secure-EL1 via the accessfn.
3208 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3209 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3210 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3211 .accessfn
= gt_stimer_access
,
3212 .readfn
= gt_sec_tval_read
,
3213 .writefn
= gt_sec_tval_write
,
3214 .resetfn
= gt_sec_timer_reset
,
3216 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3217 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3218 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3219 .accessfn
= gt_stimer_access
,
3220 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3222 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3224 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3225 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3226 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3227 .accessfn
= gt_stimer_access
,
3228 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3229 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3233 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3236 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3237 return CP_ACCESS_TRAP
;
3239 return CP_ACCESS_OK
;
3245 * In user-mode most of the generic timer registers are inaccessible
3246 * however modern kernels (4.12+) allow access to cntvct_el0
3249 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3251 ARMCPU
*cpu
= env_archcpu(env
);
3254 * Currently we have no support for QEMUTimer in linux-user so we
3255 * can't call gt_get_countervalue(env), instead we directly
3256 * call the lower level functions.
3258 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3261 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3262 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3263 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3264 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3265 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3266 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3268 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3269 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3270 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3271 .readfn
= gt_virt_cnt_read
,
3277 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3279 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3280 raw_write(env
, ri
, value
);
3281 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3282 raw_write(env
, ri
, value
& 0xfffff6ff);
3284 raw_write(env
, ri
, value
& 0xfffff1ff);
3288 #ifndef CONFIG_USER_ONLY
3289 /* get_phys_addr() isn't present for user-mode-only targets */
3291 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3296 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3297 * Secure EL1 (which can only happen if EL3 is AArch64).
3298 * They are simply UNDEF if executed from NS EL1.
3299 * They function normally from EL2 or EL3.
3301 if (arm_current_el(env
) == 1) {
3302 if (arm_is_secure_below_el3(env
)) {
3303 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3304 return CP_ACCESS_TRAP_EL2
;
3306 return CP_ACCESS_TRAP_EL3
;
3308 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3311 return CP_ACCESS_OK
;
3315 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3316 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3321 bool format64
= false;
3322 ARMMMUFaultInfo fi
= {};
3323 GetPhysAddrResult res
= {};
3325 ret
= get_phys_addr_with_secure(env
, value
, access_type
, mmu_idx
,
3326 is_secure
, &res
, &fi
);
3329 * ATS operations only do S1 or S1+S2 translations, so we never
3330 * have to deal with the ARMCacheAttrs format for S2 only.
3332 assert(!res
.cacheattrs
.is_s2_format
);
3336 * Some kinds of translation fault must cause exceptions rather
3337 * than being reported in the PAR.
3339 int current_el
= arm_current_el(env
);
3341 uint32_t syn
, fsr
, fsc
;
3342 bool take_exc
= false;
3344 if (fi
.s1ptw
&& current_el
== 1
3345 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3347 * Synchronous stage 2 fault on an access made as part of the
3348 * translation table walk for AT S1E0* or AT S1E1* insn
3349 * executed from NS EL1. If this is a synchronous external abort
3350 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3351 * to EL3. Otherwise the fault is taken as an exception to EL2,
3352 * and HPFAR_EL2 holds the faulting IPA.
3354 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3355 (env
->cp15
.scr_el3
& SCR_EA
)) {
3358 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3359 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3360 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3365 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3367 * Synchronous external aborts during a translation table walk
3368 * are taken as Data Abort exceptions.
3371 if (current_el
== 3) {
3377 target_el
= exception_target_el(env
);
3383 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3384 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3385 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3386 fsr
= arm_fi_to_lfsc(&fi
);
3387 fsc
= extract32(fsr
, 0, 6);
3389 fsr
= arm_fi_to_sfsc(&fi
);
3393 * Report exception with ESR indicating a fault due to a
3394 * translation table walk for a cache maintenance instruction.
3396 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3397 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3398 env
->exception
.vaddress
= value
;
3399 env
->exception
.fsr
= fsr
;
3400 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3406 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3409 * * TTBCR.EAE determines whether the result is returned using the
3410 * 32-bit or the 64-bit PAR format
3411 * * Instructions executed in Hyp mode always use the 64bit format
3413 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3414 * * The Non-secure TTBCR.EAE bit is set to 1
3415 * * The implementation includes EL2, and the value of HCR.VM is 1
3417 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3419 * ATS1Hx always uses the 64bit format.
3421 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3423 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3424 if (mmu_idx
== ARMMMUIdx_E10_0
||
3425 mmu_idx
== ARMMMUIdx_E10_1
||
3426 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3427 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3429 format64
|= arm_current_el(env
) == 2;
3435 /* Create a 64-bit PAR */
3436 par64
= (1 << 11); /* LPAE bit always set */
3438 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3439 if (!res
.f
.attrs
.secure
) {
3440 par64
|= (1 << 9); /* NS */
3442 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3443 par64
|= res
.cacheattrs
.shareability
<< 7; /* SH */
3445 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3448 par64
|= (fsr
& 0x3f) << 1; /* FS */
3450 par64
|= (1 << 9); /* S */
3453 par64
|= (1 << 8); /* PTW */
3458 * fsr is a DFSR/IFSR value for the short descriptor
3459 * translation table format (with WnR always clear).
3460 * Convert it to a 32-bit PAR.
3463 /* We do not set any attribute bits in the PAR */
3464 if (res
.f
.lg_page_size
== 24
3465 && arm_feature(env
, ARM_FEATURE_V7
)) {
3466 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3468 par64
= res
.f
.phys_addr
& 0xfffff000;
3470 if (!res
.f
.attrs
.secure
) {
3471 par64
|= (1 << 9); /* NS */
3474 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3476 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3477 ((fsr
& 0xf) << 1) | 1;
3482 #endif /* CONFIG_TCG */
3484 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3487 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3490 int el
= arm_current_el(env
);
3491 bool secure
= arm_is_secure_below_el3(env
);
3493 switch (ri
->opc2
& 6) {
3495 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3498 mmu_idx
= ARMMMUIdx_E3
;
3502 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3505 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3506 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3508 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3512 g_assert_not_reached();
3516 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3519 mmu_idx
= ARMMMUIdx_E10_0
;
3523 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3524 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3527 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3530 g_assert_not_reached();
3534 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3535 mmu_idx
= ARMMMUIdx_E10_1
;
3539 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3540 mmu_idx
= ARMMMUIdx_E10_0
;
3544 g_assert_not_reached();
3547 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, secure
);
3549 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3551 /* Handled by hardware accelerator. */
3552 g_assert_not_reached();
3553 #endif /* CONFIG_TCG */
3556 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3560 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3563 /* There is no SecureEL2 for AArch32. */
3564 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
, false);
3566 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3568 /* Handled by hardware accelerator. */
3569 g_assert_not_reached();
3570 #endif /* CONFIG_TCG */
3573 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3576 if (arm_current_el(env
) == 3 &&
3577 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3578 return CP_ACCESS_TRAP
;
3580 return CP_ACCESS_OK
;
3583 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3587 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3589 int secure
= arm_is_secure_below_el3(env
);
3590 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3591 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3593 switch (ri
->opc2
& 6) {
3596 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3597 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3598 mmu_idx
= regime_e20
?
3599 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3601 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3604 case 4: /* AT S1E2R, AT S1E2W */
3605 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3607 case 6: /* AT S1E3R, AT S1E3W */
3608 mmu_idx
= ARMMMUIdx_E3
;
3612 g_assert_not_reached();
3615 case 2: /* AT S1E0R, AT S1E0W */
3616 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3618 case 4: /* AT S12E1R, AT S12E1W */
3619 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3621 case 6: /* AT S12E0R, AT S12E0W */
3622 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3625 g_assert_not_reached();
3628 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3631 /* Handled by hardware accelerator. */
3632 g_assert_not_reached();
3633 #endif /* CONFIG_TCG */
3637 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3638 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3639 .access
= PL1_RW
, .resetvalue
= 0,
3640 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3641 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3642 .writefn
= par_write
},
3643 #ifndef CONFIG_USER_ONLY
3644 /* This underdecoding is safe because the reginfo is NO_RAW. */
3645 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3646 .access
= PL1_W
, .accessfn
= ats_access
,
3647 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3651 /* Return basic MPU access permission bits. */
3652 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3659 for (i
= 0; i
< 16; i
+= 2) {
3660 ret
|= (val
>> i
) & mask
;
3666 /* Pad basic MPU access permission bits to extended format. */
3667 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3674 for (i
= 0; i
< 16; i
+= 2) {
3675 ret
|= (val
& mask
) << i
;
3681 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3684 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3687 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3689 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3692 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3695 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3698 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3700 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3703 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3705 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3711 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3715 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3718 ARMCPU
*cpu
= env_archcpu(env
);
3719 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3725 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3726 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3730 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3733 ARMCPU
*cpu
= env_archcpu(env
);
3734 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3736 if (value
>= nrgs
) {
3737 qemu_log_mask(LOG_GUEST_ERROR
,
3738 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3739 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3743 raw_write(env
, ri
, value
);
3746 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3749 ARMCPU
*cpu
= env_archcpu(env
);
3751 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3752 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3755 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3757 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3760 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3763 ARMCPU
*cpu
= env_archcpu(env
);
3765 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3766 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3769 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3771 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3774 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3777 ARMCPU
*cpu
= env_archcpu(env
);
3780 * Ignore writes that would select not implemented region.
3781 * This is architecturally UNPREDICTABLE.
3783 if (value
>= cpu
->pmsav7_dregion
) {
3787 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3790 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3793 ARMCPU
*cpu
= env_archcpu(env
);
3795 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3796 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3799 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3801 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3804 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3807 ARMCPU
*cpu
= env_archcpu(env
);
3809 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3810 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3813 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3815 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3818 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3823 ARMCPU
*cpu
= env_archcpu(env
);
3825 /* Ignore writes to unimplemented regions */
3826 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3827 value
&= MAKE_64BIT_MASK(0, rmax
);
3829 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3831 /* Register alias is only valid for first 32 indexes */
3832 for (n
= 0; n
< rmax
; ++n
) {
3833 bit
= extract32(value
, n
, 1);
3834 env
->pmsav8
.hprlar
[n
] = deposit32(
3835 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3839 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3842 uint32_t result
= 0x0;
3843 ARMCPU
*cpu
= env_archcpu(env
);
3845 /* Register alias is only valid for first 32 indexes */
3846 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3847 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3848 result
|= (0x1 << n
);
3854 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3857 ARMCPU
*cpu
= env_archcpu(env
);
3860 * Ignore writes that would select not implemented region.
3861 * This is architecturally UNPREDICTABLE.
3863 if (value
>= cpu
->pmsav8r_hdregion
) {
3867 env
->pmsav8
.hprselr
= value
;
3870 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3873 ARMCPU
*cpu
= env_archcpu(env
);
3874 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3875 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3877 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3880 if (index
>= cpu
->pmsav8r_hdregion
) {
3883 if (ri
->opc2
& 0x1) {
3884 env
->pmsav8
.hprlar
[index
] = value
;
3886 env
->pmsav8
.hprbar
[index
] = value
;
3889 if (index
>= cpu
->pmsav7_dregion
) {
3892 if (ri
->opc2
& 0x1) {
3893 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
3895 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
3900 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3902 ARMCPU
*cpu
= env_archcpu(env
);
3903 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3904 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3907 if (index
>= cpu
->pmsav8r_hdregion
) {
3910 if (ri
->opc2
& 0x1) {
3911 return env
->pmsav8
.hprlar
[index
];
3913 return env
->pmsav8
.hprbar
[index
];
3916 if (index
>= cpu
->pmsav7_dregion
) {
3919 if (ri
->opc2
& 0x1) {
3920 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
3922 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
3927 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
3929 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
3930 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3931 .accessfn
= access_tvm_trvm
,
3932 .readfn
= prbar_read
, .writefn
= prbar_write
},
3934 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
3935 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3936 .accessfn
= access_tvm_trvm
,
3937 .readfn
= prlar_read
, .writefn
= prlar_write
},
3938 { .name
= "PRSELR", .resetvalue
= 0,
3939 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
3940 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3941 .writefn
= prselr_write
,
3942 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
3943 { .name
= "HPRBAR", .resetvalue
= 0,
3944 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
3945 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3946 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
3948 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
3949 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3950 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
3951 { .name
= "HPRSELR", .resetvalue
= 0,
3952 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
3954 .writefn
= hprselr_write
,
3955 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
3957 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
3958 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3959 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
3962 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3964 * Reset for all these registers is handled in arm_cpu_reset(),
3965 * because the PMSAv7 is also used by M-profile CPUs, which do
3966 * not register cpregs but still need the state to be reset.
3968 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3969 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3970 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3971 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3972 .resetfn
= arm_cp_reset_ignore
},
3973 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3974 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3975 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3976 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3977 .resetfn
= arm_cp_reset_ignore
},
3978 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3979 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3980 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3981 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3982 .resetfn
= arm_cp_reset_ignore
},
3983 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3985 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3986 .writefn
= pmsav7_rgnr_write
,
3987 .resetfn
= arm_cp_reset_ignore
},
3990 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3991 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3992 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3993 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3994 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3995 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3996 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3997 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3998 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3999 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4001 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4003 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4005 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4007 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4009 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4010 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4012 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4013 /* Protection region base and size registers */
4014 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4015 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4016 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4017 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4018 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4019 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4020 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4021 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4022 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4023 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4024 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4025 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4026 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4027 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4028 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4029 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4030 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4031 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4032 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4033 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4034 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4035 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4036 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4037 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4040 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4043 ARMCPU
*cpu
= env_archcpu(env
);
4045 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4046 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4048 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4049 * using Long-descriptor translation table format
4051 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4052 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4054 * In an implementation that includes the Security Extensions
4055 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4056 * Short-descriptor translation table format.
4058 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4064 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4066 * With LPAE the TTBCR could result in a change of ASID
4067 * via the TTBCR.A1 bit, so do a TLB flush.
4069 tlb_flush(CPU(cpu
));
4071 raw_write(env
, ri
, value
);
4074 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4077 ARMCPU
*cpu
= env_archcpu(env
);
4079 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4080 tlb_flush(CPU(cpu
));
4081 raw_write(env
, ri
, value
);
4084 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4087 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4088 if (cpreg_field_is_64bit(ri
) &&
4089 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4090 ARMCPU
*cpu
= env_archcpu(env
);
4091 tlb_flush(CPU(cpu
));
4093 raw_write(env
, ri
, value
);
4096 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4100 * If we are running with E2&0 regime, then an ASID is active.
4101 * Flush if that might be changing. Note we're not checking
4102 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4103 * holds the active ASID, only checking the field that might.
4105 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4106 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4107 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4108 ARMMMUIdxBit_E20_2_PAN
|
4110 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4112 raw_write(env
, ri
, value
);
4115 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4118 ARMCPU
*cpu
= env_archcpu(env
);
4119 CPUState
*cs
= CPU(cpu
);
4122 * A change in VMID to the stage2 page table (Stage2) invalidates
4123 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4125 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4126 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4128 raw_write(env
, ri
, value
);
4131 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4132 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4133 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4134 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4135 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4136 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4137 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4138 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4139 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4140 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4141 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4142 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4143 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4144 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4145 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4146 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4148 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4152 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4153 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4154 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4155 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4157 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4158 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4159 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4160 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4161 .fgt
= FGT_TTBR0_EL1
,
4162 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4163 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4164 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4165 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4166 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4167 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4168 .fgt
= FGT_TTBR1_EL1
,
4169 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4170 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4171 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4172 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4173 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4174 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4176 .writefn
= vmsa_tcr_el12_write
,
4177 .raw_writefn
= raw_write
,
4179 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4180 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4181 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4182 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4183 .raw_writefn
= raw_write
,
4184 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4185 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4189 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4190 * qemu tlbs nor adjusting cached masks.
4192 static const ARMCPRegInfo ttbcr2_reginfo
= {
4193 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4194 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4195 .type
= ARM_CP_ALIAS
,
4196 .bank_fieldoffsets
= {
4197 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4198 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4202 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4205 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4206 /* The OS_TYPE bit in this register changes the reported CPUID! */
4207 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4208 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4211 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4214 env
->cp15
.c15_threadid
= value
& 0xffff;
4217 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4220 /* Wait-for-interrupt (deprecated) */
4221 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4224 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4228 * On OMAP there are registers indicating the max/min index of dcache lines
4229 * containing a dirty line; cache flush operations have to reset these.
4231 env
->cp15
.c15_i_max
= 0x000;
4232 env
->cp15
.c15_i_min
= 0xff0;
4235 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4236 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4237 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4238 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4240 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4241 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4242 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4244 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4245 .writefn
= omap_ticonfig_write
},
4246 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4248 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4249 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4250 .access
= PL1_RW
, .resetvalue
= 0xff0,
4251 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4252 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4254 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4255 .writefn
= omap_threadid_write
},
4256 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4257 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4258 .type
= ARM_CP_NO_RAW
,
4259 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4261 * TODO: Peripheral port remap register:
4262 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4263 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4266 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4267 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4268 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4269 .writefn
= omap_cachemaint_write
},
4270 { .name
= "C9", .cp
= 15, .crn
= 9,
4271 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4272 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4275 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4278 env
->cp15
.c15_cpar
= value
& 0x3fff;
4281 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4282 { .name
= "XSCALE_CPAR",
4283 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4284 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4285 .writefn
= xscale_cpar_write
, },
4286 { .name
= "XSCALE_AUXCR",
4287 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4288 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4291 * XScale specific cache-lockdown: since we have no cache we NOP these
4292 * and hope the guest does not really rely on cache behaviour.
4294 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4295 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4296 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4297 { .name
= "XSCALE_UNLOCK_ICACHE",
4298 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4299 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4300 { .name
= "XSCALE_DCACHE_LOCK",
4301 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4302 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4303 { .name
= "XSCALE_UNLOCK_DCACHE",
4304 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4305 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4308 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4310 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4311 * implementation of this implementation-defined space.
4312 * Ideally this should eventually disappear in favour of actually
4313 * implementing the correct behaviour for all cores.
4315 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4316 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4318 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4322 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4323 /* Cache status: RAZ because we have no cache so it's always clean */
4324 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4325 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4329 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4330 /* We never have a block transfer operation in progress */
4331 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4332 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4334 /* The cache ops themselves: these all NOP for QEMU */
4335 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4336 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4337 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4338 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4339 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4340 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4341 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4342 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4343 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4344 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4345 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4346 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4349 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4351 * The cache test-and-clean instructions always return (1 << 30)
4352 * to indicate that there are no dirty cache lines.
4354 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4355 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4356 .resetvalue
= (1 << 30) },
4357 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4358 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4359 .resetvalue
= (1 << 30) },
4362 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4363 /* Ignore ReadBuffer accesses */
4364 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4365 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4366 .access
= PL1_RW
, .resetvalue
= 0,
4367 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4370 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4372 unsigned int cur_el
= arm_current_el(env
);
4374 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4375 return env
->cp15
.vpidr_el2
;
4377 return raw_read(env
, ri
);
4380 static uint64_t mpidr_read_val(CPUARMState
*env
)
4382 ARMCPU
*cpu
= env_archcpu(env
);
4383 uint64_t mpidr
= cpu
->mp_affinity
;
4385 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4386 mpidr
|= (1U << 31);
4388 * Cores which are uniprocessor (non-coherent)
4389 * but still implement the MP extensions set
4390 * bit 30. (For instance, Cortex-R5).
4392 if (cpu
->mp_is_up
) {
4393 mpidr
|= (1u << 30);
4399 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4401 unsigned int cur_el
= arm_current_el(env
);
4403 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4404 return env
->cp15
.vmpidr_el2
;
4406 return mpidr_read_val(env
);
4409 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4411 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4412 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4413 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4414 .fgt
= FGT_AMAIR_EL1
,
4415 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4416 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4417 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4418 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4419 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4420 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4421 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4422 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4423 offsetof(CPUARMState
, cp15
.par_ns
)} },
4424 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4425 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4426 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4427 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4428 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4429 .writefn
= vmsa_ttbr_write
, },
4430 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4431 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4432 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4433 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4434 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4435 .writefn
= vmsa_ttbr_write
, },
4438 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4440 return vfp_get_fpcr(env
);
4443 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4446 vfp_set_fpcr(env
, value
);
4449 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4451 return vfp_get_fpsr(env
);
4454 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4457 vfp_set_fpsr(env
, value
);
4460 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4463 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4464 return CP_ACCESS_TRAP
;
4466 return CP_ACCESS_OK
;
4469 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4472 env
->daif
= value
& PSTATE_DAIF
;
4475 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4477 return env
->pstate
& PSTATE_PAN
;
4480 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4483 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4486 static const ARMCPRegInfo pan_reginfo
= {
4487 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4488 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4489 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4490 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4493 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4495 return env
->pstate
& PSTATE_UAO
;
4498 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4501 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4504 static const ARMCPRegInfo uao_reginfo
= {
4505 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4506 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4507 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4508 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4511 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4513 return env
->pstate
& PSTATE_DIT
;
4516 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4519 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4522 static const ARMCPRegInfo dit_reginfo
= {
4523 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4524 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4525 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4526 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4529 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4531 return env
->pstate
& PSTATE_SSBS
;
4534 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4537 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4540 static const ARMCPRegInfo ssbs_reginfo
= {
4541 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4542 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4543 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4544 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4547 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4548 const ARMCPRegInfo
*ri
,
4551 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4552 switch (arm_current_el(env
)) {
4554 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4555 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4556 return CP_ACCESS_TRAP
;
4560 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4561 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4562 return CP_ACCESS_TRAP_EL2
;
4566 return CP_ACCESS_OK
;
4569 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4571 /* Cache invalidate/clean to Point of Unification... */
4572 switch (arm_current_el(env
)) {
4574 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4575 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4576 return CP_ACCESS_TRAP
;
4580 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4581 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4582 return CP_ACCESS_TRAP_EL2
;
4586 return CP_ACCESS_OK
;
4589 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4592 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4595 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4598 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4602 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4603 * Page D4-1736 (DDI0487A.b)
4606 static int vae1_tlbmask(CPUARMState
*env
)
4608 uint64_t hcr
= arm_hcr_el2_eff(env
);
4611 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4612 mask
= ARMMMUIdxBit_E20_2
|
4613 ARMMMUIdxBit_E20_2_PAN
|
4616 mask
= ARMMMUIdxBit_E10_1
|
4617 ARMMMUIdxBit_E10_1_PAN
|
4623 /* Return 56 if TBI is enabled, 64 otherwise. */
4624 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4627 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4628 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4629 int select
= extract64(addr
, 55, 1);
4631 return (tbi
>> select
) & 1 ? 56 : 64;
4634 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4636 uint64_t hcr
= arm_hcr_el2_eff(env
);
4639 /* Only the regime of the mmu_idx below is significant. */
4640 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4641 mmu_idx
= ARMMMUIdx_E20_0
;
4643 mmu_idx
= ARMMMUIdx_E10_0
;
4646 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4649 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4652 CPUState
*cs
= env_cpu(env
);
4653 int mask
= vae1_tlbmask(env
);
4655 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4658 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4661 CPUState
*cs
= env_cpu(env
);
4662 int mask
= vae1_tlbmask(env
);
4664 if (tlb_force_broadcast(env
)) {
4665 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4667 tlb_flush_by_mmuidx(cs
, mask
);
4671 static int e2_tlbmask(CPUARMState
*env
)
4673 return (ARMMMUIdxBit_E20_0
|
4674 ARMMMUIdxBit_E20_2
|
4675 ARMMMUIdxBit_E20_2_PAN
|
4679 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4682 CPUState
*cs
= env_cpu(env
);
4683 int mask
= alle1_tlbmask(env
);
4685 tlb_flush_by_mmuidx(cs
, mask
);
4688 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4691 CPUState
*cs
= env_cpu(env
);
4692 int mask
= e2_tlbmask(env
);
4694 tlb_flush_by_mmuidx(cs
, mask
);
4697 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4700 ARMCPU
*cpu
= env_archcpu(env
);
4701 CPUState
*cs
= CPU(cpu
);
4703 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4706 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4709 CPUState
*cs
= env_cpu(env
);
4710 int mask
= alle1_tlbmask(env
);
4712 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4715 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4718 CPUState
*cs
= env_cpu(env
);
4719 int mask
= e2_tlbmask(env
);
4721 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4724 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4727 CPUState
*cs
= env_cpu(env
);
4729 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4732 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4736 * Invalidate by VA, EL2
4737 * Currently handles both VAE2 and VALE2, since we don't support
4738 * flush-last-level-only.
4740 CPUState
*cs
= env_cpu(env
);
4741 int mask
= e2_tlbmask(env
);
4742 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4744 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4747 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4751 * Invalidate by VA, EL3
4752 * Currently handles both VAE3 and VALE3, since we don't support
4753 * flush-last-level-only.
4755 ARMCPU
*cpu
= env_archcpu(env
);
4756 CPUState
*cs
= CPU(cpu
);
4757 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4759 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4762 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4765 CPUState
*cs
= env_cpu(env
);
4766 int mask
= vae1_tlbmask(env
);
4767 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4768 int bits
= vae1_tlbbits(env
, pageaddr
);
4770 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4773 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4777 * Invalidate by VA, EL1&0 (AArch64 version).
4778 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4779 * since we don't support flush-for-specific-ASID-only or
4780 * flush-last-level-only.
4782 CPUState
*cs
= env_cpu(env
);
4783 int mask
= vae1_tlbmask(env
);
4784 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4785 int bits
= vae1_tlbbits(env
, pageaddr
);
4787 if (tlb_force_broadcast(env
)) {
4788 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4790 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4794 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4797 CPUState
*cs
= env_cpu(env
);
4798 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4799 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E2
, pageaddr
);
4801 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4802 ARMMMUIdxBit_E2
, bits
);
4805 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4808 CPUState
*cs
= env_cpu(env
);
4809 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4810 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4812 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4813 ARMMMUIdxBit_E3
, bits
);
4816 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4819 * The MSB of value is the NS field, which only applies if SEL2
4820 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4823 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4824 && arm_is_secure_below_el3(env
)
4825 ? ARMMMUIdxBit_Stage2_S
4826 : ARMMMUIdxBit_Stage2
);
4829 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4832 CPUState
*cs
= env_cpu(env
);
4833 int mask
= ipas2e1_tlbmask(env
, value
);
4834 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4836 if (tlb_force_broadcast(env
)) {
4837 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4839 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4843 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4846 CPUState
*cs
= env_cpu(env
);
4847 int mask
= ipas2e1_tlbmask(env
, value
);
4848 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4850 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4853 #ifdef TARGET_AARCH64
4859 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
4862 * Note that the TLBI range TG field encoding differs from both
4863 * TG0 and TG1 encodings.
4877 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4880 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4881 /* Extract one bit to represent the va selector in use. */
4882 uint64_t select
= sextract64(value
, 36, 1);
4883 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4884 TLBIRange ret
= { };
4885 ARMGranuleSize gran
;
4887 page_size_granule
= extract64(value
, 46, 2);
4888 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
4890 /* The granule encoded in value must match the granule in use. */
4891 if (gran
!= param
.gran
) {
4892 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4897 page_shift
= arm_granule_bits(gran
);
4898 num
= extract64(value
, 39, 5);
4899 scale
= extract64(value
, 44, 2);
4900 exponent
= (5 * scale
) + 1;
4902 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4905 ret
.base
= sextract64(value
, 0, 37);
4907 ret
.base
= extract64(value
, 0, 37);
4911 * With DS=1, BaseADDR is always shifted 16 so that it is able
4912 * to address all 52 va bits. The input address is perforce
4913 * aligned on a 64k boundary regardless of translation granule.
4917 ret
.base
<<= page_shift
;
4922 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4923 int idxmap
, bool synced
)
4925 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4929 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4930 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4933 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4939 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4940 range
.length
, idxmap
, bits
);
4944 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4945 const ARMCPRegInfo
*ri
,
4949 * Invalidate by VA range, EL1&0.
4950 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4951 * since we don't support flush-for-specific-ASID-only or
4952 * flush-last-level-only.
4955 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4956 tlb_force_broadcast(env
));
4959 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4960 const ARMCPRegInfo
*ri
,
4964 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4965 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4966 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4967 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4968 * shareable specific flushes.
4971 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4974 static int vae2_tlbmask(CPUARMState
*env
)
4976 return ARMMMUIdxBit_E2
;
4979 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4980 const ARMCPRegInfo
*ri
,
4984 * Invalidate by VA range, EL2.
4985 * Currently handles all of RVAE2 and RVALE2,
4986 * since we don't support flush-for-specific-ASID-only or
4987 * flush-last-level-only.
4990 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4991 tlb_force_broadcast(env
));
4996 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4997 const ARMCPRegInfo
*ri
,
5001 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5002 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5003 * since we don't support flush-for-specific-ASID-only,
5004 * flush-last-level-only or inner/outer shareable specific flushes.
5007 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5011 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5012 const ARMCPRegInfo
*ri
,
5016 * Invalidate by VA range, EL3.
5017 * Currently handles all of RVAE3 and RVALE3,
5018 * since we don't support flush-for-specific-ASID-only or
5019 * flush-last-level-only.
5022 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5025 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5026 const ARMCPRegInfo
*ri
,
5030 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5031 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5032 * since we don't support flush-for-specific-ASID-only,
5033 * flush-last-level-only or inner/outer specific flushes.
5036 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5039 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5042 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5043 tlb_force_broadcast(env
));
5046 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5047 const ARMCPRegInfo
*ri
,
5050 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5054 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5057 int cur_el
= arm_current_el(env
);
5060 uint64_t hcr
= arm_hcr_el2_eff(env
);
5063 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5064 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5065 return CP_ACCESS_TRAP_EL2
;
5068 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5069 return CP_ACCESS_TRAP
;
5071 if (hcr
& HCR_TDZ
) {
5072 return CP_ACCESS_TRAP_EL2
;
5075 } else if (hcr
& HCR_TDZ
) {
5076 return CP_ACCESS_TRAP_EL2
;
5079 return CP_ACCESS_OK
;
5082 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5084 ARMCPU
*cpu
= env_archcpu(env
);
5085 int dzp_bit
= 1 << 4;
5087 /* DZP indicates whether DC ZVA access is allowed */
5088 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5091 return cpu
->dcz_blocksize
| dzp_bit
;
5094 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5097 if (!(env
->pstate
& PSTATE_SP
)) {
5099 * Access to SP_EL0 is undefined if it's being used as
5100 * the stack pointer.
5102 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5104 return CP_ACCESS_OK
;
5107 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5109 return env
->pstate
& PSTATE_SP
;
5112 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5114 update_spsel(env
, val
);
5117 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5120 ARMCPU
*cpu
= env_archcpu(env
);
5122 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5123 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5127 /* ??? Lots of these bits are not implemented. */
5129 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5130 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5131 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5133 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5134 SCTLR_ATA0
| SCTLR_ATA
);
5138 if (raw_read(env
, ri
) == value
) {
5140 * Skip the TLB flush if nothing actually changed; Linux likes
5141 * to do a lot of pointless SCTLR writes.
5146 raw_write(env
, ri
, value
);
5148 /* This may enable/disable the MMU, so do a TLB flush. */
5149 tlb_flush(CPU(cpu
));
5151 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5153 * Normally we would always end the TB on an SCTLR write; see the
5154 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5155 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5156 * of hflags from the translator, so do it here.
5158 arm_rebuild_hflags(env
);
5162 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5166 * Some MDCR_EL3 bits affect whether PMU counters are running:
5167 * if we are trying to change any of those then we must
5168 * bracket this update with PMU start/finish calls.
5170 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5175 env
->cp15
.mdcr_el3
= value
;
5181 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5184 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5185 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5188 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5192 * Some MDCR_EL2 bits affect whether PMU counters are running:
5193 * if we are trying to change any of those then we must
5194 * bracket this update with PMU start/finish calls.
5196 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5201 env
->cp15
.mdcr_el2
= value
;
5207 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5209 * Minimal set of EL0-visible registers. This will need to be expanded
5210 * significantly for system emulation of AArch64 CPUs.
5212 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5213 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5214 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5215 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5216 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5217 .type
= ARM_CP_NO_RAW
,
5218 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5219 .fieldoffset
= offsetof(CPUARMState
, daif
),
5220 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5221 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5222 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5223 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5224 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5225 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5226 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5227 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5228 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5229 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5230 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5231 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5232 .fgt
= FGT_DCZID_EL0
,
5233 .readfn
= aa64_dczid_read
},
5234 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5235 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5236 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5237 #ifndef CONFIG_USER_ONLY
5238 /* Avoid overhead of an access check that always passes in user-mode */
5239 .accessfn
= aa64_zva_access
,
5242 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5243 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5244 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5245 /* Cache ops: all NOPs since we don't emulate caches */
5246 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5247 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5248 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5249 .accessfn
= access_ticab
},
5250 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5251 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5252 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5253 .accessfn
= access_tocu
},
5254 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5255 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5256 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5257 .accessfn
= access_tocu
},
5258 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5259 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5260 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5261 .type
= ARM_CP_NOP
},
5262 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5263 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5264 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5265 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5266 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5267 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5268 .accessfn
= aa64_cacheop_poc_access
},
5269 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5270 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5271 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5272 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5273 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5274 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5275 .accessfn
= access_tocu
},
5276 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5277 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5278 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5279 .accessfn
= aa64_cacheop_poc_access
},
5280 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5281 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5282 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5283 /* TLBI operations */
5284 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5285 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5286 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5287 .writefn
= tlbi_aa64_vmalle1is_write
},
5288 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5289 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5290 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5291 .writefn
= tlbi_aa64_vae1is_write
},
5292 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5293 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5294 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5295 .writefn
= tlbi_aa64_vmalle1is_write
},
5296 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5297 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5298 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5299 .writefn
= tlbi_aa64_vae1is_write
},
5300 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5301 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5302 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5303 .writefn
= tlbi_aa64_vae1is_write
},
5304 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5305 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5306 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5307 .writefn
= tlbi_aa64_vae1is_write
},
5308 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5309 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5310 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5311 .writefn
= tlbi_aa64_vmalle1_write
},
5312 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5313 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5314 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5315 .writefn
= tlbi_aa64_vae1_write
},
5316 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5317 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5318 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5319 .writefn
= tlbi_aa64_vmalle1_write
},
5320 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5321 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5322 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5323 .writefn
= tlbi_aa64_vae1_write
},
5324 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5325 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5326 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5327 .writefn
= tlbi_aa64_vae1_write
},
5328 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5329 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5330 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5331 .writefn
= tlbi_aa64_vae1_write
},
5332 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5333 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5334 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5335 .writefn
= tlbi_aa64_ipas2e1is_write
},
5336 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5337 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5338 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5339 .writefn
= tlbi_aa64_ipas2e1is_write
},
5340 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5341 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5342 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5343 .writefn
= tlbi_aa64_alle1is_write
},
5344 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5345 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5346 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5347 .writefn
= tlbi_aa64_alle1is_write
},
5348 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5349 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5350 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5351 .writefn
= tlbi_aa64_ipas2e1_write
},
5352 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5353 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5354 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5355 .writefn
= tlbi_aa64_ipas2e1_write
},
5356 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5357 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5358 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5359 .writefn
= tlbi_aa64_alle1_write
},
5360 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5361 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5362 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5363 .writefn
= tlbi_aa64_alle1is_write
},
5364 #ifndef CONFIG_USER_ONLY
5365 /* 64 bit address translation operations */
5366 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5367 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5368 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5369 .writefn
= ats_write64
},
5370 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5371 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5372 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5373 .writefn
= ats_write64
},
5374 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5375 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5376 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5377 .writefn
= ats_write64
},
5378 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5379 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5380 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5381 .writefn
= ats_write64
},
5382 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5383 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5384 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5385 .writefn
= ats_write64
},
5386 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5387 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5388 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5389 .writefn
= ats_write64
},
5390 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5391 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5392 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5393 .writefn
= ats_write64
},
5394 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5395 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5396 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5397 .writefn
= ats_write64
},
5398 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5399 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5400 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5401 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5402 .writefn
= ats_write64
},
5403 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5404 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5405 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5406 .writefn
= ats_write64
},
5407 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5408 .type
= ARM_CP_ALIAS
,
5409 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5410 .access
= PL1_RW
, .resetvalue
= 0,
5412 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5413 .writefn
= par_write
},
5415 /* TLB invalidate last level of translation table walk */
5416 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5417 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5418 .writefn
= tlbimva_is_write
},
5419 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5420 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5421 .writefn
= tlbimvaa_is_write
},
5422 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5423 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5424 .writefn
= tlbimva_write
},
5425 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5426 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5427 .writefn
= tlbimvaa_write
},
5428 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5429 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5430 .writefn
= tlbimva_hyp_write
},
5431 { .name
= "TLBIMVALHIS",
5432 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5433 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5434 .writefn
= tlbimva_hyp_is_write
},
5435 { .name
= "TLBIIPAS2",
5436 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5437 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5438 .writefn
= tlbiipas2_hyp_write
},
5439 { .name
= "TLBIIPAS2IS",
5440 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5441 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5442 .writefn
= tlbiipas2is_hyp_write
},
5443 { .name
= "TLBIIPAS2L",
5444 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5445 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5446 .writefn
= tlbiipas2_hyp_write
},
5447 { .name
= "TLBIIPAS2LIS",
5448 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5449 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5450 .writefn
= tlbiipas2is_hyp_write
},
5451 /* 32 bit cache operations */
5452 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5453 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5454 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5455 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5456 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5457 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5458 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5459 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5460 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5461 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5462 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5463 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5464 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5465 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5466 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5467 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5468 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5469 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5470 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5471 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5472 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5473 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5474 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5475 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5476 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5477 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5478 /* MMU Domain access control / MPU write buffer control */
5479 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5480 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5481 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5482 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5483 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5484 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5485 .type
= ARM_CP_ALIAS
,
5486 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5488 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5489 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5490 .type
= ARM_CP_ALIAS
,
5491 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5493 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5495 * We rely on the access checks not allowing the guest to write to the
5496 * state field when SPSel indicates that it's being used as the stack
5499 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5500 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5501 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5502 .type
= ARM_CP_ALIAS
,
5503 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5504 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5505 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5506 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5507 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5508 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5509 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5510 .type
= ARM_CP_NO_RAW
,
5511 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5512 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5513 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5515 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5516 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5517 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5518 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5519 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5520 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5521 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5522 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5523 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5524 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5525 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5526 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5527 .type
= ARM_CP_ALIAS
,
5528 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5530 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5531 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5532 .type
= ARM_CP_ALIAS
,
5533 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5535 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5536 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5537 .type
= ARM_CP_ALIAS
,
5538 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5540 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5541 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5542 .type
= ARM_CP_ALIAS
,
5543 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5545 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5546 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5548 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5551 .writefn
= mdcr_el3_write
,
5552 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5553 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5554 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5555 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5556 .writefn
= sdcr_write
,
5557 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5560 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5562 ARMCPU
*cpu
= env_archcpu(env
);
5564 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5565 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5567 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5570 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5571 valid_mask
&= ~HCR_HCD
;
5572 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5574 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5575 * However, if we're using the SMC PSCI conduit then QEMU is
5576 * effectively acting like EL3 firmware and so the guest at
5577 * EL2 should retain the ability to prevent EL1 from being
5578 * able to make SMC calls into the ersatz firmware, so in
5579 * that case HCR.TSC should be read/write.
5581 valid_mask
&= ~HCR_TSC
;
5584 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5585 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5586 valid_mask
|= HCR_E2H
;
5588 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5589 valid_mask
|= HCR_TERR
| HCR_TEA
;
5591 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5592 valid_mask
|= HCR_TLOR
;
5594 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5595 valid_mask
|= HCR_API
| HCR_APK
;
5597 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5598 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5600 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5601 valid_mask
|= HCR_ENSCXT
;
5603 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5604 valid_mask
|= HCR_FWB
;
5608 if (cpu_isar_feature(any_evt
, cpu
)) {
5609 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5610 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5611 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5614 /* Clear RES0 bits. */
5615 value
&= valid_mask
;
5618 * These bits change the MMU setup:
5619 * HCR_VM enables stage 2 translation
5620 * HCR_PTW forbids certain page-table setups
5621 * HCR_DC disables stage1 and enables stage2 translation
5622 * HCR_DCT enables tagging on (disabled) stage1 translation
5623 * HCR_FWB changes the interpretation of stage2 descriptor bits
5625 if ((env
->cp15
.hcr_el2
^ value
) &
5626 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5627 tlb_flush(CPU(cpu
));
5629 env
->cp15
.hcr_el2
= value
;
5632 * Updates to VI and VF require us to update the status of
5633 * virtual interrupts, which are the logical OR of these bits
5634 * and the state of the input lines from the GIC. (This requires
5635 * that we have the iothread lock, which is done by marking the
5636 * reginfo structs as ARM_CP_IO.)
5637 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5638 * possible for it to be taken immediately, because VIRQ and
5639 * VFIQ are masked unless running at EL0 or EL1, and HCR
5640 * can only be written at EL2.
5642 g_assert(qemu_mutex_iothread_locked());
5643 arm_cpu_update_virq(cpu
);
5644 arm_cpu_update_vfiq(cpu
);
5645 arm_cpu_update_vserr(cpu
);
5648 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5650 do_hcr_write(env
, value
, 0);
5653 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5656 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5657 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5658 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5661 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5664 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5665 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5666 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5670 * Return the effective value of HCR_EL2, at the given security state.
5671 * Bits that are not included here:
5672 * RW (read from SCR_EL3.RW as needed)
5674 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, bool secure
)
5676 uint64_t ret
= env
->cp15
.hcr_el2
;
5678 if (!arm_is_el2_enabled_secstate(env
, secure
)) {
5680 * "This register has no effect if EL2 is not enabled in the
5681 * current Security state". This is ARMv8.4-SecEL2 speak for
5682 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5684 * Prior to that, the language was "In an implementation that
5685 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5686 * as if this field is 0 for all purposes other than a direct
5687 * read or write access of HCR_EL2". With lots of enumeration
5688 * on a per-field basis. In current QEMU, this is condition
5689 * is arm_is_secure_below_el3.
5691 * Since the v8.4 language applies to the entire register, and
5692 * appears to be backward compatible, use that.
5698 * For a cpu that supports both aarch64 and aarch32, we can set bits
5699 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5700 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5702 if (!arm_el_is_aa64(env
, 2)) {
5703 uint64_t aa32_valid
;
5706 * These bits are up-to-date as of ARMv8.6.
5707 * For HCR, it's easiest to list just the 2 bits that are invalid.
5708 * For HCR2, list those that are valid.
5710 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5711 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5712 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5716 if (ret
& HCR_TGE
) {
5717 /* These bits are up-to-date as of ARMv8.6. */
5718 if (ret
& HCR_E2H
) {
5719 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5720 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5721 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5722 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5723 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5724 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5726 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5728 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5729 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5730 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5737 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5739 return arm_hcr_el2_eff_secstate(env
, arm_is_secure_below_el3(env
));
5743 * Corresponds to ARM pseudocode function ELIsInHost().
5745 bool el_is_in_host(CPUARMState
*env
, int el
)
5750 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5751 * Perform the simplest bit tests first, and validate EL2 afterward.
5754 return false; /* EL1 or EL3 */
5758 * Note that hcr_write() checks isar_feature_aa64_vh(),
5759 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5761 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5762 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5766 /* TGE and/or E2H set: double check those bits are currently legal. */
5767 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5770 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5773 uint64_t valid_mask
= 0;
5775 /* No features adding bits to HCRX are implemented. */
5777 /* Clear RES0 bits. */
5778 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5781 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5784 if (arm_current_el(env
) < 3
5785 && arm_feature(env
, ARM_FEATURE_EL3
)
5786 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5787 return CP_ACCESS_TRAP_EL3
;
5789 return CP_ACCESS_OK
;
5792 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5793 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5794 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5795 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5796 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5799 /* Return the effective value of HCRX_EL2. */
5800 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5803 * The bits in this register behave as 0 for all purposes other than
5804 * direct reads of the register if:
5805 * - EL2 is not enabled in the current security state,
5806 * - SCR_EL3.HXEn is 0.
5808 if (!arm_is_el2_enabled(env
)
5809 || (arm_feature(env
, ARM_FEATURE_EL3
)
5810 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5813 return env
->cp15
.hcrx_el2
;
5816 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5820 * For A-profile AArch32 EL3, if NSACR.CP10
5821 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5823 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5824 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5825 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5826 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5828 env
->cp15
.cptr_el
[2] = value
;
5831 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5834 * For A-profile AArch32 EL3, if NSACR.CP10
5835 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5837 uint64_t value
= env
->cp15
.cptr_el
[2];
5839 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5840 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5841 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5846 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5847 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5849 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5850 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5851 .writefn
= hcr_write
},
5852 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5853 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5854 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5855 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5856 .writefn
= hcr_writelow
},
5857 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5858 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5859 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5860 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5861 .type
= ARM_CP_ALIAS
,
5862 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5864 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5865 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5866 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5867 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5868 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5869 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5870 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5871 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5872 .type
= ARM_CP_ALIAS
,
5873 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5875 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5876 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5877 .type
= ARM_CP_ALIAS
,
5878 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5880 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5881 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5882 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5883 .access
= PL2_RW
, .writefn
= vbar_write
,
5884 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5886 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5887 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5888 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5889 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5890 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5891 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5892 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5893 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5894 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5895 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5896 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5897 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5899 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5900 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5901 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5902 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5903 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5904 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5905 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5907 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5908 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5909 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5910 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5912 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5913 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5914 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5916 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5917 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5918 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5920 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5921 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5922 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5923 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5924 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5925 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5926 .type
= ARM_CP_ALIAS
,
5927 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5928 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
5929 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5930 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5932 /* no .writefn needed as this can't cause an ASID change */
5933 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5934 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5935 .cp
= 15, .opc1
= 6, .crm
= 2,
5936 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5937 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5938 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5939 .writefn
= vttbr_write
},
5940 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5941 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5942 .access
= PL2_RW
, .writefn
= vttbr_write
,
5943 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5944 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5945 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5946 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5947 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5948 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5949 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5950 .access
= PL2_RW
, .resetvalue
= 0,
5951 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5952 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5953 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5954 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5955 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5956 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5957 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5958 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5959 { .name
= "TLBIALLNSNH",
5960 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5961 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5962 .writefn
= tlbiall_nsnh_write
},
5963 { .name
= "TLBIALLNSNHIS",
5964 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5965 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5966 .writefn
= tlbiall_nsnh_is_write
},
5967 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5968 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5969 .writefn
= tlbiall_hyp_write
},
5970 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5971 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5972 .writefn
= tlbiall_hyp_is_write
},
5973 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5974 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5975 .writefn
= tlbimva_hyp_write
},
5976 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5977 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5978 .writefn
= tlbimva_hyp_is_write
},
5979 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5980 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5981 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5982 .writefn
= tlbi_aa64_alle2_write
},
5983 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5984 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5985 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5986 .writefn
= tlbi_aa64_vae2_write
},
5987 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5988 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5989 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5990 .writefn
= tlbi_aa64_vae2_write
},
5991 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5992 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5993 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5994 .writefn
= tlbi_aa64_alle2is_write
},
5995 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5996 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5997 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5998 .writefn
= tlbi_aa64_vae2is_write
},
5999 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6000 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6001 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6002 .writefn
= tlbi_aa64_vae2is_write
},
6003 #ifndef CONFIG_USER_ONLY
6005 * Unlike the other EL2-related AT operations, these must
6006 * UNDEF from EL3 if EL2 is not implemented, which is why we
6007 * define them here rather than with the rest of the AT ops.
6009 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6010 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6011 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6012 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6013 .writefn
= ats_write64
},
6014 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6015 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6016 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6017 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6018 .writefn
= ats_write64
},
6020 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6021 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6022 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6023 * to behave as if SCR.NS was 1.
6025 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6027 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6028 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6030 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6031 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6032 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6034 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6035 * reset values as IMPDEF. We choose to reset to 3 to comply with
6036 * both ARMv7 and ARMv8.
6038 .access
= PL2_RW
, .resetvalue
= 3,
6039 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6040 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6041 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6042 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6043 .writefn
= gt_cntvoff_write
,
6044 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6045 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6046 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6047 .writefn
= gt_cntvoff_write
,
6048 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6049 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6050 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6051 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6052 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6053 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6054 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6055 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6056 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6057 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6058 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6059 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6060 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6061 .resetfn
= gt_hyp_timer_reset
,
6062 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6063 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6065 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6067 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6069 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6071 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6072 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6073 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6074 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6075 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6076 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6078 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6079 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6080 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6082 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6085 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6086 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6087 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6088 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6090 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6091 .writefn
= hcr_writehigh
},
6094 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6097 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6098 return CP_ACCESS_OK
;
6100 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6103 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6104 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6105 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6106 .access
= PL2_RW
, .accessfn
= sel2_access
,
6107 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6108 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6109 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6110 .access
= PL2_RW
, .accessfn
= sel2_access
,
6111 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6114 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6118 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6119 * At Secure EL1 it traps to EL3 or EL2.
6121 if (arm_current_el(env
) == 3) {
6122 return CP_ACCESS_OK
;
6124 if (arm_is_secure_below_el3(env
)) {
6125 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6126 return CP_ACCESS_TRAP_EL2
;
6128 return CP_ACCESS_TRAP_EL3
;
6130 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6132 return CP_ACCESS_OK
;
6134 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6137 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6138 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6139 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6140 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6141 .resetfn
= scr_reset
, .writefn
= scr_write
},
6142 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6143 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6144 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6145 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6146 .writefn
= scr_write
},
6147 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6148 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6149 .access
= PL3_RW
, .resetvalue
= 0,
6150 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6152 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6153 .access
= PL3_RW
, .resetvalue
= 0,
6154 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6155 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6156 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6157 .writefn
= vbar_write
, .resetvalue
= 0,
6158 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6159 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6160 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6161 .access
= PL3_RW
, .resetvalue
= 0,
6162 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6163 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6164 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6166 /* no .writefn needed as this can't cause an ASID change */
6168 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6169 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6170 .type
= ARM_CP_ALIAS
,
6171 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6173 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6174 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6175 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6176 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6177 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6178 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6179 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6180 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6181 .type
= ARM_CP_ALIAS
,
6182 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6184 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6185 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6186 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6187 .access
= PL3_RW
, .writefn
= vbar_write
,
6188 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6190 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6191 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6192 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6193 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6194 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6195 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6196 .access
= PL3_RW
, .resetvalue
= 0,
6197 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6198 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6199 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6200 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6202 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6203 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6204 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6206 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6207 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6208 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6210 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6211 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6212 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6213 .writefn
= tlbi_aa64_alle3is_write
},
6214 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6215 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6216 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6217 .writefn
= tlbi_aa64_vae3is_write
},
6218 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6219 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6220 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6221 .writefn
= tlbi_aa64_vae3is_write
},
6222 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6223 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6224 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6225 .writefn
= tlbi_aa64_alle3_write
},
6226 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6227 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6228 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6229 .writefn
= tlbi_aa64_vae3_write
},
6230 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6231 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6232 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6233 .writefn
= tlbi_aa64_vae3_write
},
6236 #ifndef CONFIG_USER_ONLY
6237 /* Test if system register redirection is to occur in the current state. */
6238 static bool redirect_for_e2h(CPUARMState
*env
)
6240 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6243 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6247 if (redirect_for_e2h(env
)) {
6248 /* Switch to the saved EL2 version of the register. */
6250 readfn
= ri
->readfn
;
6252 readfn
= ri
->orig_readfn
;
6254 if (readfn
== NULL
) {
6257 return readfn(env
, ri
);
6260 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6265 if (redirect_for_e2h(env
)) {
6266 /* Switch to the saved EL2 version of the register. */
6268 writefn
= ri
->writefn
;
6270 writefn
= ri
->orig_writefn
;
6272 if (writefn
== NULL
) {
6273 writefn
= raw_write
;
6275 writefn(env
, ri
, value
);
6278 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6281 uint32_t src_key
, dst_key
, new_key
;
6282 const char *src_name
, *dst_name
, *new_name
;
6283 bool (*feature
)(const ARMISARegisters
*id
);
6286 #define K(op0, op1, crn, crm, op2) \
6287 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6289 static const struct E2HAlias aliases
[] = {
6290 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6291 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6292 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6293 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6294 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6295 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6296 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6297 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6298 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6299 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6300 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6301 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6302 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6303 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6304 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6305 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6306 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6307 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6308 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6309 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6310 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6311 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6312 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6313 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6314 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6315 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6316 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6317 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6318 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6319 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6320 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6321 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6324 * Note that redirection of ZCR is mentioned in the description
6325 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6326 * not in the summary table.
6328 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6329 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6330 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6331 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6333 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6334 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6336 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6337 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6338 isar_feature_aa64_scxtnum
},
6340 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6341 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6347 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6348 const struct E2HAlias
*a
= &aliases
[i
];
6349 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6352 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6356 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6357 (gpointer
)(uintptr_t)a
->src_key
);
6358 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6359 (gpointer
)(uintptr_t)a
->dst_key
);
6360 g_assert(src_reg
!= NULL
);
6361 g_assert(dst_reg
!= NULL
);
6363 /* Cross-compare names to detect typos in the keys. */
6364 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6365 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6367 /* None of the core system registers use opaque; we will. */
6368 g_assert(src_reg
->opaque
== NULL
);
6370 /* Create alias before redirection so we dup the right data. */
6371 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6373 new_reg
->name
= a
->new_name
;
6374 new_reg
->type
|= ARM_CP_ALIAS
;
6375 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6376 new_reg
->access
&= PL2_RW
| PL3_RW
;
6378 ok
= g_hash_table_insert(cpu
->cp_regs
,
6379 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6382 src_reg
->opaque
= dst_reg
;
6383 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6384 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6385 if (!src_reg
->raw_readfn
) {
6386 src_reg
->raw_readfn
= raw_read
;
6388 if (!src_reg
->raw_writefn
) {
6389 src_reg
->raw_writefn
= raw_write
;
6391 src_reg
->readfn
= el2_e2h_read
;
6392 src_reg
->writefn
= el2_e2h_write
;
6397 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6400 int cur_el
= arm_current_el(env
);
6403 uint64_t hcr
= arm_hcr_el2_eff(env
);
6406 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6407 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6408 return CP_ACCESS_TRAP_EL2
;
6411 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6412 return CP_ACCESS_TRAP
;
6414 if (hcr
& HCR_TID2
) {
6415 return CP_ACCESS_TRAP_EL2
;
6418 } else if (hcr
& HCR_TID2
) {
6419 return CP_ACCESS_TRAP_EL2
;
6423 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6424 return CP_ACCESS_TRAP_EL2
;
6427 return CP_ACCESS_OK
;
6431 * Check for traps to RAS registers, which are controlled
6432 * by HCR_EL2.TERR and SCR_EL3.TERR.
6434 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6437 int el
= arm_current_el(env
);
6439 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6440 return CP_ACCESS_TRAP_EL2
;
6442 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6443 return CP_ACCESS_TRAP_EL3
;
6445 return CP_ACCESS_OK
;
6448 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6450 int el
= arm_current_el(env
);
6452 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6453 return env
->cp15
.vdisr_el2
;
6455 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6456 return 0; /* RAZ/WI */
6458 return env
->cp15
.disr_el1
;
6461 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6463 int el
= arm_current_el(env
);
6465 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6466 env
->cp15
.vdisr_el2
= val
;
6469 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6470 return; /* RAZ/WI */
6472 env
->cp15
.disr_el1
= val
;
6476 * Minimal RAS implementation with no Error Records.
6477 * Which means that all of the Error Record registers:
6485 * ERXPFGCDN_EL1 (RASv1p1)
6486 * ERXPFGCTL_EL1 (RASv1p1)
6487 * ERXPFGF_EL1 (RASv1p1)
6491 * may generate UNDEFINED, which is the effect we get by not
6492 * listing them at all.
6494 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6495 * is higher priority than FGT-to-EL2 so we do not need to list them
6496 * in order to check for an FGT.
6498 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6499 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6500 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6501 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6502 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6503 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6504 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6505 .access
= PL1_R
, .accessfn
= access_terr
,
6506 .fgt
= FGT_ERRIDR_EL1
,
6507 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6508 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6509 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6510 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6511 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6512 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6513 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6517 * Return the exception level to which exceptions should be taken
6518 * via SVEAccessTrap. This excludes the check for whether the exception
6519 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6520 * be found by testing 0 < fp_exception_el < sve_exception_el.
6522 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6523 * pseudocode does *not* separate out the FP trap checks, but has them
6524 * all in one function.
6526 int sve_exception_el(CPUARMState
*env
, int el
)
6528 #ifndef CONFIG_USER_ONLY
6529 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6530 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6542 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6543 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6544 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6545 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6547 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6556 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6562 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6563 if (arm_feature(env
, ARM_FEATURE_EL3
)
6564 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6572 * Return the exception level to which exceptions should be taken for SME.
6573 * C.f. the ARM pseudocode function CheckSMEAccess.
6575 int sme_exception_el(CPUARMState
*env
, int el
)
6577 #ifndef CONFIG_USER_ONLY
6578 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6579 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6591 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6592 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6593 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6594 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6596 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6605 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6611 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6612 if (arm_feature(env
, ARM_FEATURE_EL3
)
6613 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6620 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
6621 static bool sme_fa64(CPUARMState
*env
, int el
)
6623 if (!cpu_isar_feature(aa64_sme_fa64
, env_archcpu(env
))) {
6627 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6628 if (!FIELD_EX64(env
->vfp
.smcr_el
[1], SMCR
, FA64
)) {
6632 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6633 if (!FIELD_EX64(env
->vfp
.smcr_el
[2], SMCR
, FA64
)) {
6637 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6638 if (!FIELD_EX64(env
->vfp
.smcr_el
[3], SMCR
, FA64
)) {
6647 * Given that SVE is enabled, return the vector length for EL.
6649 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6651 ARMCPU
*cpu
= env_archcpu(env
);
6652 uint64_t *cr
= env
->vfp
.zcr_el
;
6653 uint32_t map
= cpu
->sve_vq
.map
;
6654 uint32_t len
= ARM_MAX_VQ
- 1;
6657 cr
= env
->vfp
.smcr_el
;
6658 map
= cpu
->sme_vq
.map
;
6661 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6662 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6664 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6665 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6667 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6668 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6671 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6673 return 31 - clz32(map
);
6676 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6678 return ctz32(cpu
->sme_vq
.map
);
6681 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6683 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6686 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6689 int cur_el
= arm_current_el(env
);
6690 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6693 /* Bits other than [3:0] are RAZ/WI. */
6694 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6695 raw_write(env
, ri
, value
& 0xf);
6698 * Because we arrived here, we know both FP and SVE are enabled;
6699 * otherwise we would have trapped access to the ZCR_ELn register.
6701 new_len
= sve_vqm1_for_el(env
, cur_el
);
6702 if (new_len
< old_len
) {
6703 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6707 static const ARMCPRegInfo zcr_reginfo
[] = {
6708 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6709 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6710 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6711 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6712 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6713 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6714 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6715 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6716 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6717 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6718 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6719 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6720 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6721 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6722 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6725 #ifdef TARGET_AARCH64
6726 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6729 int el
= arm_current_el(env
);
6732 uint64_t sctlr
= arm_sctlr(env
, el
);
6733 if (!(sctlr
& SCTLR_EnTP2
)) {
6734 return CP_ACCESS_TRAP
;
6737 /* TODO: FEAT_FGT */
6739 && arm_feature(env
, ARM_FEATURE_EL3
)
6740 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6741 return CP_ACCESS_TRAP_EL3
;
6743 return CP_ACCESS_OK
;
6746 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6749 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6750 if (arm_current_el(env
) < 3
6751 && arm_feature(env
, ARM_FEATURE_EL3
)
6752 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6753 return CP_ACCESS_TRAP_EL3
;
6755 return CP_ACCESS_OK
;
6759 static void arm_reset_sve_state(CPUARMState
*env
)
6761 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
6762 /* Recall that FFR is stored as pregs[16]. */
6763 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
6764 vfp_set_fpcr(env
, 0x0800009f);
6767 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
6769 uint64_t change
= (env
->svcr
^ new) & mask
;
6774 env
->svcr
^= change
;
6776 if (change
& R_SVCR_SM_MASK
) {
6777 arm_reset_sve_state(env
);
6783 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
6784 * on enable: while disabled, the storage is inaccessible and the
6785 * value does not matter. We're not saving the storage in vmstate
6786 * when disabled either.
6788 if (change
& new & R_SVCR_ZA_MASK
) {
6789 memset(env
->zarray
, 0, sizeof(env
->zarray
));
6792 arm_rebuild_hflags(env
);
6795 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6798 aarch64_set_svcr(env
, value
, -1);
6801 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6804 int cur_el
= arm_current_el(env
);
6805 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6808 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6809 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6810 raw_write(env
, ri
, value
);
6813 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
6814 * when SVL is widened (old values kept, or zeros). Choose to keep the
6815 * current values for simplicity. But for QEMU internals, we must still
6816 * apply the narrower SVL to the Zregs and Pregs -- see the comment
6817 * above aarch64_sve_narrow_vq.
6819 new_len
= sve_vqm1_for_el(env
, cur_el
);
6820 if (new_len
< old_len
) {
6821 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6825 static const ARMCPRegInfo sme_reginfo
[] = {
6826 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
6827 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
6828 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
6829 .fgt
= FGT_NTPIDR2_EL0
,
6830 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
6831 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
6832 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
6833 .access
= PL0_RW
, .type
= ARM_CP_SME
,
6834 .fieldoffset
= offsetof(CPUARMState
, svcr
),
6835 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
6836 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
6837 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
6838 .access
= PL1_RW
, .type
= ARM_CP_SME
,
6839 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
6840 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6841 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
6842 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
6843 .access
= PL2_RW
, .type
= ARM_CP_SME
,
6844 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
6845 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6846 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
6847 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
6848 .access
= PL3_RW
, .type
= ARM_CP_SME
,
6849 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
6850 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6851 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
6852 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
6853 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
6855 * IMPLEMENTOR = 0 (software)
6856 * REVISION = 0 (implementation defined)
6857 * SMPS = 0 (no streaming execution priority in QEMU)
6858 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
6860 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
6862 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
6864 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
6865 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
6866 .access
= PL1_RW
, .accessfn
= access_esm
,
6867 .fgt
= FGT_NSMPRI_EL1
,
6868 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6869 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
6870 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
6871 .access
= PL2_RW
, .accessfn
= access_esm
,
6872 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6874 #endif /* TARGET_AARCH64 */
6876 static void define_pmu_regs(ARMCPU
*cpu
)
6879 * v7 performance monitor control register: same implementor
6880 * field as main ID register, and we implement four counters in
6881 * addition to the cycle count register.
6883 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6884 ARMCPRegInfo pmcr
= {
6885 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6887 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6888 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6889 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6890 .raw_writefn
= raw_write
,
6892 ARMCPRegInfo pmcr64
= {
6893 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6894 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6895 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6897 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6898 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6899 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6902 define_one_arm_cp_reg(cpu
, &pmcr
);
6903 define_one_arm_cp_reg(cpu
, &pmcr64
);
6904 for (i
= 0; i
< pmcrn
; i
++) {
6905 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6906 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6907 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6908 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6909 ARMCPRegInfo pmev_regs
[] = {
6910 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6911 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6912 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6913 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6914 .accessfn
= pmreg_access_xevcntr
},
6915 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6916 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6917 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6919 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6920 .raw_readfn
= pmevcntr_rawread
,
6921 .raw_writefn
= pmevcntr_rawwrite
},
6922 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6923 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6924 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6925 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6926 .accessfn
= pmreg_access
},
6927 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6928 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6929 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6931 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6932 .raw_writefn
= pmevtyper_rawwrite
},
6934 define_arm_cp_regs(cpu
, pmev_regs
);
6935 g_free(pmevcntr_name
);
6936 g_free(pmevcntr_el0_name
);
6937 g_free(pmevtyper_name
);
6938 g_free(pmevtyper_el0_name
);
6940 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
6941 ARMCPRegInfo v81_pmu_regs
[] = {
6942 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6943 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6944 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6945 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6946 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6947 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6948 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6949 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6951 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6953 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
6954 static const ARMCPRegInfo v84_pmmir
= {
6955 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6956 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6957 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6960 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6965 * We don't know until after realize whether there's a GICv3
6966 * attached, and that is what registers the gicv3 sysregs.
6967 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6970 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6972 ARMCPU
*cpu
= env_archcpu(env
);
6973 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6975 if (env
->gicv3state
) {
6981 #ifndef CONFIG_USER_ONLY
6982 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6984 ARMCPU
*cpu
= env_archcpu(env
);
6985 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6987 if (env
->gicv3state
) {
6995 * Shared logic between LORID and the rest of the LOR* registers.
6996 * Secure state exclusion has already been dealt with.
6998 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6999 const ARMCPRegInfo
*ri
, bool isread
)
7001 int el
= arm_current_el(env
);
7003 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7004 return CP_ACCESS_TRAP_EL2
;
7006 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7007 return CP_ACCESS_TRAP_EL3
;
7009 return CP_ACCESS_OK
;
7012 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7013 const ARMCPRegInfo
*ri
, bool isread
)
7015 if (arm_is_secure_below_el3(env
)) {
7016 /* Access denied in secure mode. */
7017 return CP_ACCESS_TRAP
;
7019 return access_lor_ns(env
, ri
, isread
);
7023 * A trivial implementation of ARMv8.1-LOR leaves all of these
7024 * registers fixed at 0, which indicates that there are zero
7025 * supported Limited Ordering regions.
7027 static const ARMCPRegInfo lor_reginfo
[] = {
7028 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7029 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7030 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7031 .fgt
= FGT_LORSA_EL1
,
7032 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7033 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7034 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7035 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7036 .fgt
= FGT_LOREA_EL1
,
7037 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7038 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7039 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7040 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7041 .fgt
= FGT_LORN_EL1
,
7042 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7043 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7044 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7045 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7046 .fgt
= FGT_LORC_EL1
,
7047 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7048 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7049 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7050 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7051 .fgt
= FGT_LORID_EL1
,
7052 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7055 #ifdef TARGET_AARCH64
7056 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7059 int el
= arm_current_el(env
);
7062 arm_is_el2_enabled(env
) &&
7063 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7064 return CP_ACCESS_TRAP_EL2
;
7067 arm_feature(env
, ARM_FEATURE_EL3
) &&
7068 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7069 return CP_ACCESS_TRAP_EL3
;
7071 return CP_ACCESS_OK
;
7074 static const ARMCPRegInfo pauth_reginfo
[] = {
7075 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7076 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7077 .access
= PL1_RW
, .accessfn
= access_pauth
,
7079 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7080 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7081 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7082 .access
= PL1_RW
, .accessfn
= access_pauth
,
7084 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7085 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7086 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7087 .access
= PL1_RW
, .accessfn
= access_pauth
,
7089 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7090 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7091 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7092 .access
= PL1_RW
, .accessfn
= access_pauth
,
7094 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7095 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7096 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7097 .access
= PL1_RW
, .accessfn
= access_pauth
,
7099 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7100 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7101 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7102 .access
= PL1_RW
, .accessfn
= access_pauth
,
7104 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7105 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7106 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7107 .access
= PL1_RW
, .accessfn
= access_pauth
,
7109 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7110 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7111 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7112 .access
= PL1_RW
, .accessfn
= access_pauth
,
7114 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7115 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7116 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7117 .access
= PL1_RW
, .accessfn
= access_pauth
,
7119 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7120 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7121 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7122 .access
= PL1_RW
, .accessfn
= access_pauth
,
7124 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7127 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7128 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7129 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7130 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7131 .writefn
= tlbi_aa64_rvae1is_write
},
7132 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7133 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7134 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7135 .writefn
= tlbi_aa64_rvae1is_write
},
7136 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7137 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7138 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7139 .writefn
= tlbi_aa64_rvae1is_write
},
7140 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7141 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7142 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7143 .writefn
= tlbi_aa64_rvae1is_write
},
7144 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7145 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7146 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7147 .writefn
= tlbi_aa64_rvae1is_write
},
7148 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7149 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7150 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7151 .writefn
= tlbi_aa64_rvae1is_write
},
7152 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7153 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7154 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7155 .writefn
= tlbi_aa64_rvae1is_write
},
7156 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7157 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7158 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7159 .writefn
= tlbi_aa64_rvae1is_write
},
7160 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7161 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7162 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7163 .writefn
= tlbi_aa64_rvae1_write
},
7164 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7165 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7166 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7167 .writefn
= tlbi_aa64_rvae1_write
},
7168 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7169 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7170 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7171 .writefn
= tlbi_aa64_rvae1_write
},
7172 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7173 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7174 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7175 .writefn
= tlbi_aa64_rvae1_write
},
7176 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7177 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7178 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7179 .writefn
= tlbi_aa64_ripas2e1is_write
},
7180 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7181 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7182 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7183 .writefn
= tlbi_aa64_ripas2e1is_write
},
7184 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7185 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7186 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7187 .writefn
= tlbi_aa64_rvae2is_write
},
7188 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7189 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7190 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7191 .writefn
= tlbi_aa64_rvae2is_write
},
7192 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7193 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7194 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7195 .writefn
= tlbi_aa64_ripas2e1_write
},
7196 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7197 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7198 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7199 .writefn
= tlbi_aa64_ripas2e1_write
},
7200 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7201 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7202 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7203 .writefn
= tlbi_aa64_rvae2is_write
},
7204 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7205 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7206 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7207 .writefn
= tlbi_aa64_rvae2is_write
},
7208 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7209 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7210 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7211 .writefn
= tlbi_aa64_rvae2_write
},
7212 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7213 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7214 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7215 .writefn
= tlbi_aa64_rvae2_write
},
7216 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7217 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7218 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7219 .writefn
= tlbi_aa64_rvae3is_write
},
7220 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7221 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7222 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7223 .writefn
= tlbi_aa64_rvae3is_write
},
7224 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7225 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7226 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7227 .writefn
= tlbi_aa64_rvae3is_write
},
7228 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7229 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7230 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7231 .writefn
= tlbi_aa64_rvae3is_write
},
7232 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7233 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7234 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7235 .writefn
= tlbi_aa64_rvae3_write
},
7236 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7237 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7238 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7239 .writefn
= tlbi_aa64_rvae3_write
},
7242 static const ARMCPRegInfo tlbios_reginfo
[] = {
7243 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7244 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7245 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7246 .writefn
= tlbi_aa64_vmalle1is_write
},
7247 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7248 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7249 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7250 .writefn
= tlbi_aa64_vae1is_write
},
7251 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7252 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7253 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7254 .writefn
= tlbi_aa64_vmalle1is_write
},
7255 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7256 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7257 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7258 .writefn
= tlbi_aa64_vae1is_write
},
7259 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7260 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7261 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7262 .writefn
= tlbi_aa64_vae1is_write
},
7263 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7264 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7265 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7266 .writefn
= tlbi_aa64_vae1is_write
},
7267 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7268 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7269 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7270 .writefn
= tlbi_aa64_alle2is_write
},
7271 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7272 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7273 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7274 .writefn
= tlbi_aa64_vae2is_write
},
7275 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7276 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7277 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7278 .writefn
= tlbi_aa64_alle1is_write
},
7279 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7280 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7281 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7282 .writefn
= tlbi_aa64_vae2is_write
},
7283 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7284 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7285 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7286 .writefn
= tlbi_aa64_alle1is_write
},
7287 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7288 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7289 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7290 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7291 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7292 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7293 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7294 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7295 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7296 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7297 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7298 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7299 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7300 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7301 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7302 .writefn
= tlbi_aa64_alle3is_write
},
7303 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7304 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7305 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7306 .writefn
= tlbi_aa64_vae3is_write
},
7307 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7308 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7309 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7310 .writefn
= tlbi_aa64_vae3is_write
},
7313 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7318 /* Success sets NZCV = 0000. */
7319 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7321 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7323 * ??? Failed, for unknown reasons in the crypto subsystem.
7324 * The best we can do is log the reason and return the
7325 * timed-out indication to the guest. There is no reason
7326 * we know to expect this failure to be transitory, so the
7327 * guest may well hang retrying the operation.
7329 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7330 ri
->name
, error_get_pretty(err
));
7333 env
->ZF
= 0; /* NZCF = 0100 */
7339 /* We do not support re-seeding, so the two registers operate the same. */
7340 static const ARMCPRegInfo rndr_reginfo
[] = {
7341 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7342 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7343 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7344 .access
= PL0_R
, .readfn
= rndr_readfn
},
7345 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7346 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7347 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7348 .access
= PL0_R
, .readfn
= rndr_readfn
},
7351 #ifndef CONFIG_USER_ONLY
7352 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7355 ARMCPU
*cpu
= env_archcpu(env
);
7356 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7357 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7358 uint64_t vaddr_in
= (uint64_t) value
;
7359 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7361 int mem_idx
= cpu_mmu_index(env
, false);
7363 /* This won't be crossing page boundaries */
7364 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7370 /* RCU lock is already being held */
7371 mr
= memory_region_from_host(haddr
, &offset
);
7374 memory_region_writeback(mr
, offset
, dline_size
);
7379 static const ARMCPRegInfo dcpop_reg
[] = {
7380 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7381 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7382 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7383 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7386 static const ARMCPRegInfo dcpodp_reg
[] = {
7387 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7388 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7389 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7390 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7392 #endif /*CONFIG_USER_ONLY*/
7394 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7397 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7398 return CP_ACCESS_TRAP_EL2
;
7401 return CP_ACCESS_OK
;
7404 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7407 int el
= arm_current_el(env
);
7409 if (el
< 2 && arm_is_el2_enabled(env
)) {
7410 uint64_t hcr
= arm_hcr_el2_eff(env
);
7411 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7412 return CP_ACCESS_TRAP_EL2
;
7416 arm_feature(env
, ARM_FEATURE_EL3
) &&
7417 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7418 return CP_ACCESS_TRAP_EL3
;
7420 return CP_ACCESS_OK
;
7423 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7425 return env
->pstate
& PSTATE_TCO
;
7428 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7430 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7433 static const ARMCPRegInfo mte_reginfo
[] = {
7434 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7435 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7436 .access
= PL1_RW
, .accessfn
= access_mte
,
7437 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7438 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7439 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7440 .access
= PL1_RW
, .accessfn
= access_mte
,
7441 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7442 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7443 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7444 .access
= PL2_RW
, .accessfn
= access_mte
,
7445 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7446 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7447 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7449 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7450 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7451 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7452 .access
= PL1_RW
, .accessfn
= access_mte
,
7453 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7454 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7455 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7456 .access
= PL1_RW
, .accessfn
= access_mte
,
7457 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7458 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7459 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7460 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7461 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7462 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7463 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7464 .type
= ARM_CP_NO_RAW
,
7465 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7466 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7467 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7468 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7469 .accessfn
= aa64_cacheop_poc_access
},
7470 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7471 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7472 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7473 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7474 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7475 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7476 .accessfn
= aa64_cacheop_poc_access
},
7477 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7478 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7479 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7480 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7481 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7482 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7483 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7484 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7485 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7486 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7487 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7488 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7489 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7490 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7491 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7494 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7495 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7496 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7497 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7500 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7501 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7502 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7503 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7504 .accessfn
= aa64_cacheop_poc_access
},
7505 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7506 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7507 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7508 .accessfn
= aa64_cacheop_poc_access
},
7509 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7510 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7511 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7512 .accessfn
= aa64_cacheop_poc_access
},
7513 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7514 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7515 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7516 .accessfn
= aa64_cacheop_poc_access
},
7517 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7518 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7519 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7520 .accessfn
= aa64_cacheop_poc_access
},
7521 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7522 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7523 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7524 .accessfn
= aa64_cacheop_poc_access
},
7525 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7526 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7527 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7528 .accessfn
= aa64_cacheop_poc_access
},
7529 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7530 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7531 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7532 .accessfn
= aa64_cacheop_poc_access
},
7533 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7534 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7535 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7536 #ifndef CONFIG_USER_ONLY
7537 /* Avoid overhead of an access check that always passes in user-mode */
7538 .accessfn
= aa64_zva_access
,
7541 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7542 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7543 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7544 #ifndef CONFIG_USER_ONLY
7545 /* Avoid overhead of an access check that always passes in user-mode */
7546 .accessfn
= aa64_zva_access
,
7551 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7554 uint64_t hcr
= arm_hcr_el2_eff(env
);
7555 int el
= arm_current_el(env
);
7557 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7558 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7559 if (hcr
& HCR_TGE
) {
7560 return CP_ACCESS_TRAP_EL2
;
7562 return CP_ACCESS_TRAP
;
7564 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7565 return CP_ACCESS_TRAP_EL2
;
7567 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7568 return CP_ACCESS_TRAP_EL2
;
7571 && arm_feature(env
, ARM_FEATURE_EL3
)
7572 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7573 return CP_ACCESS_TRAP_EL3
;
7575 return CP_ACCESS_OK
;
7578 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7579 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7580 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7581 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7582 .fgt
= FGT_SCXTNUM_EL0
,
7583 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7584 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7585 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7586 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7587 .fgt
= FGT_SCXTNUM_EL1
,
7588 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7589 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7590 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7591 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7592 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7593 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7594 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7596 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7599 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7602 if (arm_current_el(env
) == 2 &&
7603 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
7604 return CP_ACCESS_TRAP_EL3
;
7606 return CP_ACCESS_OK
;
7609 static const ARMCPRegInfo fgt_reginfo
[] = {
7610 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7611 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
7612 .access
= PL2_RW
, .accessfn
= access_fgt
,
7613 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
7614 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7615 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
7616 .access
= PL2_RW
, .accessfn
= access_fgt
,
7617 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
7618 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7619 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
7620 .access
= PL2_RW
, .accessfn
= access_fgt
,
7621 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
7622 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7623 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
7624 .access
= PL2_RW
, .accessfn
= access_fgt
,
7625 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
7626 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
7627 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
7628 .access
= PL2_RW
, .accessfn
= access_fgt
,
7629 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
7631 #endif /* TARGET_AARCH64 */
7633 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7636 int el
= arm_current_el(env
);
7639 uint64_t sctlr
= arm_sctlr(env
, el
);
7640 if (!(sctlr
& SCTLR_EnRCTX
)) {
7641 return CP_ACCESS_TRAP
;
7643 } else if (el
== 1) {
7644 uint64_t hcr
= arm_hcr_el2_eff(env
);
7646 return CP_ACCESS_TRAP_EL2
;
7649 return CP_ACCESS_OK
;
7652 static const ARMCPRegInfo predinv_reginfo
[] = {
7653 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7654 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7655 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7656 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7657 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7658 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7659 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7660 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7661 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7663 * Note the AArch32 opcodes have a different OPC1.
7665 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7666 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7667 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7668 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7669 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7670 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7671 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7672 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7673 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7676 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7678 /* Read the high 32 bits of the current CCSIDR */
7679 return extract64(ccsidr_read(env
, ri
), 32, 32);
7682 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7683 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7684 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7686 .accessfn
= access_tid4
,
7687 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7690 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7693 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7694 return CP_ACCESS_TRAP_EL2
;
7697 return CP_ACCESS_OK
;
7700 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7703 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7704 return access_aa64_tid3(env
, ri
, isread
);
7707 return CP_ACCESS_OK
;
7710 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7713 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7714 return CP_ACCESS_TRAP_EL2
;
7717 return CP_ACCESS_OK
;
7720 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7721 const ARMCPRegInfo
*ri
, bool isread
)
7724 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7725 * in v7A, not in v8A.
7727 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7728 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7729 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7730 return CP_ACCESS_TRAP_EL2
;
7732 return CP_ACCESS_OK
;
7735 static const ARMCPRegInfo jazelle_regs
[] = {
7737 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7738 .access
= PL1_R
, .accessfn
= access_jazelle
,
7739 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7741 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7742 .accessfn
= access_joscr_jmcr
,
7743 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7745 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7746 .accessfn
= access_joscr_jmcr
,
7747 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7750 static const ARMCPRegInfo contextidr_el2
= {
7751 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7752 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7754 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7757 static const ARMCPRegInfo vhe_reginfo
[] = {
7758 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7759 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7760 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7761 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7762 #ifndef CONFIG_USER_ONLY
7763 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7764 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7766 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7767 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7768 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7769 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7770 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7771 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7772 .resetfn
= gt_hv_timer_reset
,
7773 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7774 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7776 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7778 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7779 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7780 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7781 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7782 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7783 .access
= PL2_RW
, .accessfn
= e2h_access
,
7784 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7785 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7786 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7787 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7788 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7789 .access
= PL2_RW
, .accessfn
= e2h_access
,
7790 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7791 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7792 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7793 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7794 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7795 .access
= PL2_RW
, .accessfn
= e2h_access
,
7796 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7797 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7798 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7799 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7800 .access
= PL2_RW
, .accessfn
= e2h_access
,
7801 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7802 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7803 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7804 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7805 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7806 .access
= PL2_RW
, .accessfn
= e2h_access
,
7807 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7808 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7809 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7810 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7811 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7812 .access
= PL2_RW
, .accessfn
= e2h_access
,
7813 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7817 #ifndef CONFIG_USER_ONLY
7818 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7819 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
7820 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7821 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7822 .writefn
= ats_write64
},
7823 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
7824 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7825 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7826 .writefn
= ats_write64
},
7829 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7830 { .name
= "ATS1CPRP",
7831 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7832 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7833 .writefn
= ats_write
},
7834 { .name
= "ATS1CPWP",
7835 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7836 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7837 .writefn
= ats_write
},
7842 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7843 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7844 * is non-zero, which is never for ARMv7, optionally in ARMv8
7845 * and mandatorily for ARMv8.2 and up.
7846 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7847 * implementation is RAZ/WI we can ignore this detail, as we
7850 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7851 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7852 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7853 .access
= PL1_RW
, .accessfn
= access_tacr
,
7854 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7855 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7856 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7857 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7861 void register_cp_regs_for_features(ARMCPU
*cpu
)
7863 /* Register all the coprocessor registers based on feature bits */
7864 CPUARMState
*env
= &cpu
->env
;
7865 if (arm_feature(env
, ARM_FEATURE_M
)) {
7866 /* M profile has no coprocessor registers */
7870 define_arm_cp_regs(cpu
, cp_reginfo
);
7871 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7873 * Must go early as it is full of wildcards that may be
7874 * overridden by later definitions.
7876 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7879 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7880 /* The ID registers all have impdef reset values */
7881 ARMCPRegInfo v6_idregs
[] = {
7882 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7883 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7884 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7885 .accessfn
= access_aa32_tid3
,
7886 .resetvalue
= cpu
->isar
.id_pfr0
},
7888 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7889 * the value of the GIC field until after we define these regs.
7891 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7892 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7893 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7894 .accessfn
= access_aa32_tid3
,
7895 .readfn
= id_pfr1_read
,
7896 .writefn
= arm_cp_write_ignore
},
7897 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7898 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7899 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7900 .accessfn
= access_aa32_tid3
,
7901 .resetvalue
= cpu
->isar
.id_dfr0
},
7902 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7903 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7904 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7905 .accessfn
= access_aa32_tid3
,
7906 .resetvalue
= cpu
->id_afr0
},
7907 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7908 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7909 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7910 .accessfn
= access_aa32_tid3
,
7911 .resetvalue
= cpu
->isar
.id_mmfr0
},
7912 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7913 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7914 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7915 .accessfn
= access_aa32_tid3
,
7916 .resetvalue
= cpu
->isar
.id_mmfr1
},
7917 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7918 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7919 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7920 .accessfn
= access_aa32_tid3
,
7921 .resetvalue
= cpu
->isar
.id_mmfr2
},
7922 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7923 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7924 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7925 .accessfn
= access_aa32_tid3
,
7926 .resetvalue
= cpu
->isar
.id_mmfr3
},
7927 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7928 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7929 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7930 .accessfn
= access_aa32_tid3
,
7931 .resetvalue
= cpu
->isar
.id_isar0
},
7932 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7933 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7934 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7935 .accessfn
= access_aa32_tid3
,
7936 .resetvalue
= cpu
->isar
.id_isar1
},
7937 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7938 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7939 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7940 .accessfn
= access_aa32_tid3
,
7941 .resetvalue
= cpu
->isar
.id_isar2
},
7942 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7943 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7944 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7945 .accessfn
= access_aa32_tid3
,
7946 .resetvalue
= cpu
->isar
.id_isar3
},
7947 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7948 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7949 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7950 .accessfn
= access_aa32_tid3
,
7951 .resetvalue
= cpu
->isar
.id_isar4
},
7952 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7953 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7954 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7955 .accessfn
= access_aa32_tid3
,
7956 .resetvalue
= cpu
->isar
.id_isar5
},
7957 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7958 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7959 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7960 .accessfn
= access_aa32_tid3
,
7961 .resetvalue
= cpu
->isar
.id_mmfr4
},
7962 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7963 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7964 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7965 .accessfn
= access_aa32_tid3
,
7966 .resetvalue
= cpu
->isar
.id_isar6
},
7968 define_arm_cp_regs(cpu
, v6_idregs
);
7969 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7971 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7973 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7974 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7976 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7977 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7978 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7980 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7981 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7983 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7984 ARMCPRegInfo clidr
= {
7985 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7986 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7987 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7988 .accessfn
= access_tid4
,
7989 .fgt
= FGT_CLIDR_EL1
,
7990 .resetvalue
= cpu
->clidr
7992 define_one_arm_cp_reg(cpu
, &clidr
);
7993 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7994 define_debug_regs(cpu
);
7995 define_pmu_regs(cpu
);
7997 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7999 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8001 * v8 ID registers, which all have impdef reset values.
8002 * Note that within the ID register ranges the unused slots
8003 * must all RAZ, not UNDEF; future architecture versions may
8004 * define new registers here.
8005 * ID registers which are AArch64 views of the AArch32 ID registers
8006 * which already existed in v6 and v7 are handled elsewhere,
8010 ARMCPRegInfo v8_idregs
[] = {
8012 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8013 * emulation because we don't know the right value for the
8014 * GIC field until after we define these regs.
8016 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8017 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8019 #ifdef CONFIG_USER_ONLY
8020 .type
= ARM_CP_CONST
,
8021 .resetvalue
= cpu
->isar
.id_aa64pfr0
8023 .type
= ARM_CP_NO_RAW
,
8024 .accessfn
= access_aa64_tid3
,
8025 .readfn
= id_aa64pfr0_read
,
8026 .writefn
= arm_cp_write_ignore
8029 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8030 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8031 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8032 .accessfn
= access_aa64_tid3
,
8033 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8034 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8035 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8036 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8037 .accessfn
= access_aa64_tid3
,
8039 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8040 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8041 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8042 .accessfn
= access_aa64_tid3
,
8044 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8045 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8046 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8047 .accessfn
= access_aa64_tid3
,
8048 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8049 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8050 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8051 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8052 .accessfn
= access_aa64_tid3
,
8053 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8054 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8055 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8056 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8057 .accessfn
= access_aa64_tid3
,
8059 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8060 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8061 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8062 .accessfn
= access_aa64_tid3
,
8064 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8065 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8066 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8067 .accessfn
= access_aa64_tid3
,
8068 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8069 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8070 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8071 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8072 .accessfn
= access_aa64_tid3
,
8073 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8074 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8075 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8076 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8077 .accessfn
= access_aa64_tid3
,
8079 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8080 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8081 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8082 .accessfn
= access_aa64_tid3
,
8084 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8085 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8086 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8087 .accessfn
= access_aa64_tid3
,
8088 .resetvalue
= cpu
->id_aa64afr0
},
8089 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8090 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8091 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8092 .accessfn
= access_aa64_tid3
,
8093 .resetvalue
= cpu
->id_aa64afr1
},
8094 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8095 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8096 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8097 .accessfn
= access_aa64_tid3
,
8099 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8100 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8101 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8102 .accessfn
= access_aa64_tid3
,
8104 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8105 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8106 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8107 .accessfn
= access_aa64_tid3
,
8108 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8109 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8110 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8111 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8112 .accessfn
= access_aa64_tid3
,
8113 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8114 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8115 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8116 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8117 .accessfn
= access_aa64_tid3
,
8119 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8120 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8121 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8122 .accessfn
= access_aa64_tid3
,
8124 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8125 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8126 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8127 .accessfn
= access_aa64_tid3
,
8129 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8130 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8131 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8132 .accessfn
= access_aa64_tid3
,
8134 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8135 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8136 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8137 .accessfn
= access_aa64_tid3
,
8139 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8140 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8141 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8142 .accessfn
= access_aa64_tid3
,
8144 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8145 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8146 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8147 .accessfn
= access_aa64_tid3
,
8148 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8149 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8150 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8151 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8152 .accessfn
= access_aa64_tid3
,
8153 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8154 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8155 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8156 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8157 .accessfn
= access_aa64_tid3
,
8158 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8159 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8160 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8161 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8162 .accessfn
= access_aa64_tid3
,
8164 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8165 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8166 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8167 .accessfn
= access_aa64_tid3
,
8169 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8170 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8171 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8172 .accessfn
= access_aa64_tid3
,
8174 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8175 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8176 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8177 .accessfn
= access_aa64_tid3
,
8179 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8180 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8181 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8182 .accessfn
= access_aa64_tid3
,
8184 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8185 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8186 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8187 .accessfn
= access_aa64_tid3
,
8188 .resetvalue
= cpu
->isar
.mvfr0
},
8189 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8190 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8191 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8192 .accessfn
= access_aa64_tid3
,
8193 .resetvalue
= cpu
->isar
.mvfr1
},
8194 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8195 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8196 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8197 .accessfn
= access_aa64_tid3
,
8198 .resetvalue
= cpu
->isar
.mvfr2
},
8200 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8201 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8202 * as RAZ, since it is in the "reserved for future ID
8203 * registers, RAZ" part of the AArch32 encoding space.
8205 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8206 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8207 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8208 .accessfn
= access_aa64_tid3
,
8210 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8211 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8212 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8213 .accessfn
= access_aa64_tid3
,
8215 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8216 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8217 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8218 .accessfn
= access_aa64_tid3
,
8221 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8222 * they're also RAZ for AArch64, and in v8 are gradually
8223 * being filled with AArch64-view-of-AArch32-ID-register
8224 * for new ID registers.
8226 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8227 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8228 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8229 .accessfn
= access_aa64_tid3
,
8231 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8232 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8233 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8234 .accessfn
= access_aa64_tid3
,
8235 .resetvalue
= cpu
->isar
.id_pfr2
},
8236 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8237 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8238 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8239 .accessfn
= access_aa64_tid3
,
8240 .resetvalue
= cpu
->isar
.id_dfr1
},
8241 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8242 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8243 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8244 .accessfn
= access_aa64_tid3
,
8245 .resetvalue
= cpu
->isar
.id_mmfr5
},
8246 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8247 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8248 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8249 .accessfn
= access_aa64_tid3
,
8251 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8252 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8253 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8254 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8255 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8256 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8257 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8258 .resetvalue
= cpu
->pmceid0
},
8259 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8260 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8261 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8262 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8263 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8264 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8265 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8266 .resetvalue
= cpu
->pmceid1
},
8268 #ifdef CONFIG_USER_ONLY
8269 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8270 { .name
= "ID_AA64PFR0_EL1",
8271 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8272 R_ID_AA64PFR0_ADVSIMD_MASK
|
8273 R_ID_AA64PFR0_SVE_MASK
|
8274 R_ID_AA64PFR0_DIT_MASK
,
8275 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8276 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8277 { .name
= "ID_AA64PFR1_EL1",
8278 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8279 R_ID_AA64PFR1_SSBS_MASK
|
8280 R_ID_AA64PFR1_MTE_MASK
|
8281 R_ID_AA64PFR1_SME_MASK
},
8282 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8284 { .name
= "ID_AA64ZFR0_EL1",
8285 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8286 R_ID_AA64ZFR0_AES_MASK
|
8287 R_ID_AA64ZFR0_BITPERM_MASK
|
8288 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8289 R_ID_AA64ZFR0_SHA3_MASK
|
8290 R_ID_AA64ZFR0_SM4_MASK
|
8291 R_ID_AA64ZFR0_I8MM_MASK
|
8292 R_ID_AA64ZFR0_F32MM_MASK
|
8293 R_ID_AA64ZFR0_F64MM_MASK
},
8294 { .name
= "ID_AA64SMFR0_EL1",
8295 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8296 R_ID_AA64SMFR0_B16F32_MASK
|
8297 R_ID_AA64SMFR0_F16F32_MASK
|
8298 R_ID_AA64SMFR0_I8I32_MASK
|
8299 R_ID_AA64SMFR0_F64F64_MASK
|
8300 R_ID_AA64SMFR0_I16I64_MASK
|
8301 R_ID_AA64SMFR0_FA64_MASK
},
8302 { .name
= "ID_AA64MMFR0_EL1",
8303 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8304 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8305 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8306 { .name
= "ID_AA64MMFR1_EL1",
8307 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8308 { .name
= "ID_AA64MMFR2_EL1",
8309 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8310 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8312 { .name
= "ID_AA64DFR0_EL1",
8313 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8314 { .name
= "ID_AA64DFR1_EL1" },
8315 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8317 { .name
= "ID_AA64AFR*",
8319 { .name
= "ID_AA64ISAR0_EL1",
8320 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8321 R_ID_AA64ISAR0_SHA1_MASK
|
8322 R_ID_AA64ISAR0_SHA2_MASK
|
8323 R_ID_AA64ISAR0_CRC32_MASK
|
8324 R_ID_AA64ISAR0_ATOMIC_MASK
|
8325 R_ID_AA64ISAR0_RDM_MASK
|
8326 R_ID_AA64ISAR0_SHA3_MASK
|
8327 R_ID_AA64ISAR0_SM3_MASK
|
8328 R_ID_AA64ISAR0_SM4_MASK
|
8329 R_ID_AA64ISAR0_DP_MASK
|
8330 R_ID_AA64ISAR0_FHM_MASK
|
8331 R_ID_AA64ISAR0_TS_MASK
|
8332 R_ID_AA64ISAR0_RNDR_MASK
},
8333 { .name
= "ID_AA64ISAR1_EL1",
8334 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8335 R_ID_AA64ISAR1_APA_MASK
|
8336 R_ID_AA64ISAR1_API_MASK
|
8337 R_ID_AA64ISAR1_JSCVT_MASK
|
8338 R_ID_AA64ISAR1_FCMA_MASK
|
8339 R_ID_AA64ISAR1_LRCPC_MASK
|
8340 R_ID_AA64ISAR1_GPA_MASK
|
8341 R_ID_AA64ISAR1_GPI_MASK
|
8342 R_ID_AA64ISAR1_FRINTTS_MASK
|
8343 R_ID_AA64ISAR1_SB_MASK
|
8344 R_ID_AA64ISAR1_BF16_MASK
|
8345 R_ID_AA64ISAR1_DGH_MASK
|
8346 R_ID_AA64ISAR1_I8MM_MASK
},
8347 { .name
= "ID_AA64ISAR2_EL1",
8348 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8349 R_ID_AA64ISAR2_RPRES_MASK
|
8350 R_ID_AA64ISAR2_GPA3_MASK
|
8351 R_ID_AA64ISAR2_APA3_MASK
},
8352 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8355 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8357 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
8358 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8359 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8360 ARMCPRegInfo rvbar
= {
8361 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8362 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8364 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8366 define_one_arm_cp_reg(cpu
, &rvbar
);
8368 define_arm_cp_regs(cpu
, v8_idregs
);
8369 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8371 for (i
= 4; i
< 16; i
++) {
8373 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8374 * For pre-v8 cores there are RAZ patterns for these in
8375 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8376 * v8 extends the "must RAZ" part of the ID register space
8377 * to also cover c0, 0, c{8-15}, {0-7}.
8378 * These are STATE_AA32 because in the AArch64 sysreg space
8379 * c4-c7 is where the AArch64 ID registers live (and we've
8380 * already defined those in v8_idregs[]), and c8-c15 are not
8381 * "must RAZ" for AArch64.
8383 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8384 ARMCPRegInfo v8_aa32_raz_idregs
= {
8386 .state
= ARM_CP_STATE_AA32
,
8387 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8388 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8389 .accessfn
= access_aa64_tid3
,
8391 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8396 * Register the base EL2 cpregs.
8397 * Pre v8, these registers are implemented only as part of the
8398 * Virtualization Extensions (EL2 present). Beginning with v8,
8399 * if EL2 is missing but EL3 is enabled, mostly these become
8400 * RES0 from EL3, with some specific exceptions.
8402 if (arm_feature(env
, ARM_FEATURE_EL2
)
8403 || (arm_feature(env
, ARM_FEATURE_EL3
)
8404 && arm_feature(env
, ARM_FEATURE_V8
))) {
8405 uint64_t vmpidr_def
= mpidr_read_val(env
);
8406 ARMCPRegInfo vpidr_regs
[] = {
8407 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8408 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8409 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8410 .resetvalue
= cpu
->midr
,
8411 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8412 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8413 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8414 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8415 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8416 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8417 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8418 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8419 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8420 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8421 .resetvalue
= vmpidr_def
,
8422 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8423 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8424 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8425 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8426 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8427 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8428 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8431 * The only field of MDCR_EL2 that has a defined architectural reset
8432 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8434 ARMCPRegInfo mdcr_el2
= {
8435 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8436 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8437 .writefn
= mdcr_el2_write
,
8438 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8439 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8441 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8442 define_arm_cp_regs(cpu
, vpidr_regs
);
8443 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8444 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8445 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8447 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8448 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8450 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
8451 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8452 ARMCPRegInfo rvbar
[] = {
8454 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8455 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8457 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8459 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8460 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8462 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8465 define_arm_cp_regs(cpu
, rvbar
);
8469 /* Register the base EL3 cpregs. */
8470 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8471 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8472 ARMCPRegInfo el3_regs
[] = {
8473 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8474 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8476 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8478 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8479 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8481 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8482 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8483 .resetvalue
= cpu
->reset_sctlr
},
8486 define_arm_cp_regs(cpu
, el3_regs
);
8489 * The behaviour of NSACR is sufficiently various that we don't
8490 * try to describe it in a single reginfo:
8491 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8492 * reads as constant 0xc00 from NS EL1 and NS EL2
8493 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8494 * if v7 without EL3, register doesn't exist
8495 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8497 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8498 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8499 static const ARMCPRegInfo nsacr
= {
8500 .name
= "NSACR", .type
= ARM_CP_CONST
,
8501 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8502 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8505 define_one_arm_cp_reg(cpu
, &nsacr
);
8507 static const ARMCPRegInfo nsacr
= {
8509 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8510 .access
= PL3_RW
| PL1_R
,
8512 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8514 define_one_arm_cp_reg(cpu
, &nsacr
);
8517 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8518 static const ARMCPRegInfo nsacr
= {
8519 .name
= "NSACR", .type
= ARM_CP_CONST
,
8520 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8524 define_one_arm_cp_reg(cpu
, &nsacr
);
8528 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8529 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8530 /* PMSAv6 not implemented */
8531 assert(arm_feature(env
, ARM_FEATURE_V7
));
8532 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8533 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8535 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8538 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8539 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8540 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8541 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8542 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8545 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8546 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8548 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8549 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8551 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8552 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8554 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8555 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8557 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8558 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8560 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8561 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8563 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8564 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8566 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8567 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8569 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8570 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8572 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8573 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8575 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8576 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8578 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8579 define_arm_cp_regs(cpu
, jazelle_regs
);
8582 * Slightly awkwardly, the OMAP and StrongARM cores need all of
8583 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8584 * be read-only (ie write causes UNDEF exception).
8587 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8589 * Pre-v8 MIDR space.
8590 * Note that the MIDR isn't a simple constant register because
8591 * of the TI925 behaviour where writes to another register can
8592 * cause the MIDR value to change.
8594 * Unimplemented registers in the c15 0 0 0 space default to
8595 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8596 * and friends override accordingly.
8599 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8600 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8601 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8602 .readfn
= midr_read
,
8603 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8604 .type
= ARM_CP_OVERRIDE
},
8605 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8607 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8608 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8610 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8611 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8613 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8614 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8616 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8617 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8619 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8620 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8622 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8623 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8624 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8625 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8626 .fgt
= FGT_MIDR_EL1
,
8627 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8628 .readfn
= midr_read
},
8629 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
8630 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8631 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8632 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8633 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8634 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8636 .accessfn
= access_aa64_tid1
,
8637 .fgt
= FGT_REVIDR_EL1
,
8638 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8640 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
8641 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8642 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8643 .access
= PL1_R
, .resetvalue
= cpu
->midr
8645 ARMCPRegInfo id_cp_reginfo
[] = {
8646 /* These are common to v8 and pre-v8 */
8648 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8649 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8650 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8651 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8652 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8653 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8655 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8656 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8658 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8660 .accessfn
= access_aa32_tid1
,
8661 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8663 /* TLBTR is specific to VMSA */
8664 ARMCPRegInfo id_tlbtr_reginfo
= {
8666 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8668 .accessfn
= access_aa32_tid1
,
8669 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8671 /* MPUIR is specific to PMSA V6+ */
8672 ARMCPRegInfo id_mpuir_reginfo
= {
8674 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8675 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8676 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8678 /* HMPUIR is specific to PMSA V8 */
8679 ARMCPRegInfo id_hmpuir_reginfo
= {
8681 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
8682 .access
= PL2_R
, .type
= ARM_CP_CONST
,
8683 .resetvalue
= cpu
->pmsav8r_hdregion
8685 static const ARMCPRegInfo crn0_wi_reginfo
= {
8686 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8687 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8688 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8690 #ifdef CONFIG_USER_ONLY
8691 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8692 { .name
= "MIDR_EL1",
8693 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
8694 R_MIDR_EL1_PARTNUM_MASK
|
8695 R_MIDR_EL1_ARCHITECTURE_MASK
|
8696 R_MIDR_EL1_VARIANT_MASK
|
8697 R_MIDR_EL1_IMPLEMENTER_MASK
},
8698 { .name
= "REVIDR_EL1" },
8700 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8702 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8703 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8706 * Register the blanket "writes ignored" value first to cover the
8707 * whole space. Then update the specific ID registers to allow write
8708 * access, so that they ignore writes rather than causing them to
8711 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8712 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8713 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8715 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8716 id_cp_reginfo
[i
].access
= PL1_RW
;
8718 id_mpuir_reginfo
.access
= PL1_RW
;
8719 id_tlbtr_reginfo
.access
= PL1_RW
;
8721 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8722 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8723 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8724 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
8727 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8729 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8730 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8731 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8732 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
8733 arm_feature(env
, ARM_FEATURE_V8
)) {
8737 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8738 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
8739 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
8741 /* Register alias is only valid for first 32 indexes */
8742 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
8743 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
8744 uint8_t opc1
= extract32(i
, 4, 1);
8745 uint8_t opc2
= extract32(i
, 0, 1) << 2;
8747 tmp_string
= g_strdup_printf("PRBAR%u", i
);
8748 ARMCPRegInfo tmp_prbarn_reginfo
= {
8749 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
8750 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8751 .access
= PL1_RW
, .resetvalue
= 0,
8752 .accessfn
= access_tvm_trvm
,
8753 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8755 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
8758 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
8759 tmp_string
= g_strdup_printf("PRLAR%u", i
);
8760 ARMCPRegInfo tmp_prlarn_reginfo
= {
8761 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
8762 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8763 .access
= PL1_RW
, .resetvalue
= 0,
8764 .accessfn
= access_tvm_trvm
,
8765 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8767 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
8771 /* Register alias is only valid for first 32 indexes */
8772 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
8773 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
8774 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
8775 uint8_t opc2
= extract32(i
, 0, 1) << 2;
8777 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
8778 ARMCPRegInfo tmp_hprbarn_reginfo
= {
8780 .type
= ARM_CP_NO_RAW
,
8781 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8782 .access
= PL2_RW
, .resetvalue
= 0,
8783 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8785 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
8788 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
8789 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
8790 ARMCPRegInfo tmp_hprlarn_reginfo
= {
8792 .type
= ARM_CP_NO_RAW
,
8793 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8794 .access
= PL2_RW
, .resetvalue
= 0,
8795 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8797 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
8800 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8801 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8805 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8806 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8807 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8808 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8809 .fgt
= FGT_MPIDR_EL1
,
8810 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8812 #ifdef CONFIG_USER_ONLY
8813 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8814 { .name
= "MPIDR_EL1",
8815 .fixed_bits
= 0x0000000080000000 },
8817 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8819 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8822 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8823 ARMCPRegInfo auxcr_reginfo
[] = {
8824 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8825 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8826 .access
= PL1_RW
, .accessfn
= access_tacr
,
8827 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8828 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8829 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8830 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8832 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8833 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8834 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8837 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8838 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8839 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8843 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8845 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8846 * There are two flavours:
8847 * (1) older 32-bit only cores have a simple 32-bit CBAR
8848 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8849 * 32-bit register visible to AArch32 at a different encoding
8850 * to the "flavour 1" register and with the bits rearranged to
8851 * be able to squash a 64-bit address into the 32-bit view.
8852 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8853 * in future if we support AArch32-only configs of some of the
8854 * AArch64 cores we might need to add a specific feature flag
8855 * to indicate cores with "flavour 2" CBAR.
8857 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8858 /* 32 bit view is [31:18] 0...0 [43:32]. */
8859 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8860 | extract64(cpu
->reset_cbar
, 32, 12);
8861 ARMCPRegInfo cbar_reginfo
[] = {
8863 .type
= ARM_CP_CONST
,
8864 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8865 .access
= PL1_R
, .resetvalue
= cbar32
},
8866 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8867 .type
= ARM_CP_CONST
,
8868 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8869 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8871 /* We don't implement a r/w 64 bit CBAR currently */
8872 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8873 define_arm_cp_regs(cpu
, cbar_reginfo
);
8875 ARMCPRegInfo cbar
= {
8877 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8878 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8879 .fieldoffset
= offsetof(CPUARMState
,
8880 cp15
.c15_config_base_address
)
8882 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8883 cbar
.access
= PL1_R
;
8884 cbar
.fieldoffset
= 0;
8885 cbar
.type
= ARM_CP_CONST
;
8887 define_one_arm_cp_reg(cpu
, &cbar
);
8891 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8892 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
8893 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8894 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8895 .access
= PL1_RW
, .writefn
= vbar_write
,
8896 .fgt
= FGT_VBAR_EL1
,
8897 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8898 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8901 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8904 /* Generic registers whose values depend on the implementation */
8906 ARMCPRegInfo sctlr
= {
8907 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8908 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8909 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8910 .fgt
= FGT_SCTLR_EL1
,
8911 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8912 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8913 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8914 .raw_writefn
= raw_write
,
8916 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8918 * Normally we would always end the TB on an SCTLR write, but Linux
8919 * arch/arm/mach-pxa/sleep.S expects two instructions following
8920 * an MMU enable to execute from cache. Imitate this behaviour.
8922 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8924 define_one_arm_cp_reg(cpu
, &sctlr
);
8926 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
8927 arm_feature(env
, ARM_FEATURE_V8
)) {
8928 ARMCPRegInfo vsctlr
= {
8929 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
8930 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
8931 .access
= PL2_RW
, .resetvalue
= 0x0,
8932 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
8934 define_one_arm_cp_reg(cpu
, &vsctlr
);
8938 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8939 define_arm_cp_regs(cpu
, lor_reginfo
);
8941 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8942 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8944 #ifndef CONFIG_USER_ONLY
8945 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8946 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8948 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8949 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8952 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8953 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8956 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8957 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8959 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8960 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8962 if (cpu_isar_feature(any_ras
, cpu
)) {
8963 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
8966 if (cpu_isar_feature(aa64_vh
, cpu
) ||
8967 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
8968 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
8970 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8971 define_arm_cp_regs(cpu
, vhe_reginfo
);
8974 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8975 define_arm_cp_regs(cpu
, zcr_reginfo
);
8978 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
8979 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
8982 #ifdef TARGET_AARCH64
8983 if (cpu_isar_feature(aa64_sme
, cpu
)) {
8984 define_arm_cp_regs(cpu
, sme_reginfo
);
8986 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8987 define_arm_cp_regs(cpu
, pauth_reginfo
);
8989 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8990 define_arm_cp_regs(cpu
, rndr_reginfo
);
8992 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8993 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8995 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8996 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8998 #ifndef CONFIG_USER_ONLY
8999 /* Data Cache clean instructions up to PoP */
9000 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9001 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9003 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9004 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9007 #endif /*CONFIG_USER_ONLY*/
9010 * If full MTE is enabled, add all of the system registers.
9011 * If only "instructions available at EL0" are enabled,
9012 * then define only a RAZ/WI version of PSTATE.TCO.
9014 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9015 define_arm_cp_regs(cpu
, mte_reginfo
);
9016 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9017 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9018 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9019 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9022 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9023 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9026 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9027 define_arm_cp_regs(cpu
, fgt_reginfo
);
9031 if (cpu_isar_feature(any_predinv
, cpu
)) {
9032 define_arm_cp_regs(cpu
, predinv_reginfo
);
9035 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9036 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9039 #ifndef CONFIG_USER_ONLY
9041 * Register redirections and aliases must be done last,
9042 * after the registers from the other extensions have been defined.
9044 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9045 define_arm_vh_e2h_redirects_aliases(cpu
);
9050 /* Sort alphabetically by type name, except for "any". */
9051 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
9053 ObjectClass
*class_a
= (ObjectClass
*)a
;
9054 ObjectClass
*class_b
= (ObjectClass
*)b
;
9055 const char *name_a
, *name_b
;
9057 name_a
= object_class_get_name(class_a
);
9058 name_b
= object_class_get_name(class_b
);
9059 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
9061 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
9064 return strcmp(name_a
, name_b
);
9068 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
9070 ObjectClass
*oc
= data
;
9071 CPUClass
*cc
= CPU_CLASS(oc
);
9072 const char *typename
;
9075 typename
= object_class_get_name(oc
);
9076 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9077 if (cc
->deprecation_note
) {
9078 qemu_printf(" %s (deprecated)\n", name
);
9080 qemu_printf(" %s\n", name
);
9085 void arm_cpu_list(void)
9089 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9090 list
= g_slist_sort(list
, arm_cpu_list_compare
);
9091 qemu_printf("Available CPUs:\n");
9092 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
9096 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
9098 ObjectClass
*oc
= data
;
9099 CpuDefinitionInfoList
**cpu_list
= user_data
;
9100 CpuDefinitionInfo
*info
;
9101 const char *typename
;
9103 typename
= object_class_get_name(oc
);
9104 info
= g_malloc0(sizeof(*info
));
9105 info
->name
= g_strndup(typename
,
9106 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9107 info
->q_typename
= g_strdup(typename
);
9109 QAPI_LIST_PREPEND(*cpu_list
, info
);
9112 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
9114 CpuDefinitionInfoList
*cpu_list
= NULL
;
9117 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9118 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
9125 * Private utility function for define_one_arm_cp_reg_with_opaque():
9126 * add a single reginfo struct to the hash table.
9128 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9129 void *opaque
, CPState state
,
9130 CPSecureState secstate
,
9131 int crm
, int opc1
, int opc2
,
9134 CPUARMState
*env
= &cpu
->env
;
9137 bool is64
= r
->type
& ARM_CP_64BIT
;
9138 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9144 case ARM_CP_STATE_AA32
:
9145 /* We assume it is a cp15 register if the .cp field is left unset. */
9146 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9149 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9151 case ARM_CP_STATE_AA64
:
9153 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9154 * cp == 0 as equivalent to the value for "standard guest-visible
9155 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9156 * in their AArch64 view (the .cp value may be non-zero for the
9157 * benefit of the AArch32 view).
9159 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9160 cp
= CP_REG_ARM64_SYSREG_CP
;
9162 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9165 g_assert_not_reached();
9168 /* Overriding of an existing definition must be explicitly requested. */
9169 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9170 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9172 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9177 * Eliminate registers that are not present because the EL is missing.
9178 * Doing this here makes it easier to put all registers for a given
9179 * feature into the same ARMCPRegInfo array and define them all at once.
9182 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9184 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9185 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9187 int min_el
= ctz32(r
->access
) / 2;
9188 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9189 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9192 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9195 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9197 if ((r
->access
& max_el
) == 0) {
9202 /* Combine cpreg and name into one allocation. */
9203 name_len
= strlen(name
) + 1;
9204 r2
= g_malloc(sizeof(*r2
) + name_len
);
9206 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9209 * Update fields to match the instantiation, overwiting wildcards
9210 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9217 r2
->secure
= secstate
;
9219 r2
->opaque
= opaque
;
9223 /* This should not have been a very special register to begin. */
9224 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9225 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9227 * Set the special function to CONST, retaining the other flags.
9228 * This is important for e.g. ARM_CP_SVE so that we still
9229 * take the SVE trap if CPTR_EL3.EZ == 0.
9231 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9233 * Usually, these registers become RES0, but there are a few
9234 * special cases like VPIDR_EL2 which have a constant non-zero
9235 * value with writes ignored.
9237 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9241 * ARM_CP_CONST has precedence, so removing the callbacks and
9242 * offsets are not strictly necessary, but it is potentially
9243 * less confusing to debug later.
9247 r2
->raw_readfn
= NULL
;
9248 r2
->raw_writefn
= NULL
;
9250 r2
->fieldoffset
= 0;
9251 r2
->bank_fieldoffsets
[0] = 0;
9252 r2
->bank_fieldoffsets
[1] = 0;
9254 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9258 * Register is banked (using both entries in array).
9259 * Overwriting fieldoffset as the array is only used to define
9260 * banked registers but later only fieldoffset is used.
9262 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9264 if (state
== ARM_CP_STATE_AA32
) {
9267 * If the register is banked then we don't need to migrate or
9268 * reset the 32-bit instance in certain cases:
9270 * 1) If the register has both 32-bit and 64-bit instances
9271 * then we can count on the 64-bit instance taking care
9272 * of the non-secure bank.
9273 * 2) If ARMv8 is enabled then we can count on a 64-bit
9274 * version taking care of the secure bank. This requires
9275 * that separate 32 and 64-bit definitions are provided.
9277 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9278 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9279 r2
->type
|= ARM_CP_ALIAS
;
9281 } else if ((secstate
!= r
->secure
) && !ns
) {
9283 * The register is not banked so we only want to allow
9284 * migration of the non-secure instance.
9286 r2
->type
|= ARM_CP_ALIAS
;
9289 if (HOST_BIG_ENDIAN
&&
9290 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9291 r2
->fieldoffset
+= sizeof(uint32_t);
9297 * By convention, for wildcarded registers only the first
9298 * entry is used for migration; the others are marked as
9299 * ALIAS so we don't try to transfer the register
9300 * multiple times. Special registers (ie NOP/WFI) are
9301 * never migratable and not even raw-accessible.
9303 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9304 r2
->type
|= ARM_CP_NO_RAW
;
9306 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9307 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9308 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9309 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9313 * Check that raw accesses are either forbidden or handled. Note that
9314 * we can't assert this earlier because the setup of fieldoffset for
9315 * banked registers has to be done first.
9317 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9318 assert(!raw_accessors_invalid(r2
));
9321 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9325 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9326 const ARMCPRegInfo
*r
, void *opaque
)
9329 * Define implementations of coprocessor registers.
9330 * We store these in a hashtable because typically
9331 * there are less than 150 registers in a space which
9332 * is 16*16*16*8*8 = 262144 in size.
9333 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9334 * If a register is defined twice then the second definition is
9335 * used, so this can be used to define some generic registers and
9336 * then override them with implementation specific variations.
9337 * At least one of the original and the second definition should
9338 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9339 * against accidental use.
9341 * The state field defines whether the register is to be
9342 * visible in the AArch32 or AArch64 execution state. If the
9343 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9344 * reginfo structure for the AArch32 view, which sees the lower
9345 * 32 bits of the 64 bit register.
9347 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9348 * be wildcarded. AArch64 registers are always considered to be 64
9349 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9350 * the register, if any.
9352 int crm
, opc1
, opc2
;
9353 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9354 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9355 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9356 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9357 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9358 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9361 /* 64 bit registers have only CRm and Opc1 fields */
9362 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9363 /* op0 only exists in the AArch64 encodings */
9364 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9365 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9366 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9368 * This API is only for Arm's system coprocessors (14 and 15) or
9369 * (M-profile or v7A-and-earlier only) for implementation defined
9370 * coprocessors in the range 0..7. Our decode assumes this, since
9371 * 8..13 can be used for other insns including VFP and Neon. See
9372 * valid_cp() in translate.c. Assert here that we haven't tried
9373 * to use an invalid coprocessor number.
9376 case ARM_CP_STATE_BOTH
:
9377 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9382 case ARM_CP_STATE_AA32
:
9383 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9384 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9385 assert(r
->cp
>= 14 && r
->cp
<= 15);
9387 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9390 case ARM_CP_STATE_AA64
:
9391 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9394 g_assert_not_reached();
9397 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9398 * encodes a minimum access level for the register. We roll this
9399 * runtime check into our general permission check code, so check
9400 * here that the reginfo's specified permissions are strict enough
9401 * to encompass the generic architectural permission check.
9403 if (r
->state
!= ARM_CP_STATE_AA32
) {
9404 CPAccessRights mask
;
9407 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9408 mask
= PL0U_R
| PL1_RW
;
9428 /* min_EL EL1, secure mode only (we don't check the latter) */
9432 /* broken reginfo with out-of-range opc1 */
9433 g_assert_not_reached();
9435 /* assert our permissions are not too lax (stricter is fine) */
9436 assert((r
->access
& ~mask
) == 0);
9440 * Check that the register definition has enough info to handle
9441 * reads and writes if they are permitted.
9443 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9444 if (r
->access
& PL3_R
) {
9445 assert((r
->fieldoffset
||
9446 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9449 if (r
->access
& PL3_W
) {
9450 assert((r
->fieldoffset
||
9451 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9456 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9457 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9458 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9459 for (state
= ARM_CP_STATE_AA32
;
9460 state
<= ARM_CP_STATE_AA64
; state
++) {
9461 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9464 if (state
== ARM_CP_STATE_AA32
) {
9466 * Under AArch32 CP registers can be common
9467 * (same for secure and non-secure world) or banked.
9471 switch (r
->secure
) {
9472 case ARM_CP_SECSTATE_S
:
9473 case ARM_CP_SECSTATE_NS
:
9474 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9475 r
->secure
, crm
, opc1
, opc2
,
9478 case ARM_CP_SECSTATE_BOTH
:
9479 name
= g_strdup_printf("%s_S", r
->name
);
9480 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9482 crm
, opc1
, opc2
, name
);
9484 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9486 crm
, opc1
, opc2
, r
->name
);
9489 g_assert_not_reached();
9493 * AArch64 registers get mapped to non-secure instance
9496 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9498 crm
, opc1
, opc2
, r
->name
);
9506 /* Define a whole list of registers */
9507 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
9508 void *opaque
, size_t len
)
9511 for (i
= 0; i
< len
; ++i
) {
9512 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
9517 * Modify ARMCPRegInfo for access from userspace.
9519 * This is a data driven modification directed by
9520 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9521 * user-space cannot alter any values and dynamic values pertaining to
9522 * execution state are hidden from user space view anyway.
9524 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
9525 const ARMCPRegUserSpaceInfo
*mods
,
9528 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9529 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9530 GPatternSpec
*pat
= NULL
;
9533 pat
= g_pattern_spec_new(m
->name
);
9535 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9536 ARMCPRegInfo
*r
= regs
+ ri
;
9538 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9539 r
->type
= ARM_CP_CONST
;
9543 } else if (strcmp(r
->name
, m
->name
) == 0) {
9544 r
->type
= ARM_CP_CONST
;
9546 r
->resetvalue
&= m
->exported_bits
;
9547 r
->resetvalue
|= m
->fixed_bits
;
9552 g_pattern_spec_free(pat
);
9557 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9559 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9562 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9565 /* Helper coprocessor write function for write-ignore registers */
9568 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9570 /* Helper coprocessor write function for read-as-zero registers */
9574 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9576 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9579 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9582 * Return true if it is not valid for us to switch to
9583 * this CPU mode (ie all the UNPREDICTABLE cases in
9584 * the ARM ARM CPSRWriteByInstr pseudocode).
9587 /* Changes to or from Hyp via MSR and CPS are illegal. */
9588 if (write_type
== CPSRWriteByInstr
&&
9589 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9590 mode
== ARM_CPU_MODE_HYP
)) {
9595 case ARM_CPU_MODE_USR
:
9597 case ARM_CPU_MODE_SYS
:
9598 case ARM_CPU_MODE_SVC
:
9599 case ARM_CPU_MODE_ABT
:
9600 case ARM_CPU_MODE_UND
:
9601 case ARM_CPU_MODE_IRQ
:
9602 case ARM_CPU_MODE_FIQ
:
9604 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
9605 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9608 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9609 * and CPS are treated as illegal mode changes.
9611 if (write_type
== CPSRWriteByInstr
&&
9612 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9613 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9617 case ARM_CPU_MODE_HYP
:
9618 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9619 case ARM_CPU_MODE_MON
:
9620 return arm_current_el(env
) < 3;
9626 uint32_t cpsr_read(CPUARMState
*env
)
9629 ZF
= (env
->ZF
== 0);
9630 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9631 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9632 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9633 | ((env
->condexec_bits
& 0xfc) << 8)
9634 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9637 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9638 CPSRWriteType write_type
)
9640 uint32_t changed_daif
;
9641 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9642 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9644 if (mask
& CPSR_NZCV
) {
9645 env
->ZF
= (~val
) & CPSR_Z
;
9647 env
->CF
= (val
>> 29) & 1;
9648 env
->VF
= (val
<< 3) & 0x80000000;
9650 if (mask
& CPSR_Q
) {
9651 env
->QF
= ((val
& CPSR_Q
) != 0);
9653 if (mask
& CPSR_T
) {
9654 env
->thumb
= ((val
& CPSR_T
) != 0);
9656 if (mask
& CPSR_IT_0_1
) {
9657 env
->condexec_bits
&= ~3;
9658 env
->condexec_bits
|= (val
>> 25) & 3;
9660 if (mask
& CPSR_IT_2_7
) {
9661 env
->condexec_bits
&= 3;
9662 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9664 if (mask
& CPSR_GE
) {
9665 env
->GE
= (val
>> 16) & 0xf;
9669 * In a V7 implementation that includes the security extensions but does
9670 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9671 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9672 * bits respectively.
9674 * In a V8 implementation, it is permitted for privileged software to
9675 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9677 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9678 arm_feature(env
, ARM_FEATURE_EL3
) &&
9679 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9680 !arm_is_secure(env
)) {
9682 changed_daif
= (env
->daif
^ val
) & mask
;
9684 if (changed_daif
& CPSR_A
) {
9686 * Check to see if we are allowed to change the masking of async
9687 * abort exceptions from a non-secure state.
9689 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9690 qemu_log_mask(LOG_GUEST_ERROR
,
9691 "Ignoring attempt to switch CPSR_A flag from "
9692 "non-secure world with SCR.AW bit clear\n");
9697 if (changed_daif
& CPSR_F
) {
9699 * Check to see if we are allowed to change the masking of FIQ
9700 * exceptions from a non-secure state.
9702 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9703 qemu_log_mask(LOG_GUEST_ERROR
,
9704 "Ignoring attempt to switch CPSR_F flag from "
9705 "non-secure world with SCR.FW bit clear\n");
9710 * Check whether non-maskable FIQ (NMFI) support is enabled.
9711 * If this bit is set software is not allowed to mask
9712 * FIQs, but is allowed to set CPSR_F to 0.
9714 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9716 qemu_log_mask(LOG_GUEST_ERROR
,
9717 "Ignoring attempt to enable CPSR_F flag "
9718 "(non-maskable FIQ [NMFI] support enabled)\n");
9724 env
->daif
&= ~(CPSR_AIF
& mask
);
9725 env
->daif
|= val
& CPSR_AIF
& mask
;
9727 if (write_type
!= CPSRWriteRaw
&&
9728 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9729 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9731 * Note that we can only get here in USR mode if this is a
9732 * gdb stub write; for this case we follow the architectural
9733 * behaviour for guest writes in USR mode of ignoring an attempt
9734 * to switch mode. (Those are caught by translate.c for writes
9735 * triggered by guest instructions.)
9738 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9740 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9741 * v7, and has defined behaviour in v8:
9742 * + leave CPSR.M untouched
9743 * + allow changes to the other CPSR fields
9745 * For user changes via the GDB stub, we don't set PSTATE.IL,
9746 * as this would be unnecessarily harsh for a user error.
9749 if (write_type
!= CPSRWriteByGDBStub
&&
9750 arm_feature(env
, ARM_FEATURE_V8
)) {
9754 qemu_log_mask(LOG_GUEST_ERROR
,
9755 "Illegal AArch32 mode switch attempt from %s to %s\n",
9756 aarch32_mode_name(env
->uncached_cpsr
),
9757 aarch32_mode_name(val
));
9759 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9760 write_type
== CPSRWriteExceptionReturn
?
9761 "Exception return from AArch32" :
9762 "AArch32 mode switch from",
9763 aarch32_mode_name(env
->uncached_cpsr
),
9764 aarch32_mode_name(val
), env
->regs
[15]);
9765 switch_mode(env
, val
& CPSR_M
);
9768 mask
&= ~CACHED_CPSR_BITS
;
9769 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9770 if (rebuild_hflags
) {
9771 arm_rebuild_hflags(env
);
9775 /* Sign/zero extend */
9776 uint32_t HELPER(sxtb16
)(uint32_t x
)
9779 res
= (uint16_t)(int8_t)x
;
9780 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9784 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9787 * Take a division-by-zero exception if necessary; otherwise return
9788 * to get the usual non-trapping division behaviour (result of 0)
9790 if (arm_feature(env
, ARM_FEATURE_M
)
9791 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9792 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9796 uint32_t HELPER(uxtb16
)(uint32_t x
)
9799 res
= (uint16_t)(uint8_t)x
;
9800 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9804 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9807 handle_possible_div0_trap(env
, GETPC());
9810 if (num
== INT_MIN
&& den
== -1) {
9816 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9819 handle_possible_div0_trap(env
, GETPC());
9825 uint32_t HELPER(rbit
)(uint32_t x
)
9830 #ifdef CONFIG_USER_ONLY
9832 static void switch_mode(CPUARMState
*env
, int mode
)
9834 ARMCPU
*cpu
= env_archcpu(env
);
9836 if (mode
!= ARM_CPU_MODE_USR
) {
9837 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9841 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9842 uint32_t cur_el
, bool secure
)
9847 void aarch64_sync_64_to_32(CPUARMState
*env
)
9849 g_assert_not_reached();
9854 static void switch_mode(CPUARMState
*env
, int mode
)
9859 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9860 if (mode
== old_mode
) {
9864 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9865 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9866 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9867 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9868 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9869 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9872 i
= bank_number(old_mode
);
9873 env
->banked_r13
[i
] = env
->regs
[13];
9874 env
->banked_spsr
[i
] = env
->spsr
;
9876 i
= bank_number(mode
);
9877 env
->regs
[13] = env
->banked_r13
[i
];
9878 env
->spsr
= env
->banked_spsr
[i
];
9880 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9881 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9885 * Physical Interrupt Target EL Lookup Table
9887 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9889 * The below multi-dimensional table is used for looking up the target
9890 * exception level given numerous condition criteria. Specifically, the
9891 * target EL is based on SCR and HCR routing controls as well as the
9892 * currently executing EL and secure state.
9895 * target_el_table[2][2][2][2][2][4]
9896 * | | | | | +--- Current EL
9897 * | | | | +------ Non-secure(0)/Secure(1)
9898 * | | | +--------- HCR mask override
9899 * | | +------------ SCR exec state control
9900 * | +--------------- SCR mask override
9901 * +------------------ 32-bit(0)/64-bit(1) EL3
9903 * The table values are as such:
9907 * The ARM ARM target EL table includes entries indicating that an "exception
9908 * is not taken". The two cases where this is applicable are:
9909 * 1) An exception is taken from EL3 but the SCR does not have the exception
9911 * 2) An exception is taken from EL2 but the HCR does not have the exception
9913 * In these two cases, the below table contain a target of EL1. This value is
9914 * returned as it is expected that the consumer of the table data will check
9915 * for "target EL >= current EL" to ensure the exception is not taken.
9919 * BIT IRQ IMO Non-secure Secure
9920 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9922 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9923 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9924 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9925 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9926 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9927 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9928 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9929 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9930 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9931 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9932 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9933 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9934 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9935 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9936 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9937 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9938 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9942 * Determine the target EL for physical exceptions
9944 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9945 uint32_t cur_el
, bool secure
)
9947 CPUARMState
*env
= cs
->env_ptr
;
9952 /* Is the highest EL AArch64? */
9953 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9956 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9957 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9960 * Either EL2 is the highest EL (and so the EL2 register width
9961 * is given by is64); or there is no EL2 or EL3, in which case
9962 * the value of 'rw' does not affect the table lookup anyway.
9967 hcr_el2
= arm_hcr_el2_eff(env
);
9970 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9971 hcr
= hcr_el2
& HCR_IMO
;
9974 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9975 hcr
= hcr_el2
& HCR_FMO
;
9978 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9979 hcr
= hcr_el2
& HCR_AMO
;
9984 * For these purposes, TGE and AMO/IMO/FMO both force the
9985 * interrupt to EL2. Fold TGE into the bit extracted above.
9987 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9989 /* Perform a table-lookup for the target EL given the current state */
9990 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9992 assert(target_el
> 0);
9997 void arm_log_exception(CPUState
*cs
)
9999 int idx
= cs
->exception_index
;
10001 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10002 const char *exc
= NULL
;
10003 static const char * const excnames
[] = {
10004 [EXCP_UDEF
] = "Undefined Instruction",
10005 [EXCP_SWI
] = "SVC",
10006 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10007 [EXCP_DATA_ABORT
] = "Data Abort",
10008 [EXCP_IRQ
] = "IRQ",
10009 [EXCP_FIQ
] = "FIQ",
10010 [EXCP_BKPT
] = "Breakpoint",
10011 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10012 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10013 [EXCP_HVC
] = "Hypervisor Call",
10014 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10015 [EXCP_SMC
] = "Secure Monitor Call",
10016 [EXCP_VIRQ
] = "Virtual IRQ",
10017 [EXCP_VFIQ
] = "Virtual FIQ",
10018 [EXCP_SEMIHOST
] = "Semihosting call",
10019 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10020 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10021 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10022 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10023 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10024 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10025 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10026 [EXCP_VSERR
] = "Virtual SERR",
10029 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10030 exc
= excnames
[idx
];
10035 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10036 idx
, exc
, cs
->cpu_index
);
10041 * Function used to synchronize QEMU's AArch64 register set with AArch32
10042 * register set. This is necessary when switching between AArch32 and AArch64
10045 void aarch64_sync_32_to_64(CPUARMState
*env
)
10048 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10050 /* We can blanket copy R[0:7] to X[0:7] */
10051 for (i
= 0; i
< 8; i
++) {
10052 env
->xregs
[i
] = env
->regs
[i
];
10056 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10057 * Otherwise, they come from the banked user regs.
10059 if (mode
== ARM_CPU_MODE_FIQ
) {
10060 for (i
= 8; i
< 13; i
++) {
10061 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10064 for (i
= 8; i
< 13; i
++) {
10065 env
->xregs
[i
] = env
->regs
[i
];
10070 * Registers x13-x23 are the various mode SP and FP registers. Registers
10071 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10072 * from the mode banked register.
10074 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10075 env
->xregs
[13] = env
->regs
[13];
10076 env
->xregs
[14] = env
->regs
[14];
10078 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10079 /* HYP is an exception in that it is copied from r14 */
10080 if (mode
== ARM_CPU_MODE_HYP
) {
10081 env
->xregs
[14] = env
->regs
[14];
10083 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10087 if (mode
== ARM_CPU_MODE_HYP
) {
10088 env
->xregs
[15] = env
->regs
[13];
10090 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10093 if (mode
== ARM_CPU_MODE_IRQ
) {
10094 env
->xregs
[16] = env
->regs
[14];
10095 env
->xregs
[17] = env
->regs
[13];
10097 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10098 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10101 if (mode
== ARM_CPU_MODE_SVC
) {
10102 env
->xregs
[18] = env
->regs
[14];
10103 env
->xregs
[19] = env
->regs
[13];
10105 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10106 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10109 if (mode
== ARM_CPU_MODE_ABT
) {
10110 env
->xregs
[20] = env
->regs
[14];
10111 env
->xregs
[21] = env
->regs
[13];
10113 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10114 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10117 if (mode
== ARM_CPU_MODE_UND
) {
10118 env
->xregs
[22] = env
->regs
[14];
10119 env
->xregs
[23] = env
->regs
[13];
10121 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10122 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10126 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10127 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10128 * FIQ bank for r8-r14.
10130 if (mode
== ARM_CPU_MODE_FIQ
) {
10131 for (i
= 24; i
< 31; i
++) {
10132 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10135 for (i
= 24; i
< 29; i
++) {
10136 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10138 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10139 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10142 env
->pc
= env
->regs
[15];
10146 * Function used to synchronize QEMU's AArch32 register set with AArch64
10147 * register set. This is necessary when switching between AArch32 and AArch64
10150 void aarch64_sync_64_to_32(CPUARMState
*env
)
10153 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10155 /* We can blanket copy X[0:7] to R[0:7] */
10156 for (i
= 0; i
< 8; i
++) {
10157 env
->regs
[i
] = env
->xregs
[i
];
10161 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10162 * Otherwise, we copy x8-x12 into the banked user regs.
10164 if (mode
== ARM_CPU_MODE_FIQ
) {
10165 for (i
= 8; i
< 13; i
++) {
10166 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10169 for (i
= 8; i
< 13; i
++) {
10170 env
->regs
[i
] = env
->xregs
[i
];
10175 * Registers r13 & r14 depend on the current mode.
10176 * If we are in a given mode, we copy the corresponding x registers to r13
10177 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10180 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10181 env
->regs
[13] = env
->xregs
[13];
10182 env
->regs
[14] = env
->xregs
[14];
10184 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10187 * HYP is an exception in that it does not have its own banked r14 but
10188 * shares the USR r14
10190 if (mode
== ARM_CPU_MODE_HYP
) {
10191 env
->regs
[14] = env
->xregs
[14];
10193 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10197 if (mode
== ARM_CPU_MODE_HYP
) {
10198 env
->regs
[13] = env
->xregs
[15];
10200 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10203 if (mode
== ARM_CPU_MODE_IRQ
) {
10204 env
->regs
[14] = env
->xregs
[16];
10205 env
->regs
[13] = env
->xregs
[17];
10207 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10208 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10211 if (mode
== ARM_CPU_MODE_SVC
) {
10212 env
->regs
[14] = env
->xregs
[18];
10213 env
->regs
[13] = env
->xregs
[19];
10215 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10216 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10219 if (mode
== ARM_CPU_MODE_ABT
) {
10220 env
->regs
[14] = env
->xregs
[20];
10221 env
->regs
[13] = env
->xregs
[21];
10223 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10224 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10227 if (mode
== ARM_CPU_MODE_UND
) {
10228 env
->regs
[14] = env
->xregs
[22];
10229 env
->regs
[13] = env
->xregs
[23];
10231 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10232 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10236 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10237 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10238 * FIQ bank for r8-r14.
10240 if (mode
== ARM_CPU_MODE_FIQ
) {
10241 for (i
= 24; i
< 31; i
++) {
10242 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10245 for (i
= 24; i
< 29; i
++) {
10246 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10248 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10249 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10252 env
->regs
[15] = env
->pc
;
10255 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10256 uint32_t mask
, uint32_t offset
,
10261 /* Change the CPU state so as to actually take the exception. */
10262 switch_mode(env
, new_mode
);
10265 * For exceptions taken to AArch32 we must clear the SS bit in both
10266 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10268 env
->pstate
&= ~PSTATE_SS
;
10269 env
->spsr
= cpsr_read(env
);
10270 /* Clear IT bits. */
10271 env
->condexec_bits
= 0;
10272 /* Switch to the new mode, and to the correct instruction set. */
10273 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10275 /* This must be after mode switching. */
10276 new_el
= arm_current_el(env
);
10278 /* Set new mode endianness */
10279 env
->uncached_cpsr
&= ~CPSR_E
;
10280 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10281 env
->uncached_cpsr
|= CPSR_E
;
10283 /* J and IL must always be cleared for exception entry */
10284 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10287 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10288 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10289 env
->uncached_cpsr
|= CPSR_SSBS
;
10291 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10295 if (new_mode
== ARM_CPU_MODE_HYP
) {
10296 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10297 env
->elr_el
[2] = env
->regs
[15];
10299 /* CPSR.PAN is normally preserved preserved unless... */
10300 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10303 if (!arm_is_secure_below_el3(env
)) {
10304 /* ... the target is EL3, from non-secure state. */
10305 env
->uncached_cpsr
&= ~CPSR_PAN
;
10308 /* ... the target is EL3, from secure state ... */
10311 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10312 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10313 env
->uncached_cpsr
|= CPSR_PAN
;
10319 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10320 * and we should just guard the thumb mode on V4
10322 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10324 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10326 env
->regs
[14] = env
->regs
[15] + offset
;
10328 env
->regs
[15] = newpc
;
10329 arm_rebuild_hflags(env
);
10332 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10335 * Handle exception entry to Hyp mode; this is sufficiently
10336 * different to entry to other AArch32 modes that we handle it
10339 * The vector table entry used is always the 0x14 Hyp mode entry point,
10340 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10341 * The offset applied to the preferred return address is always zero
10342 * (see DDI0487C.a section G1.12.3).
10343 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10345 uint32_t addr
, mask
;
10346 ARMCPU
*cpu
= ARM_CPU(cs
);
10347 CPUARMState
*env
= &cpu
->env
;
10349 switch (cs
->exception_index
) {
10357 /* Fall through to prefetch abort. */
10358 case EXCP_PREFETCH_ABORT
:
10359 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10360 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10361 (uint32_t)env
->exception
.vaddress
);
10364 case EXCP_DATA_ABORT
:
10365 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10366 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10367 (uint32_t)env
->exception
.vaddress
);
10379 case EXCP_HYP_TRAP
:
10383 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10386 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10387 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10389 * QEMU syndrome values are v8-style. v7 has the IL bit
10390 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10391 * If this is a v7 CPU, squash the IL bit in those cases.
10393 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10394 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10395 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10396 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10397 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10400 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10403 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10408 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10411 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10414 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10418 addr
+= env
->cp15
.hvbar
;
10420 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10423 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10425 ARMCPU
*cpu
= ARM_CPU(cs
);
10426 CPUARMState
*env
= &cpu
->env
;
10433 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10434 switch (syn_get_ec(env
->exception
.syndrome
)) {
10435 case EC_BREAKPOINT
:
10436 case EC_BREAKPOINT_SAME_EL
:
10439 case EC_WATCHPOINT
:
10440 case EC_WATCHPOINT_SAME_EL
:
10446 case EC_VECTORCATCH
:
10455 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10458 if (env
->exception
.target_el
== 2) {
10459 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10463 switch (cs
->exception_index
) {
10465 new_mode
= ARM_CPU_MODE_UND
;
10475 new_mode
= ARM_CPU_MODE_SVC
;
10478 /* The PC already points to the next instruction. */
10482 /* Fall through to prefetch abort. */
10483 case EXCP_PREFETCH_ABORT
:
10484 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10485 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10486 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10487 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10488 new_mode
= ARM_CPU_MODE_ABT
;
10490 mask
= CPSR_A
| CPSR_I
;
10493 case EXCP_DATA_ABORT
:
10494 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10495 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10496 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10497 env
->exception
.fsr
,
10498 (uint32_t)env
->exception
.vaddress
);
10499 new_mode
= ARM_CPU_MODE_ABT
;
10501 mask
= CPSR_A
| CPSR_I
;
10505 new_mode
= ARM_CPU_MODE_IRQ
;
10507 /* Disable IRQ and imprecise data aborts. */
10508 mask
= CPSR_A
| CPSR_I
;
10510 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10511 /* IRQ routed to monitor mode */
10512 new_mode
= ARM_CPU_MODE_MON
;
10517 new_mode
= ARM_CPU_MODE_FIQ
;
10519 /* Disable FIQ, IRQ and imprecise data aborts. */
10520 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10521 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10522 /* FIQ routed to monitor mode */
10523 new_mode
= ARM_CPU_MODE_MON
;
10528 new_mode
= ARM_CPU_MODE_IRQ
;
10530 /* Disable IRQ and imprecise data aborts. */
10531 mask
= CPSR_A
| CPSR_I
;
10535 new_mode
= ARM_CPU_MODE_FIQ
;
10537 /* Disable FIQ, IRQ and imprecise data aborts. */
10538 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10544 * Note that this is reported as a data abort, but the DFAR
10545 * has an UNKNOWN value. Construct the SError syndrome from
10546 * AET and ExT fields.
10548 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10550 if (extended_addresses_enabled(env
)) {
10551 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10553 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10555 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10556 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10557 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10558 env
->exception
.fsr
);
10560 new_mode
= ARM_CPU_MODE_ABT
;
10562 mask
= CPSR_A
| CPSR_I
;
10567 new_mode
= ARM_CPU_MODE_MON
;
10569 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10573 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10574 return; /* Never happens. Keep compiler happy. */
10577 if (new_mode
== ARM_CPU_MODE_MON
) {
10578 addr
+= env
->cp15
.mvbar
;
10579 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10580 /* High vectors. When enabled, base address cannot be remapped. */
10581 addr
+= 0xffff0000;
10584 * ARM v7 architectures provide a vector base address register to remap
10585 * the interrupt vector table.
10586 * This register is only followed in non-monitor mode, and is banked.
10587 * Note: only bits 31:5 are valid.
10589 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10592 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10593 env
->cp15
.scr_el3
&= ~SCR_NS
;
10596 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10599 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10602 * Return the register number of the AArch64 view of the AArch32
10603 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10604 * be that of the AArch32 mode the exception came from.
10606 int mode
= env
->uncached_cpsr
& CPSR_M
;
10608 switch (aarch32_reg
) {
10610 return aarch32_reg
;
10612 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10615 case ARM_CPU_MODE_USR
:
10616 case ARM_CPU_MODE_SYS
:
10618 case ARM_CPU_MODE_HYP
:
10620 case ARM_CPU_MODE_IRQ
:
10622 case ARM_CPU_MODE_SVC
:
10624 case ARM_CPU_MODE_ABT
:
10626 case ARM_CPU_MODE_UND
:
10628 case ARM_CPU_MODE_FIQ
:
10631 g_assert_not_reached();
10635 case ARM_CPU_MODE_USR
:
10636 case ARM_CPU_MODE_SYS
:
10637 case ARM_CPU_MODE_HYP
:
10639 case ARM_CPU_MODE_IRQ
:
10641 case ARM_CPU_MODE_SVC
:
10643 case ARM_CPU_MODE_ABT
:
10645 case ARM_CPU_MODE_UND
:
10647 case ARM_CPU_MODE_FIQ
:
10650 g_assert_not_reached();
10655 g_assert_not_reached();
10659 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10661 uint32_t ret
= cpsr_read(env
);
10663 /* Move DIT to the correct location for SPSR_ELx */
10664 if (ret
& CPSR_DIT
) {
10668 /* Merge PSTATE.SS into SPSR_ELx */
10669 ret
|= env
->pstate
& PSTATE_SS
;
10674 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
10676 /* Return true if this syndrome value is a synchronous external abort */
10677 switch (syn_get_ec(syndrome
)) {
10679 case EC_INSNABORT_SAME_EL
:
10681 case EC_DATAABORT_SAME_EL
:
10682 /* Look at fault status code for all the synchronous ext abort cases */
10683 switch (syndrome
& 0x3f) {
10699 /* Handle exception entry to a target EL which is using AArch64 */
10700 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10702 ARMCPU
*cpu
= ARM_CPU(cs
);
10703 CPUARMState
*env
= &cpu
->env
;
10704 unsigned int new_el
= env
->exception
.target_el
;
10705 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10706 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10707 unsigned int old_mode
;
10708 unsigned int cur_el
= arm_current_el(env
);
10712 * Note that new_el can never be 0. If cur_el is 0, then
10713 * el0_a64 is is_a64(), else el0_a64 is ignored.
10715 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10717 if (cur_el
< new_el
) {
10719 * Entry vector offset depends on whether the implemented EL
10720 * immediately lower than the target level is using AArch32 or AArch64
10727 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10730 hcr
= arm_hcr_el2_eff(env
);
10731 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10732 is_aa64
= (hcr
& HCR_RW
) != 0;
10737 is_aa64
= is_a64(env
);
10740 g_assert_not_reached();
10748 } else if (pstate_read(env
) & PSTATE_SP
) {
10752 switch (cs
->exception_index
) {
10753 case EXCP_PREFETCH_ABORT
:
10754 case EXCP_DATA_ABORT
:
10756 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
10757 * to be taken to the SError vector entrypoint.
10759 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
10760 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
10763 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10764 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10765 env
->cp15
.far_el
[new_el
]);
10771 case EXCP_HYP_TRAP
:
10773 switch (syn_get_ec(env
->exception
.syndrome
)) {
10774 case EC_ADVSIMDFPACCESSTRAP
:
10776 * QEMU internal FP/SIMD syndromes from AArch32 include the
10777 * TA and coproc fields which are only exposed if the exception
10778 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10779 * AArch64 format syndrome.
10781 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10783 case EC_CP14RTTRAP
:
10784 case EC_CP15RTTRAP
:
10785 case EC_CP14DTTRAP
:
10787 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10788 * the raw register field from the insn; when taking this to
10789 * AArch64 we must convert it to the AArch64 view of the register
10790 * number. Notice that we read a 4-bit AArch32 register number and
10791 * write back a 5-bit AArch64 one.
10793 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10794 rt
= aarch64_regnum(env
, rt
);
10795 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10798 case EC_CP15RRTTRAP
:
10799 case EC_CP14RRTTRAP
:
10800 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10801 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10802 rt
= aarch64_regnum(env
, rt
);
10803 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10805 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10806 rt
= aarch64_regnum(env
, rt
);
10807 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10811 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10823 /* Construct the SError syndrome from IDS and ISS fields. */
10824 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10825 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10828 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10832 old_mode
= pstate_read(env
);
10833 aarch64_save_sp(env
, arm_current_el(env
));
10834 env
->elr_el
[new_el
] = env
->pc
;
10836 old_mode
= cpsr_read_for_spsr_elx(env
);
10837 env
->elr_el
[new_el
] = env
->regs
[15];
10839 aarch64_sync_32_to_64(env
);
10841 env
->condexec_bits
= 0;
10843 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10845 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10846 env
->elr_el
[new_el
]);
10848 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10849 /* The value of PSTATE.PAN is normally preserved, except when ... */
10850 new_mode
|= old_mode
& PSTATE_PAN
;
10853 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10854 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10855 != (HCR_E2H
| HCR_TGE
)) {
10860 /* ... the target is EL1 ... */
10861 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10862 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10863 new_mode
|= PSTATE_PAN
;
10868 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10869 new_mode
|= PSTATE_TCO
;
10872 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10873 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10874 new_mode
|= PSTATE_SSBS
;
10876 new_mode
&= ~PSTATE_SSBS
;
10880 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10881 env
->aarch64
= true;
10882 aarch64_restore_sp(env
, new_el
);
10883 helper_rebuild_hflags_a64(env
, new_el
);
10887 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10888 new_el
, env
->pc
, pstate_read(env
));
10892 * Do semihosting call and set the appropriate return value. All the
10893 * permission and validity checks have been done at translate time.
10895 * We only see semihosting exceptions in TCG only as they are not
10896 * trapped to the hypervisor in KVM.
10899 static void handle_semihosting(CPUState
*cs
)
10901 ARMCPU
*cpu
= ARM_CPU(cs
);
10902 CPUARMState
*env
= &cpu
->env
;
10905 qemu_log_mask(CPU_LOG_INT
,
10906 "...handling as semihosting call 0x%" PRIx64
"\n",
10908 do_common_semihosting(cs
);
10911 qemu_log_mask(CPU_LOG_INT
,
10912 "...handling as semihosting call 0x%x\n",
10914 do_common_semihosting(cs
);
10915 env
->regs
[15] += env
->thumb
? 2 : 4;
10921 * Handle a CPU exception for A and R profile CPUs.
10922 * Do any appropriate logging, handle PSCI calls, and then hand off
10923 * to the AArch64-entry or AArch32-entry function depending on the
10924 * target exception level's register width.
10926 * Note: this is used for both TCG (as the do_interrupt tcg op),
10927 * and KVM to re-inject guest debug exceptions, and to
10928 * inject a Synchronous-External-Abort.
10930 void arm_cpu_do_interrupt(CPUState
*cs
)
10932 ARMCPU
*cpu
= ARM_CPU(cs
);
10933 CPUARMState
*env
= &cpu
->env
;
10934 unsigned int new_el
= env
->exception
.target_el
;
10936 assert(!arm_feature(env
, ARM_FEATURE_M
));
10938 arm_log_exception(cs
);
10939 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10941 if (qemu_loglevel_mask(CPU_LOG_INT
)
10942 && !excp_is_internal(cs
->exception_index
)) {
10943 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10944 syn_get_ec(env
->exception
.syndrome
),
10945 env
->exception
.syndrome
);
10948 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10949 arm_handle_psci_call(cpu
);
10950 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10955 * Semihosting semantics depend on the register width of the code
10956 * that caused the exception, not the target exception level, so
10957 * must be handled here.
10960 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10961 handle_semihosting(cs
);
10967 * Hooks may change global state so BQL should be held, also the
10968 * BQL needs to be held for any modification of
10969 * cs->interrupt_request.
10971 g_assert(qemu_mutex_iothread_locked());
10973 arm_call_pre_el_change_hook(cpu
);
10975 assert(!excp_is_internal(cs
->exception_index
));
10976 if (arm_el_is_aa64(env
, new_el
)) {
10977 arm_cpu_do_interrupt_aarch64(cs
);
10979 arm_cpu_do_interrupt_aarch32(cs
);
10982 arm_call_el_change_hook(cpu
);
10984 if (!kvm_enabled()) {
10985 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10988 #endif /* !CONFIG_USER_ONLY */
10990 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10992 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10994 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10995 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
10997 return env
->cp15
.sctlr_el
[el
];
11000 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11002 if (regime_has_2_ranges(mmu_idx
)) {
11003 return extract64(tcr
, 37, 2);
11004 } else if (regime_is_stage2(mmu_idx
)) {
11005 return 0; /* VTCR_EL2 */
11007 /* Replicate the single TBI bit so we always have 2 bits. */
11008 return extract32(tcr
, 20, 1) * 3;
11012 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11014 if (regime_has_2_ranges(mmu_idx
)) {
11015 return extract64(tcr
, 51, 2);
11016 } else if (regime_is_stage2(mmu_idx
)) {
11017 return 0; /* VTCR_EL2 */
11019 /* Replicate the single TBID bit so we always have 2 bits. */
11020 return extract32(tcr
, 29, 1) * 3;
11024 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11026 if (regime_has_2_ranges(mmu_idx
)) {
11027 return extract64(tcr
, 57, 2);
11029 /* Replicate the single TCMA bit so we always have 2 bits. */
11030 return extract32(tcr
, 30, 1) * 3;
11034 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11044 return GranInvalid
;
11048 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11058 return GranInvalid
;
11062 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11064 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11065 : cpu_isar_feature(aa64_tgran4
, cpu
);
11068 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11070 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11071 : cpu_isar_feature(aa64_tgran16
, cpu
);
11074 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11076 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11077 : cpu_isar_feature(aa64_tgran64
, cpu
);
11080 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11085 if (have4k(cpu
, stage2
)) {
11090 if (have16k(cpu
, stage2
)) {
11095 if (have64k(cpu
, stage2
)) {
11103 * If the guest selects a granule size that isn't implemented,
11104 * the architecture requires that we behave as if it selected one
11105 * that is (with an IMPDEF choice of which one to pick). We choose
11106 * to implement the smallest supported granule size.
11108 if (have4k(cpu
, stage2
)) {
11111 if (have16k(cpu
, stage2
)) {
11114 assert(have64k(cpu
, stage2
));
11118 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11119 ARMMMUIdx mmu_idx
, bool data
)
11121 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11122 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11123 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11124 ARMGranuleSize gran
;
11125 ARMCPU
*cpu
= env_archcpu(env
);
11126 bool stage2
= regime_is_stage2(mmu_idx
);
11128 if (!regime_has_2_ranges(mmu_idx
)) {
11130 tsz
= extract32(tcr
, 0, 6);
11131 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11136 hpd
= extract32(tcr
, 24, 1);
11139 sh
= extract32(tcr
, 12, 2);
11140 ps
= extract32(tcr
, 16, 3);
11141 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11142 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11143 ds
= extract64(tcr
, 32, 1);
11148 * Bit 55 is always between the two regions, and is canonical for
11149 * determining if address tagging is enabled.
11151 select
= extract64(va
, 55, 1);
11153 tsz
= extract32(tcr
, 0, 6);
11154 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11155 epd
= extract32(tcr
, 7, 1);
11156 sh
= extract32(tcr
, 12, 2);
11157 hpd
= extract64(tcr
, 41, 1);
11158 e0pd
= extract64(tcr
, 55, 1);
11160 tsz
= extract32(tcr
, 16, 6);
11161 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11162 epd
= extract32(tcr
, 23, 1);
11163 sh
= extract32(tcr
, 28, 2);
11164 hpd
= extract64(tcr
, 42, 1);
11165 e0pd
= extract64(tcr
, 56, 1);
11167 ps
= extract64(tcr
, 32, 3);
11168 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11169 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11170 ds
= extract64(tcr
, 59, 1);
11172 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11173 regime_is_user(env
, mmu_idx
)) {
11178 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11180 if (cpu_isar_feature(aa64_st
, cpu
)) {
11181 max_tsz
= 48 - (gran
== Gran64K
);
11187 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11188 * adjust the effective value of DS, as documented.
11191 if (gran
== Gran64K
) {
11192 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11197 if (regime_is_stage2(mmu_idx
)) {
11198 if (gran
== Gran16K
) {
11199 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11201 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11204 if (gran
== Gran16K
) {
11205 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11207 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11215 if (tsz
> max_tsz
) {
11218 } else if (tsz
< min_tsz
) {
11225 /* Present TBI as a composite with TBID. */
11226 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11228 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11230 tbi
= (tbi
>> select
) & 1;
11232 return (ARMVAParameters
) {
11240 .tsz_oob
= tsz_oob
,
11249 * Note that signed overflow is undefined in C. The following routines are
11250 * careful to use unsigned types where modulo arithmetic is required.
11251 * Failure to do so _will_ break on newer gcc.
11254 /* Signed saturating arithmetic. */
11256 /* Perform 16-bit signed saturating addition. */
11257 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11262 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11272 /* Perform 8-bit signed saturating addition. */
11273 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11278 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11288 /* Perform 16-bit signed saturating subtraction. */
11289 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11294 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11304 /* Perform 8-bit signed saturating subtraction. */
11305 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11310 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11320 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11321 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11322 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11323 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11326 #include "op_addsub.h"
11328 /* Unsigned saturating arithmetic. */
11329 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11339 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11348 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11358 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11367 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11368 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11369 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11370 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11373 #include "op_addsub.h"
11375 /* Signed modulo arithmetic. */
11376 #define SARITH16(a, b, n, op) do { \
11378 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11379 RESULT(sum, n, 16); \
11381 ge |= 3 << (n * 2); \
11384 #define SARITH8(a, b, n, op) do { \
11386 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11387 RESULT(sum, n, 8); \
11393 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11394 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11395 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11396 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11400 #include "op_addsub.h"
11402 /* Unsigned modulo arithmetic. */
11403 #define ADD16(a, b, n) do { \
11405 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11406 RESULT(sum, n, 16); \
11407 if ((sum >> 16) == 1) \
11408 ge |= 3 << (n * 2); \
11411 #define ADD8(a, b, n) do { \
11413 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11414 RESULT(sum, n, 8); \
11415 if ((sum >> 8) == 1) \
11419 #define SUB16(a, b, n) do { \
11421 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11422 RESULT(sum, n, 16); \
11423 if ((sum >> 16) == 0) \
11424 ge |= 3 << (n * 2); \
11427 #define SUB8(a, b, n) do { \
11429 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11430 RESULT(sum, n, 8); \
11431 if ((sum >> 8) == 0) \
11438 #include "op_addsub.h"
11440 /* Halved signed arithmetic. */
11441 #define ADD16(a, b, n) \
11442 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11443 #define SUB16(a, b, n) \
11444 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11445 #define ADD8(a, b, n) \
11446 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11447 #define SUB8(a, b, n) \
11448 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11451 #include "op_addsub.h"
11453 /* Halved unsigned arithmetic. */
11454 #define ADD16(a, b, n) \
11455 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11456 #define SUB16(a, b, n) \
11457 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11458 #define ADD8(a, b, n) \
11459 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11460 #define SUB8(a, b, n) \
11461 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11464 #include "op_addsub.h"
11466 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11475 /* Unsigned sum of absolute byte differences. */
11476 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11479 sum
= do_usad(a
, b
);
11480 sum
+= do_usad(a
>> 8, b
>> 8);
11481 sum
+= do_usad(a
>> 16, b
>> 16);
11482 sum
+= do_usad(a
>> 24, b
>> 24);
11486 /* For ARMv6 SEL instruction. */
11487 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11502 mask
|= 0xff000000;
11504 return (a
& mask
) | (b
& ~mask
);
11509 * The upper bytes of val (above the number specified by 'bytes') must have
11510 * been zeroed out by the caller.
11512 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11516 stl_le_p(buf
, val
);
11518 /* zlib crc32 converts the accumulator and output to one's complement. */
11519 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11522 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11526 stl_le_p(buf
, val
);
11528 /* Linux crc32c converts the output to one's complement. */
11529 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11533 * Return the exception level to which FP-disabled exceptions should
11534 * be taken, or 0 if FP is enabled.
11536 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11538 #ifndef CONFIG_USER_ONLY
11542 * CPACR and the CPTR registers don't exist before v6, so FP is
11543 * always accessible
11545 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11549 if (arm_feature(env
, ARM_FEATURE_M
)) {
11550 /* CPACR can cause a NOCP UsageFault taken to current security state */
11551 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11555 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11556 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11557 /* FP insns cause a NOCP UsageFault taken to Secure */
11565 hcr_el2
= arm_hcr_el2_eff(env
);
11568 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11569 * 0, 2 : trap EL0 and EL1/PL1 accesses
11570 * 1 : trap only EL0 accesses
11571 * 3 : trap no accesses
11572 * This register is ignored if E2H+TGE are both set.
11574 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11575 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
11585 /* Trap from Secure PL0 or PL1 to Secure PL1. */
11586 if (!arm_el_is_aa64(env
, 3)
11587 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
11598 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11599 * to control non-secure access to the FPU. It doesn't have any
11600 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11602 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11603 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11604 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11605 /* FP insns act as UNDEF */
11606 return cur_el
== 2 ? 2 : 1;
11611 * CPTR_EL2 is present in v7VE or v8, and changes format
11612 * with HCR_EL2.E2H (regardless of TGE).
11615 if (hcr_el2
& HCR_E2H
) {
11616 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
11618 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
11626 } else if (arm_is_el2_enabled(env
)) {
11627 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
11633 /* CPTR_EL3 : present in v8 */
11634 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
11635 /* Trap all FP ops to EL3 */
11642 /* Return the exception level we're running at if this is our mmu_idx */
11643 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
11645 if (mmu_idx
& ARM_MMU_IDX_M
) {
11646 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
11650 case ARMMMUIdx_E10_0
:
11651 case ARMMMUIdx_E20_0
:
11653 case ARMMMUIdx_E10_1
:
11654 case ARMMMUIdx_E10_1_PAN
:
11657 case ARMMMUIdx_E20_2
:
11658 case ARMMMUIdx_E20_2_PAN
:
11663 g_assert_not_reached();
11668 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11670 g_assert_not_reached();
11674 static bool arm_pan_enabled(CPUARMState
*env
)
11677 return env
->pstate
& PSTATE_PAN
;
11679 return env
->uncached_cpsr
& CPSR_PAN
;
11683 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11688 if (arm_feature(env
, ARM_FEATURE_M
)) {
11689 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11692 /* See ARM pseudo-function ELIsInHost. */
11695 hcr
= arm_hcr_el2_eff(env
);
11696 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
11697 idx
= ARMMMUIdx_E20_0
;
11699 idx
= ARMMMUIdx_E10_0
;
11703 if (arm_pan_enabled(env
)) {
11704 idx
= ARMMMUIdx_E10_1_PAN
;
11706 idx
= ARMMMUIdx_E10_1
;
11710 /* Note that TGE does not apply at EL2. */
11711 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
11712 if (arm_pan_enabled(env
)) {
11713 idx
= ARMMMUIdx_E20_2_PAN
;
11715 idx
= ARMMMUIdx_E20_2
;
11718 idx
= ARMMMUIdx_E2
;
11722 return ARMMMUIdx_E3
;
11724 g_assert_not_reached();
11730 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11732 return arm_mmu_idx_el(env
, arm_current_el(env
));
11735 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11737 CPUARMTBFlags flags
)
11739 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
11740 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
11742 if (arm_singlestep_active(env
)) {
11743 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
11749 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11751 CPUARMTBFlags flags
)
11753 bool sctlr_b
= arm_sctlr_b(env
);
11756 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
11758 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11759 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11761 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
11763 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11766 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11769 CPUARMTBFlags flags
= {};
11770 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
11772 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
11773 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
11774 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11777 if (arm_v7m_is_handler_mode(env
)) {
11778 DP_TBFLAG_M32(flags
, HANDLER
, 1);
11782 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11783 * is suppressing them because the requested execution priority
11786 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11787 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11788 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11789 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
11792 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && env
->v7m
.secure
) {
11793 DP_TBFLAG_M32(flags
, SECURE
, 1);
11796 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11799 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11802 CPUARMTBFlags flags
= {};
11803 int el
= arm_current_el(env
);
11805 if (arm_sctlr(env
, el
) & SCTLR_A
) {
11806 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11809 if (arm_el_is_aa64(env
, 1)) {
11810 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11813 if (el
< 2 && env
->cp15
.hstr_el2
&& arm_is_el2_enabled(env
) &&
11814 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11815 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
11818 if (arm_fgt_active(env
, el
)) {
11819 DP_TBFLAG_ANY(flags
, FGT_ACTIVE
, 1);
11822 if (env
->uncached_cpsr
& CPSR_IL
) {
11823 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11827 * The SME exception we are testing for is raised via
11828 * AArch64.CheckFPAdvSIMDEnabled(), as called from
11829 * AArch32.CheckAdvSIMDOrFPEnabled().
11832 && FIELD_EX64(env
->svcr
, SVCR
, SM
)
11833 && (!arm_is_el2_enabled(env
)
11834 || (arm_el_is_aa64(env
, 2) && !(env
->cp15
.hcr_el2
& HCR_TGE
)))
11835 && arm_el_is_aa64(env
, 1)
11836 && !sme_fa64(env
, el
)) {
11837 DP_TBFLAG_A32(flags
, SME_TRAP_NONSTREAMING
, 1);
11840 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11843 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11846 CPUARMTBFlags flags
= {};
11847 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11848 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11852 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
11854 /* Get control bits for tagged addresses. */
11855 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11856 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11858 DP_TBFLAG_A64(flags
, TBII
, tbii
);
11859 DP_TBFLAG_A64(flags
, TBID
, tbid
);
11861 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11862 int sve_el
= sve_exception_el(env
, el
);
11865 * If either FP or SVE are disabled, translator does not need len.
11866 * If SVE EL > FP EL, FP exception has precedence, and translator
11867 * does not need SVE EL. Save potential re-translations by forcing
11868 * the unneeded data to zero.
11871 if (sve_el
> fp_el
) {
11874 } else if (sve_el
== 0) {
11875 DP_TBFLAG_A64(flags
, VL
, sve_vqm1_for_el(env
, el
));
11877 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
11879 if (cpu_isar_feature(aa64_sme
, env_archcpu(env
))) {
11880 int sme_el
= sme_exception_el(env
, el
);
11881 bool sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
11883 DP_TBFLAG_A64(flags
, SMEEXC_EL
, sme_el
);
11885 /* Similarly, do not compute SVL if SME is disabled. */
11886 int svl
= sve_vqm1_for_el_sm(env
, el
, true);
11887 DP_TBFLAG_A64(flags
, SVL
, svl
);
11889 /* If SVE is disabled, we will not have set VL above. */
11890 DP_TBFLAG_A64(flags
, VL
, svl
);
11894 DP_TBFLAG_A64(flags
, PSTATE_SM
, 1);
11895 DP_TBFLAG_A64(flags
, SME_TRAP_NONSTREAMING
, !sme_fa64(env
, el
));
11897 DP_TBFLAG_A64(flags
, PSTATE_ZA
, FIELD_EX64(env
->svcr
, SVCR
, ZA
));
11900 sctlr
= regime_sctlr(env
, stage1
);
11902 if (sctlr
& SCTLR_A
) {
11903 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11906 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
11907 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11910 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
11912 * In order to save space in flags, we record only whether
11913 * pauth is "inactive", meaning all insns are implemented as
11914 * a nop, or "active" when some action must be performed.
11915 * The decision of which action to take is left to a helper.
11917 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
11918 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
11922 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11923 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
11924 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
11925 DP_TBFLAG_A64(flags
, BT
, 1);
11929 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
11930 if (!(env
->pstate
& PSTATE_UAO
)) {
11932 case ARMMMUIdx_E10_1
:
11933 case ARMMMUIdx_E10_1_PAN
:
11934 /* TODO: ARMv8.3-NV */
11935 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11937 case ARMMMUIdx_E20_2
:
11938 case ARMMMUIdx_E20_2_PAN
:
11940 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
11941 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
11943 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
11944 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11952 if (env
->pstate
& PSTATE_IL
) {
11953 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11956 if (arm_fgt_active(env
, el
)) {
11957 DP_TBFLAG_ANY(flags
, FGT_ACTIVE
, 1);
11960 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
11962 * Set MTE_ACTIVE if any access may be Checked, and leave clear
11963 * if all accesses must be Unchecked:
11964 * 1) If no TBI, then there are no tags in the address to check,
11965 * 2) If Tag Check Override, then all accesses are Unchecked,
11966 * 3) If Tag Check Fail == 0, then Checked access have no effect,
11967 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
11969 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
11970 DP_TBFLAG_A64(flags
, ATA
, 1);
11972 && !(env
->pstate
& PSTATE_TCO
)
11973 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
11974 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
11977 /* And again for unprivileged accesses, if required. */
11978 if (EX_TBFLAG_A64(flags
, UNPRIV
)
11980 && !(env
->pstate
& PSTATE_TCO
)
11981 && (sctlr
& SCTLR_TCF0
)
11982 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
11983 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
11985 /* Cache TCMA as well as TBI. */
11986 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
11989 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11992 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
11994 int el
= arm_current_el(env
);
11995 int fp_el
= fp_exception_el(env
, el
);
11996 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11999 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12000 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
12001 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12003 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12007 void arm_rebuild_hflags(CPUARMState
*env
)
12009 env
->hflags
= rebuild_hflags_internal(env
);
12013 * If we have triggered a EL state change we can't rely on the
12014 * translator having passed it to us, we need to recompute.
12016 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
12018 int el
= arm_current_el(env
);
12019 int fp_el
= fp_exception_el(env
, el
);
12020 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12022 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12025 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
12027 int fp_el
= fp_exception_el(env
, el
);
12028 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12030 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12034 * If we have triggered a EL state change we can't rely on the
12035 * translator having passed it to us, we need to recompute.
12037 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
12039 int el
= arm_current_el(env
);
12040 int fp_el
= fp_exception_el(env
, el
);
12041 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12042 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12045 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
12047 int fp_el
= fp_exception_el(env
, el
);
12048 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12050 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12053 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
12055 int fp_el
= fp_exception_el(env
, el
);
12056 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12058 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12061 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
12063 #ifdef CONFIG_DEBUG_TCG
12064 CPUARMTBFlags c
= env
->hflags
;
12065 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
12067 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
12068 fprintf(stderr
, "TCG hflags mismatch "
12069 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
12070 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
12071 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
12077 static bool mve_no_pred(CPUARMState
*env
)
12080 * Return true if there is definitely no predication of MVE
12081 * instructions by VPR or LTPSIZE. (Returning false even if there
12082 * isn't any predication is OK; generated code will just be
12084 * If the CPU does not implement MVE then this TB flag is always 0.
12086 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12087 * logic in gen_update_fp_context() needs to be updated to match.
12089 * We do not include the effect of the ECI bits here -- they are
12090 * tracked in other TB flags. This simplifies the logic for
12091 * "when did we emit code that changes the MVE_NO_PRED TB flag
12092 * and thus need to end the TB?".
12094 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12097 if (env
->v7m
.vpr
) {
12100 if (env
->v7m
.ltpsize
< 4) {
12106 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12107 target_ulong
*cs_base
, uint32_t *pflags
)
12109 CPUARMTBFlags flags
;
12111 assert_hflags_rebuild_correctly(env
);
12112 flags
= env
->hflags
;
12114 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12116 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12117 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12120 *pc
= env
->regs
[15];
12122 if (arm_feature(env
, ARM_FEATURE_M
)) {
12123 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12124 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12125 != env
->v7m
.secure
) {
12126 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12129 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12130 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12131 (env
->v7m
.secure
&&
12132 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12134 * ASPEN is set, but FPCA/SFPA indicate that there is no
12135 * active FP context; we must create a new FP context before
12136 * executing any FP insn.
12138 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12141 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12142 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12143 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12146 if (mve_no_pred(env
)) {
12147 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12151 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12152 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12154 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12155 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12157 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12158 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12160 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12161 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12165 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12166 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12170 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12171 * states defined in the ARM ARM for software singlestep:
12172 * SS_ACTIVE PSTATE.SS State
12173 * 0 x Inactive (the TB flag for SS is always 0)
12174 * 1 0 Active-pending
12175 * 1 1 Active-not-pending
12176 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12178 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12179 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12182 *pflags
= flags
.flags
;
12183 *cs_base
= flags
.flags2
;
12186 #ifdef TARGET_AARCH64
12188 * The manual says that when SVE is enabled and VQ is widened the
12189 * implementation is allowed to zero the previously inaccessible
12190 * portion of the registers. The corollary to that is that when
12191 * SVE is enabled and VQ is narrowed we are also allowed to zero
12192 * the now inaccessible portion of the registers.
12194 * The intent of this is that no predicate bit beyond VQ is ever set.
12195 * Which means that some operations on predicate registers themselves
12196 * may operate on full uint64_t or even unrolled across the maximum
12197 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12198 * may well be cheaper than conditionals to restrict the operation
12199 * to the relevant portion of a uint16_t[16].
12201 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12206 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12207 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12209 /* Zap the high bits of the zregs. */
12210 for (i
= 0; i
< 32; i
++) {
12211 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12214 /* Zap the high bits of the pregs and ffr. */
12217 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12219 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12220 for (i
= 0; i
< 17; ++i
) {
12221 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12227 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12232 exc_el
= sme_exception_el(env
, el
);
12234 exc_el
= sve_exception_el(env
, el
);
12237 return 0; /* disabled */
12239 return sve_vqm1_for_el_sm(env
, el
, sm
);
12243 * Notice a change in SVE vector size when changing EL.
12245 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12246 int new_el
, bool el0_a64
)
12248 ARMCPU
*cpu
= env_archcpu(env
);
12249 int old_len
, new_len
;
12250 bool old_a64
, new_a64
, sm
;
12252 /* Nothing to do if no SVE. */
12253 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12257 /* Nothing to do if FP is disabled in either EL. */
12258 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12262 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12263 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12266 * Both AArch64.TakeException and AArch64.ExceptionReturn
12267 * invoke ResetSVEState when taking an exception from, or
12268 * returning to, AArch32 state when PSTATE.SM is enabled.
12270 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12271 if (old_a64
!= new_a64
&& sm
) {
12272 arm_reset_sve_state(env
);
12277 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12278 * at ELx, or not available because the EL is in AArch32 state, then
12279 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12280 * has an effective value of 0".
12282 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12283 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12284 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12285 * we already have the correct register contents when encountering the
12286 * vq0->vq0 transition between EL0->EL1.
12288 old_len
= new_len
= 0;
12290 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12293 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12296 /* When changing vector length, clear inaccessible state. */
12297 if (new_len
< old_len
) {
12298 aarch64_sve_narrow_vq(env
, new_len
+ 1);