4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
16 #include "qemu/timer.h"
17 #include "qemu/bitops.h"
18 #include "qemu/crc32c.h"
19 #include "qemu/qemu-print.h"
20 #include "exec/exec-all.h"
21 #include <zlib.h> /* For crc32 */
23 #include "sysemu/cpu-timers.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/tcg.h"
26 #include "qapi/qapi-commands-machine-target.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
267 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
269 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
270 const ARMCPRegInfo
*ri
,
273 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
274 arm_is_secure_below_el3(env
)) {
275 return CP_ACCESS_TRAP_UNCATEGORIZED
;
281 * Some secure-only AArch32 registers trap to EL3 if used from
282 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
283 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
284 * We assume that the .access field is set to PL1_RW.
286 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
287 const ARMCPRegInfo
*ri
,
290 if (arm_current_el(env
) == 3) {
293 if (arm_is_secure_below_el3(env
)) {
294 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
295 return CP_ACCESS_TRAP_EL2
;
297 return CP_ACCESS_TRAP_EL3
;
299 /* This will be EL1 NS and EL2 NS, which just UNDEF */
300 return CP_ACCESS_TRAP_UNCATEGORIZED
;
304 * Check for traps to performance monitor registers, which are controlled
305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
307 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
310 int el
= arm_current_el(env
);
311 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
313 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
314 return CP_ACCESS_TRAP_EL2
;
316 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
317 return CP_ACCESS_TRAP_EL3
;
322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
323 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
326 if (arm_current_el(env
) == 1) {
327 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
328 if (arm_hcr_el2_eff(env
) & trap
) {
329 return CP_ACCESS_TRAP_EL2
;
335 /* Check for traps from EL1 due to HCR_EL2.TSW. */
336 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
340 return CP_ACCESS_TRAP_EL2
;
345 /* Check for traps from EL1 due to HCR_EL2.TACR. */
346 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
349 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
350 return CP_ACCESS_TRAP_EL2
;
355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
356 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
359 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
360 return CP_ACCESS_TRAP_EL2
;
365 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
366 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
369 if (arm_current_el(env
) == 1 &&
370 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
371 return CP_ACCESS_TRAP_EL2
;
376 #ifdef TARGET_AARCH64
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
378 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
383 return CP_ACCESS_TRAP_EL2
;
389 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
391 ARMCPU
*cpu
= env_archcpu(env
);
393 raw_write(env
, ri
, value
);
394 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
397 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
399 ARMCPU
*cpu
= env_archcpu(env
);
401 if (raw_read(env
, ri
) != value
) {
403 * Unlike real hardware the qemu TLB uses virtual addresses,
404 * not modified virtual addresses, so this causes a TLB flush.
407 raw_write(env
, ri
, value
);
411 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 ARMCPU
*cpu
= env_archcpu(env
);
416 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
417 && !extended_addresses_enabled(env
)) {
419 * For VMSA (when not using the LPAE long descriptor page table
420 * format) this register includes the ASID, so do a TLB flush.
421 * For PMSA it is purely a process ID and no action is needed.
425 raw_write(env
, ri
, value
);
428 static int alle1_tlbmask(CPUARMState
*env
)
431 * Note that the 'ALL' scope must invalidate both stage 1 and
432 * stage 2 translations, whereas most other scopes only invalidate
433 * stage 1 translations.
435 return (ARMMMUIdxBit_E10_1
|
436 ARMMMUIdxBit_E10_1_PAN
|
438 ARMMMUIdxBit_Stage2
|
439 ARMMMUIdxBit_Stage2_S
);
443 /* IS variants of TLB operations must affect all cores */
444 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
447 CPUState
*cs
= env_cpu(env
);
449 tlb_flush_all_cpus_synced(cs
);
452 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 CPUState
*cs
= env_cpu(env
);
457 tlb_flush_all_cpus_synced(cs
);
460 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
463 CPUState
*cs
= env_cpu(env
);
465 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
468 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
471 CPUState
*cs
= env_cpu(env
);
473 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
477 * Non-IS variants of TLB operations are upgraded to
478 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
479 * force broadcast of these operations.
481 static bool tlb_force_broadcast(CPUARMState
*env
)
483 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
486 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
489 /* Invalidate all (TLBIALL) */
490 CPUState
*cs
= env_cpu(env
);
492 if (tlb_force_broadcast(env
)) {
493 tlb_flush_all_cpus_synced(cs
);
499 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
503 CPUState
*cs
= env_cpu(env
);
505 value
&= TARGET_PAGE_MASK
;
506 if (tlb_force_broadcast(env
)) {
507 tlb_flush_page_all_cpus_synced(cs
, value
);
509 tlb_flush_page(cs
, value
);
513 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
516 /* Invalidate by ASID (TLBIASID) */
517 CPUState
*cs
= env_cpu(env
);
519 if (tlb_force_broadcast(env
)) {
520 tlb_flush_all_cpus_synced(cs
);
526 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530 CPUState
*cs
= env_cpu(env
);
532 value
&= TARGET_PAGE_MASK
;
533 if (tlb_force_broadcast(env
)) {
534 tlb_flush_page_all_cpus_synced(cs
, value
);
536 tlb_flush_page(cs
, value
);
540 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
543 CPUState
*cs
= env_cpu(env
);
545 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
548 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
551 CPUState
*cs
= env_cpu(env
);
553 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
557 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
560 CPUState
*cs
= env_cpu(env
);
562 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
565 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= env_cpu(env
);
570 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
573 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 CPUState
*cs
= env_cpu(env
);
577 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
579 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
582 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
585 CPUState
*cs
= env_cpu(env
);
586 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
588 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
592 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
595 CPUState
*cs
= env_cpu(env
);
596 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
598 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
601 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
604 CPUState
*cs
= env_cpu(env
);
605 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
607 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
610 static const ARMCPRegInfo cp_reginfo
[] = {
612 * Define the secure and non-secure FCSE identifier CP registers
613 * separately because there is no secure bank in V8 (no _EL3). This allows
614 * the secure register to be properly reset and migrated. There is also no
615 * v8 EL1 version of the register so the non-secure instance stands alone.
618 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
619 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
620 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
621 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
622 { .name
= "FCSEIDR_S",
623 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
624 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
625 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
626 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
628 * Define the secure and non-secure context identifier CP registers
629 * separately because there is no secure bank in V8 (no _EL3). This allows
630 * the secure register to be properly reset and migrated. In the
631 * non-secure case, the 32-bit register will have reset and migration
632 * disabled during registration as it is handled by the 64-bit instance.
634 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
635 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
636 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
637 .fgt
= FGT_CONTEXTIDR_EL1
,
638 .secure
= ARM_CP_SECSTATE_NS
,
639 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
640 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
641 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
642 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
643 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
644 .secure
= ARM_CP_SECSTATE_S
,
645 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
646 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
649 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
651 * NB: Some of these registers exist in v8 but with more precise
652 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
654 /* MMU Domain access control / MPU write buffer control */
656 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
657 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
658 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
659 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
660 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
662 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
663 * For v6 and v5, these mappings are overly broad.
665 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
666 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
667 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
668 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
669 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
670 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
671 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
672 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
673 /* Cache maintenance ops; some of this space may be overridden later. */
674 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
675 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
676 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
679 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
681 * Not all pre-v6 cores implemented this WFI, so this is slightly
684 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
685 .access
= PL1_W
, .type
= ARM_CP_WFI
},
688 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
690 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
691 * is UNPREDICTABLE; we choose to NOP as most implementations do).
693 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
694 .access
= PL1_W
, .type
= ARM_CP_WFI
},
696 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
697 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
698 * OMAPCP will override this space.
700 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
701 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
703 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
704 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
706 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
707 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
708 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
711 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
712 * implementing it as RAZ means the "debug architecture version" bits
713 * will read as a reserved value, which should cause Linux to not try
714 * to use the debug hardware.
716 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
717 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
719 * MMU TLB control. Note that the wildcarding means we cover not just
720 * the unified TLB ops but also the dside/iside/inner-shareable variants.
722 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
723 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
724 .type
= ARM_CP_NO_RAW
},
725 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
726 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
727 .type
= ARM_CP_NO_RAW
},
728 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
729 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
730 .type
= ARM_CP_NO_RAW
},
731 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
732 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
733 .type
= ARM_CP_NO_RAW
},
734 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
735 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
736 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
737 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
740 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
745 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
746 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
748 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
749 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
750 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
752 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
753 /* VFP coprocessor: cp10 & cp11 [23:20] */
754 mask
|= R_CPACR_ASEDIS_MASK
|
755 R_CPACR_D32DIS_MASK
|
759 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
760 /* ASEDIS [31] bit is RAO/WI */
761 value
|= R_CPACR_ASEDIS_MASK
;
765 * VFPv3 and upwards with NEON implement 32 double precision
766 * registers (D0-D31).
768 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
769 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
770 value
|= R_CPACR_D32DIS_MASK
;
777 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
778 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
780 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
781 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
782 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
783 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
786 env
->cp15
.cpacr_el1
= value
;
789 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
792 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
793 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
795 uint64_t value
= env
->cp15
.cpacr_el1
;
797 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
798 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
799 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
805 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
808 * Call cpacr_write() so that we reset with the correct RAO bits set
809 * for our CPU features.
811 cpacr_write(env
, ri
, 0);
814 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 if (arm_feature(env
, ARM_FEATURE_V8
)) {
818 /* Check if CPACR accesses are to be trapped to EL2 */
819 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
820 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
821 return CP_ACCESS_TRAP_EL2
;
822 /* Check if CPACR accesses are to be trapped to EL3 */
823 } else if (arm_current_el(env
) < 3 &&
824 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
825 return CP_ACCESS_TRAP_EL3
;
832 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 /* Check if CPTR accesses are set to trap to EL3 */
836 if (arm_current_el(env
) == 2 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
844 static const ARMCPRegInfo v6_cp_reginfo
[] = {
845 /* prefetch by MVA in v6, NOP in v7 */
846 { .name
= "MVA_prefetch",
847 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
850 * We need to break the TB after ISB to execute self-modifying code
851 * correctly and also to take any pending interrupts immediately.
852 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
854 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
855 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
856 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
857 .access
= PL0_W
, .type
= ARM_CP_NOP
},
858 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
859 .access
= PL0_W
, .type
= ARM_CP_NOP
},
860 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
861 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
862 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
863 offsetof(CPUARMState
, cp15
.ifar_ns
) },
866 * Watchpoint Fault Address Register : should actually only be present
867 * for 1136, 1176, 11MPCore.
869 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
870 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
871 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
872 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
873 .fgt
= FGT_CPACR_EL1
,
874 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
875 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
878 typedef struct pm_event
{
879 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
880 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
881 bool (*supported
)(CPUARMState
*);
883 * Retrieve the current count of the underlying event. The programmed
884 * counters hold a difference from the return value from this function
886 uint64_t (*get_count
)(CPUARMState
*);
888 * Return how many nanoseconds it will take (at a minimum) for count events
889 * to occur. A negative value indicates the counter will never overflow, or
890 * that the counter has otherwise arranged for the overflow bit to be set
891 * and the PMU interrupt to be raised on overflow.
893 int64_t (*ns_per_count
)(uint64_t);
896 static bool event_always_supported(CPUARMState
*env
)
901 static uint64_t swinc_get_count(CPUARMState
*env
)
904 * SW_INCR events are written directly to the pmevcntr's by writes to
905 * PMSWINC, so there is no underlying count maintained by the PMU itself
910 static int64_t swinc_ns_per(uint64_t ignored
)
916 * Return the underlying cycle count for the PMU cycle counters. If we're in
917 * usermode, simply return 0.
919 static uint64_t cycles_get_count(CPUARMState
*env
)
921 #ifndef CONFIG_USER_ONLY
922 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
923 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
925 return cpu_get_host_ticks();
929 #ifndef CONFIG_USER_ONLY
930 static int64_t cycles_ns_per(uint64_t cycles
)
932 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
935 static bool instructions_supported(CPUARMState
*env
)
937 return icount_enabled() == 1; /* Precise instruction counting */
940 static uint64_t instructions_get_count(CPUARMState
*env
)
942 return (uint64_t)icount_get_raw();
945 static int64_t instructions_ns_per(uint64_t icount
)
947 return icount_to_ns((int64_t)icount
);
951 static bool pmuv3p1_events_supported(CPUARMState
*env
)
953 /* For events which are supported in any v8.1 PMU */
954 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
957 static bool pmuv3p4_events_supported(CPUARMState
*env
)
959 /* For events which are supported in any v8.1 PMU */
960 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
963 static uint64_t zero_event_get_count(CPUARMState
*env
)
965 /* For events which on QEMU never fire, so their count is always zero */
969 static int64_t zero_event_ns_per(uint64_t cycles
)
971 /* An event which never fires can never overflow */
975 static const pm_event pm_events
[] = {
976 { .number
= 0x000, /* SW_INCR */
977 .supported
= event_always_supported
,
978 .get_count
= swinc_get_count
,
979 .ns_per_count
= swinc_ns_per
,
981 #ifndef CONFIG_USER_ONLY
982 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
983 .supported
= instructions_supported
,
984 .get_count
= instructions_get_count
,
985 .ns_per_count
= instructions_ns_per
,
987 { .number
= 0x011, /* CPU_CYCLES, Cycle */
988 .supported
= event_always_supported
,
989 .get_count
= cycles_get_count
,
990 .ns_per_count
= cycles_ns_per
,
993 { .number
= 0x023, /* STALL_FRONTEND */
994 .supported
= pmuv3p1_events_supported
,
995 .get_count
= zero_event_get_count
,
996 .ns_per_count
= zero_event_ns_per
,
998 { .number
= 0x024, /* STALL_BACKEND */
999 .supported
= pmuv3p1_events_supported
,
1000 .get_count
= zero_event_get_count
,
1001 .ns_per_count
= zero_event_ns_per
,
1003 { .number
= 0x03c, /* STALL */
1004 .supported
= pmuv3p4_events_supported
,
1005 .get_count
= zero_event_get_count
,
1006 .ns_per_count
= zero_event_ns_per
,
1011 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1012 * events (i.e. the statistical profiling extension), this implementation
1013 * should first be updated to something sparse instead of the current
1014 * supported_event_map[] array.
1016 #define MAX_EVENT_ID 0x3c
1017 #define UNSUPPORTED_EVENT UINT16_MAX
1018 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1021 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1022 * of ARM event numbers to indices in our pm_events array.
1024 * Note: Events in the 0x40XX range are not currently supported.
1026 void pmu_init(ARMCPU
*cpu
)
1031 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1034 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1035 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1040 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1041 const pm_event
*cnt
= &pm_events
[i
];
1042 assert(cnt
->number
<= MAX_EVENT_ID
);
1043 /* We do not currently support events in the 0x40xx range */
1044 assert(cnt
->number
<= 0x3f);
1046 if (cnt
->supported(&cpu
->env
)) {
1047 supported_event_map
[cnt
->number
] = i
;
1048 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1049 if (cnt
->number
& 0x20) {
1050 cpu
->pmceid1
|= event_mask
;
1052 cpu
->pmceid0
|= event_mask
;
1059 * Check at runtime whether a PMU event is supported for the current machine
1061 static bool event_supported(uint16_t number
)
1063 if (number
> MAX_EVENT_ID
) {
1066 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1069 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1073 * Performance monitor registers user accessibility is controlled
1074 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1075 * trapping to EL2 or EL3 for other accesses.
1077 int el
= arm_current_el(env
);
1078 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1080 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1081 return CP_ACCESS_TRAP
;
1083 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1084 return CP_ACCESS_TRAP_EL2
;
1086 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1087 return CP_ACCESS_TRAP_EL3
;
1090 return CP_ACCESS_OK
;
1093 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1094 const ARMCPRegInfo
*ri
,
1097 /* ER: event counter read trap control */
1098 if (arm_feature(env
, ARM_FEATURE_V8
)
1099 && arm_current_el(env
) == 0
1100 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1102 return CP_ACCESS_OK
;
1105 return pmreg_access(env
, ri
, isread
);
1108 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1109 const ARMCPRegInfo
*ri
,
1112 /* SW: software increment write trap control */
1113 if (arm_feature(env
, ARM_FEATURE_V8
)
1114 && arm_current_el(env
) == 0
1115 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1117 return CP_ACCESS_OK
;
1120 return pmreg_access(env
, ri
, isread
);
1123 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1124 const ARMCPRegInfo
*ri
,
1127 /* ER: event counter read trap control */
1128 if (arm_feature(env
, ARM_FEATURE_V8
)
1129 && arm_current_el(env
) == 0
1130 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1131 return CP_ACCESS_OK
;
1134 return pmreg_access(env
, ri
, isread
);
1137 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1138 const ARMCPRegInfo
*ri
,
1141 /* CR: cycle counter read trap control */
1142 if (arm_feature(env
, ARM_FEATURE_V8
)
1143 && arm_current_el(env
) == 0
1144 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1146 return CP_ACCESS_OK
;
1149 return pmreg_access(env
, ri
, isread
);
1153 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1154 * We use these to decide whether we need to wrap a write to MDCR_EL2
1155 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1157 #define MDCR_EL2_PMU_ENABLE_BITS \
1158 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1159 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1162 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1163 * the current EL, security state, and register configuration.
1165 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1168 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1169 bool enabled
, prohibited
= false, filtered
;
1170 bool secure
= arm_is_secure(env
);
1171 int el
= arm_current_el(env
);
1172 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1173 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1175 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1179 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1180 (counter
< hpmn
|| counter
== 31)) {
1181 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1183 e
= mdcr_el2
& MDCR_HPME
;
1185 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1187 /* Is event counting prohibited? */
1188 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1189 prohibited
= mdcr_el2
& MDCR_HPMD
;
1192 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1195 if (counter
== 31) {
1197 * The cycle counter defaults to running. PMCR.DP says "disable
1198 * the cycle counter when event counting is prohibited".
1199 * Some MDCR bits disable the cycle counter specifically.
1201 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1202 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1204 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1207 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1212 if (counter
== 31) {
1213 filter
= env
->cp15
.pmccfiltr_el0
;
1215 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1218 p
= filter
& PMXEVTYPER_P
;
1219 u
= filter
& PMXEVTYPER_U
;
1220 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1221 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1222 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1223 m
= arm_el_is_aa64(env
, 1) &&
1224 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1227 filtered
= secure
? u
: u
!= nsu
;
1228 } else if (el
== 1) {
1229 filtered
= secure
? p
: p
!= nsk
;
1230 } else if (el
== 2) {
1236 if (counter
!= 31) {
1238 * If not checking PMCCNTR, ensure the counter is setup to an event we
1241 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1242 if (!event_supported(event
)) {
1247 return enabled
&& !prohibited
&& !filtered
;
1250 static void pmu_update_irq(CPUARMState
*env
)
1252 ARMCPU
*cpu
= env_archcpu(env
);
1253 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1254 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1257 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1260 * Return true if the clock divider is enabled and the cycle counter
1261 * is supposed to tick only once every 64 clock cycles. This is
1262 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1263 * (64-bit) cycle counter PMCR.D has no effect.
1265 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1268 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1270 /* Return true if the specified event counter is configured to be 64 bit */
1272 /* This isn't intended to be used with the cycle counter */
1273 assert(counter
< 31);
1275 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1279 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1281 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1282 * current security state, so we don't use arm_mdcr_el2_eff() here.
1284 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1285 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1287 if (hpmn
!= 0 && counter
>= hpmn
) {
1291 return env
->cp15
.c9_pmcr
& PMCRLP
;
1295 * Ensure c15_ccnt is the guest-visible count so that operations such as
1296 * enabling/disabling the counter or filtering, modifying the count itself,
1297 * etc. can be done logically. This is essentially a no-op if the counter is
1298 * not enabled at the time of the call.
1300 static void pmccntr_op_start(CPUARMState
*env
)
1302 uint64_t cycles
= cycles_get_count(env
);
1304 if (pmu_counter_enabled(env
, 31)) {
1305 uint64_t eff_cycles
= cycles
;
1306 if (pmccntr_clockdiv_enabled(env
)) {
1310 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1312 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1313 1ull << 63 : 1ull << 31;
1314 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1315 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1316 pmu_update_irq(env
);
1319 env
->cp15
.c15_ccnt
= new_pmccntr
;
1321 env
->cp15
.c15_ccnt_delta
= cycles
;
1325 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1326 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1329 static void pmccntr_op_finish(CPUARMState
*env
)
1331 if (pmu_counter_enabled(env
, 31)) {
1332 #ifndef CONFIG_USER_ONLY
1333 /* Calculate when the counter will next overflow */
1334 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1335 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1336 remaining_cycles
= (uint32_t)remaining_cycles
;
1338 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1340 if (overflow_in
> 0) {
1341 int64_t overflow_at
;
1343 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1344 overflow_in
, &overflow_at
)) {
1345 ARMCPU
*cpu
= env_archcpu(env
);
1346 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1351 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1352 if (pmccntr_clockdiv_enabled(env
)) {
1355 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1359 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1362 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1364 if (event_supported(event
)) {
1365 uint16_t event_idx
= supported_event_map
[event
];
1366 count
= pm_events
[event_idx
].get_count(env
);
1369 if (pmu_counter_enabled(env
, counter
)) {
1370 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1371 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1372 1ULL << 63 : 1ULL << 31;
1374 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1375 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1376 pmu_update_irq(env
);
1378 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1380 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1383 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1385 if (pmu_counter_enabled(env
, counter
)) {
1386 #ifndef CONFIG_USER_ONLY
1387 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1388 uint16_t event_idx
= supported_event_map
[event
];
1389 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1390 int64_t overflow_in
;
1392 if (!pmevcntr_is_64_bit(env
, counter
)) {
1393 delta
= (uint32_t)delta
;
1395 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1397 if (overflow_in
> 0) {
1398 int64_t overflow_at
;
1400 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1401 overflow_in
, &overflow_at
)) {
1402 ARMCPU
*cpu
= env_archcpu(env
);
1403 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1408 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1409 env
->cp15
.c14_pmevcntr
[counter
];
1413 void pmu_op_start(CPUARMState
*env
)
1416 pmccntr_op_start(env
);
1417 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1418 pmevcntr_op_start(env
, i
);
1422 void pmu_op_finish(CPUARMState
*env
)
1425 pmccntr_op_finish(env
);
1426 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1427 pmevcntr_op_finish(env
, i
);
1431 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1433 pmu_op_start(&cpu
->env
);
1436 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1438 pmu_op_finish(&cpu
->env
);
1441 void arm_pmu_timer_cb(void *opaque
)
1443 ARMCPU
*cpu
= opaque
;
1446 * Update all the counter values based on the current underlying counts,
1447 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1448 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1449 * counter may expire.
1451 pmu_op_start(&cpu
->env
);
1452 pmu_op_finish(&cpu
->env
);
1455 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 if (value
& PMCRC
) {
1461 /* The counter has been reset */
1462 env
->cp15
.c15_ccnt
= 0;
1465 if (value
& PMCRP
) {
1467 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1468 env
->cp15
.c14_pmevcntr
[i
] = 0;
1472 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1473 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1478 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1482 uint64_t overflow_mask
, new_pmswinc
;
1484 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1485 /* Increment a counter's count iff: */
1486 if ((value
& (1 << i
)) && /* counter's bit is set */
1487 /* counter is enabled and not filtered */
1488 pmu_counter_enabled(env
, i
) &&
1489 /* counter is SW_INCR */
1490 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1491 pmevcntr_op_start(env
, i
);
1494 * Detect if this write causes an overflow since we can't predict
1495 * PMSWINC overflows like we can for other events
1497 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1499 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1500 1ULL << 63 : 1ULL << 31;
1502 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1503 env
->cp15
.c9_pmovsr
|= (1 << i
);
1504 pmu_update_irq(env
);
1507 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1509 pmevcntr_op_finish(env
, i
);
1514 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1517 pmccntr_op_start(env
);
1518 ret
= env
->cp15
.c15_ccnt
;
1519 pmccntr_op_finish(env
);
1523 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1527 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1528 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1529 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1532 env
->cp15
.c9_pmselr
= value
& 0x1f;
1535 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1538 pmccntr_op_start(env
);
1539 env
->cp15
.c15_ccnt
= value
;
1540 pmccntr_op_finish(env
);
1543 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1546 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1548 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1551 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1554 pmccntr_op_start(env
);
1555 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1556 pmccntr_op_finish(env
);
1559 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1562 pmccntr_op_start(env
);
1563 /* M is not accessible from AArch32 */
1564 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1565 (value
& PMCCFILTR
);
1566 pmccntr_op_finish(env
);
1569 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1571 /* M is not visible in AArch32 */
1572 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1575 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1579 value
&= pmu_counter_mask(env
);
1580 env
->cp15
.c9_pmcnten
|= value
;
1584 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1588 value
&= pmu_counter_mask(env
);
1589 env
->cp15
.c9_pmcnten
&= ~value
;
1593 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1596 value
&= pmu_counter_mask(env
);
1597 env
->cp15
.c9_pmovsr
&= ~value
;
1598 pmu_update_irq(env
);
1601 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1604 value
&= pmu_counter_mask(env
);
1605 env
->cp15
.c9_pmovsr
|= value
;
1606 pmu_update_irq(env
);
1609 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1610 uint64_t value
, const uint8_t counter
)
1612 if (counter
== 31) {
1613 pmccfiltr_write(env
, ri
, value
);
1614 } else if (counter
< pmu_num_counters(env
)) {
1615 pmevcntr_op_start(env
, counter
);
1618 * If this counter's event type is changing, store the current
1619 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1620 * pmevcntr_op_finish has the correct baseline when it converts back to
1623 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1624 PMXEVTYPER_EVTCOUNT
;
1625 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1626 if (old_event
!= new_event
) {
1628 if (event_supported(new_event
)) {
1629 uint16_t event_idx
= supported_event_map
[new_event
];
1630 count
= pm_events
[event_idx
].get_count(env
);
1632 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1635 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1636 pmevcntr_op_finish(env
, counter
);
1639 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1640 * PMSELR value is equal to or greater than the number of implemented
1641 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1645 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1646 const uint8_t counter
)
1648 if (counter
== 31) {
1649 return env
->cp15
.pmccfiltr_el0
;
1650 } else if (counter
< pmu_num_counters(env
)) {
1651 return env
->cp15
.c14_pmevtyper
[counter
];
1654 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1655 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1661 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1664 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1665 pmevtyper_write(env
, ri
, value
, counter
);
1668 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1671 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1672 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1675 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1676 * pmu_op_finish calls when loading saved state for a migration. Because
1677 * we're potentially updating the type of event here, the value written to
1678 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1679 * different counter type. Therefore, we need to set this value to the
1680 * current count for the counter type we're writing so that pmu_op_finish
1681 * has the correct count for its calculation.
1683 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1684 if (event_supported(event
)) {
1685 uint16_t event_idx
= supported_event_map
[event
];
1686 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1687 pm_events
[event_idx
].get_count(env
);
1691 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1693 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1694 return pmevtyper_read(env
, ri
, counter
);
1697 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1700 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1703 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1705 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1708 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 uint64_t value
, uint8_t counter
)
1711 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1712 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1713 value
&= MAKE_64BIT_MASK(0, 32);
1715 if (counter
< pmu_num_counters(env
)) {
1716 pmevcntr_op_start(env
, counter
);
1717 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1718 pmevcntr_op_finish(env
, counter
);
1721 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1722 * are CONSTRAINED UNPREDICTABLE.
1726 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1729 if (counter
< pmu_num_counters(env
)) {
1731 pmevcntr_op_start(env
, counter
);
1732 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1733 pmevcntr_op_finish(env
, counter
);
1734 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1735 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1736 ret
&= MAKE_64BIT_MASK(0, 32);
1741 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1742 * are CONSTRAINED UNPREDICTABLE.
1748 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1751 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1752 pmevcntr_write(env
, ri
, value
, counter
);
1755 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1757 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1758 return pmevcntr_read(env
, ri
, counter
);
1761 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1764 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1765 assert(counter
< pmu_num_counters(env
));
1766 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1767 pmevcntr_write(env
, ri
, value
, counter
);
1770 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1772 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1773 assert(counter
< pmu_num_counters(env
));
1774 return env
->cp15
.c14_pmevcntr
[counter
];
1777 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1780 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1783 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1785 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1788 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1791 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1792 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1794 env
->cp15
.c9_pmuserenr
= value
& 1;
1798 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1801 /* We have no event counters so only the C bit can be changed */
1802 value
&= pmu_counter_mask(env
);
1803 env
->cp15
.c9_pminten
|= value
;
1804 pmu_update_irq(env
);
1807 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1810 value
&= pmu_counter_mask(env
);
1811 env
->cp15
.c9_pminten
&= ~value
;
1812 pmu_update_irq(env
);
1815 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1819 * Note that even though the AArch64 view of this register has bits
1820 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1821 * architectural requirements for bits which are RES0 only in some
1822 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1823 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1825 raw_write(env
, ri
, value
& ~0x1FULL
);
1828 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1830 /* Begin with base v8.0 state. */
1831 uint64_t valid_mask
= 0x3fff;
1832 ARMCPU
*cpu
= env_archcpu(env
);
1836 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1837 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1838 * Instead, choose the format based on the mode of EL3.
1840 if (arm_el_is_aa64(env
, 3)) {
1841 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1842 valid_mask
&= ~SCR_NET
; /* RES0 */
1844 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1845 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1846 value
|= SCR_RW
; /* RAO/WI */
1848 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1849 valid_mask
|= SCR_TERR
;
1851 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1852 valid_mask
|= SCR_TLOR
;
1854 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1855 valid_mask
|= SCR_API
| SCR_APK
;
1857 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1858 valid_mask
|= SCR_EEL2
;
1860 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1861 valid_mask
|= SCR_ATA
;
1863 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1864 valid_mask
|= SCR_ENSCXT
;
1866 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1867 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1869 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1870 valid_mask
|= SCR_ENTP2
;
1872 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1873 valid_mask
|= SCR_HXEN
;
1875 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1876 valid_mask
|= SCR_FGTEN
;
1879 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1880 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1881 valid_mask
|= SCR_TERR
;
1885 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1886 valid_mask
&= ~SCR_HCE
;
1889 * On ARMv7, SMD (or SCD as it is called in v7) is only
1890 * supported if EL2 exists. The bit is UNK/SBZP when
1891 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1892 * when EL2 is unavailable.
1893 * On ARMv8, this bit is always available.
1895 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1896 !arm_feature(env
, ARM_FEATURE_V8
)) {
1897 valid_mask
&= ~SCR_SMD
;
1901 /* Clear all-context RES0 bits. */
1902 value
&= valid_mask
;
1903 changed
= env
->cp15
.scr_el3
^ value
;
1904 env
->cp15
.scr_el3
= value
;
1907 * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
1908 * we must invalidate all TLBs below EL3.
1910 if (changed
& SCR_NS
) {
1911 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1912 ARMMMUIdxBit_E20_0
|
1913 ARMMMUIdxBit_E10_1
|
1914 ARMMMUIdxBit_E20_2
|
1915 ARMMMUIdxBit_E10_1_PAN
|
1916 ARMMMUIdxBit_E20_2_PAN
|
1921 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1924 * scr_write will set the RES1 bits on an AArch64-only CPU.
1925 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1927 scr_write(env
, ri
, 0);
1930 static CPAccessResult
access_tid4(CPUARMState
*env
,
1931 const ARMCPRegInfo
*ri
,
1934 if (arm_current_el(env
) == 1 &&
1935 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1936 return CP_ACCESS_TRAP_EL2
;
1939 return CP_ACCESS_OK
;
1942 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1944 ARMCPU
*cpu
= env_archcpu(env
);
1947 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1950 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1951 ri
->secure
& ARM_CP_SECSTATE_S
);
1953 return cpu
->ccsidr
[index
];
1956 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1959 raw_write(env
, ri
, value
& 0xf);
1962 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1964 CPUState
*cs
= env_cpu(env
);
1965 bool el1
= arm_current_el(env
) == 1;
1966 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1969 if (hcr_el2
& HCR_IMO
) {
1970 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1974 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1979 if (hcr_el2
& HCR_FMO
) {
1980 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1984 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1989 if (hcr_el2
& HCR_AMO
) {
1990 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1998 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2001 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2002 return CP_ACCESS_TRAP_EL2
;
2005 return CP_ACCESS_OK
;
2008 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2011 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2012 return access_aa64_tid1(env
, ri
, isread
);
2015 return CP_ACCESS_OK
;
2018 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2019 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2020 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2021 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2023 * Performance monitors are implementation defined in v7,
2024 * but with an ARM recommended set of registers, which we
2027 * Performance registers fall into three categories:
2028 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2029 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2030 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2031 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2032 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2034 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2035 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2036 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2037 .writefn
= pmcntenset_write
,
2038 .accessfn
= pmreg_access
,
2040 .raw_writefn
= raw_write
},
2041 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2042 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2043 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2045 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2046 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2047 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2049 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2050 .accessfn
= pmreg_access
,
2052 .writefn
= pmcntenclr_write
,
2053 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2054 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2055 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2056 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2058 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2059 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2060 .writefn
= pmcntenclr_write
},
2061 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2062 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2063 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2064 .accessfn
= pmreg_access
,
2066 .writefn
= pmovsr_write
,
2067 .raw_writefn
= raw_write
},
2068 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2069 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2070 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2072 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2073 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2074 .writefn
= pmovsr_write
,
2075 .raw_writefn
= raw_write
},
2076 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2077 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2078 .fgt
= FGT_PMSWINC_EL0
,
2079 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2080 .writefn
= pmswinc_write
},
2081 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2082 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2083 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2084 .fgt
= FGT_PMSWINC_EL0
,
2085 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2086 .writefn
= pmswinc_write
},
2087 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2088 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2089 .fgt
= FGT_PMSELR_EL0
,
2090 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2091 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2092 .raw_writefn
= raw_write
},
2093 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2095 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2096 .fgt
= FGT_PMSELR_EL0
,
2097 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2098 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2099 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2100 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2101 .fgt
= FGT_PMCCNTR_EL0
,
2102 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2103 .accessfn
= pmreg_access_ccntr
},
2104 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2105 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2106 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2107 .fgt
= FGT_PMCCNTR_EL0
,
2109 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2110 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2111 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2112 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2113 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2114 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2115 .fgt
= FGT_PMCCFILTR_EL0
,
2116 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2118 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2119 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2120 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2121 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2122 .fgt
= FGT_PMCCFILTR_EL0
,
2124 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2126 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2127 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2128 .accessfn
= pmreg_access
,
2129 .fgt
= FGT_PMEVTYPERN_EL0
,
2130 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2131 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2132 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2133 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2134 .accessfn
= pmreg_access
,
2135 .fgt
= FGT_PMEVTYPERN_EL0
,
2136 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2137 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2138 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2139 .accessfn
= pmreg_access_xevcntr
,
2140 .fgt
= FGT_PMEVCNTRN_EL0
,
2141 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2142 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2143 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2144 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2145 .accessfn
= pmreg_access_xevcntr
,
2146 .fgt
= FGT_PMEVCNTRN_EL0
,
2147 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2148 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2149 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2150 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2152 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2153 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2154 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2155 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2156 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2158 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2159 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2160 .access
= PL1_RW
, .accessfn
= access_tpm
,
2162 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2163 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2165 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2166 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2167 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2168 .access
= PL1_RW
, .accessfn
= access_tpm
,
2171 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2172 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2173 .resetvalue
= 0x0 },
2174 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2175 .access
= PL1_RW
, .accessfn
= access_tpm
,
2177 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2178 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2179 .writefn
= pmintenclr_write
, },
2180 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2181 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2182 .access
= PL1_RW
, .accessfn
= access_tpm
,
2184 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2185 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2186 .writefn
= pmintenclr_write
},
2187 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2188 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2190 .accessfn
= access_tid4
,
2191 .fgt
= FGT_CCSIDR_EL1
,
2192 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2193 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2194 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2196 .accessfn
= access_tid4
,
2197 .fgt
= FGT_CSSELR_EL1
,
2198 .writefn
= csselr_write
, .resetvalue
= 0,
2199 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2200 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2202 * Auxiliary ID register: this actually has an IMPDEF value but for now
2203 * just RAZ for all cores:
2205 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2206 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2207 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2208 .accessfn
= access_aa64_tid1
,
2209 .fgt
= FGT_AIDR_EL1
,
2212 * Auxiliary fault status registers: these also are IMPDEF, and we
2213 * choose to RAZ/WI for all cores.
2215 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2216 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2217 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2218 .fgt
= FGT_AFSR0_EL1
,
2219 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2220 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2221 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2222 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2223 .fgt
= FGT_AFSR1_EL1
,
2224 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2226 * MAIR can just read-as-written because we don't implement caches
2227 * and so don't need to care about memory attributes.
2229 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2230 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2231 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2232 .fgt
= FGT_MAIR_EL1
,
2233 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2235 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2236 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2237 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2240 * For non-long-descriptor page tables these are PRRR and NMRR;
2241 * regardless they still act as reads-as-written for QEMU.
2244 * MAIR0/1 are defined separately from their 64-bit counterpart which
2245 * allows them to assign the correct fieldoffset based on the endianness
2246 * handled in the field definitions.
2248 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2249 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2250 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2251 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2252 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2253 .resetfn
= arm_cp_reset_ignore
},
2254 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2255 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2256 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2257 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2258 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2259 .resetfn
= arm_cp_reset_ignore
},
2260 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2261 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2263 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2264 /* 32 bit ITLB invalidates */
2265 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2266 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2267 .writefn
= tlbiall_write
},
2268 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2269 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2270 .writefn
= tlbimva_write
},
2271 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2272 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2273 .writefn
= tlbiasid_write
},
2274 /* 32 bit DTLB invalidates */
2275 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2276 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2277 .writefn
= tlbiall_write
},
2278 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2279 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2280 .writefn
= tlbimva_write
},
2281 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2282 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2283 .writefn
= tlbiasid_write
},
2284 /* 32 bit TLB invalidates */
2285 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2286 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2287 .writefn
= tlbiall_write
},
2288 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2289 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2290 .writefn
= tlbimva_write
},
2291 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2292 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2293 .writefn
= tlbiasid_write
},
2294 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2295 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2296 .writefn
= tlbimvaa_write
},
2299 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2300 /* 32 bit TLB invalidates, Inner Shareable */
2301 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2302 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2303 .writefn
= tlbiall_is_write
},
2304 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2305 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2306 .writefn
= tlbimva_is_write
},
2307 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2308 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2309 .writefn
= tlbiasid_is_write
},
2310 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2311 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2312 .writefn
= tlbimvaa_is_write
},
2315 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2316 /* PMOVSSET is not implemented in v7 before v7ve */
2317 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2318 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2320 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2321 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2322 .writefn
= pmovsset_write
,
2323 .raw_writefn
= raw_write
},
2324 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2325 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2326 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2328 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2329 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2330 .writefn
= pmovsset_write
,
2331 .raw_writefn
= raw_write
},
2334 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2341 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2345 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2346 * at all, so we don't need to check whether we're v8A.
2348 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2349 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2350 return CP_ACCESS_TRAP_EL2
;
2352 return CP_ACCESS_OK
;
2355 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2358 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2359 return CP_ACCESS_TRAP
;
2361 return teecr_access(env
, ri
, isread
);
2364 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2365 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2366 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2368 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2369 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2370 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2371 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2374 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2375 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2376 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2378 .fgt
= FGT_TPIDR_EL0
,
2379 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2380 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2382 .fgt
= FGT_TPIDR_EL0
,
2383 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2384 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2385 .resetfn
= arm_cp_reset_ignore
},
2386 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2387 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2388 .access
= PL0_R
| PL1_W
,
2389 .fgt
= FGT_TPIDRRO_EL0
,
2390 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2392 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2393 .access
= PL0_R
| PL1_W
,
2394 .fgt
= FGT_TPIDRRO_EL0
,
2395 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2396 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2397 .resetfn
= arm_cp_reset_ignore
},
2398 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2399 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2401 .fgt
= FGT_TPIDR_EL1
,
2402 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2403 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2405 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2406 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2410 #ifndef CONFIG_USER_ONLY
2412 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2416 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2417 * Writable only at the highest implemented exception level.
2419 int el
= arm_current_el(env
);
2425 hcr
= arm_hcr_el2_eff(env
);
2426 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2427 cntkctl
= env
->cp15
.cnthctl_el2
;
2429 cntkctl
= env
->cp15
.c14_cntkctl
;
2431 if (!extract32(cntkctl
, 0, 2)) {
2432 return CP_ACCESS_TRAP
;
2436 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2437 arm_is_secure_below_el3(env
)) {
2438 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2439 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2447 if (!isread
&& el
< arm_highest_el(env
)) {
2448 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2451 return CP_ACCESS_OK
;
2454 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2457 unsigned int cur_el
= arm_current_el(env
);
2458 bool has_el2
= arm_is_el2_enabled(env
);
2459 uint64_t hcr
= arm_hcr_el2_eff(env
);
2463 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2464 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2465 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2466 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2469 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2470 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2471 return CP_ACCESS_TRAP
;
2474 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2475 if (hcr
& HCR_E2H
) {
2476 if (timeridx
== GTIMER_PHYS
&&
2477 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2478 return CP_ACCESS_TRAP_EL2
;
2481 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2482 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2483 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2484 return CP_ACCESS_TRAP_EL2
;
2490 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2491 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2493 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2494 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2495 return CP_ACCESS_TRAP_EL2
;
2499 return CP_ACCESS_OK
;
2502 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2505 unsigned int cur_el
= arm_current_el(env
);
2506 bool has_el2
= arm_is_el2_enabled(env
);
2507 uint64_t hcr
= arm_hcr_el2_eff(env
);
2511 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2512 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2513 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2514 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2518 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2519 * EL0 if EL0[PV]TEN is zero.
2521 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2522 return CP_ACCESS_TRAP
;
2527 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2528 if (hcr
& HCR_E2H
) {
2529 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2530 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2531 return CP_ACCESS_TRAP_EL2
;
2534 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2535 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2536 return CP_ACCESS_TRAP_EL2
;
2542 return CP_ACCESS_OK
;
2545 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2546 const ARMCPRegInfo
*ri
,
2549 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2552 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2553 const ARMCPRegInfo
*ri
,
2556 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2559 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2562 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2565 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2568 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2571 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2572 const ARMCPRegInfo
*ri
,
2576 * The AArch64 register view of the secure physical timer is
2577 * always accessible from EL3, and configurably accessible from
2580 switch (arm_current_el(env
)) {
2582 if (!arm_is_secure(env
)) {
2583 return CP_ACCESS_TRAP
;
2585 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2586 return CP_ACCESS_TRAP_EL3
;
2588 return CP_ACCESS_OK
;
2591 return CP_ACCESS_TRAP
;
2593 return CP_ACCESS_OK
;
2595 g_assert_not_reached();
2599 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2601 ARMCPU
*cpu
= env_archcpu(env
);
2603 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2606 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2608 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2612 * Timer enabled: calculate and set current ISTATUS, irq, and
2613 * reset timer to when ISTATUS next has to change
2615 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2616 cpu
->env
.cp15
.cntvoff_el2
: 0;
2617 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2618 /* Note that this must be unsigned 64 bit arithmetic: */
2619 int istatus
= count
- offset
>= gt
->cval
;
2623 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2625 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2626 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2629 /* Next transition is when count rolls back over to zero */
2630 nexttick
= UINT64_MAX
;
2632 /* Next transition is when we hit cval */
2633 nexttick
= gt
->cval
+ offset
;
2636 * Note that the desired next expiry time might be beyond the
2637 * signed-64-bit range of a QEMUTimer -- in this case we just
2638 * set the timer for as far in the future as possible. When the
2639 * timer expires we will reset the timer for any remaining period.
2641 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2642 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2644 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2646 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2648 /* Timer disabled: ISTATUS and timer output always clear */
2650 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2651 timer_del(cpu
->gt_timer
[timeridx
]);
2652 trace_arm_gt_recalc_disabled(timeridx
);
2656 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2659 ARMCPU
*cpu
= env_archcpu(env
);
2661 timer_del(cpu
->gt_timer
[timeridx
]);
2664 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2666 return gt_get_countervalue(env
);
2669 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2673 switch (arm_current_el(env
)) {
2675 hcr
= arm_hcr_el2_eff(env
);
2676 if (hcr
& HCR_E2H
) {
2681 hcr
= arm_hcr_el2_eff(env
);
2682 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2688 return env
->cp15
.cntvoff_el2
;
2691 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2693 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2696 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2700 trace_arm_gt_cval_write(timeridx
, value
);
2701 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2702 gt_recalc_timer(env_archcpu(env
), timeridx
);
2705 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2708 uint64_t offset
= 0;
2712 case GTIMER_HYPVIRT
:
2713 offset
= gt_virt_cnt_offset(env
);
2717 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2718 (gt_get_countervalue(env
) - offset
));
2721 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2725 uint64_t offset
= 0;
2729 case GTIMER_HYPVIRT
:
2730 offset
= gt_virt_cnt_offset(env
);
2734 trace_arm_gt_tval_write(timeridx
, value
);
2735 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2736 sextract64(value
, 0, 32);
2737 gt_recalc_timer(env_archcpu(env
), timeridx
);
2740 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2744 ARMCPU
*cpu
= env_archcpu(env
);
2745 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2747 trace_arm_gt_ctl_write(timeridx
, value
);
2748 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2749 if ((oldval
^ value
) & 1) {
2750 /* Enable toggled */
2751 gt_recalc_timer(cpu
, timeridx
);
2752 } else if ((oldval
^ value
) & 2) {
2754 * IMASK toggled: don't need to recalculate,
2755 * just set the interrupt line based on ISTATUS
2757 int irqstate
= (oldval
& 4) && !(value
& 2);
2759 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2760 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2764 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2766 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2769 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2772 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2775 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2777 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2780 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2783 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2786 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2789 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2792 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2794 switch (arm_mmu_idx(env
)) {
2795 case ARMMMUIdx_E20_0
:
2796 case ARMMMUIdx_E20_2
:
2797 case ARMMMUIdx_E20_2_PAN
:
2804 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2806 switch (arm_mmu_idx(env
)) {
2807 case ARMMMUIdx_E20_0
:
2808 case ARMMMUIdx_E20_2
:
2809 case ARMMMUIdx_E20_2_PAN
:
2810 return GTIMER_HYPVIRT
;
2816 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2817 const ARMCPRegInfo
*ri
)
2819 int timeridx
= gt_phys_redir_timeridx(env
);
2820 return env
->cp15
.c14_timer
[timeridx
].cval
;
2823 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2826 int timeridx
= gt_phys_redir_timeridx(env
);
2827 gt_cval_write(env
, ri
, timeridx
, value
);
2830 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2831 const ARMCPRegInfo
*ri
)
2833 int timeridx
= gt_phys_redir_timeridx(env
);
2834 return gt_tval_read(env
, ri
, timeridx
);
2837 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2840 int timeridx
= gt_phys_redir_timeridx(env
);
2841 gt_tval_write(env
, ri
, timeridx
, value
);
2844 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2845 const ARMCPRegInfo
*ri
)
2847 int timeridx
= gt_phys_redir_timeridx(env
);
2848 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2851 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2854 int timeridx
= gt_phys_redir_timeridx(env
);
2855 gt_ctl_write(env
, ri
, timeridx
, value
);
2858 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2860 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2863 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2866 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2869 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2871 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2874 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2877 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2880 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2883 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2886 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2889 ARMCPU
*cpu
= env_archcpu(env
);
2891 trace_arm_gt_cntvoff_write(value
);
2892 raw_write(env
, ri
, value
);
2893 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2896 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2897 const ARMCPRegInfo
*ri
)
2899 int timeridx
= gt_virt_redir_timeridx(env
);
2900 return env
->cp15
.c14_timer
[timeridx
].cval
;
2903 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2906 int timeridx
= gt_virt_redir_timeridx(env
);
2907 gt_cval_write(env
, ri
, timeridx
, value
);
2910 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2911 const ARMCPRegInfo
*ri
)
2913 int timeridx
= gt_virt_redir_timeridx(env
);
2914 return gt_tval_read(env
, ri
, timeridx
);
2917 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2920 int timeridx
= gt_virt_redir_timeridx(env
);
2921 gt_tval_write(env
, ri
, timeridx
, value
);
2924 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2925 const ARMCPRegInfo
*ri
)
2927 int timeridx
= gt_virt_redir_timeridx(env
);
2928 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2931 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2934 int timeridx
= gt_virt_redir_timeridx(env
);
2935 gt_ctl_write(env
, ri
, timeridx
, value
);
2938 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2940 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2943 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2946 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2949 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2951 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2954 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2957 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2960 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2963 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2966 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2968 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2971 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2974 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2977 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2979 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2982 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2985 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2988 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2991 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2994 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2996 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2999 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3002 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3005 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3007 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3010 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3013 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3016 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3019 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3022 void arm_gt_ptimer_cb(void *opaque
)
3024 ARMCPU
*cpu
= opaque
;
3026 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3029 void arm_gt_vtimer_cb(void *opaque
)
3031 ARMCPU
*cpu
= opaque
;
3033 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3036 void arm_gt_htimer_cb(void *opaque
)
3038 ARMCPU
*cpu
= opaque
;
3040 gt_recalc_timer(cpu
, GTIMER_HYP
);
3043 void arm_gt_stimer_cb(void *opaque
)
3045 ARMCPU
*cpu
= opaque
;
3047 gt_recalc_timer(cpu
, GTIMER_SEC
);
3050 void arm_gt_hvtimer_cb(void *opaque
)
3052 ARMCPU
*cpu
= opaque
;
3054 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3057 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3059 ARMCPU
*cpu
= env_archcpu(env
);
3061 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3064 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3066 * Note that CNTFRQ is purely reads-as-written for the benefit
3067 * of software; writing it doesn't actually change the timer frequency.
3068 * Our reset value matches the fixed frequency we implement the timer at.
3070 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3071 .type
= ARM_CP_ALIAS
,
3072 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3073 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3075 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3076 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3077 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3078 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3079 .resetfn
= arm_gt_cntfrq_reset
,
3081 /* overall control: mostly access permissions */
3082 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3083 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3085 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3088 /* per-timer control */
3089 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3090 .secure
= ARM_CP_SECSTATE_NS
,
3091 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3092 .accessfn
= gt_ptimer_access
,
3093 .fieldoffset
= offsetoflow32(CPUARMState
,
3094 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3095 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3096 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3098 { .name
= "CNTP_CTL_S",
3099 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3100 .secure
= ARM_CP_SECSTATE_S
,
3101 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3102 .accessfn
= gt_ptimer_access
,
3103 .fieldoffset
= offsetoflow32(CPUARMState
,
3104 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3105 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3107 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3108 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3109 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3110 .accessfn
= gt_ptimer_access
,
3111 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3113 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3114 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3116 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3117 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3118 .accessfn
= gt_vtimer_access
,
3119 .fieldoffset
= offsetoflow32(CPUARMState
,
3120 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3121 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3122 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3124 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3125 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3126 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3127 .accessfn
= gt_vtimer_access
,
3128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3130 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3131 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3133 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3134 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3135 .secure
= ARM_CP_SECSTATE_NS
,
3136 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3137 .accessfn
= gt_ptimer_access
,
3138 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3140 { .name
= "CNTP_TVAL_S",
3141 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3142 .secure
= ARM_CP_SECSTATE_S
,
3143 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3144 .accessfn
= gt_ptimer_access
,
3145 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3147 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3148 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3149 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3150 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3151 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3153 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3154 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3155 .accessfn
= gt_vtimer_access
,
3156 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3158 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3159 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3160 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3161 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3162 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3164 /* The counter itself */
3165 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3166 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3167 .accessfn
= gt_pct_access
,
3168 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3170 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3171 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3172 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3173 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3175 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3176 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3177 .accessfn
= gt_vct_access
,
3178 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3180 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3181 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3182 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3183 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3185 /* Comparison value, indicating when the timer goes off */
3186 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3187 .secure
= ARM_CP_SECSTATE_NS
,
3189 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3190 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3191 .accessfn
= gt_ptimer_access
,
3192 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3193 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3195 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3196 .secure
= ARM_CP_SECSTATE_S
,
3198 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3199 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3200 .accessfn
= gt_ptimer_access
,
3201 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3203 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3204 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3207 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3208 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3209 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3210 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3212 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3214 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3215 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3216 .accessfn
= gt_vtimer_access
,
3217 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3218 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3220 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3221 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3224 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3225 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3226 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3227 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3230 * Secure timer -- this is actually restricted to only EL3
3231 * and configurably Secure-EL1 via the accessfn.
3233 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3234 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3235 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3236 .accessfn
= gt_stimer_access
,
3237 .readfn
= gt_sec_tval_read
,
3238 .writefn
= gt_sec_tval_write
,
3239 .resetfn
= gt_sec_timer_reset
,
3241 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3242 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3243 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3244 .accessfn
= gt_stimer_access
,
3245 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3247 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3249 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3250 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3251 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3252 .accessfn
= gt_stimer_access
,
3253 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3254 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3258 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3261 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3262 return CP_ACCESS_TRAP
;
3264 return CP_ACCESS_OK
;
3270 * In user-mode most of the generic timer registers are inaccessible
3271 * however modern kernels (4.12+) allow access to cntvct_el0
3274 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3276 ARMCPU
*cpu
= env_archcpu(env
);
3279 * Currently we have no support for QEMUTimer in linux-user so we
3280 * can't call gt_get_countervalue(env), instead we directly
3281 * call the lower level functions.
3283 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3286 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3287 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3288 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3289 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3291 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3293 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3294 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3295 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3296 .readfn
= gt_virt_cnt_read
,
3302 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3304 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3305 raw_write(env
, ri
, value
);
3306 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3307 raw_write(env
, ri
, value
& 0xfffff6ff);
3309 raw_write(env
, ri
, value
& 0xfffff1ff);
3313 #ifndef CONFIG_USER_ONLY
3314 /* get_phys_addr() isn't present for user-mode-only targets */
3316 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3321 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3322 * Secure EL1 (which can only happen if EL3 is AArch64).
3323 * They are simply UNDEF if executed from NS EL1.
3324 * They function normally from EL2 or EL3.
3326 if (arm_current_el(env
) == 1) {
3327 if (arm_is_secure_below_el3(env
)) {
3328 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3329 return CP_ACCESS_TRAP_EL2
;
3331 return CP_ACCESS_TRAP_EL3
;
3333 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3336 return CP_ACCESS_OK
;
3340 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3341 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3346 bool format64
= false;
3347 ARMMMUFaultInfo fi
= {};
3348 GetPhysAddrResult res
= {};
3350 ret
= get_phys_addr_with_secure(env
, value
, access_type
, mmu_idx
,
3351 is_secure
, &res
, &fi
);
3354 * ATS operations only do S1 or S1+S2 translations, so we never
3355 * have to deal with the ARMCacheAttrs format for S2 only.
3357 assert(!res
.cacheattrs
.is_s2_format
);
3361 * Some kinds of translation fault must cause exceptions rather
3362 * than being reported in the PAR.
3364 int current_el
= arm_current_el(env
);
3366 uint32_t syn
, fsr
, fsc
;
3367 bool take_exc
= false;
3369 if (fi
.s1ptw
&& current_el
== 1
3370 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3372 * Synchronous stage 2 fault on an access made as part of the
3373 * translation table walk for AT S1E0* or AT S1E1* insn
3374 * executed from NS EL1. If this is a synchronous external abort
3375 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3376 * to EL3. Otherwise the fault is taken as an exception to EL2,
3377 * and HPFAR_EL2 holds the faulting IPA.
3379 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3380 (env
->cp15
.scr_el3
& SCR_EA
)) {
3383 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3384 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3385 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3390 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3392 * Synchronous external aborts during a translation table walk
3393 * are taken as Data Abort exceptions.
3396 if (current_el
== 3) {
3402 target_el
= exception_target_el(env
);
3408 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3409 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3410 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3411 fsr
= arm_fi_to_lfsc(&fi
);
3412 fsc
= extract32(fsr
, 0, 6);
3414 fsr
= arm_fi_to_sfsc(&fi
);
3418 * Report exception with ESR indicating a fault due to a
3419 * translation table walk for a cache maintenance instruction.
3421 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3422 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3423 env
->exception
.vaddress
= value
;
3424 env
->exception
.fsr
= fsr
;
3425 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3431 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3434 * * TTBCR.EAE determines whether the result is returned using the
3435 * 32-bit or the 64-bit PAR format
3436 * * Instructions executed in Hyp mode always use the 64bit format
3438 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3439 * * The Non-secure TTBCR.EAE bit is set to 1
3440 * * The implementation includes EL2, and the value of HCR.VM is 1
3442 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3444 * ATS1Hx always uses the 64bit format.
3446 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3448 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3449 if (mmu_idx
== ARMMMUIdx_E10_0
||
3450 mmu_idx
== ARMMMUIdx_E10_1
||
3451 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3452 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3454 format64
|= arm_current_el(env
) == 2;
3460 /* Create a 64-bit PAR */
3461 par64
= (1 << 11); /* LPAE bit always set */
3463 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3464 if (!res
.f
.attrs
.secure
) {
3465 par64
|= (1 << 9); /* NS */
3467 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3468 par64
|= res
.cacheattrs
.shareability
<< 7; /* SH */
3470 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3473 par64
|= (fsr
& 0x3f) << 1; /* FS */
3475 par64
|= (1 << 9); /* S */
3478 par64
|= (1 << 8); /* PTW */
3483 * fsr is a DFSR/IFSR value for the short descriptor
3484 * translation table format (with WnR always clear).
3485 * Convert it to a 32-bit PAR.
3488 /* We do not set any attribute bits in the PAR */
3489 if (res
.f
.lg_page_size
== 24
3490 && arm_feature(env
, ARM_FEATURE_V7
)) {
3491 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3493 par64
= res
.f
.phys_addr
& 0xfffff000;
3495 if (!res
.f
.attrs
.secure
) {
3496 par64
|= (1 << 9); /* NS */
3499 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3501 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3502 ((fsr
& 0xf) << 1) | 1;
3507 #endif /* CONFIG_TCG */
3509 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3512 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3515 int el
= arm_current_el(env
);
3516 bool secure
= arm_is_secure_below_el3(env
);
3518 switch (ri
->opc2
& 6) {
3520 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3523 mmu_idx
= ARMMMUIdx_E3
;
3527 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3530 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3531 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3533 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3537 g_assert_not_reached();
3541 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3544 mmu_idx
= ARMMMUIdx_E10_0
;
3548 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3549 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3552 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3555 g_assert_not_reached();
3559 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3560 mmu_idx
= ARMMMUIdx_E10_1
;
3564 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3565 mmu_idx
= ARMMMUIdx_E10_0
;
3569 g_assert_not_reached();
3572 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, secure
);
3574 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3576 /* Handled by hardware accelerator. */
3577 g_assert_not_reached();
3578 #endif /* CONFIG_TCG */
3581 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3585 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3588 /* There is no SecureEL2 for AArch32. */
3589 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
, false);
3591 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3593 /* Handled by hardware accelerator. */
3594 g_assert_not_reached();
3595 #endif /* CONFIG_TCG */
3598 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3601 if (arm_current_el(env
) == 3 &&
3602 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3603 return CP_ACCESS_TRAP
;
3605 return CP_ACCESS_OK
;
3608 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3612 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3614 int secure
= arm_is_secure_below_el3(env
);
3615 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3616 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3618 switch (ri
->opc2
& 6) {
3621 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3622 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3623 mmu_idx
= regime_e20
?
3624 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3626 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3629 case 4: /* AT S1E2R, AT S1E2W */
3630 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3632 case 6: /* AT S1E3R, AT S1E3W */
3633 mmu_idx
= ARMMMUIdx_E3
;
3637 g_assert_not_reached();
3640 case 2: /* AT S1E0R, AT S1E0W */
3641 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3643 case 4: /* AT S12E1R, AT S12E1W */
3644 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3646 case 6: /* AT S12E0R, AT S12E0W */
3647 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3650 g_assert_not_reached();
3653 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3656 /* Handled by hardware accelerator. */
3657 g_assert_not_reached();
3658 #endif /* CONFIG_TCG */
3662 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3663 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3664 .access
= PL1_RW
, .resetvalue
= 0,
3665 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3666 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3667 .writefn
= par_write
},
3668 #ifndef CONFIG_USER_ONLY
3669 /* This underdecoding is safe because the reginfo is NO_RAW. */
3670 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3671 .access
= PL1_W
, .accessfn
= ats_access
,
3672 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3676 /* Return basic MPU access permission bits. */
3677 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3684 for (i
= 0; i
< 16; i
+= 2) {
3685 ret
|= (val
>> i
) & mask
;
3691 /* Pad basic MPU access permission bits to extended format. */
3692 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3699 for (i
= 0; i
< 16; i
+= 2) {
3700 ret
|= (val
& mask
) << i
;
3706 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3709 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3712 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3714 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3717 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3720 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3723 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3725 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3728 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3730 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3736 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3740 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3743 ARMCPU
*cpu
= env_archcpu(env
);
3744 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3750 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3751 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3755 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3758 ARMCPU
*cpu
= env_archcpu(env
);
3759 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3761 if (value
>= nrgs
) {
3762 qemu_log_mask(LOG_GUEST_ERROR
,
3763 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3764 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3768 raw_write(env
, ri
, value
);
3771 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3774 ARMCPU
*cpu
= env_archcpu(env
);
3776 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3777 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3780 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3782 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3785 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3788 ARMCPU
*cpu
= env_archcpu(env
);
3790 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3791 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3794 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3796 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3799 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3802 ARMCPU
*cpu
= env_archcpu(env
);
3805 * Ignore writes that would select not implemented region.
3806 * This is architecturally UNPREDICTABLE.
3808 if (value
>= cpu
->pmsav7_dregion
) {
3812 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3815 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3818 ARMCPU
*cpu
= env_archcpu(env
);
3820 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3821 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3824 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3826 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3829 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3832 ARMCPU
*cpu
= env_archcpu(env
);
3834 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3835 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3838 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3840 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3843 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3848 ARMCPU
*cpu
= env_archcpu(env
);
3850 /* Ignore writes to unimplemented regions */
3851 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3852 value
&= MAKE_64BIT_MASK(0, rmax
);
3854 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3856 /* Register alias is only valid for first 32 indexes */
3857 for (n
= 0; n
< rmax
; ++n
) {
3858 bit
= extract32(value
, n
, 1);
3859 env
->pmsav8
.hprlar
[n
] = deposit32(
3860 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3864 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3867 uint32_t result
= 0x0;
3868 ARMCPU
*cpu
= env_archcpu(env
);
3870 /* Register alias is only valid for first 32 indexes */
3871 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3872 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3873 result
|= (0x1 << n
);
3879 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3882 ARMCPU
*cpu
= env_archcpu(env
);
3885 * Ignore writes that would select not implemented region.
3886 * This is architecturally UNPREDICTABLE.
3888 if (value
>= cpu
->pmsav8r_hdregion
) {
3892 env
->pmsav8
.hprselr
= value
;
3895 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3898 ARMCPU
*cpu
= env_archcpu(env
);
3899 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3900 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3902 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3905 if (index
>= cpu
->pmsav8r_hdregion
) {
3908 if (ri
->opc2
& 0x1) {
3909 env
->pmsav8
.hprlar
[index
] = value
;
3911 env
->pmsav8
.hprbar
[index
] = value
;
3914 if (index
>= cpu
->pmsav7_dregion
) {
3917 if (ri
->opc2
& 0x1) {
3918 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
3920 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
3925 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3927 ARMCPU
*cpu
= env_archcpu(env
);
3928 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3929 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3932 if (index
>= cpu
->pmsav8r_hdregion
) {
3935 if (ri
->opc2
& 0x1) {
3936 return env
->pmsav8
.hprlar
[index
];
3938 return env
->pmsav8
.hprbar
[index
];
3941 if (index
>= cpu
->pmsav7_dregion
) {
3944 if (ri
->opc2
& 0x1) {
3945 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
3947 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
3952 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
3954 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
3955 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3956 .accessfn
= access_tvm_trvm
,
3957 .readfn
= prbar_read
, .writefn
= prbar_write
},
3959 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
3960 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3961 .accessfn
= access_tvm_trvm
,
3962 .readfn
= prlar_read
, .writefn
= prlar_write
},
3963 { .name
= "PRSELR", .resetvalue
= 0,
3964 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
3965 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3966 .writefn
= prselr_write
,
3967 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
3968 { .name
= "HPRBAR", .resetvalue
= 0,
3969 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
3970 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3971 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
3973 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
3974 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3975 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
3976 { .name
= "HPRSELR", .resetvalue
= 0,
3977 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
3979 .writefn
= hprselr_write
,
3980 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
3982 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
3983 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
3984 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
3987 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3989 * Reset for all these registers is handled in arm_cpu_reset(),
3990 * because the PMSAv7 is also used by M-profile CPUs, which do
3991 * not register cpregs but still need the state to be reset.
3993 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3994 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3995 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3996 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3997 .resetfn
= arm_cp_reset_ignore
},
3998 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3999 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4000 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4001 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4002 .resetfn
= arm_cp_reset_ignore
},
4003 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4004 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4005 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4006 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4007 .resetfn
= arm_cp_reset_ignore
},
4008 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4010 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4011 .writefn
= pmsav7_rgnr_write
,
4012 .resetfn
= arm_cp_reset_ignore
},
4015 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4016 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4017 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4018 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4019 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4020 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4021 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4022 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4023 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4024 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4026 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4028 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4030 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4032 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4034 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4035 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4037 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4038 /* Protection region base and size registers */
4039 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4040 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4041 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4042 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4043 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4045 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4046 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4047 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4048 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4049 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4050 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4051 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4052 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4053 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4054 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4055 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4056 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4057 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4058 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4059 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4060 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4061 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4062 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4065 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4068 ARMCPU
*cpu
= env_archcpu(env
);
4070 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4071 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4073 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4074 * using Long-descriptor translation table format
4076 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4077 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4079 * In an implementation that includes the Security Extensions
4080 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4081 * Short-descriptor translation table format.
4083 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4089 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4091 * With LPAE the TTBCR could result in a change of ASID
4092 * via the TTBCR.A1 bit, so do a TLB flush.
4094 tlb_flush(CPU(cpu
));
4096 raw_write(env
, ri
, value
);
4099 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4102 ARMCPU
*cpu
= env_archcpu(env
);
4104 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4105 tlb_flush(CPU(cpu
));
4106 raw_write(env
, ri
, value
);
4109 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4112 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4113 if (cpreg_field_is_64bit(ri
) &&
4114 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4115 ARMCPU
*cpu
= env_archcpu(env
);
4116 tlb_flush(CPU(cpu
));
4118 raw_write(env
, ri
, value
);
4121 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4125 * If we are running with E2&0 regime, then an ASID is active.
4126 * Flush if that might be changing. Note we're not checking
4127 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4128 * holds the active ASID, only checking the field that might.
4130 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4131 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4132 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4133 ARMMMUIdxBit_E20_2_PAN
|
4135 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4137 raw_write(env
, ri
, value
);
4140 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4143 ARMCPU
*cpu
= env_archcpu(env
);
4144 CPUState
*cs
= CPU(cpu
);
4147 * A change in VMID to the stage2 page table (Stage2) invalidates
4148 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4150 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4151 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4153 raw_write(env
, ri
, value
);
4156 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4157 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4158 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4159 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4160 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4161 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4162 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4163 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4164 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4165 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4166 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4167 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4168 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4169 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4170 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4171 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4173 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4177 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4178 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4179 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4180 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4182 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4183 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4184 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4185 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4186 .fgt
= FGT_TTBR0_EL1
,
4187 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4188 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4189 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4190 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4191 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4192 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4193 .fgt
= FGT_TTBR1_EL1
,
4194 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4195 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4196 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4197 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4198 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4199 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4201 .writefn
= vmsa_tcr_el12_write
,
4202 .raw_writefn
= raw_write
,
4204 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4205 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4206 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4207 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4208 .raw_writefn
= raw_write
,
4209 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4210 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4214 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4215 * qemu tlbs nor adjusting cached masks.
4217 static const ARMCPRegInfo ttbcr2_reginfo
= {
4218 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4219 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4220 .type
= ARM_CP_ALIAS
,
4221 .bank_fieldoffsets
= {
4222 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4223 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4227 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4230 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4231 /* The OS_TYPE bit in this register changes the reported CPUID! */
4232 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4233 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4236 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4239 env
->cp15
.c15_threadid
= value
& 0xffff;
4242 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4245 /* Wait-for-interrupt (deprecated) */
4246 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4249 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4253 * On OMAP there are registers indicating the max/min index of dcache lines
4254 * containing a dirty line; cache flush operations have to reset these.
4256 env
->cp15
.c15_i_max
= 0x000;
4257 env
->cp15
.c15_i_min
= 0xff0;
4260 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4261 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4262 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4263 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4265 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4266 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4267 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4269 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4270 .writefn
= omap_ticonfig_write
},
4271 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4273 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4274 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4275 .access
= PL1_RW
, .resetvalue
= 0xff0,
4276 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4277 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4279 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4280 .writefn
= omap_threadid_write
},
4281 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4282 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4283 .type
= ARM_CP_NO_RAW
,
4284 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4286 * TODO: Peripheral port remap register:
4287 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4288 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4291 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4292 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4293 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4294 .writefn
= omap_cachemaint_write
},
4295 { .name
= "C9", .cp
= 15, .crn
= 9,
4296 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4297 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4300 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4303 env
->cp15
.c15_cpar
= value
& 0x3fff;
4306 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4307 { .name
= "XSCALE_CPAR",
4308 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4309 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4310 .writefn
= xscale_cpar_write
, },
4311 { .name
= "XSCALE_AUXCR",
4312 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4313 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4316 * XScale specific cache-lockdown: since we have no cache we NOP these
4317 * and hope the guest does not really rely on cache behaviour.
4319 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4320 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4321 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4322 { .name
= "XSCALE_UNLOCK_ICACHE",
4323 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4324 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4325 { .name
= "XSCALE_DCACHE_LOCK",
4326 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4327 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4328 { .name
= "XSCALE_UNLOCK_DCACHE",
4329 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4330 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4333 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4335 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4336 * implementation of this implementation-defined space.
4337 * Ideally this should eventually disappear in favour of actually
4338 * implementing the correct behaviour for all cores.
4340 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4341 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4343 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4347 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4348 /* Cache status: RAZ because we have no cache so it's always clean */
4349 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4350 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4354 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4355 /* We never have a block transfer operation in progress */
4356 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4357 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4359 /* The cache ops themselves: these all NOP for QEMU */
4360 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4361 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4362 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4363 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4364 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4365 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4366 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4367 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4368 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4369 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4370 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4371 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4374 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4376 * The cache test-and-clean instructions always return (1 << 30)
4377 * to indicate that there are no dirty cache lines.
4379 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4380 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4381 .resetvalue
= (1 << 30) },
4382 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4383 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4384 .resetvalue
= (1 << 30) },
4387 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4388 /* Ignore ReadBuffer accesses */
4389 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4390 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4391 .access
= PL1_RW
, .resetvalue
= 0,
4392 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4395 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4397 unsigned int cur_el
= arm_current_el(env
);
4399 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4400 return env
->cp15
.vpidr_el2
;
4402 return raw_read(env
, ri
);
4405 static uint64_t mpidr_read_val(CPUARMState
*env
)
4407 ARMCPU
*cpu
= env_archcpu(env
);
4408 uint64_t mpidr
= cpu
->mp_affinity
;
4410 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4411 mpidr
|= (1U << 31);
4413 * Cores which are uniprocessor (non-coherent)
4414 * but still implement the MP extensions set
4415 * bit 30. (For instance, Cortex-R5).
4417 if (cpu
->mp_is_up
) {
4418 mpidr
|= (1u << 30);
4424 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4426 unsigned int cur_el
= arm_current_el(env
);
4428 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4429 return env
->cp15
.vmpidr_el2
;
4431 return mpidr_read_val(env
);
4434 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4436 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4437 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4438 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4439 .fgt
= FGT_AMAIR_EL1
,
4440 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4441 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4442 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4443 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4444 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4445 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4446 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4447 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4448 offsetof(CPUARMState
, cp15
.par_ns
)} },
4449 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4450 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4451 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4452 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4453 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4454 .writefn
= vmsa_ttbr_write
, },
4455 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4456 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4457 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4458 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4459 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4460 .writefn
= vmsa_ttbr_write
, },
4463 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4465 return vfp_get_fpcr(env
);
4468 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4471 vfp_set_fpcr(env
, value
);
4474 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4476 return vfp_get_fpsr(env
);
4479 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4482 vfp_set_fpsr(env
, value
);
4485 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4488 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4489 return CP_ACCESS_TRAP
;
4491 return CP_ACCESS_OK
;
4494 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4497 env
->daif
= value
& PSTATE_DAIF
;
4500 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4502 return env
->pstate
& PSTATE_PAN
;
4505 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4508 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4511 static const ARMCPRegInfo pan_reginfo
= {
4512 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4513 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4514 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4515 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4518 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4520 return env
->pstate
& PSTATE_UAO
;
4523 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4526 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4529 static const ARMCPRegInfo uao_reginfo
= {
4530 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4531 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4532 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4533 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4536 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4538 return env
->pstate
& PSTATE_DIT
;
4541 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4544 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4547 static const ARMCPRegInfo dit_reginfo
= {
4548 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4549 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4550 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4551 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4554 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4556 return env
->pstate
& PSTATE_SSBS
;
4559 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4562 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4565 static const ARMCPRegInfo ssbs_reginfo
= {
4566 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4567 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4568 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4569 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4572 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4573 const ARMCPRegInfo
*ri
,
4576 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4577 switch (arm_current_el(env
)) {
4579 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4580 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4581 return CP_ACCESS_TRAP
;
4585 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4586 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4587 return CP_ACCESS_TRAP_EL2
;
4591 return CP_ACCESS_OK
;
4594 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4596 /* Cache invalidate/clean to Point of Unification... */
4597 switch (arm_current_el(env
)) {
4599 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4600 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4601 return CP_ACCESS_TRAP
;
4605 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4606 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4607 return CP_ACCESS_TRAP_EL2
;
4611 return CP_ACCESS_OK
;
4614 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4617 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4620 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4623 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4627 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4628 * Page D4-1736 (DDI0487A.b)
4631 static int vae1_tlbmask(CPUARMState
*env
)
4633 uint64_t hcr
= arm_hcr_el2_eff(env
);
4636 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4637 mask
= ARMMMUIdxBit_E20_2
|
4638 ARMMMUIdxBit_E20_2_PAN
|
4641 mask
= ARMMMUIdxBit_E10_1
|
4642 ARMMMUIdxBit_E10_1_PAN
|
4648 /* Return 56 if TBI is enabled, 64 otherwise. */
4649 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4652 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4653 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4654 int select
= extract64(addr
, 55, 1);
4656 return (tbi
>> select
) & 1 ? 56 : 64;
4659 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4661 uint64_t hcr
= arm_hcr_el2_eff(env
);
4664 /* Only the regime of the mmu_idx below is significant. */
4665 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4666 mmu_idx
= ARMMMUIdx_E20_0
;
4668 mmu_idx
= ARMMMUIdx_E10_0
;
4671 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4674 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4677 CPUState
*cs
= env_cpu(env
);
4678 int mask
= vae1_tlbmask(env
);
4680 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4683 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4686 CPUState
*cs
= env_cpu(env
);
4687 int mask
= vae1_tlbmask(env
);
4689 if (tlb_force_broadcast(env
)) {
4690 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4692 tlb_flush_by_mmuidx(cs
, mask
);
4696 static int e2_tlbmask(CPUARMState
*env
)
4698 return (ARMMMUIdxBit_E20_0
|
4699 ARMMMUIdxBit_E20_2
|
4700 ARMMMUIdxBit_E20_2_PAN
|
4704 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4707 CPUState
*cs
= env_cpu(env
);
4708 int mask
= alle1_tlbmask(env
);
4710 tlb_flush_by_mmuidx(cs
, mask
);
4713 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4716 CPUState
*cs
= env_cpu(env
);
4717 int mask
= e2_tlbmask(env
);
4719 tlb_flush_by_mmuidx(cs
, mask
);
4722 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4725 ARMCPU
*cpu
= env_archcpu(env
);
4726 CPUState
*cs
= CPU(cpu
);
4728 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4731 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4734 CPUState
*cs
= env_cpu(env
);
4735 int mask
= alle1_tlbmask(env
);
4737 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4740 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4743 CPUState
*cs
= env_cpu(env
);
4744 int mask
= e2_tlbmask(env
);
4746 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4749 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4752 CPUState
*cs
= env_cpu(env
);
4754 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4757 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4761 * Invalidate by VA, EL2
4762 * Currently handles both VAE2 and VALE2, since we don't support
4763 * flush-last-level-only.
4765 CPUState
*cs
= env_cpu(env
);
4766 int mask
= e2_tlbmask(env
);
4767 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4769 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4772 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4776 * Invalidate by VA, EL3
4777 * Currently handles both VAE3 and VALE3, since we don't support
4778 * flush-last-level-only.
4780 ARMCPU
*cpu
= env_archcpu(env
);
4781 CPUState
*cs
= CPU(cpu
);
4782 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4784 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4787 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4790 CPUState
*cs
= env_cpu(env
);
4791 int mask
= vae1_tlbmask(env
);
4792 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4793 int bits
= vae1_tlbbits(env
, pageaddr
);
4795 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4798 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4802 * Invalidate by VA, EL1&0 (AArch64 version).
4803 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4804 * since we don't support flush-for-specific-ASID-only or
4805 * flush-last-level-only.
4807 CPUState
*cs
= env_cpu(env
);
4808 int mask
= vae1_tlbmask(env
);
4809 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4810 int bits
= vae1_tlbbits(env
, pageaddr
);
4812 if (tlb_force_broadcast(env
)) {
4813 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4815 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4819 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4822 CPUState
*cs
= env_cpu(env
);
4823 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4824 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E2
, pageaddr
);
4826 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4827 ARMMMUIdxBit_E2
, bits
);
4830 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4833 CPUState
*cs
= env_cpu(env
);
4834 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4835 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4837 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4838 ARMMMUIdxBit_E3
, bits
);
4841 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4844 * The MSB of value is the NS field, which only applies if SEL2
4845 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4848 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4849 && arm_is_secure_below_el3(env
)
4850 ? ARMMMUIdxBit_Stage2_S
4851 : ARMMMUIdxBit_Stage2
);
4854 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4857 CPUState
*cs
= env_cpu(env
);
4858 int mask
= ipas2e1_tlbmask(env
, value
);
4859 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4861 if (tlb_force_broadcast(env
)) {
4862 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4864 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4868 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4871 CPUState
*cs
= env_cpu(env
);
4872 int mask
= ipas2e1_tlbmask(env
, value
);
4873 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4875 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4878 #ifdef TARGET_AARCH64
4884 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
4887 * Note that the TLBI range TG field encoding differs from both
4888 * TG0 and TG1 encodings.
4902 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4905 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4906 /* Extract one bit to represent the va selector in use. */
4907 uint64_t select
= sextract64(value
, 36, 1);
4908 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4909 TLBIRange ret
= { };
4910 ARMGranuleSize gran
;
4912 page_size_granule
= extract64(value
, 46, 2);
4913 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
4915 /* The granule encoded in value must match the granule in use. */
4916 if (gran
!= param
.gran
) {
4917 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4922 page_shift
= arm_granule_bits(gran
);
4923 num
= extract64(value
, 39, 5);
4924 scale
= extract64(value
, 44, 2);
4925 exponent
= (5 * scale
) + 1;
4927 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4930 ret
.base
= sextract64(value
, 0, 37);
4932 ret
.base
= extract64(value
, 0, 37);
4936 * With DS=1, BaseADDR is always shifted 16 so that it is able
4937 * to address all 52 va bits. The input address is perforce
4938 * aligned on a 64k boundary regardless of translation granule.
4942 ret
.base
<<= page_shift
;
4947 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4948 int idxmap
, bool synced
)
4950 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4954 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4955 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4958 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4964 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4965 range
.length
, idxmap
, bits
);
4969 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4970 const ARMCPRegInfo
*ri
,
4974 * Invalidate by VA range, EL1&0.
4975 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4976 * since we don't support flush-for-specific-ASID-only or
4977 * flush-last-level-only.
4980 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4981 tlb_force_broadcast(env
));
4984 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4985 const ARMCPRegInfo
*ri
,
4989 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4990 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4991 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4992 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4993 * shareable specific flushes.
4996 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4999 static int vae2_tlbmask(CPUARMState
*env
)
5001 return ARMMMUIdxBit_E2
;
5004 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5005 const ARMCPRegInfo
*ri
,
5009 * Invalidate by VA range, EL2.
5010 * Currently handles all of RVAE2 and RVALE2,
5011 * since we don't support flush-for-specific-ASID-only or
5012 * flush-last-level-only.
5015 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5016 tlb_force_broadcast(env
));
5021 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5022 const ARMCPRegInfo
*ri
,
5026 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5027 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5028 * since we don't support flush-for-specific-ASID-only,
5029 * flush-last-level-only or inner/outer shareable specific flushes.
5032 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5036 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5037 const ARMCPRegInfo
*ri
,
5041 * Invalidate by VA range, EL3.
5042 * Currently handles all of RVAE3 and RVALE3,
5043 * since we don't support flush-for-specific-ASID-only or
5044 * flush-last-level-only.
5047 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5050 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5051 const ARMCPRegInfo
*ri
,
5055 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5056 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5057 * since we don't support flush-for-specific-ASID-only,
5058 * flush-last-level-only or inner/outer specific flushes.
5061 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5064 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5067 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5068 tlb_force_broadcast(env
));
5071 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5072 const ARMCPRegInfo
*ri
,
5075 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5079 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5082 int cur_el
= arm_current_el(env
);
5085 uint64_t hcr
= arm_hcr_el2_eff(env
);
5088 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5089 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5090 return CP_ACCESS_TRAP_EL2
;
5093 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5094 return CP_ACCESS_TRAP
;
5096 if (hcr
& HCR_TDZ
) {
5097 return CP_ACCESS_TRAP_EL2
;
5100 } else if (hcr
& HCR_TDZ
) {
5101 return CP_ACCESS_TRAP_EL2
;
5104 return CP_ACCESS_OK
;
5107 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5109 ARMCPU
*cpu
= env_archcpu(env
);
5110 int dzp_bit
= 1 << 4;
5112 /* DZP indicates whether DC ZVA access is allowed */
5113 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5116 return cpu
->dcz_blocksize
| dzp_bit
;
5119 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5122 if (!(env
->pstate
& PSTATE_SP
)) {
5124 * Access to SP_EL0 is undefined if it's being used as
5125 * the stack pointer.
5127 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5129 return CP_ACCESS_OK
;
5132 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5134 return env
->pstate
& PSTATE_SP
;
5137 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5139 update_spsel(env
, val
);
5142 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5145 ARMCPU
*cpu
= env_archcpu(env
);
5147 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5148 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5152 /* ??? Lots of these bits are not implemented. */
5154 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5155 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5156 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5158 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5159 SCTLR_ATA0
| SCTLR_ATA
);
5163 if (raw_read(env
, ri
) == value
) {
5165 * Skip the TLB flush if nothing actually changed; Linux likes
5166 * to do a lot of pointless SCTLR writes.
5171 raw_write(env
, ri
, value
);
5173 /* This may enable/disable the MMU, so do a TLB flush. */
5174 tlb_flush(CPU(cpu
));
5176 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5178 * Normally we would always end the TB on an SCTLR write; see the
5179 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5180 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5181 * of hflags from the translator, so do it here.
5183 arm_rebuild_hflags(env
);
5187 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5191 * Some MDCR_EL3 bits affect whether PMU counters are running:
5192 * if we are trying to change any of those then we must
5193 * bracket this update with PMU start/finish calls.
5195 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5200 env
->cp15
.mdcr_el3
= value
;
5206 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5209 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5210 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5213 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5217 * Some MDCR_EL2 bits affect whether PMU counters are running:
5218 * if we are trying to change any of those then we must
5219 * bracket this update with PMU start/finish calls.
5221 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5226 env
->cp15
.mdcr_el2
= value
;
5232 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5234 * Minimal set of EL0-visible registers. This will need to be expanded
5235 * significantly for system emulation of AArch64 CPUs.
5237 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5238 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5239 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5240 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5241 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5242 .type
= ARM_CP_NO_RAW
,
5243 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5244 .fieldoffset
= offsetof(CPUARMState
, daif
),
5245 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5246 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5247 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5248 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5249 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5250 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5251 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5252 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5253 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5254 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5255 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5256 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5257 .fgt
= FGT_DCZID_EL0
,
5258 .readfn
= aa64_dczid_read
},
5259 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5260 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5261 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5262 #ifndef CONFIG_USER_ONLY
5263 /* Avoid overhead of an access check that always passes in user-mode */
5264 .accessfn
= aa64_zva_access
,
5268 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5269 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5270 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5271 /* Cache ops: all NOPs since we don't emulate caches */
5272 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5273 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5274 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5275 .fgt
= FGT_ICIALLUIS
,
5276 .accessfn
= access_ticab
},
5277 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5278 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5279 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5281 .accessfn
= access_tocu
},
5282 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5283 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5284 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5286 .accessfn
= access_tocu
},
5287 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5288 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5289 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5291 .type
= ARM_CP_NOP
},
5292 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5293 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5295 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5296 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5297 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5298 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5300 .accessfn
= aa64_cacheop_poc_access
},
5301 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5302 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5304 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5305 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5306 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5307 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5309 .accessfn
= access_tocu
},
5310 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5311 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5312 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5314 .accessfn
= aa64_cacheop_poc_access
},
5315 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5316 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5318 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5319 /* TLBI operations */
5320 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5321 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5322 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5323 .fgt
= FGT_TLBIVMALLE1IS
,
5324 .writefn
= tlbi_aa64_vmalle1is_write
},
5325 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5326 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5327 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5328 .fgt
= FGT_TLBIVAE1IS
,
5329 .writefn
= tlbi_aa64_vae1is_write
},
5330 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5331 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5332 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5333 .fgt
= FGT_TLBIASIDE1IS
,
5334 .writefn
= tlbi_aa64_vmalle1is_write
},
5335 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5336 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5337 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5338 .fgt
= FGT_TLBIVAAE1IS
,
5339 .writefn
= tlbi_aa64_vae1is_write
},
5340 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5341 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5342 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5343 .fgt
= FGT_TLBIVALE1IS
,
5344 .writefn
= tlbi_aa64_vae1is_write
},
5345 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5346 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5347 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5348 .fgt
= FGT_TLBIVAALE1IS
,
5349 .writefn
= tlbi_aa64_vae1is_write
},
5350 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5351 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5352 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5353 .fgt
= FGT_TLBIVMALLE1
,
5354 .writefn
= tlbi_aa64_vmalle1_write
},
5355 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5356 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5357 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5358 .fgt
= FGT_TLBIVAE1
,
5359 .writefn
= tlbi_aa64_vae1_write
},
5360 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5361 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5362 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5363 .fgt
= FGT_TLBIASIDE1
,
5364 .writefn
= tlbi_aa64_vmalle1_write
},
5365 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5366 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5367 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5368 .fgt
= FGT_TLBIVAAE1
,
5369 .writefn
= tlbi_aa64_vae1_write
},
5370 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5371 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5372 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5373 .fgt
= FGT_TLBIVALE1
,
5374 .writefn
= tlbi_aa64_vae1_write
},
5375 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5376 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5377 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5378 .fgt
= FGT_TLBIVAALE1
,
5379 .writefn
= tlbi_aa64_vae1_write
},
5380 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5381 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5382 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5383 .writefn
= tlbi_aa64_ipas2e1is_write
},
5384 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5385 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5386 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5387 .writefn
= tlbi_aa64_ipas2e1is_write
},
5388 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5389 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5390 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5391 .writefn
= tlbi_aa64_alle1is_write
},
5392 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5393 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5394 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5395 .writefn
= tlbi_aa64_alle1is_write
},
5396 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5397 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5398 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5399 .writefn
= tlbi_aa64_ipas2e1_write
},
5400 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5401 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5402 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5403 .writefn
= tlbi_aa64_ipas2e1_write
},
5404 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5405 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5406 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5407 .writefn
= tlbi_aa64_alle1_write
},
5408 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5409 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5410 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5411 .writefn
= tlbi_aa64_alle1is_write
},
5412 #ifndef CONFIG_USER_ONLY
5413 /* 64 bit address translation operations */
5414 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5415 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5416 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5418 .writefn
= ats_write64
},
5419 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5420 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5421 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5423 .writefn
= ats_write64
},
5424 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5425 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5426 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5428 .writefn
= ats_write64
},
5429 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5430 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5431 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5433 .writefn
= ats_write64
},
5434 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5435 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5436 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5437 .writefn
= ats_write64
},
5438 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5439 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5440 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5441 .writefn
= ats_write64
},
5442 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5443 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5444 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5445 .writefn
= ats_write64
},
5446 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5447 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5448 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5449 .writefn
= ats_write64
},
5450 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5451 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5452 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5453 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5454 .writefn
= ats_write64
},
5455 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5456 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5457 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5458 .writefn
= ats_write64
},
5459 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5460 .type
= ARM_CP_ALIAS
,
5461 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5462 .access
= PL1_RW
, .resetvalue
= 0,
5464 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5465 .writefn
= par_write
},
5467 /* TLB invalidate last level of translation table walk */
5468 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5469 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5470 .writefn
= tlbimva_is_write
},
5471 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5472 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5473 .writefn
= tlbimvaa_is_write
},
5474 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5475 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5476 .writefn
= tlbimva_write
},
5477 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5478 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5479 .writefn
= tlbimvaa_write
},
5480 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5481 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5482 .writefn
= tlbimva_hyp_write
},
5483 { .name
= "TLBIMVALHIS",
5484 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5485 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5486 .writefn
= tlbimva_hyp_is_write
},
5487 { .name
= "TLBIIPAS2",
5488 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5489 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5490 .writefn
= tlbiipas2_hyp_write
},
5491 { .name
= "TLBIIPAS2IS",
5492 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5493 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5494 .writefn
= tlbiipas2is_hyp_write
},
5495 { .name
= "TLBIIPAS2L",
5496 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5497 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5498 .writefn
= tlbiipas2_hyp_write
},
5499 { .name
= "TLBIIPAS2LIS",
5500 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5501 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5502 .writefn
= tlbiipas2is_hyp_write
},
5503 /* 32 bit cache operations */
5504 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5505 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5506 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5507 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5508 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5509 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5510 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5511 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5512 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5513 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5514 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5515 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5516 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5517 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5518 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5519 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5520 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5521 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5522 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5523 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5524 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5525 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5526 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5527 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5528 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5529 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5530 /* MMU Domain access control / MPU write buffer control */
5531 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5532 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5533 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5534 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5535 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5536 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5537 .type
= ARM_CP_ALIAS
,
5538 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5540 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5541 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5542 .type
= ARM_CP_ALIAS
,
5543 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5545 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5547 * We rely on the access checks not allowing the guest to write to the
5548 * state field when SPSel indicates that it's being used as the stack
5551 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5552 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5553 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5554 .type
= ARM_CP_ALIAS
,
5555 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5556 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5557 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5558 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5559 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5560 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5561 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5562 .type
= ARM_CP_NO_RAW
,
5563 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5564 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5565 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5567 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5568 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5569 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5570 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5571 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5572 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5573 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5574 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5575 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5576 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5577 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5578 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5579 .type
= ARM_CP_ALIAS
,
5580 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5582 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5583 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5584 .type
= ARM_CP_ALIAS
,
5585 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5587 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5588 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5589 .type
= ARM_CP_ALIAS
,
5590 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5592 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5593 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5594 .type
= ARM_CP_ALIAS
,
5595 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5597 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5598 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5600 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5603 .writefn
= mdcr_el3_write
,
5604 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5605 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5606 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5607 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5608 .writefn
= sdcr_write
,
5609 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5612 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5614 ARMCPU
*cpu
= env_archcpu(env
);
5616 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5617 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5619 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5622 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5623 valid_mask
&= ~HCR_HCD
;
5624 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5626 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5627 * However, if we're using the SMC PSCI conduit then QEMU is
5628 * effectively acting like EL3 firmware and so the guest at
5629 * EL2 should retain the ability to prevent EL1 from being
5630 * able to make SMC calls into the ersatz firmware, so in
5631 * that case HCR.TSC should be read/write.
5633 valid_mask
&= ~HCR_TSC
;
5636 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5637 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5638 valid_mask
|= HCR_E2H
;
5640 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5641 valid_mask
|= HCR_TERR
| HCR_TEA
;
5643 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5644 valid_mask
|= HCR_TLOR
;
5646 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5647 valid_mask
|= HCR_API
| HCR_APK
;
5649 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5650 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5652 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5653 valid_mask
|= HCR_ENSCXT
;
5655 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5656 valid_mask
|= HCR_FWB
;
5660 if (cpu_isar_feature(any_evt
, cpu
)) {
5661 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5662 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5663 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5666 /* Clear RES0 bits. */
5667 value
&= valid_mask
;
5670 * These bits change the MMU setup:
5671 * HCR_VM enables stage 2 translation
5672 * HCR_PTW forbids certain page-table setups
5673 * HCR_DC disables stage1 and enables stage2 translation
5674 * HCR_DCT enables tagging on (disabled) stage1 translation
5675 * HCR_FWB changes the interpretation of stage2 descriptor bits
5677 if ((env
->cp15
.hcr_el2
^ value
) &
5678 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5679 tlb_flush(CPU(cpu
));
5681 env
->cp15
.hcr_el2
= value
;
5684 * Updates to VI and VF require us to update the status of
5685 * virtual interrupts, which are the logical OR of these bits
5686 * and the state of the input lines from the GIC. (This requires
5687 * that we have the iothread lock, which is done by marking the
5688 * reginfo structs as ARM_CP_IO.)
5689 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5690 * possible for it to be taken immediately, because VIRQ and
5691 * VFIQ are masked unless running at EL0 or EL1, and HCR
5692 * can only be written at EL2.
5694 g_assert(qemu_mutex_iothread_locked());
5695 arm_cpu_update_virq(cpu
);
5696 arm_cpu_update_vfiq(cpu
);
5697 arm_cpu_update_vserr(cpu
);
5700 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5702 do_hcr_write(env
, value
, 0);
5705 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5708 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5709 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5710 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5713 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5716 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5717 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5718 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5722 * Return the effective value of HCR_EL2, at the given security state.
5723 * Bits that are not included here:
5724 * RW (read from SCR_EL3.RW as needed)
5726 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, bool secure
)
5728 uint64_t ret
= env
->cp15
.hcr_el2
;
5730 if (!arm_is_el2_enabled_secstate(env
, secure
)) {
5732 * "This register has no effect if EL2 is not enabled in the
5733 * current Security state". This is ARMv8.4-SecEL2 speak for
5734 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5736 * Prior to that, the language was "In an implementation that
5737 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5738 * as if this field is 0 for all purposes other than a direct
5739 * read or write access of HCR_EL2". With lots of enumeration
5740 * on a per-field basis. In current QEMU, this is condition
5741 * is arm_is_secure_below_el3.
5743 * Since the v8.4 language applies to the entire register, and
5744 * appears to be backward compatible, use that.
5750 * For a cpu that supports both aarch64 and aarch32, we can set bits
5751 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5752 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5754 if (!arm_el_is_aa64(env
, 2)) {
5755 uint64_t aa32_valid
;
5758 * These bits are up-to-date as of ARMv8.6.
5759 * For HCR, it's easiest to list just the 2 bits that are invalid.
5760 * For HCR2, list those that are valid.
5762 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5763 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5764 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5768 if (ret
& HCR_TGE
) {
5769 /* These bits are up-to-date as of ARMv8.6. */
5770 if (ret
& HCR_E2H
) {
5771 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5772 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5773 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5774 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5775 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5776 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5778 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5780 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5781 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5782 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5789 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5791 return arm_hcr_el2_eff_secstate(env
, arm_is_secure_below_el3(env
));
5795 * Corresponds to ARM pseudocode function ELIsInHost().
5797 bool el_is_in_host(CPUARMState
*env
, int el
)
5802 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5803 * Perform the simplest bit tests first, and validate EL2 afterward.
5806 return false; /* EL1 or EL3 */
5810 * Note that hcr_write() checks isar_feature_aa64_vh(),
5811 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5813 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5814 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5818 /* TGE and/or E2H set: double check those bits are currently legal. */
5819 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5822 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5825 uint64_t valid_mask
= 0;
5827 /* No features adding bits to HCRX are implemented. */
5829 /* Clear RES0 bits. */
5830 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5833 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5836 if (arm_current_el(env
) < 3
5837 && arm_feature(env
, ARM_FEATURE_EL3
)
5838 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5839 return CP_ACCESS_TRAP_EL3
;
5841 return CP_ACCESS_OK
;
5844 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5845 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5846 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5847 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5848 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5851 /* Return the effective value of HCRX_EL2. */
5852 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5855 * The bits in this register behave as 0 for all purposes other than
5856 * direct reads of the register if:
5857 * - EL2 is not enabled in the current security state,
5858 * - SCR_EL3.HXEn is 0.
5860 if (!arm_is_el2_enabled(env
)
5861 || (arm_feature(env
, ARM_FEATURE_EL3
)
5862 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5865 return env
->cp15
.hcrx_el2
;
5868 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5872 * For A-profile AArch32 EL3, if NSACR.CP10
5873 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5875 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5876 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5877 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5878 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5880 env
->cp15
.cptr_el
[2] = value
;
5883 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5886 * For A-profile AArch32 EL3, if NSACR.CP10
5887 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5889 uint64_t value
= env
->cp15
.cptr_el
[2];
5891 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5892 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5893 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5898 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5899 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5901 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5902 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5903 .writefn
= hcr_write
},
5904 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5905 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5906 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5907 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5908 .writefn
= hcr_writelow
},
5909 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5910 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5911 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5912 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5913 .type
= ARM_CP_ALIAS
,
5914 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5916 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5917 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5918 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5919 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5920 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5921 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5922 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5923 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5924 .type
= ARM_CP_ALIAS
,
5925 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5927 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5928 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5929 .type
= ARM_CP_ALIAS
,
5930 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5932 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5933 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5934 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5935 .access
= PL2_RW
, .writefn
= vbar_write
,
5936 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5938 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5939 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5940 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5941 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5942 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5943 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5944 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5945 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5946 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5947 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5948 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5949 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5951 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5952 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5953 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5954 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5955 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5956 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5957 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5959 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5960 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5961 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5962 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5964 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5965 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5966 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5968 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5969 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5970 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5972 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5973 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5974 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5975 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5976 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5977 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5978 .type
= ARM_CP_ALIAS
,
5979 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5980 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
5981 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5982 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5984 /* no .writefn needed as this can't cause an ASID change */
5985 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5986 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5987 .cp
= 15, .opc1
= 6, .crm
= 2,
5988 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5989 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5990 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5991 .writefn
= vttbr_write
},
5992 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5993 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5994 .access
= PL2_RW
, .writefn
= vttbr_write
,
5995 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5996 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5997 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5998 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5999 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6000 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6001 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6002 .access
= PL2_RW
, .resetvalue
= 0,
6003 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6004 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6005 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6006 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
6007 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6008 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6009 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6010 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6011 { .name
= "TLBIALLNSNH",
6012 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6013 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6014 .writefn
= tlbiall_nsnh_write
},
6015 { .name
= "TLBIALLNSNHIS",
6016 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6017 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6018 .writefn
= tlbiall_nsnh_is_write
},
6019 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6020 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6021 .writefn
= tlbiall_hyp_write
},
6022 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6023 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6024 .writefn
= tlbiall_hyp_is_write
},
6025 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6026 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6027 .writefn
= tlbimva_hyp_write
},
6028 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6029 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6030 .writefn
= tlbimva_hyp_is_write
},
6031 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6032 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6033 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6034 .writefn
= tlbi_aa64_alle2_write
},
6035 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6036 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6037 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6038 .writefn
= tlbi_aa64_vae2_write
},
6039 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6040 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6041 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6042 .writefn
= tlbi_aa64_vae2_write
},
6043 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6044 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6045 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6046 .writefn
= tlbi_aa64_alle2is_write
},
6047 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6048 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6049 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6050 .writefn
= tlbi_aa64_vae2is_write
},
6051 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6052 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6053 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6054 .writefn
= tlbi_aa64_vae2is_write
},
6055 #ifndef CONFIG_USER_ONLY
6057 * Unlike the other EL2-related AT operations, these must
6058 * UNDEF from EL3 if EL2 is not implemented, which is why we
6059 * define them here rather than with the rest of the AT ops.
6061 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6062 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6063 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6064 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6065 .writefn
= ats_write64
},
6066 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6067 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6068 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6069 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6070 .writefn
= ats_write64
},
6072 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6073 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6074 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6075 * to behave as if SCR.NS was 1.
6077 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6079 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6080 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6082 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6083 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6084 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6086 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6087 * reset values as IMPDEF. We choose to reset to 3 to comply with
6088 * both ARMv7 and ARMv8.
6090 .access
= PL2_RW
, .resetvalue
= 3,
6091 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6092 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6093 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6094 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6095 .writefn
= gt_cntvoff_write
,
6096 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6097 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6098 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6099 .writefn
= gt_cntvoff_write
,
6100 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6101 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6102 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6104 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6105 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6106 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6107 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6108 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6109 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6110 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6111 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6112 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6113 .resetfn
= gt_hyp_timer_reset
,
6114 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6115 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6117 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6119 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6121 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6123 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6124 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6125 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6126 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6127 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6128 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6130 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6131 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6132 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6134 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6137 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6138 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6139 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6140 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6142 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6143 .writefn
= hcr_writehigh
},
6146 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6149 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6150 return CP_ACCESS_OK
;
6152 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6155 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6156 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6157 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6158 .access
= PL2_RW
, .accessfn
= sel2_access
,
6159 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6160 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6161 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6162 .access
= PL2_RW
, .accessfn
= sel2_access
,
6163 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6166 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6170 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6171 * At Secure EL1 it traps to EL3 or EL2.
6173 if (arm_current_el(env
) == 3) {
6174 return CP_ACCESS_OK
;
6176 if (arm_is_secure_below_el3(env
)) {
6177 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6178 return CP_ACCESS_TRAP_EL2
;
6180 return CP_ACCESS_TRAP_EL3
;
6182 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6184 return CP_ACCESS_OK
;
6186 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6189 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6190 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6191 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6192 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6193 .resetfn
= scr_reset
, .writefn
= scr_write
},
6194 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6195 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6196 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6197 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6198 .writefn
= scr_write
},
6199 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6200 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6201 .access
= PL3_RW
, .resetvalue
= 0,
6202 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6204 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6205 .access
= PL3_RW
, .resetvalue
= 0,
6206 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6207 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6208 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6209 .writefn
= vbar_write
, .resetvalue
= 0,
6210 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6211 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6212 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6213 .access
= PL3_RW
, .resetvalue
= 0,
6214 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6215 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6216 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6218 /* no .writefn needed as this can't cause an ASID change */
6220 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6221 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6222 .type
= ARM_CP_ALIAS
,
6223 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6225 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6226 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6227 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6228 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6229 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6230 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6231 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6232 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6233 .type
= ARM_CP_ALIAS
,
6234 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6236 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6237 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6238 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6239 .access
= PL3_RW
, .writefn
= vbar_write
,
6240 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6242 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6243 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6244 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6245 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6246 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6247 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6248 .access
= PL3_RW
, .resetvalue
= 0,
6249 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6250 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6251 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6252 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6254 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6255 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6256 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6258 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6259 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6260 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6262 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6263 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6264 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6265 .writefn
= tlbi_aa64_alle3is_write
},
6266 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6267 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6268 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6269 .writefn
= tlbi_aa64_vae3is_write
},
6270 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6271 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6272 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6273 .writefn
= tlbi_aa64_vae3is_write
},
6274 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6275 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6276 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6277 .writefn
= tlbi_aa64_alle3_write
},
6278 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6279 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6280 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6281 .writefn
= tlbi_aa64_vae3_write
},
6282 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6283 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6284 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6285 .writefn
= tlbi_aa64_vae3_write
},
6288 #ifndef CONFIG_USER_ONLY
6289 /* Test if system register redirection is to occur in the current state. */
6290 static bool redirect_for_e2h(CPUARMState
*env
)
6292 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6295 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6299 if (redirect_for_e2h(env
)) {
6300 /* Switch to the saved EL2 version of the register. */
6302 readfn
= ri
->readfn
;
6304 readfn
= ri
->orig_readfn
;
6306 if (readfn
== NULL
) {
6309 return readfn(env
, ri
);
6312 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6317 if (redirect_for_e2h(env
)) {
6318 /* Switch to the saved EL2 version of the register. */
6320 writefn
= ri
->writefn
;
6322 writefn
= ri
->orig_writefn
;
6324 if (writefn
== NULL
) {
6325 writefn
= raw_write
;
6327 writefn(env
, ri
, value
);
6330 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6333 uint32_t src_key
, dst_key
, new_key
;
6334 const char *src_name
, *dst_name
, *new_name
;
6335 bool (*feature
)(const ARMISARegisters
*id
);
6338 #define K(op0, op1, crn, crm, op2) \
6339 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6341 static const struct E2HAlias aliases
[] = {
6342 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6343 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6344 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6345 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6346 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6347 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6348 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6349 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6350 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6351 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6352 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6353 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6354 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6355 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6356 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6357 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6358 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6359 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6360 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6361 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6362 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6363 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6364 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6365 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6366 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6367 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6368 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6369 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6370 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6371 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6372 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6373 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6376 * Note that redirection of ZCR is mentioned in the description
6377 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6378 * not in the summary table.
6380 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6381 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6382 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6383 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6385 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6386 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6388 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6389 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6390 isar_feature_aa64_scxtnum
},
6392 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6393 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6399 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6400 const struct E2HAlias
*a
= &aliases
[i
];
6401 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6404 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6408 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6409 (gpointer
)(uintptr_t)a
->src_key
);
6410 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6411 (gpointer
)(uintptr_t)a
->dst_key
);
6412 g_assert(src_reg
!= NULL
);
6413 g_assert(dst_reg
!= NULL
);
6415 /* Cross-compare names to detect typos in the keys. */
6416 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6417 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6419 /* None of the core system registers use opaque; we will. */
6420 g_assert(src_reg
->opaque
== NULL
);
6422 /* Create alias before redirection so we dup the right data. */
6423 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6425 new_reg
->name
= a
->new_name
;
6426 new_reg
->type
|= ARM_CP_ALIAS
;
6427 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6428 new_reg
->access
&= PL2_RW
| PL3_RW
;
6430 ok
= g_hash_table_insert(cpu
->cp_regs
,
6431 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6434 src_reg
->opaque
= dst_reg
;
6435 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6436 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6437 if (!src_reg
->raw_readfn
) {
6438 src_reg
->raw_readfn
= raw_read
;
6440 if (!src_reg
->raw_writefn
) {
6441 src_reg
->raw_writefn
= raw_write
;
6443 src_reg
->readfn
= el2_e2h_read
;
6444 src_reg
->writefn
= el2_e2h_write
;
6449 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6452 int cur_el
= arm_current_el(env
);
6455 uint64_t hcr
= arm_hcr_el2_eff(env
);
6458 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6459 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6460 return CP_ACCESS_TRAP_EL2
;
6463 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6464 return CP_ACCESS_TRAP
;
6466 if (hcr
& HCR_TID2
) {
6467 return CP_ACCESS_TRAP_EL2
;
6470 } else if (hcr
& HCR_TID2
) {
6471 return CP_ACCESS_TRAP_EL2
;
6475 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6476 return CP_ACCESS_TRAP_EL2
;
6479 return CP_ACCESS_OK
;
6483 * Check for traps to RAS registers, which are controlled
6484 * by HCR_EL2.TERR and SCR_EL3.TERR.
6486 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6489 int el
= arm_current_el(env
);
6491 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6492 return CP_ACCESS_TRAP_EL2
;
6494 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6495 return CP_ACCESS_TRAP_EL3
;
6497 return CP_ACCESS_OK
;
6500 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6502 int el
= arm_current_el(env
);
6504 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6505 return env
->cp15
.vdisr_el2
;
6507 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6508 return 0; /* RAZ/WI */
6510 return env
->cp15
.disr_el1
;
6513 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6515 int el
= arm_current_el(env
);
6517 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6518 env
->cp15
.vdisr_el2
= val
;
6521 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6522 return; /* RAZ/WI */
6524 env
->cp15
.disr_el1
= val
;
6528 * Minimal RAS implementation with no Error Records.
6529 * Which means that all of the Error Record registers:
6537 * ERXPFGCDN_EL1 (RASv1p1)
6538 * ERXPFGCTL_EL1 (RASv1p1)
6539 * ERXPFGF_EL1 (RASv1p1)
6543 * may generate UNDEFINED, which is the effect we get by not
6544 * listing them at all.
6546 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6547 * is higher priority than FGT-to-EL2 so we do not need to list them
6548 * in order to check for an FGT.
6550 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6551 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6552 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6553 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6554 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6555 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6556 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6557 .access
= PL1_R
, .accessfn
= access_terr
,
6558 .fgt
= FGT_ERRIDR_EL1
,
6559 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6560 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6561 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6562 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6563 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6564 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6565 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6569 * Return the exception level to which exceptions should be taken
6570 * via SVEAccessTrap. This excludes the check for whether the exception
6571 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6572 * be found by testing 0 < fp_exception_el < sve_exception_el.
6574 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6575 * pseudocode does *not* separate out the FP trap checks, but has them
6576 * all in one function.
6578 int sve_exception_el(CPUARMState
*env
, int el
)
6580 #ifndef CONFIG_USER_ONLY
6581 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6582 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6594 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6595 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6596 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6597 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6599 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6608 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6614 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6615 if (arm_feature(env
, ARM_FEATURE_EL3
)
6616 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6624 * Return the exception level to which exceptions should be taken for SME.
6625 * C.f. the ARM pseudocode function CheckSMEAccess.
6627 int sme_exception_el(CPUARMState
*env
, int el
)
6629 #ifndef CONFIG_USER_ONLY
6630 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6631 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6643 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6644 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6645 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6646 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6648 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6657 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6663 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6664 if (arm_feature(env
, ARM_FEATURE_EL3
)
6665 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6672 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
6673 static bool sme_fa64(CPUARMState
*env
, int el
)
6675 if (!cpu_isar_feature(aa64_sme_fa64
, env_archcpu(env
))) {
6679 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6680 if (!FIELD_EX64(env
->vfp
.smcr_el
[1], SMCR
, FA64
)) {
6684 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6685 if (!FIELD_EX64(env
->vfp
.smcr_el
[2], SMCR
, FA64
)) {
6689 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6690 if (!FIELD_EX64(env
->vfp
.smcr_el
[3], SMCR
, FA64
)) {
6699 * Given that SVE is enabled, return the vector length for EL.
6701 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6703 ARMCPU
*cpu
= env_archcpu(env
);
6704 uint64_t *cr
= env
->vfp
.zcr_el
;
6705 uint32_t map
= cpu
->sve_vq
.map
;
6706 uint32_t len
= ARM_MAX_VQ
- 1;
6709 cr
= env
->vfp
.smcr_el
;
6710 map
= cpu
->sme_vq
.map
;
6713 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6714 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6716 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6717 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6719 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6720 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6723 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6725 return 31 - clz32(map
);
6728 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6730 return ctz32(cpu
->sme_vq
.map
);
6733 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6735 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6738 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6741 int cur_el
= arm_current_el(env
);
6742 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6745 /* Bits other than [3:0] are RAZ/WI. */
6746 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6747 raw_write(env
, ri
, value
& 0xf);
6750 * Because we arrived here, we know both FP and SVE are enabled;
6751 * otherwise we would have trapped access to the ZCR_ELn register.
6753 new_len
= sve_vqm1_for_el(env
, cur_el
);
6754 if (new_len
< old_len
) {
6755 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6759 static const ARMCPRegInfo zcr_reginfo
[] = {
6760 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6761 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6762 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6763 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6764 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6765 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6766 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6767 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6768 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6769 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6770 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6771 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6772 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6773 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6774 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6777 #ifdef TARGET_AARCH64
6778 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6781 int el
= arm_current_el(env
);
6784 uint64_t sctlr
= arm_sctlr(env
, el
);
6785 if (!(sctlr
& SCTLR_EnTP2
)) {
6786 return CP_ACCESS_TRAP
;
6789 /* TODO: FEAT_FGT */
6791 && arm_feature(env
, ARM_FEATURE_EL3
)
6792 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6793 return CP_ACCESS_TRAP_EL3
;
6795 return CP_ACCESS_OK
;
6798 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6801 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6802 if (arm_current_el(env
) < 3
6803 && arm_feature(env
, ARM_FEATURE_EL3
)
6804 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6805 return CP_ACCESS_TRAP_EL3
;
6807 return CP_ACCESS_OK
;
6811 static void arm_reset_sve_state(CPUARMState
*env
)
6813 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
6814 /* Recall that FFR is stored as pregs[16]. */
6815 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
6816 vfp_set_fpcr(env
, 0x0800009f);
6819 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
6821 uint64_t change
= (env
->svcr
^ new) & mask
;
6826 env
->svcr
^= change
;
6828 if (change
& R_SVCR_SM_MASK
) {
6829 arm_reset_sve_state(env
);
6835 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
6836 * on enable: while disabled, the storage is inaccessible and the
6837 * value does not matter. We're not saving the storage in vmstate
6838 * when disabled either.
6840 if (change
& new & R_SVCR_ZA_MASK
) {
6841 memset(env
->zarray
, 0, sizeof(env
->zarray
));
6844 if (tcg_enabled()) {
6845 arm_rebuild_hflags(env
);
6849 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6852 aarch64_set_svcr(env
, value
, -1);
6855 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6858 int cur_el
= arm_current_el(env
);
6859 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6862 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6863 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6864 raw_write(env
, ri
, value
);
6867 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
6868 * when SVL is widened (old values kept, or zeros). Choose to keep the
6869 * current values for simplicity. But for QEMU internals, we must still
6870 * apply the narrower SVL to the Zregs and Pregs -- see the comment
6871 * above aarch64_sve_narrow_vq.
6873 new_len
= sve_vqm1_for_el(env
, cur_el
);
6874 if (new_len
< old_len
) {
6875 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6879 static const ARMCPRegInfo sme_reginfo
[] = {
6880 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
6881 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
6882 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
6883 .fgt
= FGT_NTPIDR2_EL0
,
6884 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
6885 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
6886 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
6887 .access
= PL0_RW
, .type
= ARM_CP_SME
,
6888 .fieldoffset
= offsetof(CPUARMState
, svcr
),
6889 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
6890 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
6891 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
6892 .access
= PL1_RW
, .type
= ARM_CP_SME
,
6893 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
6894 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6895 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
6896 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
6897 .access
= PL2_RW
, .type
= ARM_CP_SME
,
6898 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
6899 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6900 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
6901 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
6902 .access
= PL3_RW
, .type
= ARM_CP_SME
,
6903 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
6904 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6905 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
6906 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
6907 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
6909 * IMPLEMENTOR = 0 (software)
6910 * REVISION = 0 (implementation defined)
6911 * SMPS = 0 (no streaming execution priority in QEMU)
6912 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
6914 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
6916 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
6918 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
6919 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
6920 .access
= PL1_RW
, .accessfn
= access_esm
,
6921 .fgt
= FGT_NSMPRI_EL1
,
6922 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6923 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
6924 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
6925 .access
= PL2_RW
, .accessfn
= access_esm
,
6926 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6928 #endif /* TARGET_AARCH64 */
6930 static void define_pmu_regs(ARMCPU
*cpu
)
6933 * v7 performance monitor control register: same implementor
6934 * field as main ID register, and we implement four counters in
6935 * addition to the cycle count register.
6937 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6938 ARMCPRegInfo pmcr
= {
6939 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6941 .fgt
= FGT_PMCR_EL0
,
6942 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6943 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6944 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6945 .raw_writefn
= raw_write
,
6947 ARMCPRegInfo pmcr64
= {
6948 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6949 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6950 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6951 .fgt
= FGT_PMCR_EL0
,
6953 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6954 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6955 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6958 define_one_arm_cp_reg(cpu
, &pmcr
);
6959 define_one_arm_cp_reg(cpu
, &pmcr64
);
6960 for (i
= 0; i
< pmcrn
; i
++) {
6961 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6962 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6963 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6964 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6965 ARMCPRegInfo pmev_regs
[] = {
6966 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6967 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6968 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6969 .fgt
= FGT_PMEVCNTRN_EL0
,
6970 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6971 .accessfn
= pmreg_access_xevcntr
},
6972 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6973 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6974 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6976 .fgt
= FGT_PMEVCNTRN_EL0
,
6977 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6978 .raw_readfn
= pmevcntr_rawread
,
6979 .raw_writefn
= pmevcntr_rawwrite
},
6980 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6981 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6982 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6983 .fgt
= FGT_PMEVTYPERN_EL0
,
6984 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6985 .accessfn
= pmreg_access
},
6986 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6987 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6988 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6989 .fgt
= FGT_PMEVTYPERN_EL0
,
6991 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6992 .raw_writefn
= pmevtyper_rawwrite
},
6994 define_arm_cp_regs(cpu
, pmev_regs
);
6995 g_free(pmevcntr_name
);
6996 g_free(pmevcntr_el0_name
);
6997 g_free(pmevtyper_name
);
6998 g_free(pmevtyper_el0_name
);
7000 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7001 ARMCPRegInfo v81_pmu_regs
[] = {
7002 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7003 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7004 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7005 .fgt
= FGT_PMCEIDN_EL0
,
7006 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7007 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7008 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7009 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7010 .fgt
= FGT_PMCEIDN_EL0
,
7011 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7013 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7015 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7016 static const ARMCPRegInfo v84_pmmir
= {
7017 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7018 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7019 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7020 .fgt
= FGT_PMMIR_EL1
,
7023 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7027 #ifndef CONFIG_USER_ONLY
7029 * We don't know until after realize whether there's a GICv3
7030 * attached, and that is what registers the gicv3 sysregs.
7031 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7034 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7036 ARMCPU
*cpu
= env_archcpu(env
);
7037 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7039 if (env
->gicv3state
) {
7045 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7047 ARMCPU
*cpu
= env_archcpu(env
);
7048 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7050 if (env
->gicv3state
) {
7058 * Shared logic between LORID and the rest of the LOR* registers.
7059 * Secure state exclusion has already been dealt with.
7061 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7062 const ARMCPRegInfo
*ri
, bool isread
)
7064 int el
= arm_current_el(env
);
7066 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7067 return CP_ACCESS_TRAP_EL2
;
7069 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7070 return CP_ACCESS_TRAP_EL3
;
7072 return CP_ACCESS_OK
;
7075 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7076 const ARMCPRegInfo
*ri
, bool isread
)
7078 if (arm_is_secure_below_el3(env
)) {
7079 /* Access denied in secure mode. */
7080 return CP_ACCESS_TRAP
;
7082 return access_lor_ns(env
, ri
, isread
);
7086 * A trivial implementation of ARMv8.1-LOR leaves all of these
7087 * registers fixed at 0, which indicates that there are zero
7088 * supported Limited Ordering regions.
7090 static const ARMCPRegInfo lor_reginfo
[] = {
7091 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7092 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7093 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7094 .fgt
= FGT_LORSA_EL1
,
7095 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7096 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7097 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7098 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7099 .fgt
= FGT_LOREA_EL1
,
7100 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7101 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7102 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7103 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7104 .fgt
= FGT_LORN_EL1
,
7105 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7106 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7107 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7108 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7109 .fgt
= FGT_LORC_EL1
,
7110 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7111 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7112 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7113 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7114 .fgt
= FGT_LORID_EL1
,
7115 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7118 #ifdef TARGET_AARCH64
7119 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7122 int el
= arm_current_el(env
);
7125 arm_is_el2_enabled(env
) &&
7126 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7127 return CP_ACCESS_TRAP_EL2
;
7130 arm_feature(env
, ARM_FEATURE_EL3
) &&
7131 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7132 return CP_ACCESS_TRAP_EL3
;
7134 return CP_ACCESS_OK
;
7137 static const ARMCPRegInfo pauth_reginfo
[] = {
7138 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7139 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7140 .access
= PL1_RW
, .accessfn
= access_pauth
,
7142 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7143 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7144 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7145 .access
= PL1_RW
, .accessfn
= access_pauth
,
7147 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7148 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7149 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7150 .access
= PL1_RW
, .accessfn
= access_pauth
,
7152 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7153 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7154 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7155 .access
= PL1_RW
, .accessfn
= access_pauth
,
7157 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7158 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7159 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7160 .access
= PL1_RW
, .accessfn
= access_pauth
,
7162 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7163 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7164 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7165 .access
= PL1_RW
, .accessfn
= access_pauth
,
7167 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7168 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7169 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7170 .access
= PL1_RW
, .accessfn
= access_pauth
,
7172 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7173 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7174 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7175 .access
= PL1_RW
, .accessfn
= access_pauth
,
7177 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7178 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7179 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7180 .access
= PL1_RW
, .accessfn
= access_pauth
,
7182 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7183 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7184 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7185 .access
= PL1_RW
, .accessfn
= access_pauth
,
7187 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7190 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7191 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7192 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7193 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7194 .fgt
= FGT_TLBIRVAE1IS
,
7195 .writefn
= tlbi_aa64_rvae1is_write
},
7196 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7197 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7198 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7199 .fgt
= FGT_TLBIRVAAE1IS
,
7200 .writefn
= tlbi_aa64_rvae1is_write
},
7201 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7202 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7203 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7204 .fgt
= FGT_TLBIRVALE1IS
,
7205 .writefn
= tlbi_aa64_rvae1is_write
},
7206 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7207 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7208 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7209 .fgt
= FGT_TLBIRVAALE1IS
,
7210 .writefn
= tlbi_aa64_rvae1is_write
},
7211 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7212 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7213 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7214 .fgt
= FGT_TLBIRVAE1OS
,
7215 .writefn
= tlbi_aa64_rvae1is_write
},
7216 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7217 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7218 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7219 .fgt
= FGT_TLBIRVAAE1OS
,
7220 .writefn
= tlbi_aa64_rvae1is_write
},
7221 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7222 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7223 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7224 .fgt
= FGT_TLBIRVALE1OS
,
7225 .writefn
= tlbi_aa64_rvae1is_write
},
7226 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7227 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7228 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7229 .fgt
= FGT_TLBIRVAALE1OS
,
7230 .writefn
= tlbi_aa64_rvae1is_write
},
7231 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7232 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7233 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7234 .fgt
= FGT_TLBIRVAE1
,
7235 .writefn
= tlbi_aa64_rvae1_write
},
7236 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7237 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7238 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7239 .fgt
= FGT_TLBIRVAAE1
,
7240 .writefn
= tlbi_aa64_rvae1_write
},
7241 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7242 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7243 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7244 .fgt
= FGT_TLBIRVALE1
,
7245 .writefn
= tlbi_aa64_rvae1_write
},
7246 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7247 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7248 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7249 .fgt
= FGT_TLBIRVAALE1
,
7250 .writefn
= tlbi_aa64_rvae1_write
},
7251 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7252 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7253 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7254 .writefn
= tlbi_aa64_ripas2e1is_write
},
7255 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7256 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7257 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7258 .writefn
= tlbi_aa64_ripas2e1is_write
},
7259 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7260 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7261 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7262 .writefn
= tlbi_aa64_rvae2is_write
},
7263 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7264 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7265 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7266 .writefn
= tlbi_aa64_rvae2is_write
},
7267 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7268 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7269 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7270 .writefn
= tlbi_aa64_ripas2e1_write
},
7271 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7272 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7273 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7274 .writefn
= tlbi_aa64_ripas2e1_write
},
7275 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7276 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7277 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7278 .writefn
= tlbi_aa64_rvae2is_write
},
7279 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7280 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7281 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7282 .writefn
= tlbi_aa64_rvae2is_write
},
7283 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7284 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7285 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7286 .writefn
= tlbi_aa64_rvae2_write
},
7287 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7288 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7289 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7290 .writefn
= tlbi_aa64_rvae2_write
},
7291 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7292 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7293 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7294 .writefn
= tlbi_aa64_rvae3is_write
},
7295 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7296 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7297 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7298 .writefn
= tlbi_aa64_rvae3is_write
},
7299 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7300 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7301 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7302 .writefn
= tlbi_aa64_rvae3is_write
},
7303 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7304 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7305 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7306 .writefn
= tlbi_aa64_rvae3is_write
},
7307 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7308 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7309 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7310 .writefn
= tlbi_aa64_rvae3_write
},
7311 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7312 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7313 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7314 .writefn
= tlbi_aa64_rvae3_write
},
7317 static const ARMCPRegInfo tlbios_reginfo
[] = {
7318 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7319 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7320 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7321 .fgt
= FGT_TLBIVMALLE1OS
,
7322 .writefn
= tlbi_aa64_vmalle1is_write
},
7323 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7324 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7325 .fgt
= FGT_TLBIVAE1OS
,
7326 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7327 .writefn
= tlbi_aa64_vae1is_write
},
7328 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7329 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7330 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7331 .fgt
= FGT_TLBIASIDE1OS
,
7332 .writefn
= tlbi_aa64_vmalle1is_write
},
7333 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7334 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7335 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7336 .fgt
= FGT_TLBIVAAE1OS
,
7337 .writefn
= tlbi_aa64_vae1is_write
},
7338 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7339 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7340 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7341 .fgt
= FGT_TLBIVALE1OS
,
7342 .writefn
= tlbi_aa64_vae1is_write
},
7343 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7344 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7345 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7346 .fgt
= FGT_TLBIVAALE1OS
,
7347 .writefn
= tlbi_aa64_vae1is_write
},
7348 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7349 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7350 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7351 .writefn
= tlbi_aa64_alle2is_write
},
7352 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7353 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7354 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7355 .writefn
= tlbi_aa64_vae2is_write
},
7356 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7357 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7358 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7359 .writefn
= tlbi_aa64_alle1is_write
},
7360 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7361 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7362 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7363 .writefn
= tlbi_aa64_vae2is_write
},
7364 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7365 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7366 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7367 .writefn
= tlbi_aa64_alle1is_write
},
7368 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7369 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7370 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7371 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7372 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7373 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7374 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7375 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7376 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7377 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7378 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7379 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7380 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7381 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7382 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7383 .writefn
= tlbi_aa64_alle3is_write
},
7384 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7385 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7386 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7387 .writefn
= tlbi_aa64_vae3is_write
},
7388 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7389 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7390 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7391 .writefn
= tlbi_aa64_vae3is_write
},
7394 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7399 /* Success sets NZCV = 0000. */
7400 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7402 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7404 * ??? Failed, for unknown reasons in the crypto subsystem.
7405 * The best we can do is log the reason and return the
7406 * timed-out indication to the guest. There is no reason
7407 * we know to expect this failure to be transitory, so the
7408 * guest may well hang retrying the operation.
7410 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7411 ri
->name
, error_get_pretty(err
));
7414 env
->ZF
= 0; /* NZCF = 0100 */
7420 /* We do not support re-seeding, so the two registers operate the same. */
7421 static const ARMCPRegInfo rndr_reginfo
[] = {
7422 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7423 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7424 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7425 .access
= PL0_R
, .readfn
= rndr_readfn
},
7426 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7427 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7428 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7429 .access
= PL0_R
, .readfn
= rndr_readfn
},
7432 #ifndef CONFIG_USER_ONLY
7433 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7436 ARMCPU
*cpu
= env_archcpu(env
);
7437 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7438 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7439 uint64_t vaddr_in
= (uint64_t) value
;
7440 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7442 int mem_idx
= cpu_mmu_index(env
, false);
7444 /* This won't be crossing page boundaries */
7445 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7451 /* RCU lock is already being held */
7452 mr
= memory_region_from_host(haddr
, &offset
);
7455 memory_region_writeback(mr
, offset
, dline_size
);
7460 static const ARMCPRegInfo dcpop_reg
[] = {
7461 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7462 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7463 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7465 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7468 static const ARMCPRegInfo dcpodp_reg
[] = {
7469 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7470 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7471 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7473 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7475 #endif /*CONFIG_USER_ONLY*/
7477 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7480 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7481 return CP_ACCESS_TRAP_EL2
;
7484 return CP_ACCESS_OK
;
7487 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7490 int el
= arm_current_el(env
);
7492 if (el
< 2 && arm_is_el2_enabled(env
)) {
7493 uint64_t hcr
= arm_hcr_el2_eff(env
);
7494 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7495 return CP_ACCESS_TRAP_EL2
;
7499 arm_feature(env
, ARM_FEATURE_EL3
) &&
7500 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7501 return CP_ACCESS_TRAP_EL3
;
7503 return CP_ACCESS_OK
;
7506 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7508 return env
->pstate
& PSTATE_TCO
;
7511 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7513 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7516 static const ARMCPRegInfo mte_reginfo
[] = {
7517 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7518 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7519 .access
= PL1_RW
, .accessfn
= access_mte
,
7520 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7521 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7522 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7523 .access
= PL1_RW
, .accessfn
= access_mte
,
7524 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7525 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7526 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7527 .access
= PL2_RW
, .accessfn
= access_mte
,
7528 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7529 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7530 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7532 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7533 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7534 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7535 .access
= PL1_RW
, .accessfn
= access_mte
,
7536 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7537 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7538 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7539 .access
= PL1_RW
, .accessfn
= access_mte
,
7540 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7541 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7542 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7543 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7544 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7545 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7546 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7547 .type
= ARM_CP_NO_RAW
,
7548 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7549 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7550 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7551 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7553 .accessfn
= aa64_cacheop_poc_access
},
7554 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7555 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7557 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7558 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7559 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7560 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7562 .accessfn
= aa64_cacheop_poc_access
},
7563 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7564 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7566 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7567 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7568 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7570 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7571 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7572 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7574 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7575 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7576 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7578 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7579 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7580 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7582 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7585 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7586 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7587 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7588 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7591 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7592 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7593 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7594 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7596 .accessfn
= aa64_cacheop_poc_access
},
7597 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7598 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7599 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7601 .accessfn
= aa64_cacheop_poc_access
},
7602 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7603 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7604 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7606 .accessfn
= aa64_cacheop_poc_access
},
7607 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7608 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7609 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7611 .accessfn
= aa64_cacheop_poc_access
},
7612 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7613 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7614 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7616 .accessfn
= aa64_cacheop_poc_access
},
7617 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7618 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7619 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7621 .accessfn
= aa64_cacheop_poc_access
},
7622 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7623 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7624 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7626 .accessfn
= aa64_cacheop_poc_access
},
7627 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7628 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7629 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7631 .accessfn
= aa64_cacheop_poc_access
},
7632 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7633 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7634 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7635 #ifndef CONFIG_USER_ONLY
7636 /* Avoid overhead of an access check that always passes in user-mode */
7637 .accessfn
= aa64_zva_access
,
7641 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7642 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7643 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7644 #ifndef CONFIG_USER_ONLY
7645 /* Avoid overhead of an access check that always passes in user-mode */
7646 .accessfn
= aa64_zva_access
,
7652 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7655 uint64_t hcr
= arm_hcr_el2_eff(env
);
7656 int el
= arm_current_el(env
);
7658 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7659 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7660 if (hcr
& HCR_TGE
) {
7661 return CP_ACCESS_TRAP_EL2
;
7663 return CP_ACCESS_TRAP
;
7665 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7666 return CP_ACCESS_TRAP_EL2
;
7668 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7669 return CP_ACCESS_TRAP_EL2
;
7672 && arm_feature(env
, ARM_FEATURE_EL3
)
7673 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7674 return CP_ACCESS_TRAP_EL3
;
7676 return CP_ACCESS_OK
;
7679 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7680 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7681 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7682 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7683 .fgt
= FGT_SCXTNUM_EL0
,
7684 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7685 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7686 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7687 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7688 .fgt
= FGT_SCXTNUM_EL1
,
7689 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7690 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7691 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7692 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7693 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7694 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7695 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7697 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7700 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7703 if (arm_current_el(env
) == 2 &&
7704 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
7705 return CP_ACCESS_TRAP_EL3
;
7707 return CP_ACCESS_OK
;
7710 static const ARMCPRegInfo fgt_reginfo
[] = {
7711 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7712 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
7713 .access
= PL2_RW
, .accessfn
= access_fgt
,
7714 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
7715 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7716 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
7717 .access
= PL2_RW
, .accessfn
= access_fgt
,
7718 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
7719 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7720 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
7721 .access
= PL2_RW
, .accessfn
= access_fgt
,
7722 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
7723 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7724 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
7725 .access
= PL2_RW
, .accessfn
= access_fgt
,
7726 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
7727 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
7728 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
7729 .access
= PL2_RW
, .accessfn
= access_fgt
,
7730 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
7732 #endif /* TARGET_AARCH64 */
7734 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7737 int el
= arm_current_el(env
);
7740 uint64_t sctlr
= arm_sctlr(env
, el
);
7741 if (!(sctlr
& SCTLR_EnRCTX
)) {
7742 return CP_ACCESS_TRAP
;
7744 } else if (el
== 1) {
7745 uint64_t hcr
= arm_hcr_el2_eff(env
);
7747 return CP_ACCESS_TRAP_EL2
;
7750 return CP_ACCESS_OK
;
7753 static const ARMCPRegInfo predinv_reginfo
[] = {
7754 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7755 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7757 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7758 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7759 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7761 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7762 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7763 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7765 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7767 * Note the AArch32 opcodes have a different OPC1.
7769 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7770 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7772 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7773 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7774 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7776 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7777 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7778 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7780 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7783 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7785 /* Read the high 32 bits of the current CCSIDR */
7786 return extract64(ccsidr_read(env
, ri
), 32, 32);
7789 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7790 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7791 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7793 .accessfn
= access_tid4
,
7794 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7797 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7800 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7801 return CP_ACCESS_TRAP_EL2
;
7804 return CP_ACCESS_OK
;
7807 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7810 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7811 return access_aa64_tid3(env
, ri
, isread
);
7814 return CP_ACCESS_OK
;
7817 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7820 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7821 return CP_ACCESS_TRAP_EL2
;
7824 return CP_ACCESS_OK
;
7827 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7828 const ARMCPRegInfo
*ri
, bool isread
)
7831 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7832 * in v7A, not in v8A.
7834 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7835 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7836 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7837 return CP_ACCESS_TRAP_EL2
;
7839 return CP_ACCESS_OK
;
7842 static const ARMCPRegInfo jazelle_regs
[] = {
7844 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7845 .access
= PL1_R
, .accessfn
= access_jazelle
,
7846 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7848 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7849 .accessfn
= access_joscr_jmcr
,
7850 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7852 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7853 .accessfn
= access_joscr_jmcr
,
7854 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7857 static const ARMCPRegInfo contextidr_el2
= {
7858 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7859 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7861 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7864 static const ARMCPRegInfo vhe_reginfo
[] = {
7865 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7866 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7867 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7868 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7869 #ifndef CONFIG_USER_ONLY
7870 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7871 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7873 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7874 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7875 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7876 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7877 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7878 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7879 .resetfn
= gt_hv_timer_reset
,
7880 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7881 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7883 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7885 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7886 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7887 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7888 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7889 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7890 .access
= PL2_RW
, .accessfn
= e2h_access
,
7891 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7892 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7893 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7894 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7895 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7896 .access
= PL2_RW
, .accessfn
= e2h_access
,
7897 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7898 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7899 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7900 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7901 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7902 .access
= PL2_RW
, .accessfn
= e2h_access
,
7903 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7904 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7905 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7906 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7907 .access
= PL2_RW
, .accessfn
= e2h_access
,
7908 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7909 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7910 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7911 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7912 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7913 .access
= PL2_RW
, .accessfn
= e2h_access
,
7914 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7915 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7916 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7917 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7918 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7919 .access
= PL2_RW
, .accessfn
= e2h_access
,
7920 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7924 #ifndef CONFIG_USER_ONLY
7925 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7926 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
7927 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7928 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7929 .fgt
= FGT_ATS1E1RP
,
7930 .writefn
= ats_write64
},
7931 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
7932 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7933 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7934 .fgt
= FGT_ATS1E1WP
,
7935 .writefn
= ats_write64
},
7938 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7939 { .name
= "ATS1CPRP",
7940 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7941 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7942 .writefn
= ats_write
},
7943 { .name
= "ATS1CPWP",
7944 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7945 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7946 .writefn
= ats_write
},
7951 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7952 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7953 * is non-zero, which is never for ARMv7, optionally in ARMv8
7954 * and mandatorily for ARMv8.2 and up.
7955 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7956 * implementation is RAZ/WI we can ignore this detail, as we
7959 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7960 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7961 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7962 .access
= PL1_RW
, .accessfn
= access_tacr
,
7963 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7964 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7965 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7966 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7970 void register_cp_regs_for_features(ARMCPU
*cpu
)
7972 /* Register all the coprocessor registers based on feature bits */
7973 CPUARMState
*env
= &cpu
->env
;
7974 if (arm_feature(env
, ARM_FEATURE_M
)) {
7975 /* M profile has no coprocessor registers */
7979 define_arm_cp_regs(cpu
, cp_reginfo
);
7980 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7982 * Must go early as it is full of wildcards that may be
7983 * overridden by later definitions.
7985 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7988 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7989 /* The ID registers all have impdef reset values */
7990 ARMCPRegInfo v6_idregs
[] = {
7991 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7992 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7993 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7994 .accessfn
= access_aa32_tid3
,
7995 .resetvalue
= cpu
->isar
.id_pfr0
},
7997 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7998 * the value of the GIC field until after we define these regs.
8000 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8001 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8002 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8003 .accessfn
= access_aa32_tid3
,
8004 #ifdef CONFIG_USER_ONLY
8005 .type
= ARM_CP_CONST
,
8006 .resetvalue
= cpu
->isar
.id_pfr1
,
8008 .type
= ARM_CP_NO_RAW
,
8009 .accessfn
= access_aa32_tid3
,
8010 .readfn
= id_pfr1_read
,
8011 .writefn
= arm_cp_write_ignore
8014 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8015 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8016 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8017 .accessfn
= access_aa32_tid3
,
8018 .resetvalue
= cpu
->isar
.id_dfr0
},
8019 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8020 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8021 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8022 .accessfn
= access_aa32_tid3
,
8023 .resetvalue
= cpu
->id_afr0
},
8024 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8025 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8026 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8027 .accessfn
= access_aa32_tid3
,
8028 .resetvalue
= cpu
->isar
.id_mmfr0
},
8029 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8030 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8031 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8032 .accessfn
= access_aa32_tid3
,
8033 .resetvalue
= cpu
->isar
.id_mmfr1
},
8034 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8035 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8036 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8037 .accessfn
= access_aa32_tid3
,
8038 .resetvalue
= cpu
->isar
.id_mmfr2
},
8039 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8040 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8041 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8042 .accessfn
= access_aa32_tid3
,
8043 .resetvalue
= cpu
->isar
.id_mmfr3
},
8044 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8045 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8046 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8047 .accessfn
= access_aa32_tid3
,
8048 .resetvalue
= cpu
->isar
.id_isar0
},
8049 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8050 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8051 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8052 .accessfn
= access_aa32_tid3
,
8053 .resetvalue
= cpu
->isar
.id_isar1
},
8054 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8055 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8056 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8057 .accessfn
= access_aa32_tid3
,
8058 .resetvalue
= cpu
->isar
.id_isar2
},
8059 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8060 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8061 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8062 .accessfn
= access_aa32_tid3
,
8063 .resetvalue
= cpu
->isar
.id_isar3
},
8064 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8065 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8066 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8067 .accessfn
= access_aa32_tid3
,
8068 .resetvalue
= cpu
->isar
.id_isar4
},
8069 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8070 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8071 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8072 .accessfn
= access_aa32_tid3
,
8073 .resetvalue
= cpu
->isar
.id_isar5
},
8074 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8075 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8076 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8077 .accessfn
= access_aa32_tid3
,
8078 .resetvalue
= cpu
->isar
.id_mmfr4
},
8079 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8080 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8081 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8082 .accessfn
= access_aa32_tid3
,
8083 .resetvalue
= cpu
->isar
.id_isar6
},
8085 define_arm_cp_regs(cpu
, v6_idregs
);
8086 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8088 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8090 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8091 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8093 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8094 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8095 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8097 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8098 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8100 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8101 ARMCPRegInfo clidr
= {
8102 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8103 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8104 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8105 .accessfn
= access_tid4
,
8106 .fgt
= FGT_CLIDR_EL1
,
8107 .resetvalue
= cpu
->clidr
8109 define_one_arm_cp_reg(cpu
, &clidr
);
8110 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8111 define_debug_regs(cpu
);
8112 define_pmu_regs(cpu
);
8114 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8116 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8118 * v8 ID registers, which all have impdef reset values.
8119 * Note that within the ID register ranges the unused slots
8120 * must all RAZ, not UNDEF; future architecture versions may
8121 * define new registers here.
8122 * ID registers which are AArch64 views of the AArch32 ID registers
8123 * which already existed in v6 and v7 are handled elsewhere,
8127 ARMCPRegInfo v8_idregs
[] = {
8129 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8130 * emulation because we don't know the right value for the
8131 * GIC field until after we define these regs.
8133 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8134 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8136 #ifdef CONFIG_USER_ONLY
8137 .type
= ARM_CP_CONST
,
8138 .resetvalue
= cpu
->isar
.id_aa64pfr0
8140 .type
= ARM_CP_NO_RAW
,
8141 .accessfn
= access_aa64_tid3
,
8142 .readfn
= id_aa64pfr0_read
,
8143 .writefn
= arm_cp_write_ignore
8146 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8147 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8148 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8149 .accessfn
= access_aa64_tid3
,
8150 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8151 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8152 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8153 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8154 .accessfn
= access_aa64_tid3
,
8156 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8157 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8158 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8159 .accessfn
= access_aa64_tid3
,
8161 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8162 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8163 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8164 .accessfn
= access_aa64_tid3
,
8165 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8166 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8167 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8168 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8169 .accessfn
= access_aa64_tid3
,
8170 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8171 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8172 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8173 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8174 .accessfn
= access_aa64_tid3
,
8176 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8177 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8178 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8179 .accessfn
= access_aa64_tid3
,
8181 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8182 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8183 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8184 .accessfn
= access_aa64_tid3
,
8185 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8186 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8187 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8188 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8189 .accessfn
= access_aa64_tid3
,
8190 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8191 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8192 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8193 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8194 .accessfn
= access_aa64_tid3
,
8196 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8197 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8198 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8199 .accessfn
= access_aa64_tid3
,
8201 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8202 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8203 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8204 .accessfn
= access_aa64_tid3
,
8205 .resetvalue
= cpu
->id_aa64afr0
},
8206 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8207 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8208 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8209 .accessfn
= access_aa64_tid3
,
8210 .resetvalue
= cpu
->id_aa64afr1
},
8211 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8212 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8213 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8214 .accessfn
= access_aa64_tid3
,
8216 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8217 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8218 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8219 .accessfn
= access_aa64_tid3
,
8221 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8222 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8223 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8224 .accessfn
= access_aa64_tid3
,
8225 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8226 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8227 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8228 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8229 .accessfn
= access_aa64_tid3
,
8230 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8231 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8232 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8233 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8234 .accessfn
= access_aa64_tid3
,
8236 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8237 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8238 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8239 .accessfn
= access_aa64_tid3
,
8241 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8242 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8243 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8244 .accessfn
= access_aa64_tid3
,
8246 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8247 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8248 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8249 .accessfn
= access_aa64_tid3
,
8251 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8252 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8253 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8254 .accessfn
= access_aa64_tid3
,
8256 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8257 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8258 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8259 .accessfn
= access_aa64_tid3
,
8261 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8262 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8263 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8264 .accessfn
= access_aa64_tid3
,
8265 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8266 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8267 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8268 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8269 .accessfn
= access_aa64_tid3
,
8270 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8271 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8272 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8273 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8274 .accessfn
= access_aa64_tid3
,
8275 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8276 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8277 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8278 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8279 .accessfn
= access_aa64_tid3
,
8281 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8282 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8283 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8284 .accessfn
= access_aa64_tid3
,
8286 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8287 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8288 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8289 .accessfn
= access_aa64_tid3
,
8291 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8292 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8293 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8294 .accessfn
= access_aa64_tid3
,
8296 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8297 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8298 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8299 .accessfn
= access_aa64_tid3
,
8301 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8302 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8303 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8304 .accessfn
= access_aa64_tid3
,
8305 .resetvalue
= cpu
->isar
.mvfr0
},
8306 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8307 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8308 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8309 .accessfn
= access_aa64_tid3
,
8310 .resetvalue
= cpu
->isar
.mvfr1
},
8311 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8312 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8313 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8314 .accessfn
= access_aa64_tid3
,
8315 .resetvalue
= cpu
->isar
.mvfr2
},
8317 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8318 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8319 * as RAZ, since it is in the "reserved for future ID
8320 * registers, RAZ" part of the AArch32 encoding space.
8322 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8323 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8324 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8325 .accessfn
= access_aa64_tid3
,
8327 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8328 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8329 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8330 .accessfn
= access_aa64_tid3
,
8332 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8333 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8334 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8335 .accessfn
= access_aa64_tid3
,
8338 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8339 * they're also RAZ for AArch64, and in v8 are gradually
8340 * being filled with AArch64-view-of-AArch32-ID-register
8341 * for new ID registers.
8343 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8344 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8345 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8346 .accessfn
= access_aa64_tid3
,
8348 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8349 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8350 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8351 .accessfn
= access_aa64_tid3
,
8352 .resetvalue
= cpu
->isar
.id_pfr2
},
8353 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8354 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8355 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8356 .accessfn
= access_aa64_tid3
,
8357 .resetvalue
= cpu
->isar
.id_dfr1
},
8358 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8359 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8360 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8361 .accessfn
= access_aa64_tid3
,
8362 .resetvalue
= cpu
->isar
.id_mmfr5
},
8363 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8364 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8365 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8366 .accessfn
= access_aa64_tid3
,
8368 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8369 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8370 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8371 .fgt
= FGT_PMCEIDN_EL0
,
8372 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8373 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8374 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8375 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8376 .fgt
= FGT_PMCEIDN_EL0
,
8377 .resetvalue
= cpu
->pmceid0
},
8378 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8379 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8380 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8381 .fgt
= FGT_PMCEIDN_EL0
,
8382 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8383 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8384 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8385 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8386 .fgt
= FGT_PMCEIDN_EL0
,
8387 .resetvalue
= cpu
->pmceid1
},
8389 #ifdef CONFIG_USER_ONLY
8390 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8391 { .name
= "ID_AA64PFR0_EL1",
8392 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8393 R_ID_AA64PFR0_ADVSIMD_MASK
|
8394 R_ID_AA64PFR0_SVE_MASK
|
8395 R_ID_AA64PFR0_DIT_MASK
,
8396 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8397 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8398 { .name
= "ID_AA64PFR1_EL1",
8399 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8400 R_ID_AA64PFR1_SSBS_MASK
|
8401 R_ID_AA64PFR1_MTE_MASK
|
8402 R_ID_AA64PFR1_SME_MASK
},
8403 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8405 { .name
= "ID_AA64ZFR0_EL1",
8406 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8407 R_ID_AA64ZFR0_AES_MASK
|
8408 R_ID_AA64ZFR0_BITPERM_MASK
|
8409 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8410 R_ID_AA64ZFR0_SHA3_MASK
|
8411 R_ID_AA64ZFR0_SM4_MASK
|
8412 R_ID_AA64ZFR0_I8MM_MASK
|
8413 R_ID_AA64ZFR0_F32MM_MASK
|
8414 R_ID_AA64ZFR0_F64MM_MASK
},
8415 { .name
= "ID_AA64SMFR0_EL1",
8416 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8417 R_ID_AA64SMFR0_B16F32_MASK
|
8418 R_ID_AA64SMFR0_F16F32_MASK
|
8419 R_ID_AA64SMFR0_I8I32_MASK
|
8420 R_ID_AA64SMFR0_F64F64_MASK
|
8421 R_ID_AA64SMFR0_I16I64_MASK
|
8422 R_ID_AA64SMFR0_FA64_MASK
},
8423 { .name
= "ID_AA64MMFR0_EL1",
8424 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8425 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8426 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8427 { .name
= "ID_AA64MMFR1_EL1",
8428 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8429 { .name
= "ID_AA64MMFR2_EL1",
8430 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8431 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8433 { .name
= "ID_AA64DFR0_EL1",
8434 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8435 { .name
= "ID_AA64DFR1_EL1" },
8436 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8438 { .name
= "ID_AA64AFR*",
8440 { .name
= "ID_AA64ISAR0_EL1",
8441 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8442 R_ID_AA64ISAR0_SHA1_MASK
|
8443 R_ID_AA64ISAR0_SHA2_MASK
|
8444 R_ID_AA64ISAR0_CRC32_MASK
|
8445 R_ID_AA64ISAR0_ATOMIC_MASK
|
8446 R_ID_AA64ISAR0_RDM_MASK
|
8447 R_ID_AA64ISAR0_SHA3_MASK
|
8448 R_ID_AA64ISAR0_SM3_MASK
|
8449 R_ID_AA64ISAR0_SM4_MASK
|
8450 R_ID_AA64ISAR0_DP_MASK
|
8451 R_ID_AA64ISAR0_FHM_MASK
|
8452 R_ID_AA64ISAR0_TS_MASK
|
8453 R_ID_AA64ISAR0_RNDR_MASK
},
8454 { .name
= "ID_AA64ISAR1_EL1",
8455 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8456 R_ID_AA64ISAR1_APA_MASK
|
8457 R_ID_AA64ISAR1_API_MASK
|
8458 R_ID_AA64ISAR1_JSCVT_MASK
|
8459 R_ID_AA64ISAR1_FCMA_MASK
|
8460 R_ID_AA64ISAR1_LRCPC_MASK
|
8461 R_ID_AA64ISAR1_GPA_MASK
|
8462 R_ID_AA64ISAR1_GPI_MASK
|
8463 R_ID_AA64ISAR1_FRINTTS_MASK
|
8464 R_ID_AA64ISAR1_SB_MASK
|
8465 R_ID_AA64ISAR1_BF16_MASK
|
8466 R_ID_AA64ISAR1_DGH_MASK
|
8467 R_ID_AA64ISAR1_I8MM_MASK
},
8468 { .name
= "ID_AA64ISAR2_EL1",
8469 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8470 R_ID_AA64ISAR2_RPRES_MASK
|
8471 R_ID_AA64ISAR2_GPA3_MASK
|
8472 R_ID_AA64ISAR2_APA3_MASK
},
8473 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8476 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8478 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
8479 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8480 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8481 ARMCPRegInfo rvbar
= {
8482 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8483 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8485 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8487 define_one_arm_cp_reg(cpu
, &rvbar
);
8489 define_arm_cp_regs(cpu
, v8_idregs
);
8490 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8492 for (i
= 4; i
< 16; i
++) {
8494 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8495 * For pre-v8 cores there are RAZ patterns for these in
8496 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8497 * v8 extends the "must RAZ" part of the ID register space
8498 * to also cover c0, 0, c{8-15}, {0-7}.
8499 * These are STATE_AA32 because in the AArch64 sysreg space
8500 * c4-c7 is where the AArch64 ID registers live (and we've
8501 * already defined those in v8_idregs[]), and c8-c15 are not
8502 * "must RAZ" for AArch64.
8504 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8505 ARMCPRegInfo v8_aa32_raz_idregs
= {
8507 .state
= ARM_CP_STATE_AA32
,
8508 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8509 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8510 .accessfn
= access_aa64_tid3
,
8512 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8517 * Register the base EL2 cpregs.
8518 * Pre v8, these registers are implemented only as part of the
8519 * Virtualization Extensions (EL2 present). Beginning with v8,
8520 * if EL2 is missing but EL3 is enabled, mostly these become
8521 * RES0 from EL3, with some specific exceptions.
8523 if (arm_feature(env
, ARM_FEATURE_EL2
)
8524 || (arm_feature(env
, ARM_FEATURE_EL3
)
8525 && arm_feature(env
, ARM_FEATURE_V8
))) {
8526 uint64_t vmpidr_def
= mpidr_read_val(env
);
8527 ARMCPRegInfo vpidr_regs
[] = {
8528 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8529 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8530 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8531 .resetvalue
= cpu
->midr
,
8532 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8533 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8534 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8535 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8536 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8537 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8538 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8539 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8540 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8541 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8542 .resetvalue
= vmpidr_def
,
8543 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8544 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8545 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8546 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8547 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8548 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8549 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8552 * The only field of MDCR_EL2 that has a defined architectural reset
8553 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8555 ARMCPRegInfo mdcr_el2
= {
8556 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8557 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8558 .writefn
= mdcr_el2_write
,
8559 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8560 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8562 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8563 define_arm_cp_regs(cpu
, vpidr_regs
);
8564 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8565 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8566 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8568 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8569 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8571 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
8572 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8573 ARMCPRegInfo rvbar
[] = {
8575 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8576 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8578 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8580 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8581 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8583 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8586 define_arm_cp_regs(cpu
, rvbar
);
8590 /* Register the base EL3 cpregs. */
8591 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8592 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8593 ARMCPRegInfo el3_regs
[] = {
8594 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8595 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8597 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8599 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8600 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8602 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8603 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8604 .resetvalue
= cpu
->reset_sctlr
},
8607 define_arm_cp_regs(cpu
, el3_regs
);
8610 * The behaviour of NSACR is sufficiently various that we don't
8611 * try to describe it in a single reginfo:
8612 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8613 * reads as constant 0xc00 from NS EL1 and NS EL2
8614 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8615 * if v7 without EL3, register doesn't exist
8616 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8618 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8619 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8620 static const ARMCPRegInfo nsacr
= {
8621 .name
= "NSACR", .type
= ARM_CP_CONST
,
8622 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8623 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8626 define_one_arm_cp_reg(cpu
, &nsacr
);
8628 static const ARMCPRegInfo nsacr
= {
8630 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8631 .access
= PL3_RW
| PL1_R
,
8633 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8635 define_one_arm_cp_reg(cpu
, &nsacr
);
8638 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8639 static const ARMCPRegInfo nsacr
= {
8640 .name
= "NSACR", .type
= ARM_CP_CONST
,
8641 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8645 define_one_arm_cp_reg(cpu
, &nsacr
);
8649 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8650 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8651 /* PMSAv6 not implemented */
8652 assert(arm_feature(env
, ARM_FEATURE_V7
));
8653 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8654 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8656 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8659 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8660 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8661 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8662 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8663 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8666 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8667 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8669 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8670 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8672 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8673 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8675 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8676 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8678 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8679 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8681 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8682 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8684 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8685 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8687 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8688 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8690 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8691 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8693 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8694 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8696 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8697 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8699 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8700 define_arm_cp_regs(cpu
, jazelle_regs
);
8703 * Slightly awkwardly, the OMAP and StrongARM cores need all of
8704 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8705 * be read-only (ie write causes UNDEF exception).
8708 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8710 * Pre-v8 MIDR space.
8711 * Note that the MIDR isn't a simple constant register because
8712 * of the TI925 behaviour where writes to another register can
8713 * cause the MIDR value to change.
8715 * Unimplemented registers in the c15 0 0 0 space default to
8716 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8717 * and friends override accordingly.
8720 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8721 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8722 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8723 .readfn
= midr_read
,
8724 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8725 .type
= ARM_CP_OVERRIDE
},
8726 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8728 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8729 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8731 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8732 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8734 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8735 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8737 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8738 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8740 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8741 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8743 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8744 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8745 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8746 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8747 .fgt
= FGT_MIDR_EL1
,
8748 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8749 .readfn
= midr_read
},
8750 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
8751 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8752 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8753 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8754 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8755 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8757 .accessfn
= access_aa64_tid1
,
8758 .fgt
= FGT_REVIDR_EL1
,
8759 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8761 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
8762 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8763 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8764 .access
= PL1_R
, .resetvalue
= cpu
->midr
8766 ARMCPRegInfo id_cp_reginfo
[] = {
8767 /* These are common to v8 and pre-v8 */
8769 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8770 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8771 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8772 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8773 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8774 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8776 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8777 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8779 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8781 .accessfn
= access_aa32_tid1
,
8782 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8784 /* TLBTR is specific to VMSA */
8785 ARMCPRegInfo id_tlbtr_reginfo
= {
8787 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8789 .accessfn
= access_aa32_tid1
,
8790 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8792 /* MPUIR is specific to PMSA V6+ */
8793 ARMCPRegInfo id_mpuir_reginfo
= {
8795 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8796 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8797 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8799 /* HMPUIR is specific to PMSA V8 */
8800 ARMCPRegInfo id_hmpuir_reginfo
= {
8802 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
8803 .access
= PL2_R
, .type
= ARM_CP_CONST
,
8804 .resetvalue
= cpu
->pmsav8r_hdregion
8806 static const ARMCPRegInfo crn0_wi_reginfo
= {
8807 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8808 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8809 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8811 #ifdef CONFIG_USER_ONLY
8812 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8813 { .name
= "MIDR_EL1",
8814 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
8815 R_MIDR_EL1_PARTNUM_MASK
|
8816 R_MIDR_EL1_ARCHITECTURE_MASK
|
8817 R_MIDR_EL1_VARIANT_MASK
|
8818 R_MIDR_EL1_IMPLEMENTER_MASK
},
8819 { .name
= "REVIDR_EL1" },
8821 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8823 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8824 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8827 * Register the blanket "writes ignored" value first to cover the
8828 * whole space. Then update the specific ID registers to allow write
8829 * access, so that they ignore writes rather than causing them to
8832 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8833 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8834 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8836 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8837 id_cp_reginfo
[i
].access
= PL1_RW
;
8839 id_mpuir_reginfo
.access
= PL1_RW
;
8840 id_tlbtr_reginfo
.access
= PL1_RW
;
8842 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8843 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8844 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8845 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
8848 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8850 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8851 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8852 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8853 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
8854 arm_feature(env
, ARM_FEATURE_V8
)) {
8858 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8859 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
8860 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
8862 /* Register alias is only valid for first 32 indexes */
8863 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
8864 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
8865 uint8_t opc1
= extract32(i
, 4, 1);
8866 uint8_t opc2
= extract32(i
, 0, 1) << 2;
8868 tmp_string
= g_strdup_printf("PRBAR%u", i
);
8869 ARMCPRegInfo tmp_prbarn_reginfo
= {
8870 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
8871 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8872 .access
= PL1_RW
, .resetvalue
= 0,
8873 .accessfn
= access_tvm_trvm
,
8874 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8876 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
8879 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
8880 tmp_string
= g_strdup_printf("PRLAR%u", i
);
8881 ARMCPRegInfo tmp_prlarn_reginfo
= {
8882 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
8883 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8884 .access
= PL1_RW
, .resetvalue
= 0,
8885 .accessfn
= access_tvm_trvm
,
8886 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8888 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
8892 /* Register alias is only valid for first 32 indexes */
8893 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
8894 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
8895 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
8896 uint8_t opc2
= extract32(i
, 0, 1) << 2;
8898 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
8899 ARMCPRegInfo tmp_hprbarn_reginfo
= {
8901 .type
= ARM_CP_NO_RAW
,
8902 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8903 .access
= PL2_RW
, .resetvalue
= 0,
8904 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8906 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
8909 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
8910 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
8911 ARMCPRegInfo tmp_hprlarn_reginfo
= {
8913 .type
= ARM_CP_NO_RAW
,
8914 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
8915 .access
= PL2_RW
, .resetvalue
= 0,
8916 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
8918 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
8921 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8922 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8926 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8927 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8928 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8929 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8930 .fgt
= FGT_MPIDR_EL1
,
8931 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8933 #ifdef CONFIG_USER_ONLY
8934 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8935 { .name
= "MPIDR_EL1",
8936 .fixed_bits
= 0x0000000080000000 },
8938 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8940 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8943 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8944 ARMCPRegInfo auxcr_reginfo
[] = {
8945 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8946 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8947 .access
= PL1_RW
, .accessfn
= access_tacr
,
8948 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8949 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8950 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8951 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8953 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8954 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8955 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8958 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8959 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8960 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8964 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8966 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8967 * There are two flavours:
8968 * (1) older 32-bit only cores have a simple 32-bit CBAR
8969 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8970 * 32-bit register visible to AArch32 at a different encoding
8971 * to the "flavour 1" register and with the bits rearranged to
8972 * be able to squash a 64-bit address into the 32-bit view.
8973 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8974 * in future if we support AArch32-only configs of some of the
8975 * AArch64 cores we might need to add a specific feature flag
8976 * to indicate cores with "flavour 2" CBAR.
8978 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8979 /* 32 bit view is [31:18] 0...0 [43:32]. */
8980 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8981 | extract64(cpu
->reset_cbar
, 32, 12);
8982 ARMCPRegInfo cbar_reginfo
[] = {
8984 .type
= ARM_CP_CONST
,
8985 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8986 .access
= PL1_R
, .resetvalue
= cbar32
},
8987 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8988 .type
= ARM_CP_CONST
,
8989 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8990 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8992 /* We don't implement a r/w 64 bit CBAR currently */
8993 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8994 define_arm_cp_regs(cpu
, cbar_reginfo
);
8996 ARMCPRegInfo cbar
= {
8998 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8999 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9000 .fieldoffset
= offsetof(CPUARMState
,
9001 cp15
.c15_config_base_address
)
9003 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9004 cbar
.access
= PL1_R
;
9005 cbar
.fieldoffset
= 0;
9006 cbar
.type
= ARM_CP_CONST
;
9008 define_one_arm_cp_reg(cpu
, &cbar
);
9012 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9013 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9014 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9015 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9016 .access
= PL1_RW
, .writefn
= vbar_write
,
9017 .fgt
= FGT_VBAR_EL1
,
9018 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9019 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9022 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9025 /* Generic registers whose values depend on the implementation */
9027 ARMCPRegInfo sctlr
= {
9028 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9029 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9030 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9031 .fgt
= FGT_SCTLR_EL1
,
9032 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9033 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9034 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9035 .raw_writefn
= raw_write
,
9037 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9039 * Normally we would always end the TB on an SCTLR write, but Linux
9040 * arch/arm/mach-pxa/sleep.S expects two instructions following
9041 * an MMU enable to execute from cache. Imitate this behaviour.
9043 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9045 define_one_arm_cp_reg(cpu
, &sctlr
);
9047 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9048 arm_feature(env
, ARM_FEATURE_V8
)) {
9049 ARMCPRegInfo vsctlr
= {
9050 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9051 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9052 .access
= PL2_RW
, .resetvalue
= 0x0,
9053 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9055 define_one_arm_cp_reg(cpu
, &vsctlr
);
9059 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9060 define_arm_cp_regs(cpu
, lor_reginfo
);
9062 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9063 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9065 #ifndef CONFIG_USER_ONLY
9066 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9067 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9069 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9070 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9073 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9074 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9077 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9078 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9080 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9081 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9083 if (cpu_isar_feature(any_ras
, cpu
)) {
9084 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9087 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9088 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9089 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9091 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9092 define_arm_cp_regs(cpu
, vhe_reginfo
);
9095 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9096 define_arm_cp_regs(cpu
, zcr_reginfo
);
9099 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9100 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9103 #ifdef TARGET_AARCH64
9104 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9105 define_arm_cp_regs(cpu
, sme_reginfo
);
9107 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9108 define_arm_cp_regs(cpu
, pauth_reginfo
);
9110 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9111 define_arm_cp_regs(cpu
, rndr_reginfo
);
9113 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9114 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9116 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9117 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9119 #ifndef CONFIG_USER_ONLY
9120 /* Data Cache clean instructions up to PoP */
9121 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9122 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9124 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9125 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9128 #endif /*CONFIG_USER_ONLY*/
9131 * If full MTE is enabled, add all of the system registers.
9132 * If only "instructions available at EL0" are enabled,
9133 * then define only a RAZ/WI version of PSTATE.TCO.
9135 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9136 define_arm_cp_regs(cpu
, mte_reginfo
);
9137 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9138 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9139 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9140 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9143 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9144 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9147 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9148 define_arm_cp_regs(cpu
, fgt_reginfo
);
9152 if (cpu_isar_feature(any_predinv
, cpu
)) {
9153 define_arm_cp_regs(cpu
, predinv_reginfo
);
9156 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9157 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9160 #ifndef CONFIG_USER_ONLY
9162 * Register redirections and aliases must be done last,
9163 * after the registers from the other extensions have been defined.
9165 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9166 define_arm_vh_e2h_redirects_aliases(cpu
);
9171 /* Sort alphabetically by type name, except for "any". */
9172 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
9174 ObjectClass
*class_a
= (ObjectClass
*)a
;
9175 ObjectClass
*class_b
= (ObjectClass
*)b
;
9176 const char *name_a
, *name_b
;
9178 name_a
= object_class_get_name(class_a
);
9179 name_b
= object_class_get_name(class_b
);
9180 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
9182 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
9185 return strcmp(name_a
, name_b
);
9189 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
9191 ObjectClass
*oc
= data
;
9192 CPUClass
*cc
= CPU_CLASS(oc
);
9193 const char *typename
;
9196 typename
= object_class_get_name(oc
);
9197 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9198 if (cc
->deprecation_note
) {
9199 qemu_printf(" %s (deprecated)\n", name
);
9201 qemu_printf(" %s\n", name
);
9206 void arm_cpu_list(void)
9210 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9211 list
= g_slist_sort(list
, arm_cpu_list_compare
);
9212 qemu_printf("Available CPUs:\n");
9213 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
9217 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
9219 ObjectClass
*oc
= data
;
9220 CpuDefinitionInfoList
**cpu_list
= user_data
;
9221 CpuDefinitionInfo
*info
;
9222 const char *typename
;
9224 typename
= object_class_get_name(oc
);
9225 info
= g_malloc0(sizeof(*info
));
9226 info
->name
= g_strndup(typename
,
9227 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9228 info
->q_typename
= g_strdup(typename
);
9230 QAPI_LIST_PREPEND(*cpu_list
, info
);
9233 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
9235 CpuDefinitionInfoList
*cpu_list
= NULL
;
9238 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9239 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
9246 * Private utility function for define_one_arm_cp_reg_with_opaque():
9247 * add a single reginfo struct to the hash table.
9249 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9250 void *opaque
, CPState state
,
9251 CPSecureState secstate
,
9252 int crm
, int opc1
, int opc2
,
9255 CPUARMState
*env
= &cpu
->env
;
9258 bool is64
= r
->type
& ARM_CP_64BIT
;
9259 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9265 case ARM_CP_STATE_AA32
:
9266 /* We assume it is a cp15 register if the .cp field is left unset. */
9267 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9270 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9272 case ARM_CP_STATE_AA64
:
9274 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9275 * cp == 0 as equivalent to the value for "standard guest-visible
9276 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9277 * in their AArch64 view (the .cp value may be non-zero for the
9278 * benefit of the AArch32 view).
9280 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9281 cp
= CP_REG_ARM64_SYSREG_CP
;
9283 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9286 g_assert_not_reached();
9289 /* Overriding of an existing definition must be explicitly requested. */
9290 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9291 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9293 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9298 * Eliminate registers that are not present because the EL is missing.
9299 * Doing this here makes it easier to put all registers for a given
9300 * feature into the same ARMCPRegInfo array and define them all at once.
9303 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9305 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9306 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9308 int min_el
= ctz32(r
->access
) / 2;
9309 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9310 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9313 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9316 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9318 if ((r
->access
& max_el
) == 0) {
9323 /* Combine cpreg and name into one allocation. */
9324 name_len
= strlen(name
) + 1;
9325 r2
= g_malloc(sizeof(*r2
) + name_len
);
9327 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9330 * Update fields to match the instantiation, overwiting wildcards
9331 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9338 r2
->secure
= secstate
;
9340 r2
->opaque
= opaque
;
9344 /* This should not have been a very special register to begin. */
9345 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9346 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9348 * Set the special function to CONST, retaining the other flags.
9349 * This is important for e.g. ARM_CP_SVE so that we still
9350 * take the SVE trap if CPTR_EL3.EZ == 0.
9352 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9354 * Usually, these registers become RES0, but there are a few
9355 * special cases like VPIDR_EL2 which have a constant non-zero
9356 * value with writes ignored.
9358 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9362 * ARM_CP_CONST has precedence, so removing the callbacks and
9363 * offsets are not strictly necessary, but it is potentially
9364 * less confusing to debug later.
9368 r2
->raw_readfn
= NULL
;
9369 r2
->raw_writefn
= NULL
;
9371 r2
->fieldoffset
= 0;
9372 r2
->bank_fieldoffsets
[0] = 0;
9373 r2
->bank_fieldoffsets
[1] = 0;
9375 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9379 * Register is banked (using both entries in array).
9380 * Overwriting fieldoffset as the array is only used to define
9381 * banked registers but later only fieldoffset is used.
9383 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9385 if (state
== ARM_CP_STATE_AA32
) {
9388 * If the register is banked then we don't need to migrate or
9389 * reset the 32-bit instance in certain cases:
9391 * 1) If the register has both 32-bit and 64-bit instances
9392 * then we can count on the 64-bit instance taking care
9393 * of the non-secure bank.
9394 * 2) If ARMv8 is enabled then we can count on a 64-bit
9395 * version taking care of the secure bank. This requires
9396 * that separate 32 and 64-bit definitions are provided.
9398 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9399 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9400 r2
->type
|= ARM_CP_ALIAS
;
9402 } else if ((secstate
!= r
->secure
) && !ns
) {
9404 * The register is not banked so we only want to allow
9405 * migration of the non-secure instance.
9407 r2
->type
|= ARM_CP_ALIAS
;
9410 if (HOST_BIG_ENDIAN
&&
9411 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9412 r2
->fieldoffset
+= sizeof(uint32_t);
9418 * By convention, for wildcarded registers only the first
9419 * entry is used for migration; the others are marked as
9420 * ALIAS so we don't try to transfer the register
9421 * multiple times. Special registers (ie NOP/WFI) are
9422 * never migratable and not even raw-accessible.
9424 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9425 r2
->type
|= ARM_CP_NO_RAW
;
9427 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9428 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9429 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9430 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9434 * Check that raw accesses are either forbidden or handled. Note that
9435 * we can't assert this earlier because the setup of fieldoffset for
9436 * banked registers has to be done first.
9438 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9439 assert(!raw_accessors_invalid(r2
));
9442 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9446 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9447 const ARMCPRegInfo
*r
, void *opaque
)
9450 * Define implementations of coprocessor registers.
9451 * We store these in a hashtable because typically
9452 * there are less than 150 registers in a space which
9453 * is 16*16*16*8*8 = 262144 in size.
9454 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9455 * If a register is defined twice then the second definition is
9456 * used, so this can be used to define some generic registers and
9457 * then override them with implementation specific variations.
9458 * At least one of the original and the second definition should
9459 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9460 * against accidental use.
9462 * The state field defines whether the register is to be
9463 * visible in the AArch32 or AArch64 execution state. If the
9464 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9465 * reginfo structure for the AArch32 view, which sees the lower
9466 * 32 bits of the 64 bit register.
9468 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9469 * be wildcarded. AArch64 registers are always considered to be 64
9470 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9471 * the register, if any.
9473 int crm
, opc1
, opc2
;
9474 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9475 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9476 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9477 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9478 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9479 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9482 /* 64 bit registers have only CRm and Opc1 fields */
9483 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9484 /* op0 only exists in the AArch64 encodings */
9485 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9486 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9487 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9489 * This API is only for Arm's system coprocessors (14 and 15) or
9490 * (M-profile or v7A-and-earlier only) for implementation defined
9491 * coprocessors in the range 0..7. Our decode assumes this, since
9492 * 8..13 can be used for other insns including VFP and Neon. See
9493 * valid_cp() in translate.c. Assert here that we haven't tried
9494 * to use an invalid coprocessor number.
9497 case ARM_CP_STATE_BOTH
:
9498 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9503 case ARM_CP_STATE_AA32
:
9504 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9505 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9506 assert(r
->cp
>= 14 && r
->cp
<= 15);
9508 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9511 case ARM_CP_STATE_AA64
:
9512 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9515 g_assert_not_reached();
9518 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9519 * encodes a minimum access level for the register. We roll this
9520 * runtime check into our general permission check code, so check
9521 * here that the reginfo's specified permissions are strict enough
9522 * to encompass the generic architectural permission check.
9524 if (r
->state
!= ARM_CP_STATE_AA32
) {
9525 CPAccessRights mask
;
9528 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9529 mask
= PL0U_R
| PL1_RW
;
9549 /* min_EL EL1, secure mode only (we don't check the latter) */
9553 /* broken reginfo with out-of-range opc1 */
9554 g_assert_not_reached();
9556 /* assert our permissions are not too lax (stricter is fine) */
9557 assert((r
->access
& ~mask
) == 0);
9561 * Check that the register definition has enough info to handle
9562 * reads and writes if they are permitted.
9564 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9565 if (r
->access
& PL3_R
) {
9566 assert((r
->fieldoffset
||
9567 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9570 if (r
->access
& PL3_W
) {
9571 assert((r
->fieldoffset
||
9572 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9577 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9578 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9579 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9580 for (state
= ARM_CP_STATE_AA32
;
9581 state
<= ARM_CP_STATE_AA64
; state
++) {
9582 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9585 if (state
== ARM_CP_STATE_AA32
) {
9587 * Under AArch32 CP registers can be common
9588 * (same for secure and non-secure world) or banked.
9592 switch (r
->secure
) {
9593 case ARM_CP_SECSTATE_S
:
9594 case ARM_CP_SECSTATE_NS
:
9595 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9596 r
->secure
, crm
, opc1
, opc2
,
9599 case ARM_CP_SECSTATE_BOTH
:
9600 name
= g_strdup_printf("%s_S", r
->name
);
9601 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9603 crm
, opc1
, opc2
, name
);
9605 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9607 crm
, opc1
, opc2
, r
->name
);
9610 g_assert_not_reached();
9614 * AArch64 registers get mapped to non-secure instance
9617 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9619 crm
, opc1
, opc2
, r
->name
);
9627 /* Define a whole list of registers */
9628 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
9629 void *opaque
, size_t len
)
9632 for (i
= 0; i
< len
; ++i
) {
9633 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
9638 * Modify ARMCPRegInfo for access from userspace.
9640 * This is a data driven modification directed by
9641 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9642 * user-space cannot alter any values and dynamic values pertaining to
9643 * execution state are hidden from user space view anyway.
9645 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
9646 const ARMCPRegUserSpaceInfo
*mods
,
9649 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9650 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9651 GPatternSpec
*pat
= NULL
;
9654 pat
= g_pattern_spec_new(m
->name
);
9656 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9657 ARMCPRegInfo
*r
= regs
+ ri
;
9659 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9660 r
->type
= ARM_CP_CONST
;
9664 } else if (strcmp(r
->name
, m
->name
) == 0) {
9665 r
->type
= ARM_CP_CONST
;
9667 r
->resetvalue
&= m
->exported_bits
;
9668 r
->resetvalue
|= m
->fixed_bits
;
9673 g_pattern_spec_free(pat
);
9678 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9680 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9683 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9686 /* Helper coprocessor write function for write-ignore registers */
9689 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9691 /* Helper coprocessor write function for read-as-zero registers */
9695 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9697 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9700 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9703 * Return true if it is not valid for us to switch to
9704 * this CPU mode (ie all the UNPREDICTABLE cases in
9705 * the ARM ARM CPSRWriteByInstr pseudocode).
9708 /* Changes to or from Hyp via MSR and CPS are illegal. */
9709 if (write_type
== CPSRWriteByInstr
&&
9710 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9711 mode
== ARM_CPU_MODE_HYP
)) {
9716 case ARM_CPU_MODE_USR
:
9718 case ARM_CPU_MODE_SYS
:
9719 case ARM_CPU_MODE_SVC
:
9720 case ARM_CPU_MODE_ABT
:
9721 case ARM_CPU_MODE_UND
:
9722 case ARM_CPU_MODE_IRQ
:
9723 case ARM_CPU_MODE_FIQ
:
9725 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
9726 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9729 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9730 * and CPS are treated as illegal mode changes.
9732 if (write_type
== CPSRWriteByInstr
&&
9733 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9734 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9738 case ARM_CPU_MODE_HYP
:
9739 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9740 case ARM_CPU_MODE_MON
:
9741 return arm_current_el(env
) < 3;
9747 uint32_t cpsr_read(CPUARMState
*env
)
9750 ZF
= (env
->ZF
== 0);
9751 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9752 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9753 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9754 | ((env
->condexec_bits
& 0xfc) << 8)
9755 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9758 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9759 CPSRWriteType write_type
)
9761 uint32_t changed_daif
;
9762 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9763 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9765 if (mask
& CPSR_NZCV
) {
9766 env
->ZF
= (~val
) & CPSR_Z
;
9768 env
->CF
= (val
>> 29) & 1;
9769 env
->VF
= (val
<< 3) & 0x80000000;
9771 if (mask
& CPSR_Q
) {
9772 env
->QF
= ((val
& CPSR_Q
) != 0);
9774 if (mask
& CPSR_T
) {
9775 env
->thumb
= ((val
& CPSR_T
) != 0);
9777 if (mask
& CPSR_IT_0_1
) {
9778 env
->condexec_bits
&= ~3;
9779 env
->condexec_bits
|= (val
>> 25) & 3;
9781 if (mask
& CPSR_IT_2_7
) {
9782 env
->condexec_bits
&= 3;
9783 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9785 if (mask
& CPSR_GE
) {
9786 env
->GE
= (val
>> 16) & 0xf;
9790 * In a V7 implementation that includes the security extensions but does
9791 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9792 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9793 * bits respectively.
9795 * In a V8 implementation, it is permitted for privileged software to
9796 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9798 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9799 arm_feature(env
, ARM_FEATURE_EL3
) &&
9800 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9801 !arm_is_secure(env
)) {
9803 changed_daif
= (env
->daif
^ val
) & mask
;
9805 if (changed_daif
& CPSR_A
) {
9807 * Check to see if we are allowed to change the masking of async
9808 * abort exceptions from a non-secure state.
9810 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9811 qemu_log_mask(LOG_GUEST_ERROR
,
9812 "Ignoring attempt to switch CPSR_A flag from "
9813 "non-secure world with SCR.AW bit clear\n");
9818 if (changed_daif
& CPSR_F
) {
9820 * Check to see if we are allowed to change the masking of FIQ
9821 * exceptions from a non-secure state.
9823 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9824 qemu_log_mask(LOG_GUEST_ERROR
,
9825 "Ignoring attempt to switch CPSR_F flag from "
9826 "non-secure world with SCR.FW bit clear\n");
9831 * Check whether non-maskable FIQ (NMFI) support is enabled.
9832 * If this bit is set software is not allowed to mask
9833 * FIQs, but is allowed to set CPSR_F to 0.
9835 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9837 qemu_log_mask(LOG_GUEST_ERROR
,
9838 "Ignoring attempt to enable CPSR_F flag "
9839 "(non-maskable FIQ [NMFI] support enabled)\n");
9845 env
->daif
&= ~(CPSR_AIF
& mask
);
9846 env
->daif
|= val
& CPSR_AIF
& mask
;
9848 if (write_type
!= CPSRWriteRaw
&&
9849 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9850 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9852 * Note that we can only get here in USR mode if this is a
9853 * gdb stub write; for this case we follow the architectural
9854 * behaviour for guest writes in USR mode of ignoring an attempt
9855 * to switch mode. (Those are caught by translate.c for writes
9856 * triggered by guest instructions.)
9859 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9861 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9862 * v7, and has defined behaviour in v8:
9863 * + leave CPSR.M untouched
9864 * + allow changes to the other CPSR fields
9866 * For user changes via the GDB stub, we don't set PSTATE.IL,
9867 * as this would be unnecessarily harsh for a user error.
9870 if (write_type
!= CPSRWriteByGDBStub
&&
9871 arm_feature(env
, ARM_FEATURE_V8
)) {
9875 qemu_log_mask(LOG_GUEST_ERROR
,
9876 "Illegal AArch32 mode switch attempt from %s to %s\n",
9877 aarch32_mode_name(env
->uncached_cpsr
),
9878 aarch32_mode_name(val
));
9880 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9881 write_type
== CPSRWriteExceptionReturn
?
9882 "Exception return from AArch32" :
9883 "AArch32 mode switch from",
9884 aarch32_mode_name(env
->uncached_cpsr
),
9885 aarch32_mode_name(val
), env
->regs
[15]);
9886 switch_mode(env
, val
& CPSR_M
);
9889 mask
&= ~CACHED_CPSR_BITS
;
9890 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9891 if (tcg_enabled() && rebuild_hflags
) {
9892 arm_rebuild_hflags(env
);
9896 /* Sign/zero extend */
9897 uint32_t HELPER(sxtb16
)(uint32_t x
)
9900 res
= (uint16_t)(int8_t)x
;
9901 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9905 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9908 * Take a division-by-zero exception if necessary; otherwise return
9909 * to get the usual non-trapping division behaviour (result of 0)
9911 if (arm_feature(env
, ARM_FEATURE_M
)
9912 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9913 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9917 uint32_t HELPER(uxtb16
)(uint32_t x
)
9920 res
= (uint16_t)(uint8_t)x
;
9921 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9925 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9928 handle_possible_div0_trap(env
, GETPC());
9931 if (num
== INT_MIN
&& den
== -1) {
9937 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9940 handle_possible_div0_trap(env
, GETPC());
9946 uint32_t HELPER(rbit
)(uint32_t x
)
9951 #ifdef CONFIG_USER_ONLY
9953 static void switch_mode(CPUARMState
*env
, int mode
)
9955 ARMCPU
*cpu
= env_archcpu(env
);
9957 if (mode
!= ARM_CPU_MODE_USR
) {
9958 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9962 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9963 uint32_t cur_el
, bool secure
)
9968 void aarch64_sync_64_to_32(CPUARMState
*env
)
9970 g_assert_not_reached();
9975 static void switch_mode(CPUARMState
*env
, int mode
)
9980 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9981 if (mode
== old_mode
) {
9985 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9986 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9987 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9988 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9989 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9990 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9993 i
= bank_number(old_mode
);
9994 env
->banked_r13
[i
] = env
->regs
[13];
9995 env
->banked_spsr
[i
] = env
->spsr
;
9997 i
= bank_number(mode
);
9998 env
->regs
[13] = env
->banked_r13
[i
];
9999 env
->spsr
= env
->banked_spsr
[i
];
10001 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10002 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10006 * Physical Interrupt Target EL Lookup Table
10008 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10010 * The below multi-dimensional table is used for looking up the target
10011 * exception level given numerous condition criteria. Specifically, the
10012 * target EL is based on SCR and HCR routing controls as well as the
10013 * currently executing EL and secure state.
10016 * target_el_table[2][2][2][2][2][4]
10017 * | | | | | +--- Current EL
10018 * | | | | +------ Non-secure(0)/Secure(1)
10019 * | | | +--------- HCR mask override
10020 * | | +------------ SCR exec state control
10021 * | +--------------- SCR mask override
10022 * +------------------ 32-bit(0)/64-bit(1) EL3
10024 * The table values are as such:
10026 * -1 = Cannot occur
10028 * The ARM ARM target EL table includes entries indicating that an "exception
10029 * is not taken". The two cases where this is applicable are:
10030 * 1) An exception is taken from EL3 but the SCR does not have the exception
10032 * 2) An exception is taken from EL2 but the HCR does not have the exception
10034 * In these two cases, the below table contain a target of EL1. This value is
10035 * returned as it is expected that the consumer of the table data will check
10036 * for "target EL >= current EL" to ensure the exception is not taken.
10040 * BIT IRQ IMO Non-secure Secure
10041 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10043 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10044 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10045 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10046 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10047 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10048 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10049 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10050 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10051 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10052 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10053 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10054 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10055 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10056 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10057 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10058 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10059 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10063 * Determine the target EL for physical exceptions
10065 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10066 uint32_t cur_el
, bool secure
)
10068 CPUARMState
*env
= cs
->env_ptr
;
10073 /* Is the highest EL AArch64? */
10074 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10077 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10078 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10081 * Either EL2 is the highest EL (and so the EL2 register width
10082 * is given by is64); or there is no EL2 or EL3, in which case
10083 * the value of 'rw' does not affect the table lookup anyway.
10088 hcr_el2
= arm_hcr_el2_eff(env
);
10089 switch (excp_idx
) {
10091 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10092 hcr
= hcr_el2
& HCR_IMO
;
10095 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10096 hcr
= hcr_el2
& HCR_FMO
;
10099 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10100 hcr
= hcr_el2
& HCR_AMO
;
10105 * For these purposes, TGE and AMO/IMO/FMO both force the
10106 * interrupt to EL2. Fold TGE into the bit extracted above.
10108 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10110 /* Perform a table-lookup for the target EL given the current state */
10111 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10113 assert(target_el
> 0);
10118 void arm_log_exception(CPUState
*cs
)
10120 int idx
= cs
->exception_index
;
10122 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10123 const char *exc
= NULL
;
10124 static const char * const excnames
[] = {
10125 [EXCP_UDEF
] = "Undefined Instruction",
10126 [EXCP_SWI
] = "SVC",
10127 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10128 [EXCP_DATA_ABORT
] = "Data Abort",
10129 [EXCP_IRQ
] = "IRQ",
10130 [EXCP_FIQ
] = "FIQ",
10131 [EXCP_BKPT
] = "Breakpoint",
10132 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10133 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10134 [EXCP_HVC
] = "Hypervisor Call",
10135 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10136 [EXCP_SMC
] = "Secure Monitor Call",
10137 [EXCP_VIRQ
] = "Virtual IRQ",
10138 [EXCP_VFIQ
] = "Virtual FIQ",
10139 [EXCP_SEMIHOST
] = "Semihosting call",
10140 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10141 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10142 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10143 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10144 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10145 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10146 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10147 [EXCP_VSERR
] = "Virtual SERR",
10150 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10151 exc
= excnames
[idx
];
10156 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10157 idx
, exc
, cs
->cpu_index
);
10162 * Function used to synchronize QEMU's AArch64 register set with AArch32
10163 * register set. This is necessary when switching between AArch32 and AArch64
10166 void aarch64_sync_32_to_64(CPUARMState
*env
)
10169 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10171 /* We can blanket copy R[0:7] to X[0:7] */
10172 for (i
= 0; i
< 8; i
++) {
10173 env
->xregs
[i
] = env
->regs
[i
];
10177 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10178 * Otherwise, they come from the banked user regs.
10180 if (mode
== ARM_CPU_MODE_FIQ
) {
10181 for (i
= 8; i
< 13; i
++) {
10182 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10185 for (i
= 8; i
< 13; i
++) {
10186 env
->xregs
[i
] = env
->regs
[i
];
10191 * Registers x13-x23 are the various mode SP and FP registers. Registers
10192 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10193 * from the mode banked register.
10195 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10196 env
->xregs
[13] = env
->regs
[13];
10197 env
->xregs
[14] = env
->regs
[14];
10199 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10200 /* HYP is an exception in that it is copied from r14 */
10201 if (mode
== ARM_CPU_MODE_HYP
) {
10202 env
->xregs
[14] = env
->regs
[14];
10204 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10208 if (mode
== ARM_CPU_MODE_HYP
) {
10209 env
->xregs
[15] = env
->regs
[13];
10211 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10214 if (mode
== ARM_CPU_MODE_IRQ
) {
10215 env
->xregs
[16] = env
->regs
[14];
10216 env
->xregs
[17] = env
->regs
[13];
10218 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10219 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10222 if (mode
== ARM_CPU_MODE_SVC
) {
10223 env
->xregs
[18] = env
->regs
[14];
10224 env
->xregs
[19] = env
->regs
[13];
10226 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10227 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10230 if (mode
== ARM_CPU_MODE_ABT
) {
10231 env
->xregs
[20] = env
->regs
[14];
10232 env
->xregs
[21] = env
->regs
[13];
10234 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10235 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10238 if (mode
== ARM_CPU_MODE_UND
) {
10239 env
->xregs
[22] = env
->regs
[14];
10240 env
->xregs
[23] = env
->regs
[13];
10242 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10243 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10247 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10248 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10249 * FIQ bank for r8-r14.
10251 if (mode
== ARM_CPU_MODE_FIQ
) {
10252 for (i
= 24; i
< 31; i
++) {
10253 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10256 for (i
= 24; i
< 29; i
++) {
10257 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10259 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10260 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10263 env
->pc
= env
->regs
[15];
10267 * Function used to synchronize QEMU's AArch32 register set with AArch64
10268 * register set. This is necessary when switching between AArch32 and AArch64
10271 void aarch64_sync_64_to_32(CPUARMState
*env
)
10274 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10276 /* We can blanket copy X[0:7] to R[0:7] */
10277 for (i
= 0; i
< 8; i
++) {
10278 env
->regs
[i
] = env
->xregs
[i
];
10282 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10283 * Otherwise, we copy x8-x12 into the banked user regs.
10285 if (mode
== ARM_CPU_MODE_FIQ
) {
10286 for (i
= 8; i
< 13; i
++) {
10287 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10290 for (i
= 8; i
< 13; i
++) {
10291 env
->regs
[i
] = env
->xregs
[i
];
10296 * Registers r13 & r14 depend on the current mode.
10297 * If we are in a given mode, we copy the corresponding x registers to r13
10298 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10301 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10302 env
->regs
[13] = env
->xregs
[13];
10303 env
->regs
[14] = env
->xregs
[14];
10305 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10308 * HYP is an exception in that it does not have its own banked r14 but
10309 * shares the USR r14
10311 if (mode
== ARM_CPU_MODE_HYP
) {
10312 env
->regs
[14] = env
->xregs
[14];
10314 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10318 if (mode
== ARM_CPU_MODE_HYP
) {
10319 env
->regs
[13] = env
->xregs
[15];
10321 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10324 if (mode
== ARM_CPU_MODE_IRQ
) {
10325 env
->regs
[14] = env
->xregs
[16];
10326 env
->regs
[13] = env
->xregs
[17];
10328 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10329 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10332 if (mode
== ARM_CPU_MODE_SVC
) {
10333 env
->regs
[14] = env
->xregs
[18];
10334 env
->regs
[13] = env
->xregs
[19];
10336 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10337 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10340 if (mode
== ARM_CPU_MODE_ABT
) {
10341 env
->regs
[14] = env
->xregs
[20];
10342 env
->regs
[13] = env
->xregs
[21];
10344 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10345 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10348 if (mode
== ARM_CPU_MODE_UND
) {
10349 env
->regs
[14] = env
->xregs
[22];
10350 env
->regs
[13] = env
->xregs
[23];
10352 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10353 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10357 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10358 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10359 * FIQ bank for r8-r14.
10361 if (mode
== ARM_CPU_MODE_FIQ
) {
10362 for (i
= 24; i
< 31; i
++) {
10363 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10366 for (i
= 24; i
< 29; i
++) {
10367 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10369 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10370 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10373 env
->regs
[15] = env
->pc
;
10376 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10377 uint32_t mask
, uint32_t offset
,
10382 /* Change the CPU state so as to actually take the exception. */
10383 switch_mode(env
, new_mode
);
10386 * For exceptions taken to AArch32 we must clear the SS bit in both
10387 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10389 env
->pstate
&= ~PSTATE_SS
;
10390 env
->spsr
= cpsr_read(env
);
10391 /* Clear IT bits. */
10392 env
->condexec_bits
= 0;
10393 /* Switch to the new mode, and to the correct instruction set. */
10394 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10396 /* This must be after mode switching. */
10397 new_el
= arm_current_el(env
);
10399 /* Set new mode endianness */
10400 env
->uncached_cpsr
&= ~CPSR_E
;
10401 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10402 env
->uncached_cpsr
|= CPSR_E
;
10404 /* J and IL must always be cleared for exception entry */
10405 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10408 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10409 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10410 env
->uncached_cpsr
|= CPSR_SSBS
;
10412 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10416 if (new_mode
== ARM_CPU_MODE_HYP
) {
10417 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10418 env
->elr_el
[2] = env
->regs
[15];
10420 /* CPSR.PAN is normally preserved preserved unless... */
10421 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10424 if (!arm_is_secure_below_el3(env
)) {
10425 /* ... the target is EL3, from non-secure state. */
10426 env
->uncached_cpsr
&= ~CPSR_PAN
;
10429 /* ... the target is EL3, from secure state ... */
10432 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10433 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10434 env
->uncached_cpsr
|= CPSR_PAN
;
10440 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10441 * and we should just guard the thumb mode on V4
10443 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10445 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10447 env
->regs
[14] = env
->regs
[15] + offset
;
10449 env
->regs
[15] = newpc
;
10451 if (tcg_enabled()) {
10452 arm_rebuild_hflags(env
);
10456 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10459 * Handle exception entry to Hyp mode; this is sufficiently
10460 * different to entry to other AArch32 modes that we handle it
10463 * The vector table entry used is always the 0x14 Hyp mode entry point,
10464 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10465 * The offset applied to the preferred return address is always zero
10466 * (see DDI0487C.a section G1.12.3).
10467 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10469 uint32_t addr
, mask
;
10470 ARMCPU
*cpu
= ARM_CPU(cs
);
10471 CPUARMState
*env
= &cpu
->env
;
10473 switch (cs
->exception_index
) {
10481 /* Fall through to prefetch abort. */
10482 case EXCP_PREFETCH_ABORT
:
10483 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10484 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10485 (uint32_t)env
->exception
.vaddress
);
10488 case EXCP_DATA_ABORT
:
10489 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10490 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10491 (uint32_t)env
->exception
.vaddress
);
10503 case EXCP_HYP_TRAP
:
10507 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10510 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10511 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10513 * QEMU syndrome values are v8-style. v7 has the IL bit
10514 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10515 * If this is a v7 CPU, squash the IL bit in those cases.
10517 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10518 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10519 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10520 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10521 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10524 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10527 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10532 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10535 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10538 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10542 addr
+= env
->cp15
.hvbar
;
10544 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10547 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10549 ARMCPU
*cpu
= ARM_CPU(cs
);
10550 CPUARMState
*env
= &cpu
->env
;
10557 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10558 switch (syn_get_ec(env
->exception
.syndrome
)) {
10559 case EC_BREAKPOINT
:
10560 case EC_BREAKPOINT_SAME_EL
:
10563 case EC_WATCHPOINT
:
10564 case EC_WATCHPOINT_SAME_EL
:
10570 case EC_VECTORCATCH
:
10579 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10582 if (env
->exception
.target_el
== 2) {
10583 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10587 switch (cs
->exception_index
) {
10589 new_mode
= ARM_CPU_MODE_UND
;
10599 new_mode
= ARM_CPU_MODE_SVC
;
10602 /* The PC already points to the next instruction. */
10606 /* Fall through to prefetch abort. */
10607 case EXCP_PREFETCH_ABORT
:
10608 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10609 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10610 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10611 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10612 new_mode
= ARM_CPU_MODE_ABT
;
10614 mask
= CPSR_A
| CPSR_I
;
10617 case EXCP_DATA_ABORT
:
10618 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10619 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10620 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10621 env
->exception
.fsr
,
10622 (uint32_t)env
->exception
.vaddress
);
10623 new_mode
= ARM_CPU_MODE_ABT
;
10625 mask
= CPSR_A
| CPSR_I
;
10629 new_mode
= ARM_CPU_MODE_IRQ
;
10631 /* Disable IRQ and imprecise data aborts. */
10632 mask
= CPSR_A
| CPSR_I
;
10634 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10635 /* IRQ routed to monitor mode */
10636 new_mode
= ARM_CPU_MODE_MON
;
10641 new_mode
= ARM_CPU_MODE_FIQ
;
10643 /* Disable FIQ, IRQ and imprecise data aborts. */
10644 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10645 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10646 /* FIQ routed to monitor mode */
10647 new_mode
= ARM_CPU_MODE_MON
;
10652 new_mode
= ARM_CPU_MODE_IRQ
;
10654 /* Disable IRQ and imprecise data aborts. */
10655 mask
= CPSR_A
| CPSR_I
;
10659 new_mode
= ARM_CPU_MODE_FIQ
;
10661 /* Disable FIQ, IRQ and imprecise data aborts. */
10662 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10668 * Note that this is reported as a data abort, but the DFAR
10669 * has an UNKNOWN value. Construct the SError syndrome from
10670 * AET and ExT fields.
10672 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10674 if (extended_addresses_enabled(env
)) {
10675 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10677 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10679 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10680 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10681 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10682 env
->exception
.fsr
);
10684 new_mode
= ARM_CPU_MODE_ABT
;
10686 mask
= CPSR_A
| CPSR_I
;
10691 new_mode
= ARM_CPU_MODE_MON
;
10693 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10697 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10698 return; /* Never happens. Keep compiler happy. */
10701 if (new_mode
== ARM_CPU_MODE_MON
) {
10702 addr
+= env
->cp15
.mvbar
;
10703 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10704 /* High vectors. When enabled, base address cannot be remapped. */
10705 addr
+= 0xffff0000;
10708 * ARM v7 architectures provide a vector base address register to remap
10709 * the interrupt vector table.
10710 * This register is only followed in non-monitor mode, and is banked.
10711 * Note: only bits 31:5 are valid.
10713 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10716 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10717 env
->cp15
.scr_el3
&= ~SCR_NS
;
10720 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10723 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10726 * Return the register number of the AArch64 view of the AArch32
10727 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10728 * be that of the AArch32 mode the exception came from.
10730 int mode
= env
->uncached_cpsr
& CPSR_M
;
10732 switch (aarch32_reg
) {
10734 return aarch32_reg
;
10736 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10739 case ARM_CPU_MODE_USR
:
10740 case ARM_CPU_MODE_SYS
:
10742 case ARM_CPU_MODE_HYP
:
10744 case ARM_CPU_MODE_IRQ
:
10746 case ARM_CPU_MODE_SVC
:
10748 case ARM_CPU_MODE_ABT
:
10750 case ARM_CPU_MODE_UND
:
10752 case ARM_CPU_MODE_FIQ
:
10755 g_assert_not_reached();
10759 case ARM_CPU_MODE_USR
:
10760 case ARM_CPU_MODE_SYS
:
10761 case ARM_CPU_MODE_HYP
:
10763 case ARM_CPU_MODE_IRQ
:
10765 case ARM_CPU_MODE_SVC
:
10767 case ARM_CPU_MODE_ABT
:
10769 case ARM_CPU_MODE_UND
:
10771 case ARM_CPU_MODE_FIQ
:
10774 g_assert_not_reached();
10779 g_assert_not_reached();
10783 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10785 uint32_t ret
= cpsr_read(env
);
10787 /* Move DIT to the correct location for SPSR_ELx */
10788 if (ret
& CPSR_DIT
) {
10792 /* Merge PSTATE.SS into SPSR_ELx */
10793 ret
|= env
->pstate
& PSTATE_SS
;
10798 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
10800 /* Return true if this syndrome value is a synchronous external abort */
10801 switch (syn_get_ec(syndrome
)) {
10803 case EC_INSNABORT_SAME_EL
:
10805 case EC_DATAABORT_SAME_EL
:
10806 /* Look at fault status code for all the synchronous ext abort cases */
10807 switch (syndrome
& 0x3f) {
10823 /* Handle exception entry to a target EL which is using AArch64 */
10824 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10826 ARMCPU
*cpu
= ARM_CPU(cs
);
10827 CPUARMState
*env
= &cpu
->env
;
10828 unsigned int new_el
= env
->exception
.target_el
;
10829 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10830 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10831 unsigned int old_mode
;
10832 unsigned int cur_el
= arm_current_el(env
);
10835 if (tcg_enabled()) {
10837 * Note that new_el can never be 0. If cur_el is 0, then
10838 * el0_a64 is is_a64(), else el0_a64 is ignored.
10840 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10843 if (cur_el
< new_el
) {
10845 * Entry vector offset depends on whether the implemented EL
10846 * immediately lower than the target level is using AArch32 or AArch64
10853 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10856 hcr
= arm_hcr_el2_eff(env
);
10857 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10858 is_aa64
= (hcr
& HCR_RW
) != 0;
10863 is_aa64
= is_a64(env
);
10866 g_assert_not_reached();
10874 } else if (pstate_read(env
) & PSTATE_SP
) {
10878 switch (cs
->exception_index
) {
10879 case EXCP_PREFETCH_ABORT
:
10880 case EXCP_DATA_ABORT
:
10882 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
10883 * to be taken to the SError vector entrypoint.
10885 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
10886 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
10889 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10890 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10891 env
->cp15
.far_el
[new_el
]);
10897 case EXCP_HYP_TRAP
:
10899 switch (syn_get_ec(env
->exception
.syndrome
)) {
10900 case EC_ADVSIMDFPACCESSTRAP
:
10902 * QEMU internal FP/SIMD syndromes from AArch32 include the
10903 * TA and coproc fields which are only exposed if the exception
10904 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10905 * AArch64 format syndrome.
10907 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10909 case EC_CP14RTTRAP
:
10910 case EC_CP15RTTRAP
:
10911 case EC_CP14DTTRAP
:
10913 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10914 * the raw register field from the insn; when taking this to
10915 * AArch64 we must convert it to the AArch64 view of the register
10916 * number. Notice that we read a 4-bit AArch32 register number and
10917 * write back a 5-bit AArch64 one.
10919 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10920 rt
= aarch64_regnum(env
, rt
);
10921 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10924 case EC_CP15RRTTRAP
:
10925 case EC_CP14RRTTRAP
:
10926 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10927 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10928 rt
= aarch64_regnum(env
, rt
);
10929 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10931 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10932 rt
= aarch64_regnum(env
, rt
);
10933 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10937 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10949 /* Construct the SError syndrome from IDS and ISS fields. */
10950 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10951 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10954 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10958 old_mode
= pstate_read(env
);
10959 aarch64_save_sp(env
, arm_current_el(env
));
10960 env
->elr_el
[new_el
] = env
->pc
;
10962 old_mode
= cpsr_read_for_spsr_elx(env
);
10963 env
->elr_el
[new_el
] = env
->regs
[15];
10965 aarch64_sync_32_to_64(env
);
10967 env
->condexec_bits
= 0;
10969 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10971 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10972 env
->elr_el
[new_el
]);
10974 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10975 /* The value of PSTATE.PAN is normally preserved, except when ... */
10976 new_mode
|= old_mode
& PSTATE_PAN
;
10979 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10980 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10981 != (HCR_E2H
| HCR_TGE
)) {
10986 /* ... the target is EL1 ... */
10987 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10988 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10989 new_mode
|= PSTATE_PAN
;
10994 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10995 new_mode
|= PSTATE_TCO
;
10998 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10999 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11000 new_mode
|= PSTATE_SSBS
;
11002 new_mode
&= ~PSTATE_SSBS
;
11006 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11007 env
->aarch64
= true;
11008 aarch64_restore_sp(env
, new_el
);
11010 if (tcg_enabled()) {
11011 helper_rebuild_hflags_a64(env
, new_el
);
11016 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11017 new_el
, env
->pc
, pstate_read(env
));
11021 * Do semihosting call and set the appropriate return value. All the
11022 * permission and validity checks have been done at translate time.
11024 * We only see semihosting exceptions in TCG only as they are not
11025 * trapped to the hypervisor in KVM.
11028 static void tcg_handle_semihosting(CPUState
*cs
)
11030 ARMCPU
*cpu
= ARM_CPU(cs
);
11031 CPUARMState
*env
= &cpu
->env
;
11034 qemu_log_mask(CPU_LOG_INT
,
11035 "...handling as semihosting call 0x%" PRIx64
"\n",
11037 do_common_semihosting(cs
);
11040 qemu_log_mask(CPU_LOG_INT
,
11041 "...handling as semihosting call 0x%x\n",
11043 do_common_semihosting(cs
);
11044 env
->regs
[15] += env
->thumb
? 2 : 4;
11050 * Handle a CPU exception for A and R profile CPUs.
11051 * Do any appropriate logging, handle PSCI calls, and then hand off
11052 * to the AArch64-entry or AArch32-entry function depending on the
11053 * target exception level's register width.
11055 * Note: this is used for both TCG (as the do_interrupt tcg op),
11056 * and KVM to re-inject guest debug exceptions, and to
11057 * inject a Synchronous-External-Abort.
11059 void arm_cpu_do_interrupt(CPUState
*cs
)
11061 ARMCPU
*cpu
= ARM_CPU(cs
);
11062 CPUARMState
*env
= &cpu
->env
;
11063 unsigned int new_el
= env
->exception
.target_el
;
11065 assert(!arm_feature(env
, ARM_FEATURE_M
));
11067 arm_log_exception(cs
);
11068 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11070 if (qemu_loglevel_mask(CPU_LOG_INT
)
11071 && !excp_is_internal(cs
->exception_index
)) {
11072 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11073 syn_get_ec(env
->exception
.syndrome
),
11074 env
->exception
.syndrome
);
11077 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11078 arm_handle_psci_call(cpu
);
11079 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11084 * Semihosting semantics depend on the register width of the code
11085 * that caused the exception, not the target exception level, so
11086 * must be handled here.
11089 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11090 tcg_handle_semihosting(cs
);
11096 * Hooks may change global state so BQL should be held, also the
11097 * BQL needs to be held for any modification of
11098 * cs->interrupt_request.
11100 g_assert(qemu_mutex_iothread_locked());
11102 arm_call_pre_el_change_hook(cpu
);
11104 assert(!excp_is_internal(cs
->exception_index
));
11105 if (arm_el_is_aa64(env
, new_el
)) {
11106 arm_cpu_do_interrupt_aarch64(cs
);
11108 arm_cpu_do_interrupt_aarch32(cs
);
11111 arm_call_el_change_hook(cpu
);
11113 if (!kvm_enabled()) {
11114 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11117 #endif /* !CONFIG_USER_ONLY */
11119 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11121 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11123 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11124 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11126 return env
->cp15
.sctlr_el
[el
];
11129 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11131 if (regime_has_2_ranges(mmu_idx
)) {
11132 return extract64(tcr
, 37, 2);
11133 } else if (regime_is_stage2(mmu_idx
)) {
11134 return 0; /* VTCR_EL2 */
11136 /* Replicate the single TBI bit so we always have 2 bits. */
11137 return extract32(tcr
, 20, 1) * 3;
11141 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11143 if (regime_has_2_ranges(mmu_idx
)) {
11144 return extract64(tcr
, 51, 2);
11145 } else if (regime_is_stage2(mmu_idx
)) {
11146 return 0; /* VTCR_EL2 */
11148 /* Replicate the single TBID bit so we always have 2 bits. */
11149 return extract32(tcr
, 29, 1) * 3;
11153 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11155 if (regime_has_2_ranges(mmu_idx
)) {
11156 return extract64(tcr
, 57, 2);
11158 /* Replicate the single TCMA bit so we always have 2 bits. */
11159 return extract32(tcr
, 30, 1) * 3;
11163 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11173 return GranInvalid
;
11177 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11187 return GranInvalid
;
11191 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11193 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11194 : cpu_isar_feature(aa64_tgran4
, cpu
);
11197 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11199 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11200 : cpu_isar_feature(aa64_tgran16
, cpu
);
11203 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11205 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11206 : cpu_isar_feature(aa64_tgran64
, cpu
);
11209 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11214 if (have4k(cpu
, stage2
)) {
11219 if (have16k(cpu
, stage2
)) {
11224 if (have64k(cpu
, stage2
)) {
11232 * If the guest selects a granule size that isn't implemented,
11233 * the architecture requires that we behave as if it selected one
11234 * that is (with an IMPDEF choice of which one to pick). We choose
11235 * to implement the smallest supported granule size.
11237 if (have4k(cpu
, stage2
)) {
11240 if (have16k(cpu
, stage2
)) {
11243 assert(have64k(cpu
, stage2
));
11247 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11248 ARMMMUIdx mmu_idx
, bool data
)
11250 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11251 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11252 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11253 ARMGranuleSize gran
;
11254 ARMCPU
*cpu
= env_archcpu(env
);
11255 bool stage2
= regime_is_stage2(mmu_idx
);
11257 if (!regime_has_2_ranges(mmu_idx
)) {
11259 tsz
= extract32(tcr
, 0, 6);
11260 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11265 hpd
= extract32(tcr
, 24, 1);
11268 sh
= extract32(tcr
, 12, 2);
11269 ps
= extract32(tcr
, 16, 3);
11270 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11271 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11272 ds
= extract64(tcr
, 32, 1);
11277 * Bit 55 is always between the two regions, and is canonical for
11278 * determining if address tagging is enabled.
11280 select
= extract64(va
, 55, 1);
11282 tsz
= extract32(tcr
, 0, 6);
11283 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11284 epd
= extract32(tcr
, 7, 1);
11285 sh
= extract32(tcr
, 12, 2);
11286 hpd
= extract64(tcr
, 41, 1);
11287 e0pd
= extract64(tcr
, 55, 1);
11289 tsz
= extract32(tcr
, 16, 6);
11290 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11291 epd
= extract32(tcr
, 23, 1);
11292 sh
= extract32(tcr
, 28, 2);
11293 hpd
= extract64(tcr
, 42, 1);
11294 e0pd
= extract64(tcr
, 56, 1);
11296 ps
= extract64(tcr
, 32, 3);
11297 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11298 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11299 ds
= extract64(tcr
, 59, 1);
11301 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11302 regime_is_user(env
, mmu_idx
)) {
11307 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11309 if (cpu_isar_feature(aa64_st
, cpu
)) {
11310 max_tsz
= 48 - (gran
== Gran64K
);
11316 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11317 * adjust the effective value of DS, as documented.
11320 if (gran
== Gran64K
) {
11321 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11326 if (regime_is_stage2(mmu_idx
)) {
11327 if (gran
== Gran16K
) {
11328 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11330 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11333 if (gran
== Gran16K
) {
11334 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11336 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11344 if (tsz
> max_tsz
) {
11347 } else if (tsz
< min_tsz
) {
11354 /* Present TBI as a composite with TBID. */
11355 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11357 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11359 tbi
= (tbi
>> select
) & 1;
11361 return (ARMVAParameters
) {
11369 .tsz_oob
= tsz_oob
,
11378 * Note that signed overflow is undefined in C. The following routines are
11379 * careful to use unsigned types where modulo arithmetic is required.
11380 * Failure to do so _will_ break on newer gcc.
11383 /* Signed saturating arithmetic. */
11385 /* Perform 16-bit signed saturating addition. */
11386 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11391 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11401 /* Perform 8-bit signed saturating addition. */
11402 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11407 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11417 /* Perform 16-bit signed saturating subtraction. */
11418 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11423 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11433 /* Perform 8-bit signed saturating subtraction. */
11434 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11439 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11449 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11450 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11451 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11452 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11455 #include "op_addsub.h"
11457 /* Unsigned saturating arithmetic. */
11458 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11468 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11477 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11487 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11496 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11497 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11498 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11499 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11502 #include "op_addsub.h"
11504 /* Signed modulo arithmetic. */
11505 #define SARITH16(a, b, n, op) do { \
11507 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11508 RESULT(sum, n, 16); \
11510 ge |= 3 << (n * 2); \
11513 #define SARITH8(a, b, n, op) do { \
11515 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11516 RESULT(sum, n, 8); \
11522 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11523 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11524 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11525 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11529 #include "op_addsub.h"
11531 /* Unsigned modulo arithmetic. */
11532 #define ADD16(a, b, n) do { \
11534 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11535 RESULT(sum, n, 16); \
11536 if ((sum >> 16) == 1) \
11537 ge |= 3 << (n * 2); \
11540 #define ADD8(a, b, n) do { \
11542 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11543 RESULT(sum, n, 8); \
11544 if ((sum >> 8) == 1) \
11548 #define SUB16(a, b, n) do { \
11550 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11551 RESULT(sum, n, 16); \
11552 if ((sum >> 16) == 0) \
11553 ge |= 3 << (n * 2); \
11556 #define SUB8(a, b, n) do { \
11558 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11559 RESULT(sum, n, 8); \
11560 if ((sum >> 8) == 0) \
11567 #include "op_addsub.h"
11569 /* Halved signed arithmetic. */
11570 #define ADD16(a, b, n) \
11571 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11572 #define SUB16(a, b, n) \
11573 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11574 #define ADD8(a, b, n) \
11575 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11576 #define SUB8(a, b, n) \
11577 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11580 #include "op_addsub.h"
11582 /* Halved unsigned arithmetic. */
11583 #define ADD16(a, b, n) \
11584 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11585 #define SUB16(a, b, n) \
11586 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11587 #define ADD8(a, b, n) \
11588 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11589 #define SUB8(a, b, n) \
11590 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11593 #include "op_addsub.h"
11595 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11604 /* Unsigned sum of absolute byte differences. */
11605 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11608 sum
= do_usad(a
, b
);
11609 sum
+= do_usad(a
>> 8, b
>> 8);
11610 sum
+= do_usad(a
>> 16, b
>> 16);
11611 sum
+= do_usad(a
>> 24, b
>> 24);
11615 /* For ARMv6 SEL instruction. */
11616 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11631 mask
|= 0xff000000;
11633 return (a
& mask
) | (b
& ~mask
);
11638 * The upper bytes of val (above the number specified by 'bytes') must have
11639 * been zeroed out by the caller.
11641 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11645 stl_le_p(buf
, val
);
11647 /* zlib crc32 converts the accumulator and output to one's complement. */
11648 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11651 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11655 stl_le_p(buf
, val
);
11657 /* Linux crc32c converts the output to one's complement. */
11658 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11662 * Return the exception level to which FP-disabled exceptions should
11663 * be taken, or 0 if FP is enabled.
11665 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11667 #ifndef CONFIG_USER_ONLY
11671 * CPACR and the CPTR registers don't exist before v6, so FP is
11672 * always accessible
11674 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11678 if (arm_feature(env
, ARM_FEATURE_M
)) {
11679 /* CPACR can cause a NOCP UsageFault taken to current security state */
11680 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11684 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11685 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11686 /* FP insns cause a NOCP UsageFault taken to Secure */
11694 hcr_el2
= arm_hcr_el2_eff(env
);
11697 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11698 * 0, 2 : trap EL0 and EL1/PL1 accesses
11699 * 1 : trap only EL0 accesses
11700 * 3 : trap no accesses
11701 * This register is ignored if E2H+TGE are both set.
11703 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11704 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
11714 /* Trap from Secure PL0 or PL1 to Secure PL1. */
11715 if (!arm_el_is_aa64(env
, 3)
11716 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
11727 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11728 * to control non-secure access to the FPU. It doesn't have any
11729 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11731 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11732 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11733 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11734 /* FP insns act as UNDEF */
11735 return cur_el
== 2 ? 2 : 1;
11740 * CPTR_EL2 is present in v7VE or v8, and changes format
11741 * with HCR_EL2.E2H (regardless of TGE).
11744 if (hcr_el2
& HCR_E2H
) {
11745 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
11747 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
11755 } else if (arm_is_el2_enabled(env
)) {
11756 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
11762 /* CPTR_EL3 : present in v8 */
11763 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
11764 /* Trap all FP ops to EL3 */
11771 /* Return the exception level we're running at if this is our mmu_idx */
11772 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
11774 if (mmu_idx
& ARM_MMU_IDX_M
) {
11775 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
11779 case ARMMMUIdx_E10_0
:
11780 case ARMMMUIdx_E20_0
:
11782 case ARMMMUIdx_E10_1
:
11783 case ARMMMUIdx_E10_1_PAN
:
11786 case ARMMMUIdx_E20_2
:
11787 case ARMMMUIdx_E20_2_PAN
:
11792 g_assert_not_reached();
11797 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11799 g_assert_not_reached();
11803 static bool arm_pan_enabled(CPUARMState
*env
)
11806 return env
->pstate
& PSTATE_PAN
;
11808 return env
->uncached_cpsr
& CPSR_PAN
;
11812 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11817 if (arm_feature(env
, ARM_FEATURE_M
)) {
11818 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11821 /* See ARM pseudo-function ELIsInHost. */
11824 hcr
= arm_hcr_el2_eff(env
);
11825 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
11826 idx
= ARMMMUIdx_E20_0
;
11828 idx
= ARMMMUIdx_E10_0
;
11832 if (arm_pan_enabled(env
)) {
11833 idx
= ARMMMUIdx_E10_1_PAN
;
11835 idx
= ARMMMUIdx_E10_1
;
11839 /* Note that TGE does not apply at EL2. */
11840 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
11841 if (arm_pan_enabled(env
)) {
11842 idx
= ARMMMUIdx_E20_2_PAN
;
11844 idx
= ARMMMUIdx_E20_2
;
11847 idx
= ARMMMUIdx_E2
;
11851 return ARMMMUIdx_E3
;
11853 g_assert_not_reached();
11859 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11861 return arm_mmu_idx_el(env
, arm_current_el(env
));
11864 static inline bool fgt_svc(CPUARMState
*env
, int el
)
11867 * Assuming fine-grained-traps are active, return true if we
11868 * should be trapping on SVC instructions. Only AArch64 can
11869 * trap on an SVC at EL1, but we don't need to special-case this
11870 * because if this is AArch32 EL1 then arm_fgt_active() is false.
11871 * We also know el is 0 or 1.
11874 FIELD_EX64(env
->cp15
.fgt_exec
[FGTREG_HFGITR
], HFGITR_EL2
, SVC_EL0
) :
11875 FIELD_EX64(env
->cp15
.fgt_exec
[FGTREG_HFGITR
], HFGITR_EL2
, SVC_EL1
);
11878 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11880 CPUARMTBFlags flags
)
11882 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
11883 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
11885 if (arm_singlestep_active(env
)) {
11886 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
11892 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11894 CPUARMTBFlags flags
)
11896 bool sctlr_b
= arm_sctlr_b(env
);
11899 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
11901 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11902 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11904 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
11906 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11909 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11912 CPUARMTBFlags flags
= {};
11913 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
11915 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
11916 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
11917 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11920 if (arm_v7m_is_handler_mode(env
)) {
11921 DP_TBFLAG_M32(flags
, HANDLER
, 1);
11925 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11926 * is suppressing them because the requested execution priority
11929 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11930 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11931 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11932 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
11935 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && env
->v7m
.secure
) {
11936 DP_TBFLAG_M32(flags
, SECURE
, 1);
11939 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11942 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11945 CPUARMTBFlags flags
= {};
11946 int el
= arm_current_el(env
);
11948 if (arm_sctlr(env
, el
) & SCTLR_A
) {
11949 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11952 if (arm_el_is_aa64(env
, 1)) {
11953 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11956 if (el
< 2 && env
->cp15
.hstr_el2
&& arm_is_el2_enabled(env
) &&
11957 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11958 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
11961 if (arm_fgt_active(env
, el
)) {
11962 DP_TBFLAG_ANY(flags
, FGT_ACTIVE
, 1);
11963 if (fgt_svc(env
, el
)) {
11964 DP_TBFLAG_ANY(flags
, FGT_SVC
, 1);
11968 if (env
->uncached_cpsr
& CPSR_IL
) {
11969 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11973 * The SME exception we are testing for is raised via
11974 * AArch64.CheckFPAdvSIMDEnabled(), as called from
11975 * AArch32.CheckAdvSIMDOrFPEnabled().
11978 && FIELD_EX64(env
->svcr
, SVCR
, SM
)
11979 && (!arm_is_el2_enabled(env
)
11980 || (arm_el_is_aa64(env
, 2) && !(env
->cp15
.hcr_el2
& HCR_TGE
)))
11981 && arm_el_is_aa64(env
, 1)
11982 && !sme_fa64(env
, el
)) {
11983 DP_TBFLAG_A32(flags
, SME_TRAP_NONSTREAMING
, 1);
11986 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11989 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11992 CPUARMTBFlags flags
= {};
11993 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11994 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11998 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
12000 /* Get control bits for tagged addresses. */
12001 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12002 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12004 DP_TBFLAG_A64(flags
, TBII
, tbii
);
12005 DP_TBFLAG_A64(flags
, TBID
, tbid
);
12007 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
12008 int sve_el
= sve_exception_el(env
, el
);
12011 * If either FP or SVE are disabled, translator does not need len.
12012 * If SVE EL > FP EL, FP exception has precedence, and translator
12013 * does not need SVE EL. Save potential re-translations by forcing
12014 * the unneeded data to zero.
12017 if (sve_el
> fp_el
) {
12020 } else if (sve_el
== 0) {
12021 DP_TBFLAG_A64(flags
, VL
, sve_vqm1_for_el(env
, el
));
12023 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
12025 if (cpu_isar_feature(aa64_sme
, env_archcpu(env
))) {
12026 int sme_el
= sme_exception_el(env
, el
);
12027 bool sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12029 DP_TBFLAG_A64(flags
, SMEEXC_EL
, sme_el
);
12031 /* Similarly, do not compute SVL if SME is disabled. */
12032 int svl
= sve_vqm1_for_el_sm(env
, el
, true);
12033 DP_TBFLAG_A64(flags
, SVL
, svl
);
12035 /* If SVE is disabled, we will not have set VL above. */
12036 DP_TBFLAG_A64(flags
, VL
, svl
);
12040 DP_TBFLAG_A64(flags
, PSTATE_SM
, 1);
12041 DP_TBFLAG_A64(flags
, SME_TRAP_NONSTREAMING
, !sme_fa64(env
, el
));
12043 DP_TBFLAG_A64(flags
, PSTATE_ZA
, FIELD_EX64(env
->svcr
, SVCR
, ZA
));
12046 sctlr
= regime_sctlr(env
, stage1
);
12048 if (sctlr
& SCTLR_A
) {
12049 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
12052 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
12053 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
12056 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
12058 * In order to save space in flags, we record only whether
12059 * pauth is "inactive", meaning all insns are implemented as
12060 * a nop, or "active" when some action must be performed.
12061 * The decision of which action to take is left to a helper.
12063 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
12064 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
12068 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12069 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12070 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
12071 DP_TBFLAG_A64(flags
, BT
, 1);
12075 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12076 if (!(env
->pstate
& PSTATE_UAO
)) {
12078 case ARMMMUIdx_E10_1
:
12079 case ARMMMUIdx_E10_1_PAN
:
12080 /* TODO: ARMv8.3-NV */
12081 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
12083 case ARMMMUIdx_E20_2
:
12084 case ARMMMUIdx_E20_2_PAN
:
12086 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12087 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12089 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
12090 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
12098 if (env
->pstate
& PSTATE_IL
) {
12099 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
12102 if (arm_fgt_active(env
, el
)) {
12103 DP_TBFLAG_ANY(flags
, FGT_ACTIVE
, 1);
12104 if (FIELD_EX64(env
->cp15
.fgt_exec
[FGTREG_HFGITR
], HFGITR_EL2
, ERET
)) {
12105 DP_TBFLAG_A64(flags
, FGT_ERET
, 1);
12107 if (fgt_svc(env
, el
)) {
12108 DP_TBFLAG_ANY(flags
, FGT_SVC
, 1);
12112 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
12114 * Set MTE_ACTIVE if any access may be Checked, and leave clear
12115 * if all accesses must be Unchecked:
12116 * 1) If no TBI, then there are no tags in the address to check,
12117 * 2) If Tag Check Override, then all accesses are Unchecked,
12118 * 3) If Tag Check Fail == 0, then Checked access have no effect,
12119 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
12121 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
12122 DP_TBFLAG_A64(flags
, ATA
, 1);
12124 && !(env
->pstate
& PSTATE_TCO
)
12125 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
12126 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
12129 /* And again for unprivileged accesses, if required. */
12130 if (EX_TBFLAG_A64(flags
, UNPRIV
)
12132 && !(env
->pstate
& PSTATE_TCO
)
12133 && (sctlr
& SCTLR_TCF0
)
12134 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
12135 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
12137 /* Cache TCMA as well as TBI. */
12138 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
12141 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12144 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
12146 int el
= arm_current_el(env
);
12147 int fp_el
= fp_exception_el(env
, el
);
12148 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12151 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12152 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
12153 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12155 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12159 void arm_rebuild_hflags(CPUARMState
*env
)
12161 env
->hflags
= rebuild_hflags_internal(env
);
12165 * If we have triggered a EL state change we can't rely on the
12166 * translator having passed it to us, we need to recompute.
12168 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
12170 int el
= arm_current_el(env
);
12171 int fp_el
= fp_exception_el(env
, el
);
12172 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12174 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12177 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
12179 int fp_el
= fp_exception_el(env
, el
);
12180 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12182 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12186 * If we have triggered a EL state change we can't rely on the
12187 * translator having passed it to us, we need to recompute.
12189 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
12191 int el
= arm_current_el(env
);
12192 int fp_el
= fp_exception_el(env
, el
);
12193 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12194 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12197 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
12199 int fp_el
= fp_exception_el(env
, el
);
12200 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12202 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12205 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
12207 int fp_el
= fp_exception_el(env
, el
);
12208 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12210 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12213 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
12215 #ifdef CONFIG_DEBUG_TCG
12216 CPUARMTBFlags c
= env
->hflags
;
12217 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
12219 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
12220 fprintf(stderr
, "TCG hflags mismatch "
12221 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
12222 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
12223 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
12229 static bool mve_no_pred(CPUARMState
*env
)
12232 * Return true if there is definitely no predication of MVE
12233 * instructions by VPR or LTPSIZE. (Returning false even if there
12234 * isn't any predication is OK; generated code will just be
12236 * If the CPU does not implement MVE then this TB flag is always 0.
12238 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12239 * logic in gen_update_fp_context() needs to be updated to match.
12241 * We do not include the effect of the ECI bits here -- they are
12242 * tracked in other TB flags. This simplifies the logic for
12243 * "when did we emit code that changes the MVE_NO_PRED TB flag
12244 * and thus need to end the TB?".
12246 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12249 if (env
->v7m
.vpr
) {
12252 if (env
->v7m
.ltpsize
< 4) {
12258 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12259 target_ulong
*cs_base
, uint32_t *pflags
)
12261 CPUARMTBFlags flags
;
12263 assert_hflags_rebuild_correctly(env
);
12264 flags
= env
->hflags
;
12266 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12268 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12269 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12272 *pc
= env
->regs
[15];
12274 if (arm_feature(env
, ARM_FEATURE_M
)) {
12275 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12276 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12277 != env
->v7m
.secure
) {
12278 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12281 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12282 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12283 (env
->v7m
.secure
&&
12284 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12286 * ASPEN is set, but FPCA/SFPA indicate that there is no
12287 * active FP context; we must create a new FP context before
12288 * executing any FP insn.
12290 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12293 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12294 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12295 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12298 if (mve_no_pred(env
)) {
12299 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12303 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12304 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12306 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12307 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12309 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12310 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12312 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12313 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12317 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12318 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12322 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12323 * states defined in the ARM ARM for software singlestep:
12324 * SS_ACTIVE PSTATE.SS State
12325 * 0 x Inactive (the TB flag for SS is always 0)
12326 * 1 0 Active-pending
12327 * 1 1 Active-not-pending
12328 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12330 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12331 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12334 *pflags
= flags
.flags
;
12335 *cs_base
= flags
.flags2
;
12338 #ifdef TARGET_AARCH64
12340 * The manual says that when SVE is enabled and VQ is widened the
12341 * implementation is allowed to zero the previously inaccessible
12342 * portion of the registers. The corollary to that is that when
12343 * SVE is enabled and VQ is narrowed we are also allowed to zero
12344 * the now inaccessible portion of the registers.
12346 * The intent of this is that no predicate bit beyond VQ is ever set.
12347 * Which means that some operations on predicate registers themselves
12348 * may operate on full uint64_t or even unrolled across the maximum
12349 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12350 * may well be cheaper than conditionals to restrict the operation
12351 * to the relevant portion of a uint16_t[16].
12353 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12358 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12359 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12361 /* Zap the high bits of the zregs. */
12362 for (i
= 0; i
< 32; i
++) {
12363 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12366 /* Zap the high bits of the pregs and ffr. */
12369 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12371 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12372 for (i
= 0; i
< 17; ++i
) {
12373 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12379 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12384 exc_el
= sme_exception_el(env
, el
);
12386 exc_el
= sve_exception_el(env
, el
);
12389 return 0; /* disabled */
12391 return sve_vqm1_for_el_sm(env
, el
, sm
);
12395 * Notice a change in SVE vector size when changing EL.
12397 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12398 int new_el
, bool el0_a64
)
12400 ARMCPU
*cpu
= env_archcpu(env
);
12401 int old_len
, new_len
;
12402 bool old_a64
, new_a64
, sm
;
12404 /* Nothing to do if no SVE. */
12405 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12409 /* Nothing to do if FP is disabled in either EL. */
12410 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12414 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12415 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12418 * Both AArch64.TakeException and AArch64.ExceptionReturn
12419 * invoke ResetSVEState when taking an exception from, or
12420 * returning to, AArch32 state when PSTATE.SM is enabled.
12422 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12423 if (old_a64
!= new_a64
&& sm
) {
12424 arm_reset_sve_state(env
);
12429 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12430 * at ELx, or not available because the EL is in AArch32 state, then
12431 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12432 * has an effective value of 0".
12434 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12435 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12436 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12437 * we already have the correct register contents when encountering the
12438 * vq0->vq0 transition between EL0->EL1.
12440 old_len
= new_len
= 0;
12442 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12445 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12448 /* When changing vector length, clear inaccessible state. */
12449 if (new_len
< old_len
) {
12450 aarch64_sve_narrow_vq(env
, new_len
+ 1);