1 #include "qemu/osdep.h"
5 #include "exec/gdbstub.h"
6 #include "exec/helper-proto.h"
7 #include "qemu/host-utils.h"
8 #include "sysemu/arch_init.h"
9 #include "sysemu/sysemu.h"
10 #include "qemu/bitops.h"
11 #include "qemu/crc32c.h"
12 #include "exec/exec-all.h"
13 #include "exec/cpu_ldst.h"
15 #include <zlib.h> /* For crc32 */
16 #include "exec/semihost.h"
17 #include "sysemu/kvm.h"
19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
21 #ifndef CONFIG_USER_ONLY
22 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
23 int access_type
, ARMMMUIdx mmu_idx
,
24 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
25 target_ulong
*page_size
, uint32_t *fsr
,
28 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
29 int access_type
, ARMMMUIdx mmu_idx
,
30 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
31 target_ulong
*page_size_ptr
, uint32_t *fsr
,
34 /* Definitions for the PMCCNTR and PMCR registers */
40 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
44 /* VFP data registers are always little-endian. */
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
51 /* Aliases for Q regs. */
54 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
55 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
59 switch (reg
- nregs
) {
60 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
61 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
62 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
67 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
71 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
73 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
76 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
79 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
80 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
84 switch (reg
- nregs
) {
85 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
86 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
87 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
92 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
96 /* 128 bit FP register */
97 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
98 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
102 stl_p(buf
, vfp_get_fpsr(env
));
106 stl_p(buf
, vfp_get_fpcr(env
));
113 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
117 /* 128 bit FP register */
118 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
119 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
123 vfp_set_fpsr(env
, ldl_p(buf
));
127 vfp_set_fpcr(env
, ldl_p(buf
));
134 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
136 assert(ri
->fieldoffset
);
137 if (cpreg_field_is_64bit(ri
)) {
138 return CPREG_FIELD64(env
, ri
);
140 return CPREG_FIELD32(env
, ri
);
144 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
147 assert(ri
->fieldoffset
);
148 if (cpreg_field_is_64bit(ri
)) {
149 CPREG_FIELD64(env
, ri
) = value
;
151 CPREG_FIELD32(env
, ri
) = value
;
155 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
157 return (char *)env
+ ri
->fieldoffset
;
160 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
162 /* Raw read of a coprocessor register (as needed for migration, etc). */
163 if (ri
->type
& ARM_CP_CONST
) {
164 return ri
->resetvalue
;
165 } else if (ri
->raw_readfn
) {
166 return ri
->raw_readfn(env
, ri
);
167 } else if (ri
->readfn
) {
168 return ri
->readfn(env
, ri
);
170 return raw_read(env
, ri
);
174 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
177 /* Raw write of a coprocessor register (as needed for migration, etc).
178 * Note that constant registers are treated as write-ignored; the
179 * caller should check for success by whether a readback gives the
182 if (ri
->type
& ARM_CP_CONST
) {
184 } else if (ri
->raw_writefn
) {
185 ri
->raw_writefn(env
, ri
, v
);
186 } else if (ri
->writefn
) {
187 ri
->writefn(env
, ri
, v
);
189 raw_write(env
, ri
, v
);
193 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
195 /* Return true if the regdef would cause an assertion if you called
196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
197 * program bug for it not to have the NO_RAW flag).
198 * NB that returning false here doesn't necessarily mean that calling
199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
200 * read/write access functions which are safe for raw use" from "has
201 * read/write access functions which have side effects but has forgotten
202 * to provide raw access functions".
203 * The tests here line up with the conditions in read/write_raw_cp_reg()
204 * and assertions in raw_read()/raw_write().
206 if ((ri
->type
& ARM_CP_CONST
) ||
208 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
214 bool write_cpustate_to_list(ARMCPU
*cpu
)
216 /* Write the coprocessor state from cpu->env to the (index,value) list. */
220 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
221 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
222 const ARMCPRegInfo
*ri
;
224 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
229 if (ri
->type
& ARM_CP_NO_RAW
) {
232 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
237 bool write_list_to_cpustate(ARMCPU
*cpu
)
242 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
243 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
244 uint64_t v
= cpu
->cpreg_values
[i
];
245 const ARMCPRegInfo
*ri
;
247 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
252 if (ri
->type
& ARM_CP_NO_RAW
) {
255 /* Write value and confirm it reads back as written
256 * (to catch read-only registers and partially read-only
257 * registers where the incoming migration value doesn't match)
259 write_raw_cp_reg(&cpu
->env
, ri
, v
);
260 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
267 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
269 ARMCPU
*cpu
= opaque
;
271 const ARMCPRegInfo
*ri
;
273 regidx
= *(uint32_t *)key
;
274 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
276 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
277 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
278 /* The value array need not be initialized at this point */
279 cpu
->cpreg_array_len
++;
283 static void count_cpreg(gpointer key
, gpointer opaque
)
285 ARMCPU
*cpu
= opaque
;
287 const ARMCPRegInfo
*ri
;
289 regidx
= *(uint32_t *)key
;
290 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
292 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
293 cpu
->cpreg_array_len
++;
297 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
299 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
300 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
311 void init_cpreg_list(ARMCPU
*cpu
)
313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
314 * Note that we require cpreg_tuples[] to be sorted by key ID.
319 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
320 keys
= g_list_sort(keys
, cpreg_key_compare
);
322 cpu
->cpreg_array_len
= 0;
324 g_list_foreach(keys
, count_cpreg
, cpu
);
326 arraylen
= cpu
->cpreg_array_len
;
327 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
328 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
329 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
330 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
331 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
332 cpu
->cpreg_array_len
= 0;
334 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
336 assert(cpu
->cpreg_array_len
== arraylen
);
342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
345 * access_el3_aa32ns: Used to check AArch32 register views.
346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
348 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
349 const ARMCPRegInfo
*ri
,
352 bool secure
= arm_is_secure_below_el3(env
);
354 assert(!arm_el_is_aa64(env
, 3));
356 return CP_ACCESS_TRAP_UNCATEGORIZED
;
361 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
362 const ARMCPRegInfo
*ri
,
365 if (!arm_el_is_aa64(env
, 3)) {
366 return access_el3_aa32ns(env
, ri
, isread
);
371 /* Some secure-only AArch32 registers trap to EL3 if used from
372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
374 * We assume that the .access field is set to PL1_RW.
376 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
377 const ARMCPRegInfo
*ri
,
380 if (arm_current_el(env
) == 3) {
383 if (arm_is_secure_below_el3(env
)) {
384 return CP_ACCESS_TRAP_EL3
;
386 /* This will be EL1 NS and EL2 NS, which just UNDEF */
387 return CP_ACCESS_TRAP_UNCATEGORIZED
;
390 /* Check for traps to "powerdown debug" registers, which are controlled
393 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
396 int el
= arm_current_el(env
);
398 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDOSA
)
399 && !arm_is_secure_below_el3(env
)) {
400 return CP_ACCESS_TRAP_EL2
;
402 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
403 return CP_ACCESS_TRAP_EL3
;
408 /* Check for traps to "debug ROM" registers, which are controlled
409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
411 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 int el
= arm_current_el(env
);
416 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDRA
)
417 && !arm_is_secure_below_el3(env
)) {
418 return CP_ACCESS_TRAP_EL2
;
420 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
421 return CP_ACCESS_TRAP_EL3
;
426 /* Check for traps to general debug registers, which are controlled
427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
429 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
432 int el
= arm_current_el(env
);
434 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDA
)
435 && !arm_is_secure_below_el3(env
)) {
436 return CP_ACCESS_TRAP_EL2
;
438 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
439 return CP_ACCESS_TRAP_EL3
;
444 /* Check for traps to performance monitor registers, which are controlled
445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
447 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
450 int el
= arm_current_el(env
);
452 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
453 && !arm_is_secure_below_el3(env
)) {
454 return CP_ACCESS_TRAP_EL2
;
456 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
457 return CP_ACCESS_TRAP_EL3
;
462 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
464 ARMCPU
*cpu
= arm_env_get_cpu(env
);
466 raw_write(env
, ri
, value
);
467 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
470 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
472 ARMCPU
*cpu
= arm_env_get_cpu(env
);
474 if (raw_read(env
, ri
) != value
) {
475 /* Unlike real hardware the qemu TLB uses virtual addresses,
476 * not modified virtual addresses, so this causes a TLB flush.
479 raw_write(env
, ri
, value
);
483 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
486 ARMCPU
*cpu
= arm_env_get_cpu(env
);
488 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
489 && !extended_addresses_enabled(env
)) {
490 /* For VMSA (when not using the LPAE long descriptor page table
491 * format) this register includes the ASID, so do a TLB flush.
492 * For PMSA it is purely a process ID and no action is needed.
496 raw_write(env
, ri
, value
);
499 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate all (TLBIALL) */
503 ARMCPU
*cpu
= arm_env_get_cpu(env
);
508 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
512 ARMCPU
*cpu
= arm_env_get_cpu(env
);
514 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
517 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
520 /* Invalidate by ASID (TLBIASID) */
521 ARMCPU
*cpu
= arm_env_get_cpu(env
);
526 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530 ARMCPU
*cpu
= arm_env_get_cpu(env
);
532 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
535 /* IS variants of TLB operations must affect all cores */
536 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 CPU_FOREACH(other_cs
) {
546 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
551 CPU_FOREACH(other_cs
) {
556 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
561 CPU_FOREACH(other_cs
) {
562 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
566 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
571 CPU_FOREACH(other_cs
) {
572 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
576 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
579 CPUState
*cs
= ENV_GET_CPU(env
);
581 tlb_flush_by_mmuidx(cs
,
582 (1 << ARMMMUIdx_S12NSE1
) |
583 (1 << ARMMMUIdx_S12NSE0
) |
584 (1 << ARMMMUIdx_S2NS
));
587 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
592 CPU_FOREACH(other_cs
) {
593 tlb_flush_by_mmuidx(other_cs
,
594 (1 << ARMMMUIdx_S12NSE1
) |
595 (1 << ARMMMUIdx_S12NSE0
) |
596 (1 << ARMMMUIdx_S2NS
));
600 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
603 /* Invalidate by IPA. This has to invalidate any structures that
604 * contain only stage 2 translation information, but does not need
605 * to apply to structures that contain combined stage 1 and stage 2
606 * translation information.
607 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
609 CPUState
*cs
= ENV_GET_CPU(env
);
612 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
616 pageaddr
= sextract64(value
<< 12, 0, 40);
618 tlb_flush_page_by_mmuidx(cs
, pageaddr
, (1 << ARMMMUIdx_S2NS
));
621 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
627 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
631 pageaddr
= sextract64(value
<< 12, 0, 40);
633 CPU_FOREACH(other_cs
) {
634 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, (1 << ARMMMUIdx_S2NS
));
638 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
641 CPUState
*cs
= ENV_GET_CPU(env
);
643 tlb_flush_by_mmuidx(cs
, (1 << ARMMMUIdx_S1E2
));
646 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
651 CPU_FOREACH(other_cs
) {
652 tlb_flush_by_mmuidx(other_cs
, (1 << ARMMMUIdx_S1E2
));
656 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
659 CPUState
*cs
= ENV_GET_CPU(env
);
660 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
662 tlb_flush_page_by_mmuidx(cs
, pageaddr
, (1 << ARMMMUIdx_S1E2
));
665 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
669 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
671 CPU_FOREACH(other_cs
) {
672 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, (1 << ARMMMUIdx_S1E2
));
676 static const ARMCPRegInfo cp_reginfo
[] = {
677 /* Define the secure and non-secure FCSE identifier CP registers
678 * separately because there is no secure bank in V8 (no _EL3). This allows
679 * the secure register to be properly reset and migrated. There is also no
680 * v8 EL1 version of the register so the non-secure instance stands alone.
682 { .name
= "FCSEIDR(NS)",
683 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
684 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
685 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
686 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
687 { .name
= "FCSEIDR(S)",
688 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
689 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
690 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
691 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
692 /* Define the secure and non-secure context identifier CP registers
693 * separately because there is no secure bank in V8 (no _EL3). This allows
694 * the secure register to be properly reset and migrated. In the
695 * non-secure case, the 32-bit register will have reset and migration
696 * disabled during registration as it is handled by the 64-bit instance.
698 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
699 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
700 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
701 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
702 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
703 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
704 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
705 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
706 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
707 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
711 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
712 /* NB: Some of these registers exist in v8 but with more precise
713 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
715 /* MMU Domain access control / MPU write buffer control */
717 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
718 .access
= PL1_RW
, .resetvalue
= 0,
719 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
720 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
721 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
722 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
723 * For v6 and v5, these mappings are overly broad.
725 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
726 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
727 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
728 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
729 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
730 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
731 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
732 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
733 /* Cache maintenance ops; some of this space may be overridden later. */
734 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
735 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
736 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
740 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
741 /* Not all pre-v6 cores implemented this WFI, so this is slightly
744 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
745 .access
= PL1_W
, .type
= ARM_CP_WFI
},
749 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
750 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
751 * is UNPREDICTABLE; we choose to NOP as most implementations do).
753 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
754 .access
= PL1_W
, .type
= ARM_CP_WFI
},
755 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
756 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
757 * OMAPCP will override this space.
759 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
760 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
762 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
763 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
765 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
766 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
767 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
769 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
770 * implementing it as RAZ means the "debug architecture version" bits
771 * will read as a reserved value, which should cause Linux to not try
772 * to use the debug hardware.
774 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
775 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
776 /* MMU TLB control. Note that the wildcarding means we cover not just
777 * the unified TLB ops but also the dside/iside/inner-shareable variants.
779 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
780 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
781 .type
= ARM_CP_NO_RAW
},
782 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
783 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
784 .type
= ARM_CP_NO_RAW
},
785 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
786 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
787 .type
= ARM_CP_NO_RAW
},
788 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
789 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
790 .type
= ARM_CP_NO_RAW
},
791 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
792 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
793 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
794 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
798 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
803 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
804 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
805 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
806 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
807 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
809 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
810 /* VFP coprocessor: cp10 & cp11 [23:20] */
811 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
813 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
814 /* ASEDIS [31] bit is RAO/WI */
818 /* VFPv3 and upwards with NEON implement 32 double precision
819 * registers (D0-D31).
821 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
822 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
823 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
829 env
->cp15
.cpacr_el1
= value
;
832 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 if (arm_feature(env
, ARM_FEATURE_V8
)) {
836 /* Check if CPACR accesses are to be trapped to EL2 */
837 if (arm_current_el(env
) == 1 &&
838 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
839 return CP_ACCESS_TRAP_EL2
;
840 /* Check if CPACR accesses are to be trapped to EL3 */
841 } else if (arm_current_el(env
) < 3 &&
842 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
843 return CP_ACCESS_TRAP_EL3
;
850 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
853 /* Check if CPTR accesses are set to trap to EL3 */
854 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
855 return CP_ACCESS_TRAP_EL3
;
861 static const ARMCPRegInfo v6_cp_reginfo
[] = {
862 /* prefetch by MVA in v6, NOP in v7 */
863 { .name
= "MVA_prefetch",
864 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
865 .access
= PL1_W
, .type
= ARM_CP_NOP
},
866 /* We need to break the TB after ISB to execute self-modifying code
867 * correctly and also to take any pending interrupts immediately.
868 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
870 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
871 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
872 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
873 .access
= PL0_W
, .type
= ARM_CP_NOP
},
874 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
875 .access
= PL0_W
, .type
= ARM_CP_NOP
},
876 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
878 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
879 offsetof(CPUARMState
, cp15
.ifar_ns
) },
881 /* Watchpoint Fault Address Register : should actually only be present
882 * for 1136, 1176, 11MPCore.
884 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
885 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
886 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
887 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
888 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
889 .resetvalue
= 0, .writefn
= cpacr_write
},
893 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
896 /* Performance monitor registers user accessibility is controlled
897 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
898 * trapping to EL2 or EL3 for other accesses.
900 int el
= arm_current_el(env
);
902 if (el
== 0 && !env
->cp15
.c9_pmuserenr
) {
903 return CP_ACCESS_TRAP
;
905 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
906 && !arm_is_secure_below_el3(env
)) {
907 return CP_ACCESS_TRAP_EL2
;
909 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
910 return CP_ACCESS_TRAP_EL3
;
916 #ifndef CONFIG_USER_ONLY
918 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
920 /* This does not support checking PMCCFILTR_EL0 register */
922 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
929 void pmccntr_sync(CPUARMState
*env
)
933 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
934 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
936 if (env
->cp15
.c9_pmcr
& PMCRD
) {
937 /* Increment once every 64 processor clock cycles */
941 if (arm_ccnt_enabled(env
)) {
942 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
946 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
952 /* The counter has been reset */
953 env
->cp15
.c15_ccnt
= 0;
956 /* only the DP, X, D and E bits are writable */
957 env
->cp15
.c9_pmcr
&= ~0x39;
958 env
->cp15
.c9_pmcr
|= (value
& 0x39);
963 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
965 uint64_t total_ticks
;
967 if (!arm_ccnt_enabled(env
)) {
968 /* Counter is disabled, do not change value */
969 return env
->cp15
.c15_ccnt
;
972 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
973 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
975 if (env
->cp15
.c9_pmcr
& PMCRD
) {
976 /* Increment once every 64 processor clock cycles */
979 return total_ticks
- env
->cp15
.c15_ccnt
;
982 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
985 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
986 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
987 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
990 env
->cp15
.c9_pmselr
= value
& 0x1f;
993 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
996 uint64_t total_ticks
;
998 if (!arm_ccnt_enabled(env
)) {
999 /* Counter is disabled, set the absolute value */
1000 env
->cp15
.c15_ccnt
= value
;
1004 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1005 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1007 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1008 /* Increment once every 64 processor clock cycles */
1011 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1014 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1017 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1019 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1022 #else /* CONFIG_USER_ONLY */
1024 void pmccntr_sync(CPUARMState
*env
)
1030 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1034 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
1038 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1042 env
->cp15
.c9_pmcnten
|= value
;
1045 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1049 env
->cp15
.c9_pmcnten
&= ~value
;
1052 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1055 env
->cp15
.c9_pmovsr
&= ~value
;
1058 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1061 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1062 * PMSELR value is equal to or greater than the number of implemented
1063 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1065 if (env
->cp15
.c9_pmselr
== 0x1f) {
1066 pmccfiltr_write(env
, ri
, value
);
1070 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1072 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1073 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1075 if (env
->cp15
.c9_pmselr
== 0x1f) {
1076 return env
->cp15
.pmccfiltr_el0
;
1082 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1085 env
->cp15
.c9_pmuserenr
= value
& 1;
1088 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1091 /* We have no event counters so only the C bit can be changed */
1093 env
->cp15
.c9_pminten
|= value
;
1096 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1100 env
->cp15
.c9_pminten
&= ~value
;
1103 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1106 /* Note that even though the AArch64 view of this register has bits
1107 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1108 * architectural requirements for bits which are RES0 only in some
1109 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1110 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1112 raw_write(env
, ri
, value
& ~0x1FULL
);
1115 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1117 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1118 * For bits that vary between AArch32/64, code needs to check the
1119 * current execution mode before directly using the feature bit.
1121 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1123 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1124 valid_mask
&= ~SCR_HCE
;
1126 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1127 * supported if EL2 exists. The bit is UNK/SBZP when
1128 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1129 * when EL2 is unavailable.
1130 * On ARMv8, this bit is always available.
1132 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1133 !arm_feature(env
, ARM_FEATURE_V8
)) {
1134 valid_mask
&= ~SCR_SMD
;
1138 /* Clear all-context RES0 bits. */
1139 value
&= valid_mask
;
1140 raw_write(env
, ri
, value
);
1143 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1145 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1147 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1150 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1151 ri
->secure
& ARM_CP_SECSTATE_S
);
1153 return cpu
->ccsidr
[index
];
1156 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1159 raw_write(env
, ri
, value
& 0xf);
1162 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1164 CPUState
*cs
= ENV_GET_CPU(env
);
1167 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1170 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1173 /* External aborts are not possible in QEMU so A bit is always clear */
1177 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1178 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1179 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1180 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1181 /* Performance monitors are implementation defined in v7,
1182 * but with an ARM recommended set of registers, which we
1183 * follow (although we don't actually implement any counters)
1185 * Performance registers fall into three categories:
1186 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1187 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1188 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1189 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1190 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1192 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1193 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1194 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1195 .writefn
= pmcntenset_write
,
1196 .accessfn
= pmreg_access
,
1197 .raw_writefn
= raw_write
},
1198 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1199 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1200 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1201 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1202 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1203 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1205 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1206 .accessfn
= pmreg_access
,
1207 .writefn
= pmcntenclr_write
,
1208 .type
= ARM_CP_ALIAS
},
1209 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1210 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1211 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1212 .type
= ARM_CP_ALIAS
,
1213 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1214 .writefn
= pmcntenclr_write
},
1215 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1216 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1217 .accessfn
= pmreg_access
,
1218 .writefn
= pmovsr_write
,
1219 .raw_writefn
= raw_write
},
1220 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1221 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1222 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1223 .type
= ARM_CP_ALIAS
,
1224 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1225 .writefn
= pmovsr_write
,
1226 .raw_writefn
= raw_write
},
1227 /* Unimplemented so WI. */
1228 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1229 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
1230 #ifndef CONFIG_USER_ONLY
1231 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1232 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1233 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1234 .accessfn
= pmreg_access
, .writefn
= pmselr_write
,
1235 .raw_writefn
= raw_write
},
1236 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1237 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1238 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1239 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1240 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1241 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1242 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
1243 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1244 .accessfn
= pmreg_access
},
1245 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1246 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1247 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1249 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1251 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1252 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1253 .writefn
= pmccfiltr_write
,
1254 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1256 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1258 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1259 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1260 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1261 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1262 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1263 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1264 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1265 /* Unimplemented, RAZ/WI. */
1266 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1267 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1268 .accessfn
= pmreg_access
},
1269 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1270 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1271 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1273 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1274 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1275 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1276 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1279 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1280 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1281 .access
= PL1_RW
, .accessfn
= access_tpm
,
1282 .type
= ARM_CP_ALIAS
,
1283 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1285 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1286 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1287 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1288 .access
= PL1_RW
, .accessfn
= access_tpm
,
1290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1291 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1292 .resetvalue
= 0x0 },
1293 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1294 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1295 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1296 .writefn
= pmintenclr_write
, },
1297 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1298 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1299 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1300 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1301 .writefn
= pmintenclr_write
},
1302 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1303 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1304 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1305 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1306 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1307 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1308 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1309 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1310 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1311 * just RAZ for all cores:
1313 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1314 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1315 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1316 /* Auxiliary fault status registers: these also are IMPDEF, and we
1317 * choose to RAZ/WI for all cores.
1319 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1320 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1321 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1322 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1323 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1324 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1325 /* MAIR can just read-as-written because we don't implement caches
1326 * and so don't need to care about memory attributes.
1328 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1329 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1330 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1332 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1333 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1334 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1336 /* For non-long-descriptor page tables these are PRRR and NMRR;
1337 * regardless they still act as reads-as-written for QEMU.
1339 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1340 * allows them to assign the correct fieldoffset based on the endianness
1341 * handled in the field definitions.
1343 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1344 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1345 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1346 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1347 .resetfn
= arm_cp_reset_ignore
},
1348 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1349 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1350 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1351 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1352 .resetfn
= arm_cp_reset_ignore
},
1353 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1354 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1355 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1356 /* 32 bit ITLB invalidates */
1357 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1358 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1359 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1360 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1361 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1362 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1363 /* 32 bit DTLB invalidates */
1364 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1365 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1366 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1367 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1368 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1369 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1370 /* 32 bit TLB invalidates */
1371 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1372 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1373 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1374 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1375 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1376 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1377 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1378 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1382 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1383 /* 32 bit TLB invalidates, Inner Shareable */
1384 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1385 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1386 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1387 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1388 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1389 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1390 .writefn
= tlbiasid_is_write
},
1391 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1392 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1393 .writefn
= tlbimvaa_is_write
},
1397 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1404 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1407 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1408 return CP_ACCESS_TRAP
;
1410 return CP_ACCESS_OK
;
1413 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1414 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1415 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1417 .writefn
= teecr_write
},
1418 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1419 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1420 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1424 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1425 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1426 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1428 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1429 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1431 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1432 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1433 .resetfn
= arm_cp_reset_ignore
},
1434 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1435 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1436 .access
= PL0_R
|PL1_W
,
1437 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1439 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1440 .access
= PL0_R
|PL1_W
,
1441 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1442 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1443 .resetfn
= arm_cp_reset_ignore
},
1444 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1445 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1447 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1448 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1450 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1451 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1456 #ifndef CONFIG_USER_ONLY
1458 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1461 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1462 * Writable only at the highest implemented exception level.
1464 int el
= arm_current_el(env
);
1468 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1469 return CP_ACCESS_TRAP
;
1473 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1474 arm_is_secure_below_el3(env
)) {
1475 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1476 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1484 if (!isread
&& el
< arm_highest_el(env
)) {
1485 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1488 return CP_ACCESS_OK
;
1491 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1494 unsigned int cur_el
= arm_current_el(env
);
1495 bool secure
= arm_is_secure(env
);
1497 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1499 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1500 return CP_ACCESS_TRAP
;
1503 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1504 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1505 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1506 return CP_ACCESS_TRAP_EL2
;
1508 return CP_ACCESS_OK
;
1511 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1514 unsigned int cur_el
= arm_current_el(env
);
1515 bool secure
= arm_is_secure(env
);
1517 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1518 * EL0[PV]TEN is zero.
1521 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1522 return CP_ACCESS_TRAP
;
1525 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1526 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1527 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1528 return CP_ACCESS_TRAP_EL2
;
1530 return CP_ACCESS_OK
;
1533 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1534 const ARMCPRegInfo
*ri
,
1537 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1540 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1541 const ARMCPRegInfo
*ri
,
1544 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1547 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1550 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1553 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1556 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1559 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1560 const ARMCPRegInfo
*ri
,
1563 /* The AArch64 register view of the secure physical timer is
1564 * always accessible from EL3, and configurably accessible from
1567 switch (arm_current_el(env
)) {
1569 if (!arm_is_secure(env
)) {
1570 return CP_ACCESS_TRAP
;
1572 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1573 return CP_ACCESS_TRAP_EL3
;
1575 return CP_ACCESS_OK
;
1578 return CP_ACCESS_TRAP
;
1580 return CP_ACCESS_OK
;
1582 g_assert_not_reached();
1586 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1588 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1591 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1593 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1596 /* Timer enabled: calculate and set current ISTATUS, irq, and
1597 * reset timer to when ISTATUS next has to change
1599 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1600 cpu
->env
.cp15
.cntvoff_el2
: 0;
1601 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1602 /* Note that this must be unsigned 64 bit arithmetic: */
1603 int istatus
= count
- offset
>= gt
->cval
;
1607 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1609 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1610 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1613 /* Next transition is when count rolls back over to zero */
1614 nexttick
= UINT64_MAX
;
1616 /* Next transition is when we hit cval */
1617 nexttick
= gt
->cval
+ offset
;
1619 /* Note that the desired next expiry time might be beyond the
1620 * signed-64-bit range of a QEMUTimer -- in this case we just
1621 * set the timer for as far in the future as possible. When the
1622 * timer expires we will reset the timer for any remaining period.
1624 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1625 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1627 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1628 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1630 /* Timer disabled: ISTATUS and timer output always clear */
1632 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1633 timer_del(cpu
->gt_timer
[timeridx
]);
1634 trace_arm_gt_recalc_disabled(timeridx
);
1638 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1641 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1643 timer_del(cpu
->gt_timer
[timeridx
]);
1646 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1648 return gt_get_countervalue(env
);
1651 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1653 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1656 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1660 trace_arm_gt_cval_write(timeridx
, value
);
1661 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1662 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1665 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1668 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1670 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1671 (gt_get_countervalue(env
) - offset
));
1674 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1678 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1680 trace_arm_gt_tval_write(timeridx
, value
);
1681 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1682 sextract64(value
, 0, 32);
1683 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1686 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1690 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1691 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1693 trace_arm_gt_ctl_write(timeridx
, value
);
1694 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1695 if ((oldval
^ value
) & 1) {
1696 /* Enable toggled */
1697 gt_recalc_timer(cpu
, timeridx
);
1698 } else if ((oldval
^ value
) & 2) {
1699 /* IMASK toggled: don't need to recalculate,
1700 * just set the interrupt line based on ISTATUS
1702 int irqstate
= (oldval
& 4) && !(value
& 2);
1704 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1705 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1709 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1711 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1714 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1717 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1720 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1722 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1725 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1731 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1734 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1737 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1739 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1742 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1745 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1748 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1750 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1753 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1756 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1759 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1762 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1765 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1768 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1770 trace_arm_gt_cntvoff_write(value
);
1771 raw_write(env
, ri
, value
);
1772 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1775 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1777 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1780 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1783 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1786 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1788 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1791 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1794 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1797 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1800 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1803 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1805 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1808 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1814 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1816 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1819 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1822 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1825 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1828 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1831 void arm_gt_ptimer_cb(void *opaque
)
1833 ARMCPU
*cpu
= opaque
;
1835 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1838 void arm_gt_vtimer_cb(void *opaque
)
1840 ARMCPU
*cpu
= opaque
;
1842 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1845 void arm_gt_htimer_cb(void *opaque
)
1847 ARMCPU
*cpu
= opaque
;
1849 gt_recalc_timer(cpu
, GTIMER_HYP
);
1852 void arm_gt_stimer_cb(void *opaque
)
1854 ARMCPU
*cpu
= opaque
;
1856 gt_recalc_timer(cpu
, GTIMER_SEC
);
1859 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1860 /* Note that CNTFRQ is purely reads-as-written for the benefit
1861 * of software; writing it doesn't actually change the timer frequency.
1862 * Our reset value matches the fixed frequency we implement the timer at.
1864 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1865 .type
= ARM_CP_ALIAS
,
1866 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1867 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1869 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1870 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1871 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1872 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1873 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1875 /* overall control: mostly access permissions */
1876 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1877 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1879 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1882 /* per-timer control */
1883 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1884 .secure
= ARM_CP_SECSTATE_NS
,
1885 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1886 .accessfn
= gt_ptimer_access
,
1887 .fieldoffset
= offsetoflow32(CPUARMState
,
1888 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1889 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1891 { .name
= "CNTP_CTL(S)",
1892 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1893 .secure
= ARM_CP_SECSTATE_S
,
1894 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1895 .accessfn
= gt_ptimer_access
,
1896 .fieldoffset
= offsetoflow32(CPUARMState
,
1897 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1898 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1900 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1901 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1902 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1903 .accessfn
= gt_ptimer_access
,
1904 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1906 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1908 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1909 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1910 .accessfn
= gt_vtimer_access
,
1911 .fieldoffset
= offsetoflow32(CPUARMState
,
1912 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1913 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1915 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1916 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1917 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1918 .accessfn
= gt_vtimer_access
,
1919 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1921 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1923 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1924 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1925 .secure
= ARM_CP_SECSTATE_NS
,
1926 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1927 .accessfn
= gt_ptimer_access
,
1928 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1930 { .name
= "CNTP_TVAL(S)",
1931 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1932 .secure
= ARM_CP_SECSTATE_S
,
1933 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1934 .accessfn
= gt_ptimer_access
,
1935 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
1937 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1938 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1939 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1940 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
1941 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1943 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1944 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1945 .accessfn
= gt_vtimer_access
,
1946 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1948 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1949 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1950 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1951 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
1952 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1954 /* The counter itself */
1955 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1956 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1957 .accessfn
= gt_pct_access
,
1958 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1960 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1961 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1962 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1963 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
1965 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1966 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1967 .accessfn
= gt_vct_access
,
1968 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1970 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1971 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1972 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1973 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
1975 /* Comparison value, indicating when the timer goes off */
1976 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1977 .secure
= ARM_CP_SECSTATE_NS
,
1978 .access
= PL1_RW
| PL0_R
,
1979 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1980 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1981 .accessfn
= gt_ptimer_access
,
1982 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
1984 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
1985 .secure
= ARM_CP_SECSTATE_S
,
1986 .access
= PL1_RW
| PL0_R
,
1987 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1988 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
1989 .accessfn
= gt_ptimer_access
,
1990 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
1992 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1993 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1994 .access
= PL1_RW
| PL0_R
,
1996 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1997 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
1998 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2000 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2001 .access
= PL1_RW
| PL0_R
,
2002 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2003 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2004 .accessfn
= gt_vtimer_access
,
2005 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2007 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2008 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2009 .access
= PL1_RW
| PL0_R
,
2011 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2012 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2013 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2015 /* Secure timer -- this is actually restricted to only EL3
2016 * and configurably Secure-EL1 via the accessfn.
2018 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2019 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2020 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2021 .accessfn
= gt_stimer_access
,
2022 .readfn
= gt_sec_tval_read
,
2023 .writefn
= gt_sec_tval_write
,
2024 .resetfn
= gt_sec_timer_reset
,
2026 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2027 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2028 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2029 .accessfn
= gt_stimer_access
,
2030 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2032 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2034 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2035 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2036 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2037 .accessfn
= gt_stimer_access
,
2038 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2039 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2045 /* In user-mode none of the generic timer registers are accessible,
2046 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
2047 * so instead just don't register any of them.
2049 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2055 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2057 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2058 raw_write(env
, ri
, value
);
2059 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2060 raw_write(env
, ri
, value
& 0xfffff6ff);
2062 raw_write(env
, ri
, value
& 0xfffff1ff);
2066 #ifndef CONFIG_USER_ONLY
2067 /* get_phys_addr() isn't present for user-mode-only targets */
2069 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2073 /* The ATS12NSO* operations must trap to EL3 if executed in
2074 * Secure EL1 (which can only happen if EL3 is AArch64).
2075 * They are simply UNDEF if executed from NS EL1.
2076 * They function normally from EL2 or EL3.
2078 if (arm_current_el(env
) == 1) {
2079 if (arm_is_secure_below_el3(env
)) {
2080 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2082 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2085 return CP_ACCESS_OK
;
2088 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2089 int access_type
, ARMMMUIdx mmu_idx
)
2092 target_ulong page_size
;
2097 MemTxAttrs attrs
= {};
2098 ARMMMUFaultInfo fi
= {};
2100 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
2101 &phys_addr
, &attrs
, &prot
, &page_size
, &fsr
, &fi
);
2102 if (extended_addresses_enabled(env
)) {
2103 /* fsr is a DFSR/IFSR value for the long descriptor
2104 * translation table format, but with WnR always clear.
2105 * Convert it to a 64-bit PAR.
2107 par64
= (1 << 11); /* LPAE bit always set */
2109 par64
|= phys_addr
& ~0xfffULL
;
2110 if (!attrs
.secure
) {
2111 par64
|= (1 << 9); /* NS */
2113 /* We don't set the ATTR or SH fields in the PAR. */
2116 par64
|= (fsr
& 0x3f) << 1; /* FS */
2117 /* Note that S2WLK and FSTAGE are always zero, because we don't
2118 * implement virtualization and therefore there can't be a stage 2
2123 /* fsr is a DFSR/IFSR value for the short descriptor
2124 * translation table format (with WnR always clear).
2125 * Convert it to a 32-bit PAR.
2128 /* We do not set any attribute bits in the PAR */
2129 if (page_size
== (1 << 24)
2130 && arm_feature(env
, ARM_FEATURE_V7
)) {
2131 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2133 par64
= phys_addr
& 0xfffff000;
2135 if (!attrs
.secure
) {
2136 par64
|= (1 << 9); /* NS */
2139 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2140 ((fsr
& 0xf) << 1) | 1;
2146 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2148 int access_type
= ri
->opc2
& 1;
2151 int el
= arm_current_el(env
);
2152 bool secure
= arm_is_secure_below_el3(env
);
2154 switch (ri
->opc2
& 6) {
2156 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2159 mmu_idx
= ARMMMUIdx_S1E3
;
2162 mmu_idx
= ARMMMUIdx_S1NSE1
;
2165 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2168 g_assert_not_reached();
2172 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2175 mmu_idx
= ARMMMUIdx_S1SE0
;
2178 mmu_idx
= ARMMMUIdx_S1NSE0
;
2181 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2184 g_assert_not_reached();
2188 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2189 mmu_idx
= ARMMMUIdx_S12NSE1
;
2192 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2193 mmu_idx
= ARMMMUIdx_S12NSE0
;
2196 g_assert_not_reached();
2199 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2201 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2204 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2207 int access_type
= ri
->opc2
& 1;
2210 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2212 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2215 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2218 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2219 return CP_ACCESS_TRAP
;
2221 return CP_ACCESS_OK
;
2224 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2227 int access_type
= ri
->opc2
& 1;
2229 int secure
= arm_is_secure_below_el3(env
);
2231 switch (ri
->opc2
& 6) {
2234 case 0: /* AT S1E1R, AT S1E1W */
2235 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2237 case 4: /* AT S1E2R, AT S1E2W */
2238 mmu_idx
= ARMMMUIdx_S1E2
;
2240 case 6: /* AT S1E3R, AT S1E3W */
2241 mmu_idx
= ARMMMUIdx_S1E3
;
2244 g_assert_not_reached();
2247 case 2: /* AT S1E0R, AT S1E0W */
2248 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2250 case 4: /* AT S12E1R, AT S12E1W */
2251 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2253 case 6: /* AT S12E0R, AT S12E0W */
2254 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2257 g_assert_not_reached();
2260 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2264 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2265 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2266 .access
= PL1_RW
, .resetvalue
= 0,
2267 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2268 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2269 .writefn
= par_write
},
2270 #ifndef CONFIG_USER_ONLY
2271 /* This underdecoding is safe because the reginfo is NO_RAW. */
2272 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2273 .access
= PL1_W
, .accessfn
= ats_access
,
2274 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2279 /* Return basic MPU access permission bits. */
2280 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2287 for (i
= 0; i
< 16; i
+= 2) {
2288 ret
|= (val
>> i
) & mask
;
2294 /* Pad basic MPU access permission bits to extended format. */
2295 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2302 for (i
= 0; i
< 16; i
+= 2) {
2303 ret
|= (val
& mask
) << i
;
2309 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2312 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2315 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2317 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2320 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2323 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2326 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2328 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2331 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2333 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2339 u32p
+= env
->cp15
.c6_rgnr
;
2343 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2346 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2347 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2353 u32p
+= env
->cp15
.c6_rgnr
;
2354 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2358 static void pmsav7_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2360 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2361 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2367 memset(u32p
, 0, sizeof(*u32p
) * cpu
->pmsav7_dregion
);
2370 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2373 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2374 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2376 if (value
>= nrgs
) {
2377 qemu_log_mask(LOG_GUEST_ERROR
,
2378 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2379 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2383 raw_write(env
, ri
, value
);
2386 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2387 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2388 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2389 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2390 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2391 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2392 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2393 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2394 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2395 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2396 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2397 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2398 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2399 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2401 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_rgnr
),
2402 .writefn
= pmsav7_rgnr_write
},
2406 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2407 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2408 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2409 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2410 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2411 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2412 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2413 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2414 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2415 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2417 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2419 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2421 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2423 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2425 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2426 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2428 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2429 /* Protection region base and size registers */
2430 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2431 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2432 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2433 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2434 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2435 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2436 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2437 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2438 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2439 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2440 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2441 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2442 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2443 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2444 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2445 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2446 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2447 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2448 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2449 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2450 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2451 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2452 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2453 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2457 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2460 TCR
*tcr
= raw_ptr(env
, ri
);
2461 int maskshift
= extract32(value
, 0, 3);
2463 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2464 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2465 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2466 * using Long-desciptor translation table format */
2467 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2468 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2469 /* In an implementation that includes the Security Extensions
2470 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2471 * Short-descriptor translation table format.
2473 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2479 /* Update the masks corresponding to the TCR bank being written
2480 * Note that we always calculate mask and base_mask, but
2481 * they are only used for short-descriptor tables (ie if EAE is 0);
2482 * for long-descriptor tables the TCR fields are used differently
2483 * and the mask and base_mask values are meaningless.
2485 tcr
->raw_tcr
= value
;
2486 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2487 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2490 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2493 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2495 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2496 /* With LPAE the TTBCR could result in a change of ASID
2497 * via the TTBCR.A1 bit, so do a TLB flush.
2499 tlb_flush(CPU(cpu
));
2501 vmsa_ttbcr_raw_write(env
, ri
, value
);
2504 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2506 TCR
*tcr
= raw_ptr(env
, ri
);
2508 /* Reset both the TCR as well as the masks corresponding to the bank of
2509 * the TCR being reset.
2513 tcr
->base_mask
= 0xffffc000u
;
2516 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2519 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2520 TCR
*tcr
= raw_ptr(env
, ri
);
2522 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2523 tlb_flush(CPU(cpu
));
2524 tcr
->raw_tcr
= value
;
2527 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2530 /* 64 bit accesses to the TTBRs can change the ASID and so we
2531 * must flush the TLB.
2533 if (cpreg_field_is_64bit(ri
)) {
2534 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2536 tlb_flush(CPU(cpu
));
2538 raw_write(env
, ri
, value
);
2541 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2544 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2545 CPUState
*cs
= CPU(cpu
);
2547 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2548 if (raw_read(env
, ri
) != value
) {
2549 tlb_flush_by_mmuidx(cs
,
2550 (1 << ARMMMUIdx_S12NSE1
) |
2551 (1 << ARMMMUIdx_S12NSE0
) |
2552 (1 << ARMMMUIdx_S2NS
));
2553 raw_write(env
, ri
, value
);
2557 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2558 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2559 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2560 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2561 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2562 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2563 .access
= PL1_RW
, .resetvalue
= 0,
2564 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2565 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2566 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2567 .access
= PL1_RW
, .resetvalue
= 0,
2568 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2569 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2570 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2571 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2572 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2577 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2578 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2579 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2581 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2582 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2583 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2584 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2585 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2586 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2587 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2588 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2589 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2590 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2591 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2592 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2593 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2594 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2595 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2596 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2597 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2598 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2599 .raw_writefn
= vmsa_ttbcr_raw_write
,
2600 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2601 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2605 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2608 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2609 /* The OS_TYPE bit in this register changes the reported CPUID! */
2610 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2611 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2614 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2617 env
->cp15
.c15_threadid
= value
& 0xffff;
2620 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2623 /* Wait-for-interrupt (deprecated) */
2624 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2627 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2630 /* On OMAP there are registers indicating the max/min index of dcache lines
2631 * containing a dirty line; cache flush operations have to reset these.
2633 env
->cp15
.c15_i_max
= 0x000;
2634 env
->cp15
.c15_i_min
= 0xff0;
2637 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2638 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2639 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2640 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2642 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2643 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2644 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2646 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2647 .writefn
= omap_ticonfig_write
},
2648 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2650 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2651 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2652 .access
= PL1_RW
, .resetvalue
= 0xff0,
2653 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2654 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2656 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2657 .writefn
= omap_threadid_write
},
2658 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2659 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2660 .type
= ARM_CP_NO_RAW
,
2661 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2662 /* TODO: Peripheral port remap register:
2663 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2664 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2667 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2668 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2669 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2670 .writefn
= omap_cachemaint_write
},
2671 { .name
= "C9", .cp
= 15, .crn
= 9,
2672 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2673 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2677 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2680 env
->cp15
.c15_cpar
= value
& 0x3fff;
2683 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2684 { .name
= "XSCALE_CPAR",
2685 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2686 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2687 .writefn
= xscale_cpar_write
, },
2688 { .name
= "XSCALE_AUXCR",
2689 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2690 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2692 /* XScale specific cache-lockdown: since we have no cache we NOP these
2693 * and hope the guest does not really rely on cache behaviour.
2695 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2696 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2697 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2698 { .name
= "XSCALE_UNLOCK_ICACHE",
2699 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2700 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2701 { .name
= "XSCALE_DCACHE_LOCK",
2702 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2703 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2704 { .name
= "XSCALE_UNLOCK_DCACHE",
2705 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2706 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2710 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2711 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2712 * implementation of this implementation-defined space.
2713 * Ideally this should eventually disappear in favour of actually
2714 * implementing the correct behaviour for all cores.
2716 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2717 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2719 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2724 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2725 /* Cache status: RAZ because we have no cache so it's always clean */
2726 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2727 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2732 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2733 /* We never have a a block transfer operation in progress */
2734 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2735 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2737 /* The cache ops themselves: these all NOP for QEMU */
2738 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2739 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2740 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2741 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2742 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2743 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2744 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2745 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2746 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2747 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2748 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2749 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2753 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2754 /* The cache test-and-clean instructions always return (1 << 30)
2755 * to indicate that there are no dirty cache lines.
2757 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2758 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2759 .resetvalue
= (1 << 30) },
2760 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2761 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2762 .resetvalue
= (1 << 30) },
2766 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2767 /* Ignore ReadBuffer accesses */
2768 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2769 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2770 .access
= PL1_RW
, .resetvalue
= 0,
2771 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2775 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2777 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2778 unsigned int cur_el
= arm_current_el(env
);
2779 bool secure
= arm_is_secure(env
);
2781 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2782 return env
->cp15
.vpidr_el2
;
2784 return raw_read(env
, ri
);
2787 static uint64_t mpidr_read_val(CPUARMState
*env
)
2789 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2790 uint64_t mpidr
= cpu
->mp_affinity
;
2792 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2793 mpidr
|= (1U << 31);
2794 /* Cores which are uniprocessor (non-coherent)
2795 * but still implement the MP extensions set
2796 * bit 30. (For instance, Cortex-R5).
2798 if (cpu
->mp_is_up
) {
2799 mpidr
|= (1u << 30);
2805 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2807 unsigned int cur_el
= arm_current_el(env
);
2808 bool secure
= arm_is_secure(env
);
2810 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2811 return env
->cp15
.vmpidr_el2
;
2813 return mpidr_read_val(env
);
2816 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2817 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2818 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2819 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2823 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2825 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2826 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2827 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2829 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2830 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2831 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2833 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2834 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2835 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2836 offsetof(CPUARMState
, cp15
.par_ns
)} },
2837 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2838 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2839 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2840 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2841 .writefn
= vmsa_ttbr_write
, },
2842 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2843 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2844 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2845 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2846 .writefn
= vmsa_ttbr_write
, },
2850 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2852 return vfp_get_fpcr(env
);
2855 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2858 vfp_set_fpcr(env
, value
);
2861 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2863 return vfp_get_fpsr(env
);
2866 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2869 vfp_set_fpsr(env
, value
);
2872 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2875 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2876 return CP_ACCESS_TRAP
;
2878 return CP_ACCESS_OK
;
2881 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2884 env
->daif
= value
& PSTATE_DAIF
;
2887 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2888 const ARMCPRegInfo
*ri
,
2891 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2892 * SCTLR_EL1.UCI is set.
2894 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2895 return CP_ACCESS_TRAP
;
2897 return CP_ACCESS_OK
;
2900 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2901 * Page D4-1736 (DDI0487A.b)
2904 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2907 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2908 CPUState
*cs
= CPU(cpu
);
2910 if (arm_is_secure_below_el3(env
)) {
2911 tlb_flush_by_mmuidx(cs
,
2912 (1 << ARMMMUIdx_S1SE1
) |
2913 (1 << ARMMMUIdx_S1SE0
));
2915 tlb_flush_by_mmuidx(cs
,
2916 (1 << ARMMMUIdx_S12NSE1
) |
2917 (1 << ARMMMUIdx_S12NSE0
));
2921 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2924 bool sec
= arm_is_secure_below_el3(env
);
2927 CPU_FOREACH(other_cs
) {
2929 tlb_flush_by_mmuidx(other_cs
,
2930 (1 << ARMMMUIdx_S1SE1
) |
2931 (1 << ARMMMUIdx_S1SE0
));
2933 tlb_flush_by_mmuidx(other_cs
,
2934 (1 << ARMMMUIdx_S12NSE1
) |
2935 (1 << ARMMMUIdx_S12NSE0
));
2940 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2943 /* Note that the 'ALL' scope must invalidate both stage 1 and
2944 * stage 2 translations, whereas most other scopes only invalidate
2945 * stage 1 translations.
2947 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2948 CPUState
*cs
= CPU(cpu
);
2950 if (arm_is_secure_below_el3(env
)) {
2951 tlb_flush_by_mmuidx(cs
,
2952 (1 << ARMMMUIdx_S1SE1
) |
2953 (1 << ARMMMUIdx_S1SE0
));
2955 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2956 tlb_flush_by_mmuidx(cs
,
2957 (1 << ARMMMUIdx_S12NSE1
) |
2958 (1 << ARMMMUIdx_S12NSE0
) |
2959 (1 << ARMMMUIdx_S2NS
));
2961 tlb_flush_by_mmuidx(cs
,
2962 (1 << ARMMMUIdx_S12NSE1
) |
2963 (1 << ARMMMUIdx_S12NSE0
));
2968 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2971 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2972 CPUState
*cs
= CPU(cpu
);
2974 tlb_flush_by_mmuidx(cs
, (1 << ARMMMUIdx_S1E2
));
2977 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2980 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2981 CPUState
*cs
= CPU(cpu
);
2983 tlb_flush_by_mmuidx(cs
, (1 << ARMMMUIdx_S1E3
));
2986 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2989 /* Note that the 'ALL' scope must invalidate both stage 1 and
2990 * stage 2 translations, whereas most other scopes only invalidate
2991 * stage 1 translations.
2993 bool sec
= arm_is_secure_below_el3(env
);
2994 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
2997 CPU_FOREACH(other_cs
) {
2999 tlb_flush_by_mmuidx(other_cs
,
3000 (1 << ARMMMUIdx_S1SE1
) |
3001 (1 << ARMMMUIdx_S1SE0
));
3002 } else if (has_el2
) {
3003 tlb_flush_by_mmuidx(other_cs
,
3004 (1 << ARMMMUIdx_S12NSE1
) |
3005 (1 << ARMMMUIdx_S12NSE0
) |
3006 (1 << ARMMMUIdx_S2NS
));
3008 tlb_flush_by_mmuidx(other_cs
,
3009 (1 << ARMMMUIdx_S12NSE1
) |
3010 (1 << ARMMMUIdx_S12NSE0
));
3015 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3020 CPU_FOREACH(other_cs
) {
3021 tlb_flush_by_mmuidx(other_cs
, (1 << ARMMMUIdx_S1E2
));
3025 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3030 CPU_FOREACH(other_cs
) {
3031 tlb_flush_by_mmuidx(other_cs
, (1 << ARMMMUIdx_S1E3
));
3035 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3038 /* Invalidate by VA, EL1&0 (AArch64 version).
3039 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3040 * since we don't support flush-for-specific-ASID-only or
3041 * flush-last-level-only.
3043 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3044 CPUState
*cs
= CPU(cpu
);
3045 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3047 if (arm_is_secure_below_el3(env
)) {
3048 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3049 (1 << ARMMMUIdx_S1SE1
) |
3050 (1 << ARMMMUIdx_S1SE0
));
3052 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3053 (1 << ARMMMUIdx_S12NSE1
) |
3054 (1 << ARMMMUIdx_S12NSE0
));
3058 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3061 /* Invalidate by VA, EL2
3062 * Currently handles both VAE2 and VALE2, since we don't support
3063 * flush-last-level-only.
3065 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3066 CPUState
*cs
= CPU(cpu
);
3067 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3069 tlb_flush_page_by_mmuidx(cs
, pageaddr
, (1 << ARMMMUIdx_S1E2
));
3072 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3075 /* Invalidate by VA, EL3
3076 * Currently handles both VAE3 and VALE3, since we don't support
3077 * flush-last-level-only.
3079 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3080 CPUState
*cs
= CPU(cpu
);
3081 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3083 tlb_flush_page_by_mmuidx(cs
, pageaddr
, (1 << ARMMMUIdx_S1E3
));
3086 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3089 bool sec
= arm_is_secure_below_el3(env
);
3091 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3093 CPU_FOREACH(other_cs
) {
3095 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
,
3096 (1 << ARMMMUIdx_S1SE1
) |
3097 (1 << ARMMMUIdx_S1SE0
));
3099 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
,
3100 (1 << ARMMMUIdx_S12NSE1
) |
3101 (1 << ARMMMUIdx_S12NSE0
));
3106 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3110 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3112 CPU_FOREACH(other_cs
) {
3113 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, (1 << ARMMMUIdx_S1E2
));
3117 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3121 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3123 CPU_FOREACH(other_cs
) {
3124 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, (1 << ARMMMUIdx_S1E3
));
3128 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3131 /* Invalidate by IPA. This has to invalidate any structures that
3132 * contain only stage 2 translation information, but does not need
3133 * to apply to structures that contain combined stage 1 and stage 2
3134 * translation information.
3135 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3137 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3138 CPUState
*cs
= CPU(cpu
);
3141 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3145 pageaddr
= sextract64(value
<< 12, 0, 48);
3147 tlb_flush_page_by_mmuidx(cs
, pageaddr
, (1 << ARMMMUIdx_S2NS
));
3150 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3156 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3160 pageaddr
= sextract64(value
<< 12, 0, 48);
3162 CPU_FOREACH(other_cs
) {
3163 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, (1 << ARMMMUIdx_S2NS
));
3167 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3170 /* We don't implement EL2, so the only control on DC ZVA is the
3171 * bit in the SCTLR which can prohibit access for EL0.
3173 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3174 return CP_ACCESS_TRAP
;
3176 return CP_ACCESS_OK
;
3179 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3181 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3182 int dzp_bit
= 1 << 4;
3184 /* DZP indicates whether DC ZVA access is allowed */
3185 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3188 return cpu
->dcz_blocksize
| dzp_bit
;
3191 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3194 if (!(env
->pstate
& PSTATE_SP
)) {
3195 /* Access to SP_EL0 is undefined if it's being used as
3196 * the stack pointer.
3198 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3200 return CP_ACCESS_OK
;
3203 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3205 return env
->pstate
& PSTATE_SP
;
3208 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3210 update_spsel(env
, val
);
3213 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3216 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3218 if (raw_read(env
, ri
) == value
) {
3219 /* Skip the TLB flush if nothing actually changed; Linux likes
3220 * to do a lot of pointless SCTLR writes.
3225 raw_write(env
, ri
, value
);
3226 /* ??? Lots of these bits are not implemented. */
3227 /* This may enable/disable the MMU, so do a TLB flush. */
3228 tlb_flush(CPU(cpu
));
3231 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3234 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3235 return CP_ACCESS_TRAP_FP_EL2
;
3237 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3238 return CP_ACCESS_TRAP_FP_EL3
;
3240 return CP_ACCESS_OK
;
3243 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3246 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3249 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3250 /* Minimal set of EL0-visible registers. This will need to be expanded
3251 * significantly for system emulation of AArch64 CPUs.
3253 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3254 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3255 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3256 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3257 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3258 .type
= ARM_CP_NO_RAW
,
3259 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3260 .fieldoffset
= offsetof(CPUARMState
, daif
),
3261 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3262 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3263 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3264 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3265 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3266 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3267 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3268 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3269 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3270 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3271 .readfn
= aa64_dczid_read
},
3272 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3273 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3274 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3275 #ifndef CONFIG_USER_ONLY
3276 /* Avoid overhead of an access check that always passes in user-mode */
3277 .accessfn
= aa64_zva_access
,
3280 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3281 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3282 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3283 /* Cache ops: all NOPs since we don't emulate caches */
3284 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3285 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3286 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3287 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3288 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3289 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3290 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3291 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3292 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3293 .accessfn
= aa64_cacheop_access
},
3294 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3295 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3296 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3297 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3298 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3299 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3300 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3301 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3302 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3303 .accessfn
= aa64_cacheop_access
},
3304 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3305 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3306 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3307 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3308 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3309 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3310 .accessfn
= aa64_cacheop_access
},
3311 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3312 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3313 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3314 .accessfn
= aa64_cacheop_access
},
3315 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3316 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3317 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3318 /* TLBI operations */
3319 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3320 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3321 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3322 .writefn
= tlbi_aa64_vmalle1is_write
},
3323 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3324 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3325 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3326 .writefn
= tlbi_aa64_vae1is_write
},
3327 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3328 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3329 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3330 .writefn
= tlbi_aa64_vmalle1is_write
},
3331 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3333 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3334 .writefn
= tlbi_aa64_vae1is_write
},
3335 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3336 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3337 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3338 .writefn
= tlbi_aa64_vae1is_write
},
3339 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3340 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3341 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3342 .writefn
= tlbi_aa64_vae1is_write
},
3343 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3344 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3345 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3346 .writefn
= tlbi_aa64_vmalle1_write
},
3347 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3348 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3349 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3350 .writefn
= tlbi_aa64_vae1_write
},
3351 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3352 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3353 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3354 .writefn
= tlbi_aa64_vmalle1_write
},
3355 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3356 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3357 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3358 .writefn
= tlbi_aa64_vae1_write
},
3359 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3360 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3361 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3362 .writefn
= tlbi_aa64_vae1_write
},
3363 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3364 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3365 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3366 .writefn
= tlbi_aa64_vae1_write
},
3367 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3368 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3369 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3370 .writefn
= tlbi_aa64_ipas2e1is_write
},
3371 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3372 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3373 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3374 .writefn
= tlbi_aa64_ipas2e1is_write
},
3375 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3376 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3377 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3378 .writefn
= tlbi_aa64_alle1is_write
},
3379 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3380 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3381 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3382 .writefn
= tlbi_aa64_alle1is_write
},
3383 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3384 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3385 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3386 .writefn
= tlbi_aa64_ipas2e1_write
},
3387 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3388 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3389 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3390 .writefn
= tlbi_aa64_ipas2e1_write
},
3391 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3392 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3393 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3394 .writefn
= tlbi_aa64_alle1_write
},
3395 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3396 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3397 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3398 .writefn
= tlbi_aa64_alle1is_write
},
3399 #ifndef CONFIG_USER_ONLY
3400 /* 64 bit address translation operations */
3401 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3402 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3403 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3404 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3405 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3406 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3407 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3408 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3409 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3410 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3411 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3412 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3413 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3414 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3415 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3416 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3417 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3418 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3419 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3420 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3421 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3422 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3423 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3424 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3425 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3426 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3427 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3428 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3429 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3430 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3431 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3432 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3433 .type
= ARM_CP_ALIAS
,
3434 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3435 .access
= PL1_RW
, .resetvalue
= 0,
3436 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3437 .writefn
= par_write
},
3439 /* TLB invalidate last level of translation table walk */
3440 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3441 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3442 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3443 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3444 .writefn
= tlbimvaa_is_write
},
3445 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3446 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3447 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3448 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3449 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3450 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3451 .writefn
= tlbimva_hyp_write
},
3452 { .name
= "TLBIMVALHIS",
3453 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3454 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3455 .writefn
= tlbimva_hyp_is_write
},
3456 { .name
= "TLBIIPAS2",
3457 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3458 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3459 .writefn
= tlbiipas2_write
},
3460 { .name
= "TLBIIPAS2IS",
3461 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3462 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3463 .writefn
= tlbiipas2_is_write
},
3464 { .name
= "TLBIIPAS2L",
3465 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3466 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3467 .writefn
= tlbiipas2_write
},
3468 { .name
= "TLBIIPAS2LIS",
3469 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3470 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3471 .writefn
= tlbiipas2_is_write
},
3472 /* 32 bit cache operations */
3473 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3474 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3475 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3476 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3477 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3478 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3479 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3480 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3481 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3482 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3483 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3484 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3485 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3486 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3487 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3488 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3489 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3490 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3491 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3492 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3493 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3494 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3495 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3496 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3497 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3498 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3499 /* MMU Domain access control / MPU write buffer control */
3500 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3501 .access
= PL1_RW
, .resetvalue
= 0,
3502 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3503 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3504 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3505 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3506 .type
= ARM_CP_ALIAS
,
3507 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3509 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3510 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3511 .type
= ARM_CP_ALIAS
,
3512 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3514 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3515 /* We rely on the access checks not allowing the guest to write to the
3516 * state field when SPSel indicates that it's being used as the stack
3519 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3520 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3521 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3522 .type
= ARM_CP_ALIAS
,
3523 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3524 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3525 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3526 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3527 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3528 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3529 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3530 .type
= ARM_CP_NO_RAW
,
3531 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3532 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3533 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3534 .type
= ARM_CP_ALIAS
,
3535 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3536 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3537 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3538 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3539 .access
= PL2_RW
, .resetvalue
= 0,
3540 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3541 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3542 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3543 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3544 .access
= PL2_RW
, .resetvalue
= 0,
3545 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3546 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3547 .type
= ARM_CP_ALIAS
,
3548 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3550 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3551 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3552 .type
= ARM_CP_ALIAS
,
3553 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3555 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3556 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3557 .type
= ARM_CP_ALIAS
,
3558 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3560 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3561 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3562 .type
= ARM_CP_ALIAS
,
3563 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3565 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3566 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3567 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3569 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3570 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3571 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3572 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3573 .writefn
= sdcr_write
,
3574 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3578 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3579 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3580 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3581 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3583 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3584 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3585 .type
= ARM_CP_NO_RAW
,
3586 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3588 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3589 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3590 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3591 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3592 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3593 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3594 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3596 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3597 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3598 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3599 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3600 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3601 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3603 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3604 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3605 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3607 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3608 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3609 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3611 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3612 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3613 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3615 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3616 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3617 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3618 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3619 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3620 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3621 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3622 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3623 .cp
= 15, .opc1
= 6, .crm
= 2,
3624 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3625 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3626 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3627 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3628 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3629 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3630 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3631 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3632 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3633 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3634 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3635 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3636 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3637 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3638 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3639 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3641 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3642 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3643 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3644 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3645 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3646 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3647 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3648 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3650 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3651 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3652 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3653 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3654 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3656 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3657 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3658 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3659 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3660 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3661 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3662 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3663 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3664 .access
= PL2_RW
, .accessfn
= access_tda
,
3665 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3666 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3667 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3668 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3669 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3670 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3671 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3672 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3676 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3678 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3679 uint64_t valid_mask
= HCR_MASK
;
3681 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3682 valid_mask
&= ~HCR_HCD
;
3684 valid_mask
&= ~HCR_TSC
;
3687 /* Clear RES0 bits. */
3688 value
&= valid_mask
;
3690 /* These bits change the MMU setup:
3691 * HCR_VM enables stage 2 translation
3692 * HCR_PTW forbids certain page-table setups
3693 * HCR_DC Disables stage1 and enables stage2 translation
3695 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3696 tlb_flush(CPU(cpu
));
3698 raw_write(env
, ri
, value
);
3701 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3702 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3703 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3704 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3705 .writefn
= hcr_write
},
3706 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3707 .type
= ARM_CP_ALIAS
,
3708 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3710 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3711 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3712 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3713 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3714 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3715 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3716 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3717 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3718 .type
= ARM_CP_ALIAS
,
3719 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3721 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3722 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3723 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3724 .access
= PL2_RW
, .writefn
= vbar_write
,
3725 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3727 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3728 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3729 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3730 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3731 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3732 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3733 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3734 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3735 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3736 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3737 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3739 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3740 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3741 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3742 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3743 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3744 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3745 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3747 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3748 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3749 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3750 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3752 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3753 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3754 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3756 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3757 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3758 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3760 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3761 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3763 /* no .writefn needed as this can't cause an ASID change;
3764 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3766 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3767 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3768 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3769 .type
= ARM_CP_ALIAS
,
3770 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3771 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3772 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3773 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3775 /* no .writefn needed as this can't cause an ASID change;
3776 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3778 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3779 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3780 .cp
= 15, .opc1
= 6, .crm
= 2,
3781 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3782 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3783 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3784 .writefn
= vttbr_write
},
3785 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3786 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3787 .access
= PL2_RW
, .writefn
= vttbr_write
,
3788 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3789 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3790 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3791 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3792 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3793 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3794 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3795 .access
= PL2_RW
, .resetvalue
= 0,
3796 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3797 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3798 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3799 .access
= PL2_RW
, .resetvalue
= 0,
3800 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3801 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3802 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3803 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3804 { .name
= "TLBIALLNSNH",
3805 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3806 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3807 .writefn
= tlbiall_nsnh_write
},
3808 { .name
= "TLBIALLNSNHIS",
3809 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3810 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3811 .writefn
= tlbiall_nsnh_is_write
},
3812 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3813 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3814 .writefn
= tlbiall_hyp_write
},
3815 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3816 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3817 .writefn
= tlbiall_hyp_is_write
},
3818 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3819 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3820 .writefn
= tlbimva_hyp_write
},
3821 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3822 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3823 .writefn
= tlbimva_hyp_is_write
},
3824 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3825 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3826 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3827 .writefn
= tlbi_aa64_alle2_write
},
3828 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3829 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3830 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3831 .writefn
= tlbi_aa64_vae2_write
},
3832 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3833 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3834 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3835 .writefn
= tlbi_aa64_vae2_write
},
3836 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3837 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3838 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3839 .writefn
= tlbi_aa64_alle2is_write
},
3840 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3841 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3842 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3843 .writefn
= tlbi_aa64_vae2is_write
},
3844 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3845 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3846 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3847 .writefn
= tlbi_aa64_vae2is_write
},
3848 #ifndef CONFIG_USER_ONLY
3849 /* Unlike the other EL2-related AT operations, these must
3850 * UNDEF from EL3 if EL2 is not implemented, which is why we
3851 * define them here rather than with the rest of the AT ops.
3853 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3854 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3855 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3856 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3857 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3858 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3859 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3860 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3861 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3862 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3863 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3864 * to behave as if SCR.NS was 1.
3866 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3868 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3869 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3871 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3872 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3873 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3874 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3875 * reset values as IMPDEF. We choose to reset to 3 to comply with
3876 * both ARMv7 and ARMv8.
3878 .access
= PL2_RW
, .resetvalue
= 3,
3879 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3880 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3881 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3882 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3883 .writefn
= gt_cntvoff_write
,
3884 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3885 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3886 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3887 .writefn
= gt_cntvoff_write
,
3888 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3889 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3890 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3891 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3892 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3893 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3894 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3895 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3896 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
3897 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3898 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3899 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3900 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
3901 .resetfn
= gt_hyp_timer_reset
,
3902 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
3903 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3905 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3907 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
3909 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
3911 /* The only field of MDCR_EL2 that has a defined architectural reset value
3912 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3913 * don't impelment any PMU event counters, so using zero as a reset
3914 * value for MDCR_EL2 is okay
3916 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3917 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3918 .access
= PL2_RW
, .resetvalue
= 0,
3919 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
3920 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
3921 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3922 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3923 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3924 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
3925 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3927 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3928 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3929 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3931 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
3935 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3938 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3939 * At Secure EL1 it traps to EL3.
3941 if (arm_current_el(env
) == 3) {
3942 return CP_ACCESS_OK
;
3944 if (arm_is_secure_below_el3(env
)) {
3945 return CP_ACCESS_TRAP_EL3
;
3947 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3949 return CP_ACCESS_OK
;
3951 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3954 static const ARMCPRegInfo el3_cp_reginfo
[] = {
3955 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
3956 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
3957 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
3958 .resetvalue
= 0, .writefn
= scr_write
},
3959 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
3960 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
3961 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3962 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
3963 .writefn
= scr_write
},
3964 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
3965 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
3966 .access
= PL3_RW
, .resetvalue
= 0,
3967 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
3969 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
3970 .access
= PL3_RW
, .resetvalue
= 0,
3971 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
3972 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
3973 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3974 .writefn
= vbar_write
, .resetvalue
= 0,
3975 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
3976 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
3977 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
3978 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3979 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
3980 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
3981 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
3983 /* no .writefn needed as this can't cause an ASID change;
3984 * we must provide a .raw_writefn and .resetfn because we handle
3985 * reset and migration for the AArch32 TTBCR(S), which might be
3986 * using mask and base_mask.
3988 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
3989 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
3990 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
3991 .type
= ARM_CP_ALIAS
,
3992 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
3994 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
3995 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
3996 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
3997 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
3998 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
3999 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4000 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4001 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4002 .type
= ARM_CP_ALIAS
,
4003 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4005 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4006 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4007 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4008 .access
= PL3_RW
, .writefn
= vbar_write
,
4009 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4011 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4012 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4013 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4014 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4015 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4016 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4017 .access
= PL3_RW
, .resetvalue
= 0,
4018 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4019 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4020 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4021 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4023 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4024 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4025 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4027 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4028 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4029 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4031 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4032 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4033 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4034 .writefn
= tlbi_aa64_alle3is_write
},
4035 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4036 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4037 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4038 .writefn
= tlbi_aa64_vae3is_write
},
4039 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4040 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4041 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4042 .writefn
= tlbi_aa64_vae3is_write
},
4043 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4044 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4045 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4046 .writefn
= tlbi_aa64_alle3_write
},
4047 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4048 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4049 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4050 .writefn
= tlbi_aa64_vae3_write
},
4051 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4052 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4053 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4054 .writefn
= tlbi_aa64_vae3_write
},
4058 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4061 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4062 * but the AArch32 CTR has its own reginfo struct)
4064 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4065 return CP_ACCESS_TRAP
;
4067 return CP_ACCESS_OK
;
4070 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4073 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4074 * read via a bit in OSLSR_EL1.
4078 if (ri
->state
== ARM_CP_STATE_AA32
) {
4079 oslock
= (value
== 0xC5ACCE55);
4084 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4087 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4088 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4089 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4090 * unlike DBGDRAR it is never accessible from EL0.
4091 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4094 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4095 .access
= PL0_R
, .accessfn
= access_tdra
,
4096 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4097 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4098 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4099 .access
= PL1_R
, .accessfn
= access_tdra
,
4100 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4101 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4102 .access
= PL0_R
, .accessfn
= access_tdra
,
4103 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4104 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4105 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4106 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4107 .access
= PL1_RW
, .accessfn
= access_tda
,
4108 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4110 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4111 * We don't implement the configurable EL0 access.
4113 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4114 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4115 .type
= ARM_CP_ALIAS
,
4116 .access
= PL1_R
, .accessfn
= access_tda
,
4117 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4118 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4119 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4120 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4121 .accessfn
= access_tdosa
,
4122 .writefn
= oslar_write
},
4123 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4124 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4125 .access
= PL1_R
, .resetvalue
= 10,
4126 .accessfn
= access_tdosa
,
4127 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4128 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4129 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4130 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4131 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4132 .type
= ARM_CP_NOP
},
4133 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4134 * implement vector catch debug events yet.
4137 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4138 .access
= PL1_RW
, .accessfn
= access_tda
,
4139 .type
= ARM_CP_NOP
},
4140 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4141 * to save and restore a 32-bit guest's DBGVCR)
4143 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4144 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4145 .access
= PL2_RW
, .accessfn
= access_tda
,
4146 .type
= ARM_CP_NOP
},
4147 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4148 * Channel but Linux may try to access this register. The 32-bit
4149 * alias is DBGDCCINT.
4151 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4152 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4153 .access
= PL1_RW
, .accessfn
= access_tda
,
4154 .type
= ARM_CP_NOP
},
4158 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4159 /* 64 bit access versions of the (dummy) debug registers */
4160 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4161 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4162 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4163 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4167 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4169 CPUARMState
*env
= &cpu
->env
;
4171 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4172 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4174 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4176 if (env
->cpu_watchpoint
[n
]) {
4177 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4178 env
->cpu_watchpoint
[n
] = NULL
;
4181 if (!extract64(wcr
, 0, 1)) {
4182 /* E bit clear : watchpoint disabled */
4186 switch (extract64(wcr
, 3, 2)) {
4188 /* LSC 00 is reserved and must behave as if the wp is disabled */
4191 flags
|= BP_MEM_READ
;
4194 flags
|= BP_MEM_WRITE
;
4197 flags
|= BP_MEM_ACCESS
;
4201 /* Attempts to use both MASK and BAS fields simultaneously are
4202 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4203 * thus generating a watchpoint for every byte in the masked region.
4205 mask
= extract64(wcr
, 24, 4);
4206 if (mask
== 1 || mask
== 2) {
4207 /* Reserved values of MASK; we must act as if the mask value was
4208 * some non-reserved value, or as if the watchpoint were disabled.
4209 * We choose the latter.
4213 /* Watchpoint covers an aligned area up to 2GB in size */
4215 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4216 * whether the watchpoint fires when the unmasked bits match; we opt
4217 * to generate the exceptions.
4221 /* Watchpoint covers bytes defined by the byte address select bits */
4222 int bas
= extract64(wcr
, 5, 8);
4226 /* This must act as if the watchpoint is disabled */
4230 if (extract64(wvr
, 2, 1)) {
4231 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4232 * ignored, and BAS[3:0] define which bytes to watch.
4236 /* The BAS bits are supposed to be programmed to indicate a contiguous
4237 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4238 * we fire for each byte in the word/doubleword addressed by the WVR.
4239 * We choose to ignore any non-zero bits after the first range of 1s.
4241 basstart
= ctz32(bas
);
4242 len
= cto32(bas
>> basstart
);
4246 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4247 &env
->cpu_watchpoint
[n
]);
4250 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4253 CPUARMState
*env
= &cpu
->env
;
4255 /* Completely clear out existing QEMU watchpoints and our array, to
4256 * avoid possible stale entries following migration load.
4258 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4259 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4261 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4262 hw_watchpoint_update(cpu
, i
);
4266 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4269 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4272 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4273 * register reads and behaves as if values written are sign extended.
4274 * Bits [1:0] are RES0.
4276 value
= sextract64(value
, 0, 49) & ~3ULL;
4278 raw_write(env
, ri
, value
);
4279 hw_watchpoint_update(cpu
, i
);
4282 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4285 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4288 raw_write(env
, ri
, value
);
4289 hw_watchpoint_update(cpu
, i
);
4292 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4294 CPUARMState
*env
= &cpu
->env
;
4295 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4296 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4301 if (env
->cpu_breakpoint
[n
]) {
4302 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4303 env
->cpu_breakpoint
[n
] = NULL
;
4306 if (!extract64(bcr
, 0, 1)) {
4307 /* E bit clear : watchpoint disabled */
4311 bt
= extract64(bcr
, 20, 4);
4314 case 4: /* unlinked address mismatch (reserved if AArch64) */
4315 case 5: /* linked address mismatch (reserved if AArch64) */
4316 qemu_log_mask(LOG_UNIMP
,
4317 "arm: address mismatch breakpoint types not implemented");
4319 case 0: /* unlinked address match */
4320 case 1: /* linked address match */
4322 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4323 * we behave as if the register was sign extended. Bits [1:0] are
4324 * RES0. The BAS field is used to allow setting breakpoints on 16
4325 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4326 * a bp will fire if the addresses covered by the bp and the addresses
4327 * covered by the insn overlap but the insn doesn't start at the
4328 * start of the bp address range. We choose to require the insn and
4329 * the bp to have the same address. The constraints on writing to
4330 * BAS enforced in dbgbcr_write mean we have only four cases:
4331 * 0b0000 => no breakpoint
4332 * 0b0011 => breakpoint on addr
4333 * 0b1100 => breakpoint on addr + 2
4334 * 0b1111 => breakpoint on addr
4335 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4337 int bas
= extract64(bcr
, 5, 4);
4338 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4347 case 2: /* unlinked context ID match */
4348 case 8: /* unlinked VMID match (reserved if no EL2) */
4349 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4350 qemu_log_mask(LOG_UNIMP
,
4351 "arm: unlinked context breakpoint types not implemented");
4353 case 9: /* linked VMID match (reserved if no EL2) */
4354 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4355 case 3: /* linked context ID match */
4357 /* We must generate no events for Linked context matches (unless
4358 * they are linked to by some other bp/wp, which is handled in
4359 * updates for the linking bp/wp). We choose to also generate no events
4360 * for reserved values.
4365 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4368 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4371 CPUARMState
*env
= &cpu
->env
;
4373 /* Completely clear out existing QEMU breakpoints and our array, to
4374 * avoid possible stale entries following migration load.
4376 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4377 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4379 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4380 hw_breakpoint_update(cpu
, i
);
4384 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4387 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4390 raw_write(env
, ri
, value
);
4391 hw_breakpoint_update(cpu
, i
);
4394 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4397 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4400 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4403 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4404 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4406 raw_write(env
, ri
, value
);
4407 hw_breakpoint_update(cpu
, i
);
4410 static void define_debug_regs(ARMCPU
*cpu
)
4412 /* Define v7 and v8 architectural debug registers.
4413 * These are just dummy implementations for now.
4416 int wrps
, brps
, ctx_cmps
;
4417 ARMCPRegInfo dbgdidr
= {
4418 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4419 .access
= PL0_R
, .accessfn
= access_tda
,
4420 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4423 /* Note that all these register fields hold "number of Xs minus 1". */
4424 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4425 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4426 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4428 assert(ctx_cmps
<= brps
);
4430 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4431 * of the debug registers such as number of breakpoints;
4432 * check that if they both exist then they agree.
4434 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4435 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4436 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4437 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4440 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4441 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4443 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4444 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4447 for (i
= 0; i
< brps
+ 1; i
++) {
4448 ARMCPRegInfo dbgregs
[] = {
4449 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4450 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4451 .access
= PL1_RW
, .accessfn
= access_tda
,
4452 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4453 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4455 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4456 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4457 .access
= PL1_RW
, .accessfn
= access_tda
,
4458 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4459 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4463 define_arm_cp_regs(cpu
, dbgregs
);
4466 for (i
= 0; i
< wrps
+ 1; i
++) {
4467 ARMCPRegInfo dbgregs
[] = {
4468 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4469 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4470 .access
= PL1_RW
, .accessfn
= access_tda
,
4471 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4472 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4474 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4475 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4476 .access
= PL1_RW
, .accessfn
= access_tda
,
4477 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4478 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4482 define_arm_cp_regs(cpu
, dbgregs
);
4486 void register_cp_regs_for_features(ARMCPU
*cpu
)
4488 /* Register all the coprocessor registers based on feature bits */
4489 CPUARMState
*env
= &cpu
->env
;
4490 if (arm_feature(env
, ARM_FEATURE_M
)) {
4491 /* M profile has no coprocessor registers */
4495 define_arm_cp_regs(cpu
, cp_reginfo
);
4496 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4497 /* Must go early as it is full of wildcards that may be
4498 * overridden by later definitions.
4500 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4503 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4504 /* The ID registers all have impdef reset values */
4505 ARMCPRegInfo v6_idregs
[] = {
4506 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4507 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4508 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4509 .resetvalue
= cpu
->id_pfr0
},
4510 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4511 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4512 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4513 .resetvalue
= cpu
->id_pfr1
},
4514 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4515 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4516 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4517 .resetvalue
= cpu
->id_dfr0
},
4518 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4519 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4520 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4521 .resetvalue
= cpu
->id_afr0
},
4522 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4523 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4524 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4525 .resetvalue
= cpu
->id_mmfr0
},
4526 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4527 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4528 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4529 .resetvalue
= cpu
->id_mmfr1
},
4530 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4531 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4532 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4533 .resetvalue
= cpu
->id_mmfr2
},
4534 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4535 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4536 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4537 .resetvalue
= cpu
->id_mmfr3
},
4538 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4539 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4540 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4541 .resetvalue
= cpu
->id_isar0
},
4542 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4543 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4544 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4545 .resetvalue
= cpu
->id_isar1
},
4546 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4547 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4548 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4549 .resetvalue
= cpu
->id_isar2
},
4550 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4551 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4552 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4553 .resetvalue
= cpu
->id_isar3
},
4554 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4555 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4556 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4557 .resetvalue
= cpu
->id_isar4
},
4558 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4559 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4560 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4561 .resetvalue
= cpu
->id_isar5
},
4562 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4563 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4564 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4565 .resetvalue
= cpu
->id_mmfr4
},
4566 /* 7 is as yet unallocated and must RAZ */
4567 { .name
= "ID_ISAR7_RESERVED", .state
= ARM_CP_STATE_BOTH
,
4568 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4569 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4573 define_arm_cp_regs(cpu
, v6_idregs
);
4574 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4576 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4578 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4579 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4581 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4582 !arm_feature(env
, ARM_FEATURE_MPU
)) {
4583 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4585 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4586 /* v7 performance monitor control register: same implementor
4587 * field as main ID register, and we implement only the cycle
4590 #ifndef CONFIG_USER_ONLY
4591 ARMCPRegInfo pmcr
= {
4592 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4594 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4595 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4596 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4597 .raw_writefn
= raw_write
,
4599 ARMCPRegInfo pmcr64
= {
4600 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4601 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4602 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4604 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4605 .resetvalue
= cpu
->midr
& 0xff000000,
4606 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4608 define_one_arm_cp_reg(cpu
, &pmcr
);
4609 define_one_arm_cp_reg(cpu
, &pmcr64
);
4611 ARMCPRegInfo clidr
= {
4612 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4613 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4614 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4616 define_one_arm_cp_reg(cpu
, &clidr
);
4617 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4618 define_debug_regs(cpu
);
4620 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4622 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4623 /* AArch64 ID registers, which all have impdef reset values.
4624 * Note that within the ID register ranges the unused slots
4625 * must all RAZ, not UNDEF; future architecture versions may
4626 * define new registers here.
4628 ARMCPRegInfo v8_idregs
[] = {
4629 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4630 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4631 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4632 .resetvalue
= cpu
->id_aa64pfr0
},
4633 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4634 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4635 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4636 .resetvalue
= cpu
->id_aa64pfr1
},
4637 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4638 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
4639 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4641 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4642 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
4643 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4645 { .name
= "ID_AA64PFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4646 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
4647 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4649 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4650 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
4651 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4653 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4654 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
4655 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4657 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4658 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
4659 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4661 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4662 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4663 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4664 .resetvalue
= cpu
->id_aa64dfr0
},
4665 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4666 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4667 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4668 .resetvalue
= cpu
->id_aa64dfr1
},
4669 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4670 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
4671 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4673 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4674 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
4675 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4677 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4678 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4679 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4680 .resetvalue
= cpu
->id_aa64afr0
},
4681 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4682 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4683 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4684 .resetvalue
= cpu
->id_aa64afr1
},
4685 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4686 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
4687 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4689 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4690 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
4691 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4693 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4694 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4695 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4696 .resetvalue
= cpu
->id_aa64isar0
},
4697 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4698 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4699 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4700 .resetvalue
= cpu
->id_aa64isar1
},
4701 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4702 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
4703 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4705 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4706 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
4707 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4709 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4710 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
4711 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4713 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4714 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
4715 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4717 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4718 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
4719 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4721 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4722 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
4723 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4725 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4726 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4727 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4728 .resetvalue
= cpu
->id_aa64mmfr0
},
4729 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4730 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4731 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4732 .resetvalue
= cpu
->id_aa64mmfr1
},
4733 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4734 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
4735 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4737 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4738 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
4739 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4741 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4742 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
4743 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4745 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4746 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
4747 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4749 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4750 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
4751 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4753 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4754 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
4755 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4757 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4758 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
4759 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4760 .resetvalue
= cpu
->mvfr0
},
4761 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4762 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
4763 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4764 .resetvalue
= cpu
->mvfr1
},
4765 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
4766 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
4767 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4768 .resetvalue
= cpu
->mvfr2
},
4769 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4770 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
4771 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4773 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4774 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
4775 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4777 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4778 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
4779 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4781 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4782 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
4783 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4785 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4786 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
4787 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4789 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
4790 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
4791 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4792 .resetvalue
= cpu
->pmceid0
},
4793 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
4794 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
4795 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4796 .resetvalue
= cpu
->pmceid0
},
4797 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
4798 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
4799 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4800 .resetvalue
= cpu
->pmceid1
},
4801 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
4802 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
4803 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4804 .resetvalue
= cpu
->pmceid1
},
4807 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4808 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
4809 !arm_feature(env
, ARM_FEATURE_EL2
)) {
4810 ARMCPRegInfo rvbar
= {
4811 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4812 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4813 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
4815 define_one_arm_cp_reg(cpu
, &rvbar
);
4817 define_arm_cp_regs(cpu
, v8_idregs
);
4818 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
4820 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4821 uint64_t vmpidr_def
= mpidr_read_val(env
);
4822 ARMCPRegInfo vpidr_regs
[] = {
4823 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
4824 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4825 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4826 .resetvalue
= cpu
->midr
,
4827 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4828 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4829 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4830 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
4831 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4832 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
4833 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4834 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4835 .resetvalue
= vmpidr_def
,
4836 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4837 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4838 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4840 .resetvalue
= vmpidr_def
,
4841 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4844 define_arm_cp_regs(cpu
, vpidr_regs
);
4845 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
4846 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4847 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
4848 ARMCPRegInfo rvbar
= {
4849 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
4850 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
4851 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
4853 define_one_arm_cp_reg(cpu
, &rvbar
);
4856 /* If EL2 is missing but higher ELs are enabled, we need to
4857 * register the no_el2 reginfos.
4859 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4860 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4861 * of MIDR_EL1 and MPIDR_EL1.
4863 ARMCPRegInfo vpidr_regs
[] = {
4864 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4865 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4866 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4867 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
4868 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4869 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4870 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4871 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4872 .type
= ARM_CP_NO_RAW
,
4873 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
4876 define_arm_cp_regs(cpu
, vpidr_regs
);
4877 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
4880 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4881 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
4882 ARMCPRegInfo el3_regs
[] = {
4883 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4884 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
4885 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
4886 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
4889 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4890 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
4891 .resetvalue
= cpu
->reset_sctlr
},
4895 define_arm_cp_regs(cpu
, el3_regs
);
4897 /* The behaviour of NSACR is sufficiently various that we don't
4898 * try to describe it in a single reginfo:
4899 * if EL3 is 64 bit, then trap to EL3 from S EL1,
4900 * reads as constant 0xc00 from NS EL1 and NS EL2
4901 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4902 * if v7 without EL3, register doesn't exist
4903 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4905 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4906 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4907 ARMCPRegInfo nsacr
= {
4908 .name
= "NSACR", .type
= ARM_CP_CONST
,
4909 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4910 .access
= PL1_RW
, .accessfn
= nsacr_access
,
4913 define_one_arm_cp_reg(cpu
, &nsacr
);
4915 ARMCPRegInfo nsacr
= {
4917 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4918 .access
= PL3_RW
| PL1_R
,
4920 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
4922 define_one_arm_cp_reg(cpu
, &nsacr
);
4925 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4926 ARMCPRegInfo nsacr
= {
4927 .name
= "NSACR", .type
= ARM_CP_CONST
,
4928 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4932 define_one_arm_cp_reg(cpu
, &nsacr
);
4936 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
4937 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4938 /* PMSAv6 not implemented */
4939 assert(arm_feature(env
, ARM_FEATURE_V7
));
4940 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4941 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
4943 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
4946 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4947 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
4949 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
4950 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
4952 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
4953 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
4955 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
4956 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
4958 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
4959 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
4961 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
4962 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
4964 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
4965 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
4967 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
4968 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
4970 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
4971 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
4973 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
4974 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
4976 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
4977 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
4979 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4980 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
4982 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4983 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4984 * be read-only (ie write causes UNDEF exception).
4987 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
4988 /* Pre-v8 MIDR space.
4989 * Note that the MIDR isn't a simple constant register because
4990 * of the TI925 behaviour where writes to another register can
4991 * cause the MIDR value to change.
4993 * Unimplemented registers in the c15 0 0 0 space default to
4994 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4995 * and friends override accordingly.
4998 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
4999 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5000 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5001 .readfn
= midr_read
,
5002 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5003 .type
= ARM_CP_OVERRIDE
},
5004 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5006 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5007 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5009 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5010 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5012 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5013 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5015 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5016 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5018 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5019 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5022 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5023 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5024 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5025 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5026 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5027 .readfn
= midr_read
},
5028 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5029 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5030 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5031 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5032 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5033 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5034 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5035 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5036 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5037 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5040 ARMCPRegInfo id_cp_reginfo
[] = {
5041 /* These are common to v8 and pre-v8 */
5043 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5044 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5045 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5046 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5047 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5048 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5049 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5051 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5052 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5055 /* TLBTR is specific to VMSA */
5056 ARMCPRegInfo id_tlbtr_reginfo
= {
5058 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5059 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5061 /* MPUIR is specific to PMSA V6+ */
5062 ARMCPRegInfo id_mpuir_reginfo
= {
5064 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5065 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5066 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5068 ARMCPRegInfo crn0_wi_reginfo
= {
5069 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5070 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5071 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5073 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5074 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5076 /* Register the blanket "writes ignored" value first to cover the
5077 * whole space. Then update the specific ID registers to allow write
5078 * access, so that they ignore writes rather than causing them to
5081 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5082 for (r
= id_pre_v8_midr_cp_reginfo
;
5083 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5086 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5089 id_tlbtr_reginfo
.access
= PL1_RW
;
5090 id_tlbtr_reginfo
.access
= PL1_RW
;
5092 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5093 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5095 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5097 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5098 if (!arm_feature(env
, ARM_FEATURE_MPU
)) {
5099 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5100 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5101 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5105 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5106 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5109 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5110 ARMCPRegInfo auxcr_reginfo
[] = {
5111 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5112 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5113 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5114 .resetvalue
= cpu
->reset_auxcr
},
5115 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5116 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5117 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5119 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5120 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5121 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5125 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5128 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5129 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5130 /* 32 bit view is [31:18] 0...0 [43:32]. */
5131 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5132 | extract64(cpu
->reset_cbar
, 32, 12);
5133 ARMCPRegInfo cbar_reginfo
[] = {
5135 .type
= ARM_CP_CONST
,
5136 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5137 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5138 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5139 .type
= ARM_CP_CONST
,
5140 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5141 .access
= PL1_R
, .resetvalue
= cbar32
},
5144 /* We don't implement a r/w 64 bit CBAR currently */
5145 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5146 define_arm_cp_regs(cpu
, cbar_reginfo
);
5148 ARMCPRegInfo cbar
= {
5150 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5151 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5152 .fieldoffset
= offsetof(CPUARMState
,
5153 cp15
.c15_config_base_address
)
5155 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5156 cbar
.access
= PL1_R
;
5157 cbar
.fieldoffset
= 0;
5158 cbar
.type
= ARM_CP_CONST
;
5160 define_one_arm_cp_reg(cpu
, &cbar
);
5164 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5165 ARMCPRegInfo vbar_cp_reginfo
[] = {
5166 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5167 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5168 .access
= PL1_RW
, .writefn
= vbar_write
,
5169 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5170 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5174 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5177 /* Generic registers whose values depend on the implementation */
5179 ARMCPRegInfo sctlr
= {
5180 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5181 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5183 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5184 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5185 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5186 .raw_writefn
= raw_write
,
5188 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5189 /* Normally we would always end the TB on an SCTLR write, but Linux
5190 * arch/arm/mach-pxa/sleep.S expects two instructions following
5191 * an MMU enable to execute from cache. Imitate this behaviour.
5193 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5195 define_one_arm_cp_reg(cpu
, &sctlr
);
5199 ARMCPU
*cpu_arm_init(const char *cpu_model
)
5201 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
5204 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5206 CPUState
*cs
= CPU(cpu
);
5207 CPUARMState
*env
= &cpu
->env
;
5209 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5210 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5211 aarch64_fpu_gdb_set_reg
,
5212 34, "aarch64-fpu.xml", 0);
5213 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5214 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5215 51, "arm-neon.xml", 0);
5216 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5217 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5218 35, "arm-vfp3.xml", 0);
5219 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5220 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5221 19, "arm-vfp.xml", 0);
5225 /* Sort alphabetically by type name, except for "any". */
5226 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5228 ObjectClass
*class_a
= (ObjectClass
*)a
;
5229 ObjectClass
*class_b
= (ObjectClass
*)b
;
5230 const char *name_a
, *name_b
;
5232 name_a
= object_class_get_name(class_a
);
5233 name_b
= object_class_get_name(class_b
);
5234 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5236 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5239 return strcmp(name_a
, name_b
);
5243 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5245 ObjectClass
*oc
= data
;
5246 CPUListState
*s
= user_data
;
5247 const char *typename
;
5250 typename
= object_class_get_name(oc
);
5251 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5252 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5257 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5261 .cpu_fprintf
= cpu_fprintf
,
5265 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5266 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5267 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5268 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5271 /* The 'host' CPU type is dynamically registered only if KVM is
5272 * enabled, so we have to special-case it here:
5274 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
5278 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5280 ObjectClass
*oc
= data
;
5281 CpuDefinitionInfoList
**cpu_list
= user_data
;
5282 CpuDefinitionInfoList
*entry
;
5283 CpuDefinitionInfo
*info
;
5284 const char *typename
;
5286 typename
= object_class_get_name(oc
);
5287 info
= g_malloc0(sizeof(*info
));
5288 info
->name
= g_strndup(typename
,
5289 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5290 info
->q_typename
= g_strdup(typename
);
5292 entry
= g_malloc0(sizeof(*entry
));
5293 entry
->value
= info
;
5294 entry
->next
= *cpu_list
;
5298 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5300 CpuDefinitionInfoList
*cpu_list
= NULL
;
5303 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5304 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5310 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5311 void *opaque
, int state
, int secstate
,
5312 int crm
, int opc1
, int opc2
)
5314 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5315 * add a single reginfo struct to the hash table.
5317 uint32_t *key
= g_new(uint32_t, 1);
5318 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5319 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5320 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5322 /* Reset the secure state to the specific incoming state. This is
5323 * necessary as the register may have been defined with both states.
5325 r2
->secure
= secstate
;
5327 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5328 /* Register is banked (using both entries in array).
5329 * Overwriting fieldoffset as the array is only used to define
5330 * banked registers but later only fieldoffset is used.
5332 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5335 if (state
== ARM_CP_STATE_AA32
) {
5336 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5337 /* If the register is banked then we don't need to migrate or
5338 * reset the 32-bit instance in certain cases:
5340 * 1) If the register has both 32-bit and 64-bit instances then we
5341 * can count on the 64-bit instance taking care of the
5343 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5344 * taking care of the secure bank. This requires that separate
5345 * 32 and 64-bit definitions are provided.
5347 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5348 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5349 r2
->type
|= ARM_CP_ALIAS
;
5351 } else if ((secstate
!= r
->secure
) && !ns
) {
5352 /* The register is not banked so we only want to allow migration of
5353 * the non-secure instance.
5355 r2
->type
|= ARM_CP_ALIAS
;
5358 if (r
->state
== ARM_CP_STATE_BOTH
) {
5359 /* We assume it is a cp15 register if the .cp field is left unset.
5365 #ifdef HOST_WORDS_BIGENDIAN
5366 if (r2
->fieldoffset
) {
5367 r2
->fieldoffset
+= sizeof(uint32_t);
5372 if (state
== ARM_CP_STATE_AA64
) {
5373 /* To allow abbreviation of ARMCPRegInfo
5374 * definitions, we treat cp == 0 as equivalent to
5375 * the value for "standard guest-visible sysreg".
5376 * STATE_BOTH definitions are also always "standard
5377 * sysreg" in their AArch64 view (the .cp value may
5378 * be non-zero for the benefit of the AArch32 view).
5380 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5381 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5383 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5384 r2
->opc0
, opc1
, opc2
);
5386 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5389 r2
->opaque
= opaque
;
5391 /* reginfo passed to helpers is correct for the actual access,
5392 * and is never ARM_CP_STATE_BOTH:
5395 /* Make sure reginfo passed to helpers for wildcarded regs
5396 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5401 /* By convention, for wildcarded registers only the first
5402 * entry is used for migration; the others are marked as
5403 * ALIAS so we don't try to transfer the register
5404 * multiple times. Special registers (ie NOP/WFI) are
5405 * never migratable and not even raw-accessible.
5407 if ((r
->type
& ARM_CP_SPECIAL
)) {
5408 r2
->type
|= ARM_CP_NO_RAW
;
5410 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5411 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5412 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5413 r2
->type
|= ARM_CP_ALIAS
;
5416 /* Check that raw accesses are either forbidden or handled. Note that
5417 * we can't assert this earlier because the setup of fieldoffset for
5418 * banked registers has to be done first.
5420 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5421 assert(!raw_accessors_invalid(r2
));
5424 /* Overriding of an existing definition must be explicitly
5427 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5428 ARMCPRegInfo
*oldreg
;
5429 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5430 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5431 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5432 "crn=%d crm=%d opc1=%d opc2=%d, "
5433 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5434 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5435 oldreg
->name
, r2
->name
);
5436 g_assert_not_reached();
5439 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5443 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5444 const ARMCPRegInfo
*r
, void *opaque
)
5446 /* Define implementations of coprocessor registers.
5447 * We store these in a hashtable because typically
5448 * there are less than 150 registers in a space which
5449 * is 16*16*16*8*8 = 262144 in size.
5450 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5451 * If a register is defined twice then the second definition is
5452 * used, so this can be used to define some generic registers and
5453 * then override them with implementation specific variations.
5454 * At least one of the original and the second definition should
5455 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5456 * against accidental use.
5458 * The state field defines whether the register is to be
5459 * visible in the AArch32 or AArch64 execution state. If the
5460 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5461 * reginfo structure for the AArch32 view, which sees the lower
5462 * 32 bits of the 64 bit register.
5464 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5465 * be wildcarded. AArch64 registers are always considered to be 64
5466 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5467 * the register, if any.
5469 int crm
, opc1
, opc2
, state
;
5470 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5471 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5472 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5473 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5474 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5475 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5476 /* 64 bit registers have only CRm and Opc1 fields */
5477 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5478 /* op0 only exists in the AArch64 encodings */
5479 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5480 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5481 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5482 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5483 * encodes a minimum access level for the register. We roll this
5484 * runtime check into our general permission check code, so check
5485 * here that the reginfo's specified permissions are strict enough
5486 * to encompass the generic architectural permission check.
5488 if (r
->state
!= ARM_CP_STATE_AA32
) {
5491 case 0: case 1: case 2:
5504 /* unallocated encoding, so not possible */
5512 /* min_EL EL1, secure mode only (we don't check the latter) */
5516 /* broken reginfo with out-of-range opc1 */
5520 /* assert our permissions are not too lax (stricter is fine) */
5521 assert((r
->access
& ~mask
) == 0);
5524 /* Check that the register definition has enough info to handle
5525 * reads and writes if they are permitted.
5527 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5528 if (r
->access
& PL3_R
) {
5529 assert((r
->fieldoffset
||
5530 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5533 if (r
->access
& PL3_W
) {
5534 assert((r
->fieldoffset
||
5535 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5539 /* Bad type field probably means missing sentinel at end of reg list */
5540 assert(cptype_valid(r
->type
));
5541 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5542 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5543 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5544 for (state
= ARM_CP_STATE_AA32
;
5545 state
<= ARM_CP_STATE_AA64
; state
++) {
5546 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5549 if (state
== ARM_CP_STATE_AA32
) {
5550 /* Under AArch32 CP registers can be common
5551 * (same for secure and non-secure world) or banked.
5553 switch (r
->secure
) {
5554 case ARM_CP_SECSTATE_S
:
5555 case ARM_CP_SECSTATE_NS
:
5556 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5557 r
->secure
, crm
, opc1
, opc2
);
5560 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5563 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5569 /* AArch64 registers get mapped to non-secure instance
5571 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5581 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
5582 const ARMCPRegInfo
*regs
, void *opaque
)
5584 /* Define a whole list of registers */
5585 const ARMCPRegInfo
*r
;
5586 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5587 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
5591 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
5593 return g_hash_table_lookup(cpregs
, &encoded_cp
);
5596 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5599 /* Helper coprocessor write function for write-ignore registers */
5602 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5604 /* Helper coprocessor write function for read-as-zero registers */
5608 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
5610 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5613 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
5615 /* Return true if it is not valid for us to switch to
5616 * this CPU mode (ie all the UNPREDICTABLE cases in
5617 * the ARM ARM CPSRWriteByInstr pseudocode).
5620 /* Changes to or from Hyp via MSR and CPS are illegal. */
5621 if (write_type
== CPSRWriteByInstr
&&
5622 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
5623 mode
== ARM_CPU_MODE_HYP
)) {
5628 case ARM_CPU_MODE_USR
:
5630 case ARM_CPU_MODE_SYS
:
5631 case ARM_CPU_MODE_SVC
:
5632 case ARM_CPU_MODE_ABT
:
5633 case ARM_CPU_MODE_UND
:
5634 case ARM_CPU_MODE_IRQ
:
5635 case ARM_CPU_MODE_FIQ
:
5636 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5637 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5639 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5640 * and CPS are treated as illegal mode changes.
5642 if (write_type
== CPSRWriteByInstr
&&
5643 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
5644 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
5645 !arm_is_secure_below_el3(env
)) {
5649 case ARM_CPU_MODE_HYP
:
5650 return !arm_feature(env
, ARM_FEATURE_EL2
)
5651 || arm_current_el(env
) < 2 || arm_is_secure(env
);
5652 case ARM_CPU_MODE_MON
:
5653 return arm_current_el(env
) < 3;
5659 uint32_t cpsr_read(CPUARMState
*env
)
5662 ZF
= (env
->ZF
== 0);
5663 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
5664 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
5665 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
5666 | ((env
->condexec_bits
& 0xfc) << 8)
5667 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
5670 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
5671 CPSRWriteType write_type
)
5673 uint32_t changed_daif
;
5675 if (mask
& CPSR_NZCV
) {
5676 env
->ZF
= (~val
) & CPSR_Z
;
5678 env
->CF
= (val
>> 29) & 1;
5679 env
->VF
= (val
<< 3) & 0x80000000;
5682 env
->QF
= ((val
& CPSR_Q
) != 0);
5684 env
->thumb
= ((val
& CPSR_T
) != 0);
5685 if (mask
& CPSR_IT_0_1
) {
5686 env
->condexec_bits
&= ~3;
5687 env
->condexec_bits
|= (val
>> 25) & 3;
5689 if (mask
& CPSR_IT_2_7
) {
5690 env
->condexec_bits
&= 3;
5691 env
->condexec_bits
|= (val
>> 8) & 0xfc;
5693 if (mask
& CPSR_GE
) {
5694 env
->GE
= (val
>> 16) & 0xf;
5697 /* In a V7 implementation that includes the security extensions but does
5698 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5699 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5700 * bits respectively.
5702 * In a V8 implementation, it is permitted for privileged software to
5703 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5705 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
5706 arm_feature(env
, ARM_FEATURE_EL3
) &&
5707 !arm_feature(env
, ARM_FEATURE_EL2
) &&
5708 !arm_is_secure(env
)) {
5710 changed_daif
= (env
->daif
^ val
) & mask
;
5712 if (changed_daif
& CPSR_A
) {
5713 /* Check to see if we are allowed to change the masking of async
5714 * abort exceptions from a non-secure state.
5716 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
5717 qemu_log_mask(LOG_GUEST_ERROR
,
5718 "Ignoring attempt to switch CPSR_A flag from "
5719 "non-secure world with SCR.AW bit clear\n");
5724 if (changed_daif
& CPSR_F
) {
5725 /* Check to see if we are allowed to change the masking of FIQ
5726 * exceptions from a non-secure state.
5728 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
5729 qemu_log_mask(LOG_GUEST_ERROR
,
5730 "Ignoring attempt to switch CPSR_F flag from "
5731 "non-secure world with SCR.FW bit clear\n");
5735 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5736 * If this bit is set software is not allowed to mask
5737 * FIQs, but is allowed to set CPSR_F to 0.
5739 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
5741 qemu_log_mask(LOG_GUEST_ERROR
,
5742 "Ignoring attempt to enable CPSR_F flag "
5743 "(non-maskable FIQ [NMFI] support enabled)\n");
5749 env
->daif
&= ~(CPSR_AIF
& mask
);
5750 env
->daif
|= val
& CPSR_AIF
& mask
;
5752 if (write_type
!= CPSRWriteRaw
&&
5753 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
5754 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
5755 /* Note that we can only get here in USR mode if this is a
5756 * gdb stub write; for this case we follow the architectural
5757 * behaviour for guest writes in USR mode of ignoring an attempt
5758 * to switch mode. (Those are caught by translate.c for writes
5759 * triggered by guest instructions.)
5762 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
5763 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5764 * v7, and has defined behaviour in v8:
5765 * + leave CPSR.M untouched
5766 * + allow changes to the other CPSR fields
5768 * For user changes via the GDB stub, we don't set PSTATE.IL,
5769 * as this would be unnecessarily harsh for a user error.
5772 if (write_type
!= CPSRWriteByGDBStub
&&
5773 arm_feature(env
, ARM_FEATURE_V8
)) {
5778 switch_mode(env
, val
& CPSR_M
);
5781 mask
&= ~CACHED_CPSR_BITS
;
5782 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
5785 /* Sign/zero extend */
5786 uint32_t HELPER(sxtb16
)(uint32_t x
)
5789 res
= (uint16_t)(int8_t)x
;
5790 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
5794 uint32_t HELPER(uxtb16
)(uint32_t x
)
5797 res
= (uint16_t)(uint8_t)x
;
5798 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
5802 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
5806 if (num
== INT_MIN
&& den
== -1)
5811 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
5818 uint32_t HELPER(rbit
)(uint32_t x
)
5823 #if defined(CONFIG_USER_ONLY)
5825 /* These should probably raise undefined insn exceptions. */
5826 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
5828 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5830 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
5833 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5835 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5837 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
5841 void switch_mode(CPUARMState
*env
, int mode
)
5843 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5845 if (mode
!= ARM_CPU_MODE_USR
) {
5846 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
5850 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5851 uint32_t cur_el
, bool secure
)
5856 void aarch64_sync_64_to_32(CPUARMState
*env
)
5858 g_assert_not_reached();
5863 void switch_mode(CPUARMState
*env
, int mode
)
5868 old_mode
= env
->uncached_cpsr
& CPSR_M
;
5869 if (mode
== old_mode
)
5872 if (old_mode
== ARM_CPU_MODE_FIQ
) {
5873 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5874 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
5875 } else if (mode
== ARM_CPU_MODE_FIQ
) {
5876 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5877 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
5880 i
= bank_number(old_mode
);
5881 env
->banked_r13
[i
] = env
->regs
[13];
5882 env
->banked_r14
[i
] = env
->regs
[14];
5883 env
->banked_spsr
[i
] = env
->spsr
;
5885 i
= bank_number(mode
);
5886 env
->regs
[13] = env
->banked_r13
[i
];
5887 env
->regs
[14] = env
->banked_r14
[i
];
5888 env
->spsr
= env
->banked_spsr
[i
];
5891 /* Physical Interrupt Target EL Lookup Table
5893 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5895 * The below multi-dimensional table is used for looking up the target
5896 * exception level given numerous condition criteria. Specifically, the
5897 * target EL is based on SCR and HCR routing controls as well as the
5898 * currently executing EL and secure state.
5901 * target_el_table[2][2][2][2][2][4]
5902 * | | | | | +--- Current EL
5903 * | | | | +------ Non-secure(0)/Secure(1)
5904 * | | | +--------- HCR mask override
5905 * | | +------------ SCR exec state control
5906 * | +--------------- SCR mask override
5907 * +------------------ 32-bit(0)/64-bit(1) EL3
5909 * The table values are as such:
5913 * The ARM ARM target EL table includes entries indicating that an "exception
5914 * is not taken". The two cases where this is applicable are:
5915 * 1) An exception is taken from EL3 but the SCR does not have the exception
5917 * 2) An exception is taken from EL2 but the HCR does not have the exception
5919 * In these two cases, the below table contain a target of EL1. This value is
5920 * returned as it is expected that the consumer of the table data will check
5921 * for "target EL >= current EL" to ensure the exception is not taken.
5925 * BIT IRQ IMO Non-secure Secure
5926 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5928 static const int8_t target_el_table
[2][2][2][2][2][4] = {
5929 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5930 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5931 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5932 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5933 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5934 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
5935 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5936 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
5937 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
5938 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
5939 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
5940 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
5941 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5942 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
5943 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5944 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
5948 * Determine the target EL for physical exceptions
5950 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5951 uint32_t cur_el
, bool secure
)
5953 CPUARMState
*env
= cs
->env_ptr
;
5958 /* Is the highest EL AArch64? */
5959 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
5961 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5962 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
5964 /* Either EL2 is the highest EL (and so the EL2 register width
5965 * is given by is64); or there is no EL2 or EL3, in which case
5966 * the value of 'rw' does not affect the table lookup anyway.
5973 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
5974 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
5977 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
5978 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
5981 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
5982 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
5986 /* If HCR.TGE is set then HCR is treated as being 1 */
5987 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
5989 /* Perform a table-lookup for the target EL given the current state */
5990 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
5992 assert(target_el
> 0);
5997 static void v7m_push(CPUARMState
*env
, uint32_t val
)
5999 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6002 stl_phys(cs
->as
, env
->regs
[13], val
);
6005 static uint32_t v7m_pop(CPUARMState
*env
)
6007 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6010 val
= ldl_phys(cs
->as
, env
->regs
[13]);
6015 /* Switch to V7M main or process stack pointer. */
6016 static void switch_v7m_sp(CPUARMState
*env
, bool new_spsel
)
6019 bool old_spsel
= env
->v7m
.control
& R_V7M_CONTROL_SPSEL_MASK
;
6021 if (old_spsel
!= new_spsel
) {
6022 tmp
= env
->v7m
.other_sp
;
6023 env
->v7m
.other_sp
= env
->regs
[13];
6024 env
->regs
[13] = tmp
;
6026 env
->v7m
.control
= deposit32(env
->v7m
.control
,
6027 R_V7M_CONTROL_SPSEL_SHIFT
,
6028 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6032 static void do_v7m_exception_exit(CPUARMState
*env
)
6037 type
= env
->regs
[15];
6038 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
6039 /* Auto-clear FAULTMASK on return from other than NMI */
6040 env
->daif
&= ~PSTATE_F
;
6042 if (env
->v7m
.exception
!= 0) {
6043 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
6046 /* Switch to the target stack. */
6047 switch_v7m_sp(env
, (type
& 4) != 0);
6048 /* Pop registers. */
6049 env
->regs
[0] = v7m_pop(env
);
6050 env
->regs
[1] = v7m_pop(env
);
6051 env
->regs
[2] = v7m_pop(env
);
6052 env
->regs
[3] = v7m_pop(env
);
6053 env
->regs
[12] = v7m_pop(env
);
6054 env
->regs
[14] = v7m_pop(env
);
6055 env
->regs
[15] = v7m_pop(env
);
6056 if (env
->regs
[15] & 1) {
6057 qemu_log_mask(LOG_GUEST_ERROR
,
6058 "M profile return from interrupt with misaligned "
6059 "PC is UNPREDICTABLE\n");
6060 /* Actual hardware seems to ignore the lsbit, and there are several
6061 * RTOSes out there which incorrectly assume the r15 in the stack
6062 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
6064 env
->regs
[15] &= ~1U;
6066 xpsr
= v7m_pop(env
);
6067 xpsr_write(env
, xpsr
, 0xfffffdff);
6068 /* Undo stack alignment. */
6071 /* ??? The exception return type specifies Thread/Handler mode. However
6072 this is also implied by the xPSR value. Not sure what to do
6073 if there is a mismatch. */
6074 /* ??? Likewise for mismatches between the CONTROL register and the stack
6078 static void arm_log_exception(int idx
)
6080 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
6081 const char *exc
= NULL
;
6083 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
6084 exc
= excnames
[idx
];
6089 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
6093 static uint32_t arm_v7m_load_vector(ARMCPU
*cpu
)
6096 CPUState
*cs
= CPU(cpu
);
6097 CPUARMState
*env
= &cpu
->env
;
6099 hwaddr vec
= env
->v7m
.vecbase
+ env
->v7m
.exception
* 4;
6102 addr
= address_space_ldl(cs
->as
, vec
,
6103 MEMTXATTRS_UNSPECIFIED
, &result
);
6104 if (result
!= MEMTX_OK
) {
6105 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
6106 * which would then be immediately followed by our failing to load
6107 * the entry vector for that HardFault, which is a Lockup case.
6108 * Since we don't model Lockup, we just report this guest error
6111 cpu_abort(cs
, "Failed to read from exception vector table "
6112 "entry %08x\n", (unsigned)vec
);
6117 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
6119 ARMCPU
*cpu
= ARM_CPU(cs
);
6120 CPUARMState
*env
= &cpu
->env
;
6121 uint32_t xpsr
= xpsr_read(env
);
6125 arm_log_exception(cs
->exception_index
);
6128 if (env
->v7m
.control
& R_V7M_CONTROL_SPSEL_MASK
) {
6131 if (env
->v7m
.exception
== 0)
6134 /* For exceptions we just mark as pending on the NVIC, and let that
6136 /* TODO: Need to escalate if the current priority is higher than the
6137 one we're raising. */
6138 switch (cs
->exception_index
) {
6140 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6141 env
->v7m
.cfsr
|= R_V7M_CFSR_UNDEFINSTR_MASK
;
6144 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6145 env
->v7m
.cfsr
|= R_V7M_CFSR_NOCP_MASK
;
6148 /* The PC already points to the next instruction. */
6149 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
6151 case EXCP_PREFETCH_ABORT
:
6152 case EXCP_DATA_ABORT
:
6153 /* TODO: if we implemented the MPU registers, this is where we
6154 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
6156 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
6159 if (semihosting_enabled()) {
6161 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
6164 qemu_log_mask(CPU_LOG_INT
,
6165 "...handling as semihosting call 0x%x\n",
6167 env
->regs
[0] = do_arm_semihosting(env
);
6171 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
6174 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
6176 case EXCP_EXCEPTION_EXIT
:
6177 do_v7m_exception_exit(env
);
6180 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
6181 return; /* Never happens. Keep compiler happy. */
6184 /* Align stack pointer if the guest wants that */
6185 if ((env
->regs
[13] & 4) && (env
->v7m
.ccr
& R_V7M_CCR_STKALIGN_MASK
)) {
6189 /* Switch to the handler mode. */
6190 v7m_push(env
, xpsr
);
6191 v7m_push(env
, env
->regs
[15]);
6192 v7m_push(env
, env
->regs
[14]);
6193 v7m_push(env
, env
->regs
[12]);
6194 v7m_push(env
, env
->regs
[3]);
6195 v7m_push(env
, env
->regs
[2]);
6196 v7m_push(env
, env
->regs
[1]);
6197 v7m_push(env
, env
->regs
[0]);
6198 switch_v7m_sp(env
, 0);
6200 env
->condexec_bits
= 0;
6202 addr
= arm_v7m_load_vector(cpu
);
6203 env
->regs
[15] = addr
& 0xfffffffe;
6204 env
->thumb
= addr
& 1;
6207 /* Function used to synchronize QEMU's AArch64 register set with AArch32
6208 * register set. This is necessary when switching between AArch32 and AArch64
6211 void aarch64_sync_32_to_64(CPUARMState
*env
)
6214 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
6216 /* We can blanket copy R[0:7] to X[0:7] */
6217 for (i
= 0; i
< 8; i
++) {
6218 env
->xregs
[i
] = env
->regs
[i
];
6221 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
6222 * Otherwise, they come from the banked user regs.
6224 if (mode
== ARM_CPU_MODE_FIQ
) {
6225 for (i
= 8; i
< 13; i
++) {
6226 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
6229 for (i
= 8; i
< 13; i
++) {
6230 env
->xregs
[i
] = env
->regs
[i
];
6234 /* Registers x13-x23 are the various mode SP and FP registers. Registers
6235 * r13 and r14 are only copied if we are in that mode, otherwise we copy
6236 * from the mode banked register.
6238 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
6239 env
->xregs
[13] = env
->regs
[13];
6240 env
->xregs
[14] = env
->regs
[14];
6242 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
6243 /* HYP is an exception in that it is copied from r14 */
6244 if (mode
== ARM_CPU_MODE_HYP
) {
6245 env
->xregs
[14] = env
->regs
[14];
6247 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
6251 if (mode
== ARM_CPU_MODE_HYP
) {
6252 env
->xregs
[15] = env
->regs
[13];
6254 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
6257 if (mode
== ARM_CPU_MODE_IRQ
) {
6258 env
->xregs
[16] = env
->regs
[14];
6259 env
->xregs
[17] = env
->regs
[13];
6261 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
6262 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
6265 if (mode
== ARM_CPU_MODE_SVC
) {
6266 env
->xregs
[18] = env
->regs
[14];
6267 env
->xregs
[19] = env
->regs
[13];
6269 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
6270 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
6273 if (mode
== ARM_CPU_MODE_ABT
) {
6274 env
->xregs
[20] = env
->regs
[14];
6275 env
->xregs
[21] = env
->regs
[13];
6277 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
6278 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
6281 if (mode
== ARM_CPU_MODE_UND
) {
6282 env
->xregs
[22] = env
->regs
[14];
6283 env
->xregs
[23] = env
->regs
[13];
6285 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
6286 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
6289 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
6290 * mode, then we can copy from r8-r14. Otherwise, we copy from the
6291 * FIQ bank for r8-r14.
6293 if (mode
== ARM_CPU_MODE_FIQ
) {
6294 for (i
= 24; i
< 31; i
++) {
6295 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
6298 for (i
= 24; i
< 29; i
++) {
6299 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
6301 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
6302 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
6305 env
->pc
= env
->regs
[15];
6308 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6309 * register set. This is necessary when switching between AArch32 and AArch64
6312 void aarch64_sync_64_to_32(CPUARMState
*env
)
6315 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
6317 /* We can blanket copy X[0:7] to R[0:7] */
6318 for (i
= 0; i
< 8; i
++) {
6319 env
->regs
[i
] = env
->xregs
[i
];
6322 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6323 * Otherwise, we copy x8-x12 into the banked user regs.
6325 if (mode
== ARM_CPU_MODE_FIQ
) {
6326 for (i
= 8; i
< 13; i
++) {
6327 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
6330 for (i
= 8; i
< 13; i
++) {
6331 env
->regs
[i
] = env
->xregs
[i
];
6335 /* Registers r13 & r14 depend on the current mode.
6336 * If we are in a given mode, we copy the corresponding x registers to r13
6337 * and r14. Otherwise, we copy the x register to the banked r13 and r14
6340 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
6341 env
->regs
[13] = env
->xregs
[13];
6342 env
->regs
[14] = env
->xregs
[14];
6344 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
6346 /* HYP is an exception in that it does not have its own banked r14 but
6347 * shares the USR r14
6349 if (mode
== ARM_CPU_MODE_HYP
) {
6350 env
->regs
[14] = env
->xregs
[14];
6352 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
6356 if (mode
== ARM_CPU_MODE_HYP
) {
6357 env
->regs
[13] = env
->xregs
[15];
6359 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
6362 if (mode
== ARM_CPU_MODE_IRQ
) {
6363 env
->regs
[14] = env
->xregs
[16];
6364 env
->regs
[13] = env
->xregs
[17];
6366 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
6367 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
6370 if (mode
== ARM_CPU_MODE_SVC
) {
6371 env
->regs
[14] = env
->xregs
[18];
6372 env
->regs
[13] = env
->xregs
[19];
6374 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
6375 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
6378 if (mode
== ARM_CPU_MODE_ABT
) {
6379 env
->regs
[14] = env
->xregs
[20];
6380 env
->regs
[13] = env
->xregs
[21];
6382 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
6383 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
6386 if (mode
== ARM_CPU_MODE_UND
) {
6387 env
->regs
[14] = env
->xregs
[22];
6388 env
->regs
[13] = env
->xregs
[23];
6390 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
6391 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
6394 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
6395 * mode, then we can copy to r8-r14. Otherwise, we copy to the
6396 * FIQ bank for r8-r14.
6398 if (mode
== ARM_CPU_MODE_FIQ
) {
6399 for (i
= 24; i
< 31; i
++) {
6400 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
6403 for (i
= 24; i
< 29; i
++) {
6404 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
6406 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
6407 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
6410 env
->regs
[15] = env
->pc
;
6413 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
6415 ARMCPU
*cpu
= ARM_CPU(cs
);
6416 CPUARMState
*env
= &cpu
->env
;
6423 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6424 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
6426 case EC_BREAKPOINT_SAME_EL
:
6430 case EC_WATCHPOINT_SAME_EL
:
6436 case EC_VECTORCATCH
:
6445 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
6448 /* TODO: Vectored interrupt controller. */
6449 switch (cs
->exception_index
) {
6451 new_mode
= ARM_CPU_MODE_UND
;
6460 new_mode
= ARM_CPU_MODE_SVC
;
6463 /* The PC already points to the next instruction. */
6467 env
->exception
.fsr
= 2;
6468 /* Fall through to prefetch abort. */
6469 case EXCP_PREFETCH_ABORT
:
6470 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
6471 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
6472 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
6473 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
6474 new_mode
= ARM_CPU_MODE_ABT
;
6476 mask
= CPSR_A
| CPSR_I
;
6479 case EXCP_DATA_ABORT
:
6480 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
6481 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
6482 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
6484 (uint32_t)env
->exception
.vaddress
);
6485 new_mode
= ARM_CPU_MODE_ABT
;
6487 mask
= CPSR_A
| CPSR_I
;
6491 new_mode
= ARM_CPU_MODE_IRQ
;
6493 /* Disable IRQ and imprecise data aborts. */
6494 mask
= CPSR_A
| CPSR_I
;
6496 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
6497 /* IRQ routed to monitor mode */
6498 new_mode
= ARM_CPU_MODE_MON
;
6503 new_mode
= ARM_CPU_MODE_FIQ
;
6505 /* Disable FIQ, IRQ and imprecise data aborts. */
6506 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
6507 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
6508 /* FIQ routed to monitor mode */
6509 new_mode
= ARM_CPU_MODE_MON
;
6514 new_mode
= ARM_CPU_MODE_IRQ
;
6516 /* Disable IRQ and imprecise data aborts. */
6517 mask
= CPSR_A
| CPSR_I
;
6521 new_mode
= ARM_CPU_MODE_FIQ
;
6523 /* Disable FIQ, IRQ and imprecise data aborts. */
6524 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
6528 new_mode
= ARM_CPU_MODE_MON
;
6530 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
6534 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
6535 return; /* Never happens. Keep compiler happy. */
6538 if (new_mode
== ARM_CPU_MODE_MON
) {
6539 addr
+= env
->cp15
.mvbar
;
6540 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
6541 /* High vectors. When enabled, base address cannot be remapped. */
6544 /* ARM v7 architectures provide a vector base address register to remap
6545 * the interrupt vector table.
6546 * This register is only followed in non-monitor mode, and is banked.
6547 * Note: only bits 31:5 are valid.
6549 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
6552 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
6553 env
->cp15
.scr_el3
&= ~SCR_NS
;
6556 switch_mode (env
, new_mode
);
6557 /* For exceptions taken to AArch32 we must clear the SS bit in both
6558 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6560 env
->uncached_cpsr
&= ~PSTATE_SS
;
6561 env
->spsr
= cpsr_read(env
);
6562 /* Clear IT bits. */
6563 env
->condexec_bits
= 0;
6564 /* Switch to the new mode, and to the correct instruction set. */
6565 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
6566 /* Set new mode endianness */
6567 env
->uncached_cpsr
&= ~CPSR_E
;
6568 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
6569 env
->uncached_cpsr
|= CPSR_E
;
6572 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6573 * and we should just guard the thumb mode on V4 */
6574 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
6575 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
6577 env
->regs
[14] = env
->regs
[15] + offset
;
6578 env
->regs
[15] = addr
;
6581 /* Handle exception entry to a target EL which is using AArch64 */
6582 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
6584 ARMCPU
*cpu
= ARM_CPU(cs
);
6585 CPUARMState
*env
= &cpu
->env
;
6586 unsigned int new_el
= env
->exception
.target_el
;
6587 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
6588 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
6590 if (arm_current_el(env
) < new_el
) {
6591 /* Entry vector offset depends on whether the implemented EL
6592 * immediately lower than the target level is using AArch32 or AArch64
6598 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
6601 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
6604 is_aa64
= is_a64(env
);
6607 g_assert_not_reached();
6615 } else if (pstate_read(env
) & PSTATE_SP
) {
6619 switch (cs
->exception_index
) {
6620 case EXCP_PREFETCH_ABORT
:
6621 case EXCP_DATA_ABORT
:
6622 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
6623 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
6624 env
->cp15
.far_el
[new_el
]);
6632 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
6643 qemu_log_mask(CPU_LOG_INT
,
6644 "...handling as semihosting call 0x%" PRIx64
"\n",
6646 env
->xregs
[0] = do_arm_semihosting(env
);
6649 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
6653 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
6654 aarch64_save_sp(env
, arm_current_el(env
));
6655 env
->elr_el
[new_el
] = env
->pc
;
6657 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
6658 env
->elr_el
[new_el
] = env
->regs
[15];
6660 aarch64_sync_32_to_64(env
);
6662 env
->condexec_bits
= 0;
6664 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
6665 env
->elr_el
[new_el
]);
6667 pstate_write(env
, PSTATE_DAIF
| new_mode
);
6669 aarch64_restore_sp(env
, new_el
);
6673 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
6674 new_el
, env
->pc
, pstate_read(env
));
6677 static inline bool check_for_semihosting(CPUState
*cs
)
6679 /* Check whether this exception is a semihosting call; if so
6680 * then handle it and return true; otherwise return false.
6682 ARMCPU
*cpu
= ARM_CPU(cs
);
6683 CPUARMState
*env
= &cpu
->env
;
6686 if (cs
->exception_index
== EXCP_SEMIHOST
) {
6687 /* This is always the 64-bit semihosting exception.
6688 * The "is this usermode" and "is semihosting enabled"
6689 * checks have been done at translate time.
6691 qemu_log_mask(CPU_LOG_INT
,
6692 "...handling as semihosting call 0x%" PRIx64
"\n",
6694 env
->xregs
[0] = do_arm_semihosting(env
);
6701 /* Only intercept calls from privileged modes, to provide some
6702 * semblance of security.
6704 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
6705 (!semihosting_enabled() ||
6706 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
6710 switch (cs
->exception_index
) {
6712 /* This is always a semihosting call; the "is this usermode"
6713 * and "is semihosting enabled" checks have been done at
6718 /* Check for semihosting interrupt. */
6720 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
6726 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
6728 if (imm
== 0x123456) {
6734 /* See if this is a semihosting syscall. */
6736 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
6748 qemu_log_mask(CPU_LOG_INT
,
6749 "...handling as semihosting call 0x%x\n",
6751 env
->regs
[0] = do_arm_semihosting(env
);
6756 /* Handle a CPU exception for A and R profile CPUs.
6757 * Do any appropriate logging, handle PSCI calls, and then hand off
6758 * to the AArch64-entry or AArch32-entry function depending on the
6759 * target exception level's register width.
6761 void arm_cpu_do_interrupt(CPUState
*cs
)
6763 ARMCPU
*cpu
= ARM_CPU(cs
);
6764 CPUARMState
*env
= &cpu
->env
;
6765 unsigned int new_el
= env
->exception
.target_el
;
6767 assert(!arm_feature(env
, ARM_FEATURE_M
));
6769 arm_log_exception(cs
->exception_index
);
6770 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
6772 if (qemu_loglevel_mask(CPU_LOG_INT
)
6773 && !excp_is_internal(cs
->exception_index
)) {
6774 qemu_log_mask(CPU_LOG_INT
, "...with ESR %x/0x%" PRIx32
"\n",
6775 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
6776 env
->exception
.syndrome
);
6779 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
6780 arm_handle_psci_call(cpu
);
6781 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
6785 /* Semihosting semantics depend on the register width of the
6786 * code that caused the exception, not the target exception level,
6787 * so must be handled here.
6789 if (check_for_semihosting(cs
)) {
6793 assert(!excp_is_internal(cs
->exception_index
));
6794 if (arm_el_is_aa64(env
, new_el
)) {
6795 arm_cpu_do_interrupt_aarch64(cs
);
6797 arm_cpu_do_interrupt_aarch32(cs
);
6800 /* Hooks may change global state so BQL should be held, also the
6801 * BQL needs to be held for any modification of
6802 * cs->interrupt_request.
6804 g_assert(qemu_mutex_iothread_locked());
6806 arm_call_el_change_hook(cpu
);
6808 if (!kvm_enabled()) {
6809 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
6813 /* Return the exception level which controls this address translation regime */
6814 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6817 case ARMMMUIdx_S2NS
:
6818 case ARMMMUIdx_S1E2
:
6820 case ARMMMUIdx_S1E3
:
6822 case ARMMMUIdx_S1SE0
:
6823 return arm_el_is_aa64(env
, 3) ? 1 : 3;
6824 case ARMMMUIdx_S1SE1
:
6825 case ARMMMUIdx_S1NSE0
:
6826 case ARMMMUIdx_S1NSE1
:
6829 g_assert_not_reached();
6833 /* Return true if this address translation regime is secure */
6834 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6837 case ARMMMUIdx_S12NSE0
:
6838 case ARMMMUIdx_S12NSE1
:
6839 case ARMMMUIdx_S1NSE0
:
6840 case ARMMMUIdx_S1NSE1
:
6841 case ARMMMUIdx_S1E2
:
6842 case ARMMMUIdx_S2NS
:
6844 case ARMMMUIdx_S1E3
:
6845 case ARMMMUIdx_S1SE0
:
6846 case ARMMMUIdx_S1SE1
:
6849 g_assert_not_reached();
6853 /* Return the SCTLR value which controls this address translation regime */
6854 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6856 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
6859 /* Return true if the specified stage of address translation is disabled */
6860 static inline bool regime_translation_disabled(CPUARMState
*env
,
6863 if (mmu_idx
== ARMMMUIdx_S2NS
) {
6864 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
6866 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
6869 static inline bool regime_translation_big_endian(CPUARMState
*env
,
6872 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
6875 /* Return the TCR controlling this translation regime */
6876 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6878 if (mmu_idx
== ARMMMUIdx_S2NS
) {
6879 return &env
->cp15
.vtcr_el2
;
6881 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
6884 /* Returns TBI0 value for current regime el */
6885 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6890 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
6891 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
6893 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
6894 mmu_idx
+= ARMMMUIdx_S1NSE0
;
6897 tcr
= regime_tcr(env
, mmu_idx
);
6898 el
= regime_el(env
, mmu_idx
);
6901 return extract64(tcr
->raw_tcr
, 20, 1);
6903 return extract64(tcr
->raw_tcr
, 37, 1);
6907 /* Returns TBI1 value for current regime el */
6908 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6913 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
6914 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
6916 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
6917 mmu_idx
+= ARMMMUIdx_S1NSE0
;
6920 tcr
= regime_tcr(env
, mmu_idx
);
6921 el
= regime_el(env
, mmu_idx
);
6926 return extract64(tcr
->raw_tcr
, 38, 1);
6930 /* Return the TTBR associated with this translation regime */
6931 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
6934 if (mmu_idx
== ARMMMUIdx_S2NS
) {
6935 return env
->cp15
.vttbr_el2
;
6938 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
6940 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
6944 /* Return true if the translation regime is using LPAE format page tables */
6945 static inline bool regime_using_lpae_format(CPUARMState
*env
,
6948 int el
= regime_el(env
, mmu_idx
);
6949 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
6952 if (arm_feature(env
, ARM_FEATURE_LPAE
)
6953 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
6959 /* Returns true if the stage 1 translation regime is using LPAE format page
6960 * tables. Used when raising alignment exceptions, whose FSR changes depending
6961 * on whether the long or short descriptor format is in use. */
6962 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6964 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
6965 mmu_idx
+= ARMMMUIdx_S1NSE0
;
6968 return regime_using_lpae_format(env
, mmu_idx
);
6971 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6974 case ARMMMUIdx_S1SE0
:
6975 case ARMMMUIdx_S1NSE0
:
6979 case ARMMMUIdx_S12NSE0
:
6980 case ARMMMUIdx_S12NSE1
:
6981 g_assert_not_reached();
6985 /* Translate section/page access permissions to page
6986 * R/W protection flags
6989 * @mmu_idx: MMU index indicating required translation regime
6990 * @ap: The 3-bit access permissions (AP[2:0])
6991 * @domain_prot: The 2-bit domain access permissions
6993 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
6994 int ap
, int domain_prot
)
6996 bool is_user
= regime_is_user(env
, mmu_idx
);
6998 if (domain_prot
== 3) {
6999 return PAGE_READ
| PAGE_WRITE
;
7004 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7007 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
7009 return is_user
? 0 : PAGE_READ
;
7016 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
7021 return PAGE_READ
| PAGE_WRITE
;
7024 return PAGE_READ
| PAGE_WRITE
;
7025 case 4: /* Reserved. */
7028 return is_user
? 0 : PAGE_READ
;
7032 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
7037 g_assert_not_reached();
7041 /* Translate section/page access permissions to page
7042 * R/W protection flags.
7044 * @ap: The 2-bit simple AP (AP[2:1])
7045 * @is_user: TRUE if accessing from PL0
7047 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
7051 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
7053 return PAGE_READ
| PAGE_WRITE
;
7055 return is_user
? 0 : PAGE_READ
;
7059 g_assert_not_reached();
7064 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
7066 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
7069 /* Translate S2 section/page access permissions to protection flags
7072 * @s2ap: The 2-bit stage2 access permissions (S2AP)
7073 * @xn: XN (execute-never) bit
7075 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
7086 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
7093 /* Translate section/page access permissions to protection flags
7096 * @mmu_idx: MMU index indicating required translation regime
7097 * @is_aa64: TRUE if AArch64
7098 * @ap: The 2-bit simple AP (AP[2:1])
7099 * @ns: NS (non-secure) bit
7100 * @xn: XN (execute-never) bit
7101 * @pxn: PXN (privileged execute-never) bit
7103 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
7104 int ap
, int ns
, int xn
, int pxn
)
7106 bool is_user
= regime_is_user(env
, mmu_idx
);
7107 int prot_rw
, user_rw
;
7111 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
7113 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
7117 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
7120 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
7124 /* TODO have_wxn should be replaced with
7125 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
7126 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
7127 * compatible processors have EL2, which is required for [U]WXN.
7129 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
7132 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
7136 switch (regime_el(env
, mmu_idx
)) {
7139 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
7146 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
7147 switch (regime_el(env
, mmu_idx
)) {
7151 xn
= xn
|| !(user_rw
& PAGE_READ
);
7155 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
7157 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
7158 (uwxn
&& (user_rw
& PAGE_WRITE
));
7168 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
7171 return prot_rw
| PAGE_EXEC
;
7174 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7175 uint32_t *table
, uint32_t address
)
7177 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
7178 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
7180 if (address
& tcr
->mask
) {
7181 if (tcr
->raw_tcr
& TTBCR_PD1
) {
7182 /* Translation table walk disabled for TTBR1 */
7185 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
7187 if (tcr
->raw_tcr
& TTBCR_PD0
) {
7188 /* Translation table walk disabled for TTBR0 */
7191 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
7193 *table
|= (address
>> 18) & 0x3ffc;
7197 /* Translate a S1 pagetable walk through S2 if needed. */
7198 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7199 hwaddr addr
, MemTxAttrs txattrs
,
7201 ARMMMUFaultInfo
*fi
)
7203 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
7204 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
7205 target_ulong s2size
;
7210 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
7211 &txattrs
, &s2prot
, &s2size
, fsr
, fi
);
7223 /* All loads done in the course of a page table walk go through here.
7224 * TODO: rather than ignoring errors from physical memory reads (which
7225 * are external aborts in ARM terminology) we should propagate this
7226 * error out so that we can turn it into a Data Abort if this walk
7227 * was being done for a CPU load/store or an address translation instruction
7228 * (but not if it was for a debug access).
7230 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
7231 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
7232 ARMMMUFaultInfo
*fi
)
7234 ARMCPU
*cpu
= ARM_CPU(cs
);
7235 CPUARMState
*env
= &cpu
->env
;
7236 MemTxAttrs attrs
= {};
7239 attrs
.secure
= is_secure
;
7240 as
= arm_addressspace(cs
, attrs
);
7241 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
7245 if (regime_translation_big_endian(env
, mmu_idx
)) {
7246 return address_space_ldl_be(as
, addr
, attrs
, NULL
);
7248 return address_space_ldl_le(as
, addr
, attrs
, NULL
);
7252 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
7253 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
7254 ARMMMUFaultInfo
*fi
)
7256 ARMCPU
*cpu
= ARM_CPU(cs
);
7257 CPUARMState
*env
= &cpu
->env
;
7258 MemTxAttrs attrs
= {};
7261 attrs
.secure
= is_secure
;
7262 as
= arm_addressspace(cs
, attrs
);
7263 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
7267 if (regime_translation_big_endian(env
, mmu_idx
)) {
7268 return address_space_ldq_be(as
, addr
, attrs
, NULL
);
7270 return address_space_ldq_le(as
, addr
, attrs
, NULL
);
7274 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
7275 int access_type
, ARMMMUIdx mmu_idx
,
7276 hwaddr
*phys_ptr
, int *prot
,
7277 target_ulong
*page_size
, uint32_t *fsr
,
7278 ARMMMUFaultInfo
*fi
)
7280 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
7291 /* Pagetable walk. */
7292 /* Lookup l1 descriptor. */
7293 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
7294 /* Section translation fault if page walk is disabled by PD0 or PD1 */
7298 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7301 domain
= (desc
>> 5) & 0x0f;
7302 if (regime_el(env
, mmu_idx
) == 1) {
7303 dacr
= env
->cp15
.dacr_ns
;
7305 dacr
= env
->cp15
.dacr_s
;
7307 domain_prot
= (dacr
>> (domain
* 2)) & 3;
7309 /* Section translation fault. */
7313 if (domain_prot
== 0 || domain_prot
== 2) {
7315 code
= 9; /* Section domain fault. */
7317 code
= 11; /* Page domain fault. */
7322 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
7323 ap
= (desc
>> 10) & 3;
7325 *page_size
= 1024 * 1024;
7327 /* Lookup l2 entry. */
7329 /* Coarse pagetable. */
7330 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
7332 /* Fine pagetable. */
7333 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
7335 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7338 case 0: /* Page translation fault. */
7341 case 1: /* 64k page. */
7342 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
7343 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
7344 *page_size
= 0x10000;
7346 case 2: /* 4k page. */
7347 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
7348 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
7349 *page_size
= 0x1000;
7351 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
7353 /* ARMv6/XScale extended small page format */
7354 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
7355 || arm_feature(env
, ARM_FEATURE_V6
)) {
7356 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
7357 *page_size
= 0x1000;
7359 /* UNPREDICTABLE in ARMv5; we choose to take a
7360 * page translation fault.
7366 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
7369 ap
= (desc
>> 4) & 3;
7372 /* Never happens, but compiler isn't smart enough to tell. */
7377 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
7378 *prot
|= *prot
? PAGE_EXEC
: 0;
7379 if (!(*prot
& (1 << access_type
))) {
7380 /* Access permission fault. */
7383 *phys_ptr
= phys_addr
;
7386 *fsr
= code
| (domain
<< 4);
7390 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
7391 int access_type
, ARMMMUIdx mmu_idx
,
7392 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
7393 target_ulong
*page_size
, uint32_t *fsr
,
7394 ARMMMUFaultInfo
*fi
)
7396 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
7410 /* Pagetable walk. */
7411 /* Lookup l1 descriptor. */
7412 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
7413 /* Section translation fault if page walk is disabled by PD0 or PD1 */
7417 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7420 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
7421 /* Section translation fault, or attempt to use the encoding
7422 * which is Reserved on implementations without PXN.
7427 if ((type
== 1) || !(desc
& (1 << 18))) {
7428 /* Page or Section. */
7429 domain
= (desc
>> 5) & 0x0f;
7431 if (regime_el(env
, mmu_idx
) == 1) {
7432 dacr
= env
->cp15
.dacr_ns
;
7434 dacr
= env
->cp15
.dacr_s
;
7436 domain_prot
= (dacr
>> (domain
* 2)) & 3;
7437 if (domain_prot
== 0 || domain_prot
== 2) {
7439 code
= 9; /* Section domain fault. */
7441 code
= 11; /* Page domain fault. */
7446 if (desc
& (1 << 18)) {
7448 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
7449 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
7450 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
7451 *page_size
= 0x1000000;
7454 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
7455 *page_size
= 0x100000;
7457 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
7458 xn
= desc
& (1 << 4);
7461 ns
= extract32(desc
, 19, 1);
7463 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
7464 pxn
= (desc
>> 2) & 1;
7466 ns
= extract32(desc
, 3, 1);
7467 /* Lookup l2 entry. */
7468 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
7469 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7471 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
7473 case 0: /* Page translation fault. */
7476 case 1: /* 64k page. */
7477 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
7478 xn
= desc
& (1 << 15);
7479 *page_size
= 0x10000;
7481 case 2: case 3: /* 4k page. */
7482 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
7484 *page_size
= 0x1000;
7487 /* Never happens, but compiler isn't smart enough to tell. */
7492 if (domain_prot
== 3) {
7493 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
7495 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
7498 if (xn
&& access_type
== 2)
7501 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
7502 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
7503 /* The simplified model uses AP[0] as an access control bit. */
7504 if ((ap
& 1) == 0) {
7505 /* Access flag fault. */
7506 code
= (code
== 15) ? 6 : 3;
7509 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
7511 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
7516 if (!(*prot
& (1 << access_type
))) {
7517 /* Access permission fault. */
7522 /* The NS bit will (as required by the architecture) have no effect if
7523 * the CPU doesn't support TZ or this is a non-secure translation
7524 * regime, because the attribute will already be non-secure.
7526 attrs
->secure
= false;
7528 *phys_ptr
= phys_addr
;
7531 *fsr
= code
| (domain
<< 4);
7535 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7536 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7539 translation_fault
= 1,
7541 permission_fault
= 3,
7545 * check_s2_mmu_setup
7547 * @is_aa64: True if the translation regime is in AArch64 state
7548 * @startlevel: Suggested starting level
7549 * @inputsize: Bitsize of IPAs
7550 * @stride: Page-table stride (See the ARM ARM)
7552 * Returns true if the suggested S2 translation parameters are OK and
7555 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
7556 int inputsize
, int stride
)
7558 const int grainsize
= stride
+ 3;
7561 /* Negative levels are never allowed. */
7566 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
7567 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
7572 CPUARMState
*env
= &cpu
->env
;
7573 unsigned int pamax
= arm_pamax(cpu
);
7576 case 13: /* 64KB Pages. */
7577 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
7581 case 11: /* 16KB Pages. */
7582 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
7586 case 9: /* 4KB Pages. */
7587 if (level
== 0 && pamax
<= 42) {
7592 g_assert_not_reached();
7595 /* Inputsize checks. */
7596 if (inputsize
> pamax
&&
7597 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
7598 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
7602 /* AArch32 only supports 4KB pages. Assert on that. */
7603 assert(stride
== 9);
7612 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
7613 int access_type
, ARMMMUIdx mmu_idx
,
7614 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
7615 target_ulong
*page_size_ptr
, uint32_t *fsr
,
7616 ARMMMUFaultInfo
*fi
)
7618 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7619 CPUState
*cs
= CPU(cpu
);
7620 /* Read an LPAE long-descriptor translation table. */
7621 MMUFaultType fault_type
= translation_fault
;
7628 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
7629 uint32_t tableattrs
;
7630 target_ulong page_size
;
7636 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
7637 int ap
, ns
, xn
, pxn
;
7638 uint32_t el
= regime_el(env
, mmu_idx
);
7639 bool ttbr1_valid
= true;
7640 uint64_t descaddrmask
;
7641 bool aarch64
= arm_el_is_aa64(env
, el
);
7644 * This code does not handle the different format TCR for VTCR_EL2.
7645 * This code also does not support shareability levels.
7646 * Attribute and permission bit handling should also be checked when adding
7647 * support for those page table walks.
7653 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
7654 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
7657 if (extract64(address
, 55, 1)) {
7658 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
7660 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
7665 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7669 ttbr1_valid
= false;
7674 /* There is no TTBR1 for EL2 */
7676 ttbr1_valid
= false;
7680 /* Determine whether this address is in the region controlled by
7681 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7682 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7683 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7686 /* AArch64 translation. */
7687 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
7688 t0sz
= MIN(t0sz
, 39);
7689 t0sz
= MAX(t0sz
, 16);
7690 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
7691 /* AArch32 stage 1 translation. */
7692 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
7694 /* AArch32 stage 2 translation. */
7695 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
7696 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
7697 /* Address size is 40-bit for a stage 2 translation,
7698 * and t0sz can be negative (from -8 to 7),
7699 * so we need to adjust it to use the TTBR selecting logic below.
7702 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
7704 /* If the sign-extend bit is not the same as t0sz[3], the result
7705 * is unpredictable. Flag this as a guest error. */
7707 qemu_log_mask(LOG_GUEST_ERROR
,
7708 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
7711 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
7713 t1sz
= MIN(t1sz
, 39);
7714 t1sz
= MAX(t1sz
, 16);
7716 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
7717 /* there is a ttbr0 region and we are in it (high bits all zero) */
7719 } else if (ttbr1_valid
&& t1sz
&&
7720 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
7721 /* there is a ttbr1 region and we are in it (high bits all one) */
7724 /* ttbr0 region is "everything not in the ttbr1 region" */
7726 } else if (!t1sz
&& ttbr1_valid
) {
7727 /* ttbr1 region is "everything not in the ttbr0 region" */
7730 /* in the gap between the two regions, this is a Translation fault */
7731 fault_type
= translation_fault
;
7735 /* Note that QEMU ignores shareability and cacheability attributes,
7736 * so we don't need to do anything with the SH, ORGN, IRGN fields
7737 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
7738 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7739 * implement any ASID-like capability so we can ignore it (instead
7740 * we will always flush the TLB any time the ASID is changed).
7742 if (ttbr_select
== 0) {
7743 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
7745 epd
= extract32(tcr
->raw_tcr
, 7, 1);
7747 inputsize
= addrsize
- t0sz
;
7749 tg
= extract32(tcr
->raw_tcr
, 14, 2);
7750 if (tg
== 1) { /* 64KB pages */
7753 if (tg
== 2) { /* 16KB pages */
7757 /* We should only be here if TTBR1 is valid */
7758 assert(ttbr1_valid
);
7760 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
7761 epd
= extract32(tcr
->raw_tcr
, 23, 1);
7762 inputsize
= addrsize
- t1sz
;
7764 tg
= extract32(tcr
->raw_tcr
, 30, 2);
7765 if (tg
== 3) { /* 64KB pages */
7768 if (tg
== 1) { /* 16KB pages */
7773 /* Here we should have set up all the parameters for the translation:
7774 * inputsize, ttbr, epd, stride, tbi
7778 /* Translation table walk disabled => Translation fault on TLB miss
7779 * Note: This is always 0 on 64-bit EL2 and EL3.
7784 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
7785 /* The starting level depends on the virtual address size (which can
7786 * be up to 48 bits) and the translation granule size. It indicates
7787 * the number of strides (stride bits at a time) needed to
7788 * consume the bits of the input address. In the pseudocode this is:
7789 * level = 4 - RoundUp((inputsize - grainsize) / stride)
7790 * where their 'inputsize' is our 'inputsize', 'grainsize' is
7791 * our 'stride + 3' and 'stride' is our 'stride'.
7792 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7793 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7794 * = 4 - (inputsize - 4) / stride;
7796 level
= 4 - (inputsize
- 4) / stride
;
7798 /* For stage 2 translations the starting level is specified by the
7799 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7801 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
7802 uint32_t startlevel
;
7805 if (!aarch64
|| stride
== 9) {
7806 /* AArch32 or 4KB pages */
7807 startlevel
= 2 - sl0
;
7809 /* 16KB or 64KB pages */
7810 startlevel
= 3 - sl0
;
7813 /* Check that the starting level is valid. */
7814 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
7817 fault_type
= translation_fault
;
7823 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
7824 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
7826 /* Now we can extract the actual base address from the TTBR */
7827 descaddr
= extract64(ttbr
, 0, 48);
7828 descaddr
&= ~indexmask
;
7830 /* The address field in the descriptor goes up to bit 39 for ARMv7
7831 * but up to bit 47 for ARMv8, but we use the descaddrmask
7832 * up to bit 39 for AArch32, because we don't need other bits in that case
7833 * to construct next descriptor address (anyway they should be all zeroes).
7835 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
7836 ~indexmask_grainsize
;
7838 /* Secure accesses start with the page table in secure memory and
7839 * can be downgraded to non-secure at any step. Non-secure accesses
7840 * remain non-secure. We implement this by just ORing in the NSTable/NS
7841 * bits at each step.
7843 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
7845 uint64_t descriptor
;
7848 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
7850 nstable
= extract32(tableattrs
, 4, 1);
7851 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fsr
, fi
);
7856 if (!(descriptor
& 1) ||
7857 (!(descriptor
& 2) && (level
== 3))) {
7858 /* Invalid, or the Reserved level 3 encoding */
7861 descaddr
= descriptor
& descaddrmask
;
7863 if ((descriptor
& 2) && (level
< 3)) {
7864 /* Table entry. The top five bits are attributes which may
7865 * propagate down through lower levels of the table (and
7866 * which are all arranged so that 0 means "no effect", so
7867 * we can gather them up by ORing in the bits at each level).
7869 tableattrs
|= extract64(descriptor
, 59, 5);
7871 indexmask
= indexmask_grainsize
;
7874 /* Block entry at level 1 or 2, or page entry at level 3.
7875 * These are basically the same thing, although the number
7876 * of bits we pull in from the vaddr varies.
7878 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
7879 descaddr
|= (address
& (page_size
- 1));
7880 /* Extract attributes from the descriptor */
7881 attrs
= extract64(descriptor
, 2, 10)
7882 | (extract64(descriptor
, 52, 12) << 10);
7884 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7885 /* Stage 2 table descriptors do not include any attribute fields */
7888 /* Merge in attributes from table descriptors */
7889 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
7890 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
7891 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7892 * means "force PL1 access only", which means forcing AP[1] to 0.
7894 if (extract32(tableattrs
, 2, 1)) {
7897 attrs
|= nstable
<< 3; /* NS */
7900 /* Here descaddr is the final physical address, and attributes
7903 fault_type
= access_fault
;
7904 if ((attrs
& (1 << 8)) == 0) {
7909 ap
= extract32(attrs
, 4, 2);
7910 xn
= extract32(attrs
, 12, 1);
7912 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7914 *prot
= get_S2prot(env
, ap
, xn
);
7916 ns
= extract32(attrs
, 3, 1);
7917 pxn
= extract32(attrs
, 11, 1);
7918 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
7921 fault_type
= permission_fault
;
7922 if (!(*prot
& (1 << access_type
))) {
7927 /* The NS bit will (as required by the architecture) have no effect if
7928 * the CPU doesn't support TZ or this is a non-secure translation
7929 * regime, because the attribute will already be non-secure.
7931 txattrs
->secure
= false;
7933 *phys_ptr
= descaddr
;
7934 *page_size_ptr
= page_size
;
7938 /* Long-descriptor format IFSR/DFSR value */
7939 *fsr
= (1 << 9) | (fault_type
<< 2) | level
;
7940 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
7941 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
7945 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
7947 int32_t address
, int *prot
)
7949 *prot
= PAGE_READ
| PAGE_WRITE
;
7951 case 0xF0000000 ... 0xFFFFFFFF:
7952 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) { /* hivecs execing is ok */
7956 case 0x00000000 ... 0x7FFFFFFF:
7963 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
7964 int access_type
, ARMMMUIdx mmu_idx
,
7965 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
7967 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7969 bool is_user
= regime_is_user(env
, mmu_idx
);
7971 *phys_ptr
= address
;
7974 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
7975 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
7976 } else { /* MPU enabled */
7977 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
7979 uint32_t base
= env
->pmsav7
.drbar
[n
];
7980 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
7984 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
7989 qemu_log_mask(LOG_GUEST_ERROR
, "DRSR.Rsize field can not be 0");
7993 rmask
= (1ull << rsize
) - 1;
7996 qemu_log_mask(LOG_GUEST_ERROR
, "DRBAR %" PRIx32
" misaligned "
7997 "to DRSR region size, mask = %" PRIx32
,
8002 if (address
< base
|| address
> base
+ rmask
) {
8006 /* Region matched */
8008 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
8010 uint32_t srdis_mask
;
8012 rsize
-= 3; /* sub region size (power of 2) */
8013 snd
= ((address
- base
) >> rsize
) & 0x7;
8014 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
8016 srdis_mask
= srdis
? 0x3 : 0x0;
8017 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
8018 /* This will check in groups of 2, 4 and then 8, whether
8019 * the subregion bits are consistent. rsize is incremented
8020 * back up to give the region size, considering consistent
8021 * adjacent subregions as one region. Stop testing if rsize
8022 * is already big enough for an entire QEMU page.
8024 int snd_rounded
= snd
& ~(i
- 1);
8025 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
8026 snd_rounded
+ 8, i
);
8027 if (srdis_mask
^ srdis_multi
) {
8030 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
8034 if (rsize
< TARGET_PAGE_BITS
) {
8035 qemu_log_mask(LOG_UNIMP
, "No support for MPU (sub)region"
8036 "alignment of %" PRIu32
" bits. Minimum is %d\n",
8037 rsize
, TARGET_PAGE_BITS
);
8046 if (n
== -1) { /* no hits */
8047 if (cpu
->pmsav7_dregion
&&
8048 (is_user
|| !(regime_sctlr(env
, mmu_idx
) & SCTLR_BR
))) {
8049 /* background fault */
8053 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
8054 } else { /* a MPU hit! */
8055 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
8057 if (is_user
) { /* User mode AP bit decoding */
8062 break; /* no access */
8064 *prot
|= PAGE_WRITE
;
8068 *prot
|= PAGE_READ
| PAGE_EXEC
;
8071 qemu_log_mask(LOG_GUEST_ERROR
,
8072 "Bad value for AP bits in DRACR %"
8075 } else { /* Priv. mode AP bits decoding */
8078 break; /* no access */
8082 *prot
|= PAGE_WRITE
;
8086 *prot
|= PAGE_READ
| PAGE_EXEC
;
8089 qemu_log_mask(LOG_GUEST_ERROR
,
8090 "Bad value for AP bits in DRACR %"
8096 if (env
->pmsav7
.dracr
[n
] & (1 << 12)) {
8097 *prot
&= ~PAGE_EXEC
;
8102 *fsr
= 0x00d; /* Permission fault */
8103 return !(*prot
& (1 << access_type
));
8106 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
8107 int access_type
, ARMMMUIdx mmu_idx
,
8108 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
8113 bool is_user
= regime_is_user(env
, mmu_idx
);
8115 *phys_ptr
= address
;
8116 for (n
= 7; n
>= 0; n
--) {
8117 base
= env
->cp15
.c6_region
[n
];
8118 if ((base
& 1) == 0) {
8121 mask
= 1 << ((base
>> 1) & 0x1f);
8122 /* Keep this shift separate from the above to avoid an
8123 (undefined) << 32. */
8124 mask
= (mask
<< 1) - 1;
8125 if (((base
^ address
) & ~mask
) == 0) {
8134 if (access_type
== 2) {
8135 mask
= env
->cp15
.pmsav5_insn_ap
;
8137 mask
= env
->cp15
.pmsav5_data_ap
;
8139 mask
= (mask
>> (n
* 4)) & 0xf;
8149 *prot
= PAGE_READ
| PAGE_WRITE
;
8154 *prot
|= PAGE_WRITE
;
8158 *prot
= PAGE_READ
| PAGE_WRITE
;
8171 /* Bad permission. */
8179 /* get_phys_addr - get the physical address for this virtual address
8181 * Find the physical address corresponding to the given virtual address,
8182 * by doing a translation table walk on MMU based systems or using the
8183 * MPU state on MPU based systems.
8185 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
8186 * prot and page_size may not be filled in, and the populated fsr value provides
8187 * information on why the translation aborted, in the format of a
8188 * DFSR/IFSR fault register, with the following caveats:
8189 * * we honour the short vs long DFSR format differences.
8190 * * the WnR bit is never set (the caller must do this).
8191 * * for PSMAv5 based systems we don't bother to return a full FSR format
8195 * @address: virtual address to get physical address for
8196 * @access_type: 0 for read, 1 for write, 2 for execute
8197 * @mmu_idx: MMU index indicating required translation regime
8198 * @phys_ptr: set to the physical address corresponding to the virtual address
8199 * @attrs: set to the memory transaction attributes to use
8200 * @prot: set to the permissions for the page containing phys_ptr
8201 * @page_size: set to the size of the page containing phys_ptr
8202 * @fsr: set to the DFSR/IFSR value on failure
8204 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
8205 int access_type
, ARMMMUIdx mmu_idx
,
8206 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
8207 target_ulong
*page_size
, uint32_t *fsr
,
8208 ARMMMUFaultInfo
*fi
)
8210 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8211 /* Call ourselves recursively to do the stage 1 and then stage 2
8214 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
8219 ret
= get_phys_addr(env
, address
, access_type
,
8220 mmu_idx
+ ARMMMUIdx_S1NSE0
, &ipa
, attrs
,
8221 prot
, page_size
, fsr
, fi
);
8223 /* If S1 fails or S2 is disabled, return early. */
8224 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8229 /* S1 is done. Now do S2 translation. */
8230 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
8231 phys_ptr
, attrs
, &s2_prot
,
8232 page_size
, fsr
, fi
);
8234 /* Combine the S1 and S2 perms. */
8239 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
8241 mmu_idx
+= ARMMMUIdx_S1NSE0
;
8245 /* The page table entries may downgrade secure to non-secure, but
8246 * cannot upgrade an non-secure translation regime's attributes
8249 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
8250 attrs
->user
= regime_is_user(env
, mmu_idx
);
8252 /* Fast Context Switch Extension. This doesn't exist at all in v8.
8253 * In v7 and earlier it affects all stage 1 translations.
8255 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
8256 && !arm_feature(env
, ARM_FEATURE_V8
)) {
8257 if (regime_el(env
, mmu_idx
) == 3) {
8258 address
+= env
->cp15
.fcseidr_s
;
8260 address
+= env
->cp15
.fcseidr_ns
;
8264 /* pmsav7 has special handling for when MPU is disabled so call it before
8265 * the common MMU/MPU disabled check below.
8267 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
8268 arm_feature(env
, ARM_FEATURE_V7
)) {
8269 *page_size
= TARGET_PAGE_SIZE
;
8270 return get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
8271 phys_ptr
, prot
, fsr
);
8274 if (regime_translation_disabled(env
, mmu_idx
)) {
8275 /* MMU/MPU disabled. */
8276 *phys_ptr
= address
;
8277 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8278 *page_size
= TARGET_PAGE_SIZE
;
8282 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
8284 *page_size
= TARGET_PAGE_SIZE
;
8285 return get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
8286 phys_ptr
, prot
, fsr
);
8289 if (regime_using_lpae_format(env
, mmu_idx
)) {
8290 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
8291 attrs
, prot
, page_size
, fsr
, fi
);
8292 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
8293 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
8294 attrs
, prot
, page_size
, fsr
, fi
);
8296 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
8297 prot
, page_size
, fsr
, fi
);
8301 /* Walk the page table and (if the mapping exists) add the page
8302 * to the TLB. Return false on success, or true on failure. Populate
8303 * fsr with ARM DFSR/IFSR fault register format value on failure.
8305 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
8306 int access_type
, int mmu_idx
, uint32_t *fsr
,
8307 ARMMMUFaultInfo
*fi
)
8309 ARMCPU
*cpu
= ARM_CPU(cs
);
8310 CPUARMState
*env
= &cpu
->env
;
8312 target_ulong page_size
;
8315 MemTxAttrs attrs
= {};
8317 ret
= get_phys_addr(env
, address
, access_type
, mmu_idx
, &phys_addr
,
8318 &attrs
, &prot
, &page_size
, fsr
, fi
);
8320 /* Map a single [sub]page. */
8321 phys_addr
&= TARGET_PAGE_MASK
;
8322 address
&= TARGET_PAGE_MASK
;
8323 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
8324 prot
, mmu_idx
, page_size
);
8331 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
8334 ARMCPU
*cpu
= ARM_CPU(cs
);
8335 CPUARMState
*env
= &cpu
->env
;
8337 target_ulong page_size
;
8341 ARMMMUFaultInfo fi
= {};
8343 *attrs
= (MemTxAttrs
) {};
8345 ret
= get_phys_addr(env
, addr
, 0, cpu_mmu_index(env
, false), &phys_addr
,
8346 attrs
, &prot
, &page_size
, &fsr
, &fi
);
8354 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
8357 unsigned el
= arm_current_el(env
);
8359 /* First handle registers which unprivileged can read */
8362 case 0 ... 7: /* xPSR sub-fields */
8364 if ((reg
& 1) && el
) {
8365 mask
|= 0x000001ff; /* IPSR (unpriv. reads as zero) */
8368 mask
|= 0xf8000000; /* APSR */
8370 /* EPSR reads as zero */
8371 return xpsr_read(env
) & mask
;
8373 case 20: /* CONTROL */
8374 return env
->v7m
.control
;
8378 return 0; /* unprivileged reads others as zero */
8383 return (env
->v7m
.control
& R_V7M_CONTROL_SPSEL_MASK
) ?
8384 env
->v7m
.other_sp
: env
->regs
[13];
8386 return (env
->v7m
.control
& R_V7M_CONTROL_SPSEL_MASK
) ?
8387 env
->regs
[13] : env
->v7m
.other_sp
;
8388 case 16: /* PRIMASK */
8389 return (env
->daif
& PSTATE_I
) != 0;
8390 case 17: /* BASEPRI */
8391 case 18: /* BASEPRI_MAX */
8392 return env
->v7m
.basepri
;
8393 case 19: /* FAULTMASK */
8394 return (env
->daif
& PSTATE_F
) != 0;
8396 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
8397 " register %d\n", reg
);
8402 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
8404 if (arm_current_el(env
) == 0 && reg
> 7) {
8405 /* only xPSR sub-fields may be written by unprivileged */
8410 case 0 ... 7: /* xPSR sub-fields */
8411 /* only APSR is actually writable */
8413 xpsr_write(env
, val
, 0xf8000000); /* APSR */
8417 if (env
->v7m
.control
& R_V7M_CONTROL_SPSEL_MASK
) {
8418 env
->v7m
.other_sp
= val
;
8420 env
->regs
[13] = val
;
8424 if (env
->v7m
.control
& R_V7M_CONTROL_SPSEL_MASK
) {
8425 env
->regs
[13] = val
;
8427 env
->v7m
.other_sp
= val
;
8430 case 16: /* PRIMASK */
8432 env
->daif
|= PSTATE_I
;
8434 env
->daif
&= ~PSTATE_I
;
8437 case 17: /* BASEPRI */
8438 env
->v7m
.basepri
= val
& 0xff;
8440 case 18: /* BASEPRI_MAX */
8442 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
8443 env
->v7m
.basepri
= val
;
8445 case 19: /* FAULTMASK */
8447 env
->daif
|= PSTATE_F
;
8449 env
->daif
&= ~PSTATE_F
;
8452 case 20: /* CONTROL */
8453 switch_v7m_sp(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
8454 env
->v7m
.control
= val
& (R_V7M_CONTROL_SPSEL_MASK
|
8455 R_V7M_CONTROL_NPRIV_MASK
);
8458 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
8459 " register %d\n", reg
);
8466 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
8468 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8469 * Note that we do not implement the (architecturally mandated)
8470 * alignment fault for attempts to use this on Device memory
8471 * (which matches the usual QEMU behaviour of not implementing either
8472 * alignment faults or any memory attribute handling).
8475 ARMCPU
*cpu
= arm_env_get_cpu(env
);
8476 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
8477 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
8479 #ifndef CONFIG_USER_ONLY
8481 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8482 * the block size so we might have to do more than one TLB lookup.
8483 * We know that in fact for any v8 CPU the page size is at least 4K
8484 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8485 * 1K as an artefact of legacy v5 subpage support being present in the
8486 * same QEMU executable.
8488 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
8489 void *hostaddr
[maxidx
];
8491 unsigned mmu_idx
= cpu_mmu_index(env
, false);
8492 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
8494 for (try = 0; try < 2; try++) {
8496 for (i
= 0; i
< maxidx
; i
++) {
8497 hostaddr
[i
] = tlb_vaddr_to_host(env
,
8498 vaddr
+ TARGET_PAGE_SIZE
* i
,
8505 /* If it's all in the TLB it's fair game for just writing to;
8506 * we know we don't need to update dirty status, etc.
8508 for (i
= 0; i
< maxidx
- 1; i
++) {
8509 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
8511 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
8514 /* OK, try a store and see if we can populate the tlb. This
8515 * might cause an exception if the memory isn't writable,
8516 * in which case we will longjmp out of here. We must for
8517 * this purpose use the actual register value passed to us
8518 * so that we get the fault address right.
8520 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
8521 /* Now we can populate the other TLB entries, if any */
8522 for (i
= 0; i
< maxidx
; i
++) {
8523 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
8524 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
8525 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
8530 /* Slow path (probably attempt to do this to an I/O device or
8531 * similar, or clearing of a block of code we have translations
8532 * cached for). Just do a series of byte writes as the architecture
8533 * demands. It's not worth trying to use a cpu_physical_memory_map(),
8534 * memset(), unmap() sequence here because:
8535 * + we'd need to account for the blocksize being larger than a page
8536 * + the direct-RAM access case is almost always going to be dealt
8537 * with in the fastpath code above, so there's no speed benefit
8538 * + we would have to deal with the map returning NULL because the
8539 * bounce buffer was in use
8541 for (i
= 0; i
< blocklen
; i
++) {
8542 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
8546 memset(g2h(vaddr
), 0, blocklen
);
8550 /* Note that signed overflow is undefined in C. The following routines are
8551 careful to use unsigned types where modulo arithmetic is required.
8552 Failure to do so _will_ break on newer gcc. */
8554 /* Signed saturating arithmetic. */
8556 /* Perform 16-bit signed saturating addition. */
8557 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
8562 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
8571 /* Perform 8-bit signed saturating addition. */
8572 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
8577 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
8586 /* Perform 16-bit signed saturating subtraction. */
8587 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
8592 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
8601 /* Perform 8-bit signed saturating subtraction. */
8602 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
8607 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
8616 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
8617 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
8618 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
8619 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
8622 #include "op_addsub.h"
8624 /* Unsigned saturating arithmetic. */
8625 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
8634 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
8642 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
8651 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
8659 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8660 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8661 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
8662 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
8665 #include "op_addsub.h"
8667 /* Signed modulo arithmetic. */
8668 #define SARITH16(a, b, n, op) do { \
8670 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8671 RESULT(sum, n, 16); \
8673 ge |= 3 << (n * 2); \
8676 #define SARITH8(a, b, n, op) do { \
8678 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8679 RESULT(sum, n, 8); \
8685 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8686 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8687 #define ADD8(a, b, n) SARITH8(a, b, n, +)
8688 #define SUB8(a, b, n) SARITH8(a, b, n, -)
8692 #include "op_addsub.h"
8694 /* Unsigned modulo arithmetic. */
8695 #define ADD16(a, b, n) do { \
8697 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8698 RESULT(sum, n, 16); \
8699 if ((sum >> 16) == 1) \
8700 ge |= 3 << (n * 2); \
8703 #define ADD8(a, b, n) do { \
8705 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8706 RESULT(sum, n, 8); \
8707 if ((sum >> 8) == 1) \
8711 #define SUB16(a, b, n) do { \
8713 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8714 RESULT(sum, n, 16); \
8715 if ((sum >> 16) == 0) \
8716 ge |= 3 << (n * 2); \
8719 #define SUB8(a, b, n) do { \
8721 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8722 RESULT(sum, n, 8); \
8723 if ((sum >> 8) == 0) \
8730 #include "op_addsub.h"
8732 /* Halved signed arithmetic. */
8733 #define ADD16(a, b, n) \
8734 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8735 #define SUB16(a, b, n) \
8736 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8737 #define ADD8(a, b, n) \
8738 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8739 #define SUB8(a, b, n) \
8740 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8743 #include "op_addsub.h"
8745 /* Halved unsigned arithmetic. */
8746 #define ADD16(a, b, n) \
8747 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8748 #define SUB16(a, b, n) \
8749 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8750 #define ADD8(a, b, n) \
8751 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8752 #define SUB8(a, b, n) \
8753 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8756 #include "op_addsub.h"
8758 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
8766 /* Unsigned sum of absolute byte differences. */
8767 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
8770 sum
= do_usad(a
, b
);
8771 sum
+= do_usad(a
>> 8, b
>> 8);
8772 sum
+= do_usad(a
>> 16, b
>>16);
8773 sum
+= do_usad(a
>> 24, b
>> 24);
8777 /* For ARMv6 SEL instruction. */
8778 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
8791 return (a
& mask
) | (b
& ~mask
);
8794 /* VFP support. We follow the convention used for VFP instructions:
8795 Single precision routines have a "s" suffix, double precision a
8798 /* Convert host exception flags to vfp form. */
8799 static inline int vfp_exceptbits_from_host(int host_bits
)
8801 int target_bits
= 0;
8803 if (host_bits
& float_flag_invalid
)
8805 if (host_bits
& float_flag_divbyzero
)
8807 if (host_bits
& float_flag_overflow
)
8809 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
8811 if (host_bits
& float_flag_inexact
)
8812 target_bits
|= 0x10;
8813 if (host_bits
& float_flag_input_denormal
)
8814 target_bits
|= 0x80;
8818 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
8823 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
8824 | (env
->vfp
.vec_len
<< 16)
8825 | (env
->vfp
.vec_stride
<< 20);
8826 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
8827 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
8828 fpscr
|= vfp_exceptbits_from_host(i
);
8832 uint32_t vfp_get_fpscr(CPUARMState
*env
)
8834 return HELPER(vfp_get_fpscr
)(env
);
8837 /* Convert vfp exception flags to target form. */
8838 static inline int vfp_exceptbits_to_host(int target_bits
)
8842 if (target_bits
& 1)
8843 host_bits
|= float_flag_invalid
;
8844 if (target_bits
& 2)
8845 host_bits
|= float_flag_divbyzero
;
8846 if (target_bits
& 4)
8847 host_bits
|= float_flag_overflow
;
8848 if (target_bits
& 8)
8849 host_bits
|= float_flag_underflow
;
8850 if (target_bits
& 0x10)
8851 host_bits
|= float_flag_inexact
;
8852 if (target_bits
& 0x80)
8853 host_bits
|= float_flag_input_denormal
;
8857 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
8862 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
8863 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
8864 env
->vfp
.vec_len
= (val
>> 16) & 7;
8865 env
->vfp
.vec_stride
= (val
>> 20) & 3;
8868 if (changed
& (3 << 22)) {
8869 i
= (val
>> 22) & 3;
8871 case FPROUNDING_TIEEVEN
:
8872 i
= float_round_nearest_even
;
8874 case FPROUNDING_POSINF
:
8877 case FPROUNDING_NEGINF
:
8878 i
= float_round_down
;
8880 case FPROUNDING_ZERO
:
8881 i
= float_round_to_zero
;
8884 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
8886 if (changed
& (1 << 24)) {
8887 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
8888 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
8890 if (changed
& (1 << 25))
8891 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
8893 i
= vfp_exceptbits_to_host(val
);
8894 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
8895 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
8898 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
8900 HELPER(vfp_set_fpscr
)(env
, val
);
8903 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8905 #define VFP_BINOP(name) \
8906 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8908 float_status *fpst = fpstp; \
8909 return float32_ ## name(a, b, fpst); \
8911 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8913 float_status *fpst = fpstp; \
8914 return float64_ ## name(a, b, fpst); \
8926 float32
VFP_HELPER(neg
, s
)(float32 a
)
8928 return float32_chs(a
);
8931 float64
VFP_HELPER(neg
, d
)(float64 a
)
8933 return float64_chs(a
);
8936 float32
VFP_HELPER(abs
, s
)(float32 a
)
8938 return float32_abs(a
);
8941 float64
VFP_HELPER(abs
, d
)(float64 a
)
8943 return float64_abs(a
);
8946 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
8948 return float32_sqrt(a
, &env
->vfp
.fp_status
);
8951 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
8953 return float64_sqrt(a
, &env
->vfp
.fp_status
);
8956 /* XXX: check quiet/signaling case */
8957 #define DO_VFP_cmp(p, type) \
8958 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
8961 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8962 case 0: flags = 0x6; break; \
8963 case -1: flags = 0x8; break; \
8964 case 1: flags = 0x2; break; \
8965 default: case 2: flags = 0x3; break; \
8967 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8968 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8970 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8973 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8974 case 0: flags = 0x6; break; \
8975 case -1: flags = 0x8; break; \
8976 case 1: flags = 0x2; break; \
8977 default: case 2: flags = 0x3; break; \
8979 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8980 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8982 DO_VFP_cmp(s
, float32
)
8983 DO_VFP_cmp(d
, float64
)
8986 /* Integer to float and float to integer conversions */
8988 #define CONV_ITOF(name, fsz, sign) \
8989 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8991 float_status *fpst = fpstp; \
8992 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8995 #define CONV_FTOI(name, fsz, sign, round) \
8996 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8998 float_status *fpst = fpstp; \
8999 if (float##fsz##_is_any_nan(x)) { \
9000 float_raise(float_flag_invalid, fpst); \
9003 return float##fsz##_to_##sign##int32##round(x, fpst); \
9006 #define FLOAT_CONVS(name, p, fsz, sign) \
9007 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
9008 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
9009 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
9011 FLOAT_CONVS(si
, s
, 32, )
9012 FLOAT_CONVS(si
, d
, 64, )
9013 FLOAT_CONVS(ui
, s
, 32, u
)
9014 FLOAT_CONVS(ui
, d
, 64, u
)
9020 /* floating point conversion */
9021 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
9023 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
9024 /* ARM requires that S<->D conversion of any kind of NaN generates
9025 * a quiet NaN by forcing the most significant frac bit to 1.
9027 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9030 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
9032 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
9033 /* ARM requires that S<->D conversion of any kind of NaN generates
9034 * a quiet NaN by forcing the most significant frac bit to 1.
9036 return float32_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9039 /* VFP3 fixed point conversion. */
9040 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9041 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
9044 float_status *fpst = fpstp; \
9046 tmp = itype##_to_##float##fsz(x, fpst); \
9047 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
9050 /* Notice that we want only input-denormal exception flags from the
9051 * scalbn operation: the other possible flags (overflow+inexact if
9052 * we overflow to infinity, output-denormal) aren't correct for the
9053 * complete scale-and-convert operation.
9055 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
9056 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
9060 float_status *fpst = fpstp; \
9061 int old_exc_flags = get_float_exception_flags(fpst); \
9063 if (float##fsz##_is_any_nan(x)) { \
9064 float_raise(float_flag_invalid, fpst); \
9067 tmp = float##fsz##_scalbn(x, shift, fpst); \
9068 old_exc_flags |= get_float_exception_flags(fpst) \
9069 & float_flag_input_denormal; \
9070 set_float_exception_flags(old_exc_flags, fpst); \
9071 return float##fsz##_to_##itype##round(tmp, fpst); \
9074 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
9075 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9076 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
9077 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
9079 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
9080 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9081 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
9083 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
9084 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
9085 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
9086 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
9087 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
9088 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
9089 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
9090 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
9091 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
9092 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
9093 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
9094 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
9096 #undef VFP_CONV_FIX_FLOAT
9097 #undef VFP_CONV_FLOAT_FIX_ROUND
9099 /* Set the current fp rounding mode and return the old one.
9100 * The argument is a softfloat float_round_ value.
9102 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
9104 float_status
*fp_status
= &env
->vfp
.fp_status
;
9106 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
9107 set_float_rounding_mode(rmode
, fp_status
);
9112 /* Set the current fp rounding mode in the standard fp status and return
9113 * the old one. This is for NEON instructions that need to change the
9114 * rounding mode but wish to use the standard FPSCR values for everything
9115 * else. Always set the rounding mode back to the correct value after
9117 * The argument is a softfloat float_round_ value.
9119 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
9121 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
9123 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
9124 set_float_rounding_mode(rmode
, fp_status
);
9129 /* Half precision conversions. */
9130 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
9132 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9133 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
9135 return float32_maybe_silence_nan(r
, s
);
9140 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
9142 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9143 float16 r
= float32_to_float16(a
, ieee
, s
);
9145 r
= float16_maybe_silence_nan(r
, s
);
9147 return float16_val(r
);
9150 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
9152 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
9155 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
9157 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
9160 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
9162 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
9165 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
9167 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
9170 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
9172 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9173 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
9175 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9180 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
9182 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9183 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
9185 r
= float16_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9187 return float16_val(r
);
9190 #define float32_two make_float32(0x40000000)
9191 #define float32_three make_float32(0x40400000)
9192 #define float32_one_point_five make_float32(0x3fc00000)
9194 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
9196 float_status
*s
= &env
->vfp
.standard_fp_status
;
9197 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
9198 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
9199 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
9200 float_raise(float_flag_input_denormal
, s
);
9204 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
9207 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
9209 float_status
*s
= &env
->vfp
.standard_fp_status
;
9211 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
9212 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
9213 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
9214 float_raise(float_flag_input_denormal
, s
);
9216 return float32_one_point_five
;
9218 product
= float32_mul(a
, b
, s
);
9219 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
9224 /* Constants 256 and 512 are used in some helpers; we avoid relying on
9225 * int->float conversions at run-time. */
9226 #define float64_256 make_float64(0x4070000000000000LL)
9227 #define float64_512 make_float64(0x4080000000000000LL)
9228 #define float32_maxnorm make_float32(0x7f7fffff)
9229 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
9231 /* Reciprocal functions
9233 * The algorithm that must be used to calculate the estimate
9234 * is specified by the ARM ARM, see FPRecipEstimate()
9237 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
9239 /* These calculations mustn't set any fp exception flags,
9240 * so we use a local copy of the fp_status.
9242 float_status dummy_status
= *real_fp_status
;
9243 float_status
*s
= &dummy_status
;
9244 /* q = (int)(a * 512.0) */
9245 float64 q
= float64_mul(float64_512
, a
, s
);
9246 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
9248 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
9249 q
= int64_to_float64(q_int
, s
);
9250 q
= float64_add(q
, float64_half
, s
);
9251 q
= float64_div(q
, float64_512
, s
);
9252 q
= float64_div(float64_one
, q
, s
);
9254 /* s = (int)(256.0 * r + 0.5) */
9255 q
= float64_mul(q
, float64_256
, s
);
9256 q
= float64_add(q
, float64_half
, s
);
9257 q_int
= float64_to_int64_round_to_zero(q
, s
);
9259 /* return (double)s / 256.0 */
9260 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
9263 /* Common wrapper to call recip_estimate */
9264 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
9266 uint64_t val64
= float64_val(num
);
9267 uint64_t frac
= extract64(val64
, 0, 52);
9268 int64_t exp
= extract64(val64
, 52, 11);
9270 float64 scaled
, estimate
;
9272 /* Generate the scaled number for the estimate function */
9274 if (extract64(frac
, 51, 1) == 0) {
9276 frac
= extract64(frac
, 0, 50) << 2;
9278 frac
= extract64(frac
, 0, 51) << 1;
9282 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
9283 scaled
= make_float64((0x3feULL
<< 52)
9284 | extract64(frac
, 44, 8) << 44);
9286 estimate
= recip_estimate(scaled
, fpst
);
9288 /* Build new result */
9289 val64
= float64_val(estimate
);
9290 sbit
= 0x8000000000000000ULL
& val64
;
9292 frac
= extract64(val64
, 0, 52);
9295 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
9296 } else if (exp
== -1) {
9297 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
9301 return make_float64(sbit
| (exp
<< 52) | frac
);
9304 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
9306 switch (fpst
->float_rounding_mode
) {
9307 case float_round_nearest_even
: /* Round to Nearest */
9309 case float_round_up
: /* Round to +Inf */
9311 case float_round_down
: /* Round to -Inf */
9313 case float_round_to_zero
: /* Round to Zero */
9317 g_assert_not_reached();
9320 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
9322 float_status
*fpst
= fpstp
;
9323 float32 f32
= float32_squash_input_denormal(input
, fpst
);
9324 uint32_t f32_val
= float32_val(f32
);
9325 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
9326 int32_t f32_exp
= extract32(f32_val
, 23, 8);
9327 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
9333 if (float32_is_any_nan(f32
)) {
9335 if (float32_is_signaling_nan(f32
, fpst
)) {
9336 float_raise(float_flag_invalid
, fpst
);
9337 nan
= float32_maybe_silence_nan(f32
, fpst
);
9339 if (fpst
->default_nan_mode
) {
9340 nan
= float32_default_nan(fpst
);
9343 } else if (float32_is_infinity(f32
)) {
9344 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
9345 } else if (float32_is_zero(f32
)) {
9346 float_raise(float_flag_divbyzero
, fpst
);
9347 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
9348 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
9349 /* Abs(value) < 2.0^-128 */
9350 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
9351 if (round_to_inf(fpst
, f32_sbit
)) {
9352 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
9354 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
9356 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
9357 float_raise(float_flag_underflow
, fpst
);
9358 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
9362 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
9363 r64
= call_recip_estimate(f64
, 253, fpst
);
9364 r64_val
= float64_val(r64
);
9365 r64_exp
= extract64(r64_val
, 52, 11);
9366 r64_frac
= extract64(r64_val
, 0, 52);
9368 /* result = sign : result_exp<7:0> : fraction<51:29>; */
9369 return make_float32(f32_sbit
|
9370 (r64_exp
& 0xff) << 23 |
9371 extract64(r64_frac
, 29, 24));
9374 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
9376 float_status
*fpst
= fpstp
;
9377 float64 f64
= float64_squash_input_denormal(input
, fpst
);
9378 uint64_t f64_val
= float64_val(f64
);
9379 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
9380 int64_t f64_exp
= extract64(f64_val
, 52, 11);
9386 /* Deal with any special cases */
9387 if (float64_is_any_nan(f64
)) {
9389 if (float64_is_signaling_nan(f64
, fpst
)) {
9390 float_raise(float_flag_invalid
, fpst
);
9391 nan
= float64_maybe_silence_nan(f64
, fpst
);
9393 if (fpst
->default_nan_mode
) {
9394 nan
= float64_default_nan(fpst
);
9397 } else if (float64_is_infinity(f64
)) {
9398 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
9399 } else if (float64_is_zero(f64
)) {
9400 float_raise(float_flag_divbyzero
, fpst
);
9401 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
9402 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
9403 /* Abs(value) < 2.0^-1024 */
9404 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
9405 if (round_to_inf(fpst
, f64_sbit
)) {
9406 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
9408 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
9410 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
9411 float_raise(float_flag_underflow
, fpst
);
9412 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
9415 r64
= call_recip_estimate(f64
, 2045, fpst
);
9416 r64_val
= float64_val(r64
);
9417 r64_exp
= extract64(r64_val
, 52, 11);
9418 r64_frac
= extract64(r64_val
, 0, 52);
9420 /* result = sign : result_exp<10:0> : fraction<51:0> */
9421 return make_float64(f64_sbit
|
9422 ((r64_exp
& 0x7ff) << 52) |
9426 /* The algorithm that must be used to calculate the estimate
9427 * is specified by the ARM ARM.
9429 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
9431 /* These calculations mustn't set any fp exception flags,
9432 * so we use a local copy of the fp_status.
9434 float_status dummy_status
= *real_fp_status
;
9435 float_status
*s
= &dummy_status
;
9439 if (float64_lt(a
, float64_half
, s
)) {
9440 /* range 0.25 <= a < 0.5 */
9442 /* a in units of 1/512 rounded down */
9443 /* q0 = (int)(a * 512.0); */
9444 q
= float64_mul(float64_512
, a
, s
);
9445 q_int
= float64_to_int64_round_to_zero(q
, s
);
9447 /* reciprocal root r */
9448 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
9449 q
= int64_to_float64(q_int
, s
);
9450 q
= float64_add(q
, float64_half
, s
);
9451 q
= float64_div(q
, float64_512
, s
);
9452 q
= float64_sqrt(q
, s
);
9453 q
= float64_div(float64_one
, q
, s
);
9455 /* range 0.5 <= a < 1.0 */
9457 /* a in units of 1/256 rounded down */
9458 /* q1 = (int)(a * 256.0); */
9459 q
= float64_mul(float64_256
, a
, s
);
9460 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
9462 /* reciprocal root r */
9463 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9464 q
= int64_to_float64(q_int
, s
);
9465 q
= float64_add(q
, float64_half
, s
);
9466 q
= float64_div(q
, float64_256
, s
);
9467 q
= float64_sqrt(q
, s
);
9468 q
= float64_div(float64_one
, q
, s
);
9470 /* r in units of 1/256 rounded to nearest */
9471 /* s = (int)(256.0 * r + 0.5); */
9473 q
= float64_mul(q
, float64_256
,s
);
9474 q
= float64_add(q
, float64_half
, s
);
9475 q_int
= float64_to_int64_round_to_zero(q
, s
);
9477 /* return (double)s / 256.0;*/
9478 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
9481 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
9483 float_status
*s
= fpstp
;
9484 float32 f32
= float32_squash_input_denormal(input
, s
);
9485 uint32_t val
= float32_val(f32
);
9486 uint32_t f32_sbit
= 0x80000000 & val
;
9487 int32_t f32_exp
= extract32(val
, 23, 8);
9488 uint32_t f32_frac
= extract32(val
, 0, 23);
9494 if (float32_is_any_nan(f32
)) {
9496 if (float32_is_signaling_nan(f32
, s
)) {
9497 float_raise(float_flag_invalid
, s
);
9498 nan
= float32_maybe_silence_nan(f32
, s
);
9500 if (s
->default_nan_mode
) {
9501 nan
= float32_default_nan(s
);
9504 } else if (float32_is_zero(f32
)) {
9505 float_raise(float_flag_divbyzero
, s
);
9506 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
9507 } else if (float32_is_neg(f32
)) {
9508 float_raise(float_flag_invalid
, s
);
9509 return float32_default_nan(s
);
9510 } else if (float32_is_infinity(f32
)) {
9511 return float32_zero
;
9514 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9515 * preserving the parity of the exponent. */
9517 f64_frac
= ((uint64_t) f32_frac
) << 29;
9519 while (extract64(f64_frac
, 51, 1) == 0) {
9520 f64_frac
= f64_frac
<< 1;
9521 f32_exp
= f32_exp
-1;
9523 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
9526 if (extract64(f32_exp
, 0, 1) == 0) {
9527 f64
= make_float64(((uint64_t) f32_sbit
) << 32
9531 f64
= make_float64(((uint64_t) f32_sbit
) << 32
9536 result_exp
= (380 - f32_exp
) / 2;
9538 f64
= recip_sqrt_estimate(f64
, s
);
9540 val64
= float64_val(f64
);
9542 val
= ((result_exp
& 0xff) << 23)
9543 | ((val64
>> 29) & 0x7fffff);
9544 return make_float32(val
);
9547 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
9549 float_status
*s
= fpstp
;
9550 float64 f64
= float64_squash_input_denormal(input
, s
);
9551 uint64_t val
= float64_val(f64
);
9552 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
9553 int64_t f64_exp
= extract64(val
, 52, 11);
9554 uint64_t f64_frac
= extract64(val
, 0, 52);
9556 uint64_t result_frac
;
9558 if (float64_is_any_nan(f64
)) {
9560 if (float64_is_signaling_nan(f64
, s
)) {
9561 float_raise(float_flag_invalid
, s
);
9562 nan
= float64_maybe_silence_nan(f64
, s
);
9564 if (s
->default_nan_mode
) {
9565 nan
= float64_default_nan(s
);
9568 } else if (float64_is_zero(f64
)) {
9569 float_raise(float_flag_divbyzero
, s
);
9570 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
9571 } else if (float64_is_neg(f64
)) {
9572 float_raise(float_flag_invalid
, s
);
9573 return float64_default_nan(s
);
9574 } else if (float64_is_infinity(f64
)) {
9575 return float64_zero
;
9578 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9579 * preserving the parity of the exponent. */
9582 while (extract64(f64_frac
, 51, 1) == 0) {
9583 f64_frac
= f64_frac
<< 1;
9584 f64_exp
= f64_exp
- 1;
9586 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
9589 if (extract64(f64_exp
, 0, 1) == 0) {
9590 f64
= make_float64(f64_sbit
9594 f64
= make_float64(f64_sbit
9599 result_exp
= (3068 - f64_exp
) / 2;
9601 f64
= recip_sqrt_estimate(f64
, s
);
9603 result_frac
= extract64(float64_val(f64
), 0, 52);
9605 return make_float64(f64_sbit
|
9606 ((result_exp
& 0x7ff) << 52) |
9610 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
9612 float_status
*s
= fpstp
;
9615 if ((a
& 0x80000000) == 0) {
9619 f64
= make_float64((0x3feULL
<< 52)
9620 | ((int64_t)(a
& 0x7fffffff) << 21));
9622 f64
= recip_estimate(f64
, s
);
9624 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
9627 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
9629 float_status
*fpst
= fpstp
;
9632 if ((a
& 0xc0000000) == 0) {
9636 if (a
& 0x80000000) {
9637 f64
= make_float64((0x3feULL
<< 52)
9638 | ((uint64_t)(a
& 0x7fffffff) << 21));
9639 } else { /* bits 31-30 == '01' */
9640 f64
= make_float64((0x3fdULL
<< 52)
9641 | ((uint64_t)(a
& 0x3fffffff) << 22));
9644 f64
= recip_sqrt_estimate(f64
, fpst
);
9646 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
9649 /* VFPv4 fused multiply-accumulate */
9650 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
9652 float_status
*fpst
= fpstp
;
9653 return float32_muladd(a
, b
, c
, 0, fpst
);
9656 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
9658 float_status
*fpst
= fpstp
;
9659 return float64_muladd(a
, b
, c
, 0, fpst
);
9662 /* ARMv8 round to integral */
9663 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
9665 return float32_round_to_int(x
, fp_status
);
9668 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
9670 return float64_round_to_int(x
, fp_status
);
9673 float32
HELPER(rints
)(float32 x
, void *fp_status
)
9675 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
9678 ret
= float32_round_to_int(x
, fp_status
);
9680 /* Suppress any inexact exceptions the conversion produced */
9681 if (!(old_flags
& float_flag_inexact
)) {
9682 new_flags
= get_float_exception_flags(fp_status
);
9683 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
9689 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
9691 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
9694 ret
= float64_round_to_int(x
, fp_status
);
9696 new_flags
= get_float_exception_flags(fp_status
);
9698 /* Suppress any inexact exceptions the conversion produced */
9699 if (!(old_flags
& float_flag_inexact
)) {
9700 new_flags
= get_float_exception_flags(fp_status
);
9701 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
9707 /* Convert ARM rounding mode to softfloat */
9708 int arm_rmode_to_sf(int rmode
)
9711 case FPROUNDING_TIEAWAY
:
9712 rmode
= float_round_ties_away
;
9714 case FPROUNDING_ODD
:
9715 /* FIXME: add support for TIEAWAY and ODD */
9716 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
9718 case FPROUNDING_TIEEVEN
:
9720 rmode
= float_round_nearest_even
;
9722 case FPROUNDING_POSINF
:
9723 rmode
= float_round_up
;
9725 case FPROUNDING_NEGINF
:
9726 rmode
= float_round_down
;
9728 case FPROUNDING_ZERO
:
9729 rmode
= float_round_to_zero
;
9736 * The upper bytes of val (above the number specified by 'bytes') must have
9737 * been zeroed out by the caller.
9739 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
9745 /* zlib crc32 converts the accumulator and output to one's complement. */
9746 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
9749 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
9755 /* Linux crc32c converts the output to one's complement. */
9756 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;