4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/tcg.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
35 #include "exec/cpu_ldst.h"
38 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
40 #ifndef CONFIG_USER_ONLY
42 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
43 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
45 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
46 target_ulong
*page_size_ptr
,
47 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
50 static void switch_mode(CPUARMState
*env
, int mode
);
52 static int vfp_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
54 ARMCPU
*cpu
= env_archcpu(env
);
55 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
57 /* VFP data registers are always little-endian. */
59 return gdb_get_reg64(buf
, *aa32_vfp_dreg(env
, reg
));
61 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
62 /* Aliases for Q regs. */
65 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
66 return gdb_get_reg128(buf
, q
[0], q
[1]);
69 switch (reg
- nregs
) {
70 case 0: return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); break;
71 case 1: return gdb_get_reg32(buf
, vfp_get_fpscr(env
)); break;
72 case 2: return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); break;
77 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
79 ARMCPU
*cpu
= env_archcpu(env
);
80 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
83 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
86 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
89 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
91 q
[1] = ldq_le_p(buf
+ 8);
95 switch (reg
- nregs
) {
96 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
97 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
98 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
103 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
108 /* 128 bit FP register - quads are in LE order */
109 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
110 return gdb_get_reg128(buf
, q
[1], q
[0]);
114 return gdb_get_reg32(buf
, vfp_get_fpsr(env
));
117 return gdb_get_reg32(buf
,vfp_get_fpcr(env
));
123 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
127 /* 128 bit FP register */
129 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
130 q
[0] = ldq_le_p(buf
);
131 q
[1] = ldq_le_p(buf
+ 8);
136 vfp_set_fpsr(env
, ldl_p(buf
));
140 vfp_set_fpcr(env
, ldl_p(buf
));
147 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
149 assert(ri
->fieldoffset
);
150 if (cpreg_field_is_64bit(ri
)) {
151 return CPREG_FIELD64(env
, ri
);
153 return CPREG_FIELD32(env
, ri
);
157 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
160 assert(ri
->fieldoffset
);
161 if (cpreg_field_is_64bit(ri
)) {
162 CPREG_FIELD64(env
, ri
) = value
;
164 CPREG_FIELD32(env
, ri
) = value
;
168 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
170 return (char *)env
+ ri
->fieldoffset
;
173 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
175 /* Raw read of a coprocessor register (as needed for migration, etc). */
176 if (ri
->type
& ARM_CP_CONST
) {
177 return ri
->resetvalue
;
178 } else if (ri
->raw_readfn
) {
179 return ri
->raw_readfn(env
, ri
);
180 } else if (ri
->readfn
) {
181 return ri
->readfn(env
, ri
);
183 return raw_read(env
, ri
);
187 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
190 /* Raw write of a coprocessor register (as needed for migration, etc).
191 * Note that constant registers are treated as write-ignored; the
192 * caller should check for success by whether a readback gives the
195 if (ri
->type
& ARM_CP_CONST
) {
197 } else if (ri
->raw_writefn
) {
198 ri
->raw_writefn(env
, ri
, v
);
199 } else if (ri
->writefn
) {
200 ri
->writefn(env
, ri
, v
);
202 raw_write(env
, ri
, v
);
207 * arm_get/set_gdb_*: get/set a gdb register
208 * @env: the CPU state
209 * @buf: a buffer to copy to/from
210 * @reg: register number (offset from start of group)
212 * We return the number of bytes copied
215 static int arm_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
217 ARMCPU
*cpu
= env_archcpu(env
);
218 const ARMCPRegInfo
*ri
;
221 key
= cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
[reg
];
222 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
224 if (cpreg_field_is_64bit(ri
)) {
225 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
227 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
233 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
238 #ifdef TARGET_AARCH64
239 static int arm_gdb_get_svereg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
241 ARMCPU
*cpu
= env_archcpu(env
);
244 /* The first 32 registers are the zregs */
248 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
++) {
249 len
+= gdb_get_reg128(buf
,
250 env
->vfp
.zregs
[reg
].d
[vq
* 2 + 1],
251 env
->vfp
.zregs
[reg
].d
[vq
* 2]);
256 return gdb_get_reg32(buf
, vfp_get_fpsr(env
));
258 return gdb_get_reg32(buf
, vfp_get_fpcr(env
));
259 /* then 16 predicates and the ffr */
264 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
= vq
+ 4) {
265 len
+= gdb_get_reg64(buf
, env
->vfp
.pregs
[preg
].p
[vq
/ 4]);
272 * We report in Vector Granules (VG) which is 64bit in a Z reg
273 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
275 int vq
= sve_zcr_len_for_el(env
, arm_current_el(env
)) + 1;
276 return gdb_get_reg32(buf
, vq
* 2);
279 /* gdbstub asked for something out our range */
280 qemu_log_mask(LOG_UNIMP
, "%s: out of range register %d", __func__
, reg
);
287 static int arm_gdb_set_svereg(CPUARMState
*env
, uint8_t *buf
, int reg
)
289 ARMCPU
*cpu
= env_archcpu(env
);
291 /* The first 32 registers are the zregs */
293 /* The first 32 registers are the zregs */
297 uint64_t *p
= (uint64_t *) buf
;
298 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
++) {
299 env
->vfp
.zregs
[reg
].d
[vq
* 2 + 1] = *p
++;
300 env
->vfp
.zregs
[reg
].d
[vq
* 2] = *p
++;
306 vfp_set_fpsr(env
, *(uint32_t *)buf
);
309 vfp_set_fpcr(env
, *(uint32_t *)buf
);
315 uint64_t *p
= (uint64_t *) buf
;
316 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
= vq
+ 4) {
317 env
->vfp
.pregs
[preg
].p
[vq
/ 4] = *p
++;
323 /* cannot set vg via gdbstub */
326 /* gdbstub asked for something out our range */
332 #endif /* TARGET_AARCH64 */
334 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
336 /* Return true if the regdef would cause an assertion if you called
337 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
338 * program bug for it not to have the NO_RAW flag).
339 * NB that returning false here doesn't necessarily mean that calling
340 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
341 * read/write access functions which are safe for raw use" from "has
342 * read/write access functions which have side effects but has forgotten
343 * to provide raw access functions".
344 * The tests here line up with the conditions in read/write_raw_cp_reg()
345 * and assertions in raw_read()/raw_write().
347 if ((ri
->type
& ARM_CP_CONST
) ||
349 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
355 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
357 /* Write the coprocessor state from cpu->env to the (index,value) list. */
361 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
362 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
363 const ARMCPRegInfo
*ri
;
366 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
371 if (ri
->type
& ARM_CP_NO_RAW
) {
375 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
378 * Only sync if the previous list->cpustate sync succeeded.
379 * Rather than tracking the success/failure state for every
380 * item in the list, we just recheck "does the raw write we must
381 * have made in write_list_to_cpustate() read back OK" here.
383 uint64_t oldval
= cpu
->cpreg_values
[i
];
385 if (oldval
== newval
) {
389 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
390 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
394 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
396 cpu
->cpreg_values
[i
] = newval
;
401 bool write_list_to_cpustate(ARMCPU
*cpu
)
406 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
407 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
408 uint64_t v
= cpu
->cpreg_values
[i
];
409 const ARMCPRegInfo
*ri
;
411 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
416 if (ri
->type
& ARM_CP_NO_RAW
) {
419 /* Write value and confirm it reads back as written
420 * (to catch read-only registers and partially read-only
421 * registers where the incoming migration value doesn't match)
423 write_raw_cp_reg(&cpu
->env
, ri
, v
);
424 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
431 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
433 ARMCPU
*cpu
= opaque
;
435 const ARMCPRegInfo
*ri
;
437 regidx
= *(uint32_t *)key
;
438 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
440 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
441 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
442 /* The value array need not be initialized at this point */
443 cpu
->cpreg_array_len
++;
447 static void count_cpreg(gpointer key
, gpointer opaque
)
449 ARMCPU
*cpu
= opaque
;
451 const ARMCPRegInfo
*ri
;
453 regidx
= *(uint32_t *)key
;
454 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
456 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
457 cpu
->cpreg_array_len
++;
461 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
463 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
464 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
475 void init_cpreg_list(ARMCPU
*cpu
)
477 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
478 * Note that we require cpreg_tuples[] to be sorted by key ID.
483 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
484 keys
= g_list_sort(keys
, cpreg_key_compare
);
486 cpu
->cpreg_array_len
= 0;
488 g_list_foreach(keys
, count_cpreg
, cpu
);
490 arraylen
= cpu
->cpreg_array_len
;
491 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
492 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
493 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
494 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
495 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
496 cpu
->cpreg_array_len
= 0;
498 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
500 assert(cpu
->cpreg_array_len
== arraylen
);
506 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
508 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
509 const ARMCPRegInfo
*ri
,
512 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
513 arm_is_secure_below_el3(env
)) {
514 return CP_ACCESS_TRAP_UNCATEGORIZED
;
519 /* Some secure-only AArch32 registers trap to EL3 if used from
520 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
521 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
522 * We assume that the .access field is set to PL1_RW.
524 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
525 const ARMCPRegInfo
*ri
,
528 if (arm_current_el(env
) == 3) {
531 if (arm_is_secure_below_el3(env
)) {
532 return CP_ACCESS_TRAP_EL3
;
534 /* This will be EL1 NS and EL2 NS, which just UNDEF */
535 return CP_ACCESS_TRAP_UNCATEGORIZED
;
538 /* Check for traps to "powerdown debug" registers, which are controlled
541 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
544 int el
= arm_current_el(env
);
545 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
546 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
547 (arm_hcr_el2_eff(env
) & HCR_TGE
);
549 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
550 return CP_ACCESS_TRAP_EL2
;
552 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
553 return CP_ACCESS_TRAP_EL3
;
558 /* Check for traps to "debug ROM" registers, which are controlled
559 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
561 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
564 int el
= arm_current_el(env
);
565 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
566 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
567 (arm_hcr_el2_eff(env
) & HCR_TGE
);
569 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
570 return CP_ACCESS_TRAP_EL2
;
572 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
573 return CP_ACCESS_TRAP_EL3
;
578 /* Check for traps to general debug registers, which are controlled
579 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
581 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
584 int el
= arm_current_el(env
);
585 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
586 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
587 (arm_hcr_el2_eff(env
) & HCR_TGE
);
589 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
590 return CP_ACCESS_TRAP_EL2
;
592 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
593 return CP_ACCESS_TRAP_EL3
;
598 /* Check for traps to performance monitor registers, which are controlled
599 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
601 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
604 int el
= arm_current_el(env
);
606 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
607 && !arm_is_secure_below_el3(env
)) {
608 return CP_ACCESS_TRAP_EL2
;
610 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
611 return CP_ACCESS_TRAP_EL3
;
616 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
617 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
620 if (arm_current_el(env
) == 1) {
621 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
622 if (arm_hcr_el2_eff(env
) & trap
) {
623 return CP_ACCESS_TRAP_EL2
;
629 /* Check for traps from EL1 due to HCR_EL2.TSW. */
630 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
633 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
634 return CP_ACCESS_TRAP_EL2
;
639 /* Check for traps from EL1 due to HCR_EL2.TACR. */
640 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
643 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
644 return CP_ACCESS_TRAP_EL2
;
649 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
650 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
653 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
654 return CP_ACCESS_TRAP_EL2
;
659 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
661 ARMCPU
*cpu
= env_archcpu(env
);
663 raw_write(env
, ri
, value
);
664 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
667 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
669 ARMCPU
*cpu
= env_archcpu(env
);
671 if (raw_read(env
, ri
) != value
) {
672 /* Unlike real hardware the qemu TLB uses virtual addresses,
673 * not modified virtual addresses, so this causes a TLB flush.
676 raw_write(env
, ri
, value
);
680 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
683 ARMCPU
*cpu
= env_archcpu(env
);
685 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
686 && !extended_addresses_enabled(env
)) {
687 /* For VMSA (when not using the LPAE long descriptor page table
688 * format) this register includes the ASID, so do a TLB flush.
689 * For PMSA it is purely a process ID and no action is needed.
693 raw_write(env
, ri
, value
);
696 /* IS variants of TLB operations must affect all cores */
697 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
700 CPUState
*cs
= env_cpu(env
);
702 tlb_flush_all_cpus_synced(cs
);
705 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
708 CPUState
*cs
= env_cpu(env
);
710 tlb_flush_all_cpus_synced(cs
);
713 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
716 CPUState
*cs
= env_cpu(env
);
718 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
721 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
724 CPUState
*cs
= env_cpu(env
);
726 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
730 * Non-IS variants of TLB operations are upgraded to
731 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
732 * force broadcast of these operations.
734 static bool tlb_force_broadcast(CPUARMState
*env
)
736 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
737 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
740 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
743 /* Invalidate all (TLBIALL) */
744 CPUState
*cs
= env_cpu(env
);
746 if (tlb_force_broadcast(env
)) {
747 tlb_flush_all_cpus_synced(cs
);
753 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
756 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
757 CPUState
*cs
= env_cpu(env
);
759 value
&= TARGET_PAGE_MASK
;
760 if (tlb_force_broadcast(env
)) {
761 tlb_flush_page_all_cpus_synced(cs
, value
);
763 tlb_flush_page(cs
, value
);
767 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
770 /* Invalidate by ASID (TLBIASID) */
771 CPUState
*cs
= env_cpu(env
);
773 if (tlb_force_broadcast(env
)) {
774 tlb_flush_all_cpus_synced(cs
);
780 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
783 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
784 CPUState
*cs
= env_cpu(env
);
786 value
&= TARGET_PAGE_MASK
;
787 if (tlb_force_broadcast(env
)) {
788 tlb_flush_page_all_cpus_synced(cs
, value
);
790 tlb_flush_page(cs
, value
);
794 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
797 CPUState
*cs
= env_cpu(env
);
799 tlb_flush_by_mmuidx(cs
,
801 ARMMMUIdxBit_E10_1_PAN
|
805 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
808 CPUState
*cs
= env_cpu(env
);
810 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
812 ARMMMUIdxBit_E10_1_PAN
|
817 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
820 CPUState
*cs
= env_cpu(env
);
822 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
825 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
828 CPUState
*cs
= env_cpu(env
);
830 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
833 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
836 CPUState
*cs
= env_cpu(env
);
837 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
839 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
842 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
845 CPUState
*cs
= env_cpu(env
);
846 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
848 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
852 static const ARMCPRegInfo cp_reginfo
[] = {
853 /* Define the secure and non-secure FCSE identifier CP registers
854 * separately because there is no secure bank in V8 (no _EL3). This allows
855 * the secure register to be properly reset and migrated. There is also no
856 * v8 EL1 version of the register so the non-secure instance stands alone.
859 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
860 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
861 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
862 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
863 { .name
= "FCSEIDR_S",
864 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
865 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
866 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
867 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
868 /* Define the secure and non-secure context identifier CP registers
869 * separately because there is no secure bank in V8 (no _EL3). This allows
870 * the secure register to be properly reset and migrated. In the
871 * non-secure case, the 32-bit register will have reset and migration
872 * disabled during registration as it is handled by the 64-bit instance.
874 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
875 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
876 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
877 .secure
= ARM_CP_SECSTATE_NS
,
878 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
879 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
880 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
881 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
882 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
883 .secure
= ARM_CP_SECSTATE_S
,
884 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
885 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
889 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
890 /* NB: Some of these registers exist in v8 but with more precise
891 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
893 /* MMU Domain access control / MPU write buffer control */
895 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
896 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
897 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
898 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
899 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
900 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
901 * For v6 and v5, these mappings are overly broad.
903 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
904 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
905 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
906 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
907 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
908 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
909 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
910 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
911 /* Cache maintenance ops; some of this space may be overridden later. */
912 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
913 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
914 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
918 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
919 /* Not all pre-v6 cores implemented this WFI, so this is slightly
922 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
923 .access
= PL1_W
, .type
= ARM_CP_WFI
},
927 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
928 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
929 * is UNPREDICTABLE; we choose to NOP as most implementations do).
931 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
932 .access
= PL1_W
, .type
= ARM_CP_WFI
},
933 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
934 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
935 * OMAPCP will override this space.
937 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
938 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
940 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
941 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
943 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
944 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
945 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
947 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
948 * implementing it as RAZ means the "debug architecture version" bits
949 * will read as a reserved value, which should cause Linux to not try
950 * to use the debug hardware.
952 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
953 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
954 /* MMU TLB control. Note that the wildcarding means we cover not just
955 * the unified TLB ops but also the dside/iside/inner-shareable variants.
957 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
958 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
959 .type
= ARM_CP_NO_RAW
},
960 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
961 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
962 .type
= ARM_CP_NO_RAW
},
963 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
964 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
965 .type
= ARM_CP_NO_RAW
},
966 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
967 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
968 .type
= ARM_CP_NO_RAW
},
969 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
970 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
971 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
972 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
976 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
981 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
982 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
983 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
984 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
985 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
987 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
988 /* VFP coprocessor: cp10 & cp11 [23:20] */
989 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
991 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
992 /* ASEDIS [31] bit is RAO/WI */
996 /* VFPv3 and upwards with NEON implement 32 double precision
997 * registers (D0-D31).
999 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
1000 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
1008 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1009 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1011 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
1012 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
1013 value
&= ~(0xf << 20);
1014 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
1017 env
->cp15
.cpacr_el1
= value
;
1020 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1023 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1024 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1026 uint64_t value
= env
->cp15
.cpacr_el1
;
1028 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
1029 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
1030 value
&= ~(0xf << 20);
1036 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1038 /* Call cpacr_write() so that we reset with the correct RAO bits set
1039 * for our CPU features.
1041 cpacr_write(env
, ri
, 0);
1044 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1047 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1048 /* Check if CPACR accesses are to be trapped to EL2 */
1049 if (arm_current_el(env
) == 1 &&
1050 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
1051 return CP_ACCESS_TRAP_EL2
;
1052 /* Check if CPACR accesses are to be trapped to EL3 */
1053 } else if (arm_current_el(env
) < 3 &&
1054 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
1055 return CP_ACCESS_TRAP_EL3
;
1059 return CP_ACCESS_OK
;
1062 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1065 /* Check if CPTR accesses are set to trap to EL3 */
1066 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
1067 return CP_ACCESS_TRAP_EL3
;
1070 return CP_ACCESS_OK
;
1073 static const ARMCPRegInfo v6_cp_reginfo
[] = {
1074 /* prefetch by MVA in v6, NOP in v7 */
1075 { .name
= "MVA_prefetch",
1076 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
1077 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1078 /* We need to break the TB after ISB to execute self-modifying code
1079 * correctly and also to take any pending interrupts immediately.
1080 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
1082 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
1083 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
1084 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
1085 .access
= PL0_W
, .type
= ARM_CP_NOP
},
1086 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
1087 .access
= PL0_W
, .type
= ARM_CP_NOP
},
1088 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1089 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
1090 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1091 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1093 /* Watchpoint Fault Address Register : should actually only be present
1094 * for 1136, 1176, 11MPCore.
1096 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1097 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1098 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1099 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1100 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1101 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1105 /* Definitions for the PMU registers */
1106 #define PMCRN_MASK 0xf800
1107 #define PMCRN_SHIFT 11
1116 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1117 * which can be written as 1 to trigger behaviour but which stay RAZ).
1119 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1121 #define PMXEVTYPER_P 0x80000000
1122 #define PMXEVTYPER_U 0x40000000
1123 #define PMXEVTYPER_NSK 0x20000000
1124 #define PMXEVTYPER_NSU 0x10000000
1125 #define PMXEVTYPER_NSH 0x08000000
1126 #define PMXEVTYPER_M 0x04000000
1127 #define PMXEVTYPER_MT 0x02000000
1128 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1129 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1130 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1131 PMXEVTYPER_M | PMXEVTYPER_MT | \
1132 PMXEVTYPER_EVTCOUNT)
1134 #define PMCCFILTR 0xf8000000
1135 #define PMCCFILTR_M PMXEVTYPER_M
1136 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1138 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1140 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1143 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1144 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1146 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1149 typedef struct pm_event
{
1150 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1151 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1152 bool (*supported
)(CPUARMState
*);
1154 * Retrieve the current count of the underlying event. The programmed
1155 * counters hold a difference from the return value from this function
1157 uint64_t (*get_count
)(CPUARMState
*);
1159 * Return how many nanoseconds it will take (at a minimum) for count events
1160 * to occur. A negative value indicates the counter will never overflow, or
1161 * that the counter has otherwise arranged for the overflow bit to be set
1162 * and the PMU interrupt to be raised on overflow.
1164 int64_t (*ns_per_count
)(uint64_t);
1167 static bool event_always_supported(CPUARMState
*env
)
1172 static uint64_t swinc_get_count(CPUARMState
*env
)
1175 * SW_INCR events are written directly to the pmevcntr's by writes to
1176 * PMSWINC, so there is no underlying count maintained by the PMU itself
1181 static int64_t swinc_ns_per(uint64_t ignored
)
1187 * Return the underlying cycle count for the PMU cycle counters. If we're in
1188 * usermode, simply return 0.
1190 static uint64_t cycles_get_count(CPUARMState
*env
)
1192 #ifndef CONFIG_USER_ONLY
1193 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1194 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1196 return cpu_get_host_ticks();
1200 #ifndef CONFIG_USER_ONLY
1201 static int64_t cycles_ns_per(uint64_t cycles
)
1203 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1206 static bool instructions_supported(CPUARMState
*env
)
1208 return use_icount
== 1 /* Precise instruction counting */;
1211 static uint64_t instructions_get_count(CPUARMState
*env
)
1213 return (uint64_t)cpu_get_icount_raw();
1216 static int64_t instructions_ns_per(uint64_t icount
)
1218 return cpu_icount_to_ns((int64_t)icount
);
1222 static bool pmu_8_1_events_supported(CPUARMState
*env
)
1224 /* For events which are supported in any v8.1 PMU */
1225 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
1228 static bool pmu_8_4_events_supported(CPUARMState
*env
)
1230 /* For events which are supported in any v8.1 PMU */
1231 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
1234 static uint64_t zero_event_get_count(CPUARMState
*env
)
1236 /* For events which on QEMU never fire, so their count is always zero */
1240 static int64_t zero_event_ns_per(uint64_t cycles
)
1242 /* An event which never fires can never overflow */
1246 static const pm_event pm_events
[] = {
1247 { .number
= 0x000, /* SW_INCR */
1248 .supported
= event_always_supported
,
1249 .get_count
= swinc_get_count
,
1250 .ns_per_count
= swinc_ns_per
,
1252 #ifndef CONFIG_USER_ONLY
1253 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1254 .supported
= instructions_supported
,
1255 .get_count
= instructions_get_count
,
1256 .ns_per_count
= instructions_ns_per
,
1258 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1259 .supported
= event_always_supported
,
1260 .get_count
= cycles_get_count
,
1261 .ns_per_count
= cycles_ns_per
,
1264 { .number
= 0x023, /* STALL_FRONTEND */
1265 .supported
= pmu_8_1_events_supported
,
1266 .get_count
= zero_event_get_count
,
1267 .ns_per_count
= zero_event_ns_per
,
1269 { .number
= 0x024, /* STALL_BACKEND */
1270 .supported
= pmu_8_1_events_supported
,
1271 .get_count
= zero_event_get_count
,
1272 .ns_per_count
= zero_event_ns_per
,
1274 { .number
= 0x03c, /* STALL */
1275 .supported
= pmu_8_4_events_supported
,
1276 .get_count
= zero_event_get_count
,
1277 .ns_per_count
= zero_event_ns_per
,
1282 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1283 * events (i.e. the statistical profiling extension), this implementation
1284 * should first be updated to something sparse instead of the current
1285 * supported_event_map[] array.
1287 #define MAX_EVENT_ID 0x3c
1288 #define UNSUPPORTED_EVENT UINT16_MAX
1289 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1292 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1293 * of ARM event numbers to indices in our pm_events array.
1295 * Note: Events in the 0x40XX range are not currently supported.
1297 void pmu_init(ARMCPU
*cpu
)
1302 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1305 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1306 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1311 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1312 const pm_event
*cnt
= &pm_events
[i
];
1313 assert(cnt
->number
<= MAX_EVENT_ID
);
1314 /* We do not currently support events in the 0x40xx range */
1315 assert(cnt
->number
<= 0x3f);
1317 if (cnt
->supported(&cpu
->env
)) {
1318 supported_event_map
[cnt
->number
] = i
;
1319 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1320 if (cnt
->number
& 0x20) {
1321 cpu
->pmceid1
|= event_mask
;
1323 cpu
->pmceid0
|= event_mask
;
1330 * Check at runtime whether a PMU event is supported for the current machine
1332 static bool event_supported(uint16_t number
)
1334 if (number
> MAX_EVENT_ID
) {
1337 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1340 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1343 /* Performance monitor registers user accessibility is controlled
1344 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1345 * trapping to EL2 or EL3 for other accesses.
1347 int el
= arm_current_el(env
);
1349 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1350 return CP_ACCESS_TRAP
;
1352 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1353 && !arm_is_secure_below_el3(env
)) {
1354 return CP_ACCESS_TRAP_EL2
;
1356 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1357 return CP_ACCESS_TRAP_EL3
;
1360 return CP_ACCESS_OK
;
1363 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1364 const ARMCPRegInfo
*ri
,
1367 /* ER: event counter read trap control */
1368 if (arm_feature(env
, ARM_FEATURE_V8
)
1369 && arm_current_el(env
) == 0
1370 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1372 return CP_ACCESS_OK
;
1375 return pmreg_access(env
, ri
, isread
);
1378 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1379 const ARMCPRegInfo
*ri
,
1382 /* SW: software increment write trap control */
1383 if (arm_feature(env
, ARM_FEATURE_V8
)
1384 && arm_current_el(env
) == 0
1385 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1387 return CP_ACCESS_OK
;
1390 return pmreg_access(env
, ri
, isread
);
1393 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1394 const ARMCPRegInfo
*ri
,
1397 /* ER: event counter read trap control */
1398 if (arm_feature(env
, ARM_FEATURE_V8
)
1399 && arm_current_el(env
) == 0
1400 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1401 return CP_ACCESS_OK
;
1404 return pmreg_access(env
, ri
, isread
);
1407 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1408 const ARMCPRegInfo
*ri
,
1411 /* CR: cycle counter read trap control */
1412 if (arm_feature(env
, ARM_FEATURE_V8
)
1413 && arm_current_el(env
) == 0
1414 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1416 return CP_ACCESS_OK
;
1419 return pmreg_access(env
, ri
, isread
);
1422 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1423 * the current EL, security state, and register configuration.
1425 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1428 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1429 bool enabled
, prohibited
, filtered
;
1430 bool secure
= arm_is_secure(env
);
1431 int el
= arm_current_el(env
);
1432 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1434 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1438 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1439 (counter
< hpmn
|| counter
== 31)) {
1440 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1442 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1444 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1447 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1448 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1453 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1454 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1457 if (prohibited
&& counter
== 31) {
1458 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1461 if (counter
== 31) {
1462 filter
= env
->cp15
.pmccfiltr_el0
;
1464 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1467 p
= filter
& PMXEVTYPER_P
;
1468 u
= filter
& PMXEVTYPER_U
;
1469 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1470 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1471 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1472 m
= arm_el_is_aa64(env
, 1) &&
1473 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1476 filtered
= secure
? u
: u
!= nsu
;
1477 } else if (el
== 1) {
1478 filtered
= secure
? p
: p
!= nsk
;
1479 } else if (el
== 2) {
1485 if (counter
!= 31) {
1487 * If not checking PMCCNTR, ensure the counter is setup to an event we
1490 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1491 if (!event_supported(event
)) {
1496 return enabled
&& !prohibited
&& !filtered
;
1499 static void pmu_update_irq(CPUARMState
*env
)
1501 ARMCPU
*cpu
= env_archcpu(env
);
1502 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1503 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1507 * Ensure c15_ccnt is the guest-visible count so that operations such as
1508 * enabling/disabling the counter or filtering, modifying the count itself,
1509 * etc. can be done logically. This is essentially a no-op if the counter is
1510 * not enabled at the time of the call.
1512 static void pmccntr_op_start(CPUARMState
*env
)
1514 uint64_t cycles
= cycles_get_count(env
);
1516 if (pmu_counter_enabled(env
, 31)) {
1517 uint64_t eff_cycles
= cycles
;
1518 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1519 /* Increment once every 64 processor clock cycles */
1523 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1525 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1526 1ull << 63 : 1ull << 31;
1527 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1528 env
->cp15
.c9_pmovsr
|= (1 << 31);
1529 pmu_update_irq(env
);
1532 env
->cp15
.c15_ccnt
= new_pmccntr
;
1534 env
->cp15
.c15_ccnt_delta
= cycles
;
1538 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1539 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1542 static void pmccntr_op_finish(CPUARMState
*env
)
1544 if (pmu_counter_enabled(env
, 31)) {
1545 #ifndef CONFIG_USER_ONLY
1546 /* Calculate when the counter will next overflow */
1547 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1548 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1549 remaining_cycles
= (uint32_t)remaining_cycles
;
1551 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1553 if (overflow_in
> 0) {
1554 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1556 ARMCPU
*cpu
= env_archcpu(env
);
1557 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1561 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1562 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1563 /* Increment once every 64 processor clock cycles */
1566 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1570 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1573 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1575 if (event_supported(event
)) {
1576 uint16_t event_idx
= supported_event_map
[event
];
1577 count
= pm_events
[event_idx
].get_count(env
);
1580 if (pmu_counter_enabled(env
, counter
)) {
1581 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1583 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1584 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1585 pmu_update_irq(env
);
1587 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1589 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1592 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1594 if (pmu_counter_enabled(env
, counter
)) {
1595 #ifndef CONFIG_USER_ONLY
1596 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1597 uint16_t event_idx
= supported_event_map
[event
];
1598 uint64_t delta
= UINT32_MAX
-
1599 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1600 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1602 if (overflow_in
> 0) {
1603 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1605 ARMCPU
*cpu
= env_archcpu(env
);
1606 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1610 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1611 env
->cp15
.c14_pmevcntr
[counter
];
1615 void pmu_op_start(CPUARMState
*env
)
1618 pmccntr_op_start(env
);
1619 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1620 pmevcntr_op_start(env
, i
);
1624 void pmu_op_finish(CPUARMState
*env
)
1627 pmccntr_op_finish(env
);
1628 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1629 pmevcntr_op_finish(env
, i
);
1633 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1635 pmu_op_start(&cpu
->env
);
1638 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1640 pmu_op_finish(&cpu
->env
);
1643 void arm_pmu_timer_cb(void *opaque
)
1645 ARMCPU
*cpu
= opaque
;
1648 * Update all the counter values based on the current underlying counts,
1649 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1650 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1651 * counter may expire.
1653 pmu_op_start(&cpu
->env
);
1654 pmu_op_finish(&cpu
->env
);
1657 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1662 if (value
& PMCRC
) {
1663 /* The counter has been reset */
1664 env
->cp15
.c15_ccnt
= 0;
1667 if (value
& PMCRP
) {
1669 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1670 env
->cp15
.c14_pmevcntr
[i
] = 0;
1674 env
->cp15
.c9_pmcr
&= ~PMCR_WRITEABLE_MASK
;
1675 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITEABLE_MASK
);
1680 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1684 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1685 /* Increment a counter's count iff: */
1686 if ((value
& (1 << i
)) && /* counter's bit is set */
1687 /* counter is enabled and not filtered */
1688 pmu_counter_enabled(env
, i
) &&
1689 /* counter is SW_INCR */
1690 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1691 pmevcntr_op_start(env
, i
);
1694 * Detect if this write causes an overflow since we can't predict
1695 * PMSWINC overflows like we can for other events
1697 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1699 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1700 env
->cp15
.c9_pmovsr
|= (1 << i
);
1701 pmu_update_irq(env
);
1704 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1706 pmevcntr_op_finish(env
, i
);
1711 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1714 pmccntr_op_start(env
);
1715 ret
= env
->cp15
.c15_ccnt
;
1716 pmccntr_op_finish(env
);
1720 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1723 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1724 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1725 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1728 env
->cp15
.c9_pmselr
= value
& 0x1f;
1731 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1734 pmccntr_op_start(env
);
1735 env
->cp15
.c15_ccnt
= value
;
1736 pmccntr_op_finish(env
);
1739 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1742 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1744 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1747 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1750 pmccntr_op_start(env
);
1751 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1752 pmccntr_op_finish(env
);
1755 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1758 pmccntr_op_start(env
);
1759 /* M is not accessible from AArch32 */
1760 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1761 (value
& PMCCFILTR
);
1762 pmccntr_op_finish(env
);
1765 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1767 /* M is not visible in AArch32 */
1768 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1771 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1774 value
&= pmu_counter_mask(env
);
1775 env
->cp15
.c9_pmcnten
|= value
;
1778 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1781 value
&= pmu_counter_mask(env
);
1782 env
->cp15
.c9_pmcnten
&= ~value
;
1785 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1788 value
&= pmu_counter_mask(env
);
1789 env
->cp15
.c9_pmovsr
&= ~value
;
1790 pmu_update_irq(env
);
1793 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1796 value
&= pmu_counter_mask(env
);
1797 env
->cp15
.c9_pmovsr
|= value
;
1798 pmu_update_irq(env
);
1801 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1802 uint64_t value
, const uint8_t counter
)
1804 if (counter
== 31) {
1805 pmccfiltr_write(env
, ri
, value
);
1806 } else if (counter
< pmu_num_counters(env
)) {
1807 pmevcntr_op_start(env
, counter
);
1810 * If this counter's event type is changing, store the current
1811 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1812 * pmevcntr_op_finish has the correct baseline when it converts back to
1815 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1816 PMXEVTYPER_EVTCOUNT
;
1817 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1818 if (old_event
!= new_event
) {
1820 if (event_supported(new_event
)) {
1821 uint16_t event_idx
= supported_event_map
[new_event
];
1822 count
= pm_events
[event_idx
].get_count(env
);
1824 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1827 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1828 pmevcntr_op_finish(env
, counter
);
1830 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1831 * PMSELR value is equal to or greater than the number of implemented
1832 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1836 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1837 const uint8_t counter
)
1839 if (counter
== 31) {
1840 return env
->cp15
.pmccfiltr_el0
;
1841 } else if (counter
< pmu_num_counters(env
)) {
1842 return env
->cp15
.c14_pmevtyper
[counter
];
1845 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1846 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1852 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1855 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1856 pmevtyper_write(env
, ri
, value
, counter
);
1859 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1862 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1863 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1866 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1867 * pmu_op_finish calls when loading saved state for a migration. Because
1868 * we're potentially updating the type of event here, the value written to
1869 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1870 * different counter type. Therefore, we need to set this value to the
1871 * current count for the counter type we're writing so that pmu_op_finish
1872 * has the correct count for its calculation.
1874 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1875 if (event_supported(event
)) {
1876 uint16_t event_idx
= supported_event_map
[event
];
1877 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1878 pm_events
[event_idx
].get_count(env
);
1882 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1884 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1885 return pmevtyper_read(env
, ri
, counter
);
1888 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1891 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1894 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1896 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1899 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1900 uint64_t value
, uint8_t counter
)
1902 if (counter
< pmu_num_counters(env
)) {
1903 pmevcntr_op_start(env
, counter
);
1904 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1905 pmevcntr_op_finish(env
, counter
);
1908 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1909 * are CONSTRAINED UNPREDICTABLE.
1913 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1916 if (counter
< pmu_num_counters(env
)) {
1918 pmevcntr_op_start(env
, counter
);
1919 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1920 pmevcntr_op_finish(env
, counter
);
1923 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1924 * are CONSTRAINED UNPREDICTABLE. */
1929 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1932 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1933 pmevcntr_write(env
, ri
, value
, counter
);
1936 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1938 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1939 return pmevcntr_read(env
, ri
, counter
);
1942 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1945 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1946 assert(counter
< pmu_num_counters(env
));
1947 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1948 pmevcntr_write(env
, ri
, value
, counter
);
1951 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1953 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1954 assert(counter
< pmu_num_counters(env
));
1955 return env
->cp15
.c14_pmevcntr
[counter
];
1958 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1961 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1964 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1966 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1969 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1972 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1973 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1975 env
->cp15
.c9_pmuserenr
= value
& 1;
1979 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1982 /* We have no event counters so only the C bit can be changed */
1983 value
&= pmu_counter_mask(env
);
1984 env
->cp15
.c9_pminten
|= value
;
1985 pmu_update_irq(env
);
1988 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1991 value
&= pmu_counter_mask(env
);
1992 env
->cp15
.c9_pminten
&= ~value
;
1993 pmu_update_irq(env
);
1996 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1999 /* Note that even though the AArch64 view of this register has bits
2000 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
2001 * architectural requirements for bits which are RES0 only in some
2002 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
2003 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
2005 raw_write(env
, ri
, value
& ~0x1FULL
);
2008 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2010 /* Begin with base v8.0 state. */
2011 uint32_t valid_mask
= 0x3fff;
2012 ARMCPU
*cpu
= env_archcpu(env
);
2014 if (ri
->state
== ARM_CP_STATE_AA64
) {
2015 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
2016 valid_mask
&= ~SCR_NET
;
2018 if (cpu_isar_feature(aa64_lor
, cpu
)) {
2019 valid_mask
|= SCR_TLOR
;
2021 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
2022 valid_mask
|= SCR_API
| SCR_APK
;
2024 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2025 valid_mask
|= SCR_ATA
;
2028 valid_mask
&= ~(SCR_RW
| SCR_ST
);
2031 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2032 valid_mask
&= ~SCR_HCE
;
2034 /* On ARMv7, SMD (or SCD as it is called in v7) is only
2035 * supported if EL2 exists. The bit is UNK/SBZP when
2036 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
2037 * when EL2 is unavailable.
2038 * On ARMv8, this bit is always available.
2040 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2041 !arm_feature(env
, ARM_FEATURE_V8
)) {
2042 valid_mask
&= ~SCR_SMD
;
2046 /* Clear all-context RES0 bits. */
2047 value
&= valid_mask
;
2048 raw_write(env
, ri
, value
);
2051 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
2052 const ARMCPRegInfo
*ri
,
2055 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
2056 return CP_ACCESS_TRAP_EL2
;
2059 return CP_ACCESS_OK
;
2062 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2064 ARMCPU
*cpu
= env_archcpu(env
);
2066 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
2069 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
2070 ri
->secure
& ARM_CP_SECSTATE_S
);
2072 return cpu
->ccsidr
[index
];
2075 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2078 raw_write(env
, ri
, value
& 0xf);
2081 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2083 CPUState
*cs
= env_cpu(env
);
2084 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
2086 bool allow_virt
= (arm_current_el(env
) == 1 &&
2087 (!arm_is_secure_below_el3(env
) ||
2088 (env
->cp15
.scr_el3
& SCR_EEL2
)));
2090 if (allow_virt
&& (hcr_el2
& HCR_IMO
)) {
2091 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2095 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2100 if (allow_virt
&& (hcr_el2
& HCR_FMO
)) {
2101 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2105 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2110 /* External aborts are not possible in QEMU so A bit is always clear */
2114 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2117 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2118 return CP_ACCESS_TRAP_EL2
;
2121 return CP_ACCESS_OK
;
2124 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2127 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2128 return access_aa64_tid1(env
, ri
, isread
);
2131 return CP_ACCESS_OK
;
2134 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2135 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2136 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2137 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2138 /* Performance monitors are implementation defined in v7,
2139 * but with an ARM recommended set of registers, which we
2142 * Performance registers fall into three categories:
2143 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2144 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2145 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2146 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2147 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2149 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2150 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2151 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2152 .writefn
= pmcntenset_write
,
2153 .accessfn
= pmreg_access
,
2154 .raw_writefn
= raw_write
},
2155 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
2156 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2157 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2158 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2159 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2160 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2162 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2163 .accessfn
= pmreg_access
,
2164 .writefn
= pmcntenclr_write
,
2165 .type
= ARM_CP_ALIAS
},
2166 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2167 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2168 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2169 .type
= ARM_CP_ALIAS
,
2170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2171 .writefn
= pmcntenclr_write
},
2172 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2173 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2174 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2175 .accessfn
= pmreg_access
,
2176 .writefn
= pmovsr_write
,
2177 .raw_writefn
= raw_write
},
2178 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2179 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2180 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2181 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2182 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2183 .writefn
= pmovsr_write
,
2184 .raw_writefn
= raw_write
},
2185 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2186 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2187 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2188 .writefn
= pmswinc_write
},
2189 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2190 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2191 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2192 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2193 .writefn
= pmswinc_write
},
2194 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2195 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2196 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2197 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2198 .raw_writefn
= raw_write
},
2199 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2200 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2201 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2202 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2203 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2204 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2205 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2206 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2207 .accessfn
= pmreg_access_ccntr
},
2208 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2209 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2210 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2212 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2213 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2214 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2215 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2216 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2217 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2218 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2220 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2221 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2222 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2223 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2225 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2227 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2228 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2229 .accessfn
= pmreg_access
,
2230 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2231 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2232 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2233 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2234 .accessfn
= pmreg_access
,
2235 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2236 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2237 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2238 .accessfn
= pmreg_access_xevcntr
,
2239 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2240 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2241 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2242 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2243 .accessfn
= pmreg_access_xevcntr
,
2244 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2245 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2246 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2247 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2249 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2250 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2251 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2252 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2253 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2255 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2256 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2257 .access
= PL1_RW
, .accessfn
= access_tpm
,
2258 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2259 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2261 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2262 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2263 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2264 .access
= PL1_RW
, .accessfn
= access_tpm
,
2266 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2267 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2268 .resetvalue
= 0x0 },
2269 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2270 .access
= PL1_RW
, .accessfn
= access_tpm
,
2271 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2272 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2273 .writefn
= pmintenclr_write
, },
2274 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2275 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2276 .access
= PL1_RW
, .accessfn
= access_tpm
,
2277 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2279 .writefn
= pmintenclr_write
},
2280 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2281 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2283 .accessfn
= access_aa64_tid2
,
2284 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2285 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2286 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2288 .accessfn
= access_aa64_tid2
,
2289 .writefn
= csselr_write
, .resetvalue
= 0,
2290 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2291 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2292 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2293 * just RAZ for all cores:
2295 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2296 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2297 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2298 .accessfn
= access_aa64_tid1
,
2300 /* Auxiliary fault status registers: these also are IMPDEF, and we
2301 * choose to RAZ/WI for all cores.
2303 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2304 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2305 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2306 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2307 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2308 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2309 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2310 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2311 /* MAIR can just read-as-written because we don't implement caches
2312 * and so don't need to care about memory attributes.
2314 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2315 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2316 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2317 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2319 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2320 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2321 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2323 /* For non-long-descriptor page tables these are PRRR and NMRR;
2324 * regardless they still act as reads-as-written for QEMU.
2326 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2327 * allows them to assign the correct fieldoffset based on the endianness
2328 * handled in the field definitions.
2330 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2331 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2332 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2333 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2334 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2335 .resetfn
= arm_cp_reset_ignore
},
2336 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2337 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2338 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2339 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2340 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2341 .resetfn
= arm_cp_reset_ignore
},
2342 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2343 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2344 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2345 /* 32 bit ITLB invalidates */
2346 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2347 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2348 .writefn
= tlbiall_write
},
2349 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2350 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2351 .writefn
= tlbimva_write
},
2352 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2353 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2354 .writefn
= tlbiasid_write
},
2355 /* 32 bit DTLB invalidates */
2356 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2357 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2358 .writefn
= tlbiall_write
},
2359 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2360 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2361 .writefn
= tlbimva_write
},
2362 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2363 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2364 .writefn
= tlbiasid_write
},
2365 /* 32 bit TLB invalidates */
2366 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2367 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2368 .writefn
= tlbiall_write
},
2369 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2370 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2371 .writefn
= tlbimva_write
},
2372 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2373 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2374 .writefn
= tlbiasid_write
},
2375 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2376 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2377 .writefn
= tlbimvaa_write
},
2381 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2382 /* 32 bit TLB invalidates, Inner Shareable */
2383 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2384 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2385 .writefn
= tlbiall_is_write
},
2386 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2387 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2388 .writefn
= tlbimva_is_write
},
2389 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2390 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2391 .writefn
= tlbiasid_is_write
},
2392 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2393 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2394 .writefn
= tlbimvaa_is_write
},
2398 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2399 /* PMOVSSET is not implemented in v7 before v7ve */
2400 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2401 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2402 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2403 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2404 .writefn
= pmovsset_write
,
2405 .raw_writefn
= raw_write
},
2406 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2407 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2408 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2409 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2410 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2411 .writefn
= pmovsset_write
,
2412 .raw_writefn
= raw_write
},
2416 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2423 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2426 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2427 return CP_ACCESS_TRAP
;
2429 return CP_ACCESS_OK
;
2432 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2433 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2434 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2436 .writefn
= teecr_write
},
2437 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2438 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2439 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2443 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2444 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2445 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2447 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2448 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2450 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2451 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2452 .resetfn
= arm_cp_reset_ignore
},
2453 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2454 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2455 .access
= PL0_R
|PL1_W
,
2456 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2458 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2459 .access
= PL0_R
|PL1_W
,
2460 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2461 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2462 .resetfn
= arm_cp_reset_ignore
},
2463 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2464 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2466 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2467 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2469 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2470 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2475 #ifndef CONFIG_USER_ONLY
2477 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2480 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2481 * Writable only at the highest implemented exception level.
2483 int el
= arm_current_el(env
);
2489 hcr
= arm_hcr_el2_eff(env
);
2490 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2491 cntkctl
= env
->cp15
.cnthctl_el2
;
2493 cntkctl
= env
->cp15
.c14_cntkctl
;
2495 if (!extract32(cntkctl
, 0, 2)) {
2496 return CP_ACCESS_TRAP
;
2500 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2501 arm_is_secure_below_el3(env
)) {
2502 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2503 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2511 if (!isread
&& el
< arm_highest_el(env
)) {
2512 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2515 return CP_ACCESS_OK
;
2518 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2521 unsigned int cur_el
= arm_current_el(env
);
2522 bool secure
= arm_is_secure(env
);
2523 uint64_t hcr
= arm_hcr_el2_eff(env
);
2527 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2528 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2529 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2530 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2533 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2534 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2535 return CP_ACCESS_TRAP
;
2538 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2539 if (hcr
& HCR_E2H
) {
2540 if (timeridx
== GTIMER_PHYS
&&
2541 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2542 return CP_ACCESS_TRAP_EL2
;
2545 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2546 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2547 timeridx
== GTIMER_PHYS
&& !secure
&&
2548 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2549 return CP_ACCESS_TRAP_EL2
;
2555 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2556 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2557 timeridx
== GTIMER_PHYS
&& !secure
&&
2559 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2560 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2561 return CP_ACCESS_TRAP_EL2
;
2565 return CP_ACCESS_OK
;
2568 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2571 unsigned int cur_el
= arm_current_el(env
);
2572 bool secure
= arm_is_secure(env
);
2573 uint64_t hcr
= arm_hcr_el2_eff(env
);
2577 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2578 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2579 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2580 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2584 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2585 * EL0 if EL0[PV]TEN is zero.
2587 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2588 return CP_ACCESS_TRAP
;
2593 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2594 timeridx
== GTIMER_PHYS
&& !secure
) {
2595 if (hcr
& HCR_E2H
) {
2596 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2597 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2598 return CP_ACCESS_TRAP_EL2
;
2601 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2602 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2603 return CP_ACCESS_TRAP_EL2
;
2609 return CP_ACCESS_OK
;
2612 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2613 const ARMCPRegInfo
*ri
,
2616 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2619 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2620 const ARMCPRegInfo
*ri
,
2623 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2626 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2629 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2632 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2635 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2638 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2639 const ARMCPRegInfo
*ri
,
2642 /* The AArch64 register view of the secure physical timer is
2643 * always accessible from EL3, and configurably accessible from
2646 switch (arm_current_el(env
)) {
2648 if (!arm_is_secure(env
)) {
2649 return CP_ACCESS_TRAP
;
2651 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2652 return CP_ACCESS_TRAP_EL3
;
2654 return CP_ACCESS_OK
;
2657 return CP_ACCESS_TRAP
;
2659 return CP_ACCESS_OK
;
2661 g_assert_not_reached();
2665 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2667 ARMCPU
*cpu
= env_archcpu(env
);
2669 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2672 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2674 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2677 /* Timer enabled: calculate and set current ISTATUS, irq, and
2678 * reset timer to when ISTATUS next has to change
2680 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2681 cpu
->env
.cp15
.cntvoff_el2
: 0;
2682 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2683 /* Note that this must be unsigned 64 bit arithmetic: */
2684 int istatus
= count
- offset
>= gt
->cval
;
2688 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2690 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2691 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2694 /* Next transition is when count rolls back over to zero */
2695 nexttick
= UINT64_MAX
;
2697 /* Next transition is when we hit cval */
2698 nexttick
= gt
->cval
+ offset
;
2700 /* Note that the desired next expiry time might be beyond the
2701 * signed-64-bit range of a QEMUTimer -- in this case we just
2702 * set the timer for as far in the future as possible. When the
2703 * timer expires we will reset the timer for any remaining period.
2705 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2706 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2708 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2710 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2712 /* Timer disabled: ISTATUS and timer output always clear */
2714 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2715 timer_del(cpu
->gt_timer
[timeridx
]);
2716 trace_arm_gt_recalc_disabled(timeridx
);
2720 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2723 ARMCPU
*cpu
= env_archcpu(env
);
2725 timer_del(cpu
->gt_timer
[timeridx
]);
2728 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2730 return gt_get_countervalue(env
);
2733 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2737 switch (arm_current_el(env
)) {
2739 hcr
= arm_hcr_el2_eff(env
);
2740 if (hcr
& HCR_E2H
) {
2745 hcr
= arm_hcr_el2_eff(env
);
2746 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2752 return env
->cp15
.cntvoff_el2
;
2755 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2757 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2760 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2764 trace_arm_gt_cval_write(timeridx
, value
);
2765 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2766 gt_recalc_timer(env_archcpu(env
), timeridx
);
2769 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2772 uint64_t offset
= 0;
2776 case GTIMER_HYPVIRT
:
2777 offset
= gt_virt_cnt_offset(env
);
2781 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2782 (gt_get_countervalue(env
) - offset
));
2785 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2789 uint64_t offset
= 0;
2793 case GTIMER_HYPVIRT
:
2794 offset
= gt_virt_cnt_offset(env
);
2798 trace_arm_gt_tval_write(timeridx
, value
);
2799 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2800 sextract64(value
, 0, 32);
2801 gt_recalc_timer(env_archcpu(env
), timeridx
);
2804 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2808 ARMCPU
*cpu
= env_archcpu(env
);
2809 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2811 trace_arm_gt_ctl_write(timeridx
, value
);
2812 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2813 if ((oldval
^ value
) & 1) {
2814 /* Enable toggled */
2815 gt_recalc_timer(cpu
, timeridx
);
2816 } else if ((oldval
^ value
) & 2) {
2817 /* IMASK toggled: don't need to recalculate,
2818 * just set the interrupt line based on ISTATUS
2820 int irqstate
= (oldval
& 4) && !(value
& 2);
2822 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2823 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2827 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2829 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2832 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2835 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2838 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2840 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2843 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2846 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2849 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2852 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2855 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2857 switch (arm_mmu_idx(env
)) {
2858 case ARMMMUIdx_E20_0
:
2859 case ARMMMUIdx_E20_2
:
2860 case ARMMMUIdx_E20_2_PAN
:
2867 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2869 switch (arm_mmu_idx(env
)) {
2870 case ARMMMUIdx_E20_0
:
2871 case ARMMMUIdx_E20_2
:
2872 case ARMMMUIdx_E20_2_PAN
:
2873 return GTIMER_HYPVIRT
;
2879 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2880 const ARMCPRegInfo
*ri
)
2882 int timeridx
= gt_phys_redir_timeridx(env
);
2883 return env
->cp15
.c14_timer
[timeridx
].cval
;
2886 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2889 int timeridx
= gt_phys_redir_timeridx(env
);
2890 gt_cval_write(env
, ri
, timeridx
, value
);
2893 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2894 const ARMCPRegInfo
*ri
)
2896 int timeridx
= gt_phys_redir_timeridx(env
);
2897 return gt_tval_read(env
, ri
, timeridx
);
2900 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2903 int timeridx
= gt_phys_redir_timeridx(env
);
2904 gt_tval_write(env
, ri
, timeridx
, value
);
2907 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2908 const ARMCPRegInfo
*ri
)
2910 int timeridx
= gt_phys_redir_timeridx(env
);
2911 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2914 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2917 int timeridx
= gt_phys_redir_timeridx(env
);
2918 gt_ctl_write(env
, ri
, timeridx
, value
);
2921 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2923 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2926 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2929 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2932 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2934 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2937 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2940 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2943 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2946 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2949 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2952 ARMCPU
*cpu
= env_archcpu(env
);
2954 trace_arm_gt_cntvoff_write(value
);
2955 raw_write(env
, ri
, value
);
2956 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2959 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2960 const ARMCPRegInfo
*ri
)
2962 int timeridx
= gt_virt_redir_timeridx(env
);
2963 return env
->cp15
.c14_timer
[timeridx
].cval
;
2966 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2969 int timeridx
= gt_virt_redir_timeridx(env
);
2970 gt_cval_write(env
, ri
, timeridx
, value
);
2973 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2974 const ARMCPRegInfo
*ri
)
2976 int timeridx
= gt_virt_redir_timeridx(env
);
2977 return gt_tval_read(env
, ri
, timeridx
);
2980 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2983 int timeridx
= gt_virt_redir_timeridx(env
);
2984 gt_tval_write(env
, ri
, timeridx
, value
);
2987 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2988 const ARMCPRegInfo
*ri
)
2990 int timeridx
= gt_virt_redir_timeridx(env
);
2991 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2994 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2997 int timeridx
= gt_virt_redir_timeridx(env
);
2998 gt_ctl_write(env
, ri
, timeridx
, value
);
3001 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3003 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3006 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3009 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3012 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3014 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3017 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3020 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3023 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3026 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3029 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3031 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3034 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3037 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3040 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3042 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3045 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3048 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3051 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3054 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3057 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3059 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3062 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3065 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3068 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3070 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3073 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3076 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3079 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3082 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3085 void arm_gt_ptimer_cb(void *opaque
)
3087 ARMCPU
*cpu
= opaque
;
3089 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3092 void arm_gt_vtimer_cb(void *opaque
)
3094 ARMCPU
*cpu
= opaque
;
3096 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3099 void arm_gt_htimer_cb(void *opaque
)
3101 ARMCPU
*cpu
= opaque
;
3103 gt_recalc_timer(cpu
, GTIMER_HYP
);
3106 void arm_gt_stimer_cb(void *opaque
)
3108 ARMCPU
*cpu
= opaque
;
3110 gt_recalc_timer(cpu
, GTIMER_SEC
);
3113 void arm_gt_hvtimer_cb(void *opaque
)
3115 ARMCPU
*cpu
= opaque
;
3117 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3120 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3122 ARMCPU
*cpu
= env_archcpu(env
);
3124 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3127 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3128 /* Note that CNTFRQ is purely reads-as-written for the benefit
3129 * of software; writing it doesn't actually change the timer frequency.
3130 * Our reset value matches the fixed frequency we implement the timer at.
3132 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3133 .type
= ARM_CP_ALIAS
,
3134 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3135 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3137 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3138 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3139 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3141 .resetfn
= arm_gt_cntfrq_reset
,
3143 /* overall control: mostly access permissions */
3144 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3145 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3147 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3150 /* per-timer control */
3151 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3152 .secure
= ARM_CP_SECSTATE_NS
,
3153 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3154 .accessfn
= gt_ptimer_access
,
3155 .fieldoffset
= offsetoflow32(CPUARMState
,
3156 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3157 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3158 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3160 { .name
= "CNTP_CTL_S",
3161 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3162 .secure
= ARM_CP_SECSTATE_S
,
3163 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3164 .accessfn
= gt_ptimer_access
,
3165 .fieldoffset
= offsetoflow32(CPUARMState
,
3166 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3167 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3169 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3170 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3171 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3172 .accessfn
= gt_ptimer_access
,
3173 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3175 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3176 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3178 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3179 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3180 .accessfn
= gt_vtimer_access
,
3181 .fieldoffset
= offsetoflow32(CPUARMState
,
3182 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3183 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3184 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3186 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3187 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3188 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3189 .accessfn
= gt_vtimer_access
,
3190 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3192 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3193 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3195 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3196 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3197 .secure
= ARM_CP_SECSTATE_NS
,
3198 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3199 .accessfn
= gt_ptimer_access
,
3200 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3202 { .name
= "CNTP_TVAL_S",
3203 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3204 .secure
= ARM_CP_SECSTATE_S
,
3205 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3206 .accessfn
= gt_ptimer_access
,
3207 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3209 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3210 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3211 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3212 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3213 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3215 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3216 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3217 .accessfn
= gt_vtimer_access
,
3218 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3220 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3221 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3222 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3223 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3224 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3226 /* The counter itself */
3227 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3228 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3229 .accessfn
= gt_pct_access
,
3230 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3232 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3233 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3234 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3235 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3237 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3238 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3239 .accessfn
= gt_vct_access
,
3240 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3242 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3243 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3244 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3245 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3247 /* Comparison value, indicating when the timer goes off */
3248 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3249 .secure
= ARM_CP_SECSTATE_NS
,
3251 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3252 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3253 .accessfn
= gt_ptimer_access
,
3254 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3255 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3257 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3258 .secure
= ARM_CP_SECSTATE_S
,
3260 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3261 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3262 .accessfn
= gt_ptimer_access
,
3263 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3265 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3266 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3269 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3270 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3271 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3272 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3274 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3276 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3278 .accessfn
= gt_vtimer_access
,
3279 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3280 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3282 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3283 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3286 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3287 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3288 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3289 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3291 /* Secure timer -- this is actually restricted to only EL3
3292 * and configurably Secure-EL1 via the accessfn.
3294 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3295 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3296 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3297 .accessfn
= gt_stimer_access
,
3298 .readfn
= gt_sec_tval_read
,
3299 .writefn
= gt_sec_tval_write
,
3300 .resetfn
= gt_sec_timer_reset
,
3302 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3303 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3304 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3305 .accessfn
= gt_stimer_access
,
3306 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3308 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3310 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3311 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3312 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3313 .accessfn
= gt_stimer_access
,
3314 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3315 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3320 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3323 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3324 return CP_ACCESS_TRAP
;
3326 return CP_ACCESS_OK
;
3331 /* In user-mode most of the generic timer registers are inaccessible
3332 * however modern kernels (4.12+) allow access to cntvct_el0
3335 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3337 ARMCPU
*cpu
= env_archcpu(env
);
3339 /* Currently we have no support for QEMUTimer in linux-user so we
3340 * can't call gt_get_countervalue(env), instead we directly
3341 * call the lower level functions.
3343 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3346 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3347 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3348 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3349 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3350 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3351 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3353 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3354 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3355 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3356 .readfn
= gt_virt_cnt_read
,
3363 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3365 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3366 raw_write(env
, ri
, value
);
3367 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3368 raw_write(env
, ri
, value
& 0xfffff6ff);
3370 raw_write(env
, ri
, value
& 0xfffff1ff);
3374 #ifndef CONFIG_USER_ONLY
3375 /* get_phys_addr() isn't present for user-mode-only targets */
3377 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3381 /* The ATS12NSO* operations must trap to EL3 if executed in
3382 * Secure EL1 (which can only happen if EL3 is AArch64).
3383 * They are simply UNDEF if executed from NS EL1.
3384 * They function normally from EL2 or EL3.
3386 if (arm_current_el(env
) == 1) {
3387 if (arm_is_secure_below_el3(env
)) {
3388 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3390 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3393 return CP_ACCESS_OK
;
3397 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3398 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3401 target_ulong page_size
;
3405 bool format64
= false;
3406 MemTxAttrs attrs
= {};
3407 ARMMMUFaultInfo fi
= {};
3408 ARMCacheAttrs cacheattrs
= {};
3410 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3411 &prot
, &page_size
, &fi
, &cacheattrs
);
3415 * Some kinds of translation fault must cause exceptions rather
3416 * than being reported in the PAR.
3418 int current_el
= arm_current_el(env
);
3420 uint32_t syn
, fsr
, fsc
;
3421 bool take_exc
= false;
3423 if (fi
.s1ptw
&& current_el
== 1 && !arm_is_secure(env
)
3424 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3426 * Synchronous stage 2 fault on an access made as part of the
3427 * translation table walk for AT S1E0* or AT S1E1* insn
3428 * executed from NS EL1. If this is a synchronous external abort
3429 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3430 * to EL3. Otherwise the fault is taken as an exception to EL2,
3431 * and HPFAR_EL2 holds the faulting IPA.
3433 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3434 (env
->cp15
.scr_el3
& SCR_EA
)) {
3437 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3441 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3443 * Synchronous external aborts during a translation table walk
3444 * are taken as Data Abort exceptions.
3447 if (current_el
== 3) {
3453 target_el
= exception_target_el(env
);
3459 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3460 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3461 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3462 fsr
= arm_fi_to_lfsc(&fi
);
3463 fsc
= extract32(fsr
, 0, 6);
3465 fsr
= arm_fi_to_sfsc(&fi
);
3469 * Report exception with ESR indicating a fault due to a
3470 * translation table walk for a cache maintenance instruction.
3472 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3473 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3474 env
->exception
.vaddress
= value
;
3475 env
->exception
.fsr
= fsr
;
3476 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3482 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3485 * * TTBCR.EAE determines whether the result is returned using the
3486 * 32-bit or the 64-bit PAR format
3487 * * Instructions executed in Hyp mode always use the 64bit format
3489 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3490 * * The Non-secure TTBCR.EAE bit is set to 1
3491 * * The implementation includes EL2, and the value of HCR.VM is 1
3493 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3495 * ATS1Hx always uses the 64bit format.
3497 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3499 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3500 if (mmu_idx
== ARMMMUIdx_E10_0
||
3501 mmu_idx
== ARMMMUIdx_E10_1
||
3502 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3503 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3505 format64
|= arm_current_el(env
) == 2;
3511 /* Create a 64-bit PAR */
3512 par64
= (1 << 11); /* LPAE bit always set */
3514 par64
|= phys_addr
& ~0xfffULL
;
3515 if (!attrs
.secure
) {
3516 par64
|= (1 << 9); /* NS */
3518 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3519 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3521 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3524 par64
|= (fsr
& 0x3f) << 1; /* FS */
3526 par64
|= (1 << 9); /* S */
3529 par64
|= (1 << 8); /* PTW */
3533 /* fsr is a DFSR/IFSR value for the short descriptor
3534 * translation table format (with WnR always clear).
3535 * Convert it to a 32-bit PAR.
3538 /* We do not set any attribute bits in the PAR */
3539 if (page_size
== (1 << 24)
3540 && arm_feature(env
, ARM_FEATURE_V7
)) {
3541 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3543 par64
= phys_addr
& 0xfffff000;
3545 if (!attrs
.secure
) {
3546 par64
|= (1 << 9); /* NS */
3549 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3551 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3552 ((fsr
& 0xf) << 1) | 1;
3557 #endif /* CONFIG_TCG */
3559 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3562 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3565 int el
= arm_current_el(env
);
3566 bool secure
= arm_is_secure_below_el3(env
);
3568 switch (ri
->opc2
& 6) {
3570 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3573 mmu_idx
= ARMMMUIdx_SE3
;
3576 g_assert(!secure
); /* TODO: ARMv8.4-SecEL2 */
3579 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3580 mmu_idx
= (secure
? ARMMMUIdx_SE10_1_PAN
3581 : ARMMMUIdx_Stage1_E1_PAN
);
3583 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_Stage1_E1
;
3587 g_assert_not_reached();
3591 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3594 mmu_idx
= ARMMMUIdx_SE10_0
;
3597 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3600 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_Stage1_E0
;
3603 g_assert_not_reached();
3607 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3608 mmu_idx
= ARMMMUIdx_E10_1
;
3611 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3612 mmu_idx
= ARMMMUIdx_E10_0
;
3615 g_assert_not_reached();
3618 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3620 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3622 /* Handled by hardware accelerator. */
3623 g_assert_not_reached();
3624 #endif /* CONFIG_TCG */
3627 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3631 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3634 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3636 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3638 /* Handled by hardware accelerator. */
3639 g_assert_not_reached();
3640 #endif /* CONFIG_TCG */
3643 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3646 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3647 return CP_ACCESS_TRAP
;
3649 return CP_ACCESS_OK
;
3652 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3656 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3658 int secure
= arm_is_secure_below_el3(env
);
3660 switch (ri
->opc2
& 6) {
3663 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3664 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3665 mmu_idx
= (secure
? ARMMMUIdx_SE10_1_PAN
3666 : ARMMMUIdx_Stage1_E1_PAN
);
3668 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_Stage1_E1
;
3671 case 4: /* AT S1E2R, AT S1E2W */
3672 mmu_idx
= ARMMMUIdx_E2
;
3674 case 6: /* AT S1E3R, AT S1E3W */
3675 mmu_idx
= ARMMMUIdx_SE3
;
3678 g_assert_not_reached();
3681 case 2: /* AT S1E0R, AT S1E0W */
3682 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_Stage1_E0
;
3684 case 4: /* AT S12E1R, AT S12E1W */
3685 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3687 case 6: /* AT S12E0R, AT S12E0W */
3688 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3691 g_assert_not_reached();
3694 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3696 /* Handled by hardware accelerator. */
3697 g_assert_not_reached();
3698 #endif /* CONFIG_TCG */
3702 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3703 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3704 .access
= PL1_RW
, .resetvalue
= 0,
3705 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3706 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3707 .writefn
= par_write
},
3708 #ifndef CONFIG_USER_ONLY
3709 /* This underdecoding is safe because the reginfo is NO_RAW. */
3710 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3711 .access
= PL1_W
, .accessfn
= ats_access
,
3712 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3717 /* Return basic MPU access permission bits. */
3718 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3725 for (i
= 0; i
< 16; i
+= 2) {
3726 ret
|= (val
>> i
) & mask
;
3732 /* Pad basic MPU access permission bits to extended format. */
3733 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3740 for (i
= 0; i
< 16; i
+= 2) {
3741 ret
|= (val
& mask
) << i
;
3747 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3750 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3753 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3755 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3758 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3761 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3764 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3766 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3769 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3771 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3777 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3781 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3784 ARMCPU
*cpu
= env_archcpu(env
);
3785 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3791 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3792 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3796 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3799 ARMCPU
*cpu
= env_archcpu(env
);
3800 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3802 if (value
>= nrgs
) {
3803 qemu_log_mask(LOG_GUEST_ERROR
,
3804 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3805 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3809 raw_write(env
, ri
, value
);
3812 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3813 /* Reset for all these registers is handled in arm_cpu_reset(),
3814 * because the PMSAv7 is also used by M-profile CPUs, which do
3815 * not register cpregs but still need the state to be reset.
3817 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3818 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3819 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3820 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3821 .resetfn
= arm_cp_reset_ignore
},
3822 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3823 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3824 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3825 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3826 .resetfn
= arm_cp_reset_ignore
},
3827 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3828 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3829 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3830 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3831 .resetfn
= arm_cp_reset_ignore
},
3832 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3834 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3835 .writefn
= pmsav7_rgnr_write
,
3836 .resetfn
= arm_cp_reset_ignore
},
3840 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3841 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3842 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3843 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3844 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3845 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3846 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3847 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3848 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3849 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3851 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3853 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3855 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3857 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3859 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3860 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3862 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3863 /* Protection region base and size registers */
3864 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3865 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3866 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3867 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3868 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3869 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3870 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3871 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3872 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3873 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3874 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3875 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3876 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3877 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3878 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3879 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3880 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3881 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3882 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3883 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3884 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3885 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3886 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3887 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3891 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3894 TCR
*tcr
= raw_ptr(env
, ri
);
3895 int maskshift
= extract32(value
, 0, 3);
3897 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3898 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3899 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3900 * using Long-desciptor translation table format */
3901 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3902 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3903 /* In an implementation that includes the Security Extensions
3904 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3905 * Short-descriptor translation table format.
3907 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3913 /* Update the masks corresponding to the TCR bank being written
3914 * Note that we always calculate mask and base_mask, but
3915 * they are only used for short-descriptor tables (ie if EAE is 0);
3916 * for long-descriptor tables the TCR fields are used differently
3917 * and the mask and base_mask values are meaningless.
3919 tcr
->raw_tcr
= value
;
3920 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3921 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3924 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3927 ARMCPU
*cpu
= env_archcpu(env
);
3928 TCR
*tcr
= raw_ptr(env
, ri
);
3930 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3931 /* With LPAE the TTBCR could result in a change of ASID
3932 * via the TTBCR.A1 bit, so do a TLB flush.
3934 tlb_flush(CPU(cpu
));
3936 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3937 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3938 vmsa_ttbcr_raw_write(env
, ri
, value
);
3941 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3943 TCR
*tcr
= raw_ptr(env
, ri
);
3945 /* Reset both the TCR as well as the masks corresponding to the bank of
3946 * the TCR being reset.
3950 tcr
->base_mask
= 0xffffc000u
;
3953 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3956 ARMCPU
*cpu
= env_archcpu(env
);
3957 TCR
*tcr
= raw_ptr(env
, ri
);
3959 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3960 tlb_flush(CPU(cpu
));
3961 tcr
->raw_tcr
= value
;
3964 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3967 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3968 if (cpreg_field_is_64bit(ri
) &&
3969 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3970 ARMCPU
*cpu
= env_archcpu(env
);
3971 tlb_flush(CPU(cpu
));
3973 raw_write(env
, ri
, value
);
3976 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3980 * If we are running with E2&0 regime, then an ASID is active.
3981 * Flush if that might be changing. Note we're not checking
3982 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3983 * holds the active ASID, only checking the field that might.
3985 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3986 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3987 tlb_flush_by_mmuidx(env_cpu(env
),
3988 ARMMMUIdxBit_E20_2
|
3989 ARMMMUIdxBit_E20_2_PAN
|
3990 ARMMMUIdxBit_E20_0
);
3992 raw_write(env
, ri
, value
);
3995 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3998 ARMCPU
*cpu
= env_archcpu(env
);
3999 CPUState
*cs
= CPU(cpu
);
4002 * A change in VMID to the stage2 page table (Stage2) invalidates
4003 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
4005 if (raw_read(env
, ri
) != value
) {
4006 tlb_flush_by_mmuidx(cs
,
4007 ARMMMUIdxBit_E10_1
|
4008 ARMMMUIdxBit_E10_1_PAN
|
4009 ARMMMUIdxBit_E10_0
);
4010 raw_write(env
, ri
, value
);
4014 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4015 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4016 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4017 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4018 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4019 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4020 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4021 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4022 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4023 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4024 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4025 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4026 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4027 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4028 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4029 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4030 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4035 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4036 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4037 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4038 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4039 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4040 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4041 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4042 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4043 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4044 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4045 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4046 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4047 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4048 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4049 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4050 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4051 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4052 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4053 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4054 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4055 .writefn
= vmsa_tcr_el12_write
,
4056 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
4057 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4058 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4059 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4060 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4061 .raw_writefn
= vmsa_ttbcr_raw_write
,
4062 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4063 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4067 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4068 * qemu tlbs nor adjusting cached masks.
4070 static const ARMCPRegInfo ttbcr2_reginfo
= {
4071 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4072 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4073 .type
= ARM_CP_ALIAS
,
4074 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4075 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
4078 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4081 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4082 /* The OS_TYPE bit in this register changes the reported CPUID! */
4083 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4084 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4087 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4090 env
->cp15
.c15_threadid
= value
& 0xffff;
4093 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4096 /* Wait-for-interrupt (deprecated) */
4097 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4100 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4103 /* On OMAP there are registers indicating the max/min index of dcache lines
4104 * containing a dirty line; cache flush operations have to reset these.
4106 env
->cp15
.c15_i_max
= 0x000;
4107 env
->cp15
.c15_i_min
= 0xff0;
4110 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4111 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4112 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4113 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4115 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4116 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4117 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4119 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4120 .writefn
= omap_ticonfig_write
},
4121 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4123 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4124 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4125 .access
= PL1_RW
, .resetvalue
= 0xff0,
4126 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4127 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4129 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4130 .writefn
= omap_threadid_write
},
4131 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4132 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4133 .type
= ARM_CP_NO_RAW
,
4134 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4135 /* TODO: Peripheral port remap register:
4136 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4137 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4140 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4141 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4142 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4143 .writefn
= omap_cachemaint_write
},
4144 { .name
= "C9", .cp
= 15, .crn
= 9,
4145 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4146 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4150 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4153 env
->cp15
.c15_cpar
= value
& 0x3fff;
4156 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4157 { .name
= "XSCALE_CPAR",
4158 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4159 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4160 .writefn
= xscale_cpar_write
, },
4161 { .name
= "XSCALE_AUXCR",
4162 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4163 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4165 /* XScale specific cache-lockdown: since we have no cache we NOP these
4166 * and hope the guest does not really rely on cache behaviour.
4168 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4169 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4170 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4171 { .name
= "XSCALE_UNLOCK_ICACHE",
4172 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4173 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4174 { .name
= "XSCALE_DCACHE_LOCK",
4175 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4176 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4177 { .name
= "XSCALE_UNLOCK_DCACHE",
4178 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4179 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4183 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4184 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4185 * implementation of this implementation-defined space.
4186 * Ideally this should eventually disappear in favour of actually
4187 * implementing the correct behaviour for all cores.
4189 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4190 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4192 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4197 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4198 /* Cache status: RAZ because we have no cache so it's always clean */
4199 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4200 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4205 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4206 /* We never have a a block transfer operation in progress */
4207 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4208 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4210 /* The cache ops themselves: these all NOP for QEMU */
4211 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4212 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4213 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4214 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4215 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4216 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4217 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4218 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4219 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4220 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4221 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4222 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4226 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4227 /* The cache test-and-clean instructions always return (1 << 30)
4228 * to indicate that there are no dirty cache lines.
4230 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4231 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4232 .resetvalue
= (1 << 30) },
4233 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4234 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4235 .resetvalue
= (1 << 30) },
4239 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4240 /* Ignore ReadBuffer accesses */
4241 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4242 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4243 .access
= PL1_RW
, .resetvalue
= 0,
4244 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4248 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4250 ARMCPU
*cpu
= env_archcpu(env
);
4251 unsigned int cur_el
= arm_current_el(env
);
4252 bool secure
= arm_is_secure(env
);
4254 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
4255 return env
->cp15
.vpidr_el2
;
4257 return raw_read(env
, ri
);
4260 static uint64_t mpidr_read_val(CPUARMState
*env
)
4262 ARMCPU
*cpu
= env_archcpu(env
);
4263 uint64_t mpidr
= cpu
->mp_affinity
;
4265 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4266 mpidr
|= (1U << 31);
4267 /* Cores which are uniprocessor (non-coherent)
4268 * but still implement the MP extensions set
4269 * bit 30. (For instance, Cortex-R5).
4271 if (cpu
->mp_is_up
) {
4272 mpidr
|= (1u << 30);
4278 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4280 unsigned int cur_el
= arm_current_el(env
);
4281 bool secure
= arm_is_secure(env
);
4283 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
4284 return env
->cp15
.vmpidr_el2
;
4286 return mpidr_read_val(env
);
4289 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4291 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4292 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4293 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4294 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4295 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4296 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4297 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4298 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4299 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4300 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4301 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4302 offsetof(CPUARMState
, cp15
.par_ns
)} },
4303 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4304 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4305 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4306 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4307 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4308 .writefn
= vmsa_ttbr_write
, },
4309 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4310 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4311 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4312 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4313 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4314 .writefn
= vmsa_ttbr_write
, },
4318 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4320 return vfp_get_fpcr(env
);
4323 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4326 vfp_set_fpcr(env
, value
);
4329 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4331 return vfp_get_fpsr(env
);
4334 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4337 vfp_set_fpsr(env
, value
);
4340 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4343 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4344 return CP_ACCESS_TRAP
;
4346 return CP_ACCESS_OK
;
4349 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4352 env
->daif
= value
& PSTATE_DAIF
;
4355 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4357 return env
->pstate
& PSTATE_PAN
;
4360 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4363 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4366 static const ARMCPRegInfo pan_reginfo
= {
4367 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4368 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4369 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4370 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4373 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4375 return env
->pstate
& PSTATE_UAO
;
4378 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4381 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4384 static const ARMCPRegInfo uao_reginfo
= {
4385 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4386 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4387 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4388 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4391 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4392 const ARMCPRegInfo
*ri
,
4395 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4396 switch (arm_current_el(env
)) {
4398 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4399 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4400 return CP_ACCESS_TRAP
;
4404 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4405 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4406 return CP_ACCESS_TRAP_EL2
;
4410 return CP_ACCESS_OK
;
4413 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4414 const ARMCPRegInfo
*ri
,
4417 /* Cache invalidate/clean to Point of Unification... */
4418 switch (arm_current_el(env
)) {
4420 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4421 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4422 return CP_ACCESS_TRAP
;
4426 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4427 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4428 return CP_ACCESS_TRAP_EL2
;
4432 return CP_ACCESS_OK
;
4435 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4436 * Page D4-1736 (DDI0487A.b)
4439 static int vae1_tlbmask(CPUARMState
*env
)
4441 /* Since we exclude secure first, we may read HCR_EL2 directly. */
4442 if (arm_is_secure_below_el3(env
)) {
4443 return ARMMMUIdxBit_SE10_1
|
4444 ARMMMUIdxBit_SE10_1_PAN
|
4445 ARMMMUIdxBit_SE10_0
;
4446 } else if ((env
->cp15
.hcr_el2
& (HCR_E2H
| HCR_TGE
))
4447 == (HCR_E2H
| HCR_TGE
)) {
4448 return ARMMMUIdxBit_E20_2
|
4449 ARMMMUIdxBit_E20_2_PAN
|
4452 return ARMMMUIdxBit_E10_1
|
4453 ARMMMUIdxBit_E10_1_PAN
|
4458 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4461 CPUState
*cs
= env_cpu(env
);
4462 int mask
= vae1_tlbmask(env
);
4464 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4467 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4470 CPUState
*cs
= env_cpu(env
);
4471 int mask
= vae1_tlbmask(env
);
4473 if (tlb_force_broadcast(env
)) {
4474 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4476 tlb_flush_by_mmuidx(cs
, mask
);
4480 static int alle1_tlbmask(CPUARMState
*env
)
4483 * Note that the 'ALL' scope must invalidate both stage 1 and
4484 * stage 2 translations, whereas most other scopes only invalidate
4485 * stage 1 translations.
4487 if (arm_is_secure_below_el3(env
)) {
4488 return ARMMMUIdxBit_SE10_1
|
4489 ARMMMUIdxBit_SE10_1_PAN
|
4490 ARMMMUIdxBit_SE10_0
;
4492 return ARMMMUIdxBit_E10_1
|
4493 ARMMMUIdxBit_E10_1_PAN
|
4498 static int e2_tlbmask(CPUARMState
*env
)
4500 /* TODO: ARMv8.4-SecEL2 */
4501 return ARMMMUIdxBit_E20_0
|
4502 ARMMMUIdxBit_E20_2
|
4503 ARMMMUIdxBit_E20_2_PAN
|
4507 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4510 CPUState
*cs
= env_cpu(env
);
4511 int mask
= alle1_tlbmask(env
);
4513 tlb_flush_by_mmuidx(cs
, mask
);
4516 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4519 CPUState
*cs
= env_cpu(env
);
4520 int mask
= e2_tlbmask(env
);
4522 tlb_flush_by_mmuidx(cs
, mask
);
4525 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4528 ARMCPU
*cpu
= env_archcpu(env
);
4529 CPUState
*cs
= CPU(cpu
);
4531 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4534 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4537 CPUState
*cs
= env_cpu(env
);
4538 int mask
= alle1_tlbmask(env
);
4540 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4543 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4546 CPUState
*cs
= env_cpu(env
);
4547 int mask
= e2_tlbmask(env
);
4549 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4552 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4555 CPUState
*cs
= env_cpu(env
);
4557 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4560 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4563 /* Invalidate by VA, EL2
4564 * Currently handles both VAE2 and VALE2, since we don't support
4565 * flush-last-level-only.
4567 CPUState
*cs
= env_cpu(env
);
4568 int mask
= e2_tlbmask(env
);
4569 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4571 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4574 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4577 /* Invalidate by VA, EL3
4578 * Currently handles both VAE3 and VALE3, since we don't support
4579 * flush-last-level-only.
4581 ARMCPU
*cpu
= env_archcpu(env
);
4582 CPUState
*cs
= CPU(cpu
);
4583 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4585 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4588 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4591 CPUState
*cs
= env_cpu(env
);
4592 int mask
= vae1_tlbmask(env
);
4593 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4595 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4598 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4601 /* Invalidate by VA, EL1&0 (AArch64 version).
4602 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4603 * since we don't support flush-for-specific-ASID-only or
4604 * flush-last-level-only.
4606 CPUState
*cs
= env_cpu(env
);
4607 int mask
= vae1_tlbmask(env
);
4608 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4610 if (tlb_force_broadcast(env
)) {
4611 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4613 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4617 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4620 CPUState
*cs
= env_cpu(env
);
4621 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4623 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4627 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4630 CPUState
*cs
= env_cpu(env
);
4631 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4633 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4637 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4640 int cur_el
= arm_current_el(env
);
4643 uint64_t hcr
= arm_hcr_el2_eff(env
);
4646 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4647 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4648 return CP_ACCESS_TRAP_EL2
;
4651 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4652 return CP_ACCESS_TRAP
;
4654 if (hcr
& HCR_TDZ
) {
4655 return CP_ACCESS_TRAP_EL2
;
4658 } else if (hcr
& HCR_TDZ
) {
4659 return CP_ACCESS_TRAP_EL2
;
4662 return CP_ACCESS_OK
;
4665 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4667 ARMCPU
*cpu
= env_archcpu(env
);
4668 int dzp_bit
= 1 << 4;
4670 /* DZP indicates whether DC ZVA access is allowed */
4671 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4674 return cpu
->dcz_blocksize
| dzp_bit
;
4677 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4680 if (!(env
->pstate
& PSTATE_SP
)) {
4681 /* Access to SP_EL0 is undefined if it's being used as
4682 * the stack pointer.
4684 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4686 return CP_ACCESS_OK
;
4689 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4691 return env
->pstate
& PSTATE_SP
;
4694 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4696 update_spsel(env
, val
);
4699 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4702 ARMCPU
*cpu
= env_archcpu(env
);
4704 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4705 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4709 /* ??? Lots of these bits are not implemented. */
4711 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4712 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4713 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4715 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4716 SCTLR_ATA0
| SCTLR_ATA
);
4720 if (raw_read(env
, ri
) == value
) {
4721 /* Skip the TLB flush if nothing actually changed; Linux likes
4722 * to do a lot of pointless SCTLR writes.
4727 raw_write(env
, ri
, value
);
4729 /* This may enable/disable the MMU, so do a TLB flush. */
4730 tlb_flush(CPU(cpu
));
4732 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4734 * Normally we would always end the TB on an SCTLR write; see the
4735 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4736 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4737 * of hflags from the translator, so do it here.
4739 arm_rebuild_hflags(env
);
4743 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4746 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4747 return CP_ACCESS_TRAP_FP_EL2
;
4749 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4750 return CP_ACCESS_TRAP_FP_EL3
;
4752 return CP_ACCESS_OK
;
4755 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4758 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4761 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4762 /* Minimal set of EL0-visible registers. This will need to be expanded
4763 * significantly for system emulation of AArch64 CPUs.
4765 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4766 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4767 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4768 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4769 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4770 .type
= ARM_CP_NO_RAW
,
4771 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4772 .fieldoffset
= offsetof(CPUARMState
, daif
),
4773 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4774 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4775 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4776 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4777 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4778 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4779 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4780 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4781 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4782 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4783 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4784 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4785 .readfn
= aa64_dczid_read
},
4786 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4787 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4788 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4789 #ifndef CONFIG_USER_ONLY
4790 /* Avoid overhead of an access check that always passes in user-mode */
4791 .accessfn
= aa64_zva_access
,
4794 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4795 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4796 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4797 /* Cache ops: all NOPs since we don't emulate caches */
4798 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4799 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4800 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4801 .accessfn
= aa64_cacheop_pou_access
},
4802 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4803 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4804 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4805 .accessfn
= aa64_cacheop_pou_access
},
4806 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4807 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4808 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4809 .accessfn
= aa64_cacheop_pou_access
},
4810 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4811 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4812 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4813 .type
= ARM_CP_NOP
},
4814 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4815 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4816 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4817 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4818 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4819 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4820 .accessfn
= aa64_cacheop_poc_access
},
4821 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4822 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4823 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4824 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4825 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4826 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4827 .accessfn
= aa64_cacheop_pou_access
},
4828 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4829 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4830 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4831 .accessfn
= aa64_cacheop_poc_access
},
4832 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4833 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4834 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4835 /* TLBI operations */
4836 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4837 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4838 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4839 .writefn
= tlbi_aa64_vmalle1is_write
},
4840 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4841 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4842 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4843 .writefn
= tlbi_aa64_vae1is_write
},
4844 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4845 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4846 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4847 .writefn
= tlbi_aa64_vmalle1is_write
},
4848 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4849 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4850 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4851 .writefn
= tlbi_aa64_vae1is_write
},
4852 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4853 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4854 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4855 .writefn
= tlbi_aa64_vae1is_write
},
4856 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4857 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4858 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4859 .writefn
= tlbi_aa64_vae1is_write
},
4860 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4861 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4862 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4863 .writefn
= tlbi_aa64_vmalle1_write
},
4864 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4865 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4866 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4867 .writefn
= tlbi_aa64_vae1_write
},
4868 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4869 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4870 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4871 .writefn
= tlbi_aa64_vmalle1_write
},
4872 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4873 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4874 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4875 .writefn
= tlbi_aa64_vae1_write
},
4876 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4877 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4878 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4879 .writefn
= tlbi_aa64_vae1_write
},
4880 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4881 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4882 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4883 .writefn
= tlbi_aa64_vae1_write
},
4884 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4885 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4886 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4887 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4888 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4889 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4890 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4891 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4892 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4893 .writefn
= tlbi_aa64_alle1is_write
},
4894 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4895 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4896 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4897 .writefn
= tlbi_aa64_alle1is_write
},
4898 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4899 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4900 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4901 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4902 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4903 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4904 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4905 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4906 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4907 .writefn
= tlbi_aa64_alle1_write
},
4908 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4909 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4910 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4911 .writefn
= tlbi_aa64_alle1is_write
},
4912 #ifndef CONFIG_USER_ONLY
4913 /* 64 bit address translation operations */
4914 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4915 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4916 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4917 .writefn
= ats_write64
},
4918 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4919 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4920 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4921 .writefn
= ats_write64
},
4922 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4923 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4924 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4925 .writefn
= ats_write64
},
4926 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4927 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4928 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4929 .writefn
= ats_write64
},
4930 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4931 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4932 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4933 .writefn
= ats_write64
},
4934 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4935 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4936 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4937 .writefn
= ats_write64
},
4938 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4939 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4940 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4941 .writefn
= ats_write64
},
4942 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4943 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4944 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4945 .writefn
= ats_write64
},
4946 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4947 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4948 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4949 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4950 .writefn
= ats_write64
},
4951 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4952 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4953 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4954 .writefn
= ats_write64
},
4955 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4956 .type
= ARM_CP_ALIAS
,
4957 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4958 .access
= PL1_RW
, .resetvalue
= 0,
4959 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4960 .writefn
= par_write
},
4962 /* TLB invalidate last level of translation table walk */
4963 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4964 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4965 .writefn
= tlbimva_is_write
},
4966 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4967 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4968 .writefn
= tlbimvaa_is_write
},
4969 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4970 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4971 .writefn
= tlbimva_write
},
4972 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4973 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4974 .writefn
= tlbimvaa_write
},
4975 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4976 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4977 .writefn
= tlbimva_hyp_write
},
4978 { .name
= "TLBIMVALHIS",
4979 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4980 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4981 .writefn
= tlbimva_hyp_is_write
},
4982 { .name
= "TLBIIPAS2",
4983 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4984 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4985 { .name
= "TLBIIPAS2IS",
4986 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4987 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4988 { .name
= "TLBIIPAS2L",
4989 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4990 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4991 { .name
= "TLBIIPAS2LIS",
4992 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4993 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4994 /* 32 bit cache operations */
4995 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4996 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
4997 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4998 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4999 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5000 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5001 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5002 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5003 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5004 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5005 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5006 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5007 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5008 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5009 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5010 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5011 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5012 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5013 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5014 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5015 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5016 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5017 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5018 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5019 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5020 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5021 /* MMU Domain access control / MPU write buffer control */
5022 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5023 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5024 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5025 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5026 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5027 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5028 .type
= ARM_CP_ALIAS
,
5029 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5031 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5032 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5033 .type
= ARM_CP_ALIAS
,
5034 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5036 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5037 /* We rely on the access checks not allowing the guest to write to the
5038 * state field when SPSel indicates that it's being used as the stack
5041 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5042 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5043 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5044 .type
= ARM_CP_ALIAS
,
5045 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5046 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5047 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5048 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5049 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5050 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5051 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5052 .type
= ARM_CP_NO_RAW
,
5053 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5054 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5055 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5056 .type
= ARM_CP_ALIAS
,
5057 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
5058 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
5059 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5060 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5061 .access
= PL2_RW
, .resetvalue
= 0,
5062 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5063 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5064 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5065 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5066 .access
= PL2_RW
, .resetvalue
= 0,
5067 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5068 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5069 .type
= ARM_CP_ALIAS
,
5070 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5072 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5073 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5074 .type
= ARM_CP_ALIAS
,
5075 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5077 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5078 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5079 .type
= ARM_CP_ALIAS
,
5080 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5082 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5083 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5084 .type
= ARM_CP_ALIAS
,
5085 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5087 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5088 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5089 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5091 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5092 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5093 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5094 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5095 .writefn
= sdcr_write
,
5096 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5100 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
5101 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
5102 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5103 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5105 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
5106 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5107 .type
= ARM_CP_NO_RAW
,
5108 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5110 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5111 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5112 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5113 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5114 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5115 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5117 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5118 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5119 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5120 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5121 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5122 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5123 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5125 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5126 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5127 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5128 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5129 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5130 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5132 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5133 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5134 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5136 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5137 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5138 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5140 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5141 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5142 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5144 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5145 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5146 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5147 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5148 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5149 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5150 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5151 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5152 .cp
= 15, .opc1
= 6, .crm
= 2,
5153 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5154 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
5155 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5156 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5157 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5158 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5159 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5160 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5161 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5162 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5163 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5164 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5165 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5166 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5167 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5168 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5170 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5171 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5172 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5173 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5174 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5175 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5176 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5177 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5179 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5180 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5181 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5182 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5183 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5185 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5186 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5187 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5188 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5189 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5190 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5191 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5192 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5193 .access
= PL2_RW
, .accessfn
= access_tda
,
5194 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5195 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5196 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5197 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5198 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5199 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5200 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5201 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5202 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5203 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5204 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5205 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5206 .type
= ARM_CP_CONST
,
5207 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5208 .access
= PL2_RW
, .resetvalue
= 0 },
5212 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5213 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
5214 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5215 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5217 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5221 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5223 ARMCPU
*cpu
= env_archcpu(env
);
5225 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5226 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5228 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5231 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5232 valid_mask
&= ~HCR_HCD
;
5233 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5234 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5235 * However, if we're using the SMC PSCI conduit then QEMU is
5236 * effectively acting like EL3 firmware and so the guest at
5237 * EL2 should retain the ability to prevent EL1 from being
5238 * able to make SMC calls into the ersatz firmware, so in
5239 * that case HCR.TSC should be read/write.
5241 valid_mask
&= ~HCR_TSC
;
5244 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5245 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5246 valid_mask
|= HCR_E2H
;
5248 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5249 valid_mask
|= HCR_TLOR
;
5251 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5252 valid_mask
|= HCR_API
| HCR_APK
;
5254 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5255 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5259 /* Clear RES0 bits. */
5260 value
&= valid_mask
;
5263 * These bits change the MMU setup:
5264 * HCR_VM enables stage 2 translation
5265 * HCR_PTW forbids certain page-table setups
5266 * HCR_DC disables stage1 and enables stage2 translation
5267 * HCR_DCT enables tagging on (disabled) stage1 translation
5269 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
)) {
5270 tlb_flush(CPU(cpu
));
5272 env
->cp15
.hcr_el2
= value
;
5275 * Updates to VI and VF require us to update the status of
5276 * virtual interrupts, which are the logical OR of these bits
5277 * and the state of the input lines from the GIC. (This requires
5278 * that we have the iothread lock, which is done by marking the
5279 * reginfo structs as ARM_CP_IO.)
5280 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5281 * possible for it to be taken immediately, because VIRQ and
5282 * VFIQ are masked unless running at EL0 or EL1, and HCR
5283 * can only be written at EL2.
5285 g_assert(qemu_mutex_iothread_locked());
5286 arm_cpu_update_virq(cpu
);
5287 arm_cpu_update_vfiq(cpu
);
5290 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5292 do_hcr_write(env
, value
, 0);
5295 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5298 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5299 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5300 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5303 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5306 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5307 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5308 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5312 * Return the effective value of HCR_EL2.
5313 * Bits that are not included here:
5314 * RW (read from SCR_EL3.RW as needed)
5316 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5318 uint64_t ret
= env
->cp15
.hcr_el2
;
5320 if (arm_is_secure_below_el3(env
)) {
5322 * "This register has no effect if EL2 is not enabled in the
5323 * current Security state". This is ARMv8.4-SecEL2 speak for
5324 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5326 * Prior to that, the language was "In an implementation that
5327 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5328 * as if this field is 0 for all purposes other than a direct
5329 * read or write access of HCR_EL2". With lots of enumeration
5330 * on a per-field basis. In current QEMU, this is condition
5331 * is arm_is_secure_below_el3.
5333 * Since the v8.4 language applies to the entire register, and
5334 * appears to be backward compatible, use that.
5340 * For a cpu that supports both aarch64 and aarch32, we can set bits
5341 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5342 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5344 if (!arm_el_is_aa64(env
, 2)) {
5345 uint64_t aa32_valid
;
5348 * These bits are up-to-date as of ARMv8.6.
5349 * For HCR, it's easiest to list just the 2 bits that are invalid.
5350 * For HCR2, list those that are valid.
5352 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5353 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5354 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5358 if (ret
& HCR_TGE
) {
5359 /* These bits are up-to-date as of ARMv8.6. */
5360 if (ret
& HCR_E2H
) {
5361 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5362 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5363 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5364 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5365 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5366 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5368 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5370 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5371 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5372 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5379 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5383 * For A-profile AArch32 EL3, if NSACR.CP10
5384 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5386 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5387 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5388 value
&= ~(0x3 << 10);
5389 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
5391 env
->cp15
.cptr_el
[2] = value
;
5394 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5397 * For A-profile AArch32 EL3, if NSACR.CP10
5398 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5400 uint64_t value
= env
->cp15
.cptr_el
[2];
5402 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5403 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5409 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5410 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5412 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5413 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5414 .writefn
= hcr_write
},
5415 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5416 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5417 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5418 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5419 .writefn
= hcr_writelow
},
5420 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5421 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5422 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5423 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5424 .type
= ARM_CP_ALIAS
,
5425 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5427 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5428 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5429 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5430 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5431 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5432 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5433 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5434 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5435 .type
= ARM_CP_ALIAS
,
5436 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5438 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5439 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5440 .type
= ARM_CP_ALIAS
,
5441 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5443 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5444 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5445 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5446 .access
= PL2_RW
, .writefn
= vbar_write
,
5447 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5449 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5450 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5451 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5452 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5453 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5454 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5455 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5456 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5457 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5458 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5459 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5460 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5462 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5463 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5464 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5465 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5466 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5467 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5468 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5470 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5471 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5472 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5473 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5475 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5476 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5477 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5479 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5480 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5481 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5483 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5484 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5485 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5486 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5487 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5488 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5489 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5490 .type
= ARM_CP_ALIAS
,
5491 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5492 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5493 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5494 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5496 /* no .writefn needed as this can't cause an ASID change;
5497 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5499 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5500 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5501 .cp
= 15, .opc1
= 6, .crm
= 2,
5502 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5503 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5504 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5505 .writefn
= vttbr_write
},
5506 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5507 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5508 .access
= PL2_RW
, .writefn
= vttbr_write
,
5509 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5510 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5511 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5512 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5513 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5514 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5515 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5516 .access
= PL2_RW
, .resetvalue
= 0,
5517 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5518 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5519 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5520 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5521 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5522 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5523 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5524 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5525 { .name
= "TLBIALLNSNH",
5526 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5527 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5528 .writefn
= tlbiall_nsnh_write
},
5529 { .name
= "TLBIALLNSNHIS",
5530 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5531 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5532 .writefn
= tlbiall_nsnh_is_write
},
5533 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5534 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5535 .writefn
= tlbiall_hyp_write
},
5536 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5537 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5538 .writefn
= tlbiall_hyp_is_write
},
5539 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5540 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5541 .writefn
= tlbimva_hyp_write
},
5542 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5543 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5544 .writefn
= tlbimva_hyp_is_write
},
5545 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5546 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5547 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5548 .writefn
= tlbi_aa64_alle2_write
},
5549 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5550 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5551 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5552 .writefn
= tlbi_aa64_vae2_write
},
5553 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5554 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5555 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5556 .writefn
= tlbi_aa64_vae2_write
},
5557 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5558 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5559 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5560 .writefn
= tlbi_aa64_alle2is_write
},
5561 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5562 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5563 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5564 .writefn
= tlbi_aa64_vae2is_write
},
5565 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5566 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5567 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5568 .writefn
= tlbi_aa64_vae2is_write
},
5569 #ifndef CONFIG_USER_ONLY
5570 /* Unlike the other EL2-related AT operations, these must
5571 * UNDEF from EL3 if EL2 is not implemented, which is why we
5572 * define them here rather than with the rest of the AT ops.
5574 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5575 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5576 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5577 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5578 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5579 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5580 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5581 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5582 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5583 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5584 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5585 * to behave as if SCR.NS was 1.
5587 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5589 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5590 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5592 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5593 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5594 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5595 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5596 * reset values as IMPDEF. We choose to reset to 3 to comply with
5597 * both ARMv7 and ARMv8.
5599 .access
= PL2_RW
, .resetvalue
= 3,
5600 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5601 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5602 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5603 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5604 .writefn
= gt_cntvoff_write
,
5605 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5606 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5607 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5608 .writefn
= gt_cntvoff_write
,
5609 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5610 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5611 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5612 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5613 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5614 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5615 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5616 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5617 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5618 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5619 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5620 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5621 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5622 .resetfn
= gt_hyp_timer_reset
,
5623 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5624 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5626 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5628 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5630 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5632 /* The only field of MDCR_EL2 that has a defined architectural reset value
5633 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5634 * don't implement any PMU event counters, so using zero as a reset
5635 * value for MDCR_EL2 is okay
5637 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5638 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5639 .access
= PL2_RW
, .resetvalue
= 0,
5640 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5641 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5642 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5643 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5644 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5645 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5646 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5648 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5649 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5650 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5652 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5656 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5657 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5658 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5659 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5661 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5662 .writefn
= hcr_writehigh
},
5666 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5669 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5670 * At Secure EL1 it traps to EL3.
5672 if (arm_current_el(env
) == 3) {
5673 return CP_ACCESS_OK
;
5675 if (arm_is_secure_below_el3(env
)) {
5676 return CP_ACCESS_TRAP_EL3
;
5678 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5680 return CP_ACCESS_OK
;
5682 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5685 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5686 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5687 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5688 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5689 .resetvalue
= 0, .writefn
= scr_write
},
5690 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5691 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5692 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5693 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5694 .writefn
= scr_write
},
5695 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5696 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5697 .access
= PL3_RW
, .resetvalue
= 0,
5698 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5700 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5701 .access
= PL3_RW
, .resetvalue
= 0,
5702 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5703 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5704 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5705 .writefn
= vbar_write
, .resetvalue
= 0,
5706 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5707 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5708 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5709 .access
= PL3_RW
, .resetvalue
= 0,
5710 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5711 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5712 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5714 /* no .writefn needed as this can't cause an ASID change;
5715 * we must provide a .raw_writefn and .resetfn because we handle
5716 * reset and migration for the AArch32 TTBCR(S), which might be
5717 * using mask and base_mask.
5719 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5720 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5721 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5722 .type
= ARM_CP_ALIAS
,
5723 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5725 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5726 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5727 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5728 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5729 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5730 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5731 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5732 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5733 .type
= ARM_CP_ALIAS
,
5734 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5736 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5737 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5738 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5739 .access
= PL3_RW
, .writefn
= vbar_write
,
5740 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5742 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5743 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5744 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5745 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5746 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5747 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5748 .access
= PL3_RW
, .resetvalue
= 0,
5749 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5750 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5751 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5752 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5754 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5755 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5756 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5758 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5759 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5760 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5762 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5763 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5764 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5765 .writefn
= tlbi_aa64_alle3is_write
},
5766 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5767 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5768 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5769 .writefn
= tlbi_aa64_vae3is_write
},
5770 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5771 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5772 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5773 .writefn
= tlbi_aa64_vae3is_write
},
5774 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5775 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5776 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5777 .writefn
= tlbi_aa64_alle3_write
},
5778 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5779 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5780 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5781 .writefn
= tlbi_aa64_vae3_write
},
5782 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5783 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5784 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5785 .writefn
= tlbi_aa64_vae3_write
},
5789 #ifndef CONFIG_USER_ONLY
5790 /* Test if system register redirection is to occur in the current state. */
5791 static bool redirect_for_e2h(CPUARMState
*env
)
5793 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5796 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5800 if (redirect_for_e2h(env
)) {
5801 /* Switch to the saved EL2 version of the register. */
5803 readfn
= ri
->readfn
;
5805 readfn
= ri
->orig_readfn
;
5807 if (readfn
== NULL
) {
5810 return readfn(env
, ri
);
5813 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5818 if (redirect_for_e2h(env
)) {
5819 /* Switch to the saved EL2 version of the register. */
5821 writefn
= ri
->writefn
;
5823 writefn
= ri
->orig_writefn
;
5825 if (writefn
== NULL
) {
5826 writefn
= raw_write
;
5828 writefn(env
, ri
, value
);
5831 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5834 uint32_t src_key
, dst_key
, new_key
;
5835 const char *src_name
, *dst_name
, *new_name
;
5836 bool (*feature
)(const ARMISARegisters
*id
);
5839 #define K(op0, op1, crn, crm, op2) \
5840 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5842 static const struct E2HAlias aliases
[] = {
5843 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5844 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5845 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5846 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5847 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5848 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5849 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5850 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5851 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5852 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5853 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5854 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5855 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5856 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5857 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5858 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5859 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5860 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5861 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5862 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5863 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5864 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5865 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5866 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5867 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5868 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5869 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5870 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5871 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5872 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5873 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5874 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5877 * Note that redirection of ZCR is mentioned in the description
5878 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5879 * not in the summary table.
5881 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5882 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5884 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5885 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5887 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5888 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5894 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5895 const struct E2HAlias
*a
= &aliases
[i
];
5896 ARMCPRegInfo
*src_reg
, *dst_reg
;
5898 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5902 src_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->src_key
);
5903 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->dst_key
);
5904 g_assert(src_reg
!= NULL
);
5905 g_assert(dst_reg
!= NULL
);
5907 /* Cross-compare names to detect typos in the keys. */
5908 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5909 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5911 /* None of the core system registers use opaque; we will. */
5912 g_assert(src_reg
->opaque
== NULL
);
5914 /* Create alias before redirection so we dup the right data. */
5916 ARMCPRegInfo
*new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5917 uint32_t *new_key
= g_memdup(&a
->new_key
, sizeof(uint32_t));
5920 new_reg
->name
= a
->new_name
;
5921 new_reg
->type
|= ARM_CP_ALIAS
;
5922 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5923 new_reg
->access
&= PL2_RW
| PL3_RW
;
5925 ok
= g_hash_table_insert(cpu
->cp_regs
, new_key
, new_reg
);
5929 src_reg
->opaque
= dst_reg
;
5930 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5931 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5932 if (!src_reg
->raw_readfn
) {
5933 src_reg
->raw_readfn
= raw_read
;
5935 if (!src_reg
->raw_writefn
) {
5936 src_reg
->raw_writefn
= raw_write
;
5938 src_reg
->readfn
= el2_e2h_read
;
5939 src_reg
->writefn
= el2_e2h_write
;
5944 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5947 int cur_el
= arm_current_el(env
);
5950 uint64_t hcr
= arm_hcr_el2_eff(env
);
5953 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5954 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5955 return CP_ACCESS_TRAP_EL2
;
5958 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5959 return CP_ACCESS_TRAP
;
5961 if (hcr
& HCR_TID2
) {
5962 return CP_ACCESS_TRAP_EL2
;
5965 } else if (hcr
& HCR_TID2
) {
5966 return CP_ACCESS_TRAP_EL2
;
5970 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5971 return CP_ACCESS_TRAP_EL2
;
5974 return CP_ACCESS_OK
;
5977 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5980 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5981 * read via a bit in OSLSR_EL1.
5985 if (ri
->state
== ARM_CP_STATE_AA32
) {
5986 oslock
= (value
== 0xC5ACCE55);
5991 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5994 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5995 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5996 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5997 * unlike DBGDRAR it is never accessible from EL0.
5998 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6001 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
6002 .access
= PL0_R
, .accessfn
= access_tdra
,
6003 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6004 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
6005 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6006 .access
= PL1_R
, .accessfn
= access_tdra
,
6007 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6008 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
6009 .access
= PL0_R
, .accessfn
= access_tdra
,
6010 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6011 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6012 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
6013 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6014 .access
= PL1_RW
, .accessfn
= access_tda
,
6015 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
6017 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
6018 * We don't implement the configurable EL0 access.
6020 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
6021 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6022 .type
= ARM_CP_ALIAS
,
6023 .access
= PL1_R
, .accessfn
= access_tda
,
6024 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
6025 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
6026 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
6027 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6028 .accessfn
= access_tdosa
,
6029 .writefn
= oslar_write
},
6030 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
6031 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
6032 .access
= PL1_R
, .resetvalue
= 10,
6033 .accessfn
= access_tdosa
,
6034 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
6035 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6036 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6037 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
6038 .access
= PL1_RW
, .accessfn
= access_tdosa
,
6039 .type
= ARM_CP_NOP
},
6040 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6041 * implement vector catch debug events yet.
6044 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6045 .access
= PL1_RW
, .accessfn
= access_tda
,
6046 .type
= ARM_CP_NOP
},
6047 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6048 * to save and restore a 32-bit guest's DBGVCR)
6050 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
6051 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
6052 .access
= PL2_RW
, .accessfn
= access_tda
,
6053 .type
= ARM_CP_NOP
},
6054 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6055 * Channel but Linux may try to access this register. The 32-bit
6056 * alias is DBGDCCINT.
6058 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
6059 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6060 .access
= PL1_RW
, .accessfn
= access_tda
,
6061 .type
= ARM_CP_NOP
},
6065 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
6066 /* 64 bit access versions of the (dummy) debug registers */
6067 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
6068 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6069 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
6070 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6074 /* Return the exception level to which exceptions should be taken
6075 * via SVEAccessTrap. If an exception should be routed through
6076 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6077 * take care of raising that exception.
6078 * C.f. the ARM pseudocode function CheckSVEEnabled.
6080 int sve_exception_el(CPUARMState
*env
, int el
)
6082 #ifndef CONFIG_USER_ONLY
6083 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
6085 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6086 bool disabled
= false;
6088 /* The CPACR.ZEN controls traps to EL1:
6089 * 0, 2 : trap EL0 and EL1 accesses
6090 * 1 : trap only EL0 accesses
6091 * 3 : trap no accesses
6093 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
6095 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
6100 return hcr_el2
& HCR_TGE
? 2 : 1;
6103 /* Check CPACR.FPEN. */
6104 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
6106 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
6114 /* CPTR_EL2. Since TZ and TFP are positive,
6115 * they will be zero when EL2 is not present.
6117 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
6118 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
6121 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
6126 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6127 if (arm_feature(env
, ARM_FEATURE_EL3
)
6128 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
6135 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
6139 end_len
= start_len
&= 0xf;
6140 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
6141 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
6142 assert(end_len
< start_len
);
6148 * Given that SVE is enabled, return the vector length for EL.
6150 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
6152 ARMCPU
*cpu
= env_archcpu(env
);
6153 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
6156 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
6158 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6159 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
6161 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6162 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
6165 return sve_zcr_get_valid_len(cpu
, zcr_len
);
6168 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6171 int cur_el
= arm_current_el(env
);
6172 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
6175 /* Bits other than [3:0] are RAZ/WI. */
6176 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6177 raw_write(env
, ri
, value
& 0xf);
6180 * Because we arrived here, we know both FP and SVE are enabled;
6181 * otherwise we would have trapped access to the ZCR_ELn register.
6183 new_len
= sve_zcr_len_for_el(env
, cur_el
);
6184 if (new_len
< old_len
) {
6185 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6189 static const ARMCPRegInfo zcr_el1_reginfo
= {
6190 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6191 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6192 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6193 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6194 .writefn
= zcr_write
, .raw_writefn
= raw_write
6197 static const ARMCPRegInfo zcr_el2_reginfo
= {
6198 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6199 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6200 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6201 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6202 .writefn
= zcr_write
, .raw_writefn
= raw_write
6205 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
6206 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6207 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6208 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6209 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
6212 static const ARMCPRegInfo zcr_el3_reginfo
= {
6213 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6214 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6215 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6216 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6217 .writefn
= zcr_write
, .raw_writefn
= raw_write
6220 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6222 CPUARMState
*env
= &cpu
->env
;
6224 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6225 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6227 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6229 if (env
->cpu_watchpoint
[n
]) {
6230 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6231 env
->cpu_watchpoint
[n
] = NULL
;
6234 if (!extract64(wcr
, 0, 1)) {
6235 /* E bit clear : watchpoint disabled */
6239 switch (extract64(wcr
, 3, 2)) {
6241 /* LSC 00 is reserved and must behave as if the wp is disabled */
6244 flags
|= BP_MEM_READ
;
6247 flags
|= BP_MEM_WRITE
;
6250 flags
|= BP_MEM_ACCESS
;
6254 /* Attempts to use both MASK and BAS fields simultaneously are
6255 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6256 * thus generating a watchpoint for every byte in the masked region.
6258 mask
= extract64(wcr
, 24, 4);
6259 if (mask
== 1 || mask
== 2) {
6260 /* Reserved values of MASK; we must act as if the mask value was
6261 * some non-reserved value, or as if the watchpoint were disabled.
6262 * We choose the latter.
6266 /* Watchpoint covers an aligned area up to 2GB in size */
6268 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6269 * whether the watchpoint fires when the unmasked bits match; we opt
6270 * to generate the exceptions.
6274 /* Watchpoint covers bytes defined by the byte address select bits */
6275 int bas
= extract64(wcr
, 5, 8);
6278 if (extract64(wvr
, 2, 1)) {
6279 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6280 * ignored, and BAS[3:0] define which bytes to watch.
6286 /* This must act as if the watchpoint is disabled */
6290 /* The BAS bits are supposed to be programmed to indicate a contiguous
6291 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6292 * we fire for each byte in the word/doubleword addressed by the WVR.
6293 * We choose to ignore any non-zero bits after the first range of 1s.
6295 basstart
= ctz32(bas
);
6296 len
= cto32(bas
>> basstart
);
6300 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6301 &env
->cpu_watchpoint
[n
]);
6304 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6307 CPUARMState
*env
= &cpu
->env
;
6309 /* Completely clear out existing QEMU watchpoints and our array, to
6310 * avoid possible stale entries following migration load.
6312 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6313 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6315 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6316 hw_watchpoint_update(cpu
, i
);
6320 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6323 ARMCPU
*cpu
= env_archcpu(env
);
6326 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6327 * register reads and behaves as if values written are sign extended.
6328 * Bits [1:0] are RES0.
6330 value
= sextract64(value
, 0, 49) & ~3ULL;
6332 raw_write(env
, ri
, value
);
6333 hw_watchpoint_update(cpu
, i
);
6336 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6339 ARMCPU
*cpu
= env_archcpu(env
);
6342 raw_write(env
, ri
, value
);
6343 hw_watchpoint_update(cpu
, i
);
6346 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6348 CPUARMState
*env
= &cpu
->env
;
6349 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6350 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6355 if (env
->cpu_breakpoint
[n
]) {
6356 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6357 env
->cpu_breakpoint
[n
] = NULL
;
6360 if (!extract64(bcr
, 0, 1)) {
6361 /* E bit clear : watchpoint disabled */
6365 bt
= extract64(bcr
, 20, 4);
6368 case 4: /* unlinked address mismatch (reserved if AArch64) */
6369 case 5: /* linked address mismatch (reserved if AArch64) */
6370 qemu_log_mask(LOG_UNIMP
,
6371 "arm: address mismatch breakpoint types not implemented\n");
6373 case 0: /* unlinked address match */
6374 case 1: /* linked address match */
6376 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6377 * we behave as if the register was sign extended. Bits [1:0] are
6378 * RES0. The BAS field is used to allow setting breakpoints on 16
6379 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6380 * a bp will fire if the addresses covered by the bp and the addresses
6381 * covered by the insn overlap but the insn doesn't start at the
6382 * start of the bp address range. We choose to require the insn and
6383 * the bp to have the same address. The constraints on writing to
6384 * BAS enforced in dbgbcr_write mean we have only four cases:
6385 * 0b0000 => no breakpoint
6386 * 0b0011 => breakpoint on addr
6387 * 0b1100 => breakpoint on addr + 2
6388 * 0b1111 => breakpoint on addr
6389 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6391 int bas
= extract64(bcr
, 5, 4);
6392 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
6401 case 2: /* unlinked context ID match */
6402 case 8: /* unlinked VMID match (reserved if no EL2) */
6403 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6404 qemu_log_mask(LOG_UNIMP
,
6405 "arm: unlinked context breakpoint types not implemented\n");
6407 case 9: /* linked VMID match (reserved if no EL2) */
6408 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6409 case 3: /* linked context ID match */
6411 /* We must generate no events for Linked context matches (unless
6412 * they are linked to by some other bp/wp, which is handled in
6413 * updates for the linking bp/wp). We choose to also generate no events
6414 * for reserved values.
6419 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6422 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6425 CPUARMState
*env
= &cpu
->env
;
6427 /* Completely clear out existing QEMU breakpoints and our array, to
6428 * avoid possible stale entries following migration load.
6430 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6431 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6433 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6434 hw_breakpoint_update(cpu
, i
);
6438 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6441 ARMCPU
*cpu
= env_archcpu(env
);
6444 raw_write(env
, ri
, value
);
6445 hw_breakpoint_update(cpu
, i
);
6448 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6451 ARMCPU
*cpu
= env_archcpu(env
);
6454 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6457 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6458 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6460 raw_write(env
, ri
, value
);
6461 hw_breakpoint_update(cpu
, i
);
6464 static void define_debug_regs(ARMCPU
*cpu
)
6466 /* Define v7 and v8 architectural debug registers.
6467 * These are just dummy implementations for now.
6470 int wrps
, brps
, ctx_cmps
;
6471 ARMCPRegInfo dbgdidr
= {
6472 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
6473 .access
= PL0_R
, .accessfn
= access_tda
,
6474 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6477 /* Note that all these register fields hold "number of Xs minus 1". */
6478 brps
= arm_num_brps(cpu
);
6479 wrps
= arm_num_wrps(cpu
);
6480 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6482 assert(ctx_cmps
<= brps
);
6484 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6485 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6487 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6488 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6491 for (i
= 0; i
< brps
; i
++) {
6492 ARMCPRegInfo dbgregs
[] = {
6493 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
6494 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6495 .access
= PL1_RW
, .accessfn
= access_tda
,
6496 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6497 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6499 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
6500 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6501 .access
= PL1_RW
, .accessfn
= access_tda
,
6502 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6503 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6507 define_arm_cp_regs(cpu
, dbgregs
);
6510 for (i
= 0; i
< wrps
; i
++) {
6511 ARMCPRegInfo dbgregs
[] = {
6512 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
6513 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6514 .access
= PL1_RW
, .accessfn
= access_tda
,
6515 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6516 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6518 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
6519 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6520 .access
= PL1_RW
, .accessfn
= access_tda
,
6521 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6522 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6526 define_arm_cp_regs(cpu
, dbgregs
);
6530 static void define_pmu_regs(ARMCPU
*cpu
)
6533 * v7 performance monitor control register: same implementor
6534 * field as main ID register, and we implement four counters in
6535 * addition to the cycle count register.
6537 unsigned int i
, pmcrn
= 4;
6538 ARMCPRegInfo pmcr
= {
6539 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6541 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6542 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6543 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6544 .raw_writefn
= raw_write
,
6546 ARMCPRegInfo pmcr64
= {
6547 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6548 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6549 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6551 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6552 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
) |
6554 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6556 define_one_arm_cp_reg(cpu
, &pmcr
);
6557 define_one_arm_cp_reg(cpu
, &pmcr64
);
6558 for (i
= 0; i
< pmcrn
; i
++) {
6559 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6560 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6561 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6562 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6563 ARMCPRegInfo pmev_regs
[] = {
6564 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6565 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6566 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6567 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6568 .accessfn
= pmreg_access
},
6569 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6570 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6571 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6573 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6574 .raw_readfn
= pmevcntr_rawread
,
6575 .raw_writefn
= pmevcntr_rawwrite
},
6576 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6577 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6578 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6579 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6580 .accessfn
= pmreg_access
},
6581 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6582 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6583 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6585 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6586 .raw_writefn
= pmevtyper_rawwrite
},
6589 define_arm_cp_regs(cpu
, pmev_regs
);
6590 g_free(pmevcntr_name
);
6591 g_free(pmevcntr_el0_name
);
6592 g_free(pmevtyper_name
);
6593 g_free(pmevtyper_el0_name
);
6595 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6596 ARMCPRegInfo v81_pmu_regs
[] = {
6597 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6598 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6599 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6600 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6601 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6602 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6603 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6604 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6607 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6609 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6610 static const ARMCPRegInfo v84_pmmir
= {
6611 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6612 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6613 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6616 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6620 /* We don't know until after realize whether there's a GICv3
6621 * attached, and that is what registers the gicv3 sysregs.
6622 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6625 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6627 ARMCPU
*cpu
= env_archcpu(env
);
6628 uint64_t pfr1
= cpu
->id_pfr1
;
6630 if (env
->gicv3state
) {
6636 #ifndef CONFIG_USER_ONLY
6637 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6639 ARMCPU
*cpu
= env_archcpu(env
);
6640 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6642 if (env
->gicv3state
) {
6649 /* Shared logic between LORID and the rest of the LOR* registers.
6650 * Secure state has already been delt with.
6652 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
6654 int el
= arm_current_el(env
);
6656 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6657 return CP_ACCESS_TRAP_EL2
;
6659 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6660 return CP_ACCESS_TRAP_EL3
;
6662 return CP_ACCESS_OK
;
6665 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6668 if (arm_is_secure_below_el3(env
)) {
6669 /* Access ok in secure mode. */
6670 return CP_ACCESS_OK
;
6672 return access_lor_ns(env
);
6675 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6676 const ARMCPRegInfo
*ri
, bool isread
)
6678 if (arm_is_secure_below_el3(env
)) {
6679 /* Access denied in secure mode. */
6680 return CP_ACCESS_TRAP
;
6682 return access_lor_ns(env
);
6686 * A trivial implementation of ARMv8.1-LOR leaves all of these
6687 * registers fixed at 0, which indicates that there are zero
6688 * supported Limited Ordering regions.
6690 static const ARMCPRegInfo lor_reginfo
[] = {
6691 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6692 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6693 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6694 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6695 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6696 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6697 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6698 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6699 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6700 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6701 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6702 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6703 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6704 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6705 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6706 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6707 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6708 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6709 .access
= PL1_R
, .accessfn
= access_lorid
,
6710 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6714 #ifdef TARGET_AARCH64
6715 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6718 int el
= arm_current_el(env
);
6721 arm_feature(env
, ARM_FEATURE_EL2
) &&
6722 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6723 return CP_ACCESS_TRAP_EL2
;
6726 arm_feature(env
, ARM_FEATURE_EL3
) &&
6727 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6728 return CP_ACCESS_TRAP_EL3
;
6730 return CP_ACCESS_OK
;
6733 static const ARMCPRegInfo pauth_reginfo
[] = {
6734 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6735 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6736 .access
= PL1_RW
, .accessfn
= access_pauth
,
6737 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6738 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6739 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6740 .access
= PL1_RW
, .accessfn
= access_pauth
,
6741 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6742 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6743 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6744 .access
= PL1_RW
, .accessfn
= access_pauth
,
6745 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6746 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6747 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6748 .access
= PL1_RW
, .accessfn
= access_pauth
,
6749 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6750 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6751 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6752 .access
= PL1_RW
, .accessfn
= access_pauth
,
6753 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6754 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6755 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6756 .access
= PL1_RW
, .accessfn
= access_pauth
,
6757 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6758 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6759 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6760 .access
= PL1_RW
, .accessfn
= access_pauth
,
6761 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6762 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6763 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6764 .access
= PL1_RW
, .accessfn
= access_pauth
,
6765 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6766 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6767 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6768 .access
= PL1_RW
, .accessfn
= access_pauth
,
6769 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6770 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6771 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6772 .access
= PL1_RW
, .accessfn
= access_pauth
,
6773 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6777 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6782 /* Success sets NZCV = 0000. */
6783 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
6785 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
6787 * ??? Failed, for unknown reasons in the crypto subsystem.
6788 * The best we can do is log the reason and return the
6789 * timed-out indication to the guest. There is no reason
6790 * we know to expect this failure to be transitory, so the
6791 * guest may well hang retrying the operation.
6793 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
6794 ri
->name
, error_get_pretty(err
));
6797 env
->ZF
= 0; /* NZCF = 0100 */
6803 /* We do not support re-seeding, so the two registers operate the same. */
6804 static const ARMCPRegInfo rndr_reginfo
[] = {
6805 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
6806 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6807 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
6808 .access
= PL0_R
, .readfn
= rndr_readfn
},
6809 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
6810 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6811 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
6812 .access
= PL0_R
, .readfn
= rndr_readfn
},
6816 #ifndef CONFIG_USER_ONLY
6817 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
6820 ARMCPU
*cpu
= env_archcpu(env
);
6821 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6822 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
6823 uint64_t vaddr_in
= (uint64_t) value
;
6824 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
6826 int mem_idx
= cpu_mmu_index(env
, false);
6828 /* This won't be crossing page boundaries */
6829 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
6835 /* RCU lock is already being held */
6836 mr
= memory_region_from_host(haddr
, &offset
);
6839 memory_region_writeback(mr
, offset
, dline_size
);
6844 static const ARMCPRegInfo dcpop_reg
[] = {
6845 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
6846 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
6847 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6848 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6852 static const ARMCPRegInfo dcpodp_reg
[] = {
6853 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
6854 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
6855 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6856 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6859 #endif /*CONFIG_USER_ONLY*/
6861 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6864 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
6865 return CP_ACCESS_TRAP_EL2
;
6868 return CP_ACCESS_OK
;
6871 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6874 int el
= arm_current_el(env
);
6877 arm_feature(env
, ARM_FEATURE_EL2
) &&
6878 !(arm_hcr_el2_eff(env
) & HCR_ATA
)) {
6879 return CP_ACCESS_TRAP_EL2
;
6882 arm_feature(env
, ARM_FEATURE_EL3
) &&
6883 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
6884 return CP_ACCESS_TRAP_EL3
;
6886 return CP_ACCESS_OK
;
6889 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6891 return env
->pstate
& PSTATE_TCO
;
6894 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6896 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
6899 static const ARMCPRegInfo mte_reginfo
[] = {
6900 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
6901 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
6902 .access
= PL1_RW
, .accessfn
= access_mte
,
6903 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
6904 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
6905 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
6906 .access
= PL1_RW
, .accessfn
= access_mte
,
6907 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
6908 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
6909 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
6910 .access
= PL2_RW
, .accessfn
= access_mte
,
6911 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
6912 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
6913 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
6915 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
6916 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
6917 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
6918 .access
= PL1_RW
, .accessfn
= access_mte
,
6919 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
6920 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
6921 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
6922 .access
= PL1_RW
, .accessfn
= access_mte
,
6923 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
6924 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
6925 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
6926 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
6927 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
6928 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
6929 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
6930 .type
= ARM_CP_NO_RAW
,
6931 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
6935 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
6936 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
6937 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
6938 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
6943 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6946 int el
= arm_current_el(env
);
6949 uint64_t sctlr
= arm_sctlr(env
, el
);
6950 if (!(sctlr
& SCTLR_EnRCTX
)) {
6951 return CP_ACCESS_TRAP
;
6953 } else if (el
== 1) {
6954 uint64_t hcr
= arm_hcr_el2_eff(env
);
6956 return CP_ACCESS_TRAP_EL2
;
6959 return CP_ACCESS_OK
;
6962 static const ARMCPRegInfo predinv_reginfo
[] = {
6963 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
6964 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
6965 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6966 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
6967 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
6968 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6969 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
6970 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
6971 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6973 * Note the AArch32 opcodes have a different OPC1.
6975 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
6976 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
6977 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6978 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
6979 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
6980 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6981 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
6982 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
6983 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6987 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6989 /* Read the high 32 bits of the current CCSIDR */
6990 return extract64(ccsidr_read(env
, ri
), 32, 32);
6993 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
6994 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
6995 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
6997 .accessfn
= access_aa64_tid2
,
6998 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7002 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7005 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7006 return CP_ACCESS_TRAP_EL2
;
7009 return CP_ACCESS_OK
;
7012 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7015 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7016 return access_aa64_tid3(env
, ri
, isread
);
7019 return CP_ACCESS_OK
;
7022 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7025 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7026 return CP_ACCESS_TRAP_EL2
;
7029 return CP_ACCESS_OK
;
7032 static const ARMCPRegInfo jazelle_regs
[] = {
7034 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7035 .access
= PL1_R
, .accessfn
= access_jazelle
,
7036 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7038 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7039 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7041 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7042 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7046 static const ARMCPRegInfo vhe_reginfo
[] = {
7047 { .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7048 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7050 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2]) },
7051 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7052 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7053 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7054 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7055 #ifndef CONFIG_USER_ONLY
7056 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7057 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7059 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7060 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7061 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7062 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7063 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7064 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7065 .resetfn
= gt_hv_timer_reset
,
7066 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7067 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7069 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7071 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7072 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7073 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7074 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7075 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7076 .access
= PL2_RW
, .accessfn
= e2h_access
,
7077 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7078 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7079 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7080 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7081 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7082 .access
= PL2_RW
, .accessfn
= e2h_access
,
7083 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7084 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7085 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7086 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7087 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7088 .access
= PL2_RW
, .accessfn
= e2h_access
,
7089 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7090 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7091 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7092 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7093 .access
= PL2_RW
, .accessfn
= e2h_access
,
7094 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7095 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7096 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7097 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7098 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7099 .access
= PL2_RW
, .accessfn
= e2h_access
,
7100 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7101 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7102 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7103 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7104 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7105 .access
= PL2_RW
, .accessfn
= e2h_access
,
7106 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7111 #ifndef CONFIG_USER_ONLY
7112 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7113 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7114 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7115 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7116 .writefn
= ats_write64
},
7117 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7118 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7119 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7120 .writefn
= ats_write64
},
7124 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7125 { .name
= "ATS1CPRP",
7126 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7127 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7128 .writefn
= ats_write
},
7129 { .name
= "ATS1CPWP",
7130 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7131 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7132 .writefn
= ats_write
},
7138 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7139 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7140 * is non-zero, which is never for ARMv7, optionally in ARMv8
7141 * and mandatorily for ARMv8.2 and up.
7142 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7143 * implementation is RAZ/WI we can ignore this detail, as we
7146 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7147 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7148 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7149 .access
= PL1_RW
, .accessfn
= access_tacr
,
7150 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7151 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7152 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7153 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7158 void register_cp_regs_for_features(ARMCPU
*cpu
)
7160 /* Register all the coprocessor registers based on feature bits */
7161 CPUARMState
*env
= &cpu
->env
;
7162 if (arm_feature(env
, ARM_FEATURE_M
)) {
7163 /* M profile has no coprocessor registers */
7167 define_arm_cp_regs(cpu
, cp_reginfo
);
7168 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7169 /* Must go early as it is full of wildcards that may be
7170 * overridden by later definitions.
7172 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7175 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7176 /* The ID registers all have impdef reset values */
7177 ARMCPRegInfo v6_idregs
[] = {
7178 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7179 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7180 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7181 .accessfn
= access_aa32_tid3
,
7182 .resetvalue
= cpu
->id_pfr0
},
7183 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7184 * the value of the GIC field until after we define these regs.
7186 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7187 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7188 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7189 .accessfn
= access_aa32_tid3
,
7190 .readfn
= id_pfr1_read
,
7191 .writefn
= arm_cp_write_ignore
},
7192 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7193 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7194 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7195 .accessfn
= access_aa32_tid3
,
7196 .resetvalue
= cpu
->isar
.id_dfr0
},
7197 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7198 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7199 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7200 .accessfn
= access_aa32_tid3
,
7201 .resetvalue
= cpu
->id_afr0
},
7202 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7203 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7204 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7205 .accessfn
= access_aa32_tid3
,
7206 .resetvalue
= cpu
->isar
.id_mmfr0
},
7207 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7208 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7209 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7210 .accessfn
= access_aa32_tid3
,
7211 .resetvalue
= cpu
->isar
.id_mmfr1
},
7212 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7213 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7214 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7215 .accessfn
= access_aa32_tid3
,
7216 .resetvalue
= cpu
->isar
.id_mmfr2
},
7217 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7218 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7219 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7220 .accessfn
= access_aa32_tid3
,
7221 .resetvalue
= cpu
->isar
.id_mmfr3
},
7222 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7223 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7224 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7225 .accessfn
= access_aa32_tid3
,
7226 .resetvalue
= cpu
->isar
.id_isar0
},
7227 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7228 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7229 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7230 .accessfn
= access_aa32_tid3
,
7231 .resetvalue
= cpu
->isar
.id_isar1
},
7232 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7233 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7234 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7235 .accessfn
= access_aa32_tid3
,
7236 .resetvalue
= cpu
->isar
.id_isar2
},
7237 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7238 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7239 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7240 .accessfn
= access_aa32_tid3
,
7241 .resetvalue
= cpu
->isar
.id_isar3
},
7242 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7243 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7244 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7245 .accessfn
= access_aa32_tid3
,
7246 .resetvalue
= cpu
->isar
.id_isar4
},
7247 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7248 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7249 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7250 .accessfn
= access_aa32_tid3
,
7251 .resetvalue
= cpu
->isar
.id_isar5
},
7252 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7253 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7254 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7255 .accessfn
= access_aa32_tid3
,
7256 .resetvalue
= cpu
->isar
.id_mmfr4
},
7257 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7258 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7259 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7260 .accessfn
= access_aa32_tid3
,
7261 .resetvalue
= cpu
->isar
.id_isar6
},
7264 define_arm_cp_regs(cpu
, v6_idregs
);
7265 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7267 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7269 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7270 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7272 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7273 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7274 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7276 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7277 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7279 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7280 ARMCPRegInfo clidr
= {
7281 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7282 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7283 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7284 .accessfn
= access_aa64_tid2
,
7285 .resetvalue
= cpu
->clidr
7287 define_one_arm_cp_reg(cpu
, &clidr
);
7288 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7289 define_debug_regs(cpu
);
7290 define_pmu_regs(cpu
);
7292 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7294 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7295 /* AArch64 ID registers, which all have impdef reset values.
7296 * Note that within the ID register ranges the unused slots
7297 * must all RAZ, not UNDEF; future architecture versions may
7298 * define new registers here.
7300 ARMCPRegInfo v8_idregs
[] = {
7302 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7303 * emulation because we don't know the right value for the
7304 * GIC field until after we define these regs.
7306 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7307 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7309 #ifdef CONFIG_USER_ONLY
7310 .type
= ARM_CP_CONST
,
7311 .resetvalue
= cpu
->isar
.id_aa64pfr0
7313 .type
= ARM_CP_NO_RAW
,
7314 .accessfn
= access_aa64_tid3
,
7315 .readfn
= id_aa64pfr0_read
,
7316 .writefn
= arm_cp_write_ignore
7319 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7320 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7321 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7322 .accessfn
= access_aa64_tid3
,
7323 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7324 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7325 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7326 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7327 .accessfn
= access_aa64_tid3
,
7329 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7330 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7331 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7332 .accessfn
= access_aa64_tid3
,
7334 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7335 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7336 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7337 .accessfn
= access_aa64_tid3
,
7338 /* At present, only SVEver == 0 is defined anyway. */
7340 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7341 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7342 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7343 .accessfn
= access_aa64_tid3
,
7345 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7346 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7347 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7348 .accessfn
= access_aa64_tid3
,
7350 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7351 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7352 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7353 .accessfn
= access_aa64_tid3
,
7355 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7356 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7357 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7358 .accessfn
= access_aa64_tid3
,
7359 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7360 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7361 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7362 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7363 .accessfn
= access_aa64_tid3
,
7364 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7365 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7366 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7367 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7368 .accessfn
= access_aa64_tid3
,
7370 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7371 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7372 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7373 .accessfn
= access_aa64_tid3
,
7375 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7376 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7377 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7378 .accessfn
= access_aa64_tid3
,
7379 .resetvalue
= cpu
->id_aa64afr0
},
7380 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7381 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7382 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7383 .accessfn
= access_aa64_tid3
,
7384 .resetvalue
= cpu
->id_aa64afr1
},
7385 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7386 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7387 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7388 .accessfn
= access_aa64_tid3
,
7390 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7391 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7392 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7393 .accessfn
= access_aa64_tid3
,
7395 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7396 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7397 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7398 .accessfn
= access_aa64_tid3
,
7399 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7400 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7401 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7402 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7403 .accessfn
= access_aa64_tid3
,
7404 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7405 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7406 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7407 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7408 .accessfn
= access_aa64_tid3
,
7410 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7411 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7412 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7413 .accessfn
= access_aa64_tid3
,
7415 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7416 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7417 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7418 .accessfn
= access_aa64_tid3
,
7420 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7421 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7422 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7423 .accessfn
= access_aa64_tid3
,
7425 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7426 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7427 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7428 .accessfn
= access_aa64_tid3
,
7430 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7431 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7432 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7433 .accessfn
= access_aa64_tid3
,
7435 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7436 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7437 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7438 .accessfn
= access_aa64_tid3
,
7439 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7440 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7441 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7442 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7443 .accessfn
= access_aa64_tid3
,
7444 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7445 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7446 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7447 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7448 .accessfn
= access_aa64_tid3
,
7449 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7450 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7451 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7452 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7453 .accessfn
= access_aa64_tid3
,
7455 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7456 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7457 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7458 .accessfn
= access_aa64_tid3
,
7460 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7461 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7462 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7463 .accessfn
= access_aa64_tid3
,
7465 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7466 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7467 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7468 .accessfn
= access_aa64_tid3
,
7470 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7471 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7472 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7473 .accessfn
= access_aa64_tid3
,
7475 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7476 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7477 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7478 .accessfn
= access_aa64_tid3
,
7479 .resetvalue
= cpu
->isar
.mvfr0
},
7480 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7481 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7482 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7483 .accessfn
= access_aa64_tid3
,
7484 .resetvalue
= cpu
->isar
.mvfr1
},
7485 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7486 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7487 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7488 .accessfn
= access_aa64_tid3
,
7489 .resetvalue
= cpu
->isar
.mvfr2
},
7490 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7491 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7492 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7493 .accessfn
= access_aa64_tid3
,
7495 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7496 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7497 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7498 .accessfn
= access_aa64_tid3
,
7500 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7501 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7502 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7503 .accessfn
= access_aa64_tid3
,
7505 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7506 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7507 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7508 .accessfn
= access_aa64_tid3
,
7510 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7511 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7512 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7513 .accessfn
= access_aa64_tid3
,
7515 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7516 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7517 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7518 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7519 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7520 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7521 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7522 .resetvalue
= cpu
->pmceid0
},
7523 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7524 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7525 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7526 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7527 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7528 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7529 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7530 .resetvalue
= cpu
->pmceid1
},
7533 #ifdef CONFIG_USER_ONLY
7534 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7535 { .name
= "ID_AA64PFR0_EL1",
7536 .exported_bits
= 0x000f000f00ff0000,
7537 .fixed_bits
= 0x0000000000000011 },
7538 { .name
= "ID_AA64PFR1_EL1",
7539 .exported_bits
= 0x00000000000000f0 },
7540 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7542 { .name
= "ID_AA64ZFR0_EL1" },
7543 { .name
= "ID_AA64MMFR0_EL1",
7544 .fixed_bits
= 0x00000000ff000000 },
7545 { .name
= "ID_AA64MMFR1_EL1" },
7546 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7548 { .name
= "ID_AA64DFR0_EL1",
7549 .fixed_bits
= 0x0000000000000006 },
7550 { .name
= "ID_AA64DFR1_EL1" },
7551 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7553 { .name
= "ID_AA64AFR*",
7555 { .name
= "ID_AA64ISAR0_EL1",
7556 .exported_bits
= 0x00fffffff0fffff0 },
7557 { .name
= "ID_AA64ISAR1_EL1",
7558 .exported_bits
= 0x000000f0ffffffff },
7559 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7561 REGUSERINFO_SENTINEL
7563 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7565 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7566 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7567 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7568 ARMCPRegInfo rvbar
= {
7569 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7570 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7571 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
7573 define_one_arm_cp_reg(cpu
, &rvbar
);
7575 define_arm_cp_regs(cpu
, v8_idregs
);
7576 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7578 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7579 uint64_t vmpidr_def
= mpidr_read_val(env
);
7580 ARMCPRegInfo vpidr_regs
[] = {
7581 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7582 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7583 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7584 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
7585 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7586 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7587 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7588 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7589 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7590 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7591 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7592 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7593 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
7594 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7595 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7596 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7598 .resetvalue
= vmpidr_def
,
7599 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7602 define_arm_cp_regs(cpu
, vpidr_regs
);
7603 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7604 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7605 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7607 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7608 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7609 ARMCPRegInfo rvbar
= {
7610 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7611 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7612 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
7614 define_one_arm_cp_reg(cpu
, &rvbar
);
7617 /* If EL2 is missing but higher ELs are enabled, we need to
7618 * register the no_el2 reginfos.
7620 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7621 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7622 * of MIDR_EL1 and MPIDR_EL1.
7624 ARMCPRegInfo vpidr_regs
[] = {
7625 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7626 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7627 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7628 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
7629 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7630 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7631 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7632 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7633 .type
= ARM_CP_NO_RAW
,
7634 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
7637 define_arm_cp_regs(cpu
, vpidr_regs
);
7638 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
7639 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7640 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
7644 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7645 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7646 ARMCPRegInfo el3_regs
[] = {
7647 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7648 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7649 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
7650 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7651 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7653 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7654 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7655 .resetvalue
= cpu
->reset_sctlr
},
7659 define_arm_cp_regs(cpu
, el3_regs
);
7661 /* The behaviour of NSACR is sufficiently various that we don't
7662 * try to describe it in a single reginfo:
7663 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7664 * reads as constant 0xc00 from NS EL1 and NS EL2
7665 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7666 * if v7 without EL3, register doesn't exist
7667 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7669 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7670 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7671 ARMCPRegInfo nsacr
= {
7672 .name
= "NSACR", .type
= ARM_CP_CONST
,
7673 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7674 .access
= PL1_RW
, .accessfn
= nsacr_access
,
7677 define_one_arm_cp_reg(cpu
, &nsacr
);
7679 ARMCPRegInfo nsacr
= {
7681 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7682 .access
= PL3_RW
| PL1_R
,
7684 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
7686 define_one_arm_cp_reg(cpu
, &nsacr
);
7689 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7690 ARMCPRegInfo nsacr
= {
7691 .name
= "NSACR", .type
= ARM_CP_CONST
,
7692 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7696 define_one_arm_cp_reg(cpu
, &nsacr
);
7700 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
7701 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7702 /* PMSAv6 not implemented */
7703 assert(arm_feature(env
, ARM_FEATURE_V7
));
7704 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7705 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
7707 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
7710 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7711 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
7712 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7713 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
7714 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
7717 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
7718 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
7720 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
7721 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
7723 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
7724 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
7726 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
7727 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
7729 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
7730 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
7732 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
7733 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
7735 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
7736 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
7738 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7739 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
7741 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7742 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
7744 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
7745 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
7747 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
7748 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
7750 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
7751 define_arm_cp_regs(cpu
, jazelle_regs
);
7753 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7754 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7755 * be read-only (ie write causes UNDEF exception).
7758 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
7759 /* Pre-v8 MIDR space.
7760 * Note that the MIDR isn't a simple constant register because
7761 * of the TI925 behaviour where writes to another register can
7762 * cause the MIDR value to change.
7764 * Unimplemented registers in the c15 0 0 0 space default to
7765 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7766 * and friends override accordingly.
7769 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
7770 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
7771 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
7772 .readfn
= midr_read
,
7773 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7774 .type
= ARM_CP_OVERRIDE
},
7775 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7777 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
7778 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7780 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
7781 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7783 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
7784 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7786 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
7787 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7789 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
7790 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7793 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
7794 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7795 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
7796 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
7797 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7798 .readfn
= midr_read
},
7799 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7800 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7801 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7802 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7803 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7804 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
7805 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7806 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7807 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
7809 .accessfn
= access_aa64_tid1
,
7810 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
7813 ARMCPRegInfo id_cp_reginfo
[] = {
7814 /* These are common to v8 and pre-v8 */
7816 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
7817 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
7818 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7819 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
7820 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
7821 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
7822 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7823 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7825 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
7827 .accessfn
= access_aa32_tid1
,
7828 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7831 /* TLBTR is specific to VMSA */
7832 ARMCPRegInfo id_tlbtr_reginfo
= {
7834 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
7836 .accessfn
= access_aa32_tid1
,
7837 .type
= ARM_CP_CONST
, .resetvalue
= 0,
7839 /* MPUIR is specific to PMSA V6+ */
7840 ARMCPRegInfo id_mpuir_reginfo
= {
7842 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7843 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7844 .resetvalue
= cpu
->pmsav7_dregion
<< 8
7846 ARMCPRegInfo crn0_wi_reginfo
= {
7847 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
7848 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
7849 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
7851 #ifdef CONFIG_USER_ONLY
7852 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
7853 { .name
= "MIDR_EL1",
7854 .exported_bits
= 0x00000000ffffffff },
7855 { .name
= "REVIDR_EL1" },
7856 REGUSERINFO_SENTINEL
7858 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
7860 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
7861 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7863 /* Register the blanket "writes ignored" value first to cover the
7864 * whole space. Then update the specific ID registers to allow write
7865 * access, so that they ignore writes rather than causing them to
7868 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
7869 for (r
= id_pre_v8_midr_cp_reginfo
;
7870 r
->type
!= ARM_CP_SENTINEL
; r
++) {
7873 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7876 id_mpuir_reginfo
.access
= PL1_RW
;
7877 id_tlbtr_reginfo
.access
= PL1_RW
;
7879 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7880 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
7882 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
7884 define_arm_cp_regs(cpu
, id_cp_reginfo
);
7885 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
7886 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
7887 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
7888 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
7892 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
7893 ARMCPRegInfo mpidr_cp_reginfo
[] = {
7894 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7895 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
7896 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
7899 #ifdef CONFIG_USER_ONLY
7900 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
7901 { .name
= "MPIDR_EL1",
7902 .fixed_bits
= 0x0000000080000000 },
7903 REGUSERINFO_SENTINEL
7905 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
7907 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
7910 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
7911 ARMCPRegInfo auxcr_reginfo
[] = {
7912 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
7913 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
7914 .access
= PL1_RW
, .accessfn
= access_tacr
,
7915 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
7916 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
7917 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
7918 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7920 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7921 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
7922 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
7926 define_arm_cp_regs(cpu
, auxcr_reginfo
);
7927 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
7928 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
7932 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
7934 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
7935 * There are two flavours:
7936 * (1) older 32-bit only cores have a simple 32-bit CBAR
7937 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
7938 * 32-bit register visible to AArch32 at a different encoding
7939 * to the "flavour 1" register and with the bits rearranged to
7940 * be able to squash a 64-bit address into the 32-bit view.
7941 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
7942 * in future if we support AArch32-only configs of some of the
7943 * AArch64 cores we might need to add a specific feature flag
7944 * to indicate cores with "flavour 2" CBAR.
7946 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7947 /* 32 bit view is [31:18] 0...0 [43:32]. */
7948 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
7949 | extract64(cpu
->reset_cbar
, 32, 12);
7950 ARMCPRegInfo cbar_reginfo
[] = {
7952 .type
= ARM_CP_CONST
,
7953 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
7954 .access
= PL1_R
, .resetvalue
= cbar32
},
7955 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7956 .type
= ARM_CP_CONST
,
7957 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
7958 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
7961 /* We don't implement a r/w 64 bit CBAR currently */
7962 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
7963 define_arm_cp_regs(cpu
, cbar_reginfo
);
7965 ARMCPRegInfo cbar
= {
7967 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
7968 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
7969 .fieldoffset
= offsetof(CPUARMState
,
7970 cp15
.c15_config_base_address
)
7972 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
7973 cbar
.access
= PL1_R
;
7974 cbar
.fieldoffset
= 0;
7975 cbar
.type
= ARM_CP_CONST
;
7977 define_one_arm_cp_reg(cpu
, &cbar
);
7981 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
7982 ARMCPRegInfo vbar_cp_reginfo
[] = {
7983 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
7984 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
7985 .access
= PL1_RW
, .writefn
= vbar_write
,
7986 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
7987 offsetof(CPUARMState
, cp15
.vbar_ns
) },
7991 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
7994 /* Generic registers whose values depend on the implementation */
7996 ARMCPRegInfo sctlr
= {
7997 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
7998 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
7999 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8001 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8002 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8003 .raw_writefn
= raw_write
,
8005 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8006 /* Normally we would always end the TB on an SCTLR write, but Linux
8007 * arch/arm/mach-pxa/sleep.S expects two instructions following
8008 * an MMU enable to execute from cache. Imitate this behaviour.
8010 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8012 define_one_arm_cp_reg(cpu
, &sctlr
);
8015 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8016 define_arm_cp_regs(cpu
, lor_reginfo
);
8018 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8019 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8021 #ifndef CONFIG_USER_ONLY
8022 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8023 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8025 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8026 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8029 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8030 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8033 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8034 define_arm_cp_regs(cpu
, vhe_reginfo
);
8037 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8038 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
8039 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
8040 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
8042 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
8044 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8045 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
8049 #ifdef TARGET_AARCH64
8050 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8051 define_arm_cp_regs(cpu
, pauth_reginfo
);
8053 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8054 define_arm_cp_regs(cpu
, rndr_reginfo
);
8056 #ifndef CONFIG_USER_ONLY
8057 /* Data Cache clean instructions up to PoP */
8058 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8059 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8061 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8062 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8065 #endif /*CONFIG_USER_ONLY*/
8068 * If full MTE is enabled, add all of the system registers.
8069 * If only "instructions available at EL0" are enabled,
8070 * then define only a RAZ/WI version of PSTATE.TCO.
8072 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8073 define_arm_cp_regs(cpu
, mte_reginfo
);
8074 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8075 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8079 if (cpu_isar_feature(any_predinv
, cpu
)) {
8080 define_arm_cp_regs(cpu
, predinv_reginfo
);
8083 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8084 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8087 #ifndef CONFIG_USER_ONLY
8089 * Register redirections and aliases must be done last,
8090 * after the registers from the other extensions have been defined.
8092 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8093 define_arm_vh_e2h_redirects_aliases(cpu
);
8098 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
8100 CPUState
*cs
= CPU(cpu
);
8101 CPUARMState
*env
= &cpu
->env
;
8103 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8105 * The lower part of each SVE register aliases to the FPU
8106 * registers so we don't need to include both.
8108 #ifdef TARGET_AARCH64
8109 if (isar_feature_aa64_sve(&cpu
->isar
)) {
8110 gdb_register_coprocessor(cs
, arm_gdb_get_svereg
, arm_gdb_set_svereg
,
8111 arm_gen_dynamic_svereg_xml(cs
, cs
->gdb_num_regs
),
8112 "sve-registers.xml", 0);
8116 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
8117 aarch64_fpu_gdb_set_reg
,
8118 34, "aarch64-fpu.xml", 0);
8120 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
8121 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8122 51, "arm-neon.xml", 0);
8123 } else if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
8124 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8125 35, "arm-vfp3.xml", 0);
8126 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
8127 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8128 19, "arm-vfp.xml", 0);
8130 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
8131 arm_gen_dynamic_sysreg_xml(cs
, cs
->gdb_num_regs
),
8132 "system-registers.xml", 0);
8136 /* Sort alphabetically by type name, except for "any". */
8137 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8139 ObjectClass
*class_a
= (ObjectClass
*)a
;
8140 ObjectClass
*class_b
= (ObjectClass
*)b
;
8141 const char *name_a
, *name_b
;
8143 name_a
= object_class_get_name(class_a
);
8144 name_b
= object_class_get_name(class_b
);
8145 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8147 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8150 return strcmp(name_a
, name_b
);
8154 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8156 ObjectClass
*oc
= data
;
8157 const char *typename
;
8160 typename
= object_class_get_name(oc
);
8161 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8162 qemu_printf(" %s\n", name
);
8166 void arm_cpu_list(void)
8170 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8171 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8172 qemu_printf("Available CPUs:\n");
8173 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8177 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8179 ObjectClass
*oc
= data
;
8180 CpuDefinitionInfoList
**cpu_list
= user_data
;
8181 CpuDefinitionInfoList
*entry
;
8182 CpuDefinitionInfo
*info
;
8183 const char *typename
;
8185 typename
= object_class_get_name(oc
);
8186 info
= g_malloc0(sizeof(*info
));
8187 info
->name
= g_strndup(typename
,
8188 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8189 info
->q_typename
= g_strdup(typename
);
8191 entry
= g_malloc0(sizeof(*entry
));
8192 entry
->value
= info
;
8193 entry
->next
= *cpu_list
;
8197 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8199 CpuDefinitionInfoList
*cpu_list
= NULL
;
8202 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8203 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8209 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8210 void *opaque
, int state
, int secstate
,
8211 int crm
, int opc1
, int opc2
,
8214 /* Private utility function for define_one_arm_cp_reg_with_opaque():
8215 * add a single reginfo struct to the hash table.
8217 uint32_t *key
= g_new(uint32_t, 1);
8218 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
8219 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
8220 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
8222 r2
->name
= g_strdup(name
);
8223 /* Reset the secure state to the specific incoming state. This is
8224 * necessary as the register may have been defined with both states.
8226 r2
->secure
= secstate
;
8228 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
8229 /* Register is banked (using both entries in array).
8230 * Overwriting fieldoffset as the array is only used to define
8231 * banked registers but later only fieldoffset is used.
8233 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8236 if (state
== ARM_CP_STATE_AA32
) {
8237 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
8238 /* If the register is banked then we don't need to migrate or
8239 * reset the 32-bit instance in certain cases:
8241 * 1) If the register has both 32-bit and 64-bit instances then we
8242 * can count on the 64-bit instance taking care of the
8244 * 2) If ARMv8 is enabled then we can count on a 64-bit version
8245 * taking care of the secure bank. This requires that separate
8246 * 32 and 64-bit definitions are provided.
8248 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8249 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
8250 r2
->type
|= ARM_CP_ALIAS
;
8252 } else if ((secstate
!= r
->secure
) && !ns
) {
8253 /* The register is not banked so we only want to allow migration of
8254 * the non-secure instance.
8256 r2
->type
|= ARM_CP_ALIAS
;
8259 if (r
->state
== ARM_CP_STATE_BOTH
) {
8260 /* We assume it is a cp15 register if the .cp field is left unset.
8266 #ifdef HOST_WORDS_BIGENDIAN
8267 if (r2
->fieldoffset
) {
8268 r2
->fieldoffset
+= sizeof(uint32_t);
8273 if (state
== ARM_CP_STATE_AA64
) {
8274 /* To allow abbreviation of ARMCPRegInfo
8275 * definitions, we treat cp == 0 as equivalent to
8276 * the value for "standard guest-visible sysreg".
8277 * STATE_BOTH definitions are also always "standard
8278 * sysreg" in their AArch64 view (the .cp value may
8279 * be non-zero for the benefit of the AArch32 view).
8281 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8282 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
8284 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
8285 r2
->opc0
, opc1
, opc2
);
8287 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
8290 r2
->opaque
= opaque
;
8292 /* reginfo passed to helpers is correct for the actual access,
8293 * and is never ARM_CP_STATE_BOTH:
8296 /* Make sure reginfo passed to helpers for wildcarded regs
8297 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8302 /* By convention, for wildcarded registers only the first
8303 * entry is used for migration; the others are marked as
8304 * ALIAS so we don't try to transfer the register
8305 * multiple times. Special registers (ie NOP/WFI) are
8306 * never migratable and not even raw-accessible.
8308 if ((r
->type
& ARM_CP_SPECIAL
)) {
8309 r2
->type
|= ARM_CP_NO_RAW
;
8311 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8312 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8313 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8314 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8317 /* Check that raw accesses are either forbidden or handled. Note that
8318 * we can't assert this earlier because the setup of fieldoffset for
8319 * banked registers has to be done first.
8321 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8322 assert(!raw_accessors_invalid(r2
));
8325 /* Overriding of an existing definition must be explicitly
8328 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8329 ARMCPRegInfo
*oldreg
;
8330 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
8331 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
8332 fprintf(stderr
, "Register redefined: cp=%d %d bit "
8333 "crn=%d crm=%d opc1=%d opc2=%d, "
8334 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
8335 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
8336 oldreg
->name
, r2
->name
);
8337 g_assert_not_reached();
8340 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
8344 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8345 const ARMCPRegInfo
*r
, void *opaque
)
8347 /* Define implementations of coprocessor registers.
8348 * We store these in a hashtable because typically
8349 * there are less than 150 registers in a space which
8350 * is 16*16*16*8*8 = 262144 in size.
8351 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8352 * If a register is defined twice then the second definition is
8353 * used, so this can be used to define some generic registers and
8354 * then override them with implementation specific variations.
8355 * At least one of the original and the second definition should
8356 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8357 * against accidental use.
8359 * The state field defines whether the register is to be
8360 * visible in the AArch32 or AArch64 execution state. If the
8361 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8362 * reginfo structure for the AArch32 view, which sees the lower
8363 * 32 bits of the 64 bit register.
8365 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8366 * be wildcarded. AArch64 registers are always considered to be 64
8367 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8368 * the register, if any.
8370 int crm
, opc1
, opc2
, state
;
8371 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8372 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8373 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8374 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8375 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8376 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8377 /* 64 bit registers have only CRm and Opc1 fields */
8378 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8379 /* op0 only exists in the AArch64 encodings */
8380 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8381 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8382 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8383 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8384 * encodes a minimum access level for the register. We roll this
8385 * runtime check into our general permission check code, so check
8386 * here that the reginfo's specified permissions are strict enough
8387 * to encompass the generic architectural permission check.
8389 if (r
->state
!= ARM_CP_STATE_AA32
) {
8393 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8394 mask
= PL0U_R
| PL1_RW
;
8414 /* min_EL EL1, secure mode only (we don't check the latter) */
8418 /* broken reginfo with out-of-range opc1 */
8422 /* assert our permissions are not too lax (stricter is fine) */
8423 assert((r
->access
& ~mask
) == 0);
8426 /* Check that the register definition has enough info to handle
8427 * reads and writes if they are permitted.
8429 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
8430 if (r
->access
& PL3_R
) {
8431 assert((r
->fieldoffset
||
8432 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8435 if (r
->access
& PL3_W
) {
8436 assert((r
->fieldoffset
||
8437 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8441 /* Bad type field probably means missing sentinel at end of reg list */
8442 assert(cptype_valid(r
->type
));
8443 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8444 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8445 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8446 for (state
= ARM_CP_STATE_AA32
;
8447 state
<= ARM_CP_STATE_AA64
; state
++) {
8448 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8451 if (state
== ARM_CP_STATE_AA32
) {
8452 /* Under AArch32 CP registers can be common
8453 * (same for secure and non-secure world) or banked.
8457 switch (r
->secure
) {
8458 case ARM_CP_SECSTATE_S
:
8459 case ARM_CP_SECSTATE_NS
:
8460 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8461 r
->secure
, crm
, opc1
, opc2
,
8465 name
= g_strdup_printf("%s_S", r
->name
);
8466 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8468 crm
, opc1
, opc2
, name
);
8470 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8472 crm
, opc1
, opc2
, r
->name
);
8476 /* AArch64 registers get mapped to non-secure instance
8478 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8480 crm
, opc1
, opc2
, r
->name
);
8488 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
8489 const ARMCPRegInfo
*regs
, void *opaque
)
8491 /* Define a whole list of registers */
8492 const ARMCPRegInfo
*r
;
8493 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8494 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
8499 * Modify ARMCPRegInfo for access from userspace.
8501 * This is a data driven modification directed by
8502 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8503 * user-space cannot alter any values and dynamic values pertaining to
8504 * execution state are hidden from user space view anyway.
8506 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
8508 const ARMCPRegUserSpaceInfo
*m
;
8511 for (m
= mods
; m
->name
; m
++) {
8512 GPatternSpec
*pat
= NULL
;
8514 pat
= g_pattern_spec_new(m
->name
);
8516 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8517 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8518 r
->type
= ARM_CP_CONST
;
8522 } else if (strcmp(r
->name
, m
->name
) == 0) {
8523 r
->type
= ARM_CP_CONST
;
8525 r
->resetvalue
&= m
->exported_bits
;
8526 r
->resetvalue
|= m
->fixed_bits
;
8531 g_pattern_spec_free(pat
);
8536 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8538 return g_hash_table_lookup(cpregs
, &encoded_cp
);
8541 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8544 /* Helper coprocessor write function for write-ignore registers */
8547 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8549 /* Helper coprocessor write function for read-as-zero registers */
8553 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8555 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8558 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8560 /* Return true if it is not valid for us to switch to
8561 * this CPU mode (ie all the UNPREDICTABLE cases in
8562 * the ARM ARM CPSRWriteByInstr pseudocode).
8565 /* Changes to or from Hyp via MSR and CPS are illegal. */
8566 if (write_type
== CPSRWriteByInstr
&&
8567 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8568 mode
== ARM_CPU_MODE_HYP
)) {
8573 case ARM_CPU_MODE_USR
:
8575 case ARM_CPU_MODE_SYS
:
8576 case ARM_CPU_MODE_SVC
:
8577 case ARM_CPU_MODE_ABT
:
8578 case ARM_CPU_MODE_UND
:
8579 case ARM_CPU_MODE_IRQ
:
8580 case ARM_CPU_MODE_FIQ
:
8581 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8582 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8584 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8585 * and CPS are treated as illegal mode changes.
8587 if (write_type
== CPSRWriteByInstr
&&
8588 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8589 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
8593 case ARM_CPU_MODE_HYP
:
8594 return !arm_feature(env
, ARM_FEATURE_EL2
)
8595 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
8596 case ARM_CPU_MODE_MON
:
8597 return arm_current_el(env
) < 3;
8603 uint32_t cpsr_read(CPUARMState
*env
)
8606 ZF
= (env
->ZF
== 0);
8607 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
8608 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
8609 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
8610 | ((env
->condexec_bits
& 0xfc) << 8)
8611 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
8614 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
8615 CPSRWriteType write_type
)
8617 uint32_t changed_daif
;
8619 if (mask
& CPSR_NZCV
) {
8620 env
->ZF
= (~val
) & CPSR_Z
;
8622 env
->CF
= (val
>> 29) & 1;
8623 env
->VF
= (val
<< 3) & 0x80000000;
8626 env
->QF
= ((val
& CPSR_Q
) != 0);
8628 env
->thumb
= ((val
& CPSR_T
) != 0);
8629 if (mask
& CPSR_IT_0_1
) {
8630 env
->condexec_bits
&= ~3;
8631 env
->condexec_bits
|= (val
>> 25) & 3;
8633 if (mask
& CPSR_IT_2_7
) {
8634 env
->condexec_bits
&= 3;
8635 env
->condexec_bits
|= (val
>> 8) & 0xfc;
8637 if (mask
& CPSR_GE
) {
8638 env
->GE
= (val
>> 16) & 0xf;
8641 /* In a V7 implementation that includes the security extensions but does
8642 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8643 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8644 * bits respectively.
8646 * In a V8 implementation, it is permitted for privileged software to
8647 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8649 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
8650 arm_feature(env
, ARM_FEATURE_EL3
) &&
8651 !arm_feature(env
, ARM_FEATURE_EL2
) &&
8652 !arm_is_secure(env
)) {
8654 changed_daif
= (env
->daif
^ val
) & mask
;
8656 if (changed_daif
& CPSR_A
) {
8657 /* Check to see if we are allowed to change the masking of async
8658 * abort exceptions from a non-secure state.
8660 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
8661 qemu_log_mask(LOG_GUEST_ERROR
,
8662 "Ignoring attempt to switch CPSR_A flag from "
8663 "non-secure world with SCR.AW bit clear\n");
8668 if (changed_daif
& CPSR_F
) {
8669 /* Check to see if we are allowed to change the masking of FIQ
8670 * exceptions from a non-secure state.
8672 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
8673 qemu_log_mask(LOG_GUEST_ERROR
,
8674 "Ignoring attempt to switch CPSR_F flag from "
8675 "non-secure world with SCR.FW bit clear\n");
8679 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8680 * If this bit is set software is not allowed to mask
8681 * FIQs, but is allowed to set CPSR_F to 0.
8683 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
8685 qemu_log_mask(LOG_GUEST_ERROR
,
8686 "Ignoring attempt to enable CPSR_F flag "
8687 "(non-maskable FIQ [NMFI] support enabled)\n");
8693 env
->daif
&= ~(CPSR_AIF
& mask
);
8694 env
->daif
|= val
& CPSR_AIF
& mask
;
8696 if (write_type
!= CPSRWriteRaw
&&
8697 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
8698 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
8699 /* Note that we can only get here in USR mode if this is a
8700 * gdb stub write; for this case we follow the architectural
8701 * behaviour for guest writes in USR mode of ignoring an attempt
8702 * to switch mode. (Those are caught by translate.c for writes
8703 * triggered by guest instructions.)
8706 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
8707 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8708 * v7, and has defined behaviour in v8:
8709 * + leave CPSR.M untouched
8710 * + allow changes to the other CPSR fields
8712 * For user changes via the GDB stub, we don't set PSTATE.IL,
8713 * as this would be unnecessarily harsh for a user error.
8716 if (write_type
!= CPSRWriteByGDBStub
&&
8717 arm_feature(env
, ARM_FEATURE_V8
)) {
8721 qemu_log_mask(LOG_GUEST_ERROR
,
8722 "Illegal AArch32 mode switch attempt from %s to %s\n",
8723 aarch32_mode_name(env
->uncached_cpsr
),
8724 aarch32_mode_name(val
));
8726 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
8727 write_type
== CPSRWriteExceptionReturn
?
8728 "Exception return from AArch32" :
8729 "AArch32 mode switch from",
8730 aarch32_mode_name(env
->uncached_cpsr
),
8731 aarch32_mode_name(val
), env
->regs
[15]);
8732 switch_mode(env
, val
& CPSR_M
);
8735 mask
&= ~CACHED_CPSR_BITS
;
8736 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
8739 /* Sign/zero extend */
8740 uint32_t HELPER(sxtb16
)(uint32_t x
)
8743 res
= (uint16_t)(int8_t)x
;
8744 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
8748 uint32_t HELPER(uxtb16
)(uint32_t x
)
8751 res
= (uint16_t)(uint8_t)x
;
8752 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
8756 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
8760 if (num
== INT_MIN
&& den
== -1)
8765 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
8772 uint32_t HELPER(rbit
)(uint32_t x
)
8777 #ifdef CONFIG_USER_ONLY
8779 static void switch_mode(CPUARMState
*env
, int mode
)
8781 ARMCPU
*cpu
= env_archcpu(env
);
8783 if (mode
!= ARM_CPU_MODE_USR
) {
8784 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
8788 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8789 uint32_t cur_el
, bool secure
)
8794 void aarch64_sync_64_to_32(CPUARMState
*env
)
8796 g_assert_not_reached();
8801 static void switch_mode(CPUARMState
*env
, int mode
)
8806 old_mode
= env
->uncached_cpsr
& CPSR_M
;
8807 if (mode
== old_mode
)
8810 if (old_mode
== ARM_CPU_MODE_FIQ
) {
8811 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8812 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
8813 } else if (mode
== ARM_CPU_MODE_FIQ
) {
8814 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8815 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
8818 i
= bank_number(old_mode
);
8819 env
->banked_r13
[i
] = env
->regs
[13];
8820 env
->banked_spsr
[i
] = env
->spsr
;
8822 i
= bank_number(mode
);
8823 env
->regs
[13] = env
->banked_r13
[i
];
8824 env
->spsr
= env
->banked_spsr
[i
];
8826 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
8827 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
8830 /* Physical Interrupt Target EL Lookup Table
8832 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
8834 * The below multi-dimensional table is used for looking up the target
8835 * exception level given numerous condition criteria. Specifically, the
8836 * target EL is based on SCR and HCR routing controls as well as the
8837 * currently executing EL and secure state.
8840 * target_el_table[2][2][2][2][2][4]
8841 * | | | | | +--- Current EL
8842 * | | | | +------ Non-secure(0)/Secure(1)
8843 * | | | +--------- HCR mask override
8844 * | | +------------ SCR exec state control
8845 * | +--------------- SCR mask override
8846 * +------------------ 32-bit(0)/64-bit(1) EL3
8848 * The table values are as such:
8852 * The ARM ARM target EL table includes entries indicating that an "exception
8853 * is not taken". The two cases where this is applicable are:
8854 * 1) An exception is taken from EL3 but the SCR does not have the exception
8856 * 2) An exception is taken from EL2 but the HCR does not have the exception
8858 * In these two cases, the below table contain a target of EL1. This value is
8859 * returned as it is expected that the consumer of the table data will check
8860 * for "target EL >= current EL" to ensure the exception is not taken.
8864 * BIT IRQ IMO Non-secure Secure
8865 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
8867 static const int8_t target_el_table
[2][2][2][2][2][4] = {
8868 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8869 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
8870 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8871 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
8872 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8873 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
8874 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8875 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
8876 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
8877 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
8878 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
8879 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
8880 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8881 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
8882 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8883 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
8887 * Determine the target EL for physical exceptions
8889 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8890 uint32_t cur_el
, bool secure
)
8892 CPUARMState
*env
= cs
->env_ptr
;
8897 /* Is the highest EL AArch64? */
8898 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
8901 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8902 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
8904 /* Either EL2 is the highest EL (and so the EL2 register width
8905 * is given by is64); or there is no EL2 or EL3, in which case
8906 * the value of 'rw' does not affect the table lookup anyway.
8911 hcr_el2
= arm_hcr_el2_eff(env
);
8914 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
8915 hcr
= hcr_el2
& HCR_IMO
;
8918 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
8919 hcr
= hcr_el2
& HCR_FMO
;
8922 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
8923 hcr
= hcr_el2
& HCR_AMO
;
8928 * For these purposes, TGE and AMO/IMO/FMO both force the
8929 * interrupt to EL2. Fold TGE into the bit extracted above.
8931 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
8933 /* Perform a table-lookup for the target EL given the current state */
8934 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
8936 assert(target_el
> 0);
8941 void arm_log_exception(int idx
)
8943 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
8944 const char *exc
= NULL
;
8945 static const char * const excnames
[] = {
8946 [EXCP_UDEF
] = "Undefined Instruction",
8948 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
8949 [EXCP_DATA_ABORT
] = "Data Abort",
8952 [EXCP_BKPT
] = "Breakpoint",
8953 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
8954 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
8955 [EXCP_HVC
] = "Hypervisor Call",
8956 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
8957 [EXCP_SMC
] = "Secure Monitor Call",
8958 [EXCP_VIRQ
] = "Virtual IRQ",
8959 [EXCP_VFIQ
] = "Virtual FIQ",
8960 [EXCP_SEMIHOST
] = "Semihosting call",
8961 [EXCP_NOCP
] = "v7M NOCP UsageFault",
8962 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
8963 [EXCP_STKOF
] = "v8M STKOF UsageFault",
8964 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
8965 [EXCP_LSERR
] = "v8M LSERR UsageFault",
8966 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
8969 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
8970 exc
= excnames
[idx
];
8975 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
8980 * Function used to synchronize QEMU's AArch64 register set with AArch32
8981 * register set. This is necessary when switching between AArch32 and AArch64
8984 void aarch64_sync_32_to_64(CPUARMState
*env
)
8987 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8989 /* We can blanket copy R[0:7] to X[0:7] */
8990 for (i
= 0; i
< 8; i
++) {
8991 env
->xregs
[i
] = env
->regs
[i
];
8995 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
8996 * Otherwise, they come from the banked user regs.
8998 if (mode
== ARM_CPU_MODE_FIQ
) {
8999 for (i
= 8; i
< 13; i
++) {
9000 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9003 for (i
= 8; i
< 13; i
++) {
9004 env
->xregs
[i
] = env
->regs
[i
];
9009 * Registers x13-x23 are the various mode SP and FP registers. Registers
9010 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9011 * from the mode banked register.
9013 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9014 env
->xregs
[13] = env
->regs
[13];
9015 env
->xregs
[14] = env
->regs
[14];
9017 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9018 /* HYP is an exception in that it is copied from r14 */
9019 if (mode
== ARM_CPU_MODE_HYP
) {
9020 env
->xregs
[14] = env
->regs
[14];
9022 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9026 if (mode
== ARM_CPU_MODE_HYP
) {
9027 env
->xregs
[15] = env
->regs
[13];
9029 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9032 if (mode
== ARM_CPU_MODE_IRQ
) {
9033 env
->xregs
[16] = env
->regs
[14];
9034 env
->xregs
[17] = env
->regs
[13];
9036 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9037 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9040 if (mode
== ARM_CPU_MODE_SVC
) {
9041 env
->xregs
[18] = env
->regs
[14];
9042 env
->xregs
[19] = env
->regs
[13];
9044 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9045 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9048 if (mode
== ARM_CPU_MODE_ABT
) {
9049 env
->xregs
[20] = env
->regs
[14];
9050 env
->xregs
[21] = env
->regs
[13];
9052 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9053 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9056 if (mode
== ARM_CPU_MODE_UND
) {
9057 env
->xregs
[22] = env
->regs
[14];
9058 env
->xregs
[23] = env
->regs
[13];
9060 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9061 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9065 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9066 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9067 * FIQ bank for r8-r14.
9069 if (mode
== ARM_CPU_MODE_FIQ
) {
9070 for (i
= 24; i
< 31; i
++) {
9071 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9074 for (i
= 24; i
< 29; i
++) {
9075 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9077 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9078 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9081 env
->pc
= env
->regs
[15];
9085 * Function used to synchronize QEMU's AArch32 register set with AArch64
9086 * register set. This is necessary when switching between AArch32 and AArch64
9089 void aarch64_sync_64_to_32(CPUARMState
*env
)
9092 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9094 /* We can blanket copy X[0:7] to R[0:7] */
9095 for (i
= 0; i
< 8; i
++) {
9096 env
->regs
[i
] = env
->xregs
[i
];
9100 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9101 * Otherwise, we copy x8-x12 into the banked user regs.
9103 if (mode
== ARM_CPU_MODE_FIQ
) {
9104 for (i
= 8; i
< 13; i
++) {
9105 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9108 for (i
= 8; i
< 13; i
++) {
9109 env
->regs
[i
] = env
->xregs
[i
];
9114 * Registers r13 & r14 depend on the current mode.
9115 * If we are in a given mode, we copy the corresponding x registers to r13
9116 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9119 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9120 env
->regs
[13] = env
->xregs
[13];
9121 env
->regs
[14] = env
->xregs
[14];
9123 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9126 * HYP is an exception in that it does not have its own banked r14 but
9127 * shares the USR r14
9129 if (mode
== ARM_CPU_MODE_HYP
) {
9130 env
->regs
[14] = env
->xregs
[14];
9132 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9136 if (mode
== ARM_CPU_MODE_HYP
) {
9137 env
->regs
[13] = env
->xregs
[15];
9139 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9142 if (mode
== ARM_CPU_MODE_IRQ
) {
9143 env
->regs
[14] = env
->xregs
[16];
9144 env
->regs
[13] = env
->xregs
[17];
9146 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9147 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9150 if (mode
== ARM_CPU_MODE_SVC
) {
9151 env
->regs
[14] = env
->xregs
[18];
9152 env
->regs
[13] = env
->xregs
[19];
9154 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9155 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9158 if (mode
== ARM_CPU_MODE_ABT
) {
9159 env
->regs
[14] = env
->xregs
[20];
9160 env
->regs
[13] = env
->xregs
[21];
9162 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9163 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9166 if (mode
== ARM_CPU_MODE_UND
) {
9167 env
->regs
[14] = env
->xregs
[22];
9168 env
->regs
[13] = env
->xregs
[23];
9170 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9171 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9174 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9175 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9176 * FIQ bank for r8-r14.
9178 if (mode
== ARM_CPU_MODE_FIQ
) {
9179 for (i
= 24; i
< 31; i
++) {
9180 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9183 for (i
= 24; i
< 29; i
++) {
9184 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9186 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9187 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9190 env
->regs
[15] = env
->pc
;
9193 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9194 uint32_t mask
, uint32_t offset
,
9199 /* Change the CPU state so as to actually take the exception. */
9200 switch_mode(env
, new_mode
);
9203 * For exceptions taken to AArch32 we must clear the SS bit in both
9204 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9206 env
->uncached_cpsr
&= ~PSTATE_SS
;
9207 env
->spsr
= cpsr_read(env
);
9208 /* Clear IT bits. */
9209 env
->condexec_bits
= 0;
9210 /* Switch to the new mode, and to the correct instruction set. */
9211 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9213 /* This must be after mode switching. */
9214 new_el
= arm_current_el(env
);
9216 /* Set new mode endianness */
9217 env
->uncached_cpsr
&= ~CPSR_E
;
9218 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9219 env
->uncached_cpsr
|= CPSR_E
;
9221 /* J and IL must always be cleared for exception entry */
9222 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9225 if (new_mode
== ARM_CPU_MODE_HYP
) {
9226 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9227 env
->elr_el
[2] = env
->regs
[15];
9229 /* CPSR.PAN is normally preserved preserved unless... */
9230 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9233 if (!arm_is_secure_below_el3(env
)) {
9234 /* ... the target is EL3, from non-secure state. */
9235 env
->uncached_cpsr
&= ~CPSR_PAN
;
9238 /* ... the target is EL3, from secure state ... */
9241 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9242 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9243 env
->uncached_cpsr
|= CPSR_PAN
;
9249 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9250 * and we should just guard the thumb mode on V4
9252 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9254 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9256 env
->regs
[14] = env
->regs
[15] + offset
;
9258 env
->regs
[15] = newpc
;
9259 arm_rebuild_hflags(env
);
9262 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9265 * Handle exception entry to Hyp mode; this is sufficiently
9266 * different to entry to other AArch32 modes that we handle it
9269 * The vector table entry used is always the 0x14 Hyp mode entry point,
9270 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9271 * The offset applied to the preferred return address is always zero
9272 * (see DDI0487C.a section G1.12.3).
9273 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9275 uint32_t addr
, mask
;
9276 ARMCPU
*cpu
= ARM_CPU(cs
);
9277 CPUARMState
*env
= &cpu
->env
;
9279 switch (cs
->exception_index
) {
9287 /* Fall through to prefetch abort. */
9288 case EXCP_PREFETCH_ABORT
:
9289 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9290 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9291 (uint32_t)env
->exception
.vaddress
);
9294 case EXCP_DATA_ABORT
:
9295 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9296 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9297 (uint32_t)env
->exception
.vaddress
);
9313 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9316 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9317 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9319 * QEMU syndrome values are v8-style. v7 has the IL bit
9320 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9321 * If this is a v7 CPU, squash the IL bit in those cases.
9323 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9324 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9325 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9326 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9327 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9330 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9333 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9338 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9341 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9344 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9348 addr
+= env
->cp15
.hvbar
;
9350 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9353 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9355 ARMCPU
*cpu
= ARM_CPU(cs
);
9356 CPUARMState
*env
= &cpu
->env
;
9363 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9364 switch (syn_get_ec(env
->exception
.syndrome
)) {
9366 case EC_BREAKPOINT_SAME_EL
:
9370 case EC_WATCHPOINT_SAME_EL
:
9376 case EC_VECTORCATCH
:
9385 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9388 if (env
->exception
.target_el
== 2) {
9389 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9393 switch (cs
->exception_index
) {
9395 new_mode
= ARM_CPU_MODE_UND
;
9404 new_mode
= ARM_CPU_MODE_SVC
;
9407 /* The PC already points to the next instruction. */
9411 /* Fall through to prefetch abort. */
9412 case EXCP_PREFETCH_ABORT
:
9413 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9414 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9415 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9416 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9417 new_mode
= ARM_CPU_MODE_ABT
;
9419 mask
= CPSR_A
| CPSR_I
;
9422 case EXCP_DATA_ABORT
:
9423 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9424 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9425 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9427 (uint32_t)env
->exception
.vaddress
);
9428 new_mode
= ARM_CPU_MODE_ABT
;
9430 mask
= CPSR_A
| CPSR_I
;
9434 new_mode
= ARM_CPU_MODE_IRQ
;
9436 /* Disable IRQ and imprecise data aborts. */
9437 mask
= CPSR_A
| CPSR_I
;
9439 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9440 /* IRQ routed to monitor mode */
9441 new_mode
= ARM_CPU_MODE_MON
;
9446 new_mode
= ARM_CPU_MODE_FIQ
;
9448 /* Disable FIQ, IRQ and imprecise data aborts. */
9449 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9450 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9451 /* FIQ routed to monitor mode */
9452 new_mode
= ARM_CPU_MODE_MON
;
9457 new_mode
= ARM_CPU_MODE_IRQ
;
9459 /* Disable IRQ and imprecise data aborts. */
9460 mask
= CPSR_A
| CPSR_I
;
9464 new_mode
= ARM_CPU_MODE_FIQ
;
9466 /* Disable FIQ, IRQ and imprecise data aborts. */
9467 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9471 new_mode
= ARM_CPU_MODE_MON
;
9473 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9477 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9478 return; /* Never happens. Keep compiler happy. */
9481 if (new_mode
== ARM_CPU_MODE_MON
) {
9482 addr
+= env
->cp15
.mvbar
;
9483 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9484 /* High vectors. When enabled, base address cannot be remapped. */
9487 /* ARM v7 architectures provide a vector base address register to remap
9488 * the interrupt vector table.
9489 * This register is only followed in non-monitor mode, and is banked.
9490 * Note: only bits 31:5 are valid.
9492 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9495 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9496 env
->cp15
.scr_el3
&= ~SCR_NS
;
9499 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9502 /* Handle exception entry to a target EL which is using AArch64 */
9503 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9505 ARMCPU
*cpu
= ARM_CPU(cs
);
9506 CPUARMState
*env
= &cpu
->env
;
9507 unsigned int new_el
= env
->exception
.target_el
;
9508 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9509 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9510 unsigned int old_mode
;
9511 unsigned int cur_el
= arm_current_el(env
);
9514 * Note that new_el can never be 0. If cur_el is 0, then
9515 * el0_a64 is is_a64(), else el0_a64 is ignored.
9517 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9519 if (cur_el
< new_el
) {
9520 /* Entry vector offset depends on whether the implemented EL
9521 * immediately lower than the target level is using AArch32 or AArch64
9528 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9531 hcr
= arm_hcr_el2_eff(env
);
9532 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
9533 is_aa64
= (hcr
& HCR_RW
) != 0;
9538 is_aa64
= is_a64(env
);
9541 g_assert_not_reached();
9549 } else if (pstate_read(env
) & PSTATE_SP
) {
9553 switch (cs
->exception_index
) {
9554 case EXCP_PREFETCH_ABORT
:
9555 case EXCP_DATA_ABORT
:
9556 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
9557 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
9558 env
->cp15
.far_el
[new_el
]);
9566 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
9568 * QEMU internal FP/SIMD syndromes from AArch32 include the
9569 * TA and coproc fields which are only exposed if the exception
9570 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9571 * AArch64 format syndrome.
9573 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
9575 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9586 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9590 old_mode
= pstate_read(env
);
9591 aarch64_save_sp(env
, arm_current_el(env
));
9592 env
->elr_el
[new_el
] = env
->pc
;
9594 old_mode
= cpsr_read(env
);
9595 env
->elr_el
[new_el
] = env
->regs
[15];
9597 aarch64_sync_32_to_64(env
);
9599 env
->condexec_bits
= 0;
9601 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
9603 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
9604 env
->elr_el
[new_el
]);
9606 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9607 /* The value of PSTATE.PAN is normally preserved, except when ... */
9608 new_mode
|= old_mode
& PSTATE_PAN
;
9611 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9612 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
9613 != (HCR_E2H
| HCR_TGE
)) {
9618 /* ... the target is EL1 ... */
9619 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9620 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
9621 new_mode
|= PSTATE_PAN
;
9627 pstate_write(env
, PSTATE_DAIF
| new_mode
);
9629 aarch64_restore_sp(env
, new_el
);
9630 helper_rebuild_hflags_a64(env
, new_el
);
9634 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
9635 new_el
, env
->pc
, pstate_read(env
));
9639 * Do semihosting call and set the appropriate return value. All the
9640 * permission and validity checks have been done at translate time.
9642 * We only see semihosting exceptions in TCG only as they are not
9643 * trapped to the hypervisor in KVM.
9646 static void handle_semihosting(CPUState
*cs
)
9648 ARMCPU
*cpu
= ARM_CPU(cs
);
9649 CPUARMState
*env
= &cpu
->env
;
9652 qemu_log_mask(CPU_LOG_INT
,
9653 "...handling as semihosting call 0x%" PRIx64
"\n",
9655 env
->xregs
[0] = do_arm_semihosting(env
);
9658 qemu_log_mask(CPU_LOG_INT
,
9659 "...handling as semihosting call 0x%x\n",
9661 env
->regs
[0] = do_arm_semihosting(env
);
9662 env
->regs
[15] += env
->thumb
? 2 : 4;
9667 /* Handle a CPU exception for A and R profile CPUs.
9668 * Do any appropriate logging, handle PSCI calls, and then hand off
9669 * to the AArch64-entry or AArch32-entry function depending on the
9670 * target exception level's register width.
9672 void arm_cpu_do_interrupt(CPUState
*cs
)
9674 ARMCPU
*cpu
= ARM_CPU(cs
);
9675 CPUARMState
*env
= &cpu
->env
;
9676 unsigned int new_el
= env
->exception
.target_el
;
9678 assert(!arm_feature(env
, ARM_FEATURE_M
));
9680 arm_log_exception(cs
->exception_index
);
9681 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
9683 if (qemu_loglevel_mask(CPU_LOG_INT
)
9684 && !excp_is_internal(cs
->exception_index
)) {
9685 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
9686 syn_get_ec(env
->exception
.syndrome
),
9687 env
->exception
.syndrome
);
9690 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
9691 arm_handle_psci_call(cpu
);
9692 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
9697 * Semihosting semantics depend on the register width of the code
9698 * that caused the exception, not the target exception level, so
9699 * must be handled here.
9702 if (cs
->exception_index
== EXCP_SEMIHOST
) {
9703 handle_semihosting(cs
);
9708 /* Hooks may change global state so BQL should be held, also the
9709 * BQL needs to be held for any modification of
9710 * cs->interrupt_request.
9712 g_assert(qemu_mutex_iothread_locked());
9714 arm_call_pre_el_change_hook(cpu
);
9716 assert(!excp_is_internal(cs
->exception_index
));
9717 if (arm_el_is_aa64(env
, new_el
)) {
9718 arm_cpu_do_interrupt_aarch64(cs
);
9720 arm_cpu_do_interrupt_aarch32(cs
);
9723 arm_call_el_change_hook(cpu
);
9725 if (!kvm_enabled()) {
9726 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
9729 #endif /* !CONFIG_USER_ONLY */
9731 /* Return the exception level which controls this address translation regime */
9732 static uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9735 case ARMMMUIdx_E20_0
:
9736 case ARMMMUIdx_E20_2
:
9737 case ARMMMUIdx_E20_2_PAN
:
9738 case ARMMMUIdx_Stage2
:
9743 case ARMMMUIdx_SE10_0
:
9744 return arm_el_is_aa64(env
, 3) ? 1 : 3;
9745 case ARMMMUIdx_SE10_1
:
9746 case ARMMMUIdx_SE10_1_PAN
:
9747 case ARMMMUIdx_Stage1_E0
:
9748 case ARMMMUIdx_Stage1_E1
:
9749 case ARMMMUIdx_Stage1_E1_PAN
:
9750 case ARMMMUIdx_E10_0
:
9751 case ARMMMUIdx_E10_1
:
9752 case ARMMMUIdx_E10_1_PAN
:
9753 case ARMMMUIdx_MPrivNegPri
:
9754 case ARMMMUIdx_MUserNegPri
:
9755 case ARMMMUIdx_MPriv
:
9756 case ARMMMUIdx_MUser
:
9757 case ARMMMUIdx_MSPrivNegPri
:
9758 case ARMMMUIdx_MSUserNegPri
:
9759 case ARMMMUIdx_MSPriv
:
9760 case ARMMMUIdx_MSUser
:
9763 g_assert_not_reached();
9767 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
9769 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
9771 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
9772 el
= (mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1);
9774 return env
->cp15
.sctlr_el
[el
];
9777 /* Return the SCTLR value which controls this address translation regime */
9778 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9780 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
9783 #ifndef CONFIG_USER_ONLY
9785 /* Return true if the specified stage of address translation is disabled */
9786 static inline bool regime_translation_disabled(CPUARMState
*env
,
9789 if (arm_feature(env
, ARM_FEATURE_M
)) {
9790 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
9791 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
9792 case R_V7M_MPU_CTRL_ENABLE_MASK
:
9793 /* Enabled, but not for HardFault and NMI */
9794 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
9795 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
9796 /* Enabled for all cases */
9800 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9801 * we warned about that in armv7m_nvic.c when the guest set it.
9807 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9808 /* HCR.DC means HCR.VM behaves as 1 */
9809 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
9812 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
9813 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
9814 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
9819 if ((env
->cp15
.hcr_el2
& HCR_DC
) && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
9820 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
9824 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
9827 static inline bool regime_translation_big_endian(CPUARMState
*env
,
9830 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
9833 /* Return the TTBR associated with this translation regime */
9834 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9837 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9838 return env
->cp15
.vttbr_el2
;
9841 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
9843 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
9847 #endif /* !CONFIG_USER_ONLY */
9849 /* Return the TCR controlling this translation regime */
9850 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9852 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9853 return &env
->cp15
.vtcr_el2
;
9855 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
9858 /* Convert a possible stage1+2 MMU index into the appropriate
9861 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
9864 case ARMMMUIdx_E10_0
:
9865 return ARMMMUIdx_Stage1_E0
;
9866 case ARMMMUIdx_E10_1
:
9867 return ARMMMUIdx_Stage1_E1
;
9868 case ARMMMUIdx_E10_1_PAN
:
9869 return ARMMMUIdx_Stage1_E1_PAN
;
9875 /* Return true if the translation regime is using LPAE format page tables */
9876 static inline bool regime_using_lpae_format(CPUARMState
*env
,
9879 int el
= regime_el(env
, mmu_idx
);
9880 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
9883 if (arm_feature(env
, ARM_FEATURE_LPAE
)
9884 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
9890 /* Returns true if the stage 1 translation regime is using LPAE format page
9891 * tables. Used when raising alignment exceptions, whose FSR changes depending
9892 * on whether the long or short descriptor format is in use. */
9893 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9895 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
9897 return regime_using_lpae_format(env
, mmu_idx
);
9900 #ifndef CONFIG_USER_ONLY
9901 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9904 case ARMMMUIdx_SE10_0
:
9905 case ARMMMUIdx_E20_0
:
9906 case ARMMMUIdx_Stage1_E0
:
9907 case ARMMMUIdx_MUser
:
9908 case ARMMMUIdx_MSUser
:
9909 case ARMMMUIdx_MUserNegPri
:
9910 case ARMMMUIdx_MSUserNegPri
:
9914 case ARMMMUIdx_E10_0
:
9915 case ARMMMUIdx_E10_1
:
9916 case ARMMMUIdx_E10_1_PAN
:
9917 g_assert_not_reached();
9921 /* Translate section/page access permissions to page
9922 * R/W protection flags
9925 * @mmu_idx: MMU index indicating required translation regime
9926 * @ap: The 3-bit access permissions (AP[2:0])
9927 * @domain_prot: The 2-bit domain access permissions
9929 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9930 int ap
, int domain_prot
)
9932 bool is_user
= regime_is_user(env
, mmu_idx
);
9934 if (domain_prot
== 3) {
9935 return PAGE_READ
| PAGE_WRITE
;
9940 if (arm_feature(env
, ARM_FEATURE_V7
)) {
9943 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
9945 return is_user
? 0 : PAGE_READ
;
9952 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9957 return PAGE_READ
| PAGE_WRITE
;
9960 return PAGE_READ
| PAGE_WRITE
;
9961 case 4: /* Reserved. */
9964 return is_user
? 0 : PAGE_READ
;
9968 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
9973 g_assert_not_reached();
9977 /* Translate section/page access permissions to page
9978 * R/W protection flags.
9980 * @ap: The 2-bit simple AP (AP[2:1])
9981 * @is_user: TRUE if accessing from PL0
9983 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
9987 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9989 return PAGE_READ
| PAGE_WRITE
;
9991 return is_user
? 0 : PAGE_READ
;
9995 g_assert_not_reached();
10000 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
10002 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
10005 /* Translate S2 section/page access permissions to protection flags
10007 * @env: CPUARMState
10008 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10009 * @xn: XN (execute-never) bits
10010 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
10012 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
10020 prot
|= PAGE_WRITE
;
10023 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
10041 g_assert_not_reached();
10044 if (!extract32(xn
, 1, 1)) {
10045 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
10053 /* Translate section/page access permissions to protection flags
10055 * @env: CPUARMState
10056 * @mmu_idx: MMU index indicating required translation regime
10057 * @is_aa64: TRUE if AArch64
10058 * @ap: The 2-bit simple AP (AP[2:1])
10059 * @ns: NS (non-secure) bit
10060 * @xn: XN (execute-never) bit
10061 * @pxn: PXN (privileged execute-never) bit
10063 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
10064 int ap
, int ns
, int xn
, int pxn
)
10066 bool is_user
= regime_is_user(env
, mmu_idx
);
10067 int prot_rw
, user_rw
;
10071 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
10073 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
10077 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
10078 /* PAN forbids data accesses but doesn't affect insn fetch */
10081 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
10085 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
10089 /* TODO have_wxn should be replaced with
10090 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10091 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10092 * compatible processors have EL2, which is required for [U]WXN.
10094 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
10097 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
10101 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
10102 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
10104 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10105 switch (regime_el(env
, mmu_idx
)) {
10109 xn
= xn
|| !(user_rw
& PAGE_READ
);
10113 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
10115 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
10116 (uwxn
&& (user_rw
& PAGE_WRITE
));
10126 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
10129 return prot_rw
| PAGE_EXEC
;
10132 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10133 uint32_t *table
, uint32_t address
)
10135 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10136 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10138 if (address
& tcr
->mask
) {
10139 if (tcr
->raw_tcr
& TTBCR_PD1
) {
10140 /* Translation table walk disabled for TTBR1 */
10143 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
10145 if (tcr
->raw_tcr
& TTBCR_PD0
) {
10146 /* Translation table walk disabled for TTBR0 */
10149 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
10151 *table
|= (address
>> 18) & 0x3ffc;
10155 /* Translate a S1 pagetable walk through S2 if needed. */
10156 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10157 hwaddr addr
, MemTxAttrs txattrs
,
10158 ARMMMUFaultInfo
*fi
)
10160 if (arm_mmu_idx_is_stage1_of_2(mmu_idx
) &&
10161 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
10162 target_ulong s2size
;
10166 ARMCacheAttrs cacheattrs
= {};
10167 ARMCacheAttrs
*pcacheattrs
= NULL
;
10169 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
10171 * PTW means we must fault if this S1 walk touches S2 Device
10172 * memory; otherwise we don't care about the attributes and can
10173 * save the S2 translation the effort of computing them.
10175 pcacheattrs
= &cacheattrs
;
10178 ret
= get_phys_addr_lpae(env
, addr
, MMU_DATA_LOAD
, ARMMMUIdx_Stage2
,
10180 &s2pa
, &txattrs
, &s2prot
, &s2size
, fi
,
10183 assert(fi
->type
!= ARMFault_None
);
10189 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
10190 /* Access was to Device memory: generate Permission fault */
10191 fi
->type
= ARMFault_Permission
;
10202 /* All loads done in the course of a page table walk go through here. */
10203 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10204 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10206 ARMCPU
*cpu
= ARM_CPU(cs
);
10207 CPUARMState
*env
= &cpu
->env
;
10208 MemTxAttrs attrs
= {};
10209 MemTxResult result
= MEMTX_OK
;
10213 attrs
.secure
= is_secure
;
10214 as
= arm_addressspace(cs
, attrs
);
10215 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
10219 if (regime_translation_big_endian(env
, mmu_idx
)) {
10220 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
10222 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
10224 if (result
== MEMTX_OK
) {
10227 fi
->type
= ARMFault_SyncExternalOnWalk
;
10228 fi
->ea
= arm_extabort_type(result
);
10232 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10233 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10235 ARMCPU
*cpu
= ARM_CPU(cs
);
10236 CPUARMState
*env
= &cpu
->env
;
10237 MemTxAttrs attrs
= {};
10238 MemTxResult result
= MEMTX_OK
;
10242 attrs
.secure
= is_secure
;
10243 as
= arm_addressspace(cs
, attrs
);
10244 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
10248 if (regime_translation_big_endian(env
, mmu_idx
)) {
10249 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
10251 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
10253 if (result
== MEMTX_OK
) {
10256 fi
->type
= ARMFault_SyncExternalOnWalk
;
10257 fi
->ea
= arm_extabort_type(result
);
10261 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
10262 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10263 hwaddr
*phys_ptr
, int *prot
,
10264 target_ulong
*page_size
,
10265 ARMMMUFaultInfo
*fi
)
10267 CPUState
*cs
= env_cpu(env
);
10278 /* Pagetable walk. */
10279 /* Lookup l1 descriptor. */
10280 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10281 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10282 fi
->type
= ARMFault_Translation
;
10285 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10287 if (fi
->type
!= ARMFault_None
) {
10291 domain
= (desc
>> 5) & 0x0f;
10292 if (regime_el(env
, mmu_idx
) == 1) {
10293 dacr
= env
->cp15
.dacr_ns
;
10295 dacr
= env
->cp15
.dacr_s
;
10297 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10299 /* Section translation fault. */
10300 fi
->type
= ARMFault_Translation
;
10306 if (domain_prot
== 0 || domain_prot
== 2) {
10307 fi
->type
= ARMFault_Domain
;
10312 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10313 ap
= (desc
>> 10) & 3;
10314 *page_size
= 1024 * 1024;
10316 /* Lookup l2 entry. */
10318 /* Coarse pagetable. */
10319 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10321 /* Fine pagetable. */
10322 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
10324 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10326 if (fi
->type
!= ARMFault_None
) {
10329 switch (desc
& 3) {
10330 case 0: /* Page translation fault. */
10331 fi
->type
= ARMFault_Translation
;
10333 case 1: /* 64k page. */
10334 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10335 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
10336 *page_size
= 0x10000;
10338 case 2: /* 4k page. */
10339 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10340 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
10341 *page_size
= 0x1000;
10343 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10345 /* ARMv6/XScale extended small page format */
10346 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
10347 || arm_feature(env
, ARM_FEATURE_V6
)) {
10348 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10349 *page_size
= 0x1000;
10351 /* UNPREDICTABLE in ARMv5; we choose to take a
10352 * page translation fault.
10354 fi
->type
= ARMFault_Translation
;
10358 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
10359 *page_size
= 0x400;
10361 ap
= (desc
>> 4) & 3;
10364 /* Never happens, but compiler isn't smart enough to tell. */
10368 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10369 *prot
|= *prot
? PAGE_EXEC
: 0;
10370 if (!(*prot
& (1 << access_type
))) {
10371 /* Access permission fault. */
10372 fi
->type
= ARMFault_Permission
;
10375 *phys_ptr
= phys_addr
;
10378 fi
->domain
= domain
;
10383 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
10384 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10385 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10386 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
10388 CPUState
*cs
= env_cpu(env
);
10402 /* Pagetable walk. */
10403 /* Lookup l1 descriptor. */
10404 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10405 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10406 fi
->type
= ARMFault_Translation
;
10409 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10411 if (fi
->type
!= ARMFault_None
) {
10415 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
10416 /* Section translation fault, or attempt to use the encoding
10417 * which is Reserved on implementations without PXN.
10419 fi
->type
= ARMFault_Translation
;
10422 if ((type
== 1) || !(desc
& (1 << 18))) {
10423 /* Page or Section. */
10424 domain
= (desc
>> 5) & 0x0f;
10426 if (regime_el(env
, mmu_idx
) == 1) {
10427 dacr
= env
->cp15
.dacr_ns
;
10429 dacr
= env
->cp15
.dacr_s
;
10434 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10435 if (domain_prot
== 0 || domain_prot
== 2) {
10436 /* Section or Page domain fault */
10437 fi
->type
= ARMFault_Domain
;
10441 if (desc
& (1 << 18)) {
10442 /* Supersection. */
10443 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
10444 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
10445 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
10446 *page_size
= 0x1000000;
10449 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10450 *page_size
= 0x100000;
10452 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
10453 xn
= desc
& (1 << 4);
10455 ns
= extract32(desc
, 19, 1);
10457 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
10458 pxn
= (desc
>> 2) & 1;
10460 ns
= extract32(desc
, 3, 1);
10461 /* Lookup l2 entry. */
10462 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10463 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10465 if (fi
->type
!= ARMFault_None
) {
10468 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
10469 switch (desc
& 3) {
10470 case 0: /* Page translation fault. */
10471 fi
->type
= ARMFault_Translation
;
10473 case 1: /* 64k page. */
10474 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10475 xn
= desc
& (1 << 15);
10476 *page_size
= 0x10000;
10478 case 2: case 3: /* 4k page. */
10479 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10481 *page_size
= 0x1000;
10484 /* Never happens, but compiler isn't smart enough to tell. */
10488 if (domain_prot
== 3) {
10489 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10491 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
10494 if (xn
&& access_type
== MMU_INST_FETCH
) {
10495 fi
->type
= ARMFault_Permission
;
10499 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
10500 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
10501 /* The simplified model uses AP[0] as an access control bit. */
10502 if ((ap
& 1) == 0) {
10503 /* Access flag fault. */
10504 fi
->type
= ARMFault_AccessFlag
;
10507 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
10509 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10511 if (*prot
&& !xn
) {
10512 *prot
|= PAGE_EXEC
;
10514 if (!(*prot
& (1 << access_type
))) {
10515 /* Access permission fault. */
10516 fi
->type
= ARMFault_Permission
;
10521 /* The NS bit will (as required by the architecture) have no effect if
10522 * the CPU doesn't support TZ or this is a non-secure translation
10523 * regime, because the attribute will already be non-secure.
10525 attrs
->secure
= false;
10527 *phys_ptr
= phys_addr
;
10530 fi
->domain
= domain
;
10536 * check_s2_mmu_setup
10538 * @is_aa64: True if the translation regime is in AArch64 state
10539 * @startlevel: Suggested starting level
10540 * @inputsize: Bitsize of IPAs
10541 * @stride: Page-table stride (See the ARM ARM)
10543 * Returns true if the suggested S2 translation parameters are OK and
10546 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
10547 int inputsize
, int stride
)
10549 const int grainsize
= stride
+ 3;
10550 int startsizecheck
;
10552 /* Negative levels are never allowed. */
10557 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
10558 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
10563 CPUARMState
*env
= &cpu
->env
;
10564 unsigned int pamax
= arm_pamax(cpu
);
10567 case 13: /* 64KB Pages. */
10568 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
10572 case 11: /* 16KB Pages. */
10573 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
10577 case 9: /* 4KB Pages. */
10578 if (level
== 0 && pamax
<= 42) {
10583 g_assert_not_reached();
10586 /* Inputsize checks. */
10587 if (inputsize
> pamax
&&
10588 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
10589 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10593 /* AArch32 only supports 4KB pages. Assert on that. */
10594 assert(stride
== 9);
10603 /* Translate from the 4-bit stage 2 representation of
10604 * memory attributes (without cache-allocation hints) to
10605 * the 8-bit representation of the stage 1 MAIR registers
10606 * (which includes allocation hints).
10608 * ref: shared/translation/attrs/S2AttrDecode()
10609 * .../S2ConvertAttrsHints()
10611 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
10613 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
10614 uint8_t loattr
= extract32(s2attrs
, 0, 2);
10615 uint8_t hihint
= 0, lohint
= 0;
10617 if (hiattr
!= 0) { /* normal memory */
10618 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
10619 hiattr
= loattr
= 1; /* non-cacheable */
10621 if (hiattr
!= 1) { /* Write-through or write-back */
10622 hihint
= 3; /* RW allocate */
10624 if (loattr
!= 1) { /* Write-through or write-back */
10625 lohint
= 3; /* RW allocate */
10630 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
10632 #endif /* !CONFIG_USER_ONLY */
10634 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10636 if (regime_has_2_ranges(mmu_idx
)) {
10637 return extract64(tcr
, 37, 2);
10638 } else if (mmu_idx
== ARMMMUIdx_Stage2
) {
10639 return 0; /* VTCR_EL2 */
10641 /* Replicate the single TBI bit so we always have 2 bits. */
10642 return extract32(tcr
, 20, 1) * 3;
10646 static int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10648 if (regime_has_2_ranges(mmu_idx
)) {
10649 return extract64(tcr
, 51, 2);
10650 } else if (mmu_idx
== ARMMMUIdx_Stage2
) {
10651 return 0; /* VTCR_EL2 */
10653 /* Replicate the single TBID bit so we always have 2 bits. */
10654 return extract32(tcr
, 29, 1) * 3;
10658 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10659 ARMMMUIdx mmu_idx
, bool data
)
10661 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10662 bool epd
, hpd
, using16k
, using64k
;
10663 int select
, tsz
, tbi
;
10665 if (!regime_has_2_ranges(mmu_idx
)) {
10667 tsz
= extract32(tcr
, 0, 6);
10668 using64k
= extract32(tcr
, 14, 1);
10669 using16k
= extract32(tcr
, 15, 1);
10670 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10674 hpd
= extract32(tcr
, 24, 1);
10679 * Bit 55 is always between the two regions, and is canonical for
10680 * determining if address tagging is enabled.
10682 select
= extract64(va
, 55, 1);
10684 tsz
= extract32(tcr
, 0, 6);
10685 epd
= extract32(tcr
, 7, 1);
10686 using64k
= extract32(tcr
, 14, 1);
10687 using16k
= extract32(tcr
, 15, 1);
10688 hpd
= extract64(tcr
, 41, 1);
10690 int tg
= extract32(tcr
, 30, 2);
10691 using16k
= tg
== 1;
10692 using64k
= tg
== 3;
10693 tsz
= extract32(tcr
, 16, 6);
10694 epd
= extract32(tcr
, 23, 1);
10695 hpd
= extract64(tcr
, 42, 1);
10698 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
10699 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
10701 /* Present TBI as a composite with TBID. */
10702 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10704 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10706 tbi
= (tbi
>> select
) & 1;
10708 return (ARMVAParameters
) {
10714 .using16k
= using16k
,
10715 .using64k
= using64k
,
10719 #ifndef CONFIG_USER_ONLY
10720 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
10723 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10724 uint32_t el
= regime_el(env
, mmu_idx
);
10728 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10730 bool sext
= extract32(tcr
, 4, 1);
10731 bool sign
= extract32(tcr
, 3, 1);
10734 * If the sign-extend bit is not the same as t0sz[3], the result
10735 * is unpredictable. Flag this as a guest error.
10737 if (sign
!= sext
) {
10738 qemu_log_mask(LOG_GUEST_ERROR
,
10739 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10741 tsz
= sextract32(tcr
, 0, 4) + 8;
10745 } else if (el
== 2) {
10747 tsz
= extract32(tcr
, 0, 3);
10749 hpd
= extract64(tcr
, 24, 1);
10752 int t0sz
= extract32(tcr
, 0, 3);
10753 int t1sz
= extract32(tcr
, 16, 3);
10756 select
= va
> (0xffffffffu
>> t0sz
);
10758 /* Note that we will detect errors later. */
10759 select
= va
>= ~(0xffffffffu
>> t1sz
);
10763 epd
= extract32(tcr
, 7, 1);
10764 hpd
= extract64(tcr
, 41, 1);
10767 epd
= extract32(tcr
, 23, 1);
10768 hpd
= extract64(tcr
, 42, 1);
10770 /* For aarch32, hpd0 is not enabled without t2e as well. */
10771 hpd
&= extract32(tcr
, 6, 1);
10774 return (ARMVAParameters
) {
10783 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
10785 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10786 * prot and page_size may not be filled in, and the populated fsr value provides
10787 * information on why the translation aborted, in the format of a long-format
10788 * DFSR/IFSR fault register, with the following caveats:
10789 * * the WnR bit is never set (the caller must do this).
10791 * @env: CPUARMState
10792 * @address: virtual address to get physical address for
10793 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
10794 * @mmu_idx: MMU index indicating required translation regime
10795 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
10796 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
10797 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
10798 * @phys_ptr: set to the physical address corresponding to the virtual address
10799 * @attrs: set to the memory transaction attributes to use
10800 * @prot: set to the permissions for the page containing phys_ptr
10801 * @page_size_ptr: set to the size of the page containing phys_ptr
10802 * @fi: set to fault info if the translation fails
10803 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10805 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
10806 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10808 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
10809 target_ulong
*page_size_ptr
,
10810 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10812 ARMCPU
*cpu
= env_archcpu(env
);
10813 CPUState
*cs
= CPU(cpu
);
10814 /* Read an LPAE long-descriptor translation table. */
10815 ARMFaultType fault_type
= ARMFault_Translation
;
10817 ARMVAParameters param
;
10819 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
10820 uint32_t tableattrs
;
10821 target_ulong page_size
;
10824 int addrsize
, inputsize
;
10825 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10826 int ap
, ns
, xn
, pxn
;
10827 uint32_t el
= regime_el(env
, mmu_idx
);
10828 uint64_t descaddrmask
;
10829 bool aarch64
= arm_el_is_aa64(env
, el
);
10830 bool guarded
= false;
10832 /* TODO: This code does not support shareability levels. */
10834 param
= aa64_va_parameters(env
, address
, mmu_idx
,
10835 access_type
!= MMU_INST_FETCH
);
10837 addrsize
= 64 - 8 * param
.tbi
;
10838 inputsize
= 64 - param
.tsz
;
10840 param
= aa32_va_parameters(env
, address
, mmu_idx
);
10842 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
10843 inputsize
= addrsize
- param
.tsz
;
10847 * We determined the region when collecting the parameters, but we
10848 * have not yet validated that the address is valid for the region.
10849 * Extract the top bits and verify that they all match select.
10851 * For aa32, if inputsize == addrsize, then we have selected the
10852 * region by exclusion in aa32_va_parameters and there is no more
10853 * validation to do here.
10855 if (inputsize
< addrsize
) {
10856 target_ulong top_bits
= sextract64(address
, inputsize
,
10857 addrsize
- inputsize
);
10858 if (-top_bits
!= param
.select
) {
10859 /* The gap between the two regions is a Translation fault */
10860 fault_type
= ARMFault_Translation
;
10865 if (param
.using64k
) {
10867 } else if (param
.using16k
) {
10873 /* Note that QEMU ignores shareability and cacheability attributes,
10874 * so we don't need to do anything with the SH, ORGN, IRGN fields
10875 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
10876 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
10877 * implement any ASID-like capability so we can ignore it (instead
10878 * we will always flush the TLB any time the ASID is changed).
10880 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
10882 /* Here we should have set up all the parameters for the translation:
10883 * inputsize, ttbr, epd, stride, tbi
10887 /* Translation table walk disabled => Translation fault on TLB miss
10888 * Note: This is always 0 on 64-bit EL2 and EL3.
10893 if (mmu_idx
!= ARMMMUIdx_Stage2
) {
10894 /* The starting level depends on the virtual address size (which can
10895 * be up to 48 bits) and the translation granule size. It indicates
10896 * the number of strides (stride bits at a time) needed to
10897 * consume the bits of the input address. In the pseudocode this is:
10898 * level = 4 - RoundUp((inputsize - grainsize) / stride)
10899 * where their 'inputsize' is our 'inputsize', 'grainsize' is
10900 * our 'stride + 3' and 'stride' is our 'stride'.
10901 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
10902 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
10903 * = 4 - (inputsize - 4) / stride;
10905 level
= 4 - (inputsize
- 4) / stride
;
10907 /* For stage 2 translations the starting level is specified by the
10908 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
10910 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
10911 uint32_t startlevel
;
10914 if (!aarch64
|| stride
== 9) {
10915 /* AArch32 or 4KB pages */
10916 startlevel
= 2 - sl0
;
10918 /* 16KB or 64KB pages */
10919 startlevel
= 3 - sl0
;
10922 /* Check that the starting level is valid. */
10923 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
10924 inputsize
, stride
);
10926 fault_type
= ARMFault_Translation
;
10929 level
= startlevel
;
10932 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
10933 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
10935 /* Now we can extract the actual base address from the TTBR */
10936 descaddr
= extract64(ttbr
, 0, 48);
10938 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
10939 * and also to mask out CnP (bit 0) which could validly be non-zero.
10941 descaddr
&= ~indexmask
;
10943 /* The address field in the descriptor goes up to bit 39 for ARMv7
10944 * but up to bit 47 for ARMv8, but we use the descaddrmask
10945 * up to bit 39 for AArch32, because we don't need other bits in that case
10946 * to construct next descriptor address (anyway they should be all zeroes).
10948 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
10949 ~indexmask_grainsize
;
10951 /* Secure accesses start with the page table in secure memory and
10952 * can be downgraded to non-secure at any step. Non-secure accesses
10953 * remain non-secure. We implement this by just ORing in the NSTable/NS
10954 * bits at each step.
10956 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
10958 uint64_t descriptor
;
10961 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
10963 nstable
= extract32(tableattrs
, 4, 1);
10964 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
10965 if (fi
->type
!= ARMFault_None
) {
10969 if (!(descriptor
& 1) ||
10970 (!(descriptor
& 2) && (level
== 3))) {
10971 /* Invalid, or the Reserved level 3 encoding */
10974 descaddr
= descriptor
& descaddrmask
;
10976 if ((descriptor
& 2) && (level
< 3)) {
10977 /* Table entry. The top five bits are attributes which may
10978 * propagate down through lower levels of the table (and
10979 * which are all arranged so that 0 means "no effect", so
10980 * we can gather them up by ORing in the bits at each level).
10982 tableattrs
|= extract64(descriptor
, 59, 5);
10984 indexmask
= indexmask_grainsize
;
10987 /* Block entry at level 1 or 2, or page entry at level 3.
10988 * These are basically the same thing, although the number
10989 * of bits we pull in from the vaddr varies.
10991 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
10992 descaddr
|= (address
& (page_size
- 1));
10993 /* Extract attributes from the descriptor */
10994 attrs
= extract64(descriptor
, 2, 10)
10995 | (extract64(descriptor
, 52, 12) << 10);
10997 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10998 /* Stage 2 table descriptors do not include any attribute fields */
11001 /* Merge in attributes from table descriptors */
11002 attrs
|= nstable
<< 3; /* NS */
11003 guarded
= extract64(descriptor
, 50, 1); /* GP */
11005 /* HPD disables all the table attributes except NSTable. */
11008 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
11009 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11010 * means "force PL1 access only", which means forcing AP[1] to 0.
11012 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
11013 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
11016 /* Here descaddr is the final physical address, and attributes
11017 * are all in attrs.
11019 fault_type
= ARMFault_AccessFlag
;
11020 if ((attrs
& (1 << 8)) == 0) {
11025 ap
= extract32(attrs
, 4, 2);
11027 if (mmu_idx
== ARMMMUIdx_Stage2
) {
11029 xn
= extract32(attrs
, 11, 2);
11030 *prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
11032 ns
= extract32(attrs
, 3, 1);
11033 xn
= extract32(attrs
, 12, 1);
11034 pxn
= extract32(attrs
, 11, 1);
11035 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
11038 fault_type
= ARMFault_Permission
;
11039 if (!(*prot
& (1 << access_type
))) {
11044 /* The NS bit will (as required by the architecture) have no effect if
11045 * the CPU doesn't support TZ or this is a non-secure translation
11046 * regime, because the attribute will already be non-secure.
11048 txattrs
->secure
= false;
11050 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11051 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
11052 txattrs
->target_tlb_bit0
= true;
11055 if (cacheattrs
!= NULL
) {
11056 if (mmu_idx
== ARMMMUIdx_Stage2
) {
11057 cacheattrs
->attrs
= convert_stage2_attrs(env
,
11058 extract32(attrs
, 0, 4));
11060 /* Index into MAIR registers for cache attributes */
11061 uint8_t attrindx
= extract32(attrs
, 0, 3);
11062 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
11063 assert(attrindx
<= 7);
11064 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
11066 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
11069 *phys_ptr
= descaddr
;
11070 *page_size_ptr
= page_size
;
11074 fi
->type
= fault_type
;
11076 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11077 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
);
11081 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
11083 int32_t address
, int *prot
)
11085 if (!arm_feature(env
, ARM_FEATURE_M
)) {
11086 *prot
= PAGE_READ
| PAGE_WRITE
;
11088 case 0xF0000000 ... 0xFFFFFFFF:
11089 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
11090 /* hivecs execing is ok */
11091 *prot
|= PAGE_EXEC
;
11094 case 0x00000000 ... 0x7FFFFFFF:
11095 *prot
|= PAGE_EXEC
;
11099 /* Default system address map for M profile cores.
11100 * The architecture specifies which regions are execute-never;
11101 * at the MPU level no other checks are defined.
11104 case 0x00000000 ... 0x1fffffff: /* ROM */
11105 case 0x20000000 ... 0x3fffffff: /* SRAM */
11106 case 0x60000000 ... 0x7fffffff: /* RAM */
11107 case 0x80000000 ... 0x9fffffff: /* RAM */
11108 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11110 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11111 case 0xa0000000 ... 0xbfffffff: /* Device */
11112 case 0xc0000000 ... 0xdfffffff: /* Device */
11113 case 0xe0000000 ... 0xffffffff: /* System */
11114 *prot
= PAGE_READ
| PAGE_WRITE
;
11117 g_assert_not_reached();
11122 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
11123 ARMMMUIdx mmu_idx
, bool is_user
)
11125 /* Return true if we should use the default memory map as a
11126 * "background" region if there are no hits against any MPU regions.
11128 CPUARMState
*env
= &cpu
->env
;
11134 if (arm_feature(env
, ARM_FEATURE_M
)) {
11135 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
11136 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
11138 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
11142 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
11144 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11145 return arm_feature(env
, ARM_FEATURE_M
) &&
11146 extract32(address
, 20, 12) == 0xe00;
11149 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
11151 /* True if address is in the M profile system region
11152 * 0xe0000000 - 0xffffffff
11154 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
11157 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
11158 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11159 hwaddr
*phys_ptr
, int *prot
,
11160 target_ulong
*page_size
,
11161 ARMMMUFaultInfo
*fi
)
11163 ARMCPU
*cpu
= env_archcpu(env
);
11165 bool is_user
= regime_is_user(env
, mmu_idx
);
11167 *phys_ptr
= address
;
11168 *page_size
= TARGET_PAGE_SIZE
;
11171 if (regime_translation_disabled(env
, mmu_idx
) ||
11172 m_is_ppb_region(env
, address
)) {
11173 /* MPU disabled or M profile PPB access: use default memory map.
11174 * The other case which uses the default memory map in the
11175 * v7M ARM ARM pseudocode is exception vector reads from the vector
11176 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11177 * which always does a direct read using address_space_ldl(), rather
11178 * than going via this function, so we don't need to check that here.
11180 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11181 } else { /* MPU enabled */
11182 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11183 /* region search */
11184 uint32_t base
= env
->pmsav7
.drbar
[n
];
11185 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
11187 bool srdis
= false;
11189 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
11194 qemu_log_mask(LOG_GUEST_ERROR
,
11195 "DRSR[%d]: Rsize field cannot be 0\n", n
);
11199 rmask
= (1ull << rsize
) - 1;
11201 if (base
& rmask
) {
11202 qemu_log_mask(LOG_GUEST_ERROR
,
11203 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
11204 "to DRSR region size, mask = 0x%" PRIx32
"\n",
11209 if (address
< base
|| address
> base
+ rmask
) {
11211 * Address not in this region. We must check whether the
11212 * region covers addresses in the same page as our address.
11213 * In that case we must not report a size that covers the
11214 * whole page for a subsequent hit against a different MPU
11215 * region or the background region, because it would result in
11216 * incorrect TLB hits for subsequent accesses to addresses that
11217 * are in this MPU region.
11219 if (ranges_overlap(base
, rmask
,
11220 address
& TARGET_PAGE_MASK
,
11221 TARGET_PAGE_SIZE
)) {
11227 /* Region matched */
11229 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
11231 uint32_t srdis_mask
;
11233 rsize
-= 3; /* sub region size (power of 2) */
11234 snd
= ((address
- base
) >> rsize
) & 0x7;
11235 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
11237 srdis_mask
= srdis
? 0x3 : 0x0;
11238 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
11239 /* This will check in groups of 2, 4 and then 8, whether
11240 * the subregion bits are consistent. rsize is incremented
11241 * back up to give the region size, considering consistent
11242 * adjacent subregions as one region. Stop testing if rsize
11243 * is already big enough for an entire QEMU page.
11245 int snd_rounded
= snd
& ~(i
- 1);
11246 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
11247 snd_rounded
+ 8, i
);
11248 if (srdis_mask
^ srdis_multi
) {
11251 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
11258 if (rsize
< TARGET_PAGE_BITS
) {
11259 *page_size
= 1 << rsize
;
11264 if (n
== -1) { /* no hits */
11265 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11266 /* background fault */
11267 fi
->type
= ARMFault_Background
;
11270 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11271 } else { /* a MPU hit! */
11272 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
11273 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
11275 if (m_is_system_region(env
, address
)) {
11276 /* System space is always execute never */
11280 if (is_user
) { /* User mode AP bit decoding */
11285 break; /* no access */
11287 *prot
|= PAGE_WRITE
;
11291 *prot
|= PAGE_READ
| PAGE_EXEC
;
11294 /* for v7M, same as 6; for R profile a reserved value */
11295 if (arm_feature(env
, ARM_FEATURE_M
)) {
11296 *prot
|= PAGE_READ
| PAGE_EXEC
;
11301 qemu_log_mask(LOG_GUEST_ERROR
,
11302 "DRACR[%d]: Bad value for AP bits: 0x%"
11303 PRIx32
"\n", n
, ap
);
11305 } else { /* Priv. mode AP bits decoding */
11308 break; /* no access */
11312 *prot
|= PAGE_WRITE
;
11316 *prot
|= PAGE_READ
| PAGE_EXEC
;
11319 /* for v7M, same as 6; for R profile a reserved value */
11320 if (arm_feature(env
, ARM_FEATURE_M
)) {
11321 *prot
|= PAGE_READ
| PAGE_EXEC
;
11326 qemu_log_mask(LOG_GUEST_ERROR
,
11327 "DRACR[%d]: Bad value for AP bits: 0x%"
11328 PRIx32
"\n", n
, ap
);
11332 /* execute never */
11334 *prot
&= ~PAGE_EXEC
;
11339 fi
->type
= ARMFault_Permission
;
11341 return !(*prot
& (1 << access_type
));
11344 static bool v8m_is_sau_exempt(CPUARMState
*env
,
11345 uint32_t address
, MMUAccessType access_type
)
11347 /* The architecture specifies that certain address ranges are
11348 * exempt from v8M SAU/IDAU checks.
11351 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
11352 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
11353 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
11354 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
11355 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
11356 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
11359 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
11360 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11361 V8M_SAttributes
*sattrs
)
11363 /* Look up the security attributes for this address. Compare the
11364 * pseudocode SecurityCheck() function.
11365 * We assume the caller has zero-initialized *sattrs.
11367 ARMCPU
*cpu
= env_archcpu(env
);
11369 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
11370 int idau_region
= IREGION_NOTVALID
;
11371 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11372 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11375 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
11376 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
11378 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
11382 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
11383 /* 0xf0000000..0xffffffff is always S for insn fetches */
11387 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
11388 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
11392 if (idau_region
!= IREGION_NOTVALID
) {
11393 sattrs
->irvalid
= true;
11394 sattrs
->iregion
= idau_region
;
11397 switch (env
->sau
.ctrl
& 3) {
11398 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11400 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11403 default: /* SAU.ENABLE == 1 */
11404 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
11405 if (env
->sau
.rlar
[r
] & 1) {
11406 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
11407 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
11409 if (base
<= address
&& limit
>= address
) {
11410 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11411 sattrs
->subpage
= true;
11413 if (sattrs
->srvalid
) {
11414 /* If we hit in more than one region then we must report
11415 * as Secure, not NS-Callable, with no valid region
11418 sattrs
->ns
= false;
11419 sattrs
->nsc
= false;
11420 sattrs
->sregion
= 0;
11421 sattrs
->srvalid
= false;
11424 if (env
->sau
.rlar
[r
] & 2) {
11425 sattrs
->nsc
= true;
11429 sattrs
->srvalid
= true;
11430 sattrs
->sregion
= r
;
11434 * Address not in this region. We must check whether the
11435 * region covers addresses in the same page as our address.
11436 * In that case we must not report a size that covers the
11437 * whole page for a subsequent hit against a different MPU
11438 * region or the background region, because it would result
11439 * in incorrect TLB hits for subsequent accesses to
11440 * addresses that are in this MPU region.
11442 if (limit
>= base
&&
11443 ranges_overlap(base
, limit
- base
+ 1,
11445 TARGET_PAGE_SIZE
)) {
11446 sattrs
->subpage
= true;
11455 * The IDAU will override the SAU lookup results if it specifies
11456 * higher security than the SAU does.
11459 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
11460 sattrs
->ns
= false;
11461 sattrs
->nsc
= idau_nsc
;
11466 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
11467 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11468 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11469 int *prot
, bool *is_subpage
,
11470 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
11472 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11473 * that a full phys-to-virt translation does).
11474 * mregion is (if not NULL) set to the region number which matched,
11475 * or -1 if no region number is returned (MPU off, address did not
11476 * hit a region, address hit in multiple regions).
11477 * We set is_subpage to true if the region hit doesn't cover the
11478 * entire TARGET_PAGE the address is within.
11480 ARMCPU
*cpu
= env_archcpu(env
);
11481 bool is_user
= regime_is_user(env
, mmu_idx
);
11482 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11484 int matchregion
= -1;
11486 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11487 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11489 *is_subpage
= false;
11490 *phys_ptr
= address
;
11496 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11497 * was an exception vector read from the vector table (which is always
11498 * done using the default system address map), because those accesses
11499 * are done in arm_v7m_load_vector(), which always does a direct
11500 * read using address_space_ldl(), rather than going via this function.
11502 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
11504 } else if (m_is_ppb_region(env
, address
)) {
11507 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11511 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11512 /* region search */
11513 /* Note that the base address is bits [31:5] from the register
11514 * with bits [4:0] all zeroes, but the limit address is bits
11515 * [31:5] from the register with bits [4:0] all ones.
11517 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
11518 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
11520 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
11521 /* Region disabled */
11525 if (address
< base
|| address
> limit
) {
11527 * Address not in this region. We must check whether the
11528 * region covers addresses in the same page as our address.
11529 * In that case we must not report a size that covers the
11530 * whole page for a subsequent hit against a different MPU
11531 * region or the background region, because it would result in
11532 * incorrect TLB hits for subsequent accesses to addresses that
11533 * are in this MPU region.
11535 if (limit
>= base
&&
11536 ranges_overlap(base
, limit
- base
+ 1,
11538 TARGET_PAGE_SIZE
)) {
11539 *is_subpage
= true;
11544 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11545 *is_subpage
= true;
11548 if (matchregion
!= -1) {
11549 /* Multiple regions match -- always a failure (unlike
11550 * PMSAv7 where highest-numbered-region wins)
11552 fi
->type
= ARMFault_Permission
;
11563 /* background fault */
11564 fi
->type
= ARMFault_Background
;
11568 if (matchregion
== -1) {
11569 /* hit using the background region */
11570 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11572 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
11573 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
11575 if (m_is_system_region(env
, address
)) {
11576 /* System space is always execute never */
11580 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
11581 if (*prot
&& !xn
) {
11582 *prot
|= PAGE_EXEC
;
11584 /* We don't need to look the attribute up in the MAIR0/MAIR1
11585 * registers because that only tells us about cacheability.
11588 *mregion
= matchregion
;
11592 fi
->type
= ARMFault_Permission
;
11594 return !(*prot
& (1 << access_type
));
11598 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
11599 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11600 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11601 int *prot
, target_ulong
*page_size
,
11602 ARMMMUFaultInfo
*fi
)
11604 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11605 V8M_SAttributes sattrs
= {};
11607 bool mpu_is_subpage
;
11609 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11610 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
11611 if (access_type
== MMU_INST_FETCH
) {
11612 /* Instruction fetches always use the MMU bank and the
11613 * transaction attribute determined by the fetch address,
11614 * regardless of CPU state. This is painful for QEMU
11615 * to handle, because it would mean we need to encode
11616 * into the mmu_idx not just the (user, negpri) information
11617 * for the current security state but also that for the
11618 * other security state, which would balloon the number
11619 * of mmu_idx values needed alarmingly.
11620 * Fortunately we can avoid this because it's not actually
11621 * possible to arbitrarily execute code from memory with
11622 * the wrong security attribute: it will always generate
11623 * an exception of some kind or another, apart from the
11624 * special case of an NS CPU executing an SG instruction
11625 * in S&NSC memory. So we always just fail the translation
11626 * here and sort things out in the exception handler
11627 * (including possibly emulating an SG instruction).
11629 if (sattrs
.ns
!= !secure
) {
11631 fi
->type
= ARMFault_QEMU_NSCExec
;
11633 fi
->type
= ARMFault_QEMU_SFault
;
11635 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11636 *phys_ptr
= address
;
11641 /* For data accesses we always use the MMU bank indicated
11642 * by the current CPU state, but the security attributes
11643 * might downgrade a secure access to nonsecure.
11646 txattrs
->secure
= false;
11647 } else if (!secure
) {
11648 /* NS access to S memory must fault.
11649 * Architecturally we should first check whether the
11650 * MPU information for this address indicates that we
11651 * are doing an unaligned access to Device memory, which
11652 * should generate a UsageFault instead. QEMU does not
11653 * currently check for that kind of unaligned access though.
11654 * If we added it we would need to do so as a special case
11655 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11657 fi
->type
= ARMFault_QEMU_SFault
;
11658 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11659 *phys_ptr
= address
;
11666 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
11667 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
11668 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
11672 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
11673 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11674 hwaddr
*phys_ptr
, int *prot
,
11675 ARMMMUFaultInfo
*fi
)
11680 bool is_user
= regime_is_user(env
, mmu_idx
);
11682 if (regime_translation_disabled(env
, mmu_idx
)) {
11683 /* MPU disabled. */
11684 *phys_ptr
= address
;
11685 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11689 *phys_ptr
= address
;
11690 for (n
= 7; n
>= 0; n
--) {
11691 base
= env
->cp15
.c6_region
[n
];
11692 if ((base
& 1) == 0) {
11695 mask
= 1 << ((base
>> 1) & 0x1f);
11696 /* Keep this shift separate from the above to avoid an
11697 (undefined) << 32. */
11698 mask
= (mask
<< 1) - 1;
11699 if (((base
^ address
) & ~mask
) == 0) {
11704 fi
->type
= ARMFault_Background
;
11708 if (access_type
== MMU_INST_FETCH
) {
11709 mask
= env
->cp15
.pmsav5_insn_ap
;
11711 mask
= env
->cp15
.pmsav5_data_ap
;
11713 mask
= (mask
>> (n
* 4)) & 0xf;
11716 fi
->type
= ARMFault_Permission
;
11721 fi
->type
= ARMFault_Permission
;
11725 *prot
= PAGE_READ
| PAGE_WRITE
;
11730 *prot
|= PAGE_WRITE
;
11734 *prot
= PAGE_READ
| PAGE_WRITE
;
11738 fi
->type
= ARMFault_Permission
;
11748 /* Bad permission. */
11749 fi
->type
= ARMFault_Permission
;
11753 *prot
|= PAGE_EXEC
;
11757 /* Combine either inner or outer cacheability attributes for normal
11758 * memory, according to table D4-42 and pseudocode procedure
11759 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11761 * NB: only stage 1 includes allocation hints (RW bits), leading to
11764 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
11766 if (s1
== 4 || s2
== 4) {
11767 /* non-cacheable has precedence */
11769 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
11770 /* stage 1 write-through takes precedence */
11772 } else if (extract32(s2
, 2, 2) == 2) {
11773 /* stage 2 write-through takes precedence, but the allocation hint
11774 * is still taken from stage 1
11776 return (2 << 2) | extract32(s1
, 0, 2);
11777 } else { /* write-back */
11782 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11783 * and CombineS1S2Desc()
11785 * @s1: Attributes from stage 1 walk
11786 * @s2: Attributes from stage 2 walk
11788 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
11790 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
11791 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
11794 /* Combine shareability attributes (table D4-43) */
11795 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
11796 /* if either are outer-shareable, the result is outer-shareable */
11797 ret
.shareability
= 2;
11798 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
11799 /* if either are inner-shareable, the result is inner-shareable */
11800 ret
.shareability
= 3;
11802 /* both non-shareable */
11803 ret
.shareability
= 0;
11806 /* Combine memory type and cacheability attributes */
11807 if (s1hi
== 0 || s2hi
== 0) {
11808 /* Device has precedence over normal */
11809 if (s1lo
== 0 || s2lo
== 0) {
11810 /* nGnRnE has precedence over anything */
11812 } else if (s1lo
== 4 || s2lo
== 4) {
11813 /* non-Reordering has precedence over Reordering */
11814 ret
.attrs
= 4; /* nGnRE */
11815 } else if (s1lo
== 8 || s2lo
== 8) {
11816 /* non-Gathering has precedence over Gathering */
11817 ret
.attrs
= 8; /* nGRE */
11819 ret
.attrs
= 0xc; /* GRE */
11822 /* Any location for which the resultant memory type is any
11823 * type of Device memory is always treated as Outer Shareable.
11825 ret
.shareability
= 2;
11826 } else { /* Normal memory */
11827 /* Outer/inner cacheability combine independently */
11828 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
11829 | combine_cacheattr_nibble(s1lo
, s2lo
);
11831 if (ret
.attrs
== 0x44) {
11832 /* Any location for which the resultant memory type is Normal
11833 * Inner Non-cacheable, Outer Non-cacheable is always treated
11834 * as Outer Shareable.
11836 ret
.shareability
= 2;
11844 /* get_phys_addr - get the physical address for this virtual address
11846 * Find the physical address corresponding to the given virtual address,
11847 * by doing a translation table walk on MMU based systems or using the
11848 * MPU state on MPU based systems.
11850 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11851 * prot and page_size may not be filled in, and the populated fsr value provides
11852 * information on why the translation aborted, in the format of a
11853 * DFSR/IFSR fault register, with the following caveats:
11854 * * we honour the short vs long DFSR format differences.
11855 * * the WnR bit is never set (the caller must do this).
11856 * * for PSMAv5 based systems we don't bother to return a full FSR format
11859 * @env: CPUARMState
11860 * @address: virtual address to get physical address for
11861 * @access_type: 0 for read, 1 for write, 2 for execute
11862 * @mmu_idx: MMU index indicating required translation regime
11863 * @phys_ptr: set to the physical address corresponding to the virtual address
11864 * @attrs: set to the memory transaction attributes to use
11865 * @prot: set to the permissions for the page containing phys_ptr
11866 * @page_size: set to the size of the page containing phys_ptr
11867 * @fi: set to fault info if the translation fails
11868 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11870 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
11871 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11872 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
11873 target_ulong
*page_size
,
11874 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11876 if (mmu_idx
== ARMMMUIdx_E10_0
||
11877 mmu_idx
== ARMMMUIdx_E10_1
||
11878 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
11879 /* Call ourselves recursively to do the stage 1 and then stage 2
11882 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
11886 ARMCacheAttrs cacheattrs2
= {};
11888 ret
= get_phys_addr(env
, address
, access_type
,
11889 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
11890 prot
, page_size
, fi
, cacheattrs
);
11892 /* If S1 fails or S2 is disabled, return early. */
11893 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
11898 /* S1 is done. Now do S2 translation. */
11899 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_Stage2
,
11900 mmu_idx
== ARMMMUIdx_E10_0
,
11901 phys_ptr
, attrs
, &s2_prot
,
11903 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
11905 /* Combine the S1 and S2 perms. */
11908 /* Combine the S1 and S2 cache attributes, if needed */
11909 if (!ret
&& cacheattrs
!= NULL
) {
11910 if (env
->cp15
.hcr_el2
& HCR_DC
) {
11912 * HCR.DC forces the first stage attributes to
11913 * Normal Non-Shareable,
11914 * Inner Write-Back Read-Allocate Write-Allocate,
11915 * Outer Write-Back Read-Allocate Write-Allocate.
11917 cacheattrs
->attrs
= 0xff;
11918 cacheattrs
->shareability
= 0;
11920 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
11926 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
11928 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
11932 /* The page table entries may downgrade secure to non-secure, but
11933 * cannot upgrade an non-secure translation regime's attributes
11936 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
11937 attrs
->user
= regime_is_user(env
, mmu_idx
);
11939 /* Fast Context Switch Extension. This doesn't exist at all in v8.
11940 * In v7 and earlier it affects all stage 1 translations.
11942 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
11943 && !arm_feature(env
, ARM_FEATURE_V8
)) {
11944 if (regime_el(env
, mmu_idx
) == 3) {
11945 address
+= env
->cp15
.fcseidr_s
;
11947 address
+= env
->cp15
.fcseidr_ns
;
11951 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
11953 *page_size
= TARGET_PAGE_SIZE
;
11955 if (arm_feature(env
, ARM_FEATURE_V8
)) {
11957 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
11958 phys_ptr
, attrs
, prot
, page_size
, fi
);
11959 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
11961 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
11962 phys_ptr
, prot
, page_size
, fi
);
11965 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
11966 phys_ptr
, prot
, fi
);
11968 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
11969 " mmu_idx %u -> %s (prot %c%c%c)\n",
11970 access_type
== MMU_DATA_LOAD
? "reading" :
11971 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
11972 (uint32_t)address
, mmu_idx
,
11973 ret
? "Miss" : "Hit",
11974 *prot
& PAGE_READ
? 'r' : '-',
11975 *prot
& PAGE_WRITE
? 'w' : '-',
11976 *prot
& PAGE_EXEC
? 'x' : '-');
11981 /* Definitely a real MMU, not an MPU */
11983 if (regime_translation_disabled(env
, mmu_idx
)) {
11985 * MMU disabled. S1 addresses within aa64 translation regimes are
11986 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
11988 if (mmu_idx
!= ARMMMUIdx_Stage2
) {
11989 int r_el
= regime_el(env
, mmu_idx
);
11990 if (arm_el_is_aa64(env
, r_el
)) {
11991 int pamax
= arm_pamax(env_archcpu(env
));
11992 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
].raw_tcr
;
11995 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11996 if (access_type
== MMU_INST_FETCH
) {
11997 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11999 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
12000 addrtop
= (tbi
? 55 : 63);
12002 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
12003 fi
->type
= ARMFault_AddressSize
;
12005 fi
->stage2
= false;
12010 * When TBI is disabled, we've just validated that all of the
12011 * bits above PAMax are zero, so logically we only need to
12012 * clear the top byte for TBI. But it's clearer to follow
12013 * the pseudocode set of addrdesc.paddress.
12015 address
= extract64(address
, 0, 52);
12018 *phys_ptr
= address
;
12019 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12020 *page_size
= TARGET_PAGE_SIZE
;
12024 if (regime_using_lpae_format(env
, mmu_idx
)) {
12025 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, false,
12026 phys_ptr
, attrs
, prot
, page_size
,
12028 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
12029 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
12030 phys_ptr
, attrs
, prot
, page_size
, fi
);
12032 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
12033 phys_ptr
, prot
, page_size
, fi
);
12037 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
12040 ARMCPU
*cpu
= ARM_CPU(cs
);
12041 CPUARMState
*env
= &cpu
->env
;
12043 target_ulong page_size
;
12046 ARMMMUFaultInfo fi
= {};
12047 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
12049 *attrs
= (MemTxAttrs
) {};
12051 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
12052 attrs
, &prot
, &page_size
, &fi
, NULL
);
12062 /* Note that signed overflow is undefined in C. The following routines are
12063 careful to use unsigned types where modulo arithmetic is required.
12064 Failure to do so _will_ break on newer gcc. */
12066 /* Signed saturating arithmetic. */
12068 /* Perform 16-bit signed saturating addition. */
12069 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
12074 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
12083 /* Perform 8-bit signed saturating addition. */
12084 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
12089 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
12098 /* Perform 16-bit signed saturating subtraction. */
12099 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
12104 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
12113 /* Perform 8-bit signed saturating subtraction. */
12114 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
12119 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
12128 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12129 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12130 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12131 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12134 #include "op_addsub.h"
12136 /* Unsigned saturating arithmetic. */
12137 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
12146 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
12154 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
12163 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
12171 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12172 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12173 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12174 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12177 #include "op_addsub.h"
12179 /* Signed modulo arithmetic. */
12180 #define SARITH16(a, b, n, op) do { \
12182 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12183 RESULT(sum, n, 16); \
12185 ge |= 3 << (n * 2); \
12188 #define SARITH8(a, b, n, op) do { \
12190 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12191 RESULT(sum, n, 8); \
12197 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12198 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12199 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12200 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12204 #include "op_addsub.h"
12206 /* Unsigned modulo arithmetic. */
12207 #define ADD16(a, b, n) do { \
12209 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12210 RESULT(sum, n, 16); \
12211 if ((sum >> 16) == 1) \
12212 ge |= 3 << (n * 2); \
12215 #define ADD8(a, b, n) do { \
12217 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12218 RESULT(sum, n, 8); \
12219 if ((sum >> 8) == 1) \
12223 #define SUB16(a, b, n) do { \
12225 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12226 RESULT(sum, n, 16); \
12227 if ((sum >> 16) == 0) \
12228 ge |= 3 << (n * 2); \
12231 #define SUB8(a, b, n) do { \
12233 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12234 RESULT(sum, n, 8); \
12235 if ((sum >> 8) == 0) \
12242 #include "op_addsub.h"
12244 /* Halved signed arithmetic. */
12245 #define ADD16(a, b, n) \
12246 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12247 #define SUB16(a, b, n) \
12248 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12249 #define ADD8(a, b, n) \
12250 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12251 #define SUB8(a, b, n) \
12252 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12255 #include "op_addsub.h"
12257 /* Halved unsigned arithmetic. */
12258 #define ADD16(a, b, n) \
12259 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12260 #define SUB16(a, b, n) \
12261 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12262 #define ADD8(a, b, n) \
12263 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12264 #define SUB8(a, b, n) \
12265 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12268 #include "op_addsub.h"
12270 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
12278 /* Unsigned sum of absolute byte differences. */
12279 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12282 sum
= do_usad(a
, b
);
12283 sum
+= do_usad(a
>> 8, b
>> 8);
12284 sum
+= do_usad(a
>> 16, b
>>16);
12285 sum
+= do_usad(a
>> 24, b
>> 24);
12289 /* For ARMv6 SEL instruction. */
12290 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12302 mask
|= 0xff000000;
12303 return (a
& mask
) | (b
& ~mask
);
12307 * The upper bytes of val (above the number specified by 'bytes') must have
12308 * been zeroed out by the caller.
12310 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12314 stl_le_p(buf
, val
);
12316 /* zlib crc32 converts the accumulator and output to one's complement. */
12317 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12320 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12324 stl_le_p(buf
, val
);
12326 /* Linux crc32c converts the output to one's complement. */
12327 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12330 /* Return the exception level to which FP-disabled exceptions should
12331 * be taken, or 0 if FP is enabled.
12333 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12335 #ifndef CONFIG_USER_ONLY
12336 /* CPACR and the CPTR registers don't exist before v6, so FP is
12337 * always accessible
12339 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12343 if (arm_feature(env
, ARM_FEATURE_M
)) {
12344 /* CPACR can cause a NOCP UsageFault taken to current security state */
12345 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12349 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12350 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12351 /* FP insns cause a NOCP UsageFault taken to Secure */
12359 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12360 * 0, 2 : trap EL0 and EL1/PL1 accesses
12361 * 1 : trap only EL0 accesses
12362 * 3 : trap no accesses
12363 * This register is ignored if E2H+TGE are both set.
12365 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12366 int fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
12371 if (cur_el
== 0 || cur_el
== 1) {
12372 /* Trap to PL1, which might be EL1 or EL3 */
12373 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
12378 if (cur_el
== 3 && !is_a64(env
)) {
12379 /* Secure PL1 running at EL3 */
12394 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12395 * to control non-secure access to the FPU. It doesn't have any
12396 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12398 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12399 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12400 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12401 /* FP insns act as UNDEF */
12402 return cur_el
== 2 ? 2 : 1;
12406 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12407 * check because zero bits in the registers mean "don't trap".
12410 /* CPTR_EL2 : present in v7VE or v8 */
12411 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
12412 && !arm_is_secure_below_el3(env
)) {
12413 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12417 /* CPTR_EL3 : present in v8 */
12418 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
12419 /* Trap all FP ops to EL3 */
12426 /* Return the exception level we're running at if this is our mmu_idx */
12427 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12429 if (mmu_idx
& ARM_MMU_IDX_M
) {
12430 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12434 case ARMMMUIdx_E10_0
:
12435 case ARMMMUIdx_E20_0
:
12436 case ARMMMUIdx_SE10_0
:
12438 case ARMMMUIdx_E10_1
:
12439 case ARMMMUIdx_E10_1_PAN
:
12440 case ARMMMUIdx_SE10_1
:
12441 case ARMMMUIdx_SE10_1_PAN
:
12444 case ARMMMUIdx_E20_2
:
12445 case ARMMMUIdx_E20_2_PAN
:
12447 case ARMMMUIdx_SE3
:
12450 g_assert_not_reached();
12455 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12457 g_assert_not_reached();
12461 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12463 if (arm_feature(env
, ARM_FEATURE_M
)) {
12464 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12467 /* See ARM pseudo-function ELIsInHost. */
12470 if (arm_is_secure_below_el3(env
)) {
12471 return ARMMMUIdx_SE10_0
;
12473 if ((env
->cp15
.hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)
12474 && arm_el_is_aa64(env
, 2)) {
12475 return ARMMMUIdx_E20_0
;
12477 return ARMMMUIdx_E10_0
;
12479 if (arm_is_secure_below_el3(env
)) {
12480 if (env
->pstate
& PSTATE_PAN
) {
12481 return ARMMMUIdx_SE10_1_PAN
;
12483 return ARMMMUIdx_SE10_1
;
12485 if (env
->pstate
& PSTATE_PAN
) {
12486 return ARMMMUIdx_E10_1_PAN
;
12488 return ARMMMUIdx_E10_1
;
12490 /* TODO: ARMv8.4-SecEL2 */
12491 /* Note that TGE does not apply at EL2. */
12492 if ((env
->cp15
.hcr_el2
& HCR_E2H
) && arm_el_is_aa64(env
, 2)) {
12493 if (env
->pstate
& PSTATE_PAN
) {
12494 return ARMMMUIdx_E20_2_PAN
;
12496 return ARMMMUIdx_E20_2
;
12498 return ARMMMUIdx_E2
;
12500 return ARMMMUIdx_SE3
;
12502 g_assert_not_reached();
12506 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12508 return arm_mmu_idx_el(env
, arm_current_el(env
));
12511 #ifndef CONFIG_USER_ONLY
12512 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
12514 return stage_1_mmu_idx(arm_mmu_idx(env
));
12518 static uint32_t rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
12519 ARMMMUIdx mmu_idx
, uint32_t flags
)
12521 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
12522 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
,
12523 arm_to_core_mmu_idx(mmu_idx
));
12525 if (arm_singlestep_active(env
)) {
12526 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
12531 static uint32_t rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
12532 ARMMMUIdx mmu_idx
, uint32_t flags
)
12534 bool sctlr_b
= arm_sctlr_b(env
);
12537 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, 1);
12539 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
12540 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
12542 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
12544 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12547 static uint32_t rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
12550 uint32_t flags
= 0;
12552 if (arm_v7m_is_handler_mode(env
)) {
12553 flags
= FIELD_DP32(flags
, TBFLAG_M32
, HANDLER
, 1);
12557 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
12558 * is suppressing them because the requested execution priority
12561 if (arm_feature(env
, ARM_FEATURE_V8
) &&
12562 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
12563 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
12564 flags
= FIELD_DP32(flags
, TBFLAG_M32
, STACKCHECK
, 1);
12567 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12570 static uint32_t rebuild_hflags_aprofile(CPUARMState
*env
)
12574 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
,
12575 arm_debug_target_el(env
));
12579 static uint32_t rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
12582 uint32_t flags
= rebuild_hflags_aprofile(env
);
12584 if (arm_el_is_aa64(env
, 1)) {
12585 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12588 if (arm_current_el(env
) < 2 && env
->cp15
.hstr_el2
&&
12589 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12590 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HSTR_ACTIVE
, 1);
12593 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12596 static uint32_t rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
12599 uint32_t flags
= rebuild_hflags_aprofile(env
);
12600 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
12601 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
12605 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
12607 /* Get control bits for tagged addresses. */
12608 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12609 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12611 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
12612 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
12614 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
12615 int sve_el
= sve_exception_el(env
, el
);
12619 * If SVE is disabled, but FP is enabled,
12620 * then the effective len is 0.
12622 if (sve_el
!= 0 && fp_el
== 0) {
12625 zcr_len
= sve_zcr_len_for_el(env
, el
);
12627 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
12628 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
12631 sctlr
= regime_sctlr(env
, stage1
);
12633 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
12634 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
12637 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
12639 * In order to save space in flags, we record only whether
12640 * pauth is "inactive", meaning all insns are implemented as
12641 * a nop, or "active" when some action must be performed.
12642 * The decision of which action to take is left to a helper.
12644 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
12645 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
12649 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12650 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12651 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
12652 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
12656 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12657 if (!(env
->pstate
& PSTATE_UAO
)) {
12659 case ARMMMUIdx_E10_1
:
12660 case ARMMMUIdx_E10_1_PAN
:
12661 case ARMMMUIdx_SE10_1
:
12662 case ARMMMUIdx_SE10_1_PAN
:
12663 /* TODO: ARMv8.3-NV */
12664 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
12666 case ARMMMUIdx_E20_2
:
12667 case ARMMMUIdx_E20_2_PAN
:
12668 /* TODO: ARMv8.4-SecEL2 */
12670 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12671 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12673 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
12674 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
12682 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12685 static uint32_t rebuild_hflags_internal(CPUARMState
*env
)
12687 int el
= arm_current_el(env
);
12688 int fp_el
= fp_exception_el(env
, el
);
12689 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12692 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12693 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
12694 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12696 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12700 void arm_rebuild_hflags(CPUARMState
*env
)
12702 env
->hflags
= rebuild_hflags_internal(env
);
12706 * If we have triggered a EL state change we can't rely on the
12707 * translator having passed it to us, we need to recompute.
12709 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
12711 int el
= arm_current_el(env
);
12712 int fp_el
= fp_exception_el(env
, el
);
12713 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12714 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12717 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
12719 int fp_el
= fp_exception_el(env
, el
);
12720 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12722 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12726 * If we have triggered a EL state change we can't rely on the
12727 * translator having passed it to us, we need to recompute.
12729 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
12731 int el
= arm_current_el(env
);
12732 int fp_el
= fp_exception_el(env
, el
);
12733 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12734 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12737 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
12739 int fp_el
= fp_exception_el(env
, el
);
12740 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12742 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12745 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
12747 int fp_el
= fp_exception_el(env
, el
);
12748 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12750 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12753 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
12755 #ifdef CONFIG_DEBUG_TCG
12756 uint32_t env_flags_current
= env
->hflags
;
12757 uint32_t env_flags_rebuilt
= rebuild_hflags_internal(env
);
12759 if (unlikely(env_flags_current
!= env_flags_rebuilt
)) {
12760 fprintf(stderr
, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
12761 env_flags_current
, env_flags_rebuilt
);
12767 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12768 target_ulong
*cs_base
, uint32_t *pflags
)
12770 uint32_t flags
= env
->hflags
;
12771 uint32_t pstate_for_ss
;
12774 assert_hflags_rebuild_correctly(env
);
12776 if (FIELD_EX32(flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
12778 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12779 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
12781 pstate_for_ss
= env
->pstate
;
12783 *pc
= env
->regs
[15];
12785 if (arm_feature(env
, ARM_FEATURE_M
)) {
12786 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12787 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12788 != env
->v7m
.secure
) {
12789 flags
= FIELD_DP32(flags
, TBFLAG_M32
, FPCCR_S_WRONG
, 1);
12792 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12793 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12794 (env
->v7m
.secure
&&
12795 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12797 * ASPEN is set, but FPCA/SFPA indicate that there is no
12798 * active FP context; we must create a new FP context before
12799 * executing any FP insn.
12801 flags
= FIELD_DP32(flags
, TBFLAG_M32
, NEW_FP_CTXT_NEEDED
, 1);
12804 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12805 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12806 flags
= FIELD_DP32(flags
, TBFLAG_M32
, LSPACT
, 1);
12810 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12811 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12813 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12814 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
12815 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12817 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
,
12819 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
,
12820 env
->vfp
.vec_stride
);
12822 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12823 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12827 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, THUMB
, env
->thumb
);
12828 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, CONDEXEC
, env
->condexec_bits
);
12829 pstate_for_ss
= env
->uncached_cpsr
;
12833 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12834 * states defined in the ARM ARM for software singlestep:
12835 * SS_ACTIVE PSTATE.SS State
12836 * 0 x Inactive (the TB flag for SS is always 0)
12837 * 1 0 Active-pending
12838 * 1 1 Active-not-pending
12839 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
12841 if (FIELD_EX32(flags
, TBFLAG_ANY
, SS_ACTIVE
) &&
12842 (pstate_for_ss
& PSTATE_SS
)) {
12843 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
12849 #ifdef TARGET_AARCH64
12851 * The manual says that when SVE is enabled and VQ is widened the
12852 * implementation is allowed to zero the previously inaccessible
12853 * portion of the registers. The corollary to that is that when
12854 * SVE is enabled and VQ is narrowed we are also allowed to zero
12855 * the now inaccessible portion of the registers.
12857 * The intent of this is that no predicate bit beyond VQ is ever set.
12858 * Which means that some operations on predicate registers themselves
12859 * may operate on full uint64_t or even unrolled across the maximum
12860 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12861 * may well be cheaper than conditionals to restrict the operation
12862 * to the relevant portion of a uint16_t[16].
12864 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12869 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12870 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12872 /* Zap the high bits of the zregs. */
12873 for (i
= 0; i
< 32; i
++) {
12874 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12877 /* Zap the high bits of the pregs and ffr. */
12880 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12882 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12883 for (i
= 0; i
< 17; ++i
) {
12884 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12891 * Notice a change in SVE vector size when changing EL.
12893 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12894 int new_el
, bool el0_a64
)
12896 ARMCPU
*cpu
= env_archcpu(env
);
12897 int old_len
, new_len
;
12898 bool old_a64
, new_a64
;
12900 /* Nothing to do if no SVE. */
12901 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12905 /* Nothing to do if FP is disabled in either EL. */
12906 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12911 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12912 * at ELx, or not available because the EL is in AArch32 state, then
12913 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12914 * has an effective value of 0".
12916 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12917 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12918 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12919 * we already have the correct register contents when encountering the
12920 * vq0->vq0 transition between EL0->EL1.
12922 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12923 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
12924 ? sve_zcr_len_for_el(env
, old_el
) : 0);
12925 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12926 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
12927 ? sve_zcr_len_for_el(env
, new_el
) : 0);
12929 /* When changing vector length, clear inaccessible state. */
12930 if (new_len
< old_len
) {
12931 aarch64_sve_narrow_vq(env
, new_len
+ 1);