4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
266 static bool arm_pan_enabled(CPUARMState
*env
)
269 if ((arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
)) == (HCR_NV
| HCR_NV1
)) {
272 return env
->pstate
& PSTATE_PAN
;
274 return env
->uncached_cpsr
& CPSR_PAN
;
279 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
281 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
282 const ARMCPRegInfo
*ri
,
285 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
286 arm_is_secure_below_el3(env
)) {
287 return CP_ACCESS_TRAP_UNCATEGORIZED
;
293 * Some secure-only AArch32 registers trap to EL3 if used from
294 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
295 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
296 * We assume that the .access field is set to PL1_RW.
298 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
299 const ARMCPRegInfo
*ri
,
302 if (arm_current_el(env
) == 3) {
305 if (arm_is_secure_below_el3(env
)) {
306 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
307 return CP_ACCESS_TRAP_EL2
;
309 return CP_ACCESS_TRAP_EL3
;
311 /* This will be EL1 NS and EL2 NS, which just UNDEF */
312 return CP_ACCESS_TRAP_UNCATEGORIZED
;
316 * Check for traps to performance monitor registers, which are controlled
317 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
319 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
322 int el
= arm_current_el(env
);
323 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
325 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
326 return CP_ACCESS_TRAP_EL2
;
328 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
329 return CP_ACCESS_TRAP_EL3
;
334 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
335 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
338 if (arm_current_el(env
) == 1) {
339 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
340 if (arm_hcr_el2_eff(env
) & trap
) {
341 return CP_ACCESS_TRAP_EL2
;
347 /* Check for traps from EL1 due to HCR_EL2.TSW. */
348 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
351 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
352 return CP_ACCESS_TRAP_EL2
;
357 /* Check for traps from EL1 due to HCR_EL2.TACR. */
358 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
361 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
362 return CP_ACCESS_TRAP_EL2
;
367 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
368 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
371 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
372 return CP_ACCESS_TRAP_EL2
;
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
378 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
383 return CP_ACCESS_TRAP_EL2
;
388 #ifdef TARGET_AARCH64
389 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
390 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
393 if (arm_current_el(env
) == 1 &&
394 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
395 return CP_ACCESS_TRAP_EL2
;
401 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
403 ARMCPU
*cpu
= env_archcpu(env
);
405 raw_write(env
, ri
, value
);
406 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
409 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
411 ARMCPU
*cpu
= env_archcpu(env
);
413 if (raw_read(env
, ri
) != value
) {
415 * Unlike real hardware the qemu TLB uses virtual addresses,
416 * not modified virtual addresses, so this causes a TLB flush.
419 raw_write(env
, ri
, value
);
423 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
426 ARMCPU
*cpu
= env_archcpu(env
);
428 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
429 && !extended_addresses_enabled(env
)) {
431 * For VMSA (when not using the LPAE long descriptor page table
432 * format) this register includes the ASID, so do a TLB flush.
433 * For PMSA it is purely a process ID and no action is needed.
437 raw_write(env
, ri
, value
);
440 static int alle1_tlbmask(CPUARMState
*env
)
443 * Note that the 'ALL' scope must invalidate both stage 1 and
444 * stage 2 translations, whereas most other scopes only invalidate
445 * stage 1 translations.
447 return (ARMMMUIdxBit_E10_1
|
448 ARMMMUIdxBit_E10_1_PAN
|
450 ARMMMUIdxBit_Stage2
|
451 ARMMMUIdxBit_Stage2_S
);
455 /* IS variants of TLB operations must affect all cores */
456 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
459 CPUState
*cs
= env_cpu(env
);
461 tlb_flush_all_cpus_synced(cs
);
464 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
467 CPUState
*cs
= env_cpu(env
);
469 tlb_flush_all_cpus_synced(cs
);
472 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 CPUState
*cs
= env_cpu(env
);
477 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
480 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
483 CPUState
*cs
= env_cpu(env
);
485 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
489 * Non-IS variants of TLB operations are upgraded to
490 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
491 * force broadcast of these operations.
493 static bool tlb_force_broadcast(CPUARMState
*env
)
495 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
498 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 /* Invalidate all (TLBIALL) */
502 CPUState
*cs
= env_cpu(env
);
504 if (tlb_force_broadcast(env
)) {
505 tlb_flush_all_cpus_synced(cs
);
511 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
514 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
515 CPUState
*cs
= env_cpu(env
);
517 value
&= TARGET_PAGE_MASK
;
518 if (tlb_force_broadcast(env
)) {
519 tlb_flush_page_all_cpus_synced(cs
, value
);
521 tlb_flush_page(cs
, value
);
525 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate by ASID (TLBIASID) */
529 CPUState
*cs
= env_cpu(env
);
531 if (tlb_force_broadcast(env
)) {
532 tlb_flush_all_cpus_synced(cs
);
538 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
542 CPUState
*cs
= env_cpu(env
);
544 value
&= TARGET_PAGE_MASK
;
545 if (tlb_force_broadcast(env
)) {
546 tlb_flush_page_all_cpus_synced(cs
, value
);
548 tlb_flush_page(cs
, value
);
552 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
555 CPUState
*cs
= env_cpu(env
);
557 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
560 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
563 CPUState
*cs
= env_cpu(env
);
565 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
569 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
572 CPUState
*cs
= env_cpu(env
);
574 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
577 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
580 CPUState
*cs
= env_cpu(env
);
582 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
585 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
588 CPUState
*cs
= env_cpu(env
);
589 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
591 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
594 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= env_cpu(env
);
598 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
600 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
604 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 CPUState
*cs
= env_cpu(env
);
608 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
610 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
613 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 CPUState
*cs
= env_cpu(env
);
617 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
619 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
622 static const ARMCPRegInfo cp_reginfo
[] = {
624 * Define the secure and non-secure FCSE identifier CP registers
625 * separately because there is no secure bank in V8 (no _EL3). This allows
626 * the secure register to be properly reset and migrated. There is also no
627 * v8 EL1 version of the register so the non-secure instance stands alone.
630 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
631 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
633 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
634 { .name
= "FCSEIDR_S",
635 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
636 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
637 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
638 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
640 * Define the secure and non-secure context identifier CP registers
641 * separately because there is no secure bank in V8 (no _EL3). This allows
642 * the secure register to be properly reset and migrated. In the
643 * non-secure case, the 32-bit register will have reset and migration
644 * disabled during registration as it is handled by the 64-bit instance.
646 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
647 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
648 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
649 .fgt
= FGT_CONTEXTIDR_EL1
,
650 .secure
= ARM_CP_SECSTATE_NS
,
651 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
652 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
653 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
654 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
655 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
656 .secure
= ARM_CP_SECSTATE_S
,
657 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
658 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
661 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
663 * NB: Some of these registers exist in v8 but with more precise
664 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
666 /* MMU Domain access control / MPU write buffer control */
668 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
669 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
670 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
671 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
672 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
674 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
675 * For v6 and v5, these mappings are overly broad.
677 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
678 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
679 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
680 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
681 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
682 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
683 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
684 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
685 /* Cache maintenance ops; some of this space may be overridden later. */
686 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
687 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
688 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
691 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
693 * Not all pre-v6 cores implemented this WFI, so this is slightly
696 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
697 .access
= PL1_W
, .type
= ARM_CP_WFI
},
700 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
702 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
703 * is UNPREDICTABLE; we choose to NOP as most implementations do).
705 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
706 .access
= PL1_W
, .type
= ARM_CP_WFI
},
708 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
709 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
710 * OMAPCP will override this space.
712 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
713 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
715 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
716 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
718 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
719 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
720 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
723 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
724 * implementing it as RAZ means the "debug architecture version" bits
725 * will read as a reserved value, which should cause Linux to not try
726 * to use the debug hardware.
728 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
729 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
731 * MMU TLB control. Note that the wildcarding means we cover not just
732 * the unified TLB ops but also the dside/iside/inner-shareable variants.
734 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
735 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
736 .type
= ARM_CP_NO_RAW
},
737 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
738 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
739 .type
= ARM_CP_NO_RAW
},
740 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
741 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
742 .type
= ARM_CP_NO_RAW
},
743 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
744 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
745 .type
= ARM_CP_NO_RAW
},
746 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
747 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
748 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
749 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
752 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
757 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
758 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
760 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
761 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
762 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
764 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
765 /* VFP coprocessor: cp10 & cp11 [23:20] */
766 mask
|= R_CPACR_ASEDIS_MASK
|
767 R_CPACR_D32DIS_MASK
|
771 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
772 /* ASEDIS [31] bit is RAO/WI */
773 value
|= R_CPACR_ASEDIS_MASK
;
777 * VFPv3 and upwards with NEON implement 32 double precision
778 * registers (D0-D31).
780 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
781 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
782 value
|= R_CPACR_D32DIS_MASK
;
789 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
790 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
792 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
793 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
794 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
795 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
798 env
->cp15
.cpacr_el1
= value
;
801 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
804 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
805 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
807 uint64_t value
= env
->cp15
.cpacr_el1
;
809 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
810 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
811 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
817 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
820 * Call cpacr_write() so that we reset with the correct RAO bits set
821 * for our CPU features.
823 cpacr_write(env
, ri
, 0);
826 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
829 if (arm_feature(env
, ARM_FEATURE_V8
)) {
830 /* Check if CPACR accesses are to be trapped to EL2 */
831 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
832 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
833 return CP_ACCESS_TRAP_EL2
;
834 /* Check if CPACR accesses are to be trapped to EL3 */
835 } else if (arm_current_el(env
) < 3 &&
836 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
837 return CP_ACCESS_TRAP_EL3
;
844 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
847 /* Check if CPTR accesses are set to trap to EL3 */
848 if (arm_current_el(env
) == 2 &&
849 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
850 return CP_ACCESS_TRAP_EL3
;
856 static const ARMCPRegInfo v6_cp_reginfo
[] = {
857 /* prefetch by MVA in v6, NOP in v7 */
858 { .name
= "MVA_prefetch",
859 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
860 .access
= PL1_W
, .type
= ARM_CP_NOP
},
862 * We need to break the TB after ISB to execute self-modifying code
863 * correctly and also to take any pending interrupts immediately.
864 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
866 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
867 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
868 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
869 .access
= PL0_W
, .type
= ARM_CP_NOP
},
870 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
871 .access
= PL0_W
, .type
= ARM_CP_NOP
},
872 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
873 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
874 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
875 offsetof(CPUARMState
, cp15
.ifar_ns
) },
878 * Watchpoint Fault Address Register : should actually only be present
879 * for 1136, 1176, 11MPCore.
881 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
882 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
883 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
884 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
885 .fgt
= FGT_CPACR_EL1
,
886 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
887 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
890 typedef struct pm_event
{
891 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
892 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
893 bool (*supported
)(CPUARMState
*);
895 * Retrieve the current count of the underlying event. The programmed
896 * counters hold a difference from the return value from this function
898 uint64_t (*get_count
)(CPUARMState
*);
900 * Return how many nanoseconds it will take (at a minimum) for count events
901 * to occur. A negative value indicates the counter will never overflow, or
902 * that the counter has otherwise arranged for the overflow bit to be set
903 * and the PMU interrupt to be raised on overflow.
905 int64_t (*ns_per_count
)(uint64_t);
908 static bool event_always_supported(CPUARMState
*env
)
913 static uint64_t swinc_get_count(CPUARMState
*env
)
916 * SW_INCR events are written directly to the pmevcntr's by writes to
917 * PMSWINC, so there is no underlying count maintained by the PMU itself
922 static int64_t swinc_ns_per(uint64_t ignored
)
928 * Return the underlying cycle count for the PMU cycle counters. If we're in
929 * usermode, simply return 0.
931 static uint64_t cycles_get_count(CPUARMState
*env
)
933 #ifndef CONFIG_USER_ONLY
934 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
935 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
937 return cpu_get_host_ticks();
941 #ifndef CONFIG_USER_ONLY
942 static int64_t cycles_ns_per(uint64_t cycles
)
944 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
947 static bool instructions_supported(CPUARMState
*env
)
949 return icount_enabled() == 1; /* Precise instruction counting */
952 static uint64_t instructions_get_count(CPUARMState
*env
)
954 return (uint64_t)icount_get_raw();
957 static int64_t instructions_ns_per(uint64_t icount
)
959 return icount_to_ns((int64_t)icount
);
963 static bool pmuv3p1_events_supported(CPUARMState
*env
)
965 /* For events which are supported in any v8.1 PMU */
966 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
969 static bool pmuv3p4_events_supported(CPUARMState
*env
)
971 /* For events which are supported in any v8.1 PMU */
972 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
975 static uint64_t zero_event_get_count(CPUARMState
*env
)
977 /* For events which on QEMU never fire, so their count is always zero */
981 static int64_t zero_event_ns_per(uint64_t cycles
)
983 /* An event which never fires can never overflow */
987 static const pm_event pm_events
[] = {
988 { .number
= 0x000, /* SW_INCR */
989 .supported
= event_always_supported
,
990 .get_count
= swinc_get_count
,
991 .ns_per_count
= swinc_ns_per
,
993 #ifndef CONFIG_USER_ONLY
994 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
995 .supported
= instructions_supported
,
996 .get_count
= instructions_get_count
,
997 .ns_per_count
= instructions_ns_per
,
999 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1000 .supported
= event_always_supported
,
1001 .get_count
= cycles_get_count
,
1002 .ns_per_count
= cycles_ns_per
,
1005 { .number
= 0x023, /* STALL_FRONTEND */
1006 .supported
= pmuv3p1_events_supported
,
1007 .get_count
= zero_event_get_count
,
1008 .ns_per_count
= zero_event_ns_per
,
1010 { .number
= 0x024, /* STALL_BACKEND */
1011 .supported
= pmuv3p1_events_supported
,
1012 .get_count
= zero_event_get_count
,
1013 .ns_per_count
= zero_event_ns_per
,
1015 { .number
= 0x03c, /* STALL */
1016 .supported
= pmuv3p4_events_supported
,
1017 .get_count
= zero_event_get_count
,
1018 .ns_per_count
= zero_event_ns_per
,
1023 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1024 * events (i.e. the statistical profiling extension), this implementation
1025 * should first be updated to something sparse instead of the current
1026 * supported_event_map[] array.
1028 #define MAX_EVENT_ID 0x3c
1029 #define UNSUPPORTED_EVENT UINT16_MAX
1030 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1033 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1034 * of ARM event numbers to indices in our pm_events array.
1036 * Note: Events in the 0x40XX range are not currently supported.
1038 void pmu_init(ARMCPU
*cpu
)
1043 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1046 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1047 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1052 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1053 const pm_event
*cnt
= &pm_events
[i
];
1054 assert(cnt
->number
<= MAX_EVENT_ID
);
1055 /* We do not currently support events in the 0x40xx range */
1056 assert(cnt
->number
<= 0x3f);
1058 if (cnt
->supported(&cpu
->env
)) {
1059 supported_event_map
[cnt
->number
] = i
;
1060 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1061 if (cnt
->number
& 0x20) {
1062 cpu
->pmceid1
|= event_mask
;
1064 cpu
->pmceid0
|= event_mask
;
1071 * Check at runtime whether a PMU event is supported for the current machine
1073 static bool event_supported(uint16_t number
)
1075 if (number
> MAX_EVENT_ID
) {
1078 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1081 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1085 * Performance monitor registers user accessibility is controlled
1086 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1087 * trapping to EL2 or EL3 for other accesses.
1089 int el
= arm_current_el(env
);
1090 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1092 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1093 return CP_ACCESS_TRAP
;
1095 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1096 return CP_ACCESS_TRAP_EL2
;
1098 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1099 return CP_ACCESS_TRAP_EL3
;
1102 return CP_ACCESS_OK
;
1105 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1106 const ARMCPRegInfo
*ri
,
1109 /* ER: event counter read trap control */
1110 if (arm_feature(env
, ARM_FEATURE_V8
)
1111 && arm_current_el(env
) == 0
1112 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1114 return CP_ACCESS_OK
;
1117 return pmreg_access(env
, ri
, isread
);
1120 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1121 const ARMCPRegInfo
*ri
,
1124 /* SW: software increment write trap control */
1125 if (arm_feature(env
, ARM_FEATURE_V8
)
1126 && arm_current_el(env
) == 0
1127 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1129 return CP_ACCESS_OK
;
1132 return pmreg_access(env
, ri
, isread
);
1135 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1136 const ARMCPRegInfo
*ri
,
1139 /* ER: event counter read trap control */
1140 if (arm_feature(env
, ARM_FEATURE_V8
)
1141 && arm_current_el(env
) == 0
1142 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1143 return CP_ACCESS_OK
;
1146 return pmreg_access(env
, ri
, isread
);
1149 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1150 const ARMCPRegInfo
*ri
,
1153 /* CR: cycle counter read trap control */
1154 if (arm_feature(env
, ARM_FEATURE_V8
)
1155 && arm_current_el(env
) == 0
1156 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1158 return CP_ACCESS_OK
;
1161 return pmreg_access(env
, ri
, isread
);
1165 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1166 * We use these to decide whether we need to wrap a write to MDCR_EL2
1167 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1169 #define MDCR_EL2_PMU_ENABLE_BITS \
1170 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1171 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1174 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1175 * the current EL, security state, and register configuration.
1177 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1180 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1181 bool enabled
, prohibited
= false, filtered
;
1182 bool secure
= arm_is_secure(env
);
1183 int el
= arm_current_el(env
);
1184 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1185 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1187 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1191 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1192 (counter
< hpmn
|| counter
== 31)) {
1193 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1195 e
= mdcr_el2
& MDCR_HPME
;
1197 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1199 /* Is event counting prohibited? */
1200 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1201 prohibited
= mdcr_el2
& MDCR_HPMD
;
1204 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1207 if (counter
== 31) {
1209 * The cycle counter defaults to running. PMCR.DP says "disable
1210 * the cycle counter when event counting is prohibited".
1211 * Some MDCR bits disable the cycle counter specifically.
1213 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1214 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1216 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1219 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1224 if (counter
== 31) {
1225 filter
= env
->cp15
.pmccfiltr_el0
;
1227 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1230 p
= filter
& PMXEVTYPER_P
;
1231 u
= filter
& PMXEVTYPER_U
;
1232 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1233 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1234 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1235 m
= arm_el_is_aa64(env
, 1) &&
1236 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1239 filtered
= secure
? u
: u
!= nsu
;
1240 } else if (el
== 1) {
1241 filtered
= secure
? p
: p
!= nsk
;
1242 } else if (el
== 2) {
1248 if (counter
!= 31) {
1250 * If not checking PMCCNTR, ensure the counter is setup to an event we
1253 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1254 if (!event_supported(event
)) {
1259 return enabled
&& !prohibited
&& !filtered
;
1262 static void pmu_update_irq(CPUARMState
*env
)
1264 ARMCPU
*cpu
= env_archcpu(env
);
1265 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1266 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1269 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1272 * Return true if the clock divider is enabled and the cycle counter
1273 * is supposed to tick only once every 64 clock cycles. This is
1274 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1275 * (64-bit) cycle counter PMCR.D has no effect.
1277 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1280 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1282 /* Return true if the specified event counter is configured to be 64 bit */
1284 /* This isn't intended to be used with the cycle counter */
1285 assert(counter
< 31);
1287 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1291 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1293 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1294 * current security state, so we don't use arm_mdcr_el2_eff() here.
1296 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1297 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1299 if (counter
>= hpmn
) {
1303 return env
->cp15
.c9_pmcr
& PMCRLP
;
1307 * Ensure c15_ccnt is the guest-visible count so that operations such as
1308 * enabling/disabling the counter or filtering, modifying the count itself,
1309 * etc. can be done logically. This is essentially a no-op if the counter is
1310 * not enabled at the time of the call.
1312 static void pmccntr_op_start(CPUARMState
*env
)
1314 uint64_t cycles
= cycles_get_count(env
);
1316 if (pmu_counter_enabled(env
, 31)) {
1317 uint64_t eff_cycles
= cycles
;
1318 if (pmccntr_clockdiv_enabled(env
)) {
1322 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1324 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1325 1ull << 63 : 1ull << 31;
1326 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1327 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1328 pmu_update_irq(env
);
1331 env
->cp15
.c15_ccnt
= new_pmccntr
;
1333 env
->cp15
.c15_ccnt_delta
= cycles
;
1337 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1338 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1341 static void pmccntr_op_finish(CPUARMState
*env
)
1343 if (pmu_counter_enabled(env
, 31)) {
1344 #ifndef CONFIG_USER_ONLY
1345 /* Calculate when the counter will next overflow */
1346 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1347 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1348 remaining_cycles
= (uint32_t)remaining_cycles
;
1350 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1352 if (overflow_in
> 0) {
1353 int64_t overflow_at
;
1355 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1356 overflow_in
, &overflow_at
)) {
1357 ARMCPU
*cpu
= env_archcpu(env
);
1358 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1363 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1364 if (pmccntr_clockdiv_enabled(env
)) {
1367 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1371 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1374 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1376 if (event_supported(event
)) {
1377 uint16_t event_idx
= supported_event_map
[event
];
1378 count
= pm_events
[event_idx
].get_count(env
);
1381 if (pmu_counter_enabled(env
, counter
)) {
1382 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1383 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1384 1ULL << 63 : 1ULL << 31;
1386 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1387 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1388 pmu_update_irq(env
);
1390 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1392 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1395 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1397 if (pmu_counter_enabled(env
, counter
)) {
1398 #ifndef CONFIG_USER_ONLY
1399 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1400 uint16_t event_idx
= supported_event_map
[event
];
1401 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1402 int64_t overflow_in
;
1404 if (!pmevcntr_is_64_bit(env
, counter
)) {
1405 delta
= (uint32_t)delta
;
1407 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1409 if (overflow_in
> 0) {
1410 int64_t overflow_at
;
1412 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1413 overflow_in
, &overflow_at
)) {
1414 ARMCPU
*cpu
= env_archcpu(env
);
1415 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1420 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1421 env
->cp15
.c14_pmevcntr
[counter
];
1425 void pmu_op_start(CPUARMState
*env
)
1428 pmccntr_op_start(env
);
1429 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1430 pmevcntr_op_start(env
, i
);
1434 void pmu_op_finish(CPUARMState
*env
)
1437 pmccntr_op_finish(env
);
1438 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1439 pmevcntr_op_finish(env
, i
);
1443 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1445 pmu_op_start(&cpu
->env
);
1448 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1450 pmu_op_finish(&cpu
->env
);
1453 void arm_pmu_timer_cb(void *opaque
)
1455 ARMCPU
*cpu
= opaque
;
1458 * Update all the counter values based on the current underlying counts,
1459 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1460 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1461 * counter may expire.
1463 pmu_op_start(&cpu
->env
);
1464 pmu_op_finish(&cpu
->env
);
1467 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1472 if (value
& PMCRC
) {
1473 /* The counter has been reset */
1474 env
->cp15
.c15_ccnt
= 0;
1477 if (value
& PMCRP
) {
1479 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1480 env
->cp15
.c14_pmevcntr
[i
] = 0;
1484 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1485 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1490 static uint64_t pmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1492 uint64_t pmcr
= env
->cp15
.c9_pmcr
;
1495 * If EL2 is implemented and enabled for the current security state, reads
1496 * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN.
1498 if (arm_current_el(env
) <= 1 && arm_is_el2_enabled(env
)) {
1499 pmcr
&= ~PMCRN_MASK
;
1500 pmcr
|= (env
->cp15
.mdcr_el2
& MDCR_HPMN
) << PMCRN_SHIFT
;
1506 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1510 uint64_t overflow_mask
, new_pmswinc
;
1512 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1513 /* Increment a counter's count iff: */
1514 if ((value
& (1 << i
)) && /* counter's bit is set */
1515 /* counter is enabled and not filtered */
1516 pmu_counter_enabled(env
, i
) &&
1517 /* counter is SW_INCR */
1518 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1519 pmevcntr_op_start(env
, i
);
1522 * Detect if this write causes an overflow since we can't predict
1523 * PMSWINC overflows like we can for other events
1525 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1527 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1528 1ULL << 63 : 1ULL << 31;
1530 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1531 env
->cp15
.c9_pmovsr
|= (1 << i
);
1532 pmu_update_irq(env
);
1535 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1537 pmevcntr_op_finish(env
, i
);
1542 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1545 pmccntr_op_start(env
);
1546 ret
= env
->cp15
.c15_ccnt
;
1547 pmccntr_op_finish(env
);
1551 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1555 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1556 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1557 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1560 env
->cp15
.c9_pmselr
= value
& 0x1f;
1563 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1566 pmccntr_op_start(env
);
1567 env
->cp15
.c15_ccnt
= value
;
1568 pmccntr_op_finish(env
);
1571 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1574 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1576 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1579 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1582 pmccntr_op_start(env
);
1583 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1584 pmccntr_op_finish(env
);
1587 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1590 pmccntr_op_start(env
);
1591 /* M is not accessible from AArch32 */
1592 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1593 (value
& PMCCFILTR
);
1594 pmccntr_op_finish(env
);
1597 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1599 /* M is not visible in AArch32 */
1600 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1603 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1607 value
&= pmu_counter_mask(env
);
1608 env
->cp15
.c9_pmcnten
|= value
;
1612 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1616 value
&= pmu_counter_mask(env
);
1617 env
->cp15
.c9_pmcnten
&= ~value
;
1621 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1624 value
&= pmu_counter_mask(env
);
1625 env
->cp15
.c9_pmovsr
&= ~value
;
1626 pmu_update_irq(env
);
1629 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1632 value
&= pmu_counter_mask(env
);
1633 env
->cp15
.c9_pmovsr
|= value
;
1634 pmu_update_irq(env
);
1637 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1638 uint64_t value
, const uint8_t counter
)
1640 if (counter
== 31) {
1641 pmccfiltr_write(env
, ri
, value
);
1642 } else if (counter
< pmu_num_counters(env
)) {
1643 pmevcntr_op_start(env
, counter
);
1646 * If this counter's event type is changing, store the current
1647 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1648 * pmevcntr_op_finish has the correct baseline when it converts back to
1651 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1652 PMXEVTYPER_EVTCOUNT
;
1653 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1654 if (old_event
!= new_event
) {
1656 if (event_supported(new_event
)) {
1657 uint16_t event_idx
= supported_event_map
[new_event
];
1658 count
= pm_events
[event_idx
].get_count(env
);
1660 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1663 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1664 pmevcntr_op_finish(env
, counter
);
1667 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1668 * PMSELR value is equal to or greater than the number of implemented
1669 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1673 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1674 const uint8_t counter
)
1676 if (counter
== 31) {
1677 return env
->cp15
.pmccfiltr_el0
;
1678 } else if (counter
< pmu_num_counters(env
)) {
1679 return env
->cp15
.c14_pmevtyper
[counter
];
1682 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1683 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1689 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1692 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1693 pmevtyper_write(env
, ri
, value
, counter
);
1696 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1699 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1700 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1703 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1704 * pmu_op_finish calls when loading saved state for a migration. Because
1705 * we're potentially updating the type of event here, the value written to
1706 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1707 * different counter type. Therefore, we need to set this value to the
1708 * current count for the counter type we're writing so that pmu_op_finish
1709 * has the correct count for its calculation.
1711 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1712 if (event_supported(event
)) {
1713 uint16_t event_idx
= supported_event_map
[event
];
1714 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1715 pm_events
[event_idx
].get_count(env
);
1719 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1721 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1722 return pmevtyper_read(env
, ri
, counter
);
1725 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1731 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1733 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1736 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1737 uint64_t value
, uint8_t counter
)
1739 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1740 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1741 value
&= MAKE_64BIT_MASK(0, 32);
1743 if (counter
< pmu_num_counters(env
)) {
1744 pmevcntr_op_start(env
, counter
);
1745 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1746 pmevcntr_op_finish(env
, counter
);
1749 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1750 * are CONSTRAINED UNPREDICTABLE.
1754 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1757 if (counter
< pmu_num_counters(env
)) {
1759 pmevcntr_op_start(env
, counter
);
1760 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1761 pmevcntr_op_finish(env
, counter
);
1762 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1763 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1764 ret
&= MAKE_64BIT_MASK(0, 32);
1769 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1770 * are CONSTRAINED UNPREDICTABLE.
1776 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1779 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1780 pmevcntr_write(env
, ri
, value
, counter
);
1783 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1785 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1786 return pmevcntr_read(env
, ri
, counter
);
1789 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1792 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1793 assert(counter
< pmu_num_counters(env
));
1794 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1795 pmevcntr_write(env
, ri
, value
, counter
);
1798 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1800 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1801 assert(counter
< pmu_num_counters(env
));
1802 return env
->cp15
.c14_pmevcntr
[counter
];
1805 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1808 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1811 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1813 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1816 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1819 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1820 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1822 env
->cp15
.c9_pmuserenr
= value
& 1;
1826 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1829 /* We have no event counters so only the C bit can be changed */
1830 value
&= pmu_counter_mask(env
);
1831 env
->cp15
.c9_pminten
|= value
;
1832 pmu_update_irq(env
);
1835 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1838 value
&= pmu_counter_mask(env
);
1839 env
->cp15
.c9_pminten
&= ~value
;
1840 pmu_update_irq(env
);
1843 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1847 * Note that even though the AArch64 view of this register has bits
1848 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1849 * architectural requirements for bits which are RES0 only in some
1850 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1851 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1853 raw_write(env
, ri
, value
& ~0x1FULL
);
1856 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1858 /* Begin with base v8.0 state. */
1859 uint64_t valid_mask
= 0x3fff;
1860 ARMCPU
*cpu
= env_archcpu(env
);
1864 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1865 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1866 * Instead, choose the format based on the mode of EL3.
1868 if (arm_el_is_aa64(env
, 3)) {
1869 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1870 valid_mask
&= ~SCR_NET
; /* RES0 */
1872 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1873 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1874 value
|= SCR_RW
; /* RAO/WI */
1876 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1877 valid_mask
|= SCR_TERR
;
1879 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1880 valid_mask
|= SCR_TLOR
;
1882 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1883 valid_mask
|= SCR_API
| SCR_APK
;
1885 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1886 valid_mask
|= SCR_EEL2
;
1887 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1888 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1891 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1892 valid_mask
|= SCR_ATA
;
1894 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1895 valid_mask
|= SCR_ENSCXT
;
1897 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1898 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1900 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1901 valid_mask
|= SCR_ENTP2
;
1903 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1904 valid_mask
|= SCR_HXEN
;
1906 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1907 valid_mask
|= SCR_FGTEN
;
1909 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1910 valid_mask
|= SCR_NSE
| SCR_GPF
;
1913 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1914 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1915 valid_mask
|= SCR_TERR
;
1919 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1920 valid_mask
&= ~SCR_HCE
;
1923 * On ARMv7, SMD (or SCD as it is called in v7) is only
1924 * supported if EL2 exists. The bit is UNK/SBZP when
1925 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1926 * when EL2 is unavailable.
1927 * On ARMv8, this bit is always available.
1929 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1930 !arm_feature(env
, ARM_FEATURE_V8
)) {
1931 valid_mask
&= ~SCR_SMD
;
1935 /* Clear all-context RES0 bits. */
1936 value
&= valid_mask
;
1937 changed
= env
->cp15
.scr_el3
^ value
;
1938 env
->cp15
.scr_el3
= value
;
1941 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1942 * we must invalidate all TLBs below EL3.
1944 if (changed
& (SCR_NS
| SCR_NSE
)) {
1945 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1946 ARMMMUIdxBit_E20_0
|
1947 ARMMMUIdxBit_E10_1
|
1948 ARMMMUIdxBit_E20_2
|
1949 ARMMMUIdxBit_E10_1_PAN
|
1950 ARMMMUIdxBit_E20_2_PAN
|
1955 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1958 * scr_write will set the RES1 bits on an AArch64-only CPU.
1959 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1961 scr_write(env
, ri
, 0);
1964 static CPAccessResult
access_tid4(CPUARMState
*env
,
1965 const ARMCPRegInfo
*ri
,
1968 if (arm_current_el(env
) == 1 &&
1969 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1970 return CP_ACCESS_TRAP_EL2
;
1973 return CP_ACCESS_OK
;
1976 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1978 ARMCPU
*cpu
= env_archcpu(env
);
1981 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1984 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1985 ri
->secure
& ARM_CP_SECSTATE_S
);
1987 return cpu
->ccsidr
[index
];
1990 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1993 raw_write(env
, ri
, value
& 0xf);
1996 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1998 CPUState
*cs
= env_cpu(env
);
1999 bool el1
= arm_current_el(env
) == 1;
2000 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
2003 if (hcr_el2
& HCR_IMO
) {
2004 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2008 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2013 if (hcr_el2
& HCR_FMO
) {
2014 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2018 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2023 if (hcr_el2
& HCR_AMO
) {
2024 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2032 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2035 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2036 return CP_ACCESS_TRAP_EL2
;
2039 return CP_ACCESS_OK
;
2042 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2045 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2046 return access_aa64_tid1(env
, ri
, isread
);
2049 return CP_ACCESS_OK
;
2052 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2053 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2054 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2055 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2057 * Performance monitors are implementation defined in v7,
2058 * but with an ARM recommended set of registers, which we
2061 * Performance registers fall into three categories:
2062 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2063 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2064 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2065 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2066 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2068 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2069 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2070 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2071 .writefn
= pmcntenset_write
,
2072 .accessfn
= pmreg_access
,
2074 .raw_writefn
= raw_write
},
2075 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2076 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2077 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2079 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2080 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2081 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2083 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2084 .accessfn
= pmreg_access
,
2086 .writefn
= pmcntenclr_write
,
2087 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2088 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2089 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2090 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2092 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2093 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2094 .writefn
= pmcntenclr_write
},
2095 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2096 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2097 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2098 .accessfn
= pmreg_access
,
2100 .writefn
= pmovsr_write
,
2101 .raw_writefn
= raw_write
},
2102 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2103 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2104 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2106 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2107 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2108 .writefn
= pmovsr_write
,
2109 .raw_writefn
= raw_write
},
2110 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2111 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2112 .fgt
= FGT_PMSWINC_EL0
,
2113 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2114 .writefn
= pmswinc_write
},
2115 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2116 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2117 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2118 .fgt
= FGT_PMSWINC_EL0
,
2119 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2120 .writefn
= pmswinc_write
},
2121 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2122 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2123 .fgt
= FGT_PMSELR_EL0
,
2124 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2125 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2126 .raw_writefn
= raw_write
},
2127 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2128 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2129 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2130 .fgt
= FGT_PMSELR_EL0
,
2131 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2132 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2133 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2134 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2135 .fgt
= FGT_PMCCNTR_EL0
,
2136 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2137 .accessfn
= pmreg_access_ccntr
},
2138 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2139 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2140 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2141 .fgt
= FGT_PMCCNTR_EL0
,
2143 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2144 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2145 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2146 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2147 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2148 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2149 .fgt
= FGT_PMCCFILTR_EL0
,
2150 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2152 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2153 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2154 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2155 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2156 .fgt
= FGT_PMCCFILTR_EL0
,
2158 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2160 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2161 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2162 .accessfn
= pmreg_access
,
2163 .fgt
= FGT_PMEVTYPERN_EL0
,
2164 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2165 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2166 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2167 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2168 .accessfn
= pmreg_access
,
2169 .fgt
= FGT_PMEVTYPERN_EL0
,
2170 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2171 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2172 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2173 .accessfn
= pmreg_access_xevcntr
,
2174 .fgt
= FGT_PMEVCNTRN_EL0
,
2175 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2176 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2177 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2178 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2179 .accessfn
= pmreg_access_xevcntr
,
2180 .fgt
= FGT_PMEVCNTRN_EL0
,
2181 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2182 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2183 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2184 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2186 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2187 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2188 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2189 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2190 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2192 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2193 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2194 .access
= PL1_RW
, .accessfn
= access_tpm
,
2196 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2197 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2199 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2200 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2201 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2202 .access
= PL1_RW
, .accessfn
= access_tpm
,
2205 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2206 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2207 .resetvalue
= 0x0 },
2208 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2209 .access
= PL1_RW
, .accessfn
= access_tpm
,
2211 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2212 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2213 .writefn
= pmintenclr_write
, },
2214 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2215 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2216 .access
= PL1_RW
, .accessfn
= access_tpm
,
2218 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2219 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2220 .writefn
= pmintenclr_write
},
2221 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2222 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2224 .accessfn
= access_tid4
,
2225 .fgt
= FGT_CCSIDR_EL1
,
2226 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2227 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2228 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2230 .accessfn
= access_tid4
,
2231 .fgt
= FGT_CSSELR_EL1
,
2232 .writefn
= csselr_write
, .resetvalue
= 0,
2233 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2234 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2236 * Auxiliary ID register: this actually has an IMPDEF value but for now
2237 * just RAZ for all cores:
2239 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2240 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2241 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2242 .accessfn
= access_aa64_tid1
,
2243 .fgt
= FGT_AIDR_EL1
,
2246 * Auxiliary fault status registers: these also are IMPDEF, and we
2247 * choose to RAZ/WI for all cores.
2249 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2250 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2251 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2252 .fgt
= FGT_AFSR0_EL1
,
2253 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2254 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2255 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2256 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2257 .fgt
= FGT_AFSR1_EL1
,
2258 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2260 * MAIR can just read-as-written because we don't implement caches
2261 * and so don't need to care about memory attributes.
2263 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2264 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2265 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2266 .fgt
= FGT_MAIR_EL1
,
2267 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2269 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2270 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2271 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2274 * For non-long-descriptor page tables these are PRRR and NMRR;
2275 * regardless they still act as reads-as-written for QEMU.
2278 * MAIR0/1 are defined separately from their 64-bit counterpart which
2279 * allows them to assign the correct fieldoffset based on the endianness
2280 * handled in the field definitions.
2282 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2283 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2284 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2285 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2286 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2287 .resetfn
= arm_cp_reset_ignore
},
2288 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2289 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2290 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2291 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2292 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2293 .resetfn
= arm_cp_reset_ignore
},
2294 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2295 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2297 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2298 /* 32 bit ITLB invalidates */
2299 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2300 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2301 .writefn
= tlbiall_write
},
2302 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2303 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2304 .writefn
= tlbimva_write
},
2305 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2306 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2307 .writefn
= tlbiasid_write
},
2308 /* 32 bit DTLB invalidates */
2309 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2310 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2311 .writefn
= tlbiall_write
},
2312 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2313 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2314 .writefn
= tlbimva_write
},
2315 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2316 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2317 .writefn
= tlbiasid_write
},
2318 /* 32 bit TLB invalidates */
2319 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2320 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2321 .writefn
= tlbiall_write
},
2322 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2323 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2324 .writefn
= tlbimva_write
},
2325 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2326 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2327 .writefn
= tlbiasid_write
},
2328 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2329 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2330 .writefn
= tlbimvaa_write
},
2333 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2334 /* 32 bit TLB invalidates, Inner Shareable */
2335 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2336 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2337 .writefn
= tlbiall_is_write
},
2338 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2339 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2340 .writefn
= tlbimva_is_write
},
2341 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2342 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2343 .writefn
= tlbiasid_is_write
},
2344 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2345 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2346 .writefn
= tlbimvaa_is_write
},
2349 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2350 /* PMOVSSET is not implemented in v7 before v7ve */
2351 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2352 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2354 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2355 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2356 .writefn
= pmovsset_write
,
2357 .raw_writefn
= raw_write
},
2358 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2359 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2360 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2362 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2363 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2364 .writefn
= pmovsset_write
,
2365 .raw_writefn
= raw_write
},
2368 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2375 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2379 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2380 * at all, so we don't need to check whether we're v8A.
2382 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2383 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2384 return CP_ACCESS_TRAP_EL2
;
2386 return CP_ACCESS_OK
;
2389 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2392 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2393 return CP_ACCESS_TRAP
;
2395 return teecr_access(env
, ri
, isread
);
2398 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2399 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2400 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2402 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2403 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2404 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2405 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2408 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2409 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2410 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2412 .fgt
= FGT_TPIDR_EL0
,
2413 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2414 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2416 .fgt
= FGT_TPIDR_EL0
,
2417 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2418 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2419 .resetfn
= arm_cp_reset_ignore
},
2420 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2421 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2422 .access
= PL0_R
| PL1_W
,
2423 .fgt
= FGT_TPIDRRO_EL0
,
2424 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2426 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2427 .access
= PL0_R
| PL1_W
,
2428 .fgt
= FGT_TPIDRRO_EL0
,
2429 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2430 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2431 .resetfn
= arm_cp_reset_ignore
},
2432 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2433 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2435 .fgt
= FGT_TPIDR_EL1
,
2436 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2437 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2439 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2440 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2444 #ifndef CONFIG_USER_ONLY
2446 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2450 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2451 * Writable only at the highest implemented exception level.
2453 int el
= arm_current_el(env
);
2459 hcr
= arm_hcr_el2_eff(env
);
2460 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2461 cntkctl
= env
->cp15
.cnthctl_el2
;
2463 cntkctl
= env
->cp15
.c14_cntkctl
;
2465 if (!extract32(cntkctl
, 0, 2)) {
2466 return CP_ACCESS_TRAP
;
2470 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2471 arm_is_secure_below_el3(env
)) {
2472 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2473 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2481 if (!isread
&& el
< arm_highest_el(env
)) {
2482 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2485 return CP_ACCESS_OK
;
2488 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2491 unsigned int cur_el
= arm_current_el(env
);
2492 bool has_el2
= arm_is_el2_enabled(env
);
2493 uint64_t hcr
= arm_hcr_el2_eff(env
);
2497 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2498 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2499 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2500 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2503 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2504 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2505 return CP_ACCESS_TRAP
;
2509 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2510 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2512 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2513 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2514 return CP_ACCESS_TRAP_EL2
;
2518 return CP_ACCESS_OK
;
2521 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2524 unsigned int cur_el
= arm_current_el(env
);
2525 bool has_el2
= arm_is_el2_enabled(env
);
2526 uint64_t hcr
= arm_hcr_el2_eff(env
);
2530 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2531 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2532 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2533 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2537 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2538 * EL0 if EL0[PV]TEN is zero.
2540 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2541 return CP_ACCESS_TRAP
;
2546 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2547 if (hcr
& HCR_E2H
) {
2548 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2549 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2550 return CP_ACCESS_TRAP_EL2
;
2553 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2554 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2555 return CP_ACCESS_TRAP_EL2
;
2561 return CP_ACCESS_OK
;
2564 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2565 const ARMCPRegInfo
*ri
,
2568 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2571 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2572 const ARMCPRegInfo
*ri
,
2575 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2578 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2581 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2584 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2587 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2590 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2591 const ARMCPRegInfo
*ri
,
2595 * The AArch64 register view of the secure physical timer is
2596 * always accessible from EL3, and configurably accessible from
2599 switch (arm_current_el(env
)) {
2601 if (!arm_is_secure(env
)) {
2602 return CP_ACCESS_TRAP
;
2604 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2605 return CP_ACCESS_TRAP_EL3
;
2607 return CP_ACCESS_OK
;
2610 return CP_ACCESS_TRAP
;
2612 return CP_ACCESS_OK
;
2614 g_assert_not_reached();
2618 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2620 ARMCPU
*cpu
= env_archcpu(env
);
2622 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2625 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2627 CPUARMState
*env
= &cpu
->env
;
2628 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2629 ARMSecuritySpace ss
= arm_security_space(env
);
2630 /* ISTATUS && !IMASK */
2631 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2634 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2635 * It is RES0 in Secure and NonSecure state.
2637 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2638 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2639 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2643 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2644 trace_arm_gt_update_irq(timeridx
, irqstate
);
2647 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2650 * Changing security state between Root and Secure/NonSecure, which may
2651 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2652 * mask bits. Update the IRQ state accordingly.
2654 gt_update_irq(cpu
, GTIMER_VIRT
);
2655 gt_update_irq(cpu
, GTIMER_PHYS
);
2658 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2660 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2664 * Timer enabled: calculate and set current ISTATUS, irq, and
2665 * reset timer to when ISTATUS next has to change
2667 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2668 cpu
->env
.cp15
.cntvoff_el2
: 0;
2669 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2670 /* Note that this must be unsigned 64 bit arithmetic: */
2671 int istatus
= count
- offset
>= gt
->cval
;
2674 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2678 * Next transition is when (count - offset) rolls back over to 0.
2679 * If offset > count then this is when count == offset;
2680 * if offset <= count then this is when count == offset + 2^64
2681 * For the latter case we set nexttick to an "as far in future
2682 * as possible" value and let the code below handle it.
2684 if (offset
> count
) {
2687 nexttick
= UINT64_MAX
;
2691 * Next transition is when (count - offset) == cval, i.e.
2692 * when count == (cval + offset).
2693 * If that would overflow, then again we set up the next interrupt
2694 * for "as far in the future as possible" for the code below.
2696 if (uadd64_overflow(gt
->cval
, offset
, &nexttick
)) {
2697 nexttick
= UINT64_MAX
;
2701 * Note that the desired next expiry time might be beyond the
2702 * signed-64-bit range of a QEMUTimer -- in this case we just
2703 * set the timer for as far in the future as possible. When the
2704 * timer expires we will reset the timer for any remaining period.
2706 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2707 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2709 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2711 trace_arm_gt_recalc(timeridx
, nexttick
);
2713 /* Timer disabled: ISTATUS and timer output always clear */
2715 timer_del(cpu
->gt_timer
[timeridx
]);
2716 trace_arm_gt_recalc_disabled(timeridx
);
2718 gt_update_irq(cpu
, timeridx
);
2721 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2724 ARMCPU
*cpu
= env_archcpu(env
);
2726 timer_del(cpu
->gt_timer
[timeridx
]);
2729 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2731 return gt_get_countervalue(env
);
2734 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2738 switch (arm_current_el(env
)) {
2740 hcr
= arm_hcr_el2_eff(env
);
2741 if (hcr
& HCR_E2H
) {
2746 hcr
= arm_hcr_el2_eff(env
);
2747 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2753 return env
->cp15
.cntvoff_el2
;
2756 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2758 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2761 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2765 trace_arm_gt_cval_write(timeridx
, value
);
2766 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2767 gt_recalc_timer(env_archcpu(env
), timeridx
);
2770 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2773 uint64_t offset
= 0;
2777 case GTIMER_HYPVIRT
:
2778 offset
= gt_virt_cnt_offset(env
);
2782 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2783 (gt_get_countervalue(env
) - offset
));
2786 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2790 uint64_t offset
= 0;
2794 case GTIMER_HYPVIRT
:
2795 offset
= gt_virt_cnt_offset(env
);
2799 trace_arm_gt_tval_write(timeridx
, value
);
2800 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2801 sextract64(value
, 0, 32);
2802 gt_recalc_timer(env_archcpu(env
), timeridx
);
2805 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2809 ARMCPU
*cpu
= env_archcpu(env
);
2810 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2812 trace_arm_gt_ctl_write(timeridx
, value
);
2813 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2814 if ((oldval
^ value
) & 1) {
2815 /* Enable toggled */
2816 gt_recalc_timer(cpu
, timeridx
);
2817 } else if ((oldval
^ value
) & 2) {
2819 * IMASK toggled: don't need to recalculate,
2820 * just set the interrupt line based on ISTATUS
2822 trace_arm_gt_imask_toggle(timeridx
);
2823 gt_update_irq(cpu
, timeridx
);
2827 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2829 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2832 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2835 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2838 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2840 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2843 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2846 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2849 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2852 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2855 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2857 switch (arm_mmu_idx(env
)) {
2858 case ARMMMUIdx_E20_0
:
2859 case ARMMMUIdx_E20_2
:
2860 case ARMMMUIdx_E20_2_PAN
:
2867 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2869 switch (arm_mmu_idx(env
)) {
2870 case ARMMMUIdx_E20_0
:
2871 case ARMMMUIdx_E20_2
:
2872 case ARMMMUIdx_E20_2_PAN
:
2873 return GTIMER_HYPVIRT
;
2879 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2880 const ARMCPRegInfo
*ri
)
2882 int timeridx
= gt_phys_redir_timeridx(env
);
2883 return env
->cp15
.c14_timer
[timeridx
].cval
;
2886 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2889 int timeridx
= gt_phys_redir_timeridx(env
);
2890 gt_cval_write(env
, ri
, timeridx
, value
);
2893 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2894 const ARMCPRegInfo
*ri
)
2896 int timeridx
= gt_phys_redir_timeridx(env
);
2897 return gt_tval_read(env
, ri
, timeridx
);
2900 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2903 int timeridx
= gt_phys_redir_timeridx(env
);
2904 gt_tval_write(env
, ri
, timeridx
, value
);
2907 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2908 const ARMCPRegInfo
*ri
)
2910 int timeridx
= gt_phys_redir_timeridx(env
);
2911 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2914 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2917 int timeridx
= gt_phys_redir_timeridx(env
);
2918 gt_ctl_write(env
, ri
, timeridx
, value
);
2921 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2923 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2926 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2929 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2932 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2934 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2937 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2940 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2943 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2946 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2949 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2952 ARMCPU
*cpu
= env_archcpu(env
);
2953 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2955 raw_write(env
, ri
, value
);
2957 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2958 gt_update_irq(cpu
, GTIMER_VIRT
);
2959 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2960 gt_update_irq(cpu
, GTIMER_PHYS
);
2964 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2967 ARMCPU
*cpu
= env_archcpu(env
);
2969 trace_arm_gt_cntvoff_write(value
);
2970 raw_write(env
, ri
, value
);
2971 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2974 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2975 const ARMCPRegInfo
*ri
)
2977 int timeridx
= gt_virt_redir_timeridx(env
);
2978 return env
->cp15
.c14_timer
[timeridx
].cval
;
2981 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2984 int timeridx
= gt_virt_redir_timeridx(env
);
2985 gt_cval_write(env
, ri
, timeridx
, value
);
2988 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2989 const ARMCPRegInfo
*ri
)
2991 int timeridx
= gt_virt_redir_timeridx(env
);
2992 return gt_tval_read(env
, ri
, timeridx
);
2995 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2998 int timeridx
= gt_virt_redir_timeridx(env
);
2999 gt_tval_write(env
, ri
, timeridx
, value
);
3002 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
3003 const ARMCPRegInfo
*ri
)
3005 int timeridx
= gt_virt_redir_timeridx(env
);
3006 return env
->cp15
.c14_timer
[timeridx
].ctl
;
3009 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3012 int timeridx
= gt_virt_redir_timeridx(env
);
3013 gt_ctl_write(env
, ri
, timeridx
, value
);
3016 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3018 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3021 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3024 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3027 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3029 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3032 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3035 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3038 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3041 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3044 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3046 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3049 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3052 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3055 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3057 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3060 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3063 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3066 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3069 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3072 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3074 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3077 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3080 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3083 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3085 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3088 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3091 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3094 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3097 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3100 void arm_gt_ptimer_cb(void *opaque
)
3102 ARMCPU
*cpu
= opaque
;
3104 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3107 void arm_gt_vtimer_cb(void *opaque
)
3109 ARMCPU
*cpu
= opaque
;
3111 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3114 void arm_gt_htimer_cb(void *opaque
)
3116 ARMCPU
*cpu
= opaque
;
3118 gt_recalc_timer(cpu
, GTIMER_HYP
);
3121 void arm_gt_stimer_cb(void *opaque
)
3123 ARMCPU
*cpu
= opaque
;
3125 gt_recalc_timer(cpu
, GTIMER_SEC
);
3128 void arm_gt_hvtimer_cb(void *opaque
)
3130 ARMCPU
*cpu
= opaque
;
3132 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3135 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3137 ARMCPU
*cpu
= env_archcpu(env
);
3139 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3142 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3144 * Note that CNTFRQ is purely reads-as-written for the benefit
3145 * of software; writing it doesn't actually change the timer frequency.
3146 * Our reset value matches the fixed frequency we implement the timer at.
3148 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3149 .type
= ARM_CP_ALIAS
,
3150 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3151 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3153 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3154 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3155 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3156 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3157 .resetfn
= arm_gt_cntfrq_reset
,
3159 /* overall control: mostly access permissions */
3160 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3161 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3163 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3166 /* per-timer control */
3167 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3168 .secure
= ARM_CP_SECSTATE_NS
,
3169 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3170 .accessfn
= gt_ptimer_access
,
3171 .fieldoffset
= offsetoflow32(CPUARMState
,
3172 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3173 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3174 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3176 { .name
= "CNTP_CTL_S",
3177 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3178 .secure
= ARM_CP_SECSTATE_S
,
3179 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3180 .accessfn
= gt_ptimer_access
,
3181 .fieldoffset
= offsetoflow32(CPUARMState
,
3182 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3183 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3185 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3186 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3187 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3188 .accessfn
= gt_ptimer_access
,
3189 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3191 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3192 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3194 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3195 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3196 .accessfn
= gt_vtimer_access
,
3197 .fieldoffset
= offsetoflow32(CPUARMState
,
3198 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3199 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3200 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3202 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3203 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3204 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3205 .accessfn
= gt_vtimer_access
,
3206 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3208 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3209 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3211 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3212 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3213 .secure
= ARM_CP_SECSTATE_NS
,
3214 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3215 .accessfn
= gt_ptimer_access
,
3216 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3218 { .name
= "CNTP_TVAL_S",
3219 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3220 .secure
= ARM_CP_SECSTATE_S
,
3221 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3222 .accessfn
= gt_ptimer_access
,
3223 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3225 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3226 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3227 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3228 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3229 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3231 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3232 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3233 .accessfn
= gt_vtimer_access
,
3234 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3236 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3238 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3239 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3240 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3242 /* The counter itself */
3243 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3244 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3245 .accessfn
= gt_pct_access
,
3246 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3248 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3249 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3250 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3251 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3253 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3254 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3255 .accessfn
= gt_vct_access
,
3256 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3258 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3259 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3260 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3261 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3263 /* Comparison value, indicating when the timer goes off */
3264 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3265 .secure
= ARM_CP_SECSTATE_NS
,
3267 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3268 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3269 .accessfn
= gt_ptimer_access
,
3270 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3271 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3273 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3274 .secure
= ARM_CP_SECSTATE_S
,
3276 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3278 .accessfn
= gt_ptimer_access
,
3279 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3281 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3282 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3285 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3286 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3287 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3288 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3290 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3292 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3293 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3294 .accessfn
= gt_vtimer_access
,
3295 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3296 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3298 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3299 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3302 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3303 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3304 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3305 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3308 * Secure timer -- this is actually restricted to only EL3
3309 * and configurably Secure-EL1 via the accessfn.
3311 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3312 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3313 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3314 .accessfn
= gt_stimer_access
,
3315 .readfn
= gt_sec_tval_read
,
3316 .writefn
= gt_sec_tval_write
,
3317 .resetfn
= gt_sec_timer_reset
,
3319 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3320 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3321 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3322 .accessfn
= gt_stimer_access
,
3323 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3325 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3327 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3328 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3329 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3330 .accessfn
= gt_stimer_access
,
3331 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3332 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3336 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3339 if (arm_current_el(env
) == 1) {
3340 /* This must be a FEAT_NV access */
3341 /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
3342 return CP_ACCESS_OK
;
3344 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3345 return CP_ACCESS_TRAP
;
3347 return CP_ACCESS_OK
;
3353 * In user-mode most of the generic timer registers are inaccessible
3354 * however modern kernels (4.12+) allow access to cntvct_el0
3357 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3359 ARMCPU
*cpu
= env_archcpu(env
);
3362 * Currently we have no support for QEMUTimer in linux-user so we
3363 * can't call gt_get_countervalue(env), instead we directly
3364 * call the lower level functions.
3366 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3369 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3370 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3371 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3372 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3373 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3374 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3376 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3377 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3378 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3379 .readfn
= gt_virt_cnt_read
,
3385 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3387 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3388 raw_write(env
, ri
, value
);
3389 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3390 raw_write(env
, ri
, value
& 0xfffff6ff);
3392 raw_write(env
, ri
, value
& 0xfffff1ff);
3396 #ifndef CONFIG_USER_ONLY
3397 /* get_phys_addr() isn't present for user-mode-only targets */
3399 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3404 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3405 * Secure EL1 (which can only happen if EL3 is AArch64).
3406 * They are simply UNDEF if executed from NS EL1.
3407 * They function normally from EL2 or EL3.
3409 if (arm_current_el(env
) == 1) {
3410 if (arm_is_secure_below_el3(env
)) {
3411 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3412 return CP_ACCESS_TRAP_EL2
;
3414 return CP_ACCESS_TRAP_EL3
;
3416 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3419 return CP_ACCESS_OK
;
3423 static int par_el1_shareability(GetPhysAddrResult
*res
)
3426 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3427 * memory -- see pseudocode PAREncodeShareability().
3429 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3430 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3433 return res
->cacheattrs
.shareability
;
3436 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3437 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3438 ARMSecuritySpace ss
)
3442 bool format64
= false;
3443 ARMMMUFaultInfo fi
= {};
3444 GetPhysAddrResult res
= {};
3447 * I_MXTJT: Granule protection checks are not performed on the final address
3448 * of a successful translation.
3450 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3454 * ATS operations only do S1 or S1+S2 translations, so we never
3455 * have to deal with the ARMCacheAttrs format for S2 only.
3457 assert(!res
.cacheattrs
.is_s2_format
);
3461 * Some kinds of translation fault must cause exceptions rather
3462 * than being reported in the PAR.
3464 int current_el
= arm_current_el(env
);
3466 uint32_t syn
, fsr
, fsc
;
3467 bool take_exc
= false;
3469 if (fi
.s1ptw
&& current_el
== 1
3470 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3472 * Synchronous stage 2 fault on an access made as part of the
3473 * translation table walk for AT S1E0* or AT S1E1* insn
3474 * executed from NS EL1. If this is a synchronous external abort
3475 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3476 * to EL3. Otherwise the fault is taken as an exception to EL2,
3477 * and HPFAR_EL2 holds the faulting IPA.
3479 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3480 (env
->cp15
.scr_el3
& SCR_EA
)) {
3483 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3484 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3485 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3490 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3492 * Synchronous external aborts during a translation table walk
3493 * are taken as Data Abort exceptions.
3496 if (current_el
== 3) {
3502 target_el
= exception_target_el(env
);
3508 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3509 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3510 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3511 fsr
= arm_fi_to_lfsc(&fi
);
3512 fsc
= extract32(fsr
, 0, 6);
3514 fsr
= arm_fi_to_sfsc(&fi
);
3518 * Report exception with ESR indicating a fault due to a
3519 * translation table walk for a cache maintenance instruction.
3521 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3522 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3523 env
->exception
.vaddress
= value
;
3524 env
->exception
.fsr
= fsr
;
3525 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3531 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3534 * * TTBCR.EAE determines whether the result is returned using the
3535 * 32-bit or the 64-bit PAR format
3536 * * Instructions executed in Hyp mode always use the 64bit format
3538 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3539 * * The Non-secure TTBCR.EAE bit is set to 1
3540 * * The implementation includes EL2, and the value of HCR.VM is 1
3542 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3544 * ATS1Hx always uses the 64bit format.
3546 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3548 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3549 if (mmu_idx
== ARMMMUIdx_E10_0
||
3550 mmu_idx
== ARMMMUIdx_E10_1
||
3551 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3552 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3554 format64
|= arm_current_el(env
) == 2;
3560 /* Create a 64-bit PAR */
3561 par64
= (1 << 11); /* LPAE bit always set */
3563 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3564 if (!res
.f
.attrs
.secure
) {
3565 par64
|= (1 << 9); /* NS */
3567 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3568 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3570 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3573 par64
|= (fsr
& 0x3f) << 1; /* FS */
3575 par64
|= (1 << 9); /* S */
3578 par64
|= (1 << 8); /* PTW */
3583 * fsr is a DFSR/IFSR value for the short descriptor
3584 * translation table format (with WnR always clear).
3585 * Convert it to a 32-bit PAR.
3588 /* We do not set any attribute bits in the PAR */
3589 if (res
.f
.lg_page_size
== 24
3590 && arm_feature(env
, ARM_FEATURE_V7
)) {
3591 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3593 par64
= res
.f
.phys_addr
& 0xfffff000;
3595 if (!res
.f
.attrs
.secure
) {
3596 par64
|= (1 << 9); /* NS */
3599 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3601 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3602 ((fsr
& 0xf) << 1) | 1;
3607 #endif /* CONFIG_TCG */
3609 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3612 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3615 int el
= arm_current_el(env
);
3616 ARMSecuritySpace ss
= arm_security_space(env
);
3618 switch (ri
->opc2
& 6) {
3620 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3623 mmu_idx
= ARMMMUIdx_E3
;
3626 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3629 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3630 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3632 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3636 g_assert_not_reached();
3640 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3643 mmu_idx
= ARMMMUIdx_E10_0
;
3646 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3647 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3650 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3653 g_assert_not_reached();
3657 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3658 mmu_idx
= ARMMMUIdx_E10_1
;
3659 ss
= ARMSS_NonSecure
;
3662 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3663 mmu_idx
= ARMMMUIdx_E10_0
;
3664 ss
= ARMSS_NonSecure
;
3667 g_assert_not_reached();
3670 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3672 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3674 /* Handled by hardware accelerator. */
3675 g_assert_not_reached();
3676 #endif /* CONFIG_TCG */
3679 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3683 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3686 /* There is no SecureEL2 for AArch32. */
3687 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3690 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3692 /* Handled by hardware accelerator. */
3693 g_assert_not_reached();
3694 #endif /* CONFIG_TCG */
3697 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3701 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3702 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3703 * only happen when executing at EL3 because that combination also causes an
3704 * illegal exception return. We don't need to check FEAT_RME either, because
3705 * scr_write() ensures that the NSE bit is not set otherwise.
3707 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3708 return CP_ACCESS_TRAP
;
3710 return CP_ACCESS_OK
;
3713 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3716 if (arm_current_el(env
) == 3 &&
3717 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3718 return CP_ACCESS_TRAP
;
3720 return at_e012_access(env
, ri
, isread
);
3723 static CPAccessResult
at_s1e01_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3726 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_AT
)) {
3727 return CP_ACCESS_TRAP_EL2
;
3729 return at_e012_access(env
, ri
, isread
);
3732 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3736 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3738 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3739 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3741 switch (ri
->opc2
& 6) {
3744 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3745 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3746 mmu_idx
= regime_e20
?
3747 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3749 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3752 case 4: /* AT S1E2R, AT S1E2W */
3753 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3755 case 6: /* AT S1E3R, AT S1E3W */
3756 mmu_idx
= ARMMMUIdx_E3
;
3759 g_assert_not_reached();
3762 case 2: /* AT S1E0R, AT S1E0W */
3763 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3765 case 4: /* AT S12E1R, AT S12E1W */
3766 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3768 case 6: /* AT S12E0R, AT S12E0W */
3769 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3772 g_assert_not_reached();
3775 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3776 mmu_idx
, arm_security_space(env
));
3778 /* Handled by hardware accelerator. */
3779 g_assert_not_reached();
3780 #endif /* CONFIG_TCG */
3784 /* Return basic MPU access permission bits. */
3785 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3792 for (i
= 0; i
< 16; i
+= 2) {
3793 ret
|= (val
>> i
) & mask
;
3799 /* Pad basic MPU access permission bits to extended format. */
3800 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3807 for (i
= 0; i
< 16; i
+= 2) {
3808 ret
|= (val
& mask
) << i
;
3814 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3817 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3820 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3822 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3825 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3828 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3831 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3833 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3836 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3838 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3844 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3848 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3851 ARMCPU
*cpu
= env_archcpu(env
);
3852 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3858 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3859 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3863 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3866 ARMCPU
*cpu
= env_archcpu(env
);
3867 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3869 if (value
>= nrgs
) {
3870 qemu_log_mask(LOG_GUEST_ERROR
,
3871 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3872 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3876 raw_write(env
, ri
, value
);
3879 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3882 ARMCPU
*cpu
= env_archcpu(env
);
3884 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3885 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3888 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3890 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3893 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3896 ARMCPU
*cpu
= env_archcpu(env
);
3898 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3899 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3902 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3904 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3907 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3910 ARMCPU
*cpu
= env_archcpu(env
);
3913 * Ignore writes that would select not implemented region.
3914 * This is architecturally UNPREDICTABLE.
3916 if (value
>= cpu
->pmsav7_dregion
) {
3920 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3923 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3926 ARMCPU
*cpu
= env_archcpu(env
);
3928 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3929 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3932 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3934 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3937 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3940 ARMCPU
*cpu
= env_archcpu(env
);
3942 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3943 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3946 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3948 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3951 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3956 ARMCPU
*cpu
= env_archcpu(env
);
3958 /* Ignore writes to unimplemented regions */
3959 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3960 value
&= MAKE_64BIT_MASK(0, rmax
);
3962 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3964 /* Register alias is only valid for first 32 indexes */
3965 for (n
= 0; n
< rmax
; ++n
) {
3966 bit
= extract32(value
, n
, 1);
3967 env
->pmsav8
.hprlar
[n
] = deposit32(
3968 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3972 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3975 uint32_t result
= 0x0;
3976 ARMCPU
*cpu
= env_archcpu(env
);
3978 /* Register alias is only valid for first 32 indexes */
3979 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3980 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3981 result
|= (0x1 << n
);
3987 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3990 ARMCPU
*cpu
= env_archcpu(env
);
3993 * Ignore writes that would select not implemented region.
3994 * This is architecturally UNPREDICTABLE.
3996 if (value
>= cpu
->pmsav8r_hdregion
) {
4000 env
->pmsav8
.hprselr
= value
;
4003 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4006 ARMCPU
*cpu
= env_archcpu(env
);
4007 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4008 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4010 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4013 if (index
>= cpu
->pmsav8r_hdregion
) {
4016 if (ri
->opc2
& 0x1) {
4017 env
->pmsav8
.hprlar
[index
] = value
;
4019 env
->pmsav8
.hprbar
[index
] = value
;
4022 if (index
>= cpu
->pmsav7_dregion
) {
4025 if (ri
->opc2
& 0x1) {
4026 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
4028 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
4033 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4035 ARMCPU
*cpu
= env_archcpu(env
);
4036 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4037 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4040 if (index
>= cpu
->pmsav8r_hdregion
) {
4043 if (ri
->opc2
& 0x1) {
4044 return env
->pmsav8
.hprlar
[index
];
4046 return env
->pmsav8
.hprbar
[index
];
4049 if (index
>= cpu
->pmsav7_dregion
) {
4052 if (ri
->opc2
& 0x1) {
4053 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4055 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4060 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4062 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4063 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4064 .accessfn
= access_tvm_trvm
,
4065 .readfn
= prbar_read
, .writefn
= prbar_write
},
4067 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4068 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4069 .accessfn
= access_tvm_trvm
,
4070 .readfn
= prlar_read
, .writefn
= prlar_write
},
4071 { .name
= "PRSELR", .resetvalue
= 0,
4072 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4073 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4074 .writefn
= prselr_write
,
4075 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4076 { .name
= "HPRBAR", .resetvalue
= 0,
4077 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4078 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4079 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4081 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4082 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4083 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4084 { .name
= "HPRSELR", .resetvalue
= 0,
4085 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4087 .writefn
= hprselr_write
,
4088 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4090 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4091 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4092 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4095 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4097 * Reset for all these registers is handled in arm_cpu_reset(),
4098 * because the PMSAv7 is also used by M-profile CPUs, which do
4099 * not register cpregs but still need the state to be reset.
4101 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4102 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4103 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4104 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4105 .resetfn
= arm_cp_reset_ignore
},
4106 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4107 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4108 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4109 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4110 .resetfn
= arm_cp_reset_ignore
},
4111 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4112 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4113 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4114 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4115 .resetfn
= arm_cp_reset_ignore
},
4116 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4118 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4119 .writefn
= pmsav7_rgnr_write
,
4120 .resetfn
= arm_cp_reset_ignore
},
4123 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4124 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4125 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4126 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4127 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4128 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4129 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4130 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4131 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4132 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4134 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4136 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4138 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4140 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4142 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4143 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4145 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4146 /* Protection region base and size registers */
4147 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4148 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4149 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4150 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4151 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4152 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4153 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4154 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4155 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4156 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4157 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4158 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4159 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4160 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4161 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4162 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4163 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4164 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4165 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4166 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4167 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4168 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4169 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4173 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4176 ARMCPU
*cpu
= env_archcpu(env
);
4178 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4179 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4181 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4182 * using Long-descriptor translation table format
4184 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4185 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4187 * In an implementation that includes the Security Extensions
4188 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4189 * Short-descriptor translation table format.
4191 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4197 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4199 * With LPAE the TTBCR could result in a change of ASID
4200 * via the TTBCR.A1 bit, so do a TLB flush.
4202 tlb_flush(CPU(cpu
));
4204 raw_write(env
, ri
, value
);
4207 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4210 ARMCPU
*cpu
= env_archcpu(env
);
4212 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4213 tlb_flush(CPU(cpu
));
4214 raw_write(env
, ri
, value
);
4217 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4220 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4221 if (cpreg_field_is_64bit(ri
) &&
4222 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4223 ARMCPU
*cpu
= env_archcpu(env
);
4224 tlb_flush(CPU(cpu
));
4226 raw_write(env
, ri
, value
);
4229 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4233 * If we are running with E2&0 regime, then an ASID is active.
4234 * Flush if that might be changing. Note we're not checking
4235 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4236 * holds the active ASID, only checking the field that might.
4238 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4239 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4240 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4241 ARMMMUIdxBit_E20_2_PAN
|
4243 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4245 raw_write(env
, ri
, value
);
4248 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4251 ARMCPU
*cpu
= env_archcpu(env
);
4252 CPUState
*cs
= CPU(cpu
);
4255 * A change in VMID to the stage2 page table (Stage2) invalidates
4256 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4258 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4259 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4261 raw_write(env
, ri
, value
);
4264 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4265 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4266 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4267 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4268 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4269 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4270 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4271 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4272 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4273 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4274 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4275 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4276 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4277 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4278 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4279 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4281 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4285 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4286 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4287 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4288 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4290 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4291 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4292 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4293 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4294 .fgt
= FGT_TTBR0_EL1
,
4295 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4296 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4297 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4298 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4299 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4300 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4301 .fgt
= FGT_TTBR1_EL1
,
4302 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4303 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4304 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4305 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4306 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4307 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4309 .writefn
= vmsa_tcr_el12_write
,
4310 .raw_writefn
= raw_write
,
4312 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4313 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4314 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4315 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4316 .raw_writefn
= raw_write
,
4317 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4318 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4322 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4323 * qemu tlbs nor adjusting cached masks.
4325 static const ARMCPRegInfo ttbcr2_reginfo
= {
4326 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4327 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4328 .type
= ARM_CP_ALIAS
,
4329 .bank_fieldoffsets
= {
4330 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4331 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4335 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4338 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4339 /* The OS_TYPE bit in this register changes the reported CPUID! */
4340 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4341 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4344 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4347 env
->cp15
.c15_threadid
= value
& 0xffff;
4350 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4353 /* Wait-for-interrupt (deprecated) */
4354 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4357 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4361 * On OMAP there are registers indicating the max/min index of dcache lines
4362 * containing a dirty line; cache flush operations have to reset these.
4364 env
->cp15
.c15_i_max
= 0x000;
4365 env
->cp15
.c15_i_min
= 0xff0;
4368 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4369 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4370 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4371 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4373 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4374 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4375 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4377 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4378 .writefn
= omap_ticonfig_write
},
4379 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4381 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4382 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4383 .access
= PL1_RW
, .resetvalue
= 0xff0,
4384 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4385 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4387 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4388 .writefn
= omap_threadid_write
},
4389 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4390 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4391 .type
= ARM_CP_NO_RAW
,
4392 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4394 * TODO: Peripheral port remap register:
4395 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4396 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4399 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4400 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4401 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4402 .writefn
= omap_cachemaint_write
},
4403 { .name
= "C9", .cp
= 15, .crn
= 9,
4404 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4405 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4408 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4411 env
->cp15
.c15_cpar
= value
& 0x3fff;
4414 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4415 { .name
= "XSCALE_CPAR",
4416 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4417 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4418 .writefn
= xscale_cpar_write
, },
4419 { .name
= "XSCALE_AUXCR",
4420 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4421 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4424 * XScale specific cache-lockdown: since we have no cache we NOP these
4425 * and hope the guest does not really rely on cache behaviour.
4427 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4428 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4429 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4430 { .name
= "XSCALE_UNLOCK_ICACHE",
4431 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4432 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4433 { .name
= "XSCALE_DCACHE_LOCK",
4434 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4435 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4436 { .name
= "XSCALE_UNLOCK_DCACHE",
4437 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4438 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4441 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4443 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4444 * implementation of this implementation-defined space.
4445 * Ideally this should eventually disappear in favour of actually
4446 * implementing the correct behaviour for all cores.
4448 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4449 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4451 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4455 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4456 /* Cache status: RAZ because we have no cache so it's always clean */
4457 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4458 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4462 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4463 /* We never have a block transfer operation in progress */
4464 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4465 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4467 /* The cache ops themselves: these all NOP for QEMU */
4468 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4469 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4470 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4471 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4472 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4473 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4474 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4475 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4476 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4477 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4478 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4479 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4482 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4484 * The cache test-and-clean instructions always return (1 << 30)
4485 * to indicate that there are no dirty cache lines.
4487 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4488 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4489 .resetvalue
= (1 << 30) },
4490 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4491 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4492 .resetvalue
= (1 << 30) },
4495 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4496 /* Ignore ReadBuffer accesses */
4497 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4498 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4499 .access
= PL1_RW
, .resetvalue
= 0,
4500 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4503 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4505 unsigned int cur_el
= arm_current_el(env
);
4507 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4508 return env
->cp15
.vpidr_el2
;
4510 return raw_read(env
, ri
);
4513 static uint64_t mpidr_read_val(CPUARMState
*env
)
4515 ARMCPU
*cpu
= env_archcpu(env
);
4516 uint64_t mpidr
= cpu
->mp_affinity
;
4518 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4519 mpidr
|= (1U << 31);
4521 * Cores which are uniprocessor (non-coherent)
4522 * but still implement the MP extensions set
4523 * bit 30. (For instance, Cortex-R5).
4525 if (cpu
->mp_is_up
) {
4526 mpidr
|= (1u << 30);
4532 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4534 unsigned int cur_el
= arm_current_el(env
);
4536 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4537 return env
->cp15
.vmpidr_el2
;
4539 return mpidr_read_val(env
);
4542 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4544 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4545 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4546 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4547 .fgt
= FGT_AMAIR_EL1
,
4548 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4549 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4550 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4551 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4552 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4553 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4554 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4555 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4556 offsetof(CPUARMState
, cp15
.par_ns
)} },
4557 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4558 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4559 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4560 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4561 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4562 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4563 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4564 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4565 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4566 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4567 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4568 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4571 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4573 return vfp_get_fpcr(env
);
4576 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4579 vfp_set_fpcr(env
, value
);
4582 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4584 return vfp_get_fpsr(env
);
4587 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4590 vfp_set_fpsr(env
, value
);
4593 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4596 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4597 return CP_ACCESS_TRAP
;
4599 return CP_ACCESS_OK
;
4602 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4605 env
->daif
= value
& PSTATE_DAIF
;
4608 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4610 return env
->pstate
& PSTATE_PAN
;
4613 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4616 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4619 static const ARMCPRegInfo pan_reginfo
= {
4620 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4621 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4622 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4623 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4626 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4628 return env
->pstate
& PSTATE_UAO
;
4631 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4634 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4637 static const ARMCPRegInfo uao_reginfo
= {
4638 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4639 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4640 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4641 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4644 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4646 return env
->pstate
& PSTATE_DIT
;
4649 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4652 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4655 static const ARMCPRegInfo dit_reginfo
= {
4656 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4657 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4658 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4659 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4662 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4664 return env
->pstate
& PSTATE_SSBS
;
4667 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4670 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4673 static const ARMCPRegInfo ssbs_reginfo
= {
4674 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4675 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4676 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4677 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4680 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4681 const ARMCPRegInfo
*ri
,
4684 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4685 switch (arm_current_el(env
)) {
4687 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4688 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4689 return CP_ACCESS_TRAP
;
4693 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4694 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4695 return CP_ACCESS_TRAP_EL2
;
4699 return CP_ACCESS_OK
;
4702 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4704 /* Cache invalidate/clean to Point of Unification... */
4705 switch (arm_current_el(env
)) {
4707 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4708 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4709 return CP_ACCESS_TRAP
;
4713 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4714 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4715 return CP_ACCESS_TRAP_EL2
;
4719 return CP_ACCESS_OK
;
4722 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4725 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4728 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4731 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4735 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4736 * Page D4-1736 (DDI0487A.b)
4739 static int vae1_tlbmask(CPUARMState
*env
)
4741 uint64_t hcr
= arm_hcr_el2_eff(env
);
4744 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4745 mask
= ARMMMUIdxBit_E20_2
|
4746 ARMMMUIdxBit_E20_2_PAN
|
4749 mask
= ARMMMUIdxBit_E10_1
|
4750 ARMMMUIdxBit_E10_1_PAN
|
4756 static int vae2_tlbmask(CPUARMState
*env
)
4758 uint64_t hcr
= arm_hcr_el2_eff(env
);
4761 if (hcr
& HCR_E2H
) {
4762 mask
= ARMMMUIdxBit_E20_2
|
4763 ARMMMUIdxBit_E20_2_PAN
|
4766 mask
= ARMMMUIdxBit_E2
;
4771 /* Return 56 if TBI is enabled, 64 otherwise. */
4772 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4775 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4776 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4777 int select
= extract64(addr
, 55, 1);
4779 return (tbi
>> select
) & 1 ? 56 : 64;
4782 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4784 uint64_t hcr
= arm_hcr_el2_eff(env
);
4787 /* Only the regime of the mmu_idx below is significant. */
4788 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4789 mmu_idx
= ARMMMUIdx_E20_0
;
4791 mmu_idx
= ARMMMUIdx_E10_0
;
4794 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4797 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4799 uint64_t hcr
= arm_hcr_el2_eff(env
);
4803 * Only the regime of the mmu_idx below is significant.
4804 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4807 if (hcr
& HCR_E2H
) {
4808 mmu_idx
= ARMMMUIdx_E20_2
;
4810 mmu_idx
= ARMMMUIdx_E2
;
4813 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4816 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4819 CPUState
*cs
= env_cpu(env
);
4820 int mask
= vae1_tlbmask(env
);
4822 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4825 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4828 CPUState
*cs
= env_cpu(env
);
4829 int mask
= vae1_tlbmask(env
);
4831 if (tlb_force_broadcast(env
)) {
4832 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4834 tlb_flush_by_mmuidx(cs
, mask
);
4838 static int e2_tlbmask(CPUARMState
*env
)
4840 return (ARMMMUIdxBit_E20_0
|
4841 ARMMMUIdxBit_E20_2
|
4842 ARMMMUIdxBit_E20_2_PAN
|
4846 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4849 CPUState
*cs
= env_cpu(env
);
4850 int mask
= alle1_tlbmask(env
);
4852 tlb_flush_by_mmuidx(cs
, mask
);
4855 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4858 CPUState
*cs
= env_cpu(env
);
4859 int mask
= e2_tlbmask(env
);
4861 tlb_flush_by_mmuidx(cs
, mask
);
4864 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4867 ARMCPU
*cpu
= env_archcpu(env
);
4868 CPUState
*cs
= CPU(cpu
);
4870 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4873 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4876 CPUState
*cs
= env_cpu(env
);
4877 int mask
= alle1_tlbmask(env
);
4879 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4882 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4885 CPUState
*cs
= env_cpu(env
);
4886 int mask
= e2_tlbmask(env
);
4888 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4891 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4894 CPUState
*cs
= env_cpu(env
);
4896 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4899 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4903 * Invalidate by VA, EL2
4904 * Currently handles both VAE2 and VALE2, since we don't support
4905 * flush-last-level-only.
4907 CPUState
*cs
= env_cpu(env
);
4908 int mask
= vae2_tlbmask(env
);
4909 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4910 int bits
= vae2_tlbbits(env
, pageaddr
);
4912 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4915 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4919 * Invalidate by VA, EL3
4920 * Currently handles both VAE3 and VALE3, since we don't support
4921 * flush-last-level-only.
4923 ARMCPU
*cpu
= env_archcpu(env
);
4924 CPUState
*cs
= CPU(cpu
);
4925 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4927 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4930 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4933 CPUState
*cs
= env_cpu(env
);
4934 int mask
= vae1_tlbmask(env
);
4935 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4936 int bits
= vae1_tlbbits(env
, pageaddr
);
4938 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4941 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4945 * Invalidate by VA, EL1&0 (AArch64 version).
4946 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4947 * since we don't support flush-for-specific-ASID-only or
4948 * flush-last-level-only.
4950 CPUState
*cs
= env_cpu(env
);
4951 int mask
= vae1_tlbmask(env
);
4952 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4953 int bits
= vae1_tlbbits(env
, pageaddr
);
4955 if (tlb_force_broadcast(env
)) {
4956 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4958 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4962 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4965 CPUState
*cs
= env_cpu(env
);
4966 int mask
= vae2_tlbmask(env
);
4967 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4968 int bits
= vae2_tlbbits(env
, pageaddr
);
4970 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4973 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4976 CPUState
*cs
= env_cpu(env
);
4977 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4978 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4980 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4981 ARMMMUIdxBit_E3
, bits
);
4984 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4987 * The MSB of value is the NS field, which only applies if SEL2
4988 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4991 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4992 && arm_is_secure_below_el3(env
)
4993 ? ARMMMUIdxBit_Stage2_S
4994 : ARMMMUIdxBit_Stage2
);
4997 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5000 CPUState
*cs
= env_cpu(env
);
5001 int mask
= ipas2e1_tlbmask(env
, value
);
5002 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5004 if (tlb_force_broadcast(env
)) {
5005 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5007 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
5011 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5014 CPUState
*cs
= env_cpu(env
);
5015 int mask
= ipas2e1_tlbmask(env
, value
);
5016 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5018 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5021 #ifdef TARGET_AARCH64
5027 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
5030 * Note that the TLBI range TG field encoding differs from both
5031 * TG0 and TG1 encodings.
5045 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5048 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5049 /* Extract one bit to represent the va selector in use. */
5050 uint64_t select
= sextract64(value
, 36, 1);
5051 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5052 TLBIRange ret
= { };
5053 ARMGranuleSize gran
;
5055 page_size_granule
= extract64(value
, 46, 2);
5056 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5058 /* The granule encoded in value must match the granule in use. */
5059 if (gran
!= param
.gran
) {
5060 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5065 page_shift
= arm_granule_bits(gran
);
5066 num
= extract64(value
, 39, 5);
5067 scale
= extract64(value
, 44, 2);
5068 exponent
= (5 * scale
) + 1;
5070 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5073 ret
.base
= sextract64(value
, 0, 37);
5075 ret
.base
= extract64(value
, 0, 37);
5079 * With DS=1, BaseADDR is always shifted 16 so that it is able
5080 * to address all 52 va bits. The input address is perforce
5081 * aligned on a 64k boundary regardless of translation granule.
5085 ret
.base
<<= page_shift
;
5090 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5091 int idxmap
, bool synced
)
5093 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5097 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5098 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5101 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5107 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5108 range
.length
, idxmap
, bits
);
5112 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5113 const ARMCPRegInfo
*ri
,
5117 * Invalidate by VA range, EL1&0.
5118 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5119 * since we don't support flush-for-specific-ASID-only or
5120 * flush-last-level-only.
5123 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5124 tlb_force_broadcast(env
));
5127 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5128 const ARMCPRegInfo
*ri
,
5132 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5133 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5134 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5135 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5136 * shareable specific flushes.
5139 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5142 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5143 const ARMCPRegInfo
*ri
,
5147 * Invalidate by VA range, EL2.
5148 * Currently handles all of RVAE2 and RVALE2,
5149 * since we don't support flush-for-specific-ASID-only or
5150 * flush-last-level-only.
5153 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5154 tlb_force_broadcast(env
));
5159 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5160 const ARMCPRegInfo
*ri
,
5164 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5165 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5166 * since we don't support flush-for-specific-ASID-only,
5167 * flush-last-level-only or inner/outer shareable specific flushes.
5170 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5174 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5175 const ARMCPRegInfo
*ri
,
5179 * Invalidate by VA range, EL3.
5180 * Currently handles all of RVAE3 and RVALE3,
5181 * since we don't support flush-for-specific-ASID-only or
5182 * flush-last-level-only.
5185 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5188 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5189 const ARMCPRegInfo
*ri
,
5193 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5194 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5195 * since we don't support flush-for-specific-ASID-only,
5196 * flush-last-level-only or inner/outer specific flushes.
5199 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5202 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5205 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5206 tlb_force_broadcast(env
));
5209 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5210 const ARMCPRegInfo
*ri
,
5213 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5217 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5220 int cur_el
= arm_current_el(env
);
5223 uint64_t hcr
= arm_hcr_el2_eff(env
);
5226 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5227 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5228 return CP_ACCESS_TRAP_EL2
;
5231 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5232 return CP_ACCESS_TRAP
;
5234 if (hcr
& HCR_TDZ
) {
5235 return CP_ACCESS_TRAP_EL2
;
5238 } else if (hcr
& HCR_TDZ
) {
5239 return CP_ACCESS_TRAP_EL2
;
5242 return CP_ACCESS_OK
;
5245 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5247 ARMCPU
*cpu
= env_archcpu(env
);
5248 int dzp_bit
= 1 << 4;
5250 /* DZP indicates whether DC ZVA access is allowed */
5251 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5254 return cpu
->dcz_blocksize
| dzp_bit
;
5257 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5260 if (!(env
->pstate
& PSTATE_SP
)) {
5262 * Access to SP_EL0 is undefined if it's being used as
5263 * the stack pointer.
5265 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5267 return CP_ACCESS_OK
;
5270 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5272 return env
->pstate
& PSTATE_SP
;
5275 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5277 update_spsel(env
, val
);
5280 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5283 ARMCPU
*cpu
= env_archcpu(env
);
5285 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5286 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5290 /* ??? Lots of these bits are not implemented. */
5292 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5293 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5294 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5296 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5297 SCTLR_ATA0
| SCTLR_ATA
);
5301 if (raw_read(env
, ri
) == value
) {
5303 * Skip the TLB flush if nothing actually changed; Linux likes
5304 * to do a lot of pointless SCTLR writes.
5309 raw_write(env
, ri
, value
);
5311 /* This may enable/disable the MMU, so do a TLB flush. */
5312 tlb_flush(CPU(cpu
));
5314 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5316 * Normally we would always end the TB on an SCTLR write; see the
5317 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5318 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5319 * of hflags from the translator, so do it here.
5321 arm_rebuild_hflags(env
);
5325 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5329 * Some MDCR_EL3 bits affect whether PMU counters are running:
5330 * if we are trying to change any of those then we must
5331 * bracket this update with PMU start/finish calls.
5333 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5338 env
->cp15
.mdcr_el3
= value
;
5344 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5347 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5348 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5351 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5355 * Some MDCR_EL2 bits affect whether PMU counters are running:
5356 * if we are trying to change any of those then we must
5357 * bracket this update with PMU start/finish calls.
5359 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5364 env
->cp15
.mdcr_el2
= value
;
5370 static CPAccessResult
access_nv1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5373 if (arm_current_el(env
) == 1) {
5374 uint64_t hcr_nv
= arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
| HCR_NV2
);
5376 if (hcr_nv
== (HCR_NV
| HCR_NV1
)) {
5377 return CP_ACCESS_TRAP_EL2
;
5380 return CP_ACCESS_OK
;
5383 #ifdef CONFIG_USER_ONLY
5385 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5386 * code to get around W^X restrictions, where one region is writable and the
5387 * other is executable.
5389 * Since the executable region is never written to we cannot detect code
5390 * changes when running in user mode, and rely on the emulated JIT telling us
5391 * that the code has changed by executing this instruction.
5393 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5396 uint64_t icache_line_mask
, start_address
, end_address
;
5399 cpu
= env_archcpu(env
);
5401 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5402 start_address
= value
& ~icache_line_mask
;
5403 end_address
= value
| icache_line_mask
;
5407 tb_invalidate_phys_range(start_address
, end_address
);
5413 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5415 * Minimal set of EL0-visible registers. This will need to be expanded
5416 * significantly for system emulation of AArch64 CPUs.
5418 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5419 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5420 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5421 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5422 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5423 .type
= ARM_CP_NO_RAW
,
5424 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5425 .fieldoffset
= offsetof(CPUARMState
, daif
),
5426 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5427 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5428 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5429 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5430 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5431 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5432 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5433 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5434 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5435 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5436 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5437 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5438 .fgt
= FGT_DCZID_EL0
,
5439 .readfn
= aa64_dczid_read
},
5440 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5441 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5442 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5443 #ifndef CONFIG_USER_ONLY
5444 /* Avoid overhead of an access check that always passes in user-mode */
5445 .accessfn
= aa64_zva_access
,
5449 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5450 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5451 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5453 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5454 * don't emulate caches.
5456 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5457 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5458 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5459 .fgt
= FGT_ICIALLUIS
,
5460 .accessfn
= access_ticab
},
5461 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5462 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5463 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5465 .accessfn
= access_tocu
},
5466 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5467 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5470 .accessfn
= access_tocu
,
5471 #ifdef CONFIG_USER_ONLY
5472 .type
= ARM_CP_NO_RAW
,
5473 .writefn
= ic_ivau_write
5478 /* Cache ops: all NOPs since we don't emulate caches */
5479 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5480 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5481 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5483 .type
= ARM_CP_NOP
},
5484 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5485 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5487 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5488 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5489 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5490 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5492 .accessfn
= aa64_cacheop_poc_access
},
5493 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5494 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5496 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5497 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5498 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5499 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5501 .accessfn
= access_tocu
},
5502 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5503 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5504 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5506 .accessfn
= aa64_cacheop_poc_access
},
5507 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5508 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5510 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5511 /* TLBI operations */
5512 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5513 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5514 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5515 .fgt
= FGT_TLBIVMALLE1IS
,
5516 .writefn
= tlbi_aa64_vmalle1is_write
},
5517 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5518 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5519 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5520 .fgt
= FGT_TLBIVAE1IS
,
5521 .writefn
= tlbi_aa64_vae1is_write
},
5522 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5523 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5524 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5525 .fgt
= FGT_TLBIASIDE1IS
,
5526 .writefn
= tlbi_aa64_vmalle1is_write
},
5527 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5528 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5529 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5530 .fgt
= FGT_TLBIVAAE1IS
,
5531 .writefn
= tlbi_aa64_vae1is_write
},
5532 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5533 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5534 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5535 .fgt
= FGT_TLBIVALE1IS
,
5536 .writefn
= tlbi_aa64_vae1is_write
},
5537 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5538 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5539 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5540 .fgt
= FGT_TLBIVAALE1IS
,
5541 .writefn
= tlbi_aa64_vae1is_write
},
5542 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5543 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5544 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5545 .fgt
= FGT_TLBIVMALLE1
,
5546 .writefn
= tlbi_aa64_vmalle1_write
},
5547 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5548 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5549 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5550 .fgt
= FGT_TLBIVAE1
,
5551 .writefn
= tlbi_aa64_vae1_write
},
5552 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5553 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5554 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5555 .fgt
= FGT_TLBIASIDE1
,
5556 .writefn
= tlbi_aa64_vmalle1_write
},
5557 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5558 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5559 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5560 .fgt
= FGT_TLBIVAAE1
,
5561 .writefn
= tlbi_aa64_vae1_write
},
5562 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5563 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5564 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5565 .fgt
= FGT_TLBIVALE1
,
5566 .writefn
= tlbi_aa64_vae1_write
},
5567 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5568 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5569 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5570 .fgt
= FGT_TLBIVAALE1
,
5571 .writefn
= tlbi_aa64_vae1_write
},
5572 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5573 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5574 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5575 .writefn
= tlbi_aa64_ipas2e1is_write
},
5576 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5578 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5579 .writefn
= tlbi_aa64_ipas2e1is_write
},
5580 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5581 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5582 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5583 .writefn
= tlbi_aa64_alle1is_write
},
5584 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5585 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5586 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5587 .writefn
= tlbi_aa64_alle1is_write
},
5588 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5589 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5590 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5591 .writefn
= tlbi_aa64_ipas2e1_write
},
5592 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5593 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5594 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5595 .writefn
= tlbi_aa64_ipas2e1_write
},
5596 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5597 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5598 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5599 .writefn
= tlbi_aa64_alle1_write
},
5600 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5601 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5602 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5603 .writefn
= tlbi_aa64_alle1is_write
},
5604 #ifndef CONFIG_USER_ONLY
5605 /* 64 bit address translation operations */
5606 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5607 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5608 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5610 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5611 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5612 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5613 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5615 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5616 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5617 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5618 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5620 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5621 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5622 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5623 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5625 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5626 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5627 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5628 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5629 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5630 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5631 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5632 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5633 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5634 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5635 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5636 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5637 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5638 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5639 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5640 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5641 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5642 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5643 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5644 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5645 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5646 .writefn
= ats_write64
},
5647 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5648 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5649 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5650 .writefn
= ats_write64
},
5651 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5652 .type
= ARM_CP_ALIAS
,
5653 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5654 .access
= PL1_RW
, .resetvalue
= 0,
5656 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5657 .writefn
= par_write
},
5659 /* TLB invalidate last level of translation table walk */
5660 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5661 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5662 .writefn
= tlbimva_is_write
},
5663 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5664 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5665 .writefn
= tlbimvaa_is_write
},
5666 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5667 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5668 .writefn
= tlbimva_write
},
5669 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5670 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5671 .writefn
= tlbimvaa_write
},
5672 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5673 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5674 .writefn
= tlbimva_hyp_write
},
5675 { .name
= "TLBIMVALHIS",
5676 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5677 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5678 .writefn
= tlbimva_hyp_is_write
},
5679 { .name
= "TLBIIPAS2",
5680 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5681 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5682 .writefn
= tlbiipas2_hyp_write
},
5683 { .name
= "TLBIIPAS2IS",
5684 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5685 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5686 .writefn
= tlbiipas2is_hyp_write
},
5687 { .name
= "TLBIIPAS2L",
5688 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5689 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5690 .writefn
= tlbiipas2_hyp_write
},
5691 { .name
= "TLBIIPAS2LIS",
5692 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5693 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5694 .writefn
= tlbiipas2is_hyp_write
},
5695 /* 32 bit cache operations */
5696 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5697 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5698 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5699 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5700 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5701 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5702 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5703 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5704 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5705 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5706 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5707 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5708 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5709 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5710 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5711 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5712 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5713 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5714 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5715 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5716 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5717 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5718 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5719 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5720 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5721 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5722 /* MMU Domain access control / MPU write buffer control */
5723 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5724 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5725 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5726 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5727 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5728 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5729 .type
= ARM_CP_ALIAS
,
5730 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5731 .access
= PL1_RW
, .accessfn
= access_nv1
,
5732 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5733 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5734 .type
= ARM_CP_ALIAS
,
5735 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5736 .access
= PL1_RW
, .accessfn
= access_nv1
,
5737 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5739 * We rely on the access checks not allowing the guest to write to the
5740 * state field when SPSel indicates that it's being used as the stack
5743 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5744 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5745 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5746 .type
= ARM_CP_ALIAS
,
5747 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5748 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5749 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5750 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5751 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5752 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5753 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5754 .type
= ARM_CP_NO_RAW
,
5755 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5756 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5757 .type
= ARM_CP_ALIAS
,
5758 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5760 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5761 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5762 .type
= ARM_CP_ALIAS
,
5763 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5765 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5766 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5767 .type
= ARM_CP_ALIAS
,
5768 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5770 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5771 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5772 .type
= ARM_CP_ALIAS
,
5773 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5775 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5776 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5778 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5781 .writefn
= mdcr_el3_write
,
5782 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5783 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5784 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5785 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5786 .writefn
= sdcr_write
,
5787 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5790 /* These are present only when EL1 supports AArch32 */
5791 static const ARMCPRegInfo v8_aa32_el1_reginfo
[] = {
5792 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5793 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5795 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5796 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5797 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5798 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5799 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5800 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5801 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5802 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5803 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5804 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5805 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5808 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5810 ARMCPU
*cpu
= env_archcpu(env
);
5812 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5813 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5815 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5818 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5819 valid_mask
&= ~HCR_HCD
;
5820 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5822 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5823 * However, if we're using the SMC PSCI conduit then QEMU is
5824 * effectively acting like EL3 firmware and so the guest at
5825 * EL2 should retain the ability to prevent EL1 from being
5826 * able to make SMC calls into the ersatz firmware, so in
5827 * that case HCR.TSC should be read/write.
5829 valid_mask
&= ~HCR_TSC
;
5832 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5833 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5834 valid_mask
|= HCR_E2H
;
5836 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5837 valid_mask
|= HCR_TERR
| HCR_TEA
;
5839 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5840 valid_mask
|= HCR_TLOR
;
5842 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5843 valid_mask
|= HCR_API
| HCR_APK
;
5845 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5846 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5848 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5849 valid_mask
|= HCR_ENSCXT
;
5851 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5852 valid_mask
|= HCR_FWB
;
5854 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5855 valid_mask
|= HCR_GPF
;
5857 if (cpu_isar_feature(aa64_nv
, cpu
)) {
5858 valid_mask
|= HCR_NV
| HCR_NV1
| HCR_AT
;
5860 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
5861 valid_mask
|= HCR_NV2
;
5865 if (cpu_isar_feature(any_evt
, cpu
)) {
5866 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5867 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5868 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5871 /* Clear RES0 bits. */
5872 value
&= valid_mask
;
5875 * These bits change the MMU setup:
5876 * HCR_VM enables stage 2 translation
5877 * HCR_PTW forbids certain page-table setups
5878 * HCR_DC disables stage1 and enables stage2 translation
5879 * HCR_DCT enables tagging on (disabled) stage1 translation
5880 * HCR_FWB changes the interpretation of stage2 descriptor bits
5881 * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
5883 if ((env
->cp15
.hcr_el2
^ value
) &
5884 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
| HCR_NV
| HCR_NV1
)) {
5885 tlb_flush(CPU(cpu
));
5887 env
->cp15
.hcr_el2
= value
;
5890 * Updates to VI and VF require us to update the status of
5891 * virtual interrupts, which are the logical OR of these bits
5892 * and the state of the input lines from the GIC. (This requires
5893 * that we have the BQL, which is done by marking the
5894 * reginfo structs as ARM_CP_IO.)
5895 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5896 * possible for it to be taken immediately, because VIRQ and
5897 * VFIQ are masked unless running at EL0 or EL1, and HCR
5898 * can only be written at EL2.
5900 g_assert(bql_locked());
5901 arm_cpu_update_virq(cpu
);
5902 arm_cpu_update_vfiq(cpu
);
5903 arm_cpu_update_vserr(cpu
);
5906 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5908 do_hcr_write(env
, value
, 0);
5911 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5914 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5915 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5916 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5919 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5922 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5923 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5924 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5928 * Return the effective value of HCR_EL2, at the given security state.
5929 * Bits that are not included here:
5930 * RW (read from SCR_EL3.RW as needed)
5932 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5934 uint64_t ret
= env
->cp15
.hcr_el2
;
5936 assert(space
!= ARMSS_Root
);
5938 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5940 * "This register has no effect if EL2 is not enabled in the
5941 * current Security state". This is ARMv8.4-SecEL2 speak for
5942 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5944 * Prior to that, the language was "In an implementation that
5945 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5946 * as if this field is 0 for all purposes other than a direct
5947 * read or write access of HCR_EL2". With lots of enumeration
5948 * on a per-field basis. In current QEMU, this is condition
5949 * is arm_is_secure_below_el3.
5951 * Since the v8.4 language applies to the entire register, and
5952 * appears to be backward compatible, use that.
5958 * For a cpu that supports both aarch64 and aarch32, we can set bits
5959 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5960 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5962 if (!arm_el_is_aa64(env
, 2)) {
5963 uint64_t aa32_valid
;
5966 * These bits are up-to-date as of ARMv8.6.
5967 * For HCR, it's easiest to list just the 2 bits that are invalid.
5968 * For HCR2, list those that are valid.
5970 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5971 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5972 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5976 if (ret
& HCR_TGE
) {
5977 /* These bits are up-to-date as of ARMv8.6. */
5978 if (ret
& HCR_E2H
) {
5979 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5980 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5981 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5982 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5983 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5984 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5986 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5988 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5989 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5990 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5997 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5999 if (arm_feature(env
, ARM_FEATURE_M
)) {
6002 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
6006 * Corresponds to ARM pseudocode function ELIsInHost().
6008 bool el_is_in_host(CPUARMState
*env
, int el
)
6013 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
6014 * Perform the simplest bit tests first, and validate EL2 afterward.
6017 return false; /* EL1 or EL3 */
6021 * Note that hcr_write() checks isar_feature_aa64_vh(),
6022 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
6024 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
6025 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
6029 /* TGE and/or E2H set: double check those bits are currently legal. */
6030 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
6033 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6036 uint64_t valid_mask
= 0;
6038 /* FEAT_MOPS adds MSCEn and MCE2 */
6039 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6040 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
6043 /* Clear RES0 bits. */
6044 env
->cp15
.hcrx_el2
= value
& valid_mask
;
6047 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6050 if (arm_current_el(env
) == 2
6051 && arm_feature(env
, ARM_FEATURE_EL3
)
6052 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6053 return CP_ACCESS_TRAP_EL3
;
6055 return CP_ACCESS_OK
;
6058 static const ARMCPRegInfo hcrx_el2_reginfo
= {
6059 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
6060 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
6061 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
6062 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
6065 /* Return the effective value of HCRX_EL2. */
6066 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
6069 * The bits in this register behave as 0 for all purposes other than
6070 * direct reads of the register if SCR_EL3.HXEn is 0.
6071 * If EL2 is not enabled in the current security state, then the
6072 * bit may behave as if 0, or as if 1, depending on the bit.
6073 * For the moment, we treat the EL2-disabled case as taking
6074 * priority over the HXEn-disabled case. This is true for the only
6075 * bit for a feature which we implement where the answer is different
6076 * for the two cases (MSCEn for FEAT_MOPS).
6077 * This may need to be revisited for future bits.
6079 if (!arm_is_el2_enabled(env
)) {
6081 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6082 /* MSCEn behaves as 1 if EL2 is not enabled */
6087 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6090 return env
->cp15
.hcrx_el2
;
6093 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6097 * For A-profile AArch32 EL3, if NSACR.CP10
6098 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6100 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6101 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6102 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6103 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6105 env
->cp15
.cptr_el
[2] = value
;
6108 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6111 * For A-profile AArch32 EL3, if NSACR.CP10
6112 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6114 uint64_t value
= env
->cp15
.cptr_el
[2];
6116 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6117 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6118 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6123 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6124 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6126 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6127 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6128 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6129 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6130 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6131 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6132 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6133 .writefn
= hcr_writelow
},
6134 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6135 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6136 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6137 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6138 .type
= ARM_CP_ALIAS
,
6139 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6141 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6142 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6143 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6144 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6145 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6146 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6147 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6148 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6149 .type
= ARM_CP_ALIAS
,
6150 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6152 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6153 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6154 .type
= ARM_CP_ALIAS
,
6155 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6157 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6158 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6159 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6160 .access
= PL2_RW
, .writefn
= vbar_write
,
6161 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6163 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6164 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6165 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6166 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6167 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6168 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6169 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6170 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6171 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6172 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6173 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6174 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6176 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6177 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6178 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6179 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6180 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6181 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6182 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6184 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6185 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6186 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6187 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6189 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6190 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6191 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6193 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6194 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6195 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6197 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6198 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6199 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6200 .raw_writefn
= raw_write
,
6201 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6202 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6203 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6204 .type
= ARM_CP_ALIAS
,
6205 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6206 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6207 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6208 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6210 /* no .writefn needed as this can't cause an ASID change */
6211 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6212 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6213 .cp
= 15, .opc1
= 6, .crm
= 2,
6214 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6215 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6216 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6217 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6218 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6219 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6220 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6221 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6222 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6223 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6224 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6225 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6226 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6227 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6228 .access
= PL2_RW
, .resetvalue
= 0,
6229 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6230 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6231 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6232 .access
= PL2_RW
, .resetvalue
= 0,
6233 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6234 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6235 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6236 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6237 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6238 { .name
= "TLBIALLNSNH",
6239 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6240 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6241 .writefn
= tlbiall_nsnh_write
},
6242 { .name
= "TLBIALLNSNHIS",
6243 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6244 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6245 .writefn
= tlbiall_nsnh_is_write
},
6246 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6247 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6248 .writefn
= tlbiall_hyp_write
},
6249 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6250 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6251 .writefn
= tlbiall_hyp_is_write
},
6252 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6253 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6254 .writefn
= tlbimva_hyp_write
},
6255 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6256 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6257 .writefn
= tlbimva_hyp_is_write
},
6258 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6259 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6260 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6261 .writefn
= tlbi_aa64_alle2_write
},
6262 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6263 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6264 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6265 .writefn
= tlbi_aa64_vae2_write
},
6266 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6267 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6268 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6269 .writefn
= tlbi_aa64_vae2_write
},
6270 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6271 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6272 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6273 .writefn
= tlbi_aa64_alle2is_write
},
6274 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6275 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6276 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6277 .writefn
= tlbi_aa64_vae2is_write
},
6278 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6279 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6280 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6281 .writefn
= tlbi_aa64_vae2is_write
},
6282 #ifndef CONFIG_USER_ONLY
6284 * Unlike the other EL2-related AT operations, these must
6285 * UNDEF from EL3 if EL2 is not implemented, which is why we
6286 * define them here rather than with the rest of the AT ops.
6288 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6289 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6290 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6291 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6292 .writefn
= ats_write64
},
6293 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6294 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6295 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6296 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6297 .writefn
= ats_write64
},
6299 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6300 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6301 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6302 * to behave as if SCR.NS was 1.
6304 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6306 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6307 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6309 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6310 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6311 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6313 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6314 * reset values as IMPDEF. We choose to reset to 3 to comply with
6315 * both ARMv7 and ARMv8.
6317 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6318 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6319 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6320 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6321 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6322 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6323 .writefn
= gt_cntvoff_write
,
6324 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6325 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6326 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6327 .writefn
= gt_cntvoff_write
,
6328 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6329 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6330 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6331 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6332 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6333 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6334 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6335 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6336 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6337 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6338 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6339 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6340 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6341 .resetfn
= gt_hyp_timer_reset
,
6342 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6343 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6345 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6347 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6349 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6351 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6352 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6353 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6354 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6355 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6356 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6358 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6359 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6360 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6362 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6365 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6366 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6367 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6368 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6370 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6371 .writefn
= hcr_writehigh
},
6374 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6377 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6378 return CP_ACCESS_OK
;
6380 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6383 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6384 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6385 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6386 .access
= PL2_RW
, .accessfn
= sel2_access
,
6387 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6388 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6389 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6390 .access
= PL2_RW
, .accessfn
= sel2_access
,
6391 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6394 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6398 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6399 * At Secure EL1 it traps to EL3 or EL2.
6401 if (arm_current_el(env
) == 3) {
6402 return CP_ACCESS_OK
;
6404 if (arm_is_secure_below_el3(env
)) {
6405 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6406 return CP_ACCESS_TRAP_EL2
;
6408 return CP_ACCESS_TRAP_EL3
;
6410 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6412 return CP_ACCESS_OK
;
6414 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6417 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6418 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6419 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6420 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6421 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6422 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6423 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6424 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6425 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6426 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6427 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6428 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6429 .access
= PL3_RW
, .resetvalue
= 0,
6430 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6432 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6433 .access
= PL3_RW
, .resetvalue
= 0,
6434 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6435 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6436 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6437 .writefn
= vbar_write
, .resetvalue
= 0,
6438 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6439 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6440 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6441 .access
= PL3_RW
, .resetvalue
= 0,
6442 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6443 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6444 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6446 /* no .writefn needed as this can't cause an ASID change */
6448 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6449 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6450 .type
= ARM_CP_ALIAS
,
6451 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6453 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6454 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6455 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6456 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6457 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6458 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6459 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6460 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6461 .type
= ARM_CP_ALIAS
,
6462 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6464 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6465 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6466 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6467 .access
= PL3_RW
, .writefn
= vbar_write
,
6468 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6470 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6471 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6472 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6473 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6474 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6475 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6476 .access
= PL3_RW
, .resetvalue
= 0,
6477 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6478 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6479 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6480 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6482 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6483 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6484 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6486 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6487 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6488 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6490 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6491 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6492 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6493 .writefn
= tlbi_aa64_alle3is_write
},
6494 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6495 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6496 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6497 .writefn
= tlbi_aa64_vae3is_write
},
6498 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6499 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6500 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6501 .writefn
= tlbi_aa64_vae3is_write
},
6502 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6503 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6504 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6505 .writefn
= tlbi_aa64_alle3_write
},
6506 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6507 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6508 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6509 .writefn
= tlbi_aa64_vae3_write
},
6510 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6511 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6512 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6513 .writefn
= tlbi_aa64_vae3_write
},
6516 #ifndef CONFIG_USER_ONLY
6517 /* Test if system register redirection is to occur in the current state. */
6518 static bool redirect_for_e2h(CPUARMState
*env
)
6520 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6523 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6527 if (redirect_for_e2h(env
)) {
6528 /* Switch to the saved EL2 version of the register. */
6530 readfn
= ri
->readfn
;
6532 readfn
= ri
->orig_readfn
;
6534 if (readfn
== NULL
) {
6537 return readfn(env
, ri
);
6540 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6545 if (redirect_for_e2h(env
)) {
6546 /* Switch to the saved EL2 version of the register. */
6548 writefn
= ri
->writefn
;
6550 writefn
= ri
->orig_writefn
;
6552 if (writefn
== NULL
) {
6553 writefn
= raw_write
;
6555 writefn(env
, ri
, value
);
6558 static uint64_t el2_e2h_e12_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6560 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6561 return ri
->orig_readfn(env
, ri
->opaque
);
6564 static void el2_e2h_e12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6567 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6568 return ri
->orig_writefn(env
, ri
->opaque
, value
);
6571 static CPAccessResult
el2_e2h_e12_access(CPUARMState
*env
,
6572 const ARMCPRegInfo
*ri
,
6575 if (arm_current_el(env
) == 1) {
6577 * This must be a FEAT_NV access (will either trap or redirect
6578 * to memory). None of the registers with _EL12 aliases want to
6579 * apply their trap controls for this kind of access, so don't
6580 * call the orig_accessfn or do the "UNDEF when E2H is 0" check.
6582 return CP_ACCESS_OK
;
6584 /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
6585 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6586 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6588 if (ri
->orig_accessfn
) {
6589 return ri
->orig_accessfn(env
, ri
->opaque
, isread
);
6591 return CP_ACCESS_OK
;
6594 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6597 uint32_t src_key
, dst_key
, new_key
;
6598 const char *src_name
, *dst_name
, *new_name
;
6599 bool (*feature
)(const ARMISARegisters
*id
);
6602 #define K(op0, op1, crn, crm, op2) \
6603 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6605 static const struct E2HAlias aliases
[] = {
6606 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6607 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6608 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6609 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6610 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6611 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6612 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6613 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6614 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6615 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6616 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6617 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6618 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6619 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6620 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6621 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6622 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6623 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6624 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6625 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6626 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6627 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6628 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6629 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6630 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6631 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6632 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6633 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6634 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6635 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6636 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6637 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6640 * Note that redirection of ZCR is mentioned in the description
6641 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6642 * not in the summary table.
6644 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6645 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6646 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6647 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6649 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6650 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6652 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6653 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6654 isar_feature_aa64_scxtnum
},
6656 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6657 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6663 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6664 const struct E2HAlias
*a
= &aliases
[i
];
6665 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6668 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6672 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6673 (gpointer
)(uintptr_t)a
->src_key
);
6674 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6675 (gpointer
)(uintptr_t)a
->dst_key
);
6676 g_assert(src_reg
!= NULL
);
6677 g_assert(dst_reg
!= NULL
);
6679 /* Cross-compare names to detect typos in the keys. */
6680 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6681 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6683 /* None of the core system registers use opaque; we will. */
6684 g_assert(src_reg
->opaque
== NULL
);
6686 /* Create alias before redirection so we dup the right data. */
6687 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6689 new_reg
->name
= a
->new_name
;
6690 new_reg
->type
|= ARM_CP_ALIAS
;
6691 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6692 new_reg
->access
&= PL2_RW
| PL3_RW
;
6693 /* The new_reg op fields are as per new_key, not the target reg */
6694 new_reg
->crn
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRN_MASK
)
6695 >> CP_REG_ARM64_SYSREG_CRN_SHIFT
;
6696 new_reg
->crm
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRM_MASK
)
6697 >> CP_REG_ARM64_SYSREG_CRM_SHIFT
;
6698 new_reg
->opc0
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP0_MASK
)
6699 >> CP_REG_ARM64_SYSREG_OP0_SHIFT
;
6700 new_reg
->opc1
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP1_MASK
)
6701 >> CP_REG_ARM64_SYSREG_OP1_SHIFT
;
6702 new_reg
->opc2
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP2_MASK
)
6703 >> CP_REG_ARM64_SYSREG_OP2_SHIFT
;
6704 new_reg
->opaque
= src_reg
;
6705 new_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6706 new_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6707 new_reg
->orig_accessfn
= src_reg
->accessfn
;
6708 if (!new_reg
->raw_readfn
) {
6709 new_reg
->raw_readfn
= raw_read
;
6711 if (!new_reg
->raw_writefn
) {
6712 new_reg
->raw_writefn
= raw_write
;
6714 new_reg
->readfn
= el2_e2h_e12_read
;
6715 new_reg
->writefn
= el2_e2h_e12_write
;
6716 new_reg
->accessfn
= el2_e2h_e12_access
;
6718 ok
= g_hash_table_insert(cpu
->cp_regs
,
6719 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6722 src_reg
->opaque
= dst_reg
;
6723 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6724 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6725 if (!src_reg
->raw_readfn
) {
6726 src_reg
->raw_readfn
= raw_read
;
6728 if (!src_reg
->raw_writefn
) {
6729 src_reg
->raw_writefn
= raw_write
;
6731 src_reg
->readfn
= el2_e2h_read
;
6732 src_reg
->writefn
= el2_e2h_write
;
6737 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6740 int cur_el
= arm_current_el(env
);
6743 uint64_t hcr
= arm_hcr_el2_eff(env
);
6746 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6747 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6748 return CP_ACCESS_TRAP_EL2
;
6751 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6752 return CP_ACCESS_TRAP
;
6754 if (hcr
& HCR_TID2
) {
6755 return CP_ACCESS_TRAP_EL2
;
6758 } else if (hcr
& HCR_TID2
) {
6759 return CP_ACCESS_TRAP_EL2
;
6763 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6764 return CP_ACCESS_TRAP_EL2
;
6767 return CP_ACCESS_OK
;
6771 * Check for traps to RAS registers, which are controlled
6772 * by HCR_EL2.TERR and SCR_EL3.TERR.
6774 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6777 int el
= arm_current_el(env
);
6779 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6780 return CP_ACCESS_TRAP_EL2
;
6782 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6783 return CP_ACCESS_TRAP_EL3
;
6785 return CP_ACCESS_OK
;
6788 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6790 int el
= arm_current_el(env
);
6792 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6793 return env
->cp15
.vdisr_el2
;
6795 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6796 return 0; /* RAZ/WI */
6798 return env
->cp15
.disr_el1
;
6801 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6803 int el
= arm_current_el(env
);
6805 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6806 env
->cp15
.vdisr_el2
= val
;
6809 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6810 return; /* RAZ/WI */
6812 env
->cp15
.disr_el1
= val
;
6816 * Minimal RAS implementation with no Error Records.
6817 * Which means that all of the Error Record registers:
6825 * ERXPFGCDN_EL1 (RASv1p1)
6826 * ERXPFGCTL_EL1 (RASv1p1)
6827 * ERXPFGF_EL1 (RASv1p1)
6831 * may generate UNDEFINED, which is the effect we get by not
6832 * listing them at all.
6834 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6835 * is higher priority than FGT-to-EL2 so we do not need to list them
6836 * in order to check for an FGT.
6838 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6839 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6840 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6841 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6842 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6843 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6844 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6845 .access
= PL1_R
, .accessfn
= access_terr
,
6846 .fgt
= FGT_ERRIDR_EL1
,
6847 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6848 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6849 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6850 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6851 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6852 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6853 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6857 * Return the exception level to which exceptions should be taken
6858 * via SVEAccessTrap. This excludes the check for whether the exception
6859 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6860 * be found by testing 0 < fp_exception_el < sve_exception_el.
6862 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6863 * pseudocode does *not* separate out the FP trap checks, but has them
6864 * all in one function.
6866 int sve_exception_el(CPUARMState
*env
, int el
)
6868 #ifndef CONFIG_USER_ONLY
6869 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6870 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6882 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6883 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6884 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6885 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6887 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6896 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6902 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6903 if (arm_feature(env
, ARM_FEATURE_EL3
)
6904 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6912 * Return the exception level to which exceptions should be taken for SME.
6913 * C.f. the ARM pseudocode function CheckSMEAccess.
6915 int sme_exception_el(CPUARMState
*env
, int el
)
6917 #ifndef CONFIG_USER_ONLY
6918 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6919 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6931 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6932 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6933 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6934 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6936 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6945 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6951 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6952 if (arm_feature(env
, ARM_FEATURE_EL3
)
6953 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6961 * Given that SVE is enabled, return the vector length for EL.
6963 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6965 ARMCPU
*cpu
= env_archcpu(env
);
6966 uint64_t *cr
= env
->vfp
.zcr_el
;
6967 uint32_t map
= cpu
->sve_vq
.map
;
6968 uint32_t len
= ARM_MAX_VQ
- 1;
6971 cr
= env
->vfp
.smcr_el
;
6972 map
= cpu
->sme_vq
.map
;
6975 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6976 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6978 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6979 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6981 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6982 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6985 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6987 return 31 - clz32(map
);
6990 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6992 return ctz32(cpu
->sme_vq
.map
);
6995 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6997 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
7000 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7003 int cur_el
= arm_current_el(env
);
7004 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7007 /* Bits other than [3:0] are RAZ/WI. */
7008 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
7009 raw_write(env
, ri
, value
& 0xf);
7012 * Because we arrived here, we know both FP and SVE are enabled;
7013 * otherwise we would have trapped access to the ZCR_ELn register.
7015 new_len
= sve_vqm1_for_el(env
, cur_el
);
7016 if (new_len
< old_len
) {
7017 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7021 static const ARMCPRegInfo zcr_reginfo
[] = {
7022 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
7023 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
7024 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
7025 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
7026 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7027 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
7028 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
7029 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
7030 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
7031 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7032 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
7033 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
7034 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
7035 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
7036 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7039 #ifdef TARGET_AARCH64
7040 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7043 int el
= arm_current_el(env
);
7046 uint64_t sctlr
= arm_sctlr(env
, el
);
7047 if (!(sctlr
& SCTLR_EnTP2
)) {
7048 return CP_ACCESS_TRAP
;
7051 /* TODO: FEAT_FGT */
7053 && arm_feature(env
, ARM_FEATURE_EL3
)
7054 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
7055 return CP_ACCESS_TRAP_EL3
;
7057 return CP_ACCESS_OK
;
7060 static CPAccessResult
access_smprimap(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7063 /* If EL1 this is a FEAT_NV access and CPTR_EL3.ESM doesn't apply */
7064 if (arm_current_el(env
) == 2
7065 && arm_feature(env
, ARM_FEATURE_EL3
)
7066 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7067 return CP_ACCESS_TRAP_EL3
;
7069 return CP_ACCESS_OK
;
7072 static CPAccessResult
access_smpri(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7075 if (arm_current_el(env
) < 3
7076 && arm_feature(env
, ARM_FEATURE_EL3
)
7077 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7078 return CP_ACCESS_TRAP_EL3
;
7080 return CP_ACCESS_OK
;
7084 static void arm_reset_sve_state(CPUARMState
*env
)
7086 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
7087 /* Recall that FFR is stored as pregs[16]. */
7088 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
7089 vfp_set_fpcr(env
, 0x0800009f);
7092 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
7094 uint64_t change
= (env
->svcr
^ new) & mask
;
7099 env
->svcr
^= change
;
7101 if (change
& R_SVCR_SM_MASK
) {
7102 arm_reset_sve_state(env
);
7108 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
7109 * on enable: while disabled, the storage is inaccessible and the
7110 * value does not matter. We're not saving the storage in vmstate
7111 * when disabled either.
7113 if (change
& new & R_SVCR_ZA_MASK
) {
7114 memset(env
->zarray
, 0, sizeof(env
->zarray
));
7117 if (tcg_enabled()) {
7118 arm_rebuild_hflags(env
);
7122 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7125 aarch64_set_svcr(env
, value
, -1);
7128 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7131 int cur_el
= arm_current_el(env
);
7132 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7135 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
7136 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
7137 raw_write(env
, ri
, value
);
7140 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7141 * when SVL is widened (old values kept, or zeros). Choose to keep the
7142 * current values for simplicity. But for QEMU internals, we must still
7143 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7144 * above aarch64_sve_narrow_vq.
7146 new_len
= sve_vqm1_for_el(env
, cur_el
);
7147 if (new_len
< old_len
) {
7148 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7152 static const ARMCPRegInfo sme_reginfo
[] = {
7153 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7154 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7155 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7156 .fgt
= FGT_NTPIDR2_EL0
,
7157 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7158 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7159 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7160 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7161 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7162 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7163 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7164 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7165 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7166 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7167 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7168 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7169 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7170 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7171 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7172 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7173 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7174 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7175 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7176 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7177 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7178 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7179 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7180 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7182 * IMPLEMENTOR = 0 (software)
7183 * REVISION = 0 (implementation defined)
7184 * SMPS = 0 (no streaming execution priority in QEMU)
7185 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7187 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7189 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7191 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7192 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7193 .access
= PL1_RW
, .accessfn
= access_smpri
,
7194 .fgt
= FGT_NSMPRI_EL1
,
7195 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7196 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7197 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7198 .access
= PL2_RW
, .accessfn
= access_smprimap
,
7199 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7202 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7205 CPUState
*cs
= env_cpu(env
);
7210 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7213 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7214 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7215 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7216 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7218 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7221 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7223 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7224 env_archcpu(env
)->reset_l0gptsz
);
7227 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7230 CPUState
*cs
= env_cpu(env
);
7232 tlb_flush_all_cpus_synced(cs
);
7235 static const ARMCPRegInfo rme_reginfo
[] = {
7236 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7237 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7238 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7239 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7240 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7241 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7242 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7243 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7244 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7245 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7246 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7247 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7248 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7249 .writefn
= tlbi_aa64_paall_write
},
7250 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7251 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7252 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7253 .writefn
= tlbi_aa64_paallos_write
},
7255 * QEMU does not have a way to invalidate by physical address, thus
7256 * invalidating a range of physical addresses is accomplished by
7257 * flushing all tlb entries in the outer shareable domain,
7258 * just like PAALLOS.
7260 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7261 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7262 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7263 .writefn
= tlbi_aa64_paallos_write
},
7264 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7265 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7266 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7267 .writefn
= tlbi_aa64_paallos_write
},
7268 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7269 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7270 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7273 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7274 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7275 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7276 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7278 #endif /* TARGET_AARCH64 */
7280 static void define_pmu_regs(ARMCPU
*cpu
)
7283 * v7 performance monitor control register: same implementor
7284 * field as main ID register, and we implement four counters in
7285 * addition to the cycle count register.
7287 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7288 ARMCPRegInfo pmcr
= {
7289 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7291 .fgt
= FGT_PMCR_EL0
,
7292 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7293 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7294 .accessfn
= pmreg_access
,
7295 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7296 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7298 ARMCPRegInfo pmcr64
= {
7299 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7300 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7301 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7302 .fgt
= FGT_PMCR_EL0
,
7304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7305 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7306 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7307 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7310 define_one_arm_cp_reg(cpu
, &pmcr
);
7311 define_one_arm_cp_reg(cpu
, &pmcr64
);
7312 for (i
= 0; i
< pmcrn
; i
++) {
7313 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7314 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7315 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7316 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7317 ARMCPRegInfo pmev_regs
[] = {
7318 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7319 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7320 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7321 .fgt
= FGT_PMEVCNTRN_EL0
,
7322 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7323 .accessfn
= pmreg_access_xevcntr
},
7324 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7325 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7326 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7328 .fgt
= FGT_PMEVCNTRN_EL0
,
7329 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7330 .raw_readfn
= pmevcntr_rawread
,
7331 .raw_writefn
= pmevcntr_rawwrite
},
7332 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7333 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7334 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7335 .fgt
= FGT_PMEVTYPERN_EL0
,
7336 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7337 .accessfn
= pmreg_access
},
7338 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7339 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7340 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7341 .fgt
= FGT_PMEVTYPERN_EL0
,
7343 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7344 .raw_writefn
= pmevtyper_rawwrite
},
7346 define_arm_cp_regs(cpu
, pmev_regs
);
7347 g_free(pmevcntr_name
);
7348 g_free(pmevcntr_el0_name
);
7349 g_free(pmevtyper_name
);
7350 g_free(pmevtyper_el0_name
);
7352 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7353 ARMCPRegInfo v81_pmu_regs
[] = {
7354 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7355 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7356 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7357 .fgt
= FGT_PMCEIDN_EL0
,
7358 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7359 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7360 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7361 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7362 .fgt
= FGT_PMCEIDN_EL0
,
7363 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7365 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7367 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7368 static const ARMCPRegInfo v84_pmmir
= {
7369 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7370 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7371 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7372 .fgt
= FGT_PMMIR_EL1
,
7375 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7379 #ifndef CONFIG_USER_ONLY
7381 * We don't know until after realize whether there's a GICv3
7382 * attached, and that is what registers the gicv3 sysregs.
7383 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7386 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7388 ARMCPU
*cpu
= env_archcpu(env
);
7389 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7391 if (env
->gicv3state
) {
7397 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7399 ARMCPU
*cpu
= env_archcpu(env
);
7400 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7402 if (env
->gicv3state
) {
7410 * Shared logic between LORID and the rest of the LOR* registers.
7411 * Secure state exclusion has already been dealt with.
7413 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7414 const ARMCPRegInfo
*ri
, bool isread
)
7416 int el
= arm_current_el(env
);
7418 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7419 return CP_ACCESS_TRAP_EL2
;
7421 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7422 return CP_ACCESS_TRAP_EL3
;
7424 return CP_ACCESS_OK
;
7427 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7428 const ARMCPRegInfo
*ri
, bool isread
)
7430 if (arm_is_secure_below_el3(env
)) {
7431 /* Access denied in secure mode. */
7432 return CP_ACCESS_TRAP
;
7434 return access_lor_ns(env
, ri
, isread
);
7438 * A trivial implementation of ARMv8.1-LOR leaves all of these
7439 * registers fixed at 0, which indicates that there are zero
7440 * supported Limited Ordering regions.
7442 static const ARMCPRegInfo lor_reginfo
[] = {
7443 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7444 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7445 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7446 .fgt
= FGT_LORSA_EL1
,
7447 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7448 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7449 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7450 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7451 .fgt
= FGT_LOREA_EL1
,
7452 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7453 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7454 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7455 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7456 .fgt
= FGT_LORN_EL1
,
7457 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7458 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7459 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7460 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7461 .fgt
= FGT_LORC_EL1
,
7462 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7463 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7464 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7465 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7466 .fgt
= FGT_LORID_EL1
,
7467 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7470 #ifdef TARGET_AARCH64
7471 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7474 int el
= arm_current_el(env
);
7477 arm_is_el2_enabled(env
) &&
7478 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7479 return CP_ACCESS_TRAP_EL2
;
7482 arm_feature(env
, ARM_FEATURE_EL3
) &&
7483 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7484 return CP_ACCESS_TRAP_EL3
;
7486 return CP_ACCESS_OK
;
7489 static const ARMCPRegInfo pauth_reginfo
[] = {
7490 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7491 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7492 .access
= PL1_RW
, .accessfn
= access_pauth
,
7494 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7495 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7496 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7497 .access
= PL1_RW
, .accessfn
= access_pauth
,
7499 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7500 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7501 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7502 .access
= PL1_RW
, .accessfn
= access_pauth
,
7504 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7505 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7506 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7507 .access
= PL1_RW
, .accessfn
= access_pauth
,
7509 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7510 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7511 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7512 .access
= PL1_RW
, .accessfn
= access_pauth
,
7514 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7515 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7516 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7517 .access
= PL1_RW
, .accessfn
= access_pauth
,
7519 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7520 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7521 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7522 .access
= PL1_RW
, .accessfn
= access_pauth
,
7524 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7525 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7526 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7527 .access
= PL1_RW
, .accessfn
= access_pauth
,
7529 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7530 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7531 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7532 .access
= PL1_RW
, .accessfn
= access_pauth
,
7534 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7535 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7536 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7537 .access
= PL1_RW
, .accessfn
= access_pauth
,
7539 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7542 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7543 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7544 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7545 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7546 .fgt
= FGT_TLBIRVAE1IS
,
7547 .writefn
= tlbi_aa64_rvae1is_write
},
7548 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7549 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7550 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7551 .fgt
= FGT_TLBIRVAAE1IS
,
7552 .writefn
= tlbi_aa64_rvae1is_write
},
7553 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7554 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7555 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7556 .fgt
= FGT_TLBIRVALE1IS
,
7557 .writefn
= tlbi_aa64_rvae1is_write
},
7558 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7559 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7560 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7561 .fgt
= FGT_TLBIRVAALE1IS
,
7562 .writefn
= tlbi_aa64_rvae1is_write
},
7563 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7564 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7565 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7566 .fgt
= FGT_TLBIRVAE1OS
,
7567 .writefn
= tlbi_aa64_rvae1is_write
},
7568 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7569 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7570 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7571 .fgt
= FGT_TLBIRVAAE1OS
,
7572 .writefn
= tlbi_aa64_rvae1is_write
},
7573 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7574 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7575 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7576 .fgt
= FGT_TLBIRVALE1OS
,
7577 .writefn
= tlbi_aa64_rvae1is_write
},
7578 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7579 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7580 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7581 .fgt
= FGT_TLBIRVAALE1OS
,
7582 .writefn
= tlbi_aa64_rvae1is_write
},
7583 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7584 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7585 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7586 .fgt
= FGT_TLBIRVAE1
,
7587 .writefn
= tlbi_aa64_rvae1_write
},
7588 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7589 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7590 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7591 .fgt
= FGT_TLBIRVAAE1
,
7592 .writefn
= tlbi_aa64_rvae1_write
},
7593 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7594 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7595 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7596 .fgt
= FGT_TLBIRVALE1
,
7597 .writefn
= tlbi_aa64_rvae1_write
},
7598 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7599 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7600 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7601 .fgt
= FGT_TLBIRVAALE1
,
7602 .writefn
= tlbi_aa64_rvae1_write
},
7603 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7604 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7605 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7606 .writefn
= tlbi_aa64_ripas2e1is_write
},
7607 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7608 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7609 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7610 .writefn
= tlbi_aa64_ripas2e1is_write
},
7611 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7612 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7613 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7614 .writefn
= tlbi_aa64_rvae2is_write
},
7615 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7616 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7617 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7618 .writefn
= tlbi_aa64_rvae2is_write
},
7619 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7620 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7621 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7622 .writefn
= tlbi_aa64_ripas2e1_write
},
7623 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7624 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7625 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7626 .writefn
= tlbi_aa64_ripas2e1_write
},
7627 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7628 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7629 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7630 .writefn
= tlbi_aa64_rvae2is_write
},
7631 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7632 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7633 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7634 .writefn
= tlbi_aa64_rvae2is_write
},
7635 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7636 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7637 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7638 .writefn
= tlbi_aa64_rvae2_write
},
7639 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7640 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7641 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7642 .writefn
= tlbi_aa64_rvae2_write
},
7643 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7644 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7645 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7646 .writefn
= tlbi_aa64_rvae3is_write
},
7647 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7648 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7649 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7650 .writefn
= tlbi_aa64_rvae3is_write
},
7651 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7652 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7653 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7654 .writefn
= tlbi_aa64_rvae3is_write
},
7655 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7656 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7657 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7658 .writefn
= tlbi_aa64_rvae3is_write
},
7659 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7660 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7661 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7662 .writefn
= tlbi_aa64_rvae3_write
},
7663 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7664 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7665 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7666 .writefn
= tlbi_aa64_rvae3_write
},
7669 static const ARMCPRegInfo tlbios_reginfo
[] = {
7670 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7671 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7672 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7673 .fgt
= FGT_TLBIVMALLE1OS
,
7674 .writefn
= tlbi_aa64_vmalle1is_write
},
7675 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7676 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7677 .fgt
= FGT_TLBIVAE1OS
,
7678 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7679 .writefn
= tlbi_aa64_vae1is_write
},
7680 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7681 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7682 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7683 .fgt
= FGT_TLBIASIDE1OS
,
7684 .writefn
= tlbi_aa64_vmalle1is_write
},
7685 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7686 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7687 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7688 .fgt
= FGT_TLBIVAAE1OS
,
7689 .writefn
= tlbi_aa64_vae1is_write
},
7690 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7691 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7692 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7693 .fgt
= FGT_TLBIVALE1OS
,
7694 .writefn
= tlbi_aa64_vae1is_write
},
7695 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7696 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7697 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7698 .fgt
= FGT_TLBIVAALE1OS
,
7699 .writefn
= tlbi_aa64_vae1is_write
},
7700 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7701 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7702 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7703 .writefn
= tlbi_aa64_alle2is_write
},
7704 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7705 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7706 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7707 .writefn
= tlbi_aa64_vae2is_write
},
7708 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7709 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7710 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7711 .writefn
= tlbi_aa64_alle1is_write
},
7712 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7713 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7714 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7715 .writefn
= tlbi_aa64_vae2is_write
},
7716 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7717 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7718 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7719 .writefn
= tlbi_aa64_alle1is_write
},
7720 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7721 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7722 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7723 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7724 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7725 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7726 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7727 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7728 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7729 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7730 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7731 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7732 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7733 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7734 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7735 .writefn
= tlbi_aa64_alle3is_write
},
7736 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7737 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7738 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7739 .writefn
= tlbi_aa64_vae3is_write
},
7740 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7741 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7742 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7743 .writefn
= tlbi_aa64_vae3is_write
},
7746 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7751 /* Success sets NZCV = 0000. */
7752 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7754 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7756 * ??? Failed, for unknown reasons in the crypto subsystem.
7757 * The best we can do is log the reason and return the
7758 * timed-out indication to the guest. There is no reason
7759 * we know to expect this failure to be transitory, so the
7760 * guest may well hang retrying the operation.
7762 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7763 ri
->name
, error_get_pretty(err
));
7766 env
->ZF
= 0; /* NZCF = 0100 */
7772 /* We do not support re-seeding, so the two registers operate the same. */
7773 static const ARMCPRegInfo rndr_reginfo
[] = {
7774 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7775 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7776 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7777 .access
= PL0_R
, .readfn
= rndr_readfn
},
7778 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7779 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7780 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7781 .access
= PL0_R
, .readfn
= rndr_readfn
},
7784 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7788 ARMCPU
*cpu
= env_archcpu(env
);
7789 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7790 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7791 uint64_t vaddr_in
= (uint64_t) value
;
7792 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7794 int mem_idx
= cpu_mmu_index(env
, false);
7796 /* This won't be crossing page boundaries */
7797 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7799 #ifndef CONFIG_USER_ONLY
7804 /* RCU lock is already being held */
7805 mr
= memory_region_from_host(haddr
, &offset
);
7808 memory_region_writeback(mr
, offset
, dline_size
);
7810 #endif /*CONFIG_USER_ONLY*/
7813 /* Handled by hardware accelerator. */
7814 g_assert_not_reached();
7815 #endif /* CONFIG_TCG */
7818 static const ARMCPRegInfo dcpop_reg
[] = {
7819 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7820 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7821 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7823 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7826 static const ARMCPRegInfo dcpodp_reg
[] = {
7827 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7828 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7829 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7831 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7834 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7837 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7838 return CP_ACCESS_TRAP_EL2
;
7841 return CP_ACCESS_OK
;
7844 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7847 int el
= arm_current_el(env
);
7848 if (el
< 2 && arm_is_el2_enabled(env
)) {
7849 uint64_t hcr
= arm_hcr_el2_eff(env
);
7850 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7851 return CP_ACCESS_TRAP_EL2
;
7855 arm_feature(env
, ARM_FEATURE_EL3
) &&
7856 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7857 return CP_ACCESS_TRAP_EL3
;
7859 return CP_ACCESS_OK
;
7862 static CPAccessResult
access_tfsr_el1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7865 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
7867 if (nv1
!= CP_ACCESS_OK
) {
7870 return access_mte(env
, ri
, isread
);
7873 static CPAccessResult
access_tfsr_el2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7877 * TFSR_EL2: similar to generic access_mte(), but we need to
7878 * account for FEAT_NV. At EL1 this must be a FEAT_NV access;
7879 * we will trap to EL2 and the HCR/SCR traps do not apply.
7881 int el
= arm_current_el(env
);
7884 return CP_ACCESS_OK
;
7886 if (el
< 2 && arm_is_el2_enabled(env
)) {
7887 uint64_t hcr
= arm_hcr_el2_eff(env
);
7888 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7889 return CP_ACCESS_TRAP_EL2
;
7893 arm_feature(env
, ARM_FEATURE_EL3
) &&
7894 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7895 return CP_ACCESS_TRAP_EL3
;
7897 return CP_ACCESS_OK
;
7900 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7902 return env
->pstate
& PSTATE_TCO
;
7905 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7907 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7910 static const ARMCPRegInfo mte_reginfo
[] = {
7911 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7912 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7913 .access
= PL1_RW
, .accessfn
= access_mte
,
7914 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7915 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7916 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7917 .access
= PL1_RW
, .accessfn
= access_tfsr_el1
,
7918 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7919 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7920 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7921 .access
= PL2_RW
, .accessfn
= access_tfsr_el2
,
7922 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7923 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7924 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7926 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7927 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7928 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7929 .access
= PL1_RW
, .accessfn
= access_mte
,
7930 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7931 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7932 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7933 .access
= PL1_RW
, .accessfn
= access_mte
,
7934 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7935 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7936 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7937 .type
= ARM_CP_NO_RAW
,
7938 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7939 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7940 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7941 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7943 .accessfn
= aa64_cacheop_poc_access
},
7944 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7945 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7947 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7948 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7949 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7950 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7952 .accessfn
= aa64_cacheop_poc_access
},
7953 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7954 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7956 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7957 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7958 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7960 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7961 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7962 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7964 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7965 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7966 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7968 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7969 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7970 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7972 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7975 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7976 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7977 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7978 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7981 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7982 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7983 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7984 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7986 .accessfn
= aa64_cacheop_poc_access
},
7987 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7988 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7989 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7991 .accessfn
= aa64_cacheop_poc_access
},
7992 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7993 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7994 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7996 .accessfn
= aa64_cacheop_poc_access
},
7997 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7998 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7999 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8001 .accessfn
= aa64_cacheop_poc_access
},
8002 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
8003 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
8004 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8006 .accessfn
= aa64_cacheop_poc_access
},
8007 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
8008 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
8009 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8011 .accessfn
= aa64_cacheop_poc_access
},
8012 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
8013 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
8014 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8016 .accessfn
= aa64_cacheop_poc_access
},
8017 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
8018 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
8019 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8021 .accessfn
= aa64_cacheop_poc_access
},
8022 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
8023 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
8024 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
8025 #ifndef CONFIG_USER_ONLY
8026 /* Avoid overhead of an access check that always passes in user-mode */
8027 .accessfn
= aa64_zva_access
,
8031 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
8032 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
8033 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
8034 #ifndef CONFIG_USER_ONLY
8035 /* Avoid overhead of an access check that always passes in user-mode */
8036 .accessfn
= aa64_zva_access
,
8042 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8045 uint64_t hcr
= arm_hcr_el2_eff(env
);
8046 int el
= arm_current_el(env
);
8048 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
8049 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
8050 if (hcr
& HCR_TGE
) {
8051 return CP_ACCESS_TRAP_EL2
;
8053 return CP_ACCESS_TRAP
;
8055 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
8056 return CP_ACCESS_TRAP_EL2
;
8058 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
8059 return CP_ACCESS_TRAP_EL2
;
8062 && arm_feature(env
, ARM_FEATURE_EL3
)
8063 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
8064 return CP_ACCESS_TRAP_EL3
;
8066 return CP_ACCESS_OK
;
8069 static CPAccessResult
access_scxtnum_el1(CPUARMState
*env
,
8070 const ARMCPRegInfo
*ri
,
8073 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
8075 if (nv1
!= CP_ACCESS_OK
) {
8078 return access_scxtnum(env
, ri
, isread
);
8081 static const ARMCPRegInfo scxtnum_reginfo
[] = {
8082 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
8083 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
8084 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
8085 .fgt
= FGT_SCXTNUM_EL0
,
8086 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
8087 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
8088 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
8089 .access
= PL1_RW
, .accessfn
= access_scxtnum_el1
,
8090 .fgt
= FGT_SCXTNUM_EL1
,
8091 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
8092 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
8093 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
8094 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
8095 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
8096 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
8097 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
8099 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
8102 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8105 if (arm_current_el(env
) == 2 &&
8106 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
8107 return CP_ACCESS_TRAP_EL3
;
8109 return CP_ACCESS_OK
;
8112 static const ARMCPRegInfo fgt_reginfo
[] = {
8113 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8114 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
8115 .access
= PL2_RW
, .accessfn
= access_fgt
,
8116 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
8117 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8118 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
8119 .access
= PL2_RW
, .accessfn
= access_fgt
,
8120 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
8121 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8122 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
8123 .access
= PL2_RW
, .accessfn
= access_fgt
,
8124 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
8125 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8126 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
8127 .access
= PL2_RW
, .accessfn
= access_fgt
,
8128 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
8129 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
8130 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
8131 .access
= PL2_RW
, .accessfn
= access_fgt
,
8132 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
8135 static void vncr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8139 * Clear the RES0 bottom 12 bits; this means at runtime we can guarantee
8140 * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything
8141 * about the RESS bits at the top -- we choose the "generate an EL2
8142 * translation abort on use" CONSTRAINED UNPREDICTABLE option (i.e. let
8143 * the ptw.c code detect the resulting invalid address).
8145 env
->cp15
.vncr_el2
= value
& ~0xfffULL
;
8148 static const ARMCPRegInfo nv2_reginfo
[] = {
8149 { .name
= "VNCR_EL2", .state
= ARM_CP_STATE_AA64
,
8150 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 2, .opc2
= 0,
8152 .writefn
= vncr_write
,
8153 .fieldoffset
= offsetof(CPUARMState
, cp15
.vncr_el2
) },
8156 #endif /* TARGET_AARCH64 */
8158 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8161 int el
= arm_current_el(env
);
8164 uint64_t sctlr
= arm_sctlr(env
, el
);
8165 if (!(sctlr
& SCTLR_EnRCTX
)) {
8166 return CP_ACCESS_TRAP
;
8168 } else if (el
== 1) {
8169 uint64_t hcr
= arm_hcr_el2_eff(env
);
8171 return CP_ACCESS_TRAP_EL2
;
8174 return CP_ACCESS_OK
;
8177 static const ARMCPRegInfo predinv_reginfo
[] = {
8178 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
8179 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
8181 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8182 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
8183 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
8185 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8186 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
8187 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
8189 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8191 * Note the AArch32 opcodes have a different OPC1.
8193 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
8194 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
8196 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8197 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
8198 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
8200 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8201 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
8202 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
8204 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8207 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8209 /* Read the high 32 bits of the current CCSIDR */
8210 return extract64(ccsidr_read(env
, ri
), 32, 32);
8213 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
8214 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
8215 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
8217 .accessfn
= access_tid4
,
8218 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8221 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8224 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8225 return CP_ACCESS_TRAP_EL2
;
8228 return CP_ACCESS_OK
;
8231 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8234 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8235 return access_aa64_tid3(env
, ri
, isread
);
8238 return CP_ACCESS_OK
;
8241 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8244 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8245 return CP_ACCESS_TRAP_EL2
;
8248 return CP_ACCESS_OK
;
8251 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8252 const ARMCPRegInfo
*ri
, bool isread
)
8255 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8256 * in v7A, not in v8A.
8258 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8259 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8260 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8261 return CP_ACCESS_TRAP_EL2
;
8263 return CP_ACCESS_OK
;
8266 static const ARMCPRegInfo jazelle_regs
[] = {
8268 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8269 .access
= PL1_R
, .accessfn
= access_jazelle
,
8270 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8272 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8273 .accessfn
= access_joscr_jmcr
,
8274 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8276 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8277 .accessfn
= access_joscr_jmcr
,
8278 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8281 static const ARMCPRegInfo contextidr_el2
= {
8282 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8283 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8285 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8288 static const ARMCPRegInfo vhe_reginfo
[] = {
8289 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8290 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8291 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8292 .raw_writefn
= raw_write
,
8293 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8294 #ifndef CONFIG_USER_ONLY
8295 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8296 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8298 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8299 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8300 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8301 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8302 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8303 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8304 .resetfn
= gt_hv_timer_reset
,
8305 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8306 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8308 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8310 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8311 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8312 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8313 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8314 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8315 .access
= PL2_RW
, .accessfn
= e2h_access
,
8316 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8317 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8318 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8319 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8320 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8321 .access
= PL2_RW
, .accessfn
= e2h_access
,
8322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8323 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8324 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8325 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8326 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8327 .access
= PL2_RW
, .accessfn
= e2h_access
,
8328 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8329 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8330 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8331 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8332 .access
= PL2_RW
, .accessfn
= e2h_access
,
8333 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8334 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8335 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8336 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8337 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8338 .access
= PL2_RW
, .accessfn
= e2h_access
,
8339 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8340 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8341 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8342 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8343 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8344 .access
= PL2_RW
, .accessfn
= e2h_access
,
8345 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8349 #ifndef CONFIG_USER_ONLY
8350 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8351 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8352 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8353 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8354 .fgt
= FGT_ATS1E1RP
,
8355 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8356 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8357 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8358 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8359 .fgt
= FGT_ATS1E1WP
,
8360 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8363 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8364 { .name
= "ATS1CPRP",
8365 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8366 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8367 .writefn
= ats_write
},
8368 { .name
= "ATS1CPWP",
8369 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8370 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8371 .writefn
= ats_write
},
8376 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8377 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8378 * is non-zero, which is never for ARMv7, optionally in ARMv8
8379 * and mandatorily for ARMv8.2 and up.
8380 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8381 * implementation is RAZ/WI we can ignore this detail, as we
8384 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8385 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8386 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8387 .access
= PL1_RW
, .accessfn
= access_tacr
,
8388 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8389 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8390 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8391 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8395 void register_cp_regs_for_features(ARMCPU
*cpu
)
8397 /* Register all the coprocessor registers based on feature bits */
8398 CPUARMState
*env
= &cpu
->env
;
8399 if (arm_feature(env
, ARM_FEATURE_M
)) {
8400 /* M profile has no coprocessor registers */
8404 define_arm_cp_regs(cpu
, cp_reginfo
);
8405 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8407 * Must go early as it is full of wildcards that may be
8408 * overridden by later definitions.
8410 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8413 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8414 /* The ID registers all have impdef reset values */
8415 ARMCPRegInfo v6_idregs
[] = {
8416 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8417 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8418 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8419 .accessfn
= access_aa32_tid3
,
8420 .resetvalue
= cpu
->isar
.id_pfr0
},
8422 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8423 * the value of the GIC field until after we define these regs.
8425 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8426 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8427 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8428 .accessfn
= access_aa32_tid3
,
8429 #ifdef CONFIG_USER_ONLY
8430 .type
= ARM_CP_CONST
,
8431 .resetvalue
= cpu
->isar
.id_pfr1
,
8433 .type
= ARM_CP_NO_RAW
,
8434 .accessfn
= access_aa32_tid3
,
8435 .readfn
= id_pfr1_read
,
8436 .writefn
= arm_cp_write_ignore
8439 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8440 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8441 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8442 .accessfn
= access_aa32_tid3
,
8443 .resetvalue
= cpu
->isar
.id_dfr0
},
8444 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8445 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8446 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8447 .accessfn
= access_aa32_tid3
,
8448 .resetvalue
= cpu
->id_afr0
},
8449 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8450 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8451 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8452 .accessfn
= access_aa32_tid3
,
8453 .resetvalue
= cpu
->isar
.id_mmfr0
},
8454 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8455 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8456 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8457 .accessfn
= access_aa32_tid3
,
8458 .resetvalue
= cpu
->isar
.id_mmfr1
},
8459 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8460 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8461 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8462 .accessfn
= access_aa32_tid3
,
8463 .resetvalue
= cpu
->isar
.id_mmfr2
},
8464 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8465 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8466 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8467 .accessfn
= access_aa32_tid3
,
8468 .resetvalue
= cpu
->isar
.id_mmfr3
},
8469 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8470 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8471 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8472 .accessfn
= access_aa32_tid3
,
8473 .resetvalue
= cpu
->isar
.id_isar0
},
8474 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8475 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8476 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8477 .accessfn
= access_aa32_tid3
,
8478 .resetvalue
= cpu
->isar
.id_isar1
},
8479 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8480 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8481 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8482 .accessfn
= access_aa32_tid3
,
8483 .resetvalue
= cpu
->isar
.id_isar2
},
8484 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8485 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8486 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8487 .accessfn
= access_aa32_tid3
,
8488 .resetvalue
= cpu
->isar
.id_isar3
},
8489 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8490 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8491 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8492 .accessfn
= access_aa32_tid3
,
8493 .resetvalue
= cpu
->isar
.id_isar4
},
8494 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8495 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8496 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8497 .accessfn
= access_aa32_tid3
,
8498 .resetvalue
= cpu
->isar
.id_isar5
},
8499 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8500 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8501 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8502 .accessfn
= access_aa32_tid3
,
8503 .resetvalue
= cpu
->isar
.id_mmfr4
},
8504 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8505 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8506 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8507 .accessfn
= access_aa32_tid3
,
8508 .resetvalue
= cpu
->isar
.id_isar6
},
8510 define_arm_cp_regs(cpu
, v6_idregs
);
8511 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8513 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8515 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8516 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8518 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8519 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8520 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8522 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8523 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8525 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8526 ARMCPRegInfo clidr
= {
8527 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8528 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8529 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8530 .accessfn
= access_tid4
,
8531 .fgt
= FGT_CLIDR_EL1
,
8532 .resetvalue
= cpu
->clidr
8534 define_one_arm_cp_reg(cpu
, &clidr
);
8535 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8536 define_debug_regs(cpu
);
8537 define_pmu_regs(cpu
);
8539 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8541 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8543 * v8 ID registers, which all have impdef reset values.
8544 * Note that within the ID register ranges the unused slots
8545 * must all RAZ, not UNDEF; future architecture versions may
8546 * define new registers here.
8547 * ID registers which are AArch64 views of the AArch32 ID registers
8548 * which already existed in v6 and v7 are handled elsewhere,
8552 ARMCPRegInfo v8_idregs
[] = {
8554 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8555 * emulation because we don't know the right value for the
8556 * GIC field until after we define these regs.
8558 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8559 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8561 #ifdef CONFIG_USER_ONLY
8562 .type
= ARM_CP_CONST
,
8563 .resetvalue
= cpu
->isar
.id_aa64pfr0
8565 .type
= ARM_CP_NO_RAW
,
8566 .accessfn
= access_aa64_tid3
,
8567 .readfn
= id_aa64pfr0_read
,
8568 .writefn
= arm_cp_write_ignore
8571 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8572 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8573 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8574 .accessfn
= access_aa64_tid3
,
8575 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8576 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8577 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8578 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8579 .accessfn
= access_aa64_tid3
,
8581 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8582 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8583 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8584 .accessfn
= access_aa64_tid3
,
8586 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8587 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8588 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8589 .accessfn
= access_aa64_tid3
,
8590 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8591 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8592 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8593 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8594 .accessfn
= access_aa64_tid3
,
8595 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8596 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8597 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8598 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8599 .accessfn
= access_aa64_tid3
,
8601 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8602 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8603 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8604 .accessfn
= access_aa64_tid3
,
8606 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8607 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8608 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8609 .accessfn
= access_aa64_tid3
,
8610 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8611 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8612 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8613 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8614 .accessfn
= access_aa64_tid3
,
8615 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8616 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8617 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8618 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8619 .accessfn
= access_aa64_tid3
,
8621 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8622 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8623 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8624 .accessfn
= access_aa64_tid3
,
8626 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8627 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8628 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8629 .accessfn
= access_aa64_tid3
,
8630 .resetvalue
= cpu
->id_aa64afr0
},
8631 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8632 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8633 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8634 .accessfn
= access_aa64_tid3
,
8635 .resetvalue
= cpu
->id_aa64afr1
},
8636 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8637 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8638 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8639 .accessfn
= access_aa64_tid3
,
8641 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8642 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8643 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8644 .accessfn
= access_aa64_tid3
,
8646 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8647 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8648 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8649 .accessfn
= access_aa64_tid3
,
8650 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8651 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8652 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8653 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8654 .accessfn
= access_aa64_tid3
,
8655 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8656 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8657 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8658 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8659 .accessfn
= access_aa64_tid3
,
8660 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8661 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8662 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8663 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8664 .accessfn
= access_aa64_tid3
,
8666 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8667 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8668 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8669 .accessfn
= access_aa64_tid3
,
8671 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8672 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8673 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8674 .accessfn
= access_aa64_tid3
,
8676 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8677 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8678 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8679 .accessfn
= access_aa64_tid3
,
8681 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8682 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8683 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8684 .accessfn
= access_aa64_tid3
,
8686 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8687 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8688 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8689 .accessfn
= access_aa64_tid3
,
8690 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8691 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8692 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8693 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8694 .accessfn
= access_aa64_tid3
,
8695 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8696 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8697 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8698 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8699 .accessfn
= access_aa64_tid3
,
8700 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8701 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8702 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8703 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8704 .accessfn
= access_aa64_tid3
,
8706 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8707 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8708 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8709 .accessfn
= access_aa64_tid3
,
8711 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8712 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8713 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8714 .accessfn
= access_aa64_tid3
,
8716 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8717 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8718 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8719 .accessfn
= access_aa64_tid3
,
8721 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8722 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8723 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8724 .accessfn
= access_aa64_tid3
,
8726 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8727 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8728 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8729 .accessfn
= access_aa64_tid3
,
8730 .resetvalue
= cpu
->isar
.mvfr0
},
8731 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8732 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8733 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8734 .accessfn
= access_aa64_tid3
,
8735 .resetvalue
= cpu
->isar
.mvfr1
},
8736 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8737 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8738 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8739 .accessfn
= access_aa64_tid3
,
8740 .resetvalue
= cpu
->isar
.mvfr2
},
8742 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8743 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8744 * as RAZ, since it is in the "reserved for future ID
8745 * registers, RAZ" part of the AArch32 encoding space.
8747 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8748 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8749 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8750 .accessfn
= access_aa64_tid3
,
8752 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8753 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8754 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8755 .accessfn
= access_aa64_tid3
,
8757 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8758 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8759 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8760 .accessfn
= access_aa64_tid3
,
8763 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8764 * they're also RAZ for AArch64, and in v8 are gradually
8765 * being filled with AArch64-view-of-AArch32-ID-register
8766 * for new ID registers.
8768 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8769 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8770 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8771 .accessfn
= access_aa64_tid3
,
8773 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8774 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8775 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8776 .accessfn
= access_aa64_tid3
,
8777 .resetvalue
= cpu
->isar
.id_pfr2
},
8778 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8779 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8780 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8781 .accessfn
= access_aa64_tid3
,
8782 .resetvalue
= cpu
->isar
.id_dfr1
},
8783 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8784 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8785 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8786 .accessfn
= access_aa64_tid3
,
8787 .resetvalue
= cpu
->isar
.id_mmfr5
},
8788 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8789 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8790 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8791 .accessfn
= access_aa64_tid3
,
8793 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8794 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8795 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8796 .fgt
= FGT_PMCEIDN_EL0
,
8797 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8798 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8799 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8800 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8801 .fgt
= FGT_PMCEIDN_EL0
,
8802 .resetvalue
= cpu
->pmceid0
},
8803 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8804 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8805 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8806 .fgt
= FGT_PMCEIDN_EL0
,
8807 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8808 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8809 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8810 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8811 .fgt
= FGT_PMCEIDN_EL0
,
8812 .resetvalue
= cpu
->pmceid1
},
8814 #ifdef CONFIG_USER_ONLY
8815 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8816 { .name
= "ID_AA64PFR0_EL1",
8817 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8818 R_ID_AA64PFR0_ADVSIMD_MASK
|
8819 R_ID_AA64PFR0_SVE_MASK
|
8820 R_ID_AA64PFR0_DIT_MASK
,
8821 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8822 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8823 { .name
= "ID_AA64PFR1_EL1",
8824 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8825 R_ID_AA64PFR1_SSBS_MASK
|
8826 R_ID_AA64PFR1_MTE_MASK
|
8827 R_ID_AA64PFR1_SME_MASK
},
8828 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8830 { .name
= "ID_AA64ZFR0_EL1",
8831 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8832 R_ID_AA64ZFR0_AES_MASK
|
8833 R_ID_AA64ZFR0_BITPERM_MASK
|
8834 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8835 R_ID_AA64ZFR0_SHA3_MASK
|
8836 R_ID_AA64ZFR0_SM4_MASK
|
8837 R_ID_AA64ZFR0_I8MM_MASK
|
8838 R_ID_AA64ZFR0_F32MM_MASK
|
8839 R_ID_AA64ZFR0_F64MM_MASK
},
8840 { .name
= "ID_AA64SMFR0_EL1",
8841 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8842 R_ID_AA64SMFR0_BI32I32_MASK
|
8843 R_ID_AA64SMFR0_B16F32_MASK
|
8844 R_ID_AA64SMFR0_F16F32_MASK
|
8845 R_ID_AA64SMFR0_I8I32_MASK
|
8846 R_ID_AA64SMFR0_F16F16_MASK
|
8847 R_ID_AA64SMFR0_B16B16_MASK
|
8848 R_ID_AA64SMFR0_I16I32_MASK
|
8849 R_ID_AA64SMFR0_F64F64_MASK
|
8850 R_ID_AA64SMFR0_I16I64_MASK
|
8851 R_ID_AA64SMFR0_SMEVER_MASK
|
8852 R_ID_AA64SMFR0_FA64_MASK
},
8853 { .name
= "ID_AA64MMFR0_EL1",
8854 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8855 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8856 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8857 { .name
= "ID_AA64MMFR1_EL1",
8858 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8859 { .name
= "ID_AA64MMFR2_EL1",
8860 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8861 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8863 { .name
= "ID_AA64DFR0_EL1",
8864 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8865 { .name
= "ID_AA64DFR1_EL1" },
8866 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8868 { .name
= "ID_AA64AFR*",
8870 { .name
= "ID_AA64ISAR0_EL1",
8871 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8872 R_ID_AA64ISAR0_SHA1_MASK
|
8873 R_ID_AA64ISAR0_SHA2_MASK
|
8874 R_ID_AA64ISAR0_CRC32_MASK
|
8875 R_ID_AA64ISAR0_ATOMIC_MASK
|
8876 R_ID_AA64ISAR0_RDM_MASK
|
8877 R_ID_AA64ISAR0_SHA3_MASK
|
8878 R_ID_AA64ISAR0_SM3_MASK
|
8879 R_ID_AA64ISAR0_SM4_MASK
|
8880 R_ID_AA64ISAR0_DP_MASK
|
8881 R_ID_AA64ISAR0_FHM_MASK
|
8882 R_ID_AA64ISAR0_TS_MASK
|
8883 R_ID_AA64ISAR0_RNDR_MASK
},
8884 { .name
= "ID_AA64ISAR1_EL1",
8885 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8886 R_ID_AA64ISAR1_APA_MASK
|
8887 R_ID_AA64ISAR1_API_MASK
|
8888 R_ID_AA64ISAR1_JSCVT_MASK
|
8889 R_ID_AA64ISAR1_FCMA_MASK
|
8890 R_ID_AA64ISAR1_LRCPC_MASK
|
8891 R_ID_AA64ISAR1_GPA_MASK
|
8892 R_ID_AA64ISAR1_GPI_MASK
|
8893 R_ID_AA64ISAR1_FRINTTS_MASK
|
8894 R_ID_AA64ISAR1_SB_MASK
|
8895 R_ID_AA64ISAR1_BF16_MASK
|
8896 R_ID_AA64ISAR1_DGH_MASK
|
8897 R_ID_AA64ISAR1_I8MM_MASK
},
8898 { .name
= "ID_AA64ISAR2_EL1",
8899 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8900 R_ID_AA64ISAR2_RPRES_MASK
|
8901 R_ID_AA64ISAR2_GPA3_MASK
|
8902 R_ID_AA64ISAR2_APA3_MASK
|
8903 R_ID_AA64ISAR2_MOPS_MASK
|
8904 R_ID_AA64ISAR2_BC_MASK
|
8905 R_ID_AA64ISAR2_RPRFM_MASK
|
8906 R_ID_AA64ISAR2_CSSC_MASK
},
8907 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8910 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8913 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8914 * TODO: For RMR, a write with bit 1 set should do something with
8915 * cpu_reset(). In the meantime, "the bit is strictly a request",
8916 * so we are in spec just ignoring writes.
8918 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8919 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8920 ARMCPRegInfo el1_reset_regs
[] = {
8921 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8922 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8924 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8925 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8926 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8927 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8928 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8930 define_arm_cp_regs(cpu
, el1_reset_regs
);
8932 define_arm_cp_regs(cpu
, v8_idregs
);
8933 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8934 if (cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
8935 define_arm_cp_regs(cpu
, v8_aa32_el1_reginfo
);
8938 for (i
= 4; i
< 16; i
++) {
8940 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8941 * For pre-v8 cores there are RAZ patterns for these in
8942 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8943 * v8 extends the "must RAZ" part of the ID register space
8944 * to also cover c0, 0, c{8-15}, {0-7}.
8945 * These are STATE_AA32 because in the AArch64 sysreg space
8946 * c4-c7 is where the AArch64 ID registers live (and we've
8947 * already defined those in v8_idregs[]), and c8-c15 are not
8948 * "must RAZ" for AArch64.
8950 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8951 ARMCPRegInfo v8_aa32_raz_idregs
= {
8953 .state
= ARM_CP_STATE_AA32
,
8954 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8955 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8956 .accessfn
= access_aa64_tid3
,
8958 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8963 * Register the base EL2 cpregs.
8964 * Pre v8, these registers are implemented only as part of the
8965 * Virtualization Extensions (EL2 present). Beginning with v8,
8966 * if EL2 is missing but EL3 is enabled, mostly these become
8967 * RES0 from EL3, with some specific exceptions.
8969 if (arm_feature(env
, ARM_FEATURE_EL2
)
8970 || (arm_feature(env
, ARM_FEATURE_EL3
)
8971 && arm_feature(env
, ARM_FEATURE_V8
))) {
8972 uint64_t vmpidr_def
= mpidr_read_val(env
);
8973 ARMCPRegInfo vpidr_regs
[] = {
8974 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8975 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8976 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8977 .resetvalue
= cpu
->midr
,
8978 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8979 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8980 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8981 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8982 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8983 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8984 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8985 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8986 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8987 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8988 .resetvalue
= vmpidr_def
,
8989 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8990 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8991 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8992 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8993 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8994 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8995 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8998 * The only field of MDCR_EL2 that has a defined architectural reset
8999 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
9001 ARMCPRegInfo mdcr_el2
= {
9002 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
9003 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
9004 .writefn
= mdcr_el2_write
,
9005 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
9006 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
9008 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
9009 define_arm_cp_regs(cpu
, vpidr_regs
);
9010 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
9011 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9012 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
9014 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
9015 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
9018 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
9019 * See commentary near RMR_EL1.
9021 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
9022 static const ARMCPRegInfo el2_reset_regs
[] = {
9023 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
9024 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
9026 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9027 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
9028 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
9030 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9031 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
9032 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
9033 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9035 define_arm_cp_regs(cpu
, el2_reset_regs
);
9039 /* Register the base EL3 cpregs. */
9040 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9041 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
9042 ARMCPRegInfo el3_regs
[] = {
9043 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
9044 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
9046 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
9047 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
9048 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
9049 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9050 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
9051 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
9052 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9053 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
9054 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9055 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
9057 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
9058 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
9059 .resetvalue
= cpu
->reset_sctlr
},
9062 define_arm_cp_regs(cpu
, el3_regs
);
9065 * The behaviour of NSACR is sufficiently various that we don't
9066 * try to describe it in a single reginfo:
9067 * if EL3 is 64 bit, then trap to EL3 from S EL1,
9068 * reads as constant 0xc00 from NS EL1 and NS EL2
9069 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
9070 * if v7 without EL3, register doesn't exist
9071 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
9073 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9074 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9075 static const ARMCPRegInfo nsacr
= {
9076 .name
= "NSACR", .type
= ARM_CP_CONST
,
9077 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9078 .access
= PL1_RW
, .accessfn
= nsacr_access
,
9081 define_one_arm_cp_reg(cpu
, &nsacr
);
9083 static const ARMCPRegInfo nsacr
= {
9085 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9086 .access
= PL3_RW
| PL1_R
,
9088 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
9090 define_one_arm_cp_reg(cpu
, &nsacr
);
9093 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9094 static const ARMCPRegInfo nsacr
= {
9095 .name
= "NSACR", .type
= ARM_CP_CONST
,
9096 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9100 define_one_arm_cp_reg(cpu
, &nsacr
);
9104 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9105 if (arm_feature(env
, ARM_FEATURE_V6
)) {
9106 /* PMSAv6 not implemented */
9107 assert(arm_feature(env
, ARM_FEATURE_V7
));
9108 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9109 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
9111 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
9114 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9115 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
9116 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
9117 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
9118 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
9121 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
9122 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
9124 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
9125 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
9127 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
9128 ARMCPRegInfo vapa_cp_reginfo
[] = {
9129 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
9130 .access
= PL1_RW
, .resetvalue
= 0,
9131 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
9132 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
9133 .writefn
= par_write
},
9134 #ifndef CONFIG_USER_ONLY
9135 /* This underdecoding is safe because the reginfo is NO_RAW. */
9136 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
9137 .access
= PL1_W
, .accessfn
= ats_access
,
9138 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
9143 * When LPAE exists this 32-bit PAR register is an alias of the
9144 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
9146 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9147 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9149 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
9151 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
9152 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
9154 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
9155 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
9157 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
9158 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
9160 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
9161 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
9163 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9164 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
9166 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9167 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
9169 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
9170 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
9172 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9173 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
9175 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
9176 define_arm_cp_regs(cpu
, jazelle_regs
);
9179 * Slightly awkwardly, the OMAP and StrongARM cores need all of
9180 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
9181 * be read-only (ie write causes UNDEF exception).
9184 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
9186 * Pre-v8 MIDR space.
9187 * Note that the MIDR isn't a simple constant register because
9188 * of the TI925 behaviour where writes to another register can
9189 * cause the MIDR value to change.
9191 * Unimplemented registers in the c15 0 0 0 space default to
9192 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
9193 * and friends override accordingly.
9196 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
9197 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
9198 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
9199 .readfn
= midr_read
,
9200 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9201 .type
= ARM_CP_OVERRIDE
},
9202 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
9204 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
9205 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9207 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
9208 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9210 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
9211 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9213 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
9214 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9216 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
9217 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9219 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
9220 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9221 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
9222 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
9223 .fgt
= FGT_MIDR_EL1
,
9224 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9225 .readfn
= midr_read
},
9226 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
9227 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
9228 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
9229 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
9230 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9231 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
9233 .accessfn
= access_aa64_tid1
,
9234 .fgt
= FGT_REVIDR_EL1
,
9235 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9237 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9238 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9239 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9240 .access
= PL1_R
, .resetvalue
= cpu
->midr
9242 ARMCPRegInfo id_cp_reginfo
[] = {
9243 /* These are common to v8 and pre-v8 */
9245 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9246 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9247 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9248 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9249 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9250 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9252 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9253 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9255 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9257 .accessfn
= access_aa32_tid1
,
9258 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9260 /* TLBTR is specific to VMSA */
9261 ARMCPRegInfo id_tlbtr_reginfo
= {
9263 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9265 .accessfn
= access_aa32_tid1
,
9266 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9268 /* MPUIR is specific to PMSA V6+ */
9269 ARMCPRegInfo id_mpuir_reginfo
= {
9271 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9272 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9273 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9275 /* HMPUIR is specific to PMSA V8 */
9276 ARMCPRegInfo id_hmpuir_reginfo
= {
9278 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9279 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9280 .resetvalue
= cpu
->pmsav8r_hdregion
9282 static const ARMCPRegInfo crn0_wi_reginfo
= {
9283 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9284 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9285 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9287 #ifdef CONFIG_USER_ONLY
9288 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9289 { .name
= "MIDR_EL1",
9290 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9291 R_MIDR_EL1_PARTNUM_MASK
|
9292 R_MIDR_EL1_ARCHITECTURE_MASK
|
9293 R_MIDR_EL1_VARIANT_MASK
|
9294 R_MIDR_EL1_IMPLEMENTER_MASK
},
9295 { .name
= "REVIDR_EL1" },
9297 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9299 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9300 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9303 * Register the blanket "writes ignored" value first to cover the
9304 * whole space. Then update the specific ID registers to allow write
9305 * access, so that they ignore writes rather than causing them to
9308 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9309 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9310 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9312 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9313 id_cp_reginfo
[i
].access
= PL1_RW
;
9315 id_mpuir_reginfo
.access
= PL1_RW
;
9316 id_tlbtr_reginfo
.access
= PL1_RW
;
9318 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9319 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9320 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9321 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9324 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9326 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9327 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9328 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9329 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9330 arm_feature(env
, ARM_FEATURE_V8
)) {
9334 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9335 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9336 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9338 /* Register alias is only valid for first 32 indexes */
9339 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9340 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9341 uint8_t opc1
= extract32(i
, 4, 1);
9342 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9344 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9345 ARMCPRegInfo tmp_prbarn_reginfo
= {
9346 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9347 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9348 .access
= PL1_RW
, .resetvalue
= 0,
9349 .accessfn
= access_tvm_trvm
,
9350 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9352 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9355 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9356 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9357 ARMCPRegInfo tmp_prlarn_reginfo
= {
9358 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9359 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9360 .access
= PL1_RW
, .resetvalue
= 0,
9361 .accessfn
= access_tvm_trvm
,
9362 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9364 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9368 /* Register alias is only valid for first 32 indexes */
9369 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9370 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9371 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9372 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9374 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9375 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9377 .type
= ARM_CP_NO_RAW
,
9378 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9379 .access
= PL2_RW
, .resetvalue
= 0,
9380 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9382 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9385 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9386 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9387 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9389 .type
= ARM_CP_NO_RAW
,
9390 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9391 .access
= PL2_RW
, .resetvalue
= 0,
9392 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9394 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9397 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9398 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9402 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9403 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9404 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9405 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9406 .fgt
= FGT_MPIDR_EL1
,
9407 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9409 #ifdef CONFIG_USER_ONLY
9410 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9411 { .name
= "MPIDR_EL1",
9412 .fixed_bits
= 0x0000000080000000 },
9414 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9416 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9419 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9420 ARMCPRegInfo auxcr_reginfo
[] = {
9421 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9422 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9423 .access
= PL1_RW
, .accessfn
= access_tacr
,
9424 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9425 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9426 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9427 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9429 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9430 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9431 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9434 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9435 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9436 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9440 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9442 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9443 * There are two flavours:
9444 * (1) older 32-bit only cores have a simple 32-bit CBAR
9445 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9446 * 32-bit register visible to AArch32 at a different encoding
9447 * to the "flavour 1" register and with the bits rearranged to
9448 * be able to squash a 64-bit address into the 32-bit view.
9449 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9450 * in future if we support AArch32-only configs of some of the
9451 * AArch64 cores we might need to add a specific feature flag
9452 * to indicate cores with "flavour 2" CBAR.
9454 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9455 /* 32 bit view is [31:18] 0...0 [43:32]. */
9456 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9457 | extract64(cpu
->reset_cbar
, 32, 12);
9458 ARMCPRegInfo cbar_reginfo
[] = {
9460 .type
= ARM_CP_CONST
,
9461 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9462 .access
= PL1_R
, .resetvalue
= cbar32
},
9463 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9464 .type
= ARM_CP_CONST
,
9465 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9466 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9468 /* We don't implement a r/w 64 bit CBAR currently */
9469 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9470 define_arm_cp_regs(cpu
, cbar_reginfo
);
9472 ARMCPRegInfo cbar
= {
9474 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9475 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9476 .fieldoffset
= offsetof(CPUARMState
,
9477 cp15
.c15_config_base_address
)
9479 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9480 cbar
.access
= PL1_R
;
9481 cbar
.fieldoffset
= 0;
9482 cbar
.type
= ARM_CP_CONST
;
9484 define_one_arm_cp_reg(cpu
, &cbar
);
9488 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9489 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9490 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9491 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9492 .access
= PL1_RW
, .writefn
= vbar_write
,
9493 .accessfn
= access_nv1
,
9494 .fgt
= FGT_VBAR_EL1
,
9495 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9496 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9499 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9502 /* Generic registers whose values depend on the implementation */
9504 ARMCPRegInfo sctlr
= {
9505 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9506 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9507 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9508 .fgt
= FGT_SCTLR_EL1
,
9509 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9510 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9511 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9512 .raw_writefn
= raw_write
,
9514 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9516 * Normally we would always end the TB on an SCTLR write, but Linux
9517 * arch/arm/mach-pxa/sleep.S expects two instructions following
9518 * an MMU enable to execute from cache. Imitate this behaviour.
9520 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9522 define_one_arm_cp_reg(cpu
, &sctlr
);
9524 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9525 arm_feature(env
, ARM_FEATURE_V8
)) {
9526 ARMCPRegInfo vsctlr
= {
9527 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9528 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9529 .access
= PL2_RW
, .resetvalue
= 0x0,
9530 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9532 define_one_arm_cp_reg(cpu
, &vsctlr
);
9536 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9537 define_arm_cp_regs(cpu
, lor_reginfo
);
9539 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9540 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9542 #ifndef CONFIG_USER_ONLY
9543 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9544 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9546 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9547 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9550 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9551 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9554 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9555 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9557 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9558 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9560 if (cpu_isar_feature(any_ras
, cpu
)) {
9561 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9564 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9565 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9566 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9568 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9569 define_arm_cp_regs(cpu
, vhe_reginfo
);
9572 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9573 define_arm_cp_regs(cpu
, zcr_reginfo
);
9576 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9577 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9580 #ifdef TARGET_AARCH64
9581 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9582 define_arm_cp_regs(cpu
, sme_reginfo
);
9584 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9585 define_arm_cp_regs(cpu
, pauth_reginfo
);
9587 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9588 define_arm_cp_regs(cpu
, rndr_reginfo
);
9590 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9591 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9593 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9594 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9596 /* Data Cache clean instructions up to PoP */
9597 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9598 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9600 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9601 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9606 * If full MTE is enabled, add all of the system registers.
9607 * If only "instructions available at EL0" are enabled,
9608 * then define only a RAZ/WI version of PSTATE.TCO.
9610 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9611 ARMCPRegInfo gmid_reginfo
= {
9612 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9613 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9614 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9615 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9617 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9618 define_arm_cp_regs(cpu
, mte_reginfo
);
9619 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9620 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9621 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9622 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9625 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9626 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9629 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9630 define_arm_cp_regs(cpu
, fgt_reginfo
);
9633 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9634 define_arm_cp_regs(cpu
, rme_reginfo
);
9635 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9636 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9640 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
9641 define_arm_cp_regs(cpu
, nv2_reginfo
);
9645 if (cpu_isar_feature(any_predinv
, cpu
)) {
9646 define_arm_cp_regs(cpu
, predinv_reginfo
);
9649 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9650 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9653 #ifndef CONFIG_USER_ONLY
9655 * Register redirections and aliases must be done last,
9656 * after the registers from the other extensions have been defined.
9658 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9659 define_arm_vh_e2h_redirects_aliases(cpu
);
9665 * Private utility function for define_one_arm_cp_reg_with_opaque():
9666 * add a single reginfo struct to the hash table.
9668 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9669 void *opaque
, CPState state
,
9670 CPSecureState secstate
,
9671 int crm
, int opc1
, int opc2
,
9674 CPUARMState
*env
= &cpu
->env
;
9677 bool is64
= r
->type
& ARM_CP_64BIT
;
9678 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9684 case ARM_CP_STATE_AA32
:
9685 /* We assume it is a cp15 register if the .cp field is left unset. */
9686 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9689 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9691 case ARM_CP_STATE_AA64
:
9693 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9694 * cp == 0 as equivalent to the value for "standard guest-visible
9695 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9696 * in their AArch64 view (the .cp value may be non-zero for the
9697 * benefit of the AArch32 view).
9699 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9700 cp
= CP_REG_ARM64_SYSREG_CP
;
9702 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9705 g_assert_not_reached();
9708 /* Overriding of an existing definition must be explicitly requested. */
9709 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9710 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9712 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9717 * Eliminate registers that are not present because the EL is missing.
9718 * Doing this here makes it easier to put all registers for a given
9719 * feature into the same ARMCPRegInfo array and define them all at once.
9722 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9724 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9725 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9727 int min_el
= ctz32(r
->access
) / 2;
9728 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9729 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9732 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9735 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9737 if ((r
->access
& max_el
) == 0) {
9742 /* Combine cpreg and name into one allocation. */
9743 name_len
= strlen(name
) + 1;
9744 r2
= g_malloc(sizeof(*r2
) + name_len
);
9746 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9749 * Update fields to match the instantiation, overwiting wildcards
9750 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9757 r2
->secure
= secstate
;
9759 r2
->opaque
= opaque
;
9763 /* This should not have been a very special register to begin. */
9764 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9765 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9767 * Set the special function to CONST, retaining the other flags.
9768 * This is important for e.g. ARM_CP_SVE so that we still
9769 * take the SVE trap if CPTR_EL3.EZ == 0.
9771 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9773 * Usually, these registers become RES0, but there are a few
9774 * special cases like VPIDR_EL2 which have a constant non-zero
9775 * value with writes ignored.
9777 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9781 * ARM_CP_CONST has precedence, so removing the callbacks and
9782 * offsets are not strictly necessary, but it is potentially
9783 * less confusing to debug later.
9787 r2
->raw_readfn
= NULL
;
9788 r2
->raw_writefn
= NULL
;
9790 r2
->fieldoffset
= 0;
9791 r2
->bank_fieldoffsets
[0] = 0;
9792 r2
->bank_fieldoffsets
[1] = 0;
9794 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9798 * Register is banked (using both entries in array).
9799 * Overwriting fieldoffset as the array is only used to define
9800 * banked registers but later only fieldoffset is used.
9802 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9804 if (state
== ARM_CP_STATE_AA32
) {
9807 * If the register is banked then we don't need to migrate or
9808 * reset the 32-bit instance in certain cases:
9810 * 1) If the register has both 32-bit and 64-bit instances
9811 * then we can count on the 64-bit instance taking care
9812 * of the non-secure bank.
9813 * 2) If ARMv8 is enabled then we can count on a 64-bit
9814 * version taking care of the secure bank. This requires
9815 * that separate 32 and 64-bit definitions are provided.
9817 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9818 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9819 r2
->type
|= ARM_CP_ALIAS
;
9821 } else if ((secstate
!= r
->secure
) && !ns
) {
9823 * The register is not banked so we only want to allow
9824 * migration of the non-secure instance.
9826 r2
->type
|= ARM_CP_ALIAS
;
9829 if (HOST_BIG_ENDIAN
&&
9830 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9831 r2
->fieldoffset
+= sizeof(uint32_t);
9837 * By convention, for wildcarded registers only the first
9838 * entry is used for migration; the others are marked as
9839 * ALIAS so we don't try to transfer the register
9840 * multiple times. Special registers (ie NOP/WFI) are
9841 * never migratable and not even raw-accessible.
9843 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9844 r2
->type
|= ARM_CP_NO_RAW
;
9846 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9847 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9848 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9849 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9853 * Check that raw accesses are either forbidden or handled. Note that
9854 * we can't assert this earlier because the setup of fieldoffset for
9855 * banked registers has to be done first.
9857 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9858 assert(!raw_accessors_invalid(r2
));
9861 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9865 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9866 const ARMCPRegInfo
*r
, void *opaque
)
9869 * Define implementations of coprocessor registers.
9870 * We store these in a hashtable because typically
9871 * there are less than 150 registers in a space which
9872 * is 16*16*16*8*8 = 262144 in size.
9873 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9874 * If a register is defined twice then the second definition is
9875 * used, so this can be used to define some generic registers and
9876 * then override them with implementation specific variations.
9877 * At least one of the original and the second definition should
9878 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9879 * against accidental use.
9881 * The state field defines whether the register is to be
9882 * visible in the AArch32 or AArch64 execution state. If the
9883 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9884 * reginfo structure for the AArch32 view, which sees the lower
9885 * 32 bits of the 64 bit register.
9887 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9888 * be wildcarded. AArch64 registers are always considered to be 64
9889 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9890 * the register, if any.
9892 int crm
, opc1
, opc2
;
9893 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9894 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9895 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9896 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9897 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9898 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9901 /* 64 bit registers have only CRm and Opc1 fields */
9902 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9903 /* op0 only exists in the AArch64 encodings */
9904 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9905 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9906 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9908 * This API is only for Arm's system coprocessors (14 and 15) or
9909 * (M-profile or v7A-and-earlier only) for implementation defined
9910 * coprocessors in the range 0..7. Our decode assumes this, since
9911 * 8..13 can be used for other insns including VFP and Neon. See
9912 * valid_cp() in translate.c. Assert here that we haven't tried
9913 * to use an invalid coprocessor number.
9916 case ARM_CP_STATE_BOTH
:
9917 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9922 case ARM_CP_STATE_AA32
:
9923 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9924 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9925 assert(r
->cp
>= 14 && r
->cp
<= 15);
9927 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9930 case ARM_CP_STATE_AA64
:
9931 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9934 g_assert_not_reached();
9937 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9938 * encodes a minimum access level for the register. We roll this
9939 * runtime check into our general permission check code, so check
9940 * here that the reginfo's specified permissions are strict enough
9941 * to encompass the generic architectural permission check.
9943 if (r
->state
!= ARM_CP_STATE_AA32
) {
9944 CPAccessRights mask
;
9947 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9948 mask
= PL0U_R
| PL1_RW
;
9968 /* min_EL EL1, secure mode only (we don't check the latter) */
9972 /* broken reginfo with out-of-range opc1 */
9973 g_assert_not_reached();
9975 /* assert our permissions are not too lax (stricter is fine) */
9976 assert((r
->access
& ~mask
) == 0);
9980 * Check that the register definition has enough info to handle
9981 * reads and writes if they are permitted.
9983 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9984 if (r
->access
& PL3_R
) {
9985 assert((r
->fieldoffset
||
9986 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9989 if (r
->access
& PL3_W
) {
9990 assert((r
->fieldoffset
||
9991 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9996 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9997 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9998 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9999 for (state
= ARM_CP_STATE_AA32
;
10000 state
<= ARM_CP_STATE_AA64
; state
++) {
10001 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
10004 if (state
== ARM_CP_STATE_AA32
) {
10006 * Under AArch32 CP registers can be common
10007 * (same for secure and non-secure world) or banked.
10011 switch (r
->secure
) {
10012 case ARM_CP_SECSTATE_S
:
10013 case ARM_CP_SECSTATE_NS
:
10014 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10015 r
->secure
, crm
, opc1
, opc2
,
10018 case ARM_CP_SECSTATE_BOTH
:
10019 name
= g_strdup_printf("%s_S", r
->name
);
10020 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10022 crm
, opc1
, opc2
, name
);
10024 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10025 ARM_CP_SECSTATE_NS
,
10026 crm
, opc1
, opc2
, r
->name
);
10029 g_assert_not_reached();
10033 * AArch64 registers get mapped to non-secure instance
10036 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10037 ARM_CP_SECSTATE_NS
,
10038 crm
, opc1
, opc2
, r
->name
);
10046 /* Define a whole list of registers */
10047 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
10048 void *opaque
, size_t len
)
10051 for (i
= 0; i
< len
; ++i
) {
10052 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
10057 * Modify ARMCPRegInfo for access from userspace.
10059 * This is a data driven modification directed by
10060 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
10061 * user-space cannot alter any values and dynamic values pertaining to
10062 * execution state are hidden from user space view anyway.
10064 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
10065 const ARMCPRegUserSpaceInfo
*mods
,
10068 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
10069 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
10070 GPatternSpec
*pat
= NULL
;
10073 pat
= g_pattern_spec_new(m
->name
);
10075 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
10076 ARMCPRegInfo
*r
= regs
+ ri
;
10078 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
10079 r
->type
= ARM_CP_CONST
;
10080 r
->access
= PL0U_R
;
10083 } else if (strcmp(r
->name
, m
->name
) == 0) {
10084 r
->type
= ARM_CP_CONST
;
10085 r
->access
= PL0U_R
;
10086 r
->resetvalue
&= m
->exported_bits
;
10087 r
->resetvalue
|= m
->fixed_bits
;
10092 g_pattern_spec_free(pat
);
10097 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
10099 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
10102 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
10105 /* Helper coprocessor write function for write-ignore registers */
10108 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
10110 /* Helper coprocessor write function for read-as-zero registers */
10114 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
10116 /* Helper coprocessor reset function for do-nothing-on-reset registers */
10119 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
10122 * Return true if it is not valid for us to switch to
10123 * this CPU mode (ie all the UNPREDICTABLE cases in
10124 * the ARM ARM CPSRWriteByInstr pseudocode).
10127 /* Changes to or from Hyp via MSR and CPS are illegal. */
10128 if (write_type
== CPSRWriteByInstr
&&
10129 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
10130 mode
== ARM_CPU_MODE_HYP
)) {
10135 case ARM_CPU_MODE_USR
:
10137 case ARM_CPU_MODE_SYS
:
10138 case ARM_CPU_MODE_SVC
:
10139 case ARM_CPU_MODE_ABT
:
10140 case ARM_CPU_MODE_UND
:
10141 case ARM_CPU_MODE_IRQ
:
10142 case ARM_CPU_MODE_FIQ
:
10144 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
10145 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
10148 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
10149 * and CPS are treated as illegal mode changes.
10151 if (write_type
== CPSRWriteByInstr
&&
10152 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
10153 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
10157 case ARM_CPU_MODE_HYP
:
10158 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
10159 case ARM_CPU_MODE_MON
:
10160 return arm_current_el(env
) < 3;
10166 uint32_t cpsr_read(CPUARMState
*env
)
10169 ZF
= (env
->ZF
== 0);
10170 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
10171 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
10172 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
10173 | ((env
->condexec_bits
& 0xfc) << 8)
10174 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
10177 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
10178 CPSRWriteType write_type
)
10180 uint32_t changed_daif
;
10181 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
10182 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
10184 if (mask
& CPSR_NZCV
) {
10185 env
->ZF
= (~val
) & CPSR_Z
;
10187 env
->CF
= (val
>> 29) & 1;
10188 env
->VF
= (val
<< 3) & 0x80000000;
10190 if (mask
& CPSR_Q
) {
10191 env
->QF
= ((val
& CPSR_Q
) != 0);
10193 if (mask
& CPSR_T
) {
10194 env
->thumb
= ((val
& CPSR_T
) != 0);
10196 if (mask
& CPSR_IT_0_1
) {
10197 env
->condexec_bits
&= ~3;
10198 env
->condexec_bits
|= (val
>> 25) & 3;
10200 if (mask
& CPSR_IT_2_7
) {
10201 env
->condexec_bits
&= 3;
10202 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10204 if (mask
& CPSR_GE
) {
10205 env
->GE
= (val
>> 16) & 0xf;
10209 * In a V7 implementation that includes the security extensions but does
10210 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10211 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10212 * bits respectively.
10214 * In a V8 implementation, it is permitted for privileged software to
10215 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10217 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10218 arm_feature(env
, ARM_FEATURE_EL3
) &&
10219 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10220 !arm_is_secure(env
)) {
10222 changed_daif
= (env
->daif
^ val
) & mask
;
10224 if (changed_daif
& CPSR_A
) {
10226 * Check to see if we are allowed to change the masking of async
10227 * abort exceptions from a non-secure state.
10229 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10230 qemu_log_mask(LOG_GUEST_ERROR
,
10231 "Ignoring attempt to switch CPSR_A flag from "
10232 "non-secure world with SCR.AW bit clear\n");
10237 if (changed_daif
& CPSR_F
) {
10239 * Check to see if we are allowed to change the masking of FIQ
10240 * exceptions from a non-secure state.
10242 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10243 qemu_log_mask(LOG_GUEST_ERROR
,
10244 "Ignoring attempt to switch CPSR_F flag from "
10245 "non-secure world with SCR.FW bit clear\n");
10250 * Check whether non-maskable FIQ (NMFI) support is enabled.
10251 * If this bit is set software is not allowed to mask
10252 * FIQs, but is allowed to set CPSR_F to 0.
10254 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10256 qemu_log_mask(LOG_GUEST_ERROR
,
10257 "Ignoring attempt to enable CPSR_F flag "
10258 "(non-maskable FIQ [NMFI] support enabled)\n");
10264 env
->daif
&= ~(CPSR_AIF
& mask
);
10265 env
->daif
|= val
& CPSR_AIF
& mask
;
10267 if (write_type
!= CPSRWriteRaw
&&
10268 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10269 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10271 * Note that we can only get here in USR mode if this is a
10272 * gdb stub write; for this case we follow the architectural
10273 * behaviour for guest writes in USR mode of ignoring an attempt
10274 * to switch mode. (Those are caught by translate.c for writes
10275 * triggered by guest instructions.)
10278 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10280 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10281 * v7, and has defined behaviour in v8:
10282 * + leave CPSR.M untouched
10283 * + allow changes to the other CPSR fields
10285 * For user changes via the GDB stub, we don't set PSTATE.IL,
10286 * as this would be unnecessarily harsh for a user error.
10289 if (write_type
!= CPSRWriteByGDBStub
&&
10290 arm_feature(env
, ARM_FEATURE_V8
)) {
10294 qemu_log_mask(LOG_GUEST_ERROR
,
10295 "Illegal AArch32 mode switch attempt from %s to %s\n",
10296 aarch32_mode_name(env
->uncached_cpsr
),
10297 aarch32_mode_name(val
));
10299 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10300 write_type
== CPSRWriteExceptionReturn
?
10301 "Exception return from AArch32" :
10302 "AArch32 mode switch from",
10303 aarch32_mode_name(env
->uncached_cpsr
),
10304 aarch32_mode_name(val
), env
->regs
[15]);
10305 switch_mode(env
, val
& CPSR_M
);
10308 mask
&= ~CACHED_CPSR_BITS
;
10309 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10310 if (tcg_enabled() && rebuild_hflags
) {
10311 arm_rebuild_hflags(env
);
10315 #ifdef CONFIG_USER_ONLY
10317 static void switch_mode(CPUARMState
*env
, int mode
)
10319 ARMCPU
*cpu
= env_archcpu(env
);
10321 if (mode
!= ARM_CPU_MODE_USR
) {
10322 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10326 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10327 uint32_t cur_el
, bool secure
)
10332 void aarch64_sync_64_to_32(CPUARMState
*env
)
10334 g_assert_not_reached();
10339 static void switch_mode(CPUARMState
*env
, int mode
)
10344 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10345 if (mode
== old_mode
) {
10349 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10350 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10351 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10352 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10353 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10354 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10357 i
= bank_number(old_mode
);
10358 env
->banked_r13
[i
] = env
->regs
[13];
10359 env
->banked_spsr
[i
] = env
->spsr
;
10361 i
= bank_number(mode
);
10362 env
->regs
[13] = env
->banked_r13
[i
];
10363 env
->spsr
= env
->banked_spsr
[i
];
10365 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10366 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10370 * Physical Interrupt Target EL Lookup Table
10372 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10374 * The below multi-dimensional table is used for looking up the target
10375 * exception level given numerous condition criteria. Specifically, the
10376 * target EL is based on SCR and HCR routing controls as well as the
10377 * currently executing EL and secure state.
10380 * target_el_table[2][2][2][2][2][4]
10381 * | | | | | +--- Current EL
10382 * | | | | +------ Non-secure(0)/Secure(1)
10383 * | | | +--------- HCR mask override
10384 * | | +------------ SCR exec state control
10385 * | +--------------- SCR mask override
10386 * +------------------ 32-bit(0)/64-bit(1) EL3
10388 * The table values are as such:
10390 * -1 = Cannot occur
10392 * The ARM ARM target EL table includes entries indicating that an "exception
10393 * is not taken". The two cases where this is applicable are:
10394 * 1) An exception is taken from EL3 but the SCR does not have the exception
10396 * 2) An exception is taken from EL2 but the HCR does not have the exception
10398 * In these two cases, the below table contain a target of EL1. This value is
10399 * returned as it is expected that the consumer of the table data will check
10400 * for "target EL >= current EL" to ensure the exception is not taken.
10404 * BIT IRQ IMO Non-secure Secure
10405 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10407 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10408 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10409 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10410 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10411 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10412 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10413 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10414 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10415 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10416 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10417 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10418 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10419 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10420 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10421 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10422 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10423 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10427 * Determine the target EL for physical exceptions
10429 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10430 uint32_t cur_el
, bool secure
)
10432 CPUARMState
*env
= cpu_env(cs
);
10437 /* Is the highest EL AArch64? */
10438 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10441 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10442 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10445 * Either EL2 is the highest EL (and so the EL2 register width
10446 * is given by is64); or there is no EL2 or EL3, in which case
10447 * the value of 'rw' does not affect the table lookup anyway.
10452 hcr_el2
= arm_hcr_el2_eff(env
);
10453 switch (excp_idx
) {
10455 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10456 hcr
= hcr_el2
& HCR_IMO
;
10459 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10460 hcr
= hcr_el2
& HCR_FMO
;
10463 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10464 hcr
= hcr_el2
& HCR_AMO
;
10469 * For these purposes, TGE and AMO/IMO/FMO both force the
10470 * interrupt to EL2. Fold TGE into the bit extracted above.
10472 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10474 /* Perform a table-lookup for the target EL given the current state */
10475 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10477 assert(target_el
> 0);
10482 void arm_log_exception(CPUState
*cs
)
10484 int idx
= cs
->exception_index
;
10486 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10487 const char *exc
= NULL
;
10488 static const char * const excnames
[] = {
10489 [EXCP_UDEF
] = "Undefined Instruction",
10490 [EXCP_SWI
] = "SVC",
10491 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10492 [EXCP_DATA_ABORT
] = "Data Abort",
10493 [EXCP_IRQ
] = "IRQ",
10494 [EXCP_FIQ
] = "FIQ",
10495 [EXCP_BKPT
] = "Breakpoint",
10496 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10497 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10498 [EXCP_HVC
] = "Hypervisor Call",
10499 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10500 [EXCP_SMC
] = "Secure Monitor Call",
10501 [EXCP_VIRQ
] = "Virtual IRQ",
10502 [EXCP_VFIQ
] = "Virtual FIQ",
10503 [EXCP_SEMIHOST
] = "Semihosting call",
10504 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10505 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10506 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10507 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10508 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10509 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10510 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10511 [EXCP_VSERR
] = "Virtual SERR",
10512 [EXCP_GPC
] = "Granule Protection Check",
10515 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10516 exc
= excnames
[idx
];
10521 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10522 idx
, exc
, cs
->cpu_index
);
10527 * Function used to synchronize QEMU's AArch64 register set with AArch32
10528 * register set. This is necessary when switching between AArch32 and AArch64
10531 void aarch64_sync_32_to_64(CPUARMState
*env
)
10534 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10536 /* We can blanket copy R[0:7] to X[0:7] */
10537 for (i
= 0; i
< 8; i
++) {
10538 env
->xregs
[i
] = env
->regs
[i
];
10542 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10543 * Otherwise, they come from the banked user regs.
10545 if (mode
== ARM_CPU_MODE_FIQ
) {
10546 for (i
= 8; i
< 13; i
++) {
10547 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10550 for (i
= 8; i
< 13; i
++) {
10551 env
->xregs
[i
] = env
->regs
[i
];
10556 * Registers x13-x23 are the various mode SP and FP registers. Registers
10557 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10558 * from the mode banked register.
10560 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10561 env
->xregs
[13] = env
->regs
[13];
10562 env
->xregs
[14] = env
->regs
[14];
10564 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10565 /* HYP is an exception in that it is copied from r14 */
10566 if (mode
== ARM_CPU_MODE_HYP
) {
10567 env
->xregs
[14] = env
->regs
[14];
10569 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10573 if (mode
== ARM_CPU_MODE_HYP
) {
10574 env
->xregs
[15] = env
->regs
[13];
10576 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10579 if (mode
== ARM_CPU_MODE_IRQ
) {
10580 env
->xregs
[16] = env
->regs
[14];
10581 env
->xregs
[17] = env
->regs
[13];
10583 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10584 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10587 if (mode
== ARM_CPU_MODE_SVC
) {
10588 env
->xregs
[18] = env
->regs
[14];
10589 env
->xregs
[19] = env
->regs
[13];
10591 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10592 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10595 if (mode
== ARM_CPU_MODE_ABT
) {
10596 env
->xregs
[20] = env
->regs
[14];
10597 env
->xregs
[21] = env
->regs
[13];
10599 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10600 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10603 if (mode
== ARM_CPU_MODE_UND
) {
10604 env
->xregs
[22] = env
->regs
[14];
10605 env
->xregs
[23] = env
->regs
[13];
10607 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10608 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10612 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10613 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10614 * FIQ bank for r8-r14.
10616 if (mode
== ARM_CPU_MODE_FIQ
) {
10617 for (i
= 24; i
< 31; i
++) {
10618 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10621 for (i
= 24; i
< 29; i
++) {
10622 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10624 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10625 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10628 env
->pc
= env
->regs
[15];
10632 * Function used to synchronize QEMU's AArch32 register set with AArch64
10633 * register set. This is necessary when switching between AArch32 and AArch64
10636 void aarch64_sync_64_to_32(CPUARMState
*env
)
10639 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10641 /* We can blanket copy X[0:7] to R[0:7] */
10642 for (i
= 0; i
< 8; i
++) {
10643 env
->regs
[i
] = env
->xregs
[i
];
10647 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10648 * Otherwise, we copy x8-x12 into the banked user regs.
10650 if (mode
== ARM_CPU_MODE_FIQ
) {
10651 for (i
= 8; i
< 13; i
++) {
10652 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10655 for (i
= 8; i
< 13; i
++) {
10656 env
->regs
[i
] = env
->xregs
[i
];
10661 * Registers r13 & r14 depend on the current mode.
10662 * If we are in a given mode, we copy the corresponding x registers to r13
10663 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10666 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10667 env
->regs
[13] = env
->xregs
[13];
10668 env
->regs
[14] = env
->xregs
[14];
10670 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10673 * HYP is an exception in that it does not have its own banked r14 but
10674 * shares the USR r14
10676 if (mode
== ARM_CPU_MODE_HYP
) {
10677 env
->regs
[14] = env
->xregs
[14];
10679 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10683 if (mode
== ARM_CPU_MODE_HYP
) {
10684 env
->regs
[13] = env
->xregs
[15];
10686 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10689 if (mode
== ARM_CPU_MODE_IRQ
) {
10690 env
->regs
[14] = env
->xregs
[16];
10691 env
->regs
[13] = env
->xregs
[17];
10693 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10694 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10697 if (mode
== ARM_CPU_MODE_SVC
) {
10698 env
->regs
[14] = env
->xregs
[18];
10699 env
->regs
[13] = env
->xregs
[19];
10701 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10702 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10705 if (mode
== ARM_CPU_MODE_ABT
) {
10706 env
->regs
[14] = env
->xregs
[20];
10707 env
->regs
[13] = env
->xregs
[21];
10709 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10710 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10713 if (mode
== ARM_CPU_MODE_UND
) {
10714 env
->regs
[14] = env
->xregs
[22];
10715 env
->regs
[13] = env
->xregs
[23];
10717 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10718 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10722 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10723 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10724 * FIQ bank for r8-r14.
10726 if (mode
== ARM_CPU_MODE_FIQ
) {
10727 for (i
= 24; i
< 31; i
++) {
10728 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10731 for (i
= 24; i
< 29; i
++) {
10732 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10734 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10735 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10738 env
->regs
[15] = env
->pc
;
10741 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10742 uint32_t mask
, uint32_t offset
,
10747 /* Change the CPU state so as to actually take the exception. */
10748 switch_mode(env
, new_mode
);
10751 * For exceptions taken to AArch32 we must clear the SS bit in both
10752 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10754 env
->pstate
&= ~PSTATE_SS
;
10755 env
->spsr
= cpsr_read(env
);
10756 /* Clear IT bits. */
10757 env
->condexec_bits
= 0;
10758 /* Switch to the new mode, and to the correct instruction set. */
10759 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10761 /* This must be after mode switching. */
10762 new_el
= arm_current_el(env
);
10764 /* Set new mode endianness */
10765 env
->uncached_cpsr
&= ~CPSR_E
;
10766 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10767 env
->uncached_cpsr
|= CPSR_E
;
10769 /* J and IL must always be cleared for exception entry */
10770 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10773 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10774 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10775 env
->uncached_cpsr
|= CPSR_SSBS
;
10777 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10781 if (new_mode
== ARM_CPU_MODE_HYP
) {
10782 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10783 env
->elr_el
[2] = env
->regs
[15];
10785 /* CPSR.PAN is normally preserved preserved unless... */
10786 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10789 if (!arm_is_secure_below_el3(env
)) {
10790 /* ... the target is EL3, from non-secure state. */
10791 env
->uncached_cpsr
&= ~CPSR_PAN
;
10794 /* ... the target is EL3, from secure state ... */
10797 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10798 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10799 env
->uncached_cpsr
|= CPSR_PAN
;
10805 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10806 * and we should just guard the thumb mode on V4
10808 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10810 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10812 env
->regs
[14] = env
->regs
[15] + offset
;
10814 env
->regs
[15] = newpc
;
10816 if (tcg_enabled()) {
10817 arm_rebuild_hflags(env
);
10821 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10824 * Handle exception entry to Hyp mode; this is sufficiently
10825 * different to entry to other AArch32 modes that we handle it
10828 * The vector table entry used is always the 0x14 Hyp mode entry point,
10829 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10830 * The offset applied to the preferred return address is always zero
10831 * (see DDI0487C.a section G1.12.3).
10832 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10834 uint32_t addr
, mask
;
10835 ARMCPU
*cpu
= ARM_CPU(cs
);
10836 CPUARMState
*env
= &cpu
->env
;
10838 switch (cs
->exception_index
) {
10846 /* Fall through to prefetch abort. */
10847 case EXCP_PREFETCH_ABORT
:
10848 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10849 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10850 (uint32_t)env
->exception
.vaddress
);
10853 case EXCP_DATA_ABORT
:
10854 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10855 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10856 (uint32_t)env
->exception
.vaddress
);
10868 case EXCP_HYP_TRAP
:
10872 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10875 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10876 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10878 * QEMU syndrome values are v8-style. v7 has the IL bit
10879 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10880 * If this is a v7 CPU, squash the IL bit in those cases.
10882 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10883 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10884 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10885 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10886 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10889 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10892 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10897 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10900 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10903 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10907 addr
+= env
->cp15
.hvbar
;
10909 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10912 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10914 ARMCPU
*cpu
= ARM_CPU(cs
);
10915 CPUARMState
*env
= &cpu
->env
;
10922 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10923 switch (syn_get_ec(env
->exception
.syndrome
)) {
10924 case EC_BREAKPOINT
:
10925 case EC_BREAKPOINT_SAME_EL
:
10928 case EC_WATCHPOINT
:
10929 case EC_WATCHPOINT_SAME_EL
:
10935 case EC_VECTORCATCH
:
10944 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10947 if (env
->exception
.target_el
== 2) {
10948 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10952 switch (cs
->exception_index
) {
10954 new_mode
= ARM_CPU_MODE_UND
;
10964 new_mode
= ARM_CPU_MODE_SVC
;
10967 /* The PC already points to the next instruction. */
10971 /* Fall through to prefetch abort. */
10972 case EXCP_PREFETCH_ABORT
:
10973 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10974 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10975 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10976 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10977 new_mode
= ARM_CPU_MODE_ABT
;
10979 mask
= CPSR_A
| CPSR_I
;
10982 case EXCP_DATA_ABORT
:
10983 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10984 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10985 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10986 env
->exception
.fsr
,
10987 (uint32_t)env
->exception
.vaddress
);
10988 new_mode
= ARM_CPU_MODE_ABT
;
10990 mask
= CPSR_A
| CPSR_I
;
10994 new_mode
= ARM_CPU_MODE_IRQ
;
10996 /* Disable IRQ and imprecise data aborts. */
10997 mask
= CPSR_A
| CPSR_I
;
10999 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
11000 /* IRQ routed to monitor mode */
11001 new_mode
= ARM_CPU_MODE_MON
;
11006 new_mode
= ARM_CPU_MODE_FIQ
;
11008 /* Disable FIQ, IRQ and imprecise data aborts. */
11009 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11010 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
11011 /* FIQ routed to monitor mode */
11012 new_mode
= ARM_CPU_MODE_MON
;
11017 new_mode
= ARM_CPU_MODE_IRQ
;
11019 /* Disable IRQ and imprecise data aborts. */
11020 mask
= CPSR_A
| CPSR_I
;
11024 new_mode
= ARM_CPU_MODE_FIQ
;
11026 /* Disable FIQ, IRQ and imprecise data aborts. */
11027 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11033 * Note that this is reported as a data abort, but the DFAR
11034 * has an UNKNOWN value. Construct the SError syndrome from
11035 * AET and ExT fields.
11037 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
11039 if (extended_addresses_enabled(env
)) {
11040 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
11042 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
11044 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
11045 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11046 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
11047 env
->exception
.fsr
);
11049 new_mode
= ARM_CPU_MODE_ABT
;
11051 mask
= CPSR_A
| CPSR_I
;
11056 new_mode
= ARM_CPU_MODE_MON
;
11058 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11062 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11063 return; /* Never happens. Keep compiler happy. */
11066 if (new_mode
== ARM_CPU_MODE_MON
) {
11067 addr
+= env
->cp15
.mvbar
;
11068 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
11069 /* High vectors. When enabled, base address cannot be remapped. */
11070 addr
+= 0xffff0000;
11073 * ARM v7 architectures provide a vector base address register to remap
11074 * the interrupt vector table.
11075 * This register is only followed in non-monitor mode, and is banked.
11076 * Note: only bits 31:5 are valid.
11078 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
11081 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
11082 env
->cp15
.scr_el3
&= ~SCR_NS
;
11085 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
11088 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
11091 * Return the register number of the AArch64 view of the AArch32
11092 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
11093 * be that of the AArch32 mode the exception came from.
11095 int mode
= env
->uncached_cpsr
& CPSR_M
;
11097 switch (aarch32_reg
) {
11099 return aarch32_reg
;
11101 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
11104 case ARM_CPU_MODE_USR
:
11105 case ARM_CPU_MODE_SYS
:
11107 case ARM_CPU_MODE_HYP
:
11109 case ARM_CPU_MODE_IRQ
:
11111 case ARM_CPU_MODE_SVC
:
11113 case ARM_CPU_MODE_ABT
:
11115 case ARM_CPU_MODE_UND
:
11117 case ARM_CPU_MODE_FIQ
:
11120 g_assert_not_reached();
11124 case ARM_CPU_MODE_USR
:
11125 case ARM_CPU_MODE_SYS
:
11126 case ARM_CPU_MODE_HYP
:
11128 case ARM_CPU_MODE_IRQ
:
11130 case ARM_CPU_MODE_SVC
:
11132 case ARM_CPU_MODE_ABT
:
11134 case ARM_CPU_MODE_UND
:
11136 case ARM_CPU_MODE_FIQ
:
11139 g_assert_not_reached();
11144 g_assert_not_reached();
11148 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11150 uint32_t ret
= cpsr_read(env
);
11152 /* Move DIT to the correct location for SPSR_ELx */
11153 if (ret
& CPSR_DIT
) {
11157 /* Merge PSTATE.SS into SPSR_ELx */
11158 ret
|= env
->pstate
& PSTATE_SS
;
11163 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11165 /* Return true if this syndrome value is a synchronous external abort */
11166 switch (syn_get_ec(syndrome
)) {
11168 case EC_INSNABORT_SAME_EL
:
11170 case EC_DATAABORT_SAME_EL
:
11171 /* Look at fault status code for all the synchronous ext abort cases */
11172 switch (syndrome
& 0x3f) {
11188 /* Handle exception entry to a target EL which is using AArch64 */
11189 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11191 ARMCPU
*cpu
= ARM_CPU(cs
);
11192 CPUARMState
*env
= &cpu
->env
;
11193 unsigned int new_el
= env
->exception
.target_el
;
11194 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11195 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11196 unsigned int old_mode
;
11197 unsigned int cur_el
= arm_current_el(env
);
11200 if (tcg_enabled()) {
11202 * Note that new_el can never be 0. If cur_el is 0, then
11203 * el0_a64 is is_a64(), else el0_a64 is ignored.
11205 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11208 if (cur_el
< new_el
) {
11210 * Entry vector offset depends on whether the implemented EL
11211 * immediately lower than the target level is using AArch32 or AArch64
11218 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11221 hcr
= arm_hcr_el2_eff(env
);
11222 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11223 is_aa64
= (hcr
& HCR_RW
) != 0;
11228 is_aa64
= is_a64(env
);
11231 g_assert_not_reached();
11239 } else if (pstate_read(env
) & PSTATE_SP
) {
11243 switch (cs
->exception_index
) {
11245 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11246 env
->cp15
.mfar_el3
);
11248 case EXCP_PREFETCH_ABORT
:
11249 case EXCP_DATA_ABORT
:
11251 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11252 * to be taken to the SError vector entrypoint.
11254 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11255 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11258 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11259 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11260 env
->cp15
.far_el
[new_el
]);
11266 case EXCP_HYP_TRAP
:
11268 switch (syn_get_ec(env
->exception
.syndrome
)) {
11269 case EC_ADVSIMDFPACCESSTRAP
:
11271 * QEMU internal FP/SIMD syndromes from AArch32 include the
11272 * TA and coproc fields which are only exposed if the exception
11273 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11274 * AArch64 format syndrome.
11276 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11278 case EC_CP14RTTRAP
:
11279 case EC_CP15RTTRAP
:
11280 case EC_CP14DTTRAP
:
11282 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11283 * the raw register field from the insn; when taking this to
11284 * AArch64 we must convert it to the AArch64 view of the register
11285 * number. Notice that we read a 4-bit AArch32 register number and
11286 * write back a 5-bit AArch64 one.
11288 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11289 rt
= aarch64_regnum(env
, rt
);
11290 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11293 case EC_CP15RRTTRAP
:
11294 case EC_CP14RRTTRAP
:
11295 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11296 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11297 rt
= aarch64_regnum(env
, rt
);
11298 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11300 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11301 rt
= aarch64_regnum(env
, rt
);
11302 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11306 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11318 /* Construct the SError syndrome from IDS and ISS fields. */
11319 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11320 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11323 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11327 old_mode
= pstate_read(env
);
11328 aarch64_save_sp(env
, arm_current_el(env
));
11329 env
->elr_el
[new_el
] = env
->pc
;
11331 if (cur_el
== 1 && new_el
== 1) {
11332 uint64_t hcr
= arm_hcr_el2_eff(env
);
11333 if ((hcr
& (HCR_NV
| HCR_NV1
| HCR_NV2
)) == HCR_NV
||
11334 (hcr
& (HCR_NV
| HCR_NV2
)) == (HCR_NV
| HCR_NV2
)) {
11336 * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR
11337 * by setting M[3:2] to 0b10.
11338 * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN)
11339 * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM)
11341 old_mode
= deposit32(old_mode
, 2, 2, 2);
11345 old_mode
= cpsr_read_for_spsr_elx(env
);
11346 env
->elr_el
[new_el
] = env
->regs
[15];
11348 aarch64_sync_32_to_64(env
);
11350 env
->condexec_bits
= 0;
11352 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11354 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11355 env
->elr_el
[new_el
]);
11357 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11358 /* The value of PSTATE.PAN is normally preserved, except when ... */
11359 new_mode
|= old_mode
& PSTATE_PAN
;
11362 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11363 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11364 != (HCR_E2H
| HCR_TGE
)) {
11369 /* ... the target is EL1 ... */
11370 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11371 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11372 new_mode
|= PSTATE_PAN
;
11377 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11378 new_mode
|= PSTATE_TCO
;
11381 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11382 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11383 new_mode
|= PSTATE_SSBS
;
11385 new_mode
&= ~PSTATE_SSBS
;
11389 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11390 env
->aarch64
= true;
11391 aarch64_restore_sp(env
, new_el
);
11393 if (tcg_enabled()) {
11394 helper_rebuild_hflags_a64(env
, new_el
);
11399 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11400 new_el
, env
->pc
, pstate_read(env
));
11404 * Do semihosting call and set the appropriate return value. All the
11405 * permission and validity checks have been done at translate time.
11407 * We only see semihosting exceptions in TCG only as they are not
11408 * trapped to the hypervisor in KVM.
11411 static void tcg_handle_semihosting(CPUState
*cs
)
11413 ARMCPU
*cpu
= ARM_CPU(cs
);
11414 CPUARMState
*env
= &cpu
->env
;
11417 qemu_log_mask(CPU_LOG_INT
,
11418 "...handling as semihosting call 0x%" PRIx64
"\n",
11420 do_common_semihosting(cs
);
11423 qemu_log_mask(CPU_LOG_INT
,
11424 "...handling as semihosting call 0x%x\n",
11426 do_common_semihosting(cs
);
11427 env
->regs
[15] += env
->thumb
? 2 : 4;
11433 * Handle a CPU exception for A and R profile CPUs.
11434 * Do any appropriate logging, handle PSCI calls, and then hand off
11435 * to the AArch64-entry or AArch32-entry function depending on the
11436 * target exception level's register width.
11438 * Note: this is used for both TCG (as the do_interrupt tcg op),
11439 * and KVM to re-inject guest debug exceptions, and to
11440 * inject a Synchronous-External-Abort.
11442 void arm_cpu_do_interrupt(CPUState
*cs
)
11444 ARMCPU
*cpu
= ARM_CPU(cs
);
11445 CPUARMState
*env
= &cpu
->env
;
11446 unsigned int new_el
= env
->exception
.target_el
;
11448 assert(!arm_feature(env
, ARM_FEATURE_M
));
11450 arm_log_exception(cs
);
11451 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11453 if (qemu_loglevel_mask(CPU_LOG_INT
)
11454 && !excp_is_internal(cs
->exception_index
)) {
11455 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11456 syn_get_ec(env
->exception
.syndrome
),
11457 env
->exception
.syndrome
);
11460 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11461 arm_handle_psci_call(cpu
);
11462 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11467 * Semihosting semantics depend on the register width of the code
11468 * that caused the exception, not the target exception level, so
11469 * must be handled here.
11472 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11473 tcg_handle_semihosting(cs
);
11479 * Hooks may change global state so BQL should be held, also the
11480 * BQL needs to be held for any modification of
11481 * cs->interrupt_request.
11483 g_assert(bql_locked());
11485 arm_call_pre_el_change_hook(cpu
);
11487 assert(!excp_is_internal(cs
->exception_index
));
11488 if (arm_el_is_aa64(env
, new_el
)) {
11489 arm_cpu_do_interrupt_aarch64(cs
);
11491 arm_cpu_do_interrupt_aarch32(cs
);
11494 arm_call_el_change_hook(cpu
);
11496 if (!kvm_enabled()) {
11497 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11500 #endif /* !CONFIG_USER_ONLY */
11502 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11504 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11506 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11507 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11509 return env
->cp15
.sctlr_el
[el
];
11512 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11514 if (regime_has_2_ranges(mmu_idx
)) {
11515 return extract64(tcr
, 37, 2);
11516 } else if (regime_is_stage2(mmu_idx
)) {
11517 return 0; /* VTCR_EL2 */
11519 /* Replicate the single TBI bit so we always have 2 bits. */
11520 return extract32(tcr
, 20, 1) * 3;
11524 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11526 if (regime_has_2_ranges(mmu_idx
)) {
11527 return extract64(tcr
, 51, 2);
11528 } else if (regime_is_stage2(mmu_idx
)) {
11529 return 0; /* VTCR_EL2 */
11531 /* Replicate the single TBID bit so we always have 2 bits. */
11532 return extract32(tcr
, 29, 1) * 3;
11536 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11538 if (regime_has_2_ranges(mmu_idx
)) {
11539 return extract64(tcr
, 57, 2);
11541 /* Replicate the single TCMA bit so we always have 2 bits. */
11542 return extract32(tcr
, 30, 1) * 3;
11546 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11556 return GranInvalid
;
11560 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11570 return GranInvalid
;
11574 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11576 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11577 : cpu_isar_feature(aa64_tgran4
, cpu
);
11580 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11582 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11583 : cpu_isar_feature(aa64_tgran16
, cpu
);
11586 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11588 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11589 : cpu_isar_feature(aa64_tgran64
, cpu
);
11592 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11597 if (have4k(cpu
, stage2
)) {
11602 if (have16k(cpu
, stage2
)) {
11607 if (have64k(cpu
, stage2
)) {
11615 * If the guest selects a granule size that isn't implemented,
11616 * the architecture requires that we behave as if it selected one
11617 * that is (with an IMPDEF choice of which one to pick). We choose
11618 * to implement the smallest supported granule size.
11620 if (have4k(cpu
, stage2
)) {
11623 if (have16k(cpu
, stage2
)) {
11626 assert(have64k(cpu
, stage2
));
11630 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11631 ARMMMUIdx mmu_idx
, bool data
,
11634 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11635 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11636 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11637 ARMGranuleSize gran
;
11638 ARMCPU
*cpu
= env_archcpu(env
);
11639 bool stage2
= regime_is_stage2(mmu_idx
);
11641 if (!regime_has_2_ranges(mmu_idx
)) {
11643 tsz
= extract32(tcr
, 0, 6);
11644 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11649 hpd
= extract32(tcr
, 24, 1);
11652 sh
= extract32(tcr
, 12, 2);
11653 ps
= extract32(tcr
, 16, 3);
11654 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11655 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11656 ds
= extract64(tcr
, 32, 1);
11661 * Bit 55 is always between the two regions, and is canonical for
11662 * determining if address tagging is enabled.
11664 select
= extract64(va
, 55, 1);
11666 tsz
= extract32(tcr
, 0, 6);
11667 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11668 epd
= extract32(tcr
, 7, 1);
11669 sh
= extract32(tcr
, 12, 2);
11670 hpd
= extract64(tcr
, 41, 1);
11671 e0pd
= extract64(tcr
, 55, 1);
11673 tsz
= extract32(tcr
, 16, 6);
11674 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11675 epd
= extract32(tcr
, 23, 1);
11676 sh
= extract32(tcr
, 28, 2);
11677 hpd
= extract64(tcr
, 42, 1);
11678 e0pd
= extract64(tcr
, 56, 1);
11680 ps
= extract64(tcr
, 32, 3);
11681 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11682 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11683 ds
= extract64(tcr
, 59, 1);
11685 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11686 regime_is_user(env
, mmu_idx
)) {
11691 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11693 if (cpu_isar_feature(aa64_st
, cpu
)) {
11694 max_tsz
= 48 - (gran
== Gran64K
);
11700 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11701 * adjust the effective value of DS, as documented.
11704 if (gran
== Gran64K
) {
11705 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11710 if (regime_is_stage2(mmu_idx
)) {
11711 if (gran
== Gran16K
) {
11712 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11714 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11717 if (gran
== Gran16K
) {
11718 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11720 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11728 if (stage2
&& el1_is_aa32
) {
11730 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11731 * are loosened: a configured IPA of 40 bits is permitted even if
11732 * the implemented PA is less than that (and so a 40 bit IPA would
11733 * fault for an AArch64 EL1). See R_DTLMN.
11735 min_tsz
= MIN(min_tsz
, 24);
11738 if (tsz
> max_tsz
) {
11741 } else if (tsz
< min_tsz
) {
11748 /* Present TBI as a composite with TBID. */
11749 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11751 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11753 tbi
= (tbi
>> select
) & 1;
11755 return (ARMVAParameters
) {
11763 .tsz_oob
= tsz_oob
,
11772 * Note that signed overflow is undefined in C. The following routines are
11773 * careful to use unsigned types where modulo arithmetic is required.
11774 * Failure to do so _will_ break on newer gcc.
11777 /* Signed saturating arithmetic. */
11779 /* Perform 16-bit signed saturating addition. */
11780 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11785 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11795 /* Perform 8-bit signed saturating addition. */
11796 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11801 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11811 /* Perform 16-bit signed saturating subtraction. */
11812 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11817 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11827 /* Perform 8-bit signed saturating subtraction. */
11828 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11833 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11843 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11844 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11845 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11846 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11849 #include "op_addsub.h"
11851 /* Unsigned saturating arithmetic. */
11852 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11862 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11871 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11881 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11890 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11891 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11892 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11893 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11896 #include "op_addsub.h"
11898 /* Signed modulo arithmetic. */
11899 #define SARITH16(a, b, n, op) do { \
11901 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11902 RESULT(sum, n, 16); \
11904 ge |= 3 << (n * 2); \
11907 #define SARITH8(a, b, n, op) do { \
11909 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11910 RESULT(sum, n, 8); \
11916 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11917 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11918 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11919 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11923 #include "op_addsub.h"
11925 /* Unsigned modulo arithmetic. */
11926 #define ADD16(a, b, n) do { \
11928 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11929 RESULT(sum, n, 16); \
11930 if ((sum >> 16) == 1) \
11931 ge |= 3 << (n * 2); \
11934 #define ADD8(a, b, n) do { \
11936 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11937 RESULT(sum, n, 8); \
11938 if ((sum >> 8) == 1) \
11942 #define SUB16(a, b, n) do { \
11944 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11945 RESULT(sum, n, 16); \
11946 if ((sum >> 16) == 0) \
11947 ge |= 3 << (n * 2); \
11950 #define SUB8(a, b, n) do { \
11952 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11953 RESULT(sum, n, 8); \
11954 if ((sum >> 8) == 0) \
11961 #include "op_addsub.h"
11963 /* Halved signed arithmetic. */
11964 #define ADD16(a, b, n) \
11965 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11966 #define SUB16(a, b, n) \
11967 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11968 #define ADD8(a, b, n) \
11969 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11970 #define SUB8(a, b, n) \
11971 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11974 #include "op_addsub.h"
11976 /* Halved unsigned arithmetic. */
11977 #define ADD16(a, b, n) \
11978 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11979 #define SUB16(a, b, n) \
11980 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11981 #define ADD8(a, b, n) \
11982 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11983 #define SUB8(a, b, n) \
11984 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11987 #include "op_addsub.h"
11989 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11998 /* Unsigned sum of absolute byte differences. */
11999 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12002 sum
= do_usad(a
, b
);
12003 sum
+= do_usad(a
>> 8, b
>> 8);
12004 sum
+= do_usad(a
>> 16, b
>> 16);
12005 sum
+= do_usad(a
>> 24, b
>> 24);
12009 /* For ARMv6 SEL instruction. */
12010 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12025 mask
|= 0xff000000;
12027 return (a
& mask
) | (b
& ~mask
);
12032 * The upper bytes of val (above the number specified by 'bytes') must have
12033 * been zeroed out by the caller.
12035 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12039 stl_le_p(buf
, val
);
12041 /* zlib crc32 converts the accumulator and output to one's complement. */
12042 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12045 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12049 stl_le_p(buf
, val
);
12051 /* Linux crc32c converts the output to one's complement. */
12052 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12056 * Return the exception level to which FP-disabled exceptions should
12057 * be taken, or 0 if FP is enabled.
12059 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12061 #ifndef CONFIG_USER_ONLY
12065 * CPACR and the CPTR registers don't exist before v6, so FP is
12066 * always accessible
12068 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12072 if (arm_feature(env
, ARM_FEATURE_M
)) {
12073 /* CPACR can cause a NOCP UsageFault taken to current security state */
12074 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12078 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12079 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12080 /* FP insns cause a NOCP UsageFault taken to Secure */
12088 hcr_el2
= arm_hcr_el2_eff(env
);
12091 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12092 * 0, 2 : trap EL0 and EL1/PL1 accesses
12093 * 1 : trap only EL0 accesses
12094 * 3 : trap no accesses
12095 * This register is ignored if E2H+TGE are both set.
12097 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12098 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
12108 /* Trap from Secure PL0 or PL1 to Secure PL1. */
12109 if (!arm_el_is_aa64(env
, 3)
12110 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
12121 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12122 * to control non-secure access to the FPU. It doesn't have any
12123 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12125 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12126 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12127 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12128 /* FP insns act as UNDEF */
12129 return cur_el
== 2 ? 2 : 1;
12134 * CPTR_EL2 is present in v7VE or v8, and changes format
12135 * with HCR_EL2.E2H (regardless of TGE).
12138 if (hcr_el2
& HCR_E2H
) {
12139 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
12141 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
12149 } else if (arm_is_el2_enabled(env
)) {
12150 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
12156 /* CPTR_EL3 : present in v8 */
12157 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
12158 /* Trap all FP ops to EL3 */
12165 /* Return the exception level we're running at if this is our mmu_idx */
12166 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12168 if (mmu_idx
& ARM_MMU_IDX_M
) {
12169 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12173 case ARMMMUIdx_E10_0
:
12174 case ARMMMUIdx_E20_0
:
12176 case ARMMMUIdx_E10_1
:
12177 case ARMMMUIdx_E10_1_PAN
:
12180 case ARMMMUIdx_E20_2
:
12181 case ARMMMUIdx_E20_2_PAN
:
12186 g_assert_not_reached();
12191 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12193 g_assert_not_reached();
12197 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12202 if (arm_feature(env
, ARM_FEATURE_M
)) {
12203 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12206 /* See ARM pseudo-function ELIsInHost. */
12209 hcr
= arm_hcr_el2_eff(env
);
12210 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12211 idx
= ARMMMUIdx_E20_0
;
12213 idx
= ARMMMUIdx_E10_0
;
12217 if (arm_pan_enabled(env
)) {
12218 idx
= ARMMMUIdx_E10_1_PAN
;
12220 idx
= ARMMMUIdx_E10_1
;
12224 /* Note that TGE does not apply at EL2. */
12225 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12226 if (arm_pan_enabled(env
)) {
12227 idx
= ARMMMUIdx_E20_2_PAN
;
12229 idx
= ARMMMUIdx_E20_2
;
12232 idx
= ARMMMUIdx_E2
;
12236 return ARMMMUIdx_E3
;
12238 g_assert_not_reached();
12244 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12246 return arm_mmu_idx_el(env
, arm_current_el(env
));
12249 static bool mve_no_pred(CPUARMState
*env
)
12252 * Return true if there is definitely no predication of MVE
12253 * instructions by VPR or LTPSIZE. (Returning false even if there
12254 * isn't any predication is OK; generated code will just be
12256 * If the CPU does not implement MVE then this TB flag is always 0.
12258 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12259 * logic in gen_update_fp_context() needs to be updated to match.
12261 * We do not include the effect of the ECI bits here -- they are
12262 * tracked in other TB flags. This simplifies the logic for
12263 * "when did we emit code that changes the MVE_NO_PRED TB flag
12264 * and thus need to end the TB?".
12266 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12269 if (env
->v7m
.vpr
) {
12272 if (env
->v7m
.ltpsize
< 4) {
12278 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12279 uint64_t *cs_base
, uint32_t *pflags
)
12281 CPUARMTBFlags flags
;
12283 assert_hflags_rebuild_correctly(env
);
12284 flags
= env
->hflags
;
12286 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12288 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12289 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12292 *pc
= env
->regs
[15];
12294 if (arm_feature(env
, ARM_FEATURE_M
)) {
12295 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12296 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12297 != env
->v7m
.secure
) {
12298 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12301 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12302 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12303 (env
->v7m
.secure
&&
12304 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12306 * ASPEN is set, but FPCA/SFPA indicate that there is no
12307 * active FP context; we must create a new FP context before
12308 * executing any FP insn.
12310 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12313 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12314 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12315 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12318 if (mve_no_pred(env
)) {
12319 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12323 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12324 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12326 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12327 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12329 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12330 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12332 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12333 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12337 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12338 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12342 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12343 * states defined in the ARM ARM for software singlestep:
12344 * SS_ACTIVE PSTATE.SS State
12345 * 0 x Inactive (the TB flag for SS is always 0)
12346 * 1 0 Active-pending
12347 * 1 1 Active-not-pending
12348 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12350 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12351 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12354 *pflags
= flags
.flags
;
12355 *cs_base
= flags
.flags2
;
12358 #ifdef TARGET_AARCH64
12360 * The manual says that when SVE is enabled and VQ is widened the
12361 * implementation is allowed to zero the previously inaccessible
12362 * portion of the registers. The corollary to that is that when
12363 * SVE is enabled and VQ is narrowed we are also allowed to zero
12364 * the now inaccessible portion of the registers.
12366 * The intent of this is that no predicate bit beyond VQ is ever set.
12367 * Which means that some operations on predicate registers themselves
12368 * may operate on full uint64_t or even unrolled across the maximum
12369 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12370 * may well be cheaper than conditionals to restrict the operation
12371 * to the relevant portion of a uint16_t[16].
12373 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12378 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12379 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12381 /* Zap the high bits of the zregs. */
12382 for (i
= 0; i
< 32; i
++) {
12383 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12386 /* Zap the high bits of the pregs and ffr. */
12389 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12391 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12392 for (i
= 0; i
< 17; ++i
) {
12393 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12399 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12404 exc_el
= sme_exception_el(env
, el
);
12406 exc_el
= sve_exception_el(env
, el
);
12409 return 0; /* disabled */
12411 return sve_vqm1_for_el_sm(env
, el
, sm
);
12415 * Notice a change in SVE vector size when changing EL.
12417 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12418 int new_el
, bool el0_a64
)
12420 ARMCPU
*cpu
= env_archcpu(env
);
12421 int old_len
, new_len
;
12422 bool old_a64
, new_a64
, sm
;
12424 /* Nothing to do if no SVE. */
12425 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12429 /* Nothing to do if FP is disabled in either EL. */
12430 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12434 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12435 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12438 * Both AArch64.TakeException and AArch64.ExceptionReturn
12439 * invoke ResetSVEState when taking an exception from, or
12440 * returning to, AArch32 state when PSTATE.SM is enabled.
12442 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12443 if (old_a64
!= new_a64
&& sm
) {
12444 arm_reset_sve_state(env
);
12449 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12450 * at ELx, or not available because the EL is in AArch32 state, then
12451 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12452 * has an effective value of 0".
12454 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12455 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12456 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12457 * we already have the correct register contents when encountering the
12458 * vq0->vq0 transition between EL0->EL1.
12460 old_len
= new_len
= 0;
12462 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12465 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12468 /* When changing vector length, clear inaccessible state. */
12469 if (new_len
< old_len
) {
12470 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12475 #ifndef CONFIG_USER_ONLY
12476 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12478 if (arm_feature(env
, ARM_FEATURE_M
)) {
12479 return arm_secure_to_space(env
->v7m
.secure
);
12483 * If EL3 is not supported then the secure state is implementation
12484 * defined, in which case QEMU defaults to non-secure.
12486 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12487 return ARMSS_NonSecure
;
12490 /* Check for AArch64 EL3 or AArch32 Mon. */
12492 if (extract32(env
->pstate
, 2, 2) == 3) {
12493 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12496 return ARMSS_Secure
;
12500 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12501 return ARMSS_Secure
;
12505 return arm_security_space_below_el3(env
);
12508 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12510 assert(!arm_feature(env
, ARM_FEATURE_M
));
12513 * If EL3 is not supported then the secure state is implementation
12514 * defined, in which case QEMU defaults to non-secure.
12516 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12517 return ARMSS_NonSecure
;
12521 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12522 * Ignoring NSE when !NS retains consistency without having to
12523 * modify other predicates.
12525 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12526 return ARMSS_Secure
;
12527 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12528 return ARMSS_Realm
;
12530 return ARMSS_NonSecure
;
12533 #endif /* !CONFIG_USER_ONLY */