4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
267 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
269 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
270 const ARMCPRegInfo
*ri
,
273 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
274 arm_is_secure_below_el3(env
)) {
275 return CP_ACCESS_TRAP_UNCATEGORIZED
;
281 * Some secure-only AArch32 registers trap to EL3 if used from
282 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
283 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
284 * We assume that the .access field is set to PL1_RW.
286 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
287 const ARMCPRegInfo
*ri
,
290 if (arm_current_el(env
) == 3) {
293 if (arm_is_secure_below_el3(env
)) {
294 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
295 return CP_ACCESS_TRAP_EL2
;
297 return CP_ACCESS_TRAP_EL3
;
299 /* This will be EL1 NS and EL2 NS, which just UNDEF */
300 return CP_ACCESS_TRAP_UNCATEGORIZED
;
304 * Check for traps to performance monitor registers, which are controlled
305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
307 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
310 int el
= arm_current_el(env
);
311 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
313 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
314 return CP_ACCESS_TRAP_EL2
;
316 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
317 return CP_ACCESS_TRAP_EL3
;
322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
323 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
326 if (arm_current_el(env
) == 1) {
327 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
328 if (arm_hcr_el2_eff(env
) & trap
) {
329 return CP_ACCESS_TRAP_EL2
;
335 /* Check for traps from EL1 due to HCR_EL2.TSW. */
336 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
340 return CP_ACCESS_TRAP_EL2
;
345 /* Check for traps from EL1 due to HCR_EL2.TACR. */
346 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
349 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
350 return CP_ACCESS_TRAP_EL2
;
355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
356 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
359 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
360 return CP_ACCESS_TRAP_EL2
;
365 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
366 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
369 if (arm_current_el(env
) == 1 &&
370 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
371 return CP_ACCESS_TRAP_EL2
;
376 #ifdef TARGET_AARCH64
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
378 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
383 return CP_ACCESS_TRAP_EL2
;
389 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
391 ARMCPU
*cpu
= env_archcpu(env
);
393 raw_write(env
, ri
, value
);
394 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
397 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
399 ARMCPU
*cpu
= env_archcpu(env
);
401 if (raw_read(env
, ri
) != value
) {
403 * Unlike real hardware the qemu TLB uses virtual addresses,
404 * not modified virtual addresses, so this causes a TLB flush.
407 raw_write(env
, ri
, value
);
411 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 ARMCPU
*cpu
= env_archcpu(env
);
416 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
417 && !extended_addresses_enabled(env
)) {
419 * For VMSA (when not using the LPAE long descriptor page table
420 * format) this register includes the ASID, so do a TLB flush.
421 * For PMSA it is purely a process ID and no action is needed.
425 raw_write(env
, ri
, value
);
428 static int alle1_tlbmask(CPUARMState
*env
)
431 * Note that the 'ALL' scope must invalidate both stage 1 and
432 * stage 2 translations, whereas most other scopes only invalidate
433 * stage 1 translations.
435 return (ARMMMUIdxBit_E10_1
|
436 ARMMMUIdxBit_E10_1_PAN
|
438 ARMMMUIdxBit_Stage2
|
439 ARMMMUIdxBit_Stage2_S
);
443 /* IS variants of TLB operations must affect all cores */
444 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
447 CPUState
*cs
= env_cpu(env
);
449 tlb_flush_all_cpus_synced(cs
);
452 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 CPUState
*cs
= env_cpu(env
);
457 tlb_flush_all_cpus_synced(cs
);
460 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
463 CPUState
*cs
= env_cpu(env
);
465 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
468 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
471 CPUState
*cs
= env_cpu(env
);
473 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
477 * Non-IS variants of TLB operations are upgraded to
478 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
479 * force broadcast of these operations.
481 static bool tlb_force_broadcast(CPUARMState
*env
)
483 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
486 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
489 /* Invalidate all (TLBIALL) */
490 CPUState
*cs
= env_cpu(env
);
492 if (tlb_force_broadcast(env
)) {
493 tlb_flush_all_cpus_synced(cs
);
499 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
503 CPUState
*cs
= env_cpu(env
);
505 value
&= TARGET_PAGE_MASK
;
506 if (tlb_force_broadcast(env
)) {
507 tlb_flush_page_all_cpus_synced(cs
, value
);
509 tlb_flush_page(cs
, value
);
513 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
516 /* Invalidate by ASID (TLBIASID) */
517 CPUState
*cs
= env_cpu(env
);
519 if (tlb_force_broadcast(env
)) {
520 tlb_flush_all_cpus_synced(cs
);
526 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530 CPUState
*cs
= env_cpu(env
);
532 value
&= TARGET_PAGE_MASK
;
533 if (tlb_force_broadcast(env
)) {
534 tlb_flush_page_all_cpus_synced(cs
, value
);
536 tlb_flush_page(cs
, value
);
540 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
543 CPUState
*cs
= env_cpu(env
);
545 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
548 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
551 CPUState
*cs
= env_cpu(env
);
553 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
557 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
560 CPUState
*cs
= env_cpu(env
);
562 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
565 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= env_cpu(env
);
570 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
573 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 CPUState
*cs
= env_cpu(env
);
577 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
579 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
582 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
585 CPUState
*cs
= env_cpu(env
);
586 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
588 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
592 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
595 CPUState
*cs
= env_cpu(env
);
596 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
598 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
601 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
604 CPUState
*cs
= env_cpu(env
);
605 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
607 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
610 static const ARMCPRegInfo cp_reginfo
[] = {
612 * Define the secure and non-secure FCSE identifier CP registers
613 * separately because there is no secure bank in V8 (no _EL3). This allows
614 * the secure register to be properly reset and migrated. There is also no
615 * v8 EL1 version of the register so the non-secure instance stands alone.
618 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
619 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
620 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
621 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
622 { .name
= "FCSEIDR_S",
623 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
624 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
625 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
626 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
628 * Define the secure and non-secure context identifier CP registers
629 * separately because there is no secure bank in V8 (no _EL3). This allows
630 * the secure register to be properly reset and migrated. In the
631 * non-secure case, the 32-bit register will have reset and migration
632 * disabled during registration as it is handled by the 64-bit instance.
634 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
635 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
636 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
637 .fgt
= FGT_CONTEXTIDR_EL1
,
638 .secure
= ARM_CP_SECSTATE_NS
,
639 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
640 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
641 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
642 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
643 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
644 .secure
= ARM_CP_SECSTATE_S
,
645 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
646 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
649 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
651 * NB: Some of these registers exist in v8 but with more precise
652 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
654 /* MMU Domain access control / MPU write buffer control */
656 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
657 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
658 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
659 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
660 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
662 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
663 * For v6 and v5, these mappings are overly broad.
665 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
666 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
667 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
668 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
669 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
670 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
671 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
672 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
673 /* Cache maintenance ops; some of this space may be overridden later. */
674 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
675 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
676 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
679 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
681 * Not all pre-v6 cores implemented this WFI, so this is slightly
684 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
685 .access
= PL1_W
, .type
= ARM_CP_WFI
},
688 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
690 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
691 * is UNPREDICTABLE; we choose to NOP as most implementations do).
693 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
694 .access
= PL1_W
, .type
= ARM_CP_WFI
},
696 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
697 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
698 * OMAPCP will override this space.
700 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
701 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
703 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
704 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
706 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
707 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
708 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
711 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
712 * implementing it as RAZ means the "debug architecture version" bits
713 * will read as a reserved value, which should cause Linux to not try
714 * to use the debug hardware.
716 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
717 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
719 * MMU TLB control. Note that the wildcarding means we cover not just
720 * the unified TLB ops but also the dside/iside/inner-shareable variants.
722 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
723 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
724 .type
= ARM_CP_NO_RAW
},
725 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
726 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
727 .type
= ARM_CP_NO_RAW
},
728 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
729 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
730 .type
= ARM_CP_NO_RAW
},
731 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
732 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
733 .type
= ARM_CP_NO_RAW
},
734 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
735 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
736 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
737 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
740 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
745 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
746 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
748 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
749 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
750 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
752 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
753 /* VFP coprocessor: cp10 & cp11 [23:20] */
754 mask
|= R_CPACR_ASEDIS_MASK
|
755 R_CPACR_D32DIS_MASK
|
759 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
760 /* ASEDIS [31] bit is RAO/WI */
761 value
|= R_CPACR_ASEDIS_MASK
;
765 * VFPv3 and upwards with NEON implement 32 double precision
766 * registers (D0-D31).
768 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
769 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
770 value
|= R_CPACR_D32DIS_MASK
;
777 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
778 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
780 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
781 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
782 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
783 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
786 env
->cp15
.cpacr_el1
= value
;
789 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
792 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
793 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
795 uint64_t value
= env
->cp15
.cpacr_el1
;
797 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
798 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
799 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
805 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
808 * Call cpacr_write() so that we reset with the correct RAO bits set
809 * for our CPU features.
811 cpacr_write(env
, ri
, 0);
814 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 if (arm_feature(env
, ARM_FEATURE_V8
)) {
818 /* Check if CPACR accesses are to be trapped to EL2 */
819 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
820 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
821 return CP_ACCESS_TRAP_EL2
;
822 /* Check if CPACR accesses are to be trapped to EL3 */
823 } else if (arm_current_el(env
) < 3 &&
824 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
825 return CP_ACCESS_TRAP_EL3
;
832 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 /* Check if CPTR accesses are set to trap to EL3 */
836 if (arm_current_el(env
) == 2 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
844 static const ARMCPRegInfo v6_cp_reginfo
[] = {
845 /* prefetch by MVA in v6, NOP in v7 */
846 { .name
= "MVA_prefetch",
847 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
850 * We need to break the TB after ISB to execute self-modifying code
851 * correctly and also to take any pending interrupts immediately.
852 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
854 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
855 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
856 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
857 .access
= PL0_W
, .type
= ARM_CP_NOP
},
858 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
859 .access
= PL0_W
, .type
= ARM_CP_NOP
},
860 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
861 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
862 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
863 offsetof(CPUARMState
, cp15
.ifar_ns
) },
866 * Watchpoint Fault Address Register : should actually only be present
867 * for 1136, 1176, 11MPCore.
869 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
870 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
871 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
872 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
873 .fgt
= FGT_CPACR_EL1
,
874 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
875 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
878 typedef struct pm_event
{
879 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
880 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
881 bool (*supported
)(CPUARMState
*);
883 * Retrieve the current count of the underlying event. The programmed
884 * counters hold a difference from the return value from this function
886 uint64_t (*get_count
)(CPUARMState
*);
888 * Return how many nanoseconds it will take (at a minimum) for count events
889 * to occur. A negative value indicates the counter will never overflow, or
890 * that the counter has otherwise arranged for the overflow bit to be set
891 * and the PMU interrupt to be raised on overflow.
893 int64_t (*ns_per_count
)(uint64_t);
896 static bool event_always_supported(CPUARMState
*env
)
901 static uint64_t swinc_get_count(CPUARMState
*env
)
904 * SW_INCR events are written directly to the pmevcntr's by writes to
905 * PMSWINC, so there is no underlying count maintained by the PMU itself
910 static int64_t swinc_ns_per(uint64_t ignored
)
916 * Return the underlying cycle count for the PMU cycle counters. If we're in
917 * usermode, simply return 0.
919 static uint64_t cycles_get_count(CPUARMState
*env
)
921 #ifndef CONFIG_USER_ONLY
922 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
923 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
925 return cpu_get_host_ticks();
929 #ifndef CONFIG_USER_ONLY
930 static int64_t cycles_ns_per(uint64_t cycles
)
932 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
935 static bool instructions_supported(CPUARMState
*env
)
937 return icount_enabled() == 1; /* Precise instruction counting */
940 static uint64_t instructions_get_count(CPUARMState
*env
)
942 return (uint64_t)icount_get_raw();
945 static int64_t instructions_ns_per(uint64_t icount
)
947 return icount_to_ns((int64_t)icount
);
951 static bool pmuv3p1_events_supported(CPUARMState
*env
)
953 /* For events which are supported in any v8.1 PMU */
954 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
957 static bool pmuv3p4_events_supported(CPUARMState
*env
)
959 /* For events which are supported in any v8.1 PMU */
960 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
963 static uint64_t zero_event_get_count(CPUARMState
*env
)
965 /* For events which on QEMU never fire, so their count is always zero */
969 static int64_t zero_event_ns_per(uint64_t cycles
)
971 /* An event which never fires can never overflow */
975 static const pm_event pm_events
[] = {
976 { .number
= 0x000, /* SW_INCR */
977 .supported
= event_always_supported
,
978 .get_count
= swinc_get_count
,
979 .ns_per_count
= swinc_ns_per
,
981 #ifndef CONFIG_USER_ONLY
982 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
983 .supported
= instructions_supported
,
984 .get_count
= instructions_get_count
,
985 .ns_per_count
= instructions_ns_per
,
987 { .number
= 0x011, /* CPU_CYCLES, Cycle */
988 .supported
= event_always_supported
,
989 .get_count
= cycles_get_count
,
990 .ns_per_count
= cycles_ns_per
,
993 { .number
= 0x023, /* STALL_FRONTEND */
994 .supported
= pmuv3p1_events_supported
,
995 .get_count
= zero_event_get_count
,
996 .ns_per_count
= zero_event_ns_per
,
998 { .number
= 0x024, /* STALL_BACKEND */
999 .supported
= pmuv3p1_events_supported
,
1000 .get_count
= zero_event_get_count
,
1001 .ns_per_count
= zero_event_ns_per
,
1003 { .number
= 0x03c, /* STALL */
1004 .supported
= pmuv3p4_events_supported
,
1005 .get_count
= zero_event_get_count
,
1006 .ns_per_count
= zero_event_ns_per
,
1011 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1012 * events (i.e. the statistical profiling extension), this implementation
1013 * should first be updated to something sparse instead of the current
1014 * supported_event_map[] array.
1016 #define MAX_EVENT_ID 0x3c
1017 #define UNSUPPORTED_EVENT UINT16_MAX
1018 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1021 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1022 * of ARM event numbers to indices in our pm_events array.
1024 * Note: Events in the 0x40XX range are not currently supported.
1026 void pmu_init(ARMCPU
*cpu
)
1031 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1034 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1035 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1040 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1041 const pm_event
*cnt
= &pm_events
[i
];
1042 assert(cnt
->number
<= MAX_EVENT_ID
);
1043 /* We do not currently support events in the 0x40xx range */
1044 assert(cnt
->number
<= 0x3f);
1046 if (cnt
->supported(&cpu
->env
)) {
1047 supported_event_map
[cnt
->number
] = i
;
1048 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1049 if (cnt
->number
& 0x20) {
1050 cpu
->pmceid1
|= event_mask
;
1052 cpu
->pmceid0
|= event_mask
;
1059 * Check at runtime whether a PMU event is supported for the current machine
1061 static bool event_supported(uint16_t number
)
1063 if (number
> MAX_EVENT_ID
) {
1066 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1069 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1073 * Performance monitor registers user accessibility is controlled
1074 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1075 * trapping to EL2 or EL3 for other accesses.
1077 int el
= arm_current_el(env
);
1078 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1080 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1081 return CP_ACCESS_TRAP
;
1083 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1084 return CP_ACCESS_TRAP_EL2
;
1086 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1087 return CP_ACCESS_TRAP_EL3
;
1090 return CP_ACCESS_OK
;
1093 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1094 const ARMCPRegInfo
*ri
,
1097 /* ER: event counter read trap control */
1098 if (arm_feature(env
, ARM_FEATURE_V8
)
1099 && arm_current_el(env
) == 0
1100 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1102 return CP_ACCESS_OK
;
1105 return pmreg_access(env
, ri
, isread
);
1108 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1109 const ARMCPRegInfo
*ri
,
1112 /* SW: software increment write trap control */
1113 if (arm_feature(env
, ARM_FEATURE_V8
)
1114 && arm_current_el(env
) == 0
1115 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1117 return CP_ACCESS_OK
;
1120 return pmreg_access(env
, ri
, isread
);
1123 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1124 const ARMCPRegInfo
*ri
,
1127 /* ER: event counter read trap control */
1128 if (arm_feature(env
, ARM_FEATURE_V8
)
1129 && arm_current_el(env
) == 0
1130 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1131 return CP_ACCESS_OK
;
1134 return pmreg_access(env
, ri
, isread
);
1137 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1138 const ARMCPRegInfo
*ri
,
1141 /* CR: cycle counter read trap control */
1142 if (arm_feature(env
, ARM_FEATURE_V8
)
1143 && arm_current_el(env
) == 0
1144 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1146 return CP_ACCESS_OK
;
1149 return pmreg_access(env
, ri
, isread
);
1153 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1154 * We use these to decide whether we need to wrap a write to MDCR_EL2
1155 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1157 #define MDCR_EL2_PMU_ENABLE_BITS \
1158 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1159 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1162 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1163 * the current EL, security state, and register configuration.
1165 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1168 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1169 bool enabled
, prohibited
= false, filtered
;
1170 bool secure
= arm_is_secure(env
);
1171 int el
= arm_current_el(env
);
1172 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1173 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1175 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1179 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1180 (counter
< hpmn
|| counter
== 31)) {
1181 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1183 e
= mdcr_el2
& MDCR_HPME
;
1185 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1187 /* Is event counting prohibited? */
1188 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1189 prohibited
= mdcr_el2
& MDCR_HPMD
;
1192 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1195 if (counter
== 31) {
1197 * The cycle counter defaults to running. PMCR.DP says "disable
1198 * the cycle counter when event counting is prohibited".
1199 * Some MDCR bits disable the cycle counter specifically.
1201 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1202 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1204 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1207 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1212 if (counter
== 31) {
1213 filter
= env
->cp15
.pmccfiltr_el0
;
1215 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1218 p
= filter
& PMXEVTYPER_P
;
1219 u
= filter
& PMXEVTYPER_U
;
1220 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1221 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1222 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1223 m
= arm_el_is_aa64(env
, 1) &&
1224 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1227 filtered
= secure
? u
: u
!= nsu
;
1228 } else if (el
== 1) {
1229 filtered
= secure
? p
: p
!= nsk
;
1230 } else if (el
== 2) {
1236 if (counter
!= 31) {
1238 * If not checking PMCCNTR, ensure the counter is setup to an event we
1241 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1242 if (!event_supported(event
)) {
1247 return enabled
&& !prohibited
&& !filtered
;
1250 static void pmu_update_irq(CPUARMState
*env
)
1252 ARMCPU
*cpu
= env_archcpu(env
);
1253 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1254 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1257 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1260 * Return true if the clock divider is enabled and the cycle counter
1261 * is supposed to tick only once every 64 clock cycles. This is
1262 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1263 * (64-bit) cycle counter PMCR.D has no effect.
1265 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1268 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1270 /* Return true if the specified event counter is configured to be 64 bit */
1272 /* This isn't intended to be used with the cycle counter */
1273 assert(counter
< 31);
1275 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1279 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1281 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1282 * current security state, so we don't use arm_mdcr_el2_eff() here.
1284 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1285 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1287 if (counter
>= hpmn
) {
1291 return env
->cp15
.c9_pmcr
& PMCRLP
;
1295 * Ensure c15_ccnt is the guest-visible count so that operations such as
1296 * enabling/disabling the counter or filtering, modifying the count itself,
1297 * etc. can be done logically. This is essentially a no-op if the counter is
1298 * not enabled at the time of the call.
1300 static void pmccntr_op_start(CPUARMState
*env
)
1302 uint64_t cycles
= cycles_get_count(env
);
1304 if (pmu_counter_enabled(env
, 31)) {
1305 uint64_t eff_cycles
= cycles
;
1306 if (pmccntr_clockdiv_enabled(env
)) {
1310 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1312 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1313 1ull << 63 : 1ull << 31;
1314 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1315 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1316 pmu_update_irq(env
);
1319 env
->cp15
.c15_ccnt
= new_pmccntr
;
1321 env
->cp15
.c15_ccnt_delta
= cycles
;
1325 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1326 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1329 static void pmccntr_op_finish(CPUARMState
*env
)
1331 if (pmu_counter_enabled(env
, 31)) {
1332 #ifndef CONFIG_USER_ONLY
1333 /* Calculate when the counter will next overflow */
1334 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1335 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1336 remaining_cycles
= (uint32_t)remaining_cycles
;
1338 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1340 if (overflow_in
> 0) {
1341 int64_t overflow_at
;
1343 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1344 overflow_in
, &overflow_at
)) {
1345 ARMCPU
*cpu
= env_archcpu(env
);
1346 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1351 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1352 if (pmccntr_clockdiv_enabled(env
)) {
1355 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1359 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1362 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1364 if (event_supported(event
)) {
1365 uint16_t event_idx
= supported_event_map
[event
];
1366 count
= pm_events
[event_idx
].get_count(env
);
1369 if (pmu_counter_enabled(env
, counter
)) {
1370 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1371 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1372 1ULL << 63 : 1ULL << 31;
1374 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1375 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1376 pmu_update_irq(env
);
1378 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1380 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1383 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1385 if (pmu_counter_enabled(env
, counter
)) {
1386 #ifndef CONFIG_USER_ONLY
1387 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1388 uint16_t event_idx
= supported_event_map
[event
];
1389 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1390 int64_t overflow_in
;
1392 if (!pmevcntr_is_64_bit(env
, counter
)) {
1393 delta
= (uint32_t)delta
;
1395 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1397 if (overflow_in
> 0) {
1398 int64_t overflow_at
;
1400 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1401 overflow_in
, &overflow_at
)) {
1402 ARMCPU
*cpu
= env_archcpu(env
);
1403 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1408 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1409 env
->cp15
.c14_pmevcntr
[counter
];
1413 void pmu_op_start(CPUARMState
*env
)
1416 pmccntr_op_start(env
);
1417 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1418 pmevcntr_op_start(env
, i
);
1422 void pmu_op_finish(CPUARMState
*env
)
1425 pmccntr_op_finish(env
);
1426 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1427 pmevcntr_op_finish(env
, i
);
1431 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1433 pmu_op_start(&cpu
->env
);
1436 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1438 pmu_op_finish(&cpu
->env
);
1441 void arm_pmu_timer_cb(void *opaque
)
1443 ARMCPU
*cpu
= opaque
;
1446 * Update all the counter values based on the current underlying counts,
1447 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1448 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1449 * counter may expire.
1451 pmu_op_start(&cpu
->env
);
1452 pmu_op_finish(&cpu
->env
);
1455 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 if (value
& PMCRC
) {
1461 /* The counter has been reset */
1462 env
->cp15
.c15_ccnt
= 0;
1465 if (value
& PMCRP
) {
1467 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1468 env
->cp15
.c14_pmevcntr
[i
] = 0;
1472 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1473 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1478 static uint64_t pmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1480 uint64_t pmcr
= env
->cp15
.c9_pmcr
;
1483 * If EL2 is implemented and enabled for the current security state, reads
1484 * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN.
1486 if (arm_current_el(env
) <= 1 && arm_is_el2_enabled(env
)) {
1487 pmcr
&= ~PMCRN_MASK
;
1488 pmcr
|= (env
->cp15
.mdcr_el2
& MDCR_HPMN
) << PMCRN_SHIFT
;
1494 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1498 uint64_t overflow_mask
, new_pmswinc
;
1500 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1501 /* Increment a counter's count iff: */
1502 if ((value
& (1 << i
)) && /* counter's bit is set */
1503 /* counter is enabled and not filtered */
1504 pmu_counter_enabled(env
, i
) &&
1505 /* counter is SW_INCR */
1506 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1507 pmevcntr_op_start(env
, i
);
1510 * Detect if this write causes an overflow since we can't predict
1511 * PMSWINC overflows like we can for other events
1513 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1515 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1516 1ULL << 63 : 1ULL << 31;
1518 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1519 env
->cp15
.c9_pmovsr
|= (1 << i
);
1520 pmu_update_irq(env
);
1523 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1525 pmevcntr_op_finish(env
, i
);
1530 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1533 pmccntr_op_start(env
);
1534 ret
= env
->cp15
.c15_ccnt
;
1535 pmccntr_op_finish(env
);
1539 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1543 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1544 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1545 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1548 env
->cp15
.c9_pmselr
= value
& 0x1f;
1551 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1554 pmccntr_op_start(env
);
1555 env
->cp15
.c15_ccnt
= value
;
1556 pmccntr_op_finish(env
);
1559 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1562 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1564 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1567 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1570 pmccntr_op_start(env
);
1571 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1572 pmccntr_op_finish(env
);
1575 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1578 pmccntr_op_start(env
);
1579 /* M is not accessible from AArch32 */
1580 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1581 (value
& PMCCFILTR
);
1582 pmccntr_op_finish(env
);
1585 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1587 /* M is not visible in AArch32 */
1588 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1591 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1595 value
&= pmu_counter_mask(env
);
1596 env
->cp15
.c9_pmcnten
|= value
;
1600 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1604 value
&= pmu_counter_mask(env
);
1605 env
->cp15
.c9_pmcnten
&= ~value
;
1609 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1612 value
&= pmu_counter_mask(env
);
1613 env
->cp15
.c9_pmovsr
&= ~value
;
1614 pmu_update_irq(env
);
1617 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1620 value
&= pmu_counter_mask(env
);
1621 env
->cp15
.c9_pmovsr
|= value
;
1622 pmu_update_irq(env
);
1625 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1626 uint64_t value
, const uint8_t counter
)
1628 if (counter
== 31) {
1629 pmccfiltr_write(env
, ri
, value
);
1630 } else if (counter
< pmu_num_counters(env
)) {
1631 pmevcntr_op_start(env
, counter
);
1634 * If this counter's event type is changing, store the current
1635 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1636 * pmevcntr_op_finish has the correct baseline when it converts back to
1639 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1640 PMXEVTYPER_EVTCOUNT
;
1641 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1642 if (old_event
!= new_event
) {
1644 if (event_supported(new_event
)) {
1645 uint16_t event_idx
= supported_event_map
[new_event
];
1646 count
= pm_events
[event_idx
].get_count(env
);
1648 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1651 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1652 pmevcntr_op_finish(env
, counter
);
1655 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1656 * PMSELR value is equal to or greater than the number of implemented
1657 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1661 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1662 const uint8_t counter
)
1664 if (counter
== 31) {
1665 return env
->cp15
.pmccfiltr_el0
;
1666 } else if (counter
< pmu_num_counters(env
)) {
1667 return env
->cp15
.c14_pmevtyper
[counter
];
1670 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1671 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1677 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1680 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1681 pmevtyper_write(env
, ri
, value
, counter
);
1684 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1687 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1688 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1691 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1692 * pmu_op_finish calls when loading saved state for a migration. Because
1693 * we're potentially updating the type of event here, the value written to
1694 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1695 * different counter type. Therefore, we need to set this value to the
1696 * current count for the counter type we're writing so that pmu_op_finish
1697 * has the correct count for its calculation.
1699 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1700 if (event_supported(event
)) {
1701 uint16_t event_idx
= supported_event_map
[event
];
1702 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1703 pm_events
[event_idx
].get_count(env
);
1707 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1709 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1710 return pmevtyper_read(env
, ri
, counter
);
1713 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1716 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1719 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1721 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1724 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1725 uint64_t value
, uint8_t counter
)
1727 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1728 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1729 value
&= MAKE_64BIT_MASK(0, 32);
1731 if (counter
< pmu_num_counters(env
)) {
1732 pmevcntr_op_start(env
, counter
);
1733 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1734 pmevcntr_op_finish(env
, counter
);
1737 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1738 * are CONSTRAINED UNPREDICTABLE.
1742 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1745 if (counter
< pmu_num_counters(env
)) {
1747 pmevcntr_op_start(env
, counter
);
1748 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1749 pmevcntr_op_finish(env
, counter
);
1750 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1751 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1752 ret
&= MAKE_64BIT_MASK(0, 32);
1757 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1758 * are CONSTRAINED UNPREDICTABLE.
1764 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1767 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1768 pmevcntr_write(env
, ri
, value
, counter
);
1771 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1773 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1774 return pmevcntr_read(env
, ri
, counter
);
1777 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1780 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1781 assert(counter
< pmu_num_counters(env
));
1782 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1783 pmevcntr_write(env
, ri
, value
, counter
);
1786 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1788 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1789 assert(counter
< pmu_num_counters(env
));
1790 return env
->cp15
.c14_pmevcntr
[counter
];
1793 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1796 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1799 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1801 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1804 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1807 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1808 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1810 env
->cp15
.c9_pmuserenr
= value
& 1;
1814 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1817 /* We have no event counters so only the C bit can be changed */
1818 value
&= pmu_counter_mask(env
);
1819 env
->cp15
.c9_pminten
|= value
;
1820 pmu_update_irq(env
);
1823 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1826 value
&= pmu_counter_mask(env
);
1827 env
->cp15
.c9_pminten
&= ~value
;
1828 pmu_update_irq(env
);
1831 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1835 * Note that even though the AArch64 view of this register has bits
1836 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1837 * architectural requirements for bits which are RES0 only in some
1838 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1839 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1841 raw_write(env
, ri
, value
& ~0x1FULL
);
1844 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1846 /* Begin with base v8.0 state. */
1847 uint64_t valid_mask
= 0x3fff;
1848 ARMCPU
*cpu
= env_archcpu(env
);
1852 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1853 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1854 * Instead, choose the format based on the mode of EL3.
1856 if (arm_el_is_aa64(env
, 3)) {
1857 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1858 valid_mask
&= ~SCR_NET
; /* RES0 */
1860 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1861 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1862 value
|= SCR_RW
; /* RAO/WI */
1864 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1865 valid_mask
|= SCR_TERR
;
1867 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1868 valid_mask
|= SCR_TLOR
;
1870 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1871 valid_mask
|= SCR_API
| SCR_APK
;
1873 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1874 valid_mask
|= SCR_EEL2
;
1875 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1876 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1879 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1880 valid_mask
|= SCR_ATA
;
1882 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1883 valid_mask
|= SCR_ENSCXT
;
1885 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1886 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1888 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1889 valid_mask
|= SCR_ENTP2
;
1891 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1892 valid_mask
|= SCR_HXEN
;
1894 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1895 valid_mask
|= SCR_FGTEN
;
1897 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1898 valid_mask
|= SCR_NSE
| SCR_GPF
;
1901 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1902 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1903 valid_mask
|= SCR_TERR
;
1907 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1908 valid_mask
&= ~SCR_HCE
;
1911 * On ARMv7, SMD (or SCD as it is called in v7) is only
1912 * supported if EL2 exists. The bit is UNK/SBZP when
1913 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1914 * when EL2 is unavailable.
1915 * On ARMv8, this bit is always available.
1917 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1918 !arm_feature(env
, ARM_FEATURE_V8
)) {
1919 valid_mask
&= ~SCR_SMD
;
1923 /* Clear all-context RES0 bits. */
1924 value
&= valid_mask
;
1925 changed
= env
->cp15
.scr_el3
^ value
;
1926 env
->cp15
.scr_el3
= value
;
1929 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1930 * we must invalidate all TLBs below EL3.
1932 if (changed
& (SCR_NS
| SCR_NSE
)) {
1933 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1934 ARMMMUIdxBit_E20_0
|
1935 ARMMMUIdxBit_E10_1
|
1936 ARMMMUIdxBit_E20_2
|
1937 ARMMMUIdxBit_E10_1_PAN
|
1938 ARMMMUIdxBit_E20_2_PAN
|
1943 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1946 * scr_write will set the RES1 bits on an AArch64-only CPU.
1947 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1949 scr_write(env
, ri
, 0);
1952 static CPAccessResult
access_tid4(CPUARMState
*env
,
1953 const ARMCPRegInfo
*ri
,
1956 if (arm_current_el(env
) == 1 &&
1957 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1958 return CP_ACCESS_TRAP_EL2
;
1961 return CP_ACCESS_OK
;
1964 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1966 ARMCPU
*cpu
= env_archcpu(env
);
1969 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1972 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1973 ri
->secure
& ARM_CP_SECSTATE_S
);
1975 return cpu
->ccsidr
[index
];
1978 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1981 raw_write(env
, ri
, value
& 0xf);
1984 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1986 CPUState
*cs
= env_cpu(env
);
1987 bool el1
= arm_current_el(env
) == 1;
1988 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1991 if (hcr_el2
& HCR_IMO
) {
1992 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1996 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2001 if (hcr_el2
& HCR_FMO
) {
2002 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2006 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2011 if (hcr_el2
& HCR_AMO
) {
2012 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2020 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2023 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2024 return CP_ACCESS_TRAP_EL2
;
2027 return CP_ACCESS_OK
;
2030 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2033 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2034 return access_aa64_tid1(env
, ri
, isread
);
2037 return CP_ACCESS_OK
;
2040 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2041 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2042 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2043 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2045 * Performance monitors are implementation defined in v7,
2046 * but with an ARM recommended set of registers, which we
2049 * Performance registers fall into three categories:
2050 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2051 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2052 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2053 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2054 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2056 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2057 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2058 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2059 .writefn
= pmcntenset_write
,
2060 .accessfn
= pmreg_access
,
2062 .raw_writefn
= raw_write
},
2063 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2064 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2065 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2067 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2068 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2069 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2071 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2072 .accessfn
= pmreg_access
,
2074 .writefn
= pmcntenclr_write
,
2075 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2076 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2077 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2078 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2080 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2082 .writefn
= pmcntenclr_write
},
2083 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2084 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2085 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2086 .accessfn
= pmreg_access
,
2088 .writefn
= pmovsr_write
,
2089 .raw_writefn
= raw_write
},
2090 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2091 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2092 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2094 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2095 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2096 .writefn
= pmovsr_write
,
2097 .raw_writefn
= raw_write
},
2098 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2099 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2100 .fgt
= FGT_PMSWINC_EL0
,
2101 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2102 .writefn
= pmswinc_write
},
2103 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2104 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2105 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2106 .fgt
= FGT_PMSWINC_EL0
,
2107 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2108 .writefn
= pmswinc_write
},
2109 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2110 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2111 .fgt
= FGT_PMSELR_EL0
,
2112 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2113 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2114 .raw_writefn
= raw_write
},
2115 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2116 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2117 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2118 .fgt
= FGT_PMSELR_EL0
,
2119 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2120 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2121 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2122 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2123 .fgt
= FGT_PMCCNTR_EL0
,
2124 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2125 .accessfn
= pmreg_access_ccntr
},
2126 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2127 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2128 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2129 .fgt
= FGT_PMCCNTR_EL0
,
2131 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2132 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2133 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2134 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2135 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2136 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2137 .fgt
= FGT_PMCCFILTR_EL0
,
2138 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2140 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2141 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2142 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2143 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2144 .fgt
= FGT_PMCCFILTR_EL0
,
2146 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2148 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2149 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2150 .accessfn
= pmreg_access
,
2151 .fgt
= FGT_PMEVTYPERN_EL0
,
2152 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2153 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2154 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2155 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2156 .accessfn
= pmreg_access
,
2157 .fgt
= FGT_PMEVTYPERN_EL0
,
2158 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2159 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2160 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2161 .accessfn
= pmreg_access_xevcntr
,
2162 .fgt
= FGT_PMEVCNTRN_EL0
,
2163 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2164 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2165 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2166 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2167 .accessfn
= pmreg_access_xevcntr
,
2168 .fgt
= FGT_PMEVCNTRN_EL0
,
2169 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2170 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2171 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2172 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2174 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2175 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2176 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2177 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2178 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2180 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2181 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2182 .access
= PL1_RW
, .accessfn
= access_tpm
,
2184 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2185 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2187 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2188 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2189 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2190 .access
= PL1_RW
, .accessfn
= access_tpm
,
2193 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2194 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2195 .resetvalue
= 0x0 },
2196 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2197 .access
= PL1_RW
, .accessfn
= access_tpm
,
2199 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2200 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2201 .writefn
= pmintenclr_write
, },
2202 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2203 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2204 .access
= PL1_RW
, .accessfn
= access_tpm
,
2206 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2207 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2208 .writefn
= pmintenclr_write
},
2209 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2210 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2212 .accessfn
= access_tid4
,
2213 .fgt
= FGT_CCSIDR_EL1
,
2214 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2215 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2216 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2218 .accessfn
= access_tid4
,
2219 .fgt
= FGT_CSSELR_EL1
,
2220 .writefn
= csselr_write
, .resetvalue
= 0,
2221 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2222 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2224 * Auxiliary ID register: this actually has an IMPDEF value but for now
2225 * just RAZ for all cores:
2227 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2228 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2229 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2230 .accessfn
= access_aa64_tid1
,
2231 .fgt
= FGT_AIDR_EL1
,
2234 * Auxiliary fault status registers: these also are IMPDEF, and we
2235 * choose to RAZ/WI for all cores.
2237 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2238 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2239 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2240 .fgt
= FGT_AFSR0_EL1
,
2241 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2242 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2243 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2244 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2245 .fgt
= FGT_AFSR1_EL1
,
2246 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2248 * MAIR can just read-as-written because we don't implement caches
2249 * and so don't need to care about memory attributes.
2251 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2252 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2253 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2254 .fgt
= FGT_MAIR_EL1
,
2255 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2257 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2258 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2259 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2262 * For non-long-descriptor page tables these are PRRR and NMRR;
2263 * regardless they still act as reads-as-written for QEMU.
2266 * MAIR0/1 are defined separately from their 64-bit counterpart which
2267 * allows them to assign the correct fieldoffset based on the endianness
2268 * handled in the field definitions.
2270 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2271 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2272 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2273 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2274 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2275 .resetfn
= arm_cp_reset_ignore
},
2276 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2277 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2278 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2279 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2280 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2281 .resetfn
= arm_cp_reset_ignore
},
2282 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2283 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2285 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2286 /* 32 bit ITLB invalidates */
2287 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2288 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2289 .writefn
= tlbiall_write
},
2290 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2291 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2292 .writefn
= tlbimva_write
},
2293 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2294 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2295 .writefn
= tlbiasid_write
},
2296 /* 32 bit DTLB invalidates */
2297 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2298 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2299 .writefn
= tlbiall_write
},
2300 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2301 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2302 .writefn
= tlbimva_write
},
2303 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2304 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2305 .writefn
= tlbiasid_write
},
2306 /* 32 bit TLB invalidates */
2307 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2308 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2309 .writefn
= tlbiall_write
},
2310 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2311 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2312 .writefn
= tlbimva_write
},
2313 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2314 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2315 .writefn
= tlbiasid_write
},
2316 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2317 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2318 .writefn
= tlbimvaa_write
},
2321 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2322 /* 32 bit TLB invalidates, Inner Shareable */
2323 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2324 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2325 .writefn
= tlbiall_is_write
},
2326 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2327 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2328 .writefn
= tlbimva_is_write
},
2329 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2330 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2331 .writefn
= tlbiasid_is_write
},
2332 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2333 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2334 .writefn
= tlbimvaa_is_write
},
2337 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2338 /* PMOVSSET is not implemented in v7 before v7ve */
2339 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2340 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2342 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2343 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2344 .writefn
= pmovsset_write
,
2345 .raw_writefn
= raw_write
},
2346 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2347 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2348 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2350 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2351 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2352 .writefn
= pmovsset_write
,
2353 .raw_writefn
= raw_write
},
2356 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2363 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2367 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2368 * at all, so we don't need to check whether we're v8A.
2370 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2371 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2372 return CP_ACCESS_TRAP_EL2
;
2374 return CP_ACCESS_OK
;
2377 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2380 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2381 return CP_ACCESS_TRAP
;
2383 return teecr_access(env
, ri
, isread
);
2386 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2387 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2388 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2390 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2391 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2392 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2393 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2396 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2397 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2398 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2400 .fgt
= FGT_TPIDR_EL0
,
2401 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2402 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2404 .fgt
= FGT_TPIDR_EL0
,
2405 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2406 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2407 .resetfn
= arm_cp_reset_ignore
},
2408 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2409 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2410 .access
= PL0_R
| PL1_W
,
2411 .fgt
= FGT_TPIDRRO_EL0
,
2412 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2414 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2415 .access
= PL0_R
| PL1_W
,
2416 .fgt
= FGT_TPIDRRO_EL0
,
2417 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2418 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2419 .resetfn
= arm_cp_reset_ignore
},
2420 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2421 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2423 .fgt
= FGT_TPIDR_EL1
,
2424 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2425 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2427 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2428 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2432 #ifndef CONFIG_USER_ONLY
2434 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2438 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2439 * Writable only at the highest implemented exception level.
2441 int el
= arm_current_el(env
);
2447 hcr
= arm_hcr_el2_eff(env
);
2448 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2449 cntkctl
= env
->cp15
.cnthctl_el2
;
2451 cntkctl
= env
->cp15
.c14_cntkctl
;
2453 if (!extract32(cntkctl
, 0, 2)) {
2454 return CP_ACCESS_TRAP
;
2458 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2459 arm_is_secure_below_el3(env
)) {
2460 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2461 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2469 if (!isread
&& el
< arm_highest_el(env
)) {
2470 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2473 return CP_ACCESS_OK
;
2476 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2479 unsigned int cur_el
= arm_current_el(env
);
2480 bool has_el2
= arm_is_el2_enabled(env
);
2481 uint64_t hcr
= arm_hcr_el2_eff(env
);
2485 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2486 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2487 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2488 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2491 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2492 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2493 return CP_ACCESS_TRAP
;
2497 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2498 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2500 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2501 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2502 return CP_ACCESS_TRAP_EL2
;
2506 return CP_ACCESS_OK
;
2509 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2512 unsigned int cur_el
= arm_current_el(env
);
2513 bool has_el2
= arm_is_el2_enabled(env
);
2514 uint64_t hcr
= arm_hcr_el2_eff(env
);
2518 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2519 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2520 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2521 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2525 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2526 * EL0 if EL0[PV]TEN is zero.
2528 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2529 return CP_ACCESS_TRAP
;
2534 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2535 if (hcr
& HCR_E2H
) {
2536 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2537 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2538 return CP_ACCESS_TRAP_EL2
;
2541 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2542 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2543 return CP_ACCESS_TRAP_EL2
;
2549 return CP_ACCESS_OK
;
2552 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2553 const ARMCPRegInfo
*ri
,
2556 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2559 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2560 const ARMCPRegInfo
*ri
,
2563 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2566 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2569 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2572 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2575 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2578 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2579 const ARMCPRegInfo
*ri
,
2583 * The AArch64 register view of the secure physical timer is
2584 * always accessible from EL3, and configurably accessible from
2587 switch (arm_current_el(env
)) {
2589 if (!arm_is_secure(env
)) {
2590 return CP_ACCESS_TRAP
;
2592 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2593 return CP_ACCESS_TRAP_EL3
;
2595 return CP_ACCESS_OK
;
2598 return CP_ACCESS_TRAP
;
2600 return CP_ACCESS_OK
;
2602 g_assert_not_reached();
2606 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2608 ARMCPU
*cpu
= env_archcpu(env
);
2610 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2613 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2615 CPUARMState
*env
= &cpu
->env
;
2616 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2617 ARMSecuritySpace ss
= arm_security_space(env
);
2618 /* ISTATUS && !IMASK */
2619 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2622 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2623 * It is RES0 in Secure and NonSecure state.
2625 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2626 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2627 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2631 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2632 trace_arm_gt_update_irq(timeridx
, irqstate
);
2635 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2638 * Changing security state between Root and Secure/NonSecure, which may
2639 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2640 * mask bits. Update the IRQ state accordingly.
2642 gt_update_irq(cpu
, GTIMER_VIRT
);
2643 gt_update_irq(cpu
, GTIMER_PHYS
);
2646 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2648 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2652 * Timer enabled: calculate and set current ISTATUS, irq, and
2653 * reset timer to when ISTATUS next has to change
2655 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2656 cpu
->env
.cp15
.cntvoff_el2
: 0;
2657 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2658 /* Note that this must be unsigned 64 bit arithmetic: */
2659 int istatus
= count
- offset
>= gt
->cval
;
2662 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2666 * Next transition is when (count - offset) rolls back over to 0.
2667 * If offset > count then this is when count == offset;
2668 * if offset <= count then this is when count == offset + 2^64
2669 * For the latter case we set nexttick to an "as far in future
2670 * as possible" value and let the code below handle it.
2672 if (offset
> count
) {
2675 nexttick
= UINT64_MAX
;
2679 * Next transition is when (count - offset) == cval, i.e.
2680 * when count == (cval + offset).
2681 * If that would overflow, then again we set up the next interrupt
2682 * for "as far in the future as possible" for the code below.
2684 if (uadd64_overflow(gt
->cval
, offset
, &nexttick
)) {
2685 nexttick
= UINT64_MAX
;
2689 * Note that the desired next expiry time might be beyond the
2690 * signed-64-bit range of a QEMUTimer -- in this case we just
2691 * set the timer for as far in the future as possible. When the
2692 * timer expires we will reset the timer for any remaining period.
2694 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2695 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2697 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2699 trace_arm_gt_recalc(timeridx
, nexttick
);
2701 /* Timer disabled: ISTATUS and timer output always clear */
2703 timer_del(cpu
->gt_timer
[timeridx
]);
2704 trace_arm_gt_recalc_disabled(timeridx
);
2706 gt_update_irq(cpu
, timeridx
);
2709 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2712 ARMCPU
*cpu
= env_archcpu(env
);
2714 timer_del(cpu
->gt_timer
[timeridx
]);
2717 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2719 return gt_get_countervalue(env
);
2722 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2726 switch (arm_current_el(env
)) {
2728 hcr
= arm_hcr_el2_eff(env
);
2729 if (hcr
& HCR_E2H
) {
2734 hcr
= arm_hcr_el2_eff(env
);
2735 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2741 return env
->cp15
.cntvoff_el2
;
2744 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2746 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2749 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2753 trace_arm_gt_cval_write(timeridx
, value
);
2754 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2755 gt_recalc_timer(env_archcpu(env
), timeridx
);
2758 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2761 uint64_t offset
= 0;
2765 case GTIMER_HYPVIRT
:
2766 offset
= gt_virt_cnt_offset(env
);
2770 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2771 (gt_get_countervalue(env
) - offset
));
2774 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2778 uint64_t offset
= 0;
2782 case GTIMER_HYPVIRT
:
2783 offset
= gt_virt_cnt_offset(env
);
2787 trace_arm_gt_tval_write(timeridx
, value
);
2788 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2789 sextract64(value
, 0, 32);
2790 gt_recalc_timer(env_archcpu(env
), timeridx
);
2793 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2797 ARMCPU
*cpu
= env_archcpu(env
);
2798 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2800 trace_arm_gt_ctl_write(timeridx
, value
);
2801 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2802 if ((oldval
^ value
) & 1) {
2803 /* Enable toggled */
2804 gt_recalc_timer(cpu
, timeridx
);
2805 } else if ((oldval
^ value
) & 2) {
2807 * IMASK toggled: don't need to recalculate,
2808 * just set the interrupt line based on ISTATUS
2810 trace_arm_gt_imask_toggle(timeridx
);
2811 gt_update_irq(cpu
, timeridx
);
2815 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2817 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2820 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2823 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2826 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2828 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2831 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2834 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2837 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2840 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2843 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2845 switch (arm_mmu_idx(env
)) {
2846 case ARMMMUIdx_E20_0
:
2847 case ARMMMUIdx_E20_2
:
2848 case ARMMMUIdx_E20_2_PAN
:
2855 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2857 switch (arm_mmu_idx(env
)) {
2858 case ARMMMUIdx_E20_0
:
2859 case ARMMMUIdx_E20_2
:
2860 case ARMMMUIdx_E20_2_PAN
:
2861 return GTIMER_HYPVIRT
;
2867 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2868 const ARMCPRegInfo
*ri
)
2870 int timeridx
= gt_phys_redir_timeridx(env
);
2871 return env
->cp15
.c14_timer
[timeridx
].cval
;
2874 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2877 int timeridx
= gt_phys_redir_timeridx(env
);
2878 gt_cval_write(env
, ri
, timeridx
, value
);
2881 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2882 const ARMCPRegInfo
*ri
)
2884 int timeridx
= gt_phys_redir_timeridx(env
);
2885 return gt_tval_read(env
, ri
, timeridx
);
2888 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2891 int timeridx
= gt_phys_redir_timeridx(env
);
2892 gt_tval_write(env
, ri
, timeridx
, value
);
2895 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2896 const ARMCPRegInfo
*ri
)
2898 int timeridx
= gt_phys_redir_timeridx(env
);
2899 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2902 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2905 int timeridx
= gt_phys_redir_timeridx(env
);
2906 gt_ctl_write(env
, ri
, timeridx
, value
);
2909 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2911 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2914 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2917 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2920 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2922 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2925 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2928 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2931 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2934 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2937 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2940 ARMCPU
*cpu
= env_archcpu(env
);
2941 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2943 raw_write(env
, ri
, value
);
2945 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2946 gt_update_irq(cpu
, GTIMER_VIRT
);
2947 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2948 gt_update_irq(cpu
, GTIMER_PHYS
);
2952 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2955 ARMCPU
*cpu
= env_archcpu(env
);
2957 trace_arm_gt_cntvoff_write(value
);
2958 raw_write(env
, ri
, value
);
2959 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2962 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2963 const ARMCPRegInfo
*ri
)
2965 int timeridx
= gt_virt_redir_timeridx(env
);
2966 return env
->cp15
.c14_timer
[timeridx
].cval
;
2969 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2972 int timeridx
= gt_virt_redir_timeridx(env
);
2973 gt_cval_write(env
, ri
, timeridx
, value
);
2976 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2977 const ARMCPRegInfo
*ri
)
2979 int timeridx
= gt_virt_redir_timeridx(env
);
2980 return gt_tval_read(env
, ri
, timeridx
);
2983 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2986 int timeridx
= gt_virt_redir_timeridx(env
);
2987 gt_tval_write(env
, ri
, timeridx
, value
);
2990 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2991 const ARMCPRegInfo
*ri
)
2993 int timeridx
= gt_virt_redir_timeridx(env
);
2994 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2997 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3000 int timeridx
= gt_virt_redir_timeridx(env
);
3001 gt_ctl_write(env
, ri
, timeridx
, value
);
3004 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3006 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3009 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3012 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3015 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3017 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3020 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3023 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3026 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3029 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3032 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3034 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3037 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3040 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3043 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3045 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3048 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3051 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3054 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3057 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3060 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3062 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3065 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3068 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3071 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3073 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3076 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3079 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3082 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3085 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3088 void arm_gt_ptimer_cb(void *opaque
)
3090 ARMCPU
*cpu
= opaque
;
3092 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3095 void arm_gt_vtimer_cb(void *opaque
)
3097 ARMCPU
*cpu
= opaque
;
3099 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3102 void arm_gt_htimer_cb(void *opaque
)
3104 ARMCPU
*cpu
= opaque
;
3106 gt_recalc_timer(cpu
, GTIMER_HYP
);
3109 void arm_gt_stimer_cb(void *opaque
)
3111 ARMCPU
*cpu
= opaque
;
3113 gt_recalc_timer(cpu
, GTIMER_SEC
);
3116 void arm_gt_hvtimer_cb(void *opaque
)
3118 ARMCPU
*cpu
= opaque
;
3120 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3123 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3125 ARMCPU
*cpu
= env_archcpu(env
);
3127 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3130 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3132 * Note that CNTFRQ is purely reads-as-written for the benefit
3133 * of software; writing it doesn't actually change the timer frequency.
3134 * Our reset value matches the fixed frequency we implement the timer at.
3136 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3137 .type
= ARM_CP_ALIAS
,
3138 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3139 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3141 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3142 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3143 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3144 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3145 .resetfn
= arm_gt_cntfrq_reset
,
3147 /* overall control: mostly access permissions */
3148 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3149 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3151 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3154 /* per-timer control */
3155 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3156 .secure
= ARM_CP_SECSTATE_NS
,
3157 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3158 .accessfn
= gt_ptimer_access
,
3159 .fieldoffset
= offsetoflow32(CPUARMState
,
3160 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3161 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3162 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3164 { .name
= "CNTP_CTL_S",
3165 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3166 .secure
= ARM_CP_SECSTATE_S
,
3167 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3168 .accessfn
= gt_ptimer_access
,
3169 .fieldoffset
= offsetoflow32(CPUARMState
,
3170 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3171 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3173 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3174 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3175 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3176 .accessfn
= gt_ptimer_access
,
3177 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3179 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3180 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3182 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3183 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3184 .accessfn
= gt_vtimer_access
,
3185 .fieldoffset
= offsetoflow32(CPUARMState
,
3186 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3187 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3188 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3190 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3191 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3192 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3193 .accessfn
= gt_vtimer_access
,
3194 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3196 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3197 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3199 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3200 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3201 .secure
= ARM_CP_SECSTATE_NS
,
3202 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3203 .accessfn
= gt_ptimer_access
,
3204 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3206 { .name
= "CNTP_TVAL_S",
3207 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3208 .secure
= ARM_CP_SECSTATE_S
,
3209 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3210 .accessfn
= gt_ptimer_access
,
3211 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3213 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3214 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3215 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3216 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3217 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3219 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3220 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3221 .accessfn
= gt_vtimer_access
,
3222 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3224 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3225 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3226 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3227 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3228 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3230 /* The counter itself */
3231 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3232 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3233 .accessfn
= gt_pct_access
,
3234 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3236 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3238 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3239 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3241 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3242 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3243 .accessfn
= gt_vct_access
,
3244 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3246 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3247 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3248 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3249 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3251 /* Comparison value, indicating when the timer goes off */
3252 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3253 .secure
= ARM_CP_SECSTATE_NS
,
3255 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3256 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3257 .accessfn
= gt_ptimer_access
,
3258 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3259 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3261 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3262 .secure
= ARM_CP_SECSTATE_S
,
3264 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3265 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3266 .accessfn
= gt_ptimer_access
,
3267 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3269 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3270 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3273 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3274 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3275 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3276 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3278 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3280 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3281 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3282 .accessfn
= gt_vtimer_access
,
3283 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3284 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3286 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3287 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3291 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3292 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3293 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3296 * Secure timer -- this is actually restricted to only EL3
3297 * and configurably Secure-EL1 via the accessfn.
3299 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3300 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3301 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3302 .accessfn
= gt_stimer_access
,
3303 .readfn
= gt_sec_tval_read
,
3304 .writefn
= gt_sec_tval_write
,
3305 .resetfn
= gt_sec_timer_reset
,
3307 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3308 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3309 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3310 .accessfn
= gt_stimer_access
,
3311 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3313 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3315 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3316 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3317 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3318 .accessfn
= gt_stimer_access
,
3319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3320 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3324 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3327 if (arm_current_el(env
) == 1) {
3328 /* This must be a FEAT_NV access */
3329 /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
3330 return CP_ACCESS_OK
;
3332 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3333 return CP_ACCESS_TRAP
;
3335 return CP_ACCESS_OK
;
3341 * In user-mode most of the generic timer registers are inaccessible
3342 * however modern kernels (4.12+) allow access to cntvct_el0
3345 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3347 ARMCPU
*cpu
= env_archcpu(env
);
3350 * Currently we have no support for QEMUTimer in linux-user so we
3351 * can't call gt_get_countervalue(env), instead we directly
3352 * call the lower level functions.
3354 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3357 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3358 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3359 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3360 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3361 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3362 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3364 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3365 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3366 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3367 .readfn
= gt_virt_cnt_read
,
3373 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3375 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3376 raw_write(env
, ri
, value
);
3377 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3378 raw_write(env
, ri
, value
& 0xfffff6ff);
3380 raw_write(env
, ri
, value
& 0xfffff1ff);
3384 #ifndef CONFIG_USER_ONLY
3385 /* get_phys_addr() isn't present for user-mode-only targets */
3387 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3392 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3393 * Secure EL1 (which can only happen if EL3 is AArch64).
3394 * They are simply UNDEF if executed from NS EL1.
3395 * They function normally from EL2 or EL3.
3397 if (arm_current_el(env
) == 1) {
3398 if (arm_is_secure_below_el3(env
)) {
3399 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3400 return CP_ACCESS_TRAP_EL2
;
3402 return CP_ACCESS_TRAP_EL3
;
3404 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3407 return CP_ACCESS_OK
;
3411 static int par_el1_shareability(GetPhysAddrResult
*res
)
3414 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3415 * memory -- see pseudocode PAREncodeShareability().
3417 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3418 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3421 return res
->cacheattrs
.shareability
;
3424 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3425 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3426 ARMSecuritySpace ss
)
3430 bool format64
= false;
3431 ARMMMUFaultInfo fi
= {};
3432 GetPhysAddrResult res
= {};
3435 * I_MXTJT: Granule protection checks are not performed on the final address
3436 * of a successful translation.
3438 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3442 * ATS operations only do S1 or S1+S2 translations, so we never
3443 * have to deal with the ARMCacheAttrs format for S2 only.
3445 assert(!res
.cacheattrs
.is_s2_format
);
3449 * Some kinds of translation fault must cause exceptions rather
3450 * than being reported in the PAR.
3452 int current_el
= arm_current_el(env
);
3454 uint32_t syn
, fsr
, fsc
;
3455 bool take_exc
= false;
3457 if (fi
.s1ptw
&& current_el
== 1
3458 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3460 * Synchronous stage 2 fault on an access made as part of the
3461 * translation table walk for AT S1E0* or AT S1E1* insn
3462 * executed from NS EL1. If this is a synchronous external abort
3463 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3464 * to EL3. Otherwise the fault is taken as an exception to EL2,
3465 * and HPFAR_EL2 holds the faulting IPA.
3467 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3468 (env
->cp15
.scr_el3
& SCR_EA
)) {
3471 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3472 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3473 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3478 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3480 * Synchronous external aborts during a translation table walk
3481 * are taken as Data Abort exceptions.
3484 if (current_el
== 3) {
3490 target_el
= exception_target_el(env
);
3496 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3497 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3498 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3499 fsr
= arm_fi_to_lfsc(&fi
);
3500 fsc
= extract32(fsr
, 0, 6);
3502 fsr
= arm_fi_to_sfsc(&fi
);
3506 * Report exception with ESR indicating a fault due to a
3507 * translation table walk for a cache maintenance instruction.
3509 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3510 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3511 env
->exception
.vaddress
= value
;
3512 env
->exception
.fsr
= fsr
;
3513 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3519 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3522 * * TTBCR.EAE determines whether the result is returned using the
3523 * 32-bit or the 64-bit PAR format
3524 * * Instructions executed in Hyp mode always use the 64bit format
3526 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3527 * * The Non-secure TTBCR.EAE bit is set to 1
3528 * * The implementation includes EL2, and the value of HCR.VM is 1
3530 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3532 * ATS1Hx always uses the 64bit format.
3534 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3536 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3537 if (mmu_idx
== ARMMMUIdx_E10_0
||
3538 mmu_idx
== ARMMMUIdx_E10_1
||
3539 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3540 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3542 format64
|= arm_current_el(env
) == 2;
3548 /* Create a 64-bit PAR */
3549 par64
= (1 << 11); /* LPAE bit always set */
3551 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3552 if (!res
.f
.attrs
.secure
) {
3553 par64
|= (1 << 9); /* NS */
3555 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3556 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3558 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3561 par64
|= (fsr
& 0x3f) << 1; /* FS */
3563 par64
|= (1 << 9); /* S */
3566 par64
|= (1 << 8); /* PTW */
3571 * fsr is a DFSR/IFSR value for the short descriptor
3572 * translation table format (with WnR always clear).
3573 * Convert it to a 32-bit PAR.
3576 /* We do not set any attribute bits in the PAR */
3577 if (res
.f
.lg_page_size
== 24
3578 && arm_feature(env
, ARM_FEATURE_V7
)) {
3579 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3581 par64
= res
.f
.phys_addr
& 0xfffff000;
3583 if (!res
.f
.attrs
.secure
) {
3584 par64
|= (1 << 9); /* NS */
3587 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3589 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3590 ((fsr
& 0xf) << 1) | 1;
3595 #endif /* CONFIG_TCG */
3597 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3600 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3603 int el
= arm_current_el(env
);
3604 ARMSecuritySpace ss
= arm_security_space(env
);
3606 switch (ri
->opc2
& 6) {
3608 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3611 mmu_idx
= ARMMMUIdx_E3
;
3614 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3617 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3618 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3620 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3624 g_assert_not_reached();
3628 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3631 mmu_idx
= ARMMMUIdx_E10_0
;
3634 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3635 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3638 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3641 g_assert_not_reached();
3645 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3646 mmu_idx
= ARMMMUIdx_E10_1
;
3647 ss
= ARMSS_NonSecure
;
3650 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3651 mmu_idx
= ARMMMUIdx_E10_0
;
3652 ss
= ARMSS_NonSecure
;
3655 g_assert_not_reached();
3658 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3660 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3662 /* Handled by hardware accelerator. */
3663 g_assert_not_reached();
3664 #endif /* CONFIG_TCG */
3667 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3671 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3674 /* There is no SecureEL2 for AArch32. */
3675 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3678 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3680 /* Handled by hardware accelerator. */
3681 g_assert_not_reached();
3682 #endif /* CONFIG_TCG */
3685 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3689 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3690 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3691 * only happen when executing at EL3 because that combination also causes an
3692 * illegal exception return. We don't need to check FEAT_RME either, because
3693 * scr_write() ensures that the NSE bit is not set otherwise.
3695 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3696 return CP_ACCESS_TRAP
;
3698 return CP_ACCESS_OK
;
3701 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3704 if (arm_current_el(env
) == 3 &&
3705 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3706 return CP_ACCESS_TRAP
;
3708 return at_e012_access(env
, ri
, isread
);
3711 static CPAccessResult
at_s1e01_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3714 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_AT
)) {
3715 return CP_ACCESS_TRAP_EL2
;
3717 return at_e012_access(env
, ri
, isread
);
3720 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3724 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3726 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3727 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3729 switch (ri
->opc2
& 6) {
3732 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3733 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3734 mmu_idx
= regime_e20
?
3735 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3737 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3740 case 4: /* AT S1E2R, AT S1E2W */
3741 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3743 case 6: /* AT S1E3R, AT S1E3W */
3744 mmu_idx
= ARMMMUIdx_E3
;
3747 g_assert_not_reached();
3750 case 2: /* AT S1E0R, AT S1E0W */
3751 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3753 case 4: /* AT S12E1R, AT S12E1W */
3754 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3756 case 6: /* AT S12E0R, AT S12E0W */
3757 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3760 g_assert_not_reached();
3763 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3764 mmu_idx
, arm_security_space(env
));
3766 /* Handled by hardware accelerator. */
3767 g_assert_not_reached();
3768 #endif /* CONFIG_TCG */
3772 /* Return basic MPU access permission bits. */
3773 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3780 for (i
= 0; i
< 16; i
+= 2) {
3781 ret
|= (val
>> i
) & mask
;
3787 /* Pad basic MPU access permission bits to extended format. */
3788 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3795 for (i
= 0; i
< 16; i
+= 2) {
3796 ret
|= (val
& mask
) << i
;
3802 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3805 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3808 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3810 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3813 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3816 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3819 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3821 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3824 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3826 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3832 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3836 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3839 ARMCPU
*cpu
= env_archcpu(env
);
3840 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3846 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3847 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3851 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3854 ARMCPU
*cpu
= env_archcpu(env
);
3855 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3857 if (value
>= nrgs
) {
3858 qemu_log_mask(LOG_GUEST_ERROR
,
3859 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3860 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3864 raw_write(env
, ri
, value
);
3867 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3870 ARMCPU
*cpu
= env_archcpu(env
);
3872 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3873 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3876 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3878 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3881 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3884 ARMCPU
*cpu
= env_archcpu(env
);
3886 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3887 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3890 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3892 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3895 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3898 ARMCPU
*cpu
= env_archcpu(env
);
3901 * Ignore writes that would select not implemented region.
3902 * This is architecturally UNPREDICTABLE.
3904 if (value
>= cpu
->pmsav7_dregion
) {
3908 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3911 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3914 ARMCPU
*cpu
= env_archcpu(env
);
3916 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3917 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3920 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3922 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3925 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3928 ARMCPU
*cpu
= env_archcpu(env
);
3930 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3931 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3934 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3936 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3939 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3944 ARMCPU
*cpu
= env_archcpu(env
);
3946 /* Ignore writes to unimplemented regions */
3947 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3948 value
&= MAKE_64BIT_MASK(0, rmax
);
3950 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3952 /* Register alias is only valid for first 32 indexes */
3953 for (n
= 0; n
< rmax
; ++n
) {
3954 bit
= extract32(value
, n
, 1);
3955 env
->pmsav8
.hprlar
[n
] = deposit32(
3956 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3960 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3963 uint32_t result
= 0x0;
3964 ARMCPU
*cpu
= env_archcpu(env
);
3966 /* Register alias is only valid for first 32 indexes */
3967 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3968 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3969 result
|= (0x1 << n
);
3975 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3978 ARMCPU
*cpu
= env_archcpu(env
);
3981 * Ignore writes that would select not implemented region.
3982 * This is architecturally UNPREDICTABLE.
3984 if (value
>= cpu
->pmsav8r_hdregion
) {
3988 env
->pmsav8
.hprselr
= value
;
3991 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3994 ARMCPU
*cpu
= env_archcpu(env
);
3995 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3996 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3998 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4001 if (index
>= cpu
->pmsav8r_hdregion
) {
4004 if (ri
->opc2
& 0x1) {
4005 env
->pmsav8
.hprlar
[index
] = value
;
4007 env
->pmsav8
.hprbar
[index
] = value
;
4010 if (index
>= cpu
->pmsav7_dregion
) {
4013 if (ri
->opc2
& 0x1) {
4014 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
4016 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
4021 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4023 ARMCPU
*cpu
= env_archcpu(env
);
4024 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4025 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4028 if (index
>= cpu
->pmsav8r_hdregion
) {
4031 if (ri
->opc2
& 0x1) {
4032 return env
->pmsav8
.hprlar
[index
];
4034 return env
->pmsav8
.hprbar
[index
];
4037 if (index
>= cpu
->pmsav7_dregion
) {
4040 if (ri
->opc2
& 0x1) {
4041 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4043 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4048 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4050 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4051 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4052 .accessfn
= access_tvm_trvm
,
4053 .readfn
= prbar_read
, .writefn
= prbar_write
},
4055 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4056 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4057 .accessfn
= access_tvm_trvm
,
4058 .readfn
= prlar_read
, .writefn
= prlar_write
},
4059 { .name
= "PRSELR", .resetvalue
= 0,
4060 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4061 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4062 .writefn
= prselr_write
,
4063 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4064 { .name
= "HPRBAR", .resetvalue
= 0,
4065 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4066 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4067 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4069 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4070 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4071 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4072 { .name
= "HPRSELR", .resetvalue
= 0,
4073 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4075 .writefn
= hprselr_write
,
4076 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4078 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4079 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4080 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4083 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4085 * Reset for all these registers is handled in arm_cpu_reset(),
4086 * because the PMSAv7 is also used by M-profile CPUs, which do
4087 * not register cpregs but still need the state to be reset.
4089 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4090 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4091 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4092 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4093 .resetfn
= arm_cp_reset_ignore
},
4094 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4095 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4096 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4097 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4098 .resetfn
= arm_cp_reset_ignore
},
4099 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4100 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4101 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4102 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4103 .resetfn
= arm_cp_reset_ignore
},
4104 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4106 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4107 .writefn
= pmsav7_rgnr_write
,
4108 .resetfn
= arm_cp_reset_ignore
},
4111 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4112 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4113 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4114 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4115 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4116 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4117 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4118 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4119 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4120 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4122 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4124 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4126 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4128 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4130 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4131 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4133 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4134 /* Protection region base and size registers */
4135 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4136 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4137 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4138 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4139 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4141 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4142 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4143 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4144 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4145 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4146 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4147 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4148 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4149 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4150 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4151 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4152 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4153 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4154 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4155 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4156 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4157 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4158 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4161 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4164 ARMCPU
*cpu
= env_archcpu(env
);
4166 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4167 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4169 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4170 * using Long-descriptor translation table format
4172 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4173 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4175 * In an implementation that includes the Security Extensions
4176 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4177 * Short-descriptor translation table format.
4179 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4185 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4187 * With LPAE the TTBCR could result in a change of ASID
4188 * via the TTBCR.A1 bit, so do a TLB flush.
4190 tlb_flush(CPU(cpu
));
4192 raw_write(env
, ri
, value
);
4195 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4198 ARMCPU
*cpu
= env_archcpu(env
);
4200 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4201 tlb_flush(CPU(cpu
));
4202 raw_write(env
, ri
, value
);
4205 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4208 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4209 if (cpreg_field_is_64bit(ri
) &&
4210 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4211 ARMCPU
*cpu
= env_archcpu(env
);
4212 tlb_flush(CPU(cpu
));
4214 raw_write(env
, ri
, value
);
4217 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4221 * If we are running with E2&0 regime, then an ASID is active.
4222 * Flush if that might be changing. Note we're not checking
4223 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4224 * holds the active ASID, only checking the field that might.
4226 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4227 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4228 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4229 ARMMMUIdxBit_E20_2_PAN
|
4231 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4233 raw_write(env
, ri
, value
);
4236 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4239 ARMCPU
*cpu
= env_archcpu(env
);
4240 CPUState
*cs
= CPU(cpu
);
4243 * A change in VMID to the stage2 page table (Stage2) invalidates
4244 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4246 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4247 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4249 raw_write(env
, ri
, value
);
4252 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4253 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4254 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4255 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4256 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4257 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4258 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4259 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4260 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4261 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4262 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4263 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4264 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4265 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4266 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4267 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4269 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4273 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4274 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4275 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4276 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4278 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4279 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4280 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4281 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4282 .fgt
= FGT_TTBR0_EL1
,
4283 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4284 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4285 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4286 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4287 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4288 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4289 .fgt
= FGT_TTBR1_EL1
,
4290 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4291 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4292 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4293 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4294 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4295 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4297 .writefn
= vmsa_tcr_el12_write
,
4298 .raw_writefn
= raw_write
,
4300 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4301 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4302 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4303 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4304 .raw_writefn
= raw_write
,
4305 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4306 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4310 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4311 * qemu tlbs nor adjusting cached masks.
4313 static const ARMCPRegInfo ttbcr2_reginfo
= {
4314 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4315 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4316 .type
= ARM_CP_ALIAS
,
4317 .bank_fieldoffsets
= {
4318 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4319 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4323 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4326 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4327 /* The OS_TYPE bit in this register changes the reported CPUID! */
4328 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4329 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4332 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4335 env
->cp15
.c15_threadid
= value
& 0xffff;
4338 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4341 /* Wait-for-interrupt (deprecated) */
4342 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4345 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4349 * On OMAP there are registers indicating the max/min index of dcache lines
4350 * containing a dirty line; cache flush operations have to reset these.
4352 env
->cp15
.c15_i_max
= 0x000;
4353 env
->cp15
.c15_i_min
= 0xff0;
4356 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4357 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4358 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4359 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4361 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4362 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4363 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4365 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4366 .writefn
= omap_ticonfig_write
},
4367 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4369 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4370 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4371 .access
= PL1_RW
, .resetvalue
= 0xff0,
4372 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4373 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4375 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4376 .writefn
= omap_threadid_write
},
4377 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4378 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4379 .type
= ARM_CP_NO_RAW
,
4380 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4382 * TODO: Peripheral port remap register:
4383 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4384 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4387 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4388 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4389 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4390 .writefn
= omap_cachemaint_write
},
4391 { .name
= "C9", .cp
= 15, .crn
= 9,
4392 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4393 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4396 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4399 env
->cp15
.c15_cpar
= value
& 0x3fff;
4402 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4403 { .name
= "XSCALE_CPAR",
4404 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4405 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4406 .writefn
= xscale_cpar_write
, },
4407 { .name
= "XSCALE_AUXCR",
4408 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4409 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4412 * XScale specific cache-lockdown: since we have no cache we NOP these
4413 * and hope the guest does not really rely on cache behaviour.
4415 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4416 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4417 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4418 { .name
= "XSCALE_UNLOCK_ICACHE",
4419 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4420 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4421 { .name
= "XSCALE_DCACHE_LOCK",
4422 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4423 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4424 { .name
= "XSCALE_UNLOCK_DCACHE",
4425 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4426 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4429 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4431 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4432 * implementation of this implementation-defined space.
4433 * Ideally this should eventually disappear in favour of actually
4434 * implementing the correct behaviour for all cores.
4436 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4437 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4439 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4443 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4444 /* Cache status: RAZ because we have no cache so it's always clean */
4445 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4446 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4450 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4451 /* We never have a block transfer operation in progress */
4452 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4453 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4455 /* The cache ops themselves: these all NOP for QEMU */
4456 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4457 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4458 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4459 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4460 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4461 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4462 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4463 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4464 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4465 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4466 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4467 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4470 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4472 * The cache test-and-clean instructions always return (1 << 30)
4473 * to indicate that there are no dirty cache lines.
4475 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4476 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4477 .resetvalue
= (1 << 30) },
4478 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4479 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4480 .resetvalue
= (1 << 30) },
4483 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4484 /* Ignore ReadBuffer accesses */
4485 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4486 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4487 .access
= PL1_RW
, .resetvalue
= 0,
4488 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4491 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4493 unsigned int cur_el
= arm_current_el(env
);
4495 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4496 return env
->cp15
.vpidr_el2
;
4498 return raw_read(env
, ri
);
4501 static uint64_t mpidr_read_val(CPUARMState
*env
)
4503 ARMCPU
*cpu
= env_archcpu(env
);
4504 uint64_t mpidr
= cpu
->mp_affinity
;
4506 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4507 mpidr
|= (1U << 31);
4509 * Cores which are uniprocessor (non-coherent)
4510 * but still implement the MP extensions set
4511 * bit 30. (For instance, Cortex-R5).
4513 if (cpu
->mp_is_up
) {
4514 mpidr
|= (1u << 30);
4520 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4522 unsigned int cur_el
= arm_current_el(env
);
4524 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4525 return env
->cp15
.vmpidr_el2
;
4527 return mpidr_read_val(env
);
4530 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4532 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4533 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4534 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4535 .fgt
= FGT_AMAIR_EL1
,
4536 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4537 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4538 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4539 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4540 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4541 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4542 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4543 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4544 offsetof(CPUARMState
, cp15
.par_ns
)} },
4545 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4546 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4547 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4548 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4549 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4550 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4551 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4552 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4553 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4554 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4555 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4556 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4559 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4561 return vfp_get_fpcr(env
);
4564 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4567 vfp_set_fpcr(env
, value
);
4570 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4572 return vfp_get_fpsr(env
);
4575 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4578 vfp_set_fpsr(env
, value
);
4581 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4584 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4585 return CP_ACCESS_TRAP
;
4587 return CP_ACCESS_OK
;
4590 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4593 env
->daif
= value
& PSTATE_DAIF
;
4596 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4598 return env
->pstate
& PSTATE_PAN
;
4601 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4604 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4607 static const ARMCPRegInfo pan_reginfo
= {
4608 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4609 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4610 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4611 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4614 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4616 return env
->pstate
& PSTATE_UAO
;
4619 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4622 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4625 static const ARMCPRegInfo uao_reginfo
= {
4626 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4627 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4628 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4629 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4632 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4634 return env
->pstate
& PSTATE_DIT
;
4637 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4640 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4643 static const ARMCPRegInfo dit_reginfo
= {
4644 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4645 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4646 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4647 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4650 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4652 return env
->pstate
& PSTATE_SSBS
;
4655 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4658 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4661 static const ARMCPRegInfo ssbs_reginfo
= {
4662 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4663 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4664 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4665 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4668 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4669 const ARMCPRegInfo
*ri
,
4672 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4673 switch (arm_current_el(env
)) {
4675 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4676 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4677 return CP_ACCESS_TRAP
;
4681 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4682 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4683 return CP_ACCESS_TRAP_EL2
;
4687 return CP_ACCESS_OK
;
4690 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4692 /* Cache invalidate/clean to Point of Unification... */
4693 switch (arm_current_el(env
)) {
4695 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4696 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4697 return CP_ACCESS_TRAP
;
4701 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4702 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4703 return CP_ACCESS_TRAP_EL2
;
4707 return CP_ACCESS_OK
;
4710 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4713 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4716 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4719 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4723 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4724 * Page D4-1736 (DDI0487A.b)
4727 static int vae1_tlbmask(CPUARMState
*env
)
4729 uint64_t hcr
= arm_hcr_el2_eff(env
);
4732 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4733 mask
= ARMMMUIdxBit_E20_2
|
4734 ARMMMUIdxBit_E20_2_PAN
|
4737 mask
= ARMMMUIdxBit_E10_1
|
4738 ARMMMUIdxBit_E10_1_PAN
|
4744 static int vae2_tlbmask(CPUARMState
*env
)
4746 uint64_t hcr
= arm_hcr_el2_eff(env
);
4749 if (hcr
& HCR_E2H
) {
4750 mask
= ARMMMUIdxBit_E20_2
|
4751 ARMMMUIdxBit_E20_2_PAN
|
4754 mask
= ARMMMUIdxBit_E2
;
4759 /* Return 56 if TBI is enabled, 64 otherwise. */
4760 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4763 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4764 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4765 int select
= extract64(addr
, 55, 1);
4767 return (tbi
>> select
) & 1 ? 56 : 64;
4770 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4772 uint64_t hcr
= arm_hcr_el2_eff(env
);
4775 /* Only the regime of the mmu_idx below is significant. */
4776 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4777 mmu_idx
= ARMMMUIdx_E20_0
;
4779 mmu_idx
= ARMMMUIdx_E10_0
;
4782 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4785 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4787 uint64_t hcr
= arm_hcr_el2_eff(env
);
4791 * Only the regime of the mmu_idx below is significant.
4792 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4795 if (hcr
& HCR_E2H
) {
4796 mmu_idx
= ARMMMUIdx_E20_2
;
4798 mmu_idx
= ARMMMUIdx_E2
;
4801 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4804 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4807 CPUState
*cs
= env_cpu(env
);
4808 int mask
= vae1_tlbmask(env
);
4810 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4813 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4816 CPUState
*cs
= env_cpu(env
);
4817 int mask
= vae1_tlbmask(env
);
4819 if (tlb_force_broadcast(env
)) {
4820 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4822 tlb_flush_by_mmuidx(cs
, mask
);
4826 static int e2_tlbmask(CPUARMState
*env
)
4828 return (ARMMMUIdxBit_E20_0
|
4829 ARMMMUIdxBit_E20_2
|
4830 ARMMMUIdxBit_E20_2_PAN
|
4834 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4837 CPUState
*cs
= env_cpu(env
);
4838 int mask
= alle1_tlbmask(env
);
4840 tlb_flush_by_mmuidx(cs
, mask
);
4843 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4846 CPUState
*cs
= env_cpu(env
);
4847 int mask
= e2_tlbmask(env
);
4849 tlb_flush_by_mmuidx(cs
, mask
);
4852 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4855 ARMCPU
*cpu
= env_archcpu(env
);
4856 CPUState
*cs
= CPU(cpu
);
4858 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4861 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4864 CPUState
*cs
= env_cpu(env
);
4865 int mask
= alle1_tlbmask(env
);
4867 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4870 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4873 CPUState
*cs
= env_cpu(env
);
4874 int mask
= e2_tlbmask(env
);
4876 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4879 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4882 CPUState
*cs
= env_cpu(env
);
4884 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4887 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4891 * Invalidate by VA, EL2
4892 * Currently handles both VAE2 and VALE2, since we don't support
4893 * flush-last-level-only.
4895 CPUState
*cs
= env_cpu(env
);
4896 int mask
= vae2_tlbmask(env
);
4897 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4898 int bits
= vae2_tlbbits(env
, pageaddr
);
4900 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4903 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4907 * Invalidate by VA, EL3
4908 * Currently handles both VAE3 and VALE3, since we don't support
4909 * flush-last-level-only.
4911 ARMCPU
*cpu
= env_archcpu(env
);
4912 CPUState
*cs
= CPU(cpu
);
4913 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4915 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4918 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4921 CPUState
*cs
= env_cpu(env
);
4922 int mask
= vae1_tlbmask(env
);
4923 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4924 int bits
= vae1_tlbbits(env
, pageaddr
);
4926 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4929 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4933 * Invalidate by VA, EL1&0 (AArch64 version).
4934 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4935 * since we don't support flush-for-specific-ASID-only or
4936 * flush-last-level-only.
4938 CPUState
*cs
= env_cpu(env
);
4939 int mask
= vae1_tlbmask(env
);
4940 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4941 int bits
= vae1_tlbbits(env
, pageaddr
);
4943 if (tlb_force_broadcast(env
)) {
4944 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4946 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4950 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4953 CPUState
*cs
= env_cpu(env
);
4954 int mask
= vae2_tlbmask(env
);
4955 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4956 int bits
= vae2_tlbbits(env
, pageaddr
);
4958 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4961 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4964 CPUState
*cs
= env_cpu(env
);
4965 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4966 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4968 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4969 ARMMMUIdxBit_E3
, bits
);
4972 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4975 * The MSB of value is the NS field, which only applies if SEL2
4976 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4979 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4980 && arm_is_secure_below_el3(env
)
4981 ? ARMMMUIdxBit_Stage2_S
4982 : ARMMMUIdxBit_Stage2
);
4985 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4988 CPUState
*cs
= env_cpu(env
);
4989 int mask
= ipas2e1_tlbmask(env
, value
);
4990 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4992 if (tlb_force_broadcast(env
)) {
4993 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4995 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4999 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5002 CPUState
*cs
= env_cpu(env
);
5003 int mask
= ipas2e1_tlbmask(env
, value
);
5004 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5006 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5009 #ifdef TARGET_AARCH64
5015 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
5018 * Note that the TLBI range TG field encoding differs from both
5019 * TG0 and TG1 encodings.
5033 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5036 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5037 /* Extract one bit to represent the va selector in use. */
5038 uint64_t select
= sextract64(value
, 36, 1);
5039 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5040 TLBIRange ret
= { };
5041 ARMGranuleSize gran
;
5043 page_size_granule
= extract64(value
, 46, 2);
5044 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5046 /* The granule encoded in value must match the granule in use. */
5047 if (gran
!= param
.gran
) {
5048 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5053 page_shift
= arm_granule_bits(gran
);
5054 num
= extract64(value
, 39, 5);
5055 scale
= extract64(value
, 44, 2);
5056 exponent
= (5 * scale
) + 1;
5058 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5061 ret
.base
= sextract64(value
, 0, 37);
5063 ret
.base
= extract64(value
, 0, 37);
5067 * With DS=1, BaseADDR is always shifted 16 so that it is able
5068 * to address all 52 va bits. The input address is perforce
5069 * aligned on a 64k boundary regardless of translation granule.
5073 ret
.base
<<= page_shift
;
5078 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5079 int idxmap
, bool synced
)
5081 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5085 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5086 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5089 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5095 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5096 range
.length
, idxmap
, bits
);
5100 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5101 const ARMCPRegInfo
*ri
,
5105 * Invalidate by VA range, EL1&0.
5106 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5107 * since we don't support flush-for-specific-ASID-only or
5108 * flush-last-level-only.
5111 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5112 tlb_force_broadcast(env
));
5115 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5116 const ARMCPRegInfo
*ri
,
5120 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5121 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5122 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5123 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5124 * shareable specific flushes.
5127 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5130 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5131 const ARMCPRegInfo
*ri
,
5135 * Invalidate by VA range, EL2.
5136 * Currently handles all of RVAE2 and RVALE2,
5137 * since we don't support flush-for-specific-ASID-only or
5138 * flush-last-level-only.
5141 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5142 tlb_force_broadcast(env
));
5147 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5148 const ARMCPRegInfo
*ri
,
5152 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5153 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5154 * since we don't support flush-for-specific-ASID-only,
5155 * flush-last-level-only or inner/outer shareable specific flushes.
5158 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5162 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5163 const ARMCPRegInfo
*ri
,
5167 * Invalidate by VA range, EL3.
5168 * Currently handles all of RVAE3 and RVALE3,
5169 * since we don't support flush-for-specific-ASID-only or
5170 * flush-last-level-only.
5173 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5176 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5177 const ARMCPRegInfo
*ri
,
5181 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5182 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5183 * since we don't support flush-for-specific-ASID-only,
5184 * flush-last-level-only or inner/outer specific flushes.
5187 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5190 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5193 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5194 tlb_force_broadcast(env
));
5197 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5198 const ARMCPRegInfo
*ri
,
5201 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5205 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5208 int cur_el
= arm_current_el(env
);
5211 uint64_t hcr
= arm_hcr_el2_eff(env
);
5214 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5215 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5216 return CP_ACCESS_TRAP_EL2
;
5219 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5220 return CP_ACCESS_TRAP
;
5222 if (hcr
& HCR_TDZ
) {
5223 return CP_ACCESS_TRAP_EL2
;
5226 } else if (hcr
& HCR_TDZ
) {
5227 return CP_ACCESS_TRAP_EL2
;
5230 return CP_ACCESS_OK
;
5233 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5235 ARMCPU
*cpu
= env_archcpu(env
);
5236 int dzp_bit
= 1 << 4;
5238 /* DZP indicates whether DC ZVA access is allowed */
5239 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5242 return cpu
->dcz_blocksize
| dzp_bit
;
5245 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5248 if (!(env
->pstate
& PSTATE_SP
)) {
5250 * Access to SP_EL0 is undefined if it's being used as
5251 * the stack pointer.
5253 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5255 return CP_ACCESS_OK
;
5258 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5260 return env
->pstate
& PSTATE_SP
;
5263 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5265 update_spsel(env
, val
);
5268 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5271 ARMCPU
*cpu
= env_archcpu(env
);
5273 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5274 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5278 /* ??? Lots of these bits are not implemented. */
5280 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5281 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5282 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5284 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5285 SCTLR_ATA0
| SCTLR_ATA
);
5289 if (raw_read(env
, ri
) == value
) {
5291 * Skip the TLB flush if nothing actually changed; Linux likes
5292 * to do a lot of pointless SCTLR writes.
5297 raw_write(env
, ri
, value
);
5299 /* This may enable/disable the MMU, so do a TLB flush. */
5300 tlb_flush(CPU(cpu
));
5302 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5304 * Normally we would always end the TB on an SCTLR write; see the
5305 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5306 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5307 * of hflags from the translator, so do it here.
5309 arm_rebuild_hflags(env
);
5313 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5317 * Some MDCR_EL3 bits affect whether PMU counters are running:
5318 * if we are trying to change any of those then we must
5319 * bracket this update with PMU start/finish calls.
5321 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5326 env
->cp15
.mdcr_el3
= value
;
5332 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5335 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5336 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5339 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5343 * Some MDCR_EL2 bits affect whether PMU counters are running:
5344 * if we are trying to change any of those then we must
5345 * bracket this update with PMU start/finish calls.
5347 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5352 env
->cp15
.mdcr_el2
= value
;
5358 static CPAccessResult
access_nv1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5361 if (arm_current_el(env
) == 1) {
5362 uint64_t hcr_nv
= arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
| HCR_NV2
);
5364 if (hcr_nv
== (HCR_NV
| HCR_NV1
)) {
5365 return CP_ACCESS_TRAP_EL2
;
5368 return CP_ACCESS_OK
;
5371 #ifdef CONFIG_USER_ONLY
5373 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5374 * code to get around W^X restrictions, where one region is writable and the
5375 * other is executable.
5377 * Since the executable region is never written to we cannot detect code
5378 * changes when running in user mode, and rely on the emulated JIT telling us
5379 * that the code has changed by executing this instruction.
5381 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5384 uint64_t icache_line_mask
, start_address
, end_address
;
5387 cpu
= env_archcpu(env
);
5389 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5390 start_address
= value
& ~icache_line_mask
;
5391 end_address
= value
| icache_line_mask
;
5395 tb_invalidate_phys_range(start_address
, end_address
);
5401 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5403 * Minimal set of EL0-visible registers. This will need to be expanded
5404 * significantly for system emulation of AArch64 CPUs.
5406 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5407 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5408 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5409 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5410 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5411 .type
= ARM_CP_NO_RAW
,
5412 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5413 .fieldoffset
= offsetof(CPUARMState
, daif
),
5414 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5415 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5416 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5417 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5418 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5419 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5420 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5421 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5422 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5423 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5424 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5425 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5426 .fgt
= FGT_DCZID_EL0
,
5427 .readfn
= aa64_dczid_read
},
5428 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5429 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5430 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5431 #ifndef CONFIG_USER_ONLY
5432 /* Avoid overhead of an access check that always passes in user-mode */
5433 .accessfn
= aa64_zva_access
,
5437 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5438 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5439 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5441 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5442 * don't emulate caches.
5444 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5445 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5446 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5447 .fgt
= FGT_ICIALLUIS
,
5448 .accessfn
= access_ticab
},
5449 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5450 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5451 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5453 .accessfn
= access_tocu
},
5454 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5455 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5458 .accessfn
= access_tocu
,
5459 #ifdef CONFIG_USER_ONLY
5460 .type
= ARM_CP_NO_RAW
,
5461 .writefn
= ic_ivau_write
5466 /* Cache ops: all NOPs since we don't emulate caches */
5467 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5468 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5469 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5471 .type
= ARM_CP_NOP
},
5472 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5473 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5475 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5476 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5477 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5478 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5480 .accessfn
= aa64_cacheop_poc_access
},
5481 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5482 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5484 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5485 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5486 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5487 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5489 .accessfn
= access_tocu
},
5490 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5491 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5492 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5494 .accessfn
= aa64_cacheop_poc_access
},
5495 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5496 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5498 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5499 /* TLBI operations */
5500 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5501 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5502 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5503 .fgt
= FGT_TLBIVMALLE1IS
,
5504 .writefn
= tlbi_aa64_vmalle1is_write
},
5505 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5506 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5507 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5508 .fgt
= FGT_TLBIVAE1IS
,
5509 .writefn
= tlbi_aa64_vae1is_write
},
5510 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5511 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5512 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5513 .fgt
= FGT_TLBIASIDE1IS
,
5514 .writefn
= tlbi_aa64_vmalle1is_write
},
5515 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5516 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5517 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5518 .fgt
= FGT_TLBIVAAE1IS
,
5519 .writefn
= tlbi_aa64_vae1is_write
},
5520 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5521 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5522 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5523 .fgt
= FGT_TLBIVALE1IS
,
5524 .writefn
= tlbi_aa64_vae1is_write
},
5525 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5526 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5527 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5528 .fgt
= FGT_TLBIVAALE1IS
,
5529 .writefn
= tlbi_aa64_vae1is_write
},
5530 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5531 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5532 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5533 .fgt
= FGT_TLBIVMALLE1
,
5534 .writefn
= tlbi_aa64_vmalle1_write
},
5535 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5536 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5537 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5538 .fgt
= FGT_TLBIVAE1
,
5539 .writefn
= tlbi_aa64_vae1_write
},
5540 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5541 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5542 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5543 .fgt
= FGT_TLBIASIDE1
,
5544 .writefn
= tlbi_aa64_vmalle1_write
},
5545 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5546 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5547 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5548 .fgt
= FGT_TLBIVAAE1
,
5549 .writefn
= tlbi_aa64_vae1_write
},
5550 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5551 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5552 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5553 .fgt
= FGT_TLBIVALE1
,
5554 .writefn
= tlbi_aa64_vae1_write
},
5555 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5556 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5557 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5558 .fgt
= FGT_TLBIVAALE1
,
5559 .writefn
= tlbi_aa64_vae1_write
},
5560 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5561 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5562 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5563 .writefn
= tlbi_aa64_ipas2e1is_write
},
5564 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5565 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5566 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5567 .writefn
= tlbi_aa64_ipas2e1is_write
},
5568 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5569 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5570 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5571 .writefn
= tlbi_aa64_alle1is_write
},
5572 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5573 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5574 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5575 .writefn
= tlbi_aa64_alle1is_write
},
5576 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5578 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5579 .writefn
= tlbi_aa64_ipas2e1_write
},
5580 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5581 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5582 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5583 .writefn
= tlbi_aa64_ipas2e1_write
},
5584 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5585 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5586 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5587 .writefn
= tlbi_aa64_alle1_write
},
5588 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5589 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5590 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5591 .writefn
= tlbi_aa64_alle1is_write
},
5592 #ifndef CONFIG_USER_ONLY
5593 /* 64 bit address translation operations */
5594 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5595 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5596 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5598 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5599 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5600 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5601 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5603 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5604 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5605 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5606 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5608 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5609 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5610 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5611 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5613 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5614 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5615 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5616 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5617 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5618 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5619 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5620 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5621 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5622 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5623 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5624 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5625 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5626 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5627 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5628 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5629 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5630 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5631 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5632 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5633 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5634 .writefn
= ats_write64
},
5635 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5636 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5637 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5638 .writefn
= ats_write64
},
5639 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5640 .type
= ARM_CP_ALIAS
,
5641 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5642 .access
= PL1_RW
, .resetvalue
= 0,
5644 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5645 .writefn
= par_write
},
5647 /* TLB invalidate last level of translation table walk */
5648 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5649 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5650 .writefn
= tlbimva_is_write
},
5651 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5652 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5653 .writefn
= tlbimvaa_is_write
},
5654 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5655 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5656 .writefn
= tlbimva_write
},
5657 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5658 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5659 .writefn
= tlbimvaa_write
},
5660 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5661 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5662 .writefn
= tlbimva_hyp_write
},
5663 { .name
= "TLBIMVALHIS",
5664 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5665 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5666 .writefn
= tlbimva_hyp_is_write
},
5667 { .name
= "TLBIIPAS2",
5668 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5669 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5670 .writefn
= tlbiipas2_hyp_write
},
5671 { .name
= "TLBIIPAS2IS",
5672 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5673 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5674 .writefn
= tlbiipas2is_hyp_write
},
5675 { .name
= "TLBIIPAS2L",
5676 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5677 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5678 .writefn
= tlbiipas2_hyp_write
},
5679 { .name
= "TLBIIPAS2LIS",
5680 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5681 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5682 .writefn
= tlbiipas2is_hyp_write
},
5683 /* 32 bit cache operations */
5684 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5685 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5686 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5687 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5688 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5689 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5690 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5691 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5692 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5693 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5694 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5695 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5696 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5697 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5698 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5699 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5700 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5701 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5702 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5703 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5704 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5705 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5706 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5707 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5708 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5709 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5710 /* MMU Domain access control / MPU write buffer control */
5711 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5712 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5713 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5714 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5715 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5716 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5717 .type
= ARM_CP_ALIAS
,
5718 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5719 .access
= PL1_RW
, .accessfn
= access_nv1
,
5720 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5721 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5722 .type
= ARM_CP_ALIAS
,
5723 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5724 .access
= PL1_RW
, .accessfn
= access_nv1
,
5725 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5727 * We rely on the access checks not allowing the guest to write to the
5728 * state field when SPSel indicates that it's being used as the stack
5731 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5732 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5733 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5734 .type
= ARM_CP_ALIAS
,
5735 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5736 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5737 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5738 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5739 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5740 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5741 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5742 .type
= ARM_CP_NO_RAW
,
5743 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5744 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5745 .type
= ARM_CP_ALIAS
,
5746 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5748 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5749 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5750 .type
= ARM_CP_ALIAS
,
5751 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5753 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5754 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5755 .type
= ARM_CP_ALIAS
,
5756 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5758 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5759 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5760 .type
= ARM_CP_ALIAS
,
5761 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5763 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5764 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5766 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5769 .writefn
= mdcr_el3_write
,
5770 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5771 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5772 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5773 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5774 .writefn
= sdcr_write
,
5775 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5778 /* These are present only when EL1 supports AArch32 */
5779 static const ARMCPRegInfo v8_aa32_el1_reginfo
[] = {
5780 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5781 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5783 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5784 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5785 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5786 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5787 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5788 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5789 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5790 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5791 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5792 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5793 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5796 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5798 ARMCPU
*cpu
= env_archcpu(env
);
5800 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5801 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5803 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5806 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5807 valid_mask
&= ~HCR_HCD
;
5808 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5810 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5811 * However, if we're using the SMC PSCI conduit then QEMU is
5812 * effectively acting like EL3 firmware and so the guest at
5813 * EL2 should retain the ability to prevent EL1 from being
5814 * able to make SMC calls into the ersatz firmware, so in
5815 * that case HCR.TSC should be read/write.
5817 valid_mask
&= ~HCR_TSC
;
5820 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5821 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5822 valid_mask
|= HCR_E2H
;
5824 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5825 valid_mask
|= HCR_TERR
| HCR_TEA
;
5827 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5828 valid_mask
|= HCR_TLOR
;
5830 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5831 valid_mask
|= HCR_API
| HCR_APK
;
5833 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5834 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5836 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5837 valid_mask
|= HCR_ENSCXT
;
5839 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5840 valid_mask
|= HCR_FWB
;
5842 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5843 valid_mask
|= HCR_GPF
;
5845 if (cpu_isar_feature(aa64_nv
, cpu
)) {
5846 valid_mask
|= HCR_NV
| HCR_NV1
| HCR_AT
;
5850 if (cpu_isar_feature(any_evt
, cpu
)) {
5851 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5852 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5853 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5856 /* Clear RES0 bits. */
5857 value
&= valid_mask
;
5860 * These bits change the MMU setup:
5861 * HCR_VM enables stage 2 translation
5862 * HCR_PTW forbids certain page-table setups
5863 * HCR_DC disables stage1 and enables stage2 translation
5864 * HCR_DCT enables tagging on (disabled) stage1 translation
5865 * HCR_FWB changes the interpretation of stage2 descriptor bits
5866 * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
5868 if ((env
->cp15
.hcr_el2
^ value
) &
5869 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
| HCR_NV
| HCR_NV1
)) {
5870 tlb_flush(CPU(cpu
));
5872 env
->cp15
.hcr_el2
= value
;
5875 * Updates to VI and VF require us to update the status of
5876 * virtual interrupts, which are the logical OR of these bits
5877 * and the state of the input lines from the GIC. (This requires
5878 * that we have the BQL, which is done by marking the
5879 * reginfo structs as ARM_CP_IO.)
5880 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5881 * possible for it to be taken immediately, because VIRQ and
5882 * VFIQ are masked unless running at EL0 or EL1, and HCR
5883 * can only be written at EL2.
5885 g_assert(bql_locked());
5886 arm_cpu_update_virq(cpu
);
5887 arm_cpu_update_vfiq(cpu
);
5888 arm_cpu_update_vserr(cpu
);
5891 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5893 do_hcr_write(env
, value
, 0);
5896 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5899 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5900 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5901 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5904 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5907 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5908 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5909 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5913 * Return the effective value of HCR_EL2, at the given security state.
5914 * Bits that are not included here:
5915 * RW (read from SCR_EL3.RW as needed)
5917 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5919 uint64_t ret
= env
->cp15
.hcr_el2
;
5921 assert(space
!= ARMSS_Root
);
5923 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5925 * "This register has no effect if EL2 is not enabled in the
5926 * current Security state". This is ARMv8.4-SecEL2 speak for
5927 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5929 * Prior to that, the language was "In an implementation that
5930 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5931 * as if this field is 0 for all purposes other than a direct
5932 * read or write access of HCR_EL2". With lots of enumeration
5933 * on a per-field basis. In current QEMU, this is condition
5934 * is arm_is_secure_below_el3.
5936 * Since the v8.4 language applies to the entire register, and
5937 * appears to be backward compatible, use that.
5943 * For a cpu that supports both aarch64 and aarch32, we can set bits
5944 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5945 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5947 if (!arm_el_is_aa64(env
, 2)) {
5948 uint64_t aa32_valid
;
5951 * These bits are up-to-date as of ARMv8.6.
5952 * For HCR, it's easiest to list just the 2 bits that are invalid.
5953 * For HCR2, list those that are valid.
5955 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5956 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5957 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5961 if (ret
& HCR_TGE
) {
5962 /* These bits are up-to-date as of ARMv8.6. */
5963 if (ret
& HCR_E2H
) {
5964 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5965 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5966 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5967 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5968 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5969 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5971 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5973 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5974 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5975 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5982 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5984 if (arm_feature(env
, ARM_FEATURE_M
)) {
5987 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
5991 * Corresponds to ARM pseudocode function ELIsInHost().
5993 bool el_is_in_host(CPUARMState
*env
, int el
)
5998 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5999 * Perform the simplest bit tests first, and validate EL2 afterward.
6002 return false; /* EL1 or EL3 */
6006 * Note that hcr_write() checks isar_feature_aa64_vh(),
6007 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
6009 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
6010 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
6014 /* TGE and/or E2H set: double check those bits are currently legal. */
6015 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
6018 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6021 uint64_t valid_mask
= 0;
6023 /* FEAT_MOPS adds MSCEn and MCE2 */
6024 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6025 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
6028 /* Clear RES0 bits. */
6029 env
->cp15
.hcrx_el2
= value
& valid_mask
;
6032 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6035 if (arm_current_el(env
) == 2
6036 && arm_feature(env
, ARM_FEATURE_EL3
)
6037 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6038 return CP_ACCESS_TRAP_EL3
;
6040 return CP_ACCESS_OK
;
6043 static const ARMCPRegInfo hcrx_el2_reginfo
= {
6044 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
6045 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
6046 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
6047 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
6050 /* Return the effective value of HCRX_EL2. */
6051 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
6054 * The bits in this register behave as 0 for all purposes other than
6055 * direct reads of the register if SCR_EL3.HXEn is 0.
6056 * If EL2 is not enabled in the current security state, then the
6057 * bit may behave as if 0, or as if 1, depending on the bit.
6058 * For the moment, we treat the EL2-disabled case as taking
6059 * priority over the HXEn-disabled case. This is true for the only
6060 * bit for a feature which we implement where the answer is different
6061 * for the two cases (MSCEn for FEAT_MOPS).
6062 * This may need to be revisited for future bits.
6064 if (!arm_is_el2_enabled(env
)) {
6066 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6067 /* MSCEn behaves as 1 if EL2 is not enabled */
6072 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6075 return env
->cp15
.hcrx_el2
;
6078 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6082 * For A-profile AArch32 EL3, if NSACR.CP10
6083 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6085 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6086 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6087 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6088 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6090 env
->cp15
.cptr_el
[2] = value
;
6093 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6096 * For A-profile AArch32 EL3, if NSACR.CP10
6097 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6099 uint64_t value
= env
->cp15
.cptr_el
[2];
6101 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6102 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6103 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6108 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6109 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6111 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6112 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6113 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6114 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6115 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6116 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6117 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6118 .writefn
= hcr_writelow
},
6119 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6120 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6121 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6122 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6123 .type
= ARM_CP_ALIAS
,
6124 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6126 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6127 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6128 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6129 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6130 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6131 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6132 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6133 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6134 .type
= ARM_CP_ALIAS
,
6135 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6137 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6138 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6139 .type
= ARM_CP_ALIAS
,
6140 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6142 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6143 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6144 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6145 .access
= PL2_RW
, .writefn
= vbar_write
,
6146 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6148 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6149 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6150 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6151 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6152 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6153 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6154 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6155 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6156 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6157 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6158 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6159 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6161 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6162 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6163 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6164 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6165 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6166 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6167 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6169 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6170 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6171 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6172 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6174 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6175 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6176 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6178 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6179 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6180 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6182 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6183 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6184 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6185 .raw_writefn
= raw_write
,
6186 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6187 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6188 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6189 .type
= ARM_CP_ALIAS
,
6190 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6191 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6192 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6193 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6195 /* no .writefn needed as this can't cause an ASID change */
6196 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6197 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6198 .cp
= 15, .opc1
= 6, .crm
= 2,
6199 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6200 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6201 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6202 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6203 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6204 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6205 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6206 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6207 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6208 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6209 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6210 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6211 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6212 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6213 .access
= PL2_RW
, .resetvalue
= 0,
6214 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6215 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6216 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6217 .access
= PL2_RW
, .resetvalue
= 0,
6218 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6219 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6220 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6221 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6222 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6223 { .name
= "TLBIALLNSNH",
6224 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6225 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6226 .writefn
= tlbiall_nsnh_write
},
6227 { .name
= "TLBIALLNSNHIS",
6228 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6229 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6230 .writefn
= tlbiall_nsnh_is_write
},
6231 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6232 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6233 .writefn
= tlbiall_hyp_write
},
6234 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6235 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6236 .writefn
= tlbiall_hyp_is_write
},
6237 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6238 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6239 .writefn
= tlbimva_hyp_write
},
6240 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6241 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6242 .writefn
= tlbimva_hyp_is_write
},
6243 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6244 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6245 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6246 .writefn
= tlbi_aa64_alle2_write
},
6247 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6248 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6249 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6250 .writefn
= tlbi_aa64_vae2_write
},
6251 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6252 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6253 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6254 .writefn
= tlbi_aa64_vae2_write
},
6255 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6256 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6257 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6258 .writefn
= tlbi_aa64_alle2is_write
},
6259 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6260 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6261 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6262 .writefn
= tlbi_aa64_vae2is_write
},
6263 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6264 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6265 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6266 .writefn
= tlbi_aa64_vae2is_write
},
6267 #ifndef CONFIG_USER_ONLY
6269 * Unlike the other EL2-related AT operations, these must
6270 * UNDEF from EL3 if EL2 is not implemented, which is why we
6271 * define them here rather than with the rest of the AT ops.
6273 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6274 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6275 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6276 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6277 .writefn
= ats_write64
},
6278 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6279 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6280 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6281 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6282 .writefn
= ats_write64
},
6284 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6285 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6286 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6287 * to behave as if SCR.NS was 1.
6289 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6291 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6292 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6294 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6295 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6296 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6298 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6299 * reset values as IMPDEF. We choose to reset to 3 to comply with
6300 * both ARMv7 and ARMv8.
6302 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6303 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6304 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6305 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6306 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6307 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6308 .writefn
= gt_cntvoff_write
,
6309 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6310 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6311 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6312 .writefn
= gt_cntvoff_write
,
6313 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6314 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6315 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6316 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6317 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6318 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6319 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6320 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6321 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6322 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6323 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6324 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6325 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6326 .resetfn
= gt_hyp_timer_reset
,
6327 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6328 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6330 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6332 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6334 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6336 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6337 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6338 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6339 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6340 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6341 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6343 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6344 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6345 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6347 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6350 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6351 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6352 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6353 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6355 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6356 .writefn
= hcr_writehigh
},
6359 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6362 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6363 return CP_ACCESS_OK
;
6365 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6368 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6369 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6370 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6371 .access
= PL2_RW
, .accessfn
= sel2_access
,
6372 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6373 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6374 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6375 .access
= PL2_RW
, .accessfn
= sel2_access
,
6376 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6379 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6383 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6384 * At Secure EL1 it traps to EL3 or EL2.
6386 if (arm_current_el(env
) == 3) {
6387 return CP_ACCESS_OK
;
6389 if (arm_is_secure_below_el3(env
)) {
6390 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6391 return CP_ACCESS_TRAP_EL2
;
6393 return CP_ACCESS_TRAP_EL3
;
6395 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6397 return CP_ACCESS_OK
;
6399 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6402 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6403 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6404 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6405 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6406 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6407 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6408 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6409 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6410 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6411 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6412 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6413 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6414 .access
= PL3_RW
, .resetvalue
= 0,
6415 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6417 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6418 .access
= PL3_RW
, .resetvalue
= 0,
6419 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6420 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6421 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6422 .writefn
= vbar_write
, .resetvalue
= 0,
6423 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6424 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6425 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6426 .access
= PL3_RW
, .resetvalue
= 0,
6427 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6428 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6429 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6431 /* no .writefn needed as this can't cause an ASID change */
6433 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6434 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6435 .type
= ARM_CP_ALIAS
,
6436 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6438 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6439 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6440 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6441 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6442 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6443 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6444 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6445 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6446 .type
= ARM_CP_ALIAS
,
6447 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6449 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6450 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6451 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6452 .access
= PL3_RW
, .writefn
= vbar_write
,
6453 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6455 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6456 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6457 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6458 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6459 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6460 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6461 .access
= PL3_RW
, .resetvalue
= 0,
6462 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6463 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6464 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6465 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6467 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6468 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6469 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6471 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6472 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6473 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6475 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6476 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6477 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6478 .writefn
= tlbi_aa64_alle3is_write
},
6479 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6480 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6481 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6482 .writefn
= tlbi_aa64_vae3is_write
},
6483 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6484 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6485 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6486 .writefn
= tlbi_aa64_vae3is_write
},
6487 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6488 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6489 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6490 .writefn
= tlbi_aa64_alle3_write
},
6491 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6492 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6493 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6494 .writefn
= tlbi_aa64_vae3_write
},
6495 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6496 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6497 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6498 .writefn
= tlbi_aa64_vae3_write
},
6501 #ifndef CONFIG_USER_ONLY
6502 /* Test if system register redirection is to occur in the current state. */
6503 static bool redirect_for_e2h(CPUARMState
*env
)
6505 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6508 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6512 if (redirect_for_e2h(env
)) {
6513 /* Switch to the saved EL2 version of the register. */
6515 readfn
= ri
->readfn
;
6517 readfn
= ri
->orig_readfn
;
6519 if (readfn
== NULL
) {
6522 return readfn(env
, ri
);
6525 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6530 if (redirect_for_e2h(env
)) {
6531 /* Switch to the saved EL2 version of the register. */
6533 writefn
= ri
->writefn
;
6535 writefn
= ri
->orig_writefn
;
6537 if (writefn
== NULL
) {
6538 writefn
= raw_write
;
6540 writefn(env
, ri
, value
);
6543 static uint64_t el2_e2h_e12_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6545 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6546 return ri
->orig_readfn(env
, ri
->opaque
);
6549 static void el2_e2h_e12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6552 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6553 return ri
->orig_writefn(env
, ri
->opaque
, value
);
6556 static CPAccessResult
el2_e2h_e12_access(CPUARMState
*env
,
6557 const ARMCPRegInfo
*ri
,
6560 if (arm_current_el(env
) == 1) {
6562 * This must be a FEAT_NV access (will either trap or redirect
6563 * to memory). None of the registers with _EL12 aliases want to
6564 * apply their trap controls for this kind of access, so don't
6565 * call the orig_accessfn or do the "UNDEF when E2H is 0" check.
6567 return CP_ACCESS_OK
;
6569 /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
6570 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6571 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6573 if (ri
->orig_accessfn
) {
6574 return ri
->orig_accessfn(env
, ri
->opaque
, isread
);
6576 return CP_ACCESS_OK
;
6579 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6582 uint32_t src_key
, dst_key
, new_key
;
6583 const char *src_name
, *dst_name
, *new_name
;
6584 bool (*feature
)(const ARMISARegisters
*id
);
6587 #define K(op0, op1, crn, crm, op2) \
6588 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6590 static const struct E2HAlias aliases
[] = {
6591 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6592 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6593 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6594 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6595 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6596 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6597 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6598 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6599 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6600 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6601 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6602 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6603 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6604 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6605 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6606 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6607 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6608 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6609 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6610 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6611 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6612 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6613 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6614 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6615 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6616 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6617 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6618 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6619 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6620 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6621 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6622 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6625 * Note that redirection of ZCR is mentioned in the description
6626 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6627 * not in the summary table.
6629 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6630 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6631 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6632 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6634 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6635 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6637 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6638 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6639 isar_feature_aa64_scxtnum
},
6641 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6642 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6648 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6649 const struct E2HAlias
*a
= &aliases
[i
];
6650 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6653 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6657 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6658 (gpointer
)(uintptr_t)a
->src_key
);
6659 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6660 (gpointer
)(uintptr_t)a
->dst_key
);
6661 g_assert(src_reg
!= NULL
);
6662 g_assert(dst_reg
!= NULL
);
6664 /* Cross-compare names to detect typos in the keys. */
6665 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6666 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6668 /* None of the core system registers use opaque; we will. */
6669 g_assert(src_reg
->opaque
== NULL
);
6671 /* Create alias before redirection so we dup the right data. */
6672 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6674 new_reg
->name
= a
->new_name
;
6675 new_reg
->type
|= ARM_CP_ALIAS
;
6676 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6677 new_reg
->access
&= PL2_RW
| PL3_RW
;
6678 /* The new_reg op fields are as per new_key, not the target reg */
6679 new_reg
->crn
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRN_MASK
)
6680 >> CP_REG_ARM64_SYSREG_CRN_SHIFT
;
6681 new_reg
->crm
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRM_MASK
)
6682 >> CP_REG_ARM64_SYSREG_CRM_SHIFT
;
6683 new_reg
->opc0
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP0_MASK
)
6684 >> CP_REG_ARM64_SYSREG_OP0_SHIFT
;
6685 new_reg
->opc1
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP1_MASK
)
6686 >> CP_REG_ARM64_SYSREG_OP1_SHIFT
;
6687 new_reg
->opc2
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP2_MASK
)
6688 >> CP_REG_ARM64_SYSREG_OP2_SHIFT
;
6689 new_reg
->opaque
= src_reg
;
6690 new_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6691 new_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6692 new_reg
->orig_accessfn
= src_reg
->accessfn
;
6693 if (!new_reg
->raw_readfn
) {
6694 new_reg
->raw_readfn
= raw_read
;
6696 if (!new_reg
->raw_writefn
) {
6697 new_reg
->raw_writefn
= raw_write
;
6699 new_reg
->readfn
= el2_e2h_e12_read
;
6700 new_reg
->writefn
= el2_e2h_e12_write
;
6701 new_reg
->accessfn
= el2_e2h_e12_access
;
6703 ok
= g_hash_table_insert(cpu
->cp_regs
,
6704 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6707 src_reg
->opaque
= dst_reg
;
6708 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6709 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6710 if (!src_reg
->raw_readfn
) {
6711 src_reg
->raw_readfn
= raw_read
;
6713 if (!src_reg
->raw_writefn
) {
6714 src_reg
->raw_writefn
= raw_write
;
6716 src_reg
->readfn
= el2_e2h_read
;
6717 src_reg
->writefn
= el2_e2h_write
;
6722 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6725 int cur_el
= arm_current_el(env
);
6728 uint64_t hcr
= arm_hcr_el2_eff(env
);
6731 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6732 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6733 return CP_ACCESS_TRAP_EL2
;
6736 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6737 return CP_ACCESS_TRAP
;
6739 if (hcr
& HCR_TID2
) {
6740 return CP_ACCESS_TRAP_EL2
;
6743 } else if (hcr
& HCR_TID2
) {
6744 return CP_ACCESS_TRAP_EL2
;
6748 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6749 return CP_ACCESS_TRAP_EL2
;
6752 return CP_ACCESS_OK
;
6756 * Check for traps to RAS registers, which are controlled
6757 * by HCR_EL2.TERR and SCR_EL3.TERR.
6759 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6762 int el
= arm_current_el(env
);
6764 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6765 return CP_ACCESS_TRAP_EL2
;
6767 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6768 return CP_ACCESS_TRAP_EL3
;
6770 return CP_ACCESS_OK
;
6773 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6775 int el
= arm_current_el(env
);
6777 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6778 return env
->cp15
.vdisr_el2
;
6780 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6781 return 0; /* RAZ/WI */
6783 return env
->cp15
.disr_el1
;
6786 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6788 int el
= arm_current_el(env
);
6790 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6791 env
->cp15
.vdisr_el2
= val
;
6794 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6795 return; /* RAZ/WI */
6797 env
->cp15
.disr_el1
= val
;
6801 * Minimal RAS implementation with no Error Records.
6802 * Which means that all of the Error Record registers:
6810 * ERXPFGCDN_EL1 (RASv1p1)
6811 * ERXPFGCTL_EL1 (RASv1p1)
6812 * ERXPFGF_EL1 (RASv1p1)
6816 * may generate UNDEFINED, which is the effect we get by not
6817 * listing them at all.
6819 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6820 * is higher priority than FGT-to-EL2 so we do not need to list them
6821 * in order to check for an FGT.
6823 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6824 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6825 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6826 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6827 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6828 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6829 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6830 .access
= PL1_R
, .accessfn
= access_terr
,
6831 .fgt
= FGT_ERRIDR_EL1
,
6832 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6833 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6834 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6835 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6836 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6837 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6838 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6842 * Return the exception level to which exceptions should be taken
6843 * via SVEAccessTrap. This excludes the check for whether the exception
6844 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6845 * be found by testing 0 < fp_exception_el < sve_exception_el.
6847 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6848 * pseudocode does *not* separate out the FP trap checks, but has them
6849 * all in one function.
6851 int sve_exception_el(CPUARMState
*env
, int el
)
6853 #ifndef CONFIG_USER_ONLY
6854 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6855 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6867 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6868 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6869 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6870 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6872 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6881 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6887 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6888 if (arm_feature(env
, ARM_FEATURE_EL3
)
6889 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6897 * Return the exception level to which exceptions should be taken for SME.
6898 * C.f. the ARM pseudocode function CheckSMEAccess.
6900 int sme_exception_el(CPUARMState
*env
, int el
)
6902 #ifndef CONFIG_USER_ONLY
6903 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6904 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6916 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6917 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6918 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6919 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6921 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6930 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6936 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6937 if (arm_feature(env
, ARM_FEATURE_EL3
)
6938 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6946 * Given that SVE is enabled, return the vector length for EL.
6948 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6950 ARMCPU
*cpu
= env_archcpu(env
);
6951 uint64_t *cr
= env
->vfp
.zcr_el
;
6952 uint32_t map
= cpu
->sve_vq
.map
;
6953 uint32_t len
= ARM_MAX_VQ
- 1;
6956 cr
= env
->vfp
.smcr_el
;
6957 map
= cpu
->sme_vq
.map
;
6960 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6961 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6963 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6964 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6966 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6967 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6970 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6972 return 31 - clz32(map
);
6975 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6977 return ctz32(cpu
->sme_vq
.map
);
6980 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6982 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6985 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6988 int cur_el
= arm_current_el(env
);
6989 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6992 /* Bits other than [3:0] are RAZ/WI. */
6993 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6994 raw_write(env
, ri
, value
& 0xf);
6997 * Because we arrived here, we know both FP and SVE are enabled;
6998 * otherwise we would have trapped access to the ZCR_ELn register.
7000 new_len
= sve_vqm1_for_el(env
, cur_el
);
7001 if (new_len
< old_len
) {
7002 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7006 static const ARMCPRegInfo zcr_reginfo
[] = {
7007 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
7008 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
7009 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
7010 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
7011 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7012 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
7013 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
7014 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
7015 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
7016 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7017 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
7018 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
7019 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
7020 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
7021 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7024 #ifdef TARGET_AARCH64
7025 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7028 int el
= arm_current_el(env
);
7031 uint64_t sctlr
= arm_sctlr(env
, el
);
7032 if (!(sctlr
& SCTLR_EnTP2
)) {
7033 return CP_ACCESS_TRAP
;
7036 /* TODO: FEAT_FGT */
7038 && arm_feature(env
, ARM_FEATURE_EL3
)
7039 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
7040 return CP_ACCESS_TRAP_EL3
;
7042 return CP_ACCESS_OK
;
7045 static CPAccessResult
access_smprimap(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7048 /* If EL1 this is a FEAT_NV access and CPTR_EL3.ESM doesn't apply */
7049 if (arm_current_el(env
) == 2
7050 && arm_feature(env
, ARM_FEATURE_EL3
)
7051 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7052 return CP_ACCESS_TRAP_EL3
;
7054 return CP_ACCESS_OK
;
7057 static CPAccessResult
access_smpri(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7060 if (arm_current_el(env
) < 3
7061 && arm_feature(env
, ARM_FEATURE_EL3
)
7062 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7063 return CP_ACCESS_TRAP_EL3
;
7065 return CP_ACCESS_OK
;
7069 static void arm_reset_sve_state(CPUARMState
*env
)
7071 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
7072 /* Recall that FFR is stored as pregs[16]. */
7073 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
7074 vfp_set_fpcr(env
, 0x0800009f);
7077 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
7079 uint64_t change
= (env
->svcr
^ new) & mask
;
7084 env
->svcr
^= change
;
7086 if (change
& R_SVCR_SM_MASK
) {
7087 arm_reset_sve_state(env
);
7093 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
7094 * on enable: while disabled, the storage is inaccessible and the
7095 * value does not matter. We're not saving the storage in vmstate
7096 * when disabled either.
7098 if (change
& new & R_SVCR_ZA_MASK
) {
7099 memset(env
->zarray
, 0, sizeof(env
->zarray
));
7102 if (tcg_enabled()) {
7103 arm_rebuild_hflags(env
);
7107 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7110 aarch64_set_svcr(env
, value
, -1);
7113 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7116 int cur_el
= arm_current_el(env
);
7117 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7120 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
7121 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
7122 raw_write(env
, ri
, value
);
7125 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7126 * when SVL is widened (old values kept, or zeros). Choose to keep the
7127 * current values for simplicity. But for QEMU internals, we must still
7128 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7129 * above aarch64_sve_narrow_vq.
7131 new_len
= sve_vqm1_for_el(env
, cur_el
);
7132 if (new_len
< old_len
) {
7133 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7137 static const ARMCPRegInfo sme_reginfo
[] = {
7138 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7139 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7140 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7141 .fgt
= FGT_NTPIDR2_EL0
,
7142 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7143 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7144 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7145 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7146 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7147 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7148 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7149 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7150 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7151 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7152 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7153 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7154 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7155 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7156 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7157 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7158 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7159 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7160 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7161 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7162 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7163 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7164 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7165 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7167 * IMPLEMENTOR = 0 (software)
7168 * REVISION = 0 (implementation defined)
7169 * SMPS = 0 (no streaming execution priority in QEMU)
7170 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7172 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7174 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7176 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7177 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7178 .access
= PL1_RW
, .accessfn
= access_smpri
,
7179 .fgt
= FGT_NSMPRI_EL1
,
7180 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7181 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7182 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7183 .access
= PL2_RW
, .accessfn
= access_smprimap
,
7184 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7187 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7190 CPUState
*cs
= env_cpu(env
);
7195 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7198 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7199 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7200 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7201 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7203 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7206 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7208 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7209 env_archcpu(env
)->reset_l0gptsz
);
7212 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7215 CPUState
*cs
= env_cpu(env
);
7217 tlb_flush_all_cpus_synced(cs
);
7220 static const ARMCPRegInfo rme_reginfo
[] = {
7221 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7222 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7223 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7224 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7225 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7226 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7227 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7228 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7229 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7230 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7231 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7232 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7233 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7234 .writefn
= tlbi_aa64_paall_write
},
7235 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7236 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7237 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7238 .writefn
= tlbi_aa64_paallos_write
},
7240 * QEMU does not have a way to invalidate by physical address, thus
7241 * invalidating a range of physical addresses is accomplished by
7242 * flushing all tlb entries in the outer shareable domain,
7243 * just like PAALLOS.
7245 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7246 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7247 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7248 .writefn
= tlbi_aa64_paallos_write
},
7249 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7250 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7251 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7252 .writefn
= tlbi_aa64_paallos_write
},
7253 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7254 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7255 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7258 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7259 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7260 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7261 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7263 #endif /* TARGET_AARCH64 */
7265 static void define_pmu_regs(ARMCPU
*cpu
)
7268 * v7 performance monitor control register: same implementor
7269 * field as main ID register, and we implement four counters in
7270 * addition to the cycle count register.
7272 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7273 ARMCPRegInfo pmcr
= {
7274 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7276 .fgt
= FGT_PMCR_EL0
,
7277 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7278 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7279 .accessfn
= pmreg_access
,
7280 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7281 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7283 ARMCPRegInfo pmcr64
= {
7284 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7285 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7286 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7287 .fgt
= FGT_PMCR_EL0
,
7289 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7290 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7291 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7292 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7295 define_one_arm_cp_reg(cpu
, &pmcr
);
7296 define_one_arm_cp_reg(cpu
, &pmcr64
);
7297 for (i
= 0; i
< pmcrn
; i
++) {
7298 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7299 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7300 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7301 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7302 ARMCPRegInfo pmev_regs
[] = {
7303 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7304 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7305 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7306 .fgt
= FGT_PMEVCNTRN_EL0
,
7307 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7308 .accessfn
= pmreg_access_xevcntr
},
7309 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7310 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7311 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7313 .fgt
= FGT_PMEVCNTRN_EL0
,
7314 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7315 .raw_readfn
= pmevcntr_rawread
,
7316 .raw_writefn
= pmevcntr_rawwrite
},
7317 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7318 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7319 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7320 .fgt
= FGT_PMEVTYPERN_EL0
,
7321 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7322 .accessfn
= pmreg_access
},
7323 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7324 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7325 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7326 .fgt
= FGT_PMEVTYPERN_EL0
,
7328 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7329 .raw_writefn
= pmevtyper_rawwrite
},
7331 define_arm_cp_regs(cpu
, pmev_regs
);
7332 g_free(pmevcntr_name
);
7333 g_free(pmevcntr_el0_name
);
7334 g_free(pmevtyper_name
);
7335 g_free(pmevtyper_el0_name
);
7337 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7338 ARMCPRegInfo v81_pmu_regs
[] = {
7339 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7340 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7341 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7342 .fgt
= FGT_PMCEIDN_EL0
,
7343 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7344 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7345 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7346 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7347 .fgt
= FGT_PMCEIDN_EL0
,
7348 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7350 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7352 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7353 static const ARMCPRegInfo v84_pmmir
= {
7354 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7355 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7356 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7357 .fgt
= FGT_PMMIR_EL1
,
7360 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7364 #ifndef CONFIG_USER_ONLY
7366 * We don't know until after realize whether there's a GICv3
7367 * attached, and that is what registers the gicv3 sysregs.
7368 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7371 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7373 ARMCPU
*cpu
= env_archcpu(env
);
7374 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7376 if (env
->gicv3state
) {
7382 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7384 ARMCPU
*cpu
= env_archcpu(env
);
7385 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7387 if (env
->gicv3state
) {
7395 * Shared logic between LORID and the rest of the LOR* registers.
7396 * Secure state exclusion has already been dealt with.
7398 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7399 const ARMCPRegInfo
*ri
, bool isread
)
7401 int el
= arm_current_el(env
);
7403 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7404 return CP_ACCESS_TRAP_EL2
;
7406 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7407 return CP_ACCESS_TRAP_EL3
;
7409 return CP_ACCESS_OK
;
7412 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7413 const ARMCPRegInfo
*ri
, bool isread
)
7415 if (arm_is_secure_below_el3(env
)) {
7416 /* Access denied in secure mode. */
7417 return CP_ACCESS_TRAP
;
7419 return access_lor_ns(env
, ri
, isread
);
7423 * A trivial implementation of ARMv8.1-LOR leaves all of these
7424 * registers fixed at 0, which indicates that there are zero
7425 * supported Limited Ordering regions.
7427 static const ARMCPRegInfo lor_reginfo
[] = {
7428 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7429 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7430 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7431 .fgt
= FGT_LORSA_EL1
,
7432 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7433 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7434 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7435 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7436 .fgt
= FGT_LOREA_EL1
,
7437 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7438 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7439 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7440 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7441 .fgt
= FGT_LORN_EL1
,
7442 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7443 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7444 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7445 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7446 .fgt
= FGT_LORC_EL1
,
7447 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7448 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7449 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7450 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7451 .fgt
= FGT_LORID_EL1
,
7452 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7455 #ifdef TARGET_AARCH64
7456 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7459 int el
= arm_current_el(env
);
7462 arm_is_el2_enabled(env
) &&
7463 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7464 return CP_ACCESS_TRAP_EL2
;
7467 arm_feature(env
, ARM_FEATURE_EL3
) &&
7468 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7469 return CP_ACCESS_TRAP_EL3
;
7471 return CP_ACCESS_OK
;
7474 static const ARMCPRegInfo pauth_reginfo
[] = {
7475 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7476 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7477 .access
= PL1_RW
, .accessfn
= access_pauth
,
7479 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7480 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7481 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7482 .access
= PL1_RW
, .accessfn
= access_pauth
,
7484 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7485 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7486 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7487 .access
= PL1_RW
, .accessfn
= access_pauth
,
7489 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7490 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7491 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7492 .access
= PL1_RW
, .accessfn
= access_pauth
,
7494 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7495 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7496 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7497 .access
= PL1_RW
, .accessfn
= access_pauth
,
7499 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7500 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7501 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7502 .access
= PL1_RW
, .accessfn
= access_pauth
,
7504 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7505 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7506 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7507 .access
= PL1_RW
, .accessfn
= access_pauth
,
7509 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7510 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7511 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7512 .access
= PL1_RW
, .accessfn
= access_pauth
,
7514 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7515 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7516 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7517 .access
= PL1_RW
, .accessfn
= access_pauth
,
7519 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7520 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7521 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7522 .access
= PL1_RW
, .accessfn
= access_pauth
,
7524 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7527 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7528 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7529 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7530 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7531 .fgt
= FGT_TLBIRVAE1IS
,
7532 .writefn
= tlbi_aa64_rvae1is_write
},
7533 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7534 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7535 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7536 .fgt
= FGT_TLBIRVAAE1IS
,
7537 .writefn
= tlbi_aa64_rvae1is_write
},
7538 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7539 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7540 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7541 .fgt
= FGT_TLBIRVALE1IS
,
7542 .writefn
= tlbi_aa64_rvae1is_write
},
7543 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7544 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7545 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7546 .fgt
= FGT_TLBIRVAALE1IS
,
7547 .writefn
= tlbi_aa64_rvae1is_write
},
7548 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7549 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7550 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7551 .fgt
= FGT_TLBIRVAE1OS
,
7552 .writefn
= tlbi_aa64_rvae1is_write
},
7553 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7554 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7555 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7556 .fgt
= FGT_TLBIRVAAE1OS
,
7557 .writefn
= tlbi_aa64_rvae1is_write
},
7558 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7559 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7560 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7561 .fgt
= FGT_TLBIRVALE1OS
,
7562 .writefn
= tlbi_aa64_rvae1is_write
},
7563 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7564 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7565 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7566 .fgt
= FGT_TLBIRVAALE1OS
,
7567 .writefn
= tlbi_aa64_rvae1is_write
},
7568 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7569 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7570 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7571 .fgt
= FGT_TLBIRVAE1
,
7572 .writefn
= tlbi_aa64_rvae1_write
},
7573 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7574 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7575 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7576 .fgt
= FGT_TLBIRVAAE1
,
7577 .writefn
= tlbi_aa64_rvae1_write
},
7578 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7579 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7580 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7581 .fgt
= FGT_TLBIRVALE1
,
7582 .writefn
= tlbi_aa64_rvae1_write
},
7583 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7584 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7585 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7586 .fgt
= FGT_TLBIRVAALE1
,
7587 .writefn
= tlbi_aa64_rvae1_write
},
7588 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7589 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7590 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7591 .writefn
= tlbi_aa64_ripas2e1is_write
},
7592 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7593 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7594 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7595 .writefn
= tlbi_aa64_ripas2e1is_write
},
7596 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7597 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7598 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7599 .writefn
= tlbi_aa64_rvae2is_write
},
7600 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7601 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7602 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7603 .writefn
= tlbi_aa64_rvae2is_write
},
7604 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7605 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7606 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7607 .writefn
= tlbi_aa64_ripas2e1_write
},
7608 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7609 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7610 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7611 .writefn
= tlbi_aa64_ripas2e1_write
},
7612 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7613 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7614 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7615 .writefn
= tlbi_aa64_rvae2is_write
},
7616 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7617 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7618 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7619 .writefn
= tlbi_aa64_rvae2is_write
},
7620 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7621 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7622 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7623 .writefn
= tlbi_aa64_rvae2_write
},
7624 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7625 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7626 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7627 .writefn
= tlbi_aa64_rvae2_write
},
7628 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7629 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7630 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7631 .writefn
= tlbi_aa64_rvae3is_write
},
7632 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7633 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7634 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7635 .writefn
= tlbi_aa64_rvae3is_write
},
7636 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7637 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7638 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7639 .writefn
= tlbi_aa64_rvae3is_write
},
7640 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7641 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7642 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7643 .writefn
= tlbi_aa64_rvae3is_write
},
7644 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7645 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7646 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7647 .writefn
= tlbi_aa64_rvae3_write
},
7648 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7649 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7650 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7651 .writefn
= tlbi_aa64_rvae3_write
},
7654 static const ARMCPRegInfo tlbios_reginfo
[] = {
7655 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7656 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7657 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7658 .fgt
= FGT_TLBIVMALLE1OS
,
7659 .writefn
= tlbi_aa64_vmalle1is_write
},
7660 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7661 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7662 .fgt
= FGT_TLBIVAE1OS
,
7663 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7664 .writefn
= tlbi_aa64_vae1is_write
},
7665 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7666 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7667 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7668 .fgt
= FGT_TLBIASIDE1OS
,
7669 .writefn
= tlbi_aa64_vmalle1is_write
},
7670 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7671 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7672 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7673 .fgt
= FGT_TLBIVAAE1OS
,
7674 .writefn
= tlbi_aa64_vae1is_write
},
7675 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7676 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7677 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7678 .fgt
= FGT_TLBIVALE1OS
,
7679 .writefn
= tlbi_aa64_vae1is_write
},
7680 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7681 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7682 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7683 .fgt
= FGT_TLBIVAALE1OS
,
7684 .writefn
= tlbi_aa64_vae1is_write
},
7685 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7686 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7687 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7688 .writefn
= tlbi_aa64_alle2is_write
},
7689 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7690 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7691 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7692 .writefn
= tlbi_aa64_vae2is_write
},
7693 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7694 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7695 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7696 .writefn
= tlbi_aa64_alle1is_write
},
7697 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7698 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7699 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7700 .writefn
= tlbi_aa64_vae2is_write
},
7701 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7702 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7703 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7704 .writefn
= tlbi_aa64_alle1is_write
},
7705 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7706 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7707 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7708 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7709 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7710 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7711 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7712 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7713 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7714 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7715 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7716 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7717 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7718 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7719 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7720 .writefn
= tlbi_aa64_alle3is_write
},
7721 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7722 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7723 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7724 .writefn
= tlbi_aa64_vae3is_write
},
7725 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7726 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7727 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7728 .writefn
= tlbi_aa64_vae3is_write
},
7731 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7736 /* Success sets NZCV = 0000. */
7737 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7739 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7741 * ??? Failed, for unknown reasons in the crypto subsystem.
7742 * The best we can do is log the reason and return the
7743 * timed-out indication to the guest. There is no reason
7744 * we know to expect this failure to be transitory, so the
7745 * guest may well hang retrying the operation.
7747 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7748 ri
->name
, error_get_pretty(err
));
7751 env
->ZF
= 0; /* NZCF = 0100 */
7757 /* We do not support re-seeding, so the two registers operate the same. */
7758 static const ARMCPRegInfo rndr_reginfo
[] = {
7759 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7760 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7761 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7762 .access
= PL0_R
, .readfn
= rndr_readfn
},
7763 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7764 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7765 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7766 .access
= PL0_R
, .readfn
= rndr_readfn
},
7769 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7773 ARMCPU
*cpu
= env_archcpu(env
);
7774 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7775 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7776 uint64_t vaddr_in
= (uint64_t) value
;
7777 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7779 int mem_idx
= cpu_mmu_index(env
, false);
7781 /* This won't be crossing page boundaries */
7782 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7784 #ifndef CONFIG_USER_ONLY
7789 /* RCU lock is already being held */
7790 mr
= memory_region_from_host(haddr
, &offset
);
7793 memory_region_writeback(mr
, offset
, dline_size
);
7795 #endif /*CONFIG_USER_ONLY*/
7798 /* Handled by hardware accelerator. */
7799 g_assert_not_reached();
7800 #endif /* CONFIG_TCG */
7803 static const ARMCPRegInfo dcpop_reg
[] = {
7804 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7805 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7806 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7808 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7811 static const ARMCPRegInfo dcpodp_reg
[] = {
7812 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7813 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7814 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7816 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7819 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7822 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7823 return CP_ACCESS_TRAP_EL2
;
7826 return CP_ACCESS_OK
;
7829 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7832 int el
= arm_current_el(env
);
7833 if (el
< 2 && arm_is_el2_enabled(env
)) {
7834 uint64_t hcr
= arm_hcr_el2_eff(env
);
7835 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7836 return CP_ACCESS_TRAP_EL2
;
7840 arm_feature(env
, ARM_FEATURE_EL3
) &&
7841 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7842 return CP_ACCESS_TRAP_EL3
;
7844 return CP_ACCESS_OK
;
7847 static CPAccessResult
access_tfsr_el1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7850 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
7852 if (nv1
!= CP_ACCESS_OK
) {
7855 return access_mte(env
, ri
, isread
);
7858 static CPAccessResult
access_tfsr_el2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7862 * TFSR_EL2: similar to generic access_mte(), but we need to
7863 * account for FEAT_NV. At EL1 this must be a FEAT_NV access;
7864 * we will trap to EL2 and the HCR/SCR traps do not apply.
7866 int el
= arm_current_el(env
);
7869 return CP_ACCESS_OK
;
7871 if (el
< 2 && arm_is_el2_enabled(env
)) {
7872 uint64_t hcr
= arm_hcr_el2_eff(env
);
7873 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7874 return CP_ACCESS_TRAP_EL2
;
7878 arm_feature(env
, ARM_FEATURE_EL3
) &&
7879 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7880 return CP_ACCESS_TRAP_EL3
;
7882 return CP_ACCESS_OK
;
7885 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7887 return env
->pstate
& PSTATE_TCO
;
7890 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7892 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7895 static const ARMCPRegInfo mte_reginfo
[] = {
7896 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7897 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7898 .access
= PL1_RW
, .accessfn
= access_mte
,
7899 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7900 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7901 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7902 .access
= PL1_RW
, .accessfn
= access_tfsr_el1
,
7903 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7904 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7905 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7906 .access
= PL2_RW
, .accessfn
= access_tfsr_el2
,
7907 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7908 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7909 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7911 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7912 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7913 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7914 .access
= PL1_RW
, .accessfn
= access_mte
,
7915 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7916 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7917 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7918 .access
= PL1_RW
, .accessfn
= access_mte
,
7919 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7920 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7921 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7922 .type
= ARM_CP_NO_RAW
,
7923 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7924 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7925 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7926 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7928 .accessfn
= aa64_cacheop_poc_access
},
7929 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7930 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7932 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7933 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7934 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7935 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7937 .accessfn
= aa64_cacheop_poc_access
},
7938 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7939 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7941 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7942 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7943 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7945 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7946 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7947 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7949 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7950 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7951 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7953 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7954 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7955 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7957 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7960 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7961 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7962 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7963 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7966 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7967 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7968 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7969 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7971 .accessfn
= aa64_cacheop_poc_access
},
7972 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7973 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7974 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7976 .accessfn
= aa64_cacheop_poc_access
},
7977 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7978 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7979 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7981 .accessfn
= aa64_cacheop_poc_access
},
7982 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7983 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7984 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7986 .accessfn
= aa64_cacheop_poc_access
},
7987 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7988 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7989 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7991 .accessfn
= aa64_cacheop_poc_access
},
7992 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7993 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7994 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7996 .accessfn
= aa64_cacheop_poc_access
},
7997 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7998 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7999 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8001 .accessfn
= aa64_cacheop_poc_access
},
8002 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
8003 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
8004 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8006 .accessfn
= aa64_cacheop_poc_access
},
8007 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
8008 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
8009 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
8010 #ifndef CONFIG_USER_ONLY
8011 /* Avoid overhead of an access check that always passes in user-mode */
8012 .accessfn
= aa64_zva_access
,
8016 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
8017 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
8018 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
8019 #ifndef CONFIG_USER_ONLY
8020 /* Avoid overhead of an access check that always passes in user-mode */
8021 .accessfn
= aa64_zva_access
,
8027 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8030 uint64_t hcr
= arm_hcr_el2_eff(env
);
8031 int el
= arm_current_el(env
);
8033 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
8034 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
8035 if (hcr
& HCR_TGE
) {
8036 return CP_ACCESS_TRAP_EL2
;
8038 return CP_ACCESS_TRAP
;
8040 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
8041 return CP_ACCESS_TRAP_EL2
;
8043 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
8044 return CP_ACCESS_TRAP_EL2
;
8047 && arm_feature(env
, ARM_FEATURE_EL3
)
8048 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
8049 return CP_ACCESS_TRAP_EL3
;
8051 return CP_ACCESS_OK
;
8054 static CPAccessResult
access_scxtnum_el1(CPUARMState
*env
,
8055 const ARMCPRegInfo
*ri
,
8058 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
8060 if (nv1
!= CP_ACCESS_OK
) {
8063 return access_scxtnum(env
, ri
, isread
);
8066 static const ARMCPRegInfo scxtnum_reginfo
[] = {
8067 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
8068 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
8069 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
8070 .fgt
= FGT_SCXTNUM_EL0
,
8071 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
8072 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
8073 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
8074 .access
= PL1_RW
, .accessfn
= access_scxtnum_el1
,
8075 .fgt
= FGT_SCXTNUM_EL1
,
8076 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
8077 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
8078 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
8079 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
8080 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
8081 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
8082 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
8084 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
8087 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8090 if (arm_current_el(env
) == 2 &&
8091 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
8092 return CP_ACCESS_TRAP_EL3
;
8094 return CP_ACCESS_OK
;
8097 static const ARMCPRegInfo fgt_reginfo
[] = {
8098 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8099 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
8100 .access
= PL2_RW
, .accessfn
= access_fgt
,
8101 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
8102 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8103 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
8104 .access
= PL2_RW
, .accessfn
= access_fgt
,
8105 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
8106 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8107 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
8108 .access
= PL2_RW
, .accessfn
= access_fgt
,
8109 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
8110 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8111 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
8112 .access
= PL2_RW
, .accessfn
= access_fgt
,
8113 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
8114 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
8115 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
8116 .access
= PL2_RW
, .accessfn
= access_fgt
,
8117 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
8119 #endif /* TARGET_AARCH64 */
8121 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8124 int el
= arm_current_el(env
);
8127 uint64_t sctlr
= arm_sctlr(env
, el
);
8128 if (!(sctlr
& SCTLR_EnRCTX
)) {
8129 return CP_ACCESS_TRAP
;
8131 } else if (el
== 1) {
8132 uint64_t hcr
= arm_hcr_el2_eff(env
);
8134 return CP_ACCESS_TRAP_EL2
;
8137 return CP_ACCESS_OK
;
8140 static const ARMCPRegInfo predinv_reginfo
[] = {
8141 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
8142 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
8144 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8145 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
8146 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
8148 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8149 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
8150 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
8152 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8154 * Note the AArch32 opcodes have a different OPC1.
8156 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
8157 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
8159 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8160 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
8161 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
8163 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8164 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
8165 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
8167 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8170 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8172 /* Read the high 32 bits of the current CCSIDR */
8173 return extract64(ccsidr_read(env
, ri
), 32, 32);
8176 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
8177 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
8178 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
8180 .accessfn
= access_tid4
,
8181 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8184 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8187 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8188 return CP_ACCESS_TRAP_EL2
;
8191 return CP_ACCESS_OK
;
8194 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8197 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8198 return access_aa64_tid3(env
, ri
, isread
);
8201 return CP_ACCESS_OK
;
8204 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8207 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8208 return CP_ACCESS_TRAP_EL2
;
8211 return CP_ACCESS_OK
;
8214 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8215 const ARMCPRegInfo
*ri
, bool isread
)
8218 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8219 * in v7A, not in v8A.
8221 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8222 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8223 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8224 return CP_ACCESS_TRAP_EL2
;
8226 return CP_ACCESS_OK
;
8229 static const ARMCPRegInfo jazelle_regs
[] = {
8231 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8232 .access
= PL1_R
, .accessfn
= access_jazelle
,
8233 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8235 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8236 .accessfn
= access_joscr_jmcr
,
8237 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8239 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8240 .accessfn
= access_joscr_jmcr
,
8241 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8244 static const ARMCPRegInfo contextidr_el2
= {
8245 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8246 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8248 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8251 static const ARMCPRegInfo vhe_reginfo
[] = {
8252 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8253 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8254 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8255 .raw_writefn
= raw_write
,
8256 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8257 #ifndef CONFIG_USER_ONLY
8258 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8259 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8261 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8262 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8263 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8264 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8265 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8266 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8267 .resetfn
= gt_hv_timer_reset
,
8268 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8269 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8271 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8273 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8274 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8275 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8276 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8277 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8278 .access
= PL2_RW
, .accessfn
= e2h_access
,
8279 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8280 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8281 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8282 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8283 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8284 .access
= PL2_RW
, .accessfn
= e2h_access
,
8285 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8286 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8287 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8288 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8289 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8290 .access
= PL2_RW
, .accessfn
= e2h_access
,
8291 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8292 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8293 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8294 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8295 .access
= PL2_RW
, .accessfn
= e2h_access
,
8296 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8297 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8298 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8299 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8300 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8301 .access
= PL2_RW
, .accessfn
= e2h_access
,
8302 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8303 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8304 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8305 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8306 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8307 .access
= PL2_RW
, .accessfn
= e2h_access
,
8308 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8312 #ifndef CONFIG_USER_ONLY
8313 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8314 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8315 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8316 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8317 .fgt
= FGT_ATS1E1RP
,
8318 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8319 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8320 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8321 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8322 .fgt
= FGT_ATS1E1WP
,
8323 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8326 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8327 { .name
= "ATS1CPRP",
8328 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8329 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8330 .writefn
= ats_write
},
8331 { .name
= "ATS1CPWP",
8332 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8333 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8334 .writefn
= ats_write
},
8339 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8340 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8341 * is non-zero, which is never for ARMv7, optionally in ARMv8
8342 * and mandatorily for ARMv8.2 and up.
8343 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8344 * implementation is RAZ/WI we can ignore this detail, as we
8347 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8348 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8349 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8350 .access
= PL1_RW
, .accessfn
= access_tacr
,
8351 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8352 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8353 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8354 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8358 void register_cp_regs_for_features(ARMCPU
*cpu
)
8360 /* Register all the coprocessor registers based on feature bits */
8361 CPUARMState
*env
= &cpu
->env
;
8362 if (arm_feature(env
, ARM_FEATURE_M
)) {
8363 /* M profile has no coprocessor registers */
8367 define_arm_cp_regs(cpu
, cp_reginfo
);
8368 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8370 * Must go early as it is full of wildcards that may be
8371 * overridden by later definitions.
8373 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8376 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8377 /* The ID registers all have impdef reset values */
8378 ARMCPRegInfo v6_idregs
[] = {
8379 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8380 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8381 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8382 .accessfn
= access_aa32_tid3
,
8383 .resetvalue
= cpu
->isar
.id_pfr0
},
8385 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8386 * the value of the GIC field until after we define these regs.
8388 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8389 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8390 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8391 .accessfn
= access_aa32_tid3
,
8392 #ifdef CONFIG_USER_ONLY
8393 .type
= ARM_CP_CONST
,
8394 .resetvalue
= cpu
->isar
.id_pfr1
,
8396 .type
= ARM_CP_NO_RAW
,
8397 .accessfn
= access_aa32_tid3
,
8398 .readfn
= id_pfr1_read
,
8399 .writefn
= arm_cp_write_ignore
8402 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8403 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8404 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8405 .accessfn
= access_aa32_tid3
,
8406 .resetvalue
= cpu
->isar
.id_dfr0
},
8407 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8408 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8409 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8410 .accessfn
= access_aa32_tid3
,
8411 .resetvalue
= cpu
->id_afr0
},
8412 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8413 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8414 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8415 .accessfn
= access_aa32_tid3
,
8416 .resetvalue
= cpu
->isar
.id_mmfr0
},
8417 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8418 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8419 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8420 .accessfn
= access_aa32_tid3
,
8421 .resetvalue
= cpu
->isar
.id_mmfr1
},
8422 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8423 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8424 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8425 .accessfn
= access_aa32_tid3
,
8426 .resetvalue
= cpu
->isar
.id_mmfr2
},
8427 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8428 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8429 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8430 .accessfn
= access_aa32_tid3
,
8431 .resetvalue
= cpu
->isar
.id_mmfr3
},
8432 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8433 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8434 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8435 .accessfn
= access_aa32_tid3
,
8436 .resetvalue
= cpu
->isar
.id_isar0
},
8437 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8438 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8439 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8440 .accessfn
= access_aa32_tid3
,
8441 .resetvalue
= cpu
->isar
.id_isar1
},
8442 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8443 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8444 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8445 .accessfn
= access_aa32_tid3
,
8446 .resetvalue
= cpu
->isar
.id_isar2
},
8447 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8448 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8449 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8450 .accessfn
= access_aa32_tid3
,
8451 .resetvalue
= cpu
->isar
.id_isar3
},
8452 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8453 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8454 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8455 .accessfn
= access_aa32_tid3
,
8456 .resetvalue
= cpu
->isar
.id_isar4
},
8457 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8458 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8459 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8460 .accessfn
= access_aa32_tid3
,
8461 .resetvalue
= cpu
->isar
.id_isar5
},
8462 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8463 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8464 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8465 .accessfn
= access_aa32_tid3
,
8466 .resetvalue
= cpu
->isar
.id_mmfr4
},
8467 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8468 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8469 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8470 .accessfn
= access_aa32_tid3
,
8471 .resetvalue
= cpu
->isar
.id_isar6
},
8473 define_arm_cp_regs(cpu
, v6_idregs
);
8474 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8476 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8478 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8479 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8481 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8482 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8483 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8485 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8486 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8488 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8489 ARMCPRegInfo clidr
= {
8490 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8491 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8492 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8493 .accessfn
= access_tid4
,
8494 .fgt
= FGT_CLIDR_EL1
,
8495 .resetvalue
= cpu
->clidr
8497 define_one_arm_cp_reg(cpu
, &clidr
);
8498 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8499 define_debug_regs(cpu
);
8500 define_pmu_regs(cpu
);
8502 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8504 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8506 * v8 ID registers, which all have impdef reset values.
8507 * Note that within the ID register ranges the unused slots
8508 * must all RAZ, not UNDEF; future architecture versions may
8509 * define new registers here.
8510 * ID registers which are AArch64 views of the AArch32 ID registers
8511 * which already existed in v6 and v7 are handled elsewhere,
8515 ARMCPRegInfo v8_idregs
[] = {
8517 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8518 * emulation because we don't know the right value for the
8519 * GIC field until after we define these regs.
8521 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8522 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8524 #ifdef CONFIG_USER_ONLY
8525 .type
= ARM_CP_CONST
,
8526 .resetvalue
= cpu
->isar
.id_aa64pfr0
8528 .type
= ARM_CP_NO_RAW
,
8529 .accessfn
= access_aa64_tid3
,
8530 .readfn
= id_aa64pfr0_read
,
8531 .writefn
= arm_cp_write_ignore
8534 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8535 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8536 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8537 .accessfn
= access_aa64_tid3
,
8538 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8539 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8540 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8541 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8542 .accessfn
= access_aa64_tid3
,
8544 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8545 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8546 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8547 .accessfn
= access_aa64_tid3
,
8549 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8550 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8551 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8552 .accessfn
= access_aa64_tid3
,
8553 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8554 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8555 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8556 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8557 .accessfn
= access_aa64_tid3
,
8558 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8559 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8560 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8561 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8562 .accessfn
= access_aa64_tid3
,
8564 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8565 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8566 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8567 .accessfn
= access_aa64_tid3
,
8569 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8570 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8571 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8572 .accessfn
= access_aa64_tid3
,
8573 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8574 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8575 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8576 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8577 .accessfn
= access_aa64_tid3
,
8578 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8579 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8580 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8581 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8582 .accessfn
= access_aa64_tid3
,
8584 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8585 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8586 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8587 .accessfn
= access_aa64_tid3
,
8589 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8590 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8591 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8592 .accessfn
= access_aa64_tid3
,
8593 .resetvalue
= cpu
->id_aa64afr0
},
8594 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8595 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8596 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8597 .accessfn
= access_aa64_tid3
,
8598 .resetvalue
= cpu
->id_aa64afr1
},
8599 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8600 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8601 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8602 .accessfn
= access_aa64_tid3
,
8604 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8605 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8606 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8607 .accessfn
= access_aa64_tid3
,
8609 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8610 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8611 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8612 .accessfn
= access_aa64_tid3
,
8613 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8614 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8615 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8616 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8617 .accessfn
= access_aa64_tid3
,
8618 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8619 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8620 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8621 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8622 .accessfn
= access_aa64_tid3
,
8623 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8624 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8625 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8626 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8627 .accessfn
= access_aa64_tid3
,
8629 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8630 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8631 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8632 .accessfn
= access_aa64_tid3
,
8634 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8635 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8636 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8637 .accessfn
= access_aa64_tid3
,
8639 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8640 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8641 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8642 .accessfn
= access_aa64_tid3
,
8644 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8645 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8646 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8647 .accessfn
= access_aa64_tid3
,
8649 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8650 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8651 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8652 .accessfn
= access_aa64_tid3
,
8653 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8654 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8655 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8656 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8657 .accessfn
= access_aa64_tid3
,
8658 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8659 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8660 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8661 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8662 .accessfn
= access_aa64_tid3
,
8663 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8664 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8665 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8666 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8667 .accessfn
= access_aa64_tid3
,
8669 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8670 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8671 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8672 .accessfn
= access_aa64_tid3
,
8674 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8675 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8676 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8677 .accessfn
= access_aa64_tid3
,
8679 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8680 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8681 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8682 .accessfn
= access_aa64_tid3
,
8684 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8685 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8686 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8687 .accessfn
= access_aa64_tid3
,
8689 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8690 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8691 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8692 .accessfn
= access_aa64_tid3
,
8693 .resetvalue
= cpu
->isar
.mvfr0
},
8694 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8695 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8696 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8697 .accessfn
= access_aa64_tid3
,
8698 .resetvalue
= cpu
->isar
.mvfr1
},
8699 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8700 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8701 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8702 .accessfn
= access_aa64_tid3
,
8703 .resetvalue
= cpu
->isar
.mvfr2
},
8705 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8706 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8707 * as RAZ, since it is in the "reserved for future ID
8708 * registers, RAZ" part of the AArch32 encoding space.
8710 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8711 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8712 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8713 .accessfn
= access_aa64_tid3
,
8715 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8716 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8717 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8718 .accessfn
= access_aa64_tid3
,
8720 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8721 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8722 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8723 .accessfn
= access_aa64_tid3
,
8726 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8727 * they're also RAZ for AArch64, and in v8 are gradually
8728 * being filled with AArch64-view-of-AArch32-ID-register
8729 * for new ID registers.
8731 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8732 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8733 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8734 .accessfn
= access_aa64_tid3
,
8736 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8737 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8738 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8739 .accessfn
= access_aa64_tid3
,
8740 .resetvalue
= cpu
->isar
.id_pfr2
},
8741 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8742 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8743 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8744 .accessfn
= access_aa64_tid3
,
8745 .resetvalue
= cpu
->isar
.id_dfr1
},
8746 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8747 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8748 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8749 .accessfn
= access_aa64_tid3
,
8750 .resetvalue
= cpu
->isar
.id_mmfr5
},
8751 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8752 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8753 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8754 .accessfn
= access_aa64_tid3
,
8756 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8757 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8758 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8759 .fgt
= FGT_PMCEIDN_EL0
,
8760 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8761 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8762 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8763 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8764 .fgt
= FGT_PMCEIDN_EL0
,
8765 .resetvalue
= cpu
->pmceid0
},
8766 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8767 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8768 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8769 .fgt
= FGT_PMCEIDN_EL0
,
8770 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8771 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8772 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8773 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8774 .fgt
= FGT_PMCEIDN_EL0
,
8775 .resetvalue
= cpu
->pmceid1
},
8777 #ifdef CONFIG_USER_ONLY
8778 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8779 { .name
= "ID_AA64PFR0_EL1",
8780 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8781 R_ID_AA64PFR0_ADVSIMD_MASK
|
8782 R_ID_AA64PFR0_SVE_MASK
|
8783 R_ID_AA64PFR0_DIT_MASK
,
8784 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8785 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8786 { .name
= "ID_AA64PFR1_EL1",
8787 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8788 R_ID_AA64PFR1_SSBS_MASK
|
8789 R_ID_AA64PFR1_MTE_MASK
|
8790 R_ID_AA64PFR1_SME_MASK
},
8791 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8793 { .name
= "ID_AA64ZFR0_EL1",
8794 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8795 R_ID_AA64ZFR0_AES_MASK
|
8796 R_ID_AA64ZFR0_BITPERM_MASK
|
8797 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8798 R_ID_AA64ZFR0_SHA3_MASK
|
8799 R_ID_AA64ZFR0_SM4_MASK
|
8800 R_ID_AA64ZFR0_I8MM_MASK
|
8801 R_ID_AA64ZFR0_F32MM_MASK
|
8802 R_ID_AA64ZFR0_F64MM_MASK
},
8803 { .name
= "ID_AA64SMFR0_EL1",
8804 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8805 R_ID_AA64SMFR0_BI32I32_MASK
|
8806 R_ID_AA64SMFR0_B16F32_MASK
|
8807 R_ID_AA64SMFR0_F16F32_MASK
|
8808 R_ID_AA64SMFR0_I8I32_MASK
|
8809 R_ID_AA64SMFR0_F16F16_MASK
|
8810 R_ID_AA64SMFR0_B16B16_MASK
|
8811 R_ID_AA64SMFR0_I16I32_MASK
|
8812 R_ID_AA64SMFR0_F64F64_MASK
|
8813 R_ID_AA64SMFR0_I16I64_MASK
|
8814 R_ID_AA64SMFR0_SMEVER_MASK
|
8815 R_ID_AA64SMFR0_FA64_MASK
},
8816 { .name
= "ID_AA64MMFR0_EL1",
8817 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8818 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8819 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8820 { .name
= "ID_AA64MMFR1_EL1",
8821 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8822 { .name
= "ID_AA64MMFR2_EL1",
8823 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8824 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8826 { .name
= "ID_AA64DFR0_EL1",
8827 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8828 { .name
= "ID_AA64DFR1_EL1" },
8829 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8831 { .name
= "ID_AA64AFR*",
8833 { .name
= "ID_AA64ISAR0_EL1",
8834 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8835 R_ID_AA64ISAR0_SHA1_MASK
|
8836 R_ID_AA64ISAR0_SHA2_MASK
|
8837 R_ID_AA64ISAR0_CRC32_MASK
|
8838 R_ID_AA64ISAR0_ATOMIC_MASK
|
8839 R_ID_AA64ISAR0_RDM_MASK
|
8840 R_ID_AA64ISAR0_SHA3_MASK
|
8841 R_ID_AA64ISAR0_SM3_MASK
|
8842 R_ID_AA64ISAR0_SM4_MASK
|
8843 R_ID_AA64ISAR0_DP_MASK
|
8844 R_ID_AA64ISAR0_FHM_MASK
|
8845 R_ID_AA64ISAR0_TS_MASK
|
8846 R_ID_AA64ISAR0_RNDR_MASK
},
8847 { .name
= "ID_AA64ISAR1_EL1",
8848 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8849 R_ID_AA64ISAR1_APA_MASK
|
8850 R_ID_AA64ISAR1_API_MASK
|
8851 R_ID_AA64ISAR1_JSCVT_MASK
|
8852 R_ID_AA64ISAR1_FCMA_MASK
|
8853 R_ID_AA64ISAR1_LRCPC_MASK
|
8854 R_ID_AA64ISAR1_GPA_MASK
|
8855 R_ID_AA64ISAR1_GPI_MASK
|
8856 R_ID_AA64ISAR1_FRINTTS_MASK
|
8857 R_ID_AA64ISAR1_SB_MASK
|
8858 R_ID_AA64ISAR1_BF16_MASK
|
8859 R_ID_AA64ISAR1_DGH_MASK
|
8860 R_ID_AA64ISAR1_I8MM_MASK
},
8861 { .name
= "ID_AA64ISAR2_EL1",
8862 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8863 R_ID_AA64ISAR2_RPRES_MASK
|
8864 R_ID_AA64ISAR2_GPA3_MASK
|
8865 R_ID_AA64ISAR2_APA3_MASK
|
8866 R_ID_AA64ISAR2_MOPS_MASK
|
8867 R_ID_AA64ISAR2_BC_MASK
|
8868 R_ID_AA64ISAR2_RPRFM_MASK
|
8869 R_ID_AA64ISAR2_CSSC_MASK
},
8870 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8873 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8876 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8877 * TODO: For RMR, a write with bit 1 set should do something with
8878 * cpu_reset(). In the meantime, "the bit is strictly a request",
8879 * so we are in spec just ignoring writes.
8881 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8882 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8883 ARMCPRegInfo el1_reset_regs
[] = {
8884 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8885 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8887 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8888 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8889 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8890 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8891 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8893 define_arm_cp_regs(cpu
, el1_reset_regs
);
8895 define_arm_cp_regs(cpu
, v8_idregs
);
8896 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8897 if (cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
8898 define_arm_cp_regs(cpu
, v8_aa32_el1_reginfo
);
8901 for (i
= 4; i
< 16; i
++) {
8903 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8904 * For pre-v8 cores there are RAZ patterns for these in
8905 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8906 * v8 extends the "must RAZ" part of the ID register space
8907 * to also cover c0, 0, c{8-15}, {0-7}.
8908 * These are STATE_AA32 because in the AArch64 sysreg space
8909 * c4-c7 is where the AArch64 ID registers live (and we've
8910 * already defined those in v8_idregs[]), and c8-c15 are not
8911 * "must RAZ" for AArch64.
8913 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8914 ARMCPRegInfo v8_aa32_raz_idregs
= {
8916 .state
= ARM_CP_STATE_AA32
,
8917 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8918 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8919 .accessfn
= access_aa64_tid3
,
8921 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8926 * Register the base EL2 cpregs.
8927 * Pre v8, these registers are implemented only as part of the
8928 * Virtualization Extensions (EL2 present). Beginning with v8,
8929 * if EL2 is missing but EL3 is enabled, mostly these become
8930 * RES0 from EL3, with some specific exceptions.
8932 if (arm_feature(env
, ARM_FEATURE_EL2
)
8933 || (arm_feature(env
, ARM_FEATURE_EL3
)
8934 && arm_feature(env
, ARM_FEATURE_V8
))) {
8935 uint64_t vmpidr_def
= mpidr_read_val(env
);
8936 ARMCPRegInfo vpidr_regs
[] = {
8937 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8938 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8939 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8940 .resetvalue
= cpu
->midr
,
8941 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8942 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8943 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8944 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8945 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8946 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8947 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8948 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8949 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8950 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8951 .resetvalue
= vmpidr_def
,
8952 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8953 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8954 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8955 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8956 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8957 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8958 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8961 * The only field of MDCR_EL2 that has a defined architectural reset
8962 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8964 ARMCPRegInfo mdcr_el2
= {
8965 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8966 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8967 .writefn
= mdcr_el2_write
,
8968 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8969 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8971 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8972 define_arm_cp_regs(cpu
, vpidr_regs
);
8973 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8974 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8975 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8977 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8978 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8981 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
8982 * See commentary near RMR_EL1.
8984 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8985 static const ARMCPRegInfo el2_reset_regs
[] = {
8986 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8987 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8989 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8990 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8991 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8993 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8994 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
8995 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
8996 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8998 define_arm_cp_regs(cpu
, el2_reset_regs
);
9002 /* Register the base EL3 cpregs. */
9003 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9004 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
9005 ARMCPRegInfo el3_regs
[] = {
9006 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
9007 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
9009 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
9010 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
9011 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
9012 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9013 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
9014 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
9015 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9016 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
9017 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9018 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
9020 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
9021 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
9022 .resetvalue
= cpu
->reset_sctlr
},
9025 define_arm_cp_regs(cpu
, el3_regs
);
9028 * The behaviour of NSACR is sufficiently various that we don't
9029 * try to describe it in a single reginfo:
9030 * if EL3 is 64 bit, then trap to EL3 from S EL1,
9031 * reads as constant 0xc00 from NS EL1 and NS EL2
9032 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
9033 * if v7 without EL3, register doesn't exist
9034 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
9036 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9037 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9038 static const ARMCPRegInfo nsacr
= {
9039 .name
= "NSACR", .type
= ARM_CP_CONST
,
9040 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9041 .access
= PL1_RW
, .accessfn
= nsacr_access
,
9044 define_one_arm_cp_reg(cpu
, &nsacr
);
9046 static const ARMCPRegInfo nsacr
= {
9048 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9049 .access
= PL3_RW
| PL1_R
,
9051 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
9053 define_one_arm_cp_reg(cpu
, &nsacr
);
9056 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9057 static const ARMCPRegInfo nsacr
= {
9058 .name
= "NSACR", .type
= ARM_CP_CONST
,
9059 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9063 define_one_arm_cp_reg(cpu
, &nsacr
);
9067 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9068 if (arm_feature(env
, ARM_FEATURE_V6
)) {
9069 /* PMSAv6 not implemented */
9070 assert(arm_feature(env
, ARM_FEATURE_V7
));
9071 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9072 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
9074 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
9077 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9078 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
9079 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
9080 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
9081 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
9084 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
9085 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
9087 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
9088 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
9090 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
9091 ARMCPRegInfo vapa_cp_reginfo
[] = {
9092 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
9093 .access
= PL1_RW
, .resetvalue
= 0,
9094 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
9095 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
9096 .writefn
= par_write
},
9097 #ifndef CONFIG_USER_ONLY
9098 /* This underdecoding is safe because the reginfo is NO_RAW. */
9099 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
9100 .access
= PL1_W
, .accessfn
= ats_access
,
9101 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
9106 * When LPAE exists this 32-bit PAR register is an alias of the
9107 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
9109 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9110 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9112 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
9114 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
9115 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
9117 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
9118 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
9120 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
9121 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
9123 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
9124 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
9126 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9127 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
9129 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9130 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
9132 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
9133 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
9135 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9136 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
9138 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
9139 define_arm_cp_regs(cpu
, jazelle_regs
);
9142 * Slightly awkwardly, the OMAP and StrongARM cores need all of
9143 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
9144 * be read-only (ie write causes UNDEF exception).
9147 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
9149 * Pre-v8 MIDR space.
9150 * Note that the MIDR isn't a simple constant register because
9151 * of the TI925 behaviour where writes to another register can
9152 * cause the MIDR value to change.
9154 * Unimplemented registers in the c15 0 0 0 space default to
9155 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
9156 * and friends override accordingly.
9159 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
9160 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
9161 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
9162 .readfn
= midr_read
,
9163 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9164 .type
= ARM_CP_OVERRIDE
},
9165 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
9167 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
9168 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9170 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
9171 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9173 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
9174 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9176 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
9177 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9179 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
9180 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9182 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
9183 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9184 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
9185 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
9186 .fgt
= FGT_MIDR_EL1
,
9187 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9188 .readfn
= midr_read
},
9189 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
9190 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
9191 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
9192 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
9193 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9194 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
9196 .accessfn
= access_aa64_tid1
,
9197 .fgt
= FGT_REVIDR_EL1
,
9198 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9200 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9201 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9202 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9203 .access
= PL1_R
, .resetvalue
= cpu
->midr
9205 ARMCPRegInfo id_cp_reginfo
[] = {
9206 /* These are common to v8 and pre-v8 */
9208 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9209 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9210 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9211 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9212 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9213 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9215 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9216 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9218 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9220 .accessfn
= access_aa32_tid1
,
9221 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9223 /* TLBTR is specific to VMSA */
9224 ARMCPRegInfo id_tlbtr_reginfo
= {
9226 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9228 .accessfn
= access_aa32_tid1
,
9229 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9231 /* MPUIR is specific to PMSA V6+ */
9232 ARMCPRegInfo id_mpuir_reginfo
= {
9234 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9235 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9236 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9238 /* HMPUIR is specific to PMSA V8 */
9239 ARMCPRegInfo id_hmpuir_reginfo
= {
9241 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9242 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9243 .resetvalue
= cpu
->pmsav8r_hdregion
9245 static const ARMCPRegInfo crn0_wi_reginfo
= {
9246 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9247 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9248 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9250 #ifdef CONFIG_USER_ONLY
9251 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9252 { .name
= "MIDR_EL1",
9253 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9254 R_MIDR_EL1_PARTNUM_MASK
|
9255 R_MIDR_EL1_ARCHITECTURE_MASK
|
9256 R_MIDR_EL1_VARIANT_MASK
|
9257 R_MIDR_EL1_IMPLEMENTER_MASK
},
9258 { .name
= "REVIDR_EL1" },
9260 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9262 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9263 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9266 * Register the blanket "writes ignored" value first to cover the
9267 * whole space. Then update the specific ID registers to allow write
9268 * access, so that they ignore writes rather than causing them to
9271 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9272 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9273 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9275 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9276 id_cp_reginfo
[i
].access
= PL1_RW
;
9278 id_mpuir_reginfo
.access
= PL1_RW
;
9279 id_tlbtr_reginfo
.access
= PL1_RW
;
9281 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9282 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9283 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9284 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9287 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9289 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9290 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9291 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9292 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9293 arm_feature(env
, ARM_FEATURE_V8
)) {
9297 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9298 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9299 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9301 /* Register alias is only valid for first 32 indexes */
9302 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9303 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9304 uint8_t opc1
= extract32(i
, 4, 1);
9305 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9307 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9308 ARMCPRegInfo tmp_prbarn_reginfo
= {
9309 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9310 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9311 .access
= PL1_RW
, .resetvalue
= 0,
9312 .accessfn
= access_tvm_trvm
,
9313 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9315 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9318 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9319 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9320 ARMCPRegInfo tmp_prlarn_reginfo
= {
9321 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9322 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9323 .access
= PL1_RW
, .resetvalue
= 0,
9324 .accessfn
= access_tvm_trvm
,
9325 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9327 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9331 /* Register alias is only valid for first 32 indexes */
9332 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9333 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9334 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9335 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9337 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9338 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9340 .type
= ARM_CP_NO_RAW
,
9341 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9342 .access
= PL2_RW
, .resetvalue
= 0,
9343 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9345 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9348 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9349 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9350 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9352 .type
= ARM_CP_NO_RAW
,
9353 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9354 .access
= PL2_RW
, .resetvalue
= 0,
9355 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9357 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9360 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9361 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9365 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9366 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9367 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9368 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9369 .fgt
= FGT_MPIDR_EL1
,
9370 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9372 #ifdef CONFIG_USER_ONLY
9373 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9374 { .name
= "MPIDR_EL1",
9375 .fixed_bits
= 0x0000000080000000 },
9377 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9379 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9382 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9383 ARMCPRegInfo auxcr_reginfo
[] = {
9384 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9385 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9386 .access
= PL1_RW
, .accessfn
= access_tacr
,
9387 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9388 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9389 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9390 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9392 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9393 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9394 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9397 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9398 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9399 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9403 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9405 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9406 * There are two flavours:
9407 * (1) older 32-bit only cores have a simple 32-bit CBAR
9408 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9409 * 32-bit register visible to AArch32 at a different encoding
9410 * to the "flavour 1" register and with the bits rearranged to
9411 * be able to squash a 64-bit address into the 32-bit view.
9412 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9413 * in future if we support AArch32-only configs of some of the
9414 * AArch64 cores we might need to add a specific feature flag
9415 * to indicate cores with "flavour 2" CBAR.
9417 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9418 /* 32 bit view is [31:18] 0...0 [43:32]. */
9419 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9420 | extract64(cpu
->reset_cbar
, 32, 12);
9421 ARMCPRegInfo cbar_reginfo
[] = {
9423 .type
= ARM_CP_CONST
,
9424 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9425 .access
= PL1_R
, .resetvalue
= cbar32
},
9426 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9427 .type
= ARM_CP_CONST
,
9428 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9429 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9431 /* We don't implement a r/w 64 bit CBAR currently */
9432 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9433 define_arm_cp_regs(cpu
, cbar_reginfo
);
9435 ARMCPRegInfo cbar
= {
9437 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9438 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9439 .fieldoffset
= offsetof(CPUARMState
,
9440 cp15
.c15_config_base_address
)
9442 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9443 cbar
.access
= PL1_R
;
9444 cbar
.fieldoffset
= 0;
9445 cbar
.type
= ARM_CP_CONST
;
9447 define_one_arm_cp_reg(cpu
, &cbar
);
9451 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9452 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9453 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9454 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9455 .access
= PL1_RW
, .writefn
= vbar_write
,
9456 .accessfn
= access_nv1
,
9457 .fgt
= FGT_VBAR_EL1
,
9458 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9459 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9462 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9465 /* Generic registers whose values depend on the implementation */
9467 ARMCPRegInfo sctlr
= {
9468 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9469 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9470 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9471 .fgt
= FGT_SCTLR_EL1
,
9472 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9473 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9474 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9475 .raw_writefn
= raw_write
,
9477 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9479 * Normally we would always end the TB on an SCTLR write, but Linux
9480 * arch/arm/mach-pxa/sleep.S expects two instructions following
9481 * an MMU enable to execute from cache. Imitate this behaviour.
9483 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9485 define_one_arm_cp_reg(cpu
, &sctlr
);
9487 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9488 arm_feature(env
, ARM_FEATURE_V8
)) {
9489 ARMCPRegInfo vsctlr
= {
9490 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9491 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9492 .access
= PL2_RW
, .resetvalue
= 0x0,
9493 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9495 define_one_arm_cp_reg(cpu
, &vsctlr
);
9499 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9500 define_arm_cp_regs(cpu
, lor_reginfo
);
9502 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9503 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9505 #ifndef CONFIG_USER_ONLY
9506 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9507 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9509 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9510 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9513 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9514 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9517 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9518 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9520 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9521 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9523 if (cpu_isar_feature(any_ras
, cpu
)) {
9524 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9527 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9528 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9529 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9531 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9532 define_arm_cp_regs(cpu
, vhe_reginfo
);
9535 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9536 define_arm_cp_regs(cpu
, zcr_reginfo
);
9539 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9540 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9543 #ifdef TARGET_AARCH64
9544 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9545 define_arm_cp_regs(cpu
, sme_reginfo
);
9547 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9548 define_arm_cp_regs(cpu
, pauth_reginfo
);
9550 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9551 define_arm_cp_regs(cpu
, rndr_reginfo
);
9553 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9554 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9556 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9557 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9559 /* Data Cache clean instructions up to PoP */
9560 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9561 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9563 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9564 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9569 * If full MTE is enabled, add all of the system registers.
9570 * If only "instructions available at EL0" are enabled,
9571 * then define only a RAZ/WI version of PSTATE.TCO.
9573 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9574 ARMCPRegInfo gmid_reginfo
= {
9575 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9576 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9577 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9578 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9580 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9581 define_arm_cp_regs(cpu
, mte_reginfo
);
9582 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9583 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9584 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9585 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9588 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9589 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9592 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9593 define_arm_cp_regs(cpu
, fgt_reginfo
);
9596 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9597 define_arm_cp_regs(cpu
, rme_reginfo
);
9598 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9599 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9604 if (cpu_isar_feature(any_predinv
, cpu
)) {
9605 define_arm_cp_regs(cpu
, predinv_reginfo
);
9608 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9609 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9612 #ifndef CONFIG_USER_ONLY
9614 * Register redirections and aliases must be done last,
9615 * after the registers from the other extensions have been defined.
9617 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9618 define_arm_vh_e2h_redirects_aliases(cpu
);
9624 * Private utility function for define_one_arm_cp_reg_with_opaque():
9625 * add a single reginfo struct to the hash table.
9627 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9628 void *opaque
, CPState state
,
9629 CPSecureState secstate
,
9630 int crm
, int opc1
, int opc2
,
9633 CPUARMState
*env
= &cpu
->env
;
9636 bool is64
= r
->type
& ARM_CP_64BIT
;
9637 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9643 case ARM_CP_STATE_AA32
:
9644 /* We assume it is a cp15 register if the .cp field is left unset. */
9645 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9648 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9650 case ARM_CP_STATE_AA64
:
9652 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9653 * cp == 0 as equivalent to the value for "standard guest-visible
9654 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9655 * in their AArch64 view (the .cp value may be non-zero for the
9656 * benefit of the AArch32 view).
9658 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9659 cp
= CP_REG_ARM64_SYSREG_CP
;
9661 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9664 g_assert_not_reached();
9667 /* Overriding of an existing definition must be explicitly requested. */
9668 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9669 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9671 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9676 * Eliminate registers that are not present because the EL is missing.
9677 * Doing this here makes it easier to put all registers for a given
9678 * feature into the same ARMCPRegInfo array and define them all at once.
9681 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9683 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9684 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9686 int min_el
= ctz32(r
->access
) / 2;
9687 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9688 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9691 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9694 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9696 if ((r
->access
& max_el
) == 0) {
9701 /* Combine cpreg and name into one allocation. */
9702 name_len
= strlen(name
) + 1;
9703 r2
= g_malloc(sizeof(*r2
) + name_len
);
9705 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9708 * Update fields to match the instantiation, overwiting wildcards
9709 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9716 r2
->secure
= secstate
;
9718 r2
->opaque
= opaque
;
9722 /* This should not have been a very special register to begin. */
9723 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9724 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9726 * Set the special function to CONST, retaining the other flags.
9727 * This is important for e.g. ARM_CP_SVE so that we still
9728 * take the SVE trap if CPTR_EL3.EZ == 0.
9730 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9732 * Usually, these registers become RES0, but there are a few
9733 * special cases like VPIDR_EL2 which have a constant non-zero
9734 * value with writes ignored.
9736 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9740 * ARM_CP_CONST has precedence, so removing the callbacks and
9741 * offsets are not strictly necessary, but it is potentially
9742 * less confusing to debug later.
9746 r2
->raw_readfn
= NULL
;
9747 r2
->raw_writefn
= NULL
;
9749 r2
->fieldoffset
= 0;
9750 r2
->bank_fieldoffsets
[0] = 0;
9751 r2
->bank_fieldoffsets
[1] = 0;
9753 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9757 * Register is banked (using both entries in array).
9758 * Overwriting fieldoffset as the array is only used to define
9759 * banked registers but later only fieldoffset is used.
9761 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9763 if (state
== ARM_CP_STATE_AA32
) {
9766 * If the register is banked then we don't need to migrate or
9767 * reset the 32-bit instance in certain cases:
9769 * 1) If the register has both 32-bit and 64-bit instances
9770 * then we can count on the 64-bit instance taking care
9771 * of the non-secure bank.
9772 * 2) If ARMv8 is enabled then we can count on a 64-bit
9773 * version taking care of the secure bank. This requires
9774 * that separate 32 and 64-bit definitions are provided.
9776 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9777 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9778 r2
->type
|= ARM_CP_ALIAS
;
9780 } else if ((secstate
!= r
->secure
) && !ns
) {
9782 * The register is not banked so we only want to allow
9783 * migration of the non-secure instance.
9785 r2
->type
|= ARM_CP_ALIAS
;
9788 if (HOST_BIG_ENDIAN
&&
9789 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9790 r2
->fieldoffset
+= sizeof(uint32_t);
9796 * By convention, for wildcarded registers only the first
9797 * entry is used for migration; the others are marked as
9798 * ALIAS so we don't try to transfer the register
9799 * multiple times. Special registers (ie NOP/WFI) are
9800 * never migratable and not even raw-accessible.
9802 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9803 r2
->type
|= ARM_CP_NO_RAW
;
9805 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9806 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9807 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9808 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9812 * Check that raw accesses are either forbidden or handled. Note that
9813 * we can't assert this earlier because the setup of fieldoffset for
9814 * banked registers has to be done first.
9816 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9817 assert(!raw_accessors_invalid(r2
));
9820 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9824 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9825 const ARMCPRegInfo
*r
, void *opaque
)
9828 * Define implementations of coprocessor registers.
9829 * We store these in a hashtable because typically
9830 * there are less than 150 registers in a space which
9831 * is 16*16*16*8*8 = 262144 in size.
9832 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9833 * If a register is defined twice then the second definition is
9834 * used, so this can be used to define some generic registers and
9835 * then override them with implementation specific variations.
9836 * At least one of the original and the second definition should
9837 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9838 * against accidental use.
9840 * The state field defines whether the register is to be
9841 * visible in the AArch32 or AArch64 execution state. If the
9842 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9843 * reginfo structure for the AArch32 view, which sees the lower
9844 * 32 bits of the 64 bit register.
9846 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9847 * be wildcarded. AArch64 registers are always considered to be 64
9848 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9849 * the register, if any.
9851 int crm
, opc1
, opc2
;
9852 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9853 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9854 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9855 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9856 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9857 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9860 /* 64 bit registers have only CRm and Opc1 fields */
9861 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9862 /* op0 only exists in the AArch64 encodings */
9863 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9864 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9865 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9867 * This API is only for Arm's system coprocessors (14 and 15) or
9868 * (M-profile or v7A-and-earlier only) for implementation defined
9869 * coprocessors in the range 0..7. Our decode assumes this, since
9870 * 8..13 can be used for other insns including VFP and Neon. See
9871 * valid_cp() in translate.c. Assert here that we haven't tried
9872 * to use an invalid coprocessor number.
9875 case ARM_CP_STATE_BOTH
:
9876 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9881 case ARM_CP_STATE_AA32
:
9882 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9883 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9884 assert(r
->cp
>= 14 && r
->cp
<= 15);
9886 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9889 case ARM_CP_STATE_AA64
:
9890 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9893 g_assert_not_reached();
9896 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9897 * encodes a minimum access level for the register. We roll this
9898 * runtime check into our general permission check code, so check
9899 * here that the reginfo's specified permissions are strict enough
9900 * to encompass the generic architectural permission check.
9902 if (r
->state
!= ARM_CP_STATE_AA32
) {
9903 CPAccessRights mask
;
9906 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9907 mask
= PL0U_R
| PL1_RW
;
9927 /* min_EL EL1, secure mode only (we don't check the latter) */
9931 /* broken reginfo with out-of-range opc1 */
9932 g_assert_not_reached();
9934 /* assert our permissions are not too lax (stricter is fine) */
9935 assert((r
->access
& ~mask
) == 0);
9939 * Check that the register definition has enough info to handle
9940 * reads and writes if they are permitted.
9942 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9943 if (r
->access
& PL3_R
) {
9944 assert((r
->fieldoffset
||
9945 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9948 if (r
->access
& PL3_W
) {
9949 assert((r
->fieldoffset
||
9950 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9955 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9956 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9957 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9958 for (state
= ARM_CP_STATE_AA32
;
9959 state
<= ARM_CP_STATE_AA64
; state
++) {
9960 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9963 if (state
== ARM_CP_STATE_AA32
) {
9965 * Under AArch32 CP registers can be common
9966 * (same for secure and non-secure world) or banked.
9970 switch (r
->secure
) {
9971 case ARM_CP_SECSTATE_S
:
9972 case ARM_CP_SECSTATE_NS
:
9973 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9974 r
->secure
, crm
, opc1
, opc2
,
9977 case ARM_CP_SECSTATE_BOTH
:
9978 name
= g_strdup_printf("%s_S", r
->name
);
9979 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9981 crm
, opc1
, opc2
, name
);
9983 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9985 crm
, opc1
, opc2
, r
->name
);
9988 g_assert_not_reached();
9992 * AArch64 registers get mapped to non-secure instance
9995 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9997 crm
, opc1
, opc2
, r
->name
);
10005 /* Define a whole list of registers */
10006 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
10007 void *opaque
, size_t len
)
10010 for (i
= 0; i
< len
; ++i
) {
10011 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
10016 * Modify ARMCPRegInfo for access from userspace.
10018 * This is a data driven modification directed by
10019 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
10020 * user-space cannot alter any values and dynamic values pertaining to
10021 * execution state are hidden from user space view anyway.
10023 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
10024 const ARMCPRegUserSpaceInfo
*mods
,
10027 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
10028 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
10029 GPatternSpec
*pat
= NULL
;
10032 pat
= g_pattern_spec_new(m
->name
);
10034 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
10035 ARMCPRegInfo
*r
= regs
+ ri
;
10037 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
10038 r
->type
= ARM_CP_CONST
;
10039 r
->access
= PL0U_R
;
10042 } else if (strcmp(r
->name
, m
->name
) == 0) {
10043 r
->type
= ARM_CP_CONST
;
10044 r
->access
= PL0U_R
;
10045 r
->resetvalue
&= m
->exported_bits
;
10046 r
->resetvalue
|= m
->fixed_bits
;
10051 g_pattern_spec_free(pat
);
10056 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
10058 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
10061 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
10064 /* Helper coprocessor write function for write-ignore registers */
10067 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
10069 /* Helper coprocessor write function for read-as-zero registers */
10073 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
10075 /* Helper coprocessor reset function for do-nothing-on-reset registers */
10078 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
10081 * Return true if it is not valid for us to switch to
10082 * this CPU mode (ie all the UNPREDICTABLE cases in
10083 * the ARM ARM CPSRWriteByInstr pseudocode).
10086 /* Changes to or from Hyp via MSR and CPS are illegal. */
10087 if (write_type
== CPSRWriteByInstr
&&
10088 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
10089 mode
== ARM_CPU_MODE_HYP
)) {
10094 case ARM_CPU_MODE_USR
:
10096 case ARM_CPU_MODE_SYS
:
10097 case ARM_CPU_MODE_SVC
:
10098 case ARM_CPU_MODE_ABT
:
10099 case ARM_CPU_MODE_UND
:
10100 case ARM_CPU_MODE_IRQ
:
10101 case ARM_CPU_MODE_FIQ
:
10103 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
10104 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
10107 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
10108 * and CPS are treated as illegal mode changes.
10110 if (write_type
== CPSRWriteByInstr
&&
10111 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
10112 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
10116 case ARM_CPU_MODE_HYP
:
10117 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
10118 case ARM_CPU_MODE_MON
:
10119 return arm_current_el(env
) < 3;
10125 uint32_t cpsr_read(CPUARMState
*env
)
10128 ZF
= (env
->ZF
== 0);
10129 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
10130 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
10131 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
10132 | ((env
->condexec_bits
& 0xfc) << 8)
10133 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
10136 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
10137 CPSRWriteType write_type
)
10139 uint32_t changed_daif
;
10140 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
10141 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
10143 if (mask
& CPSR_NZCV
) {
10144 env
->ZF
= (~val
) & CPSR_Z
;
10146 env
->CF
= (val
>> 29) & 1;
10147 env
->VF
= (val
<< 3) & 0x80000000;
10149 if (mask
& CPSR_Q
) {
10150 env
->QF
= ((val
& CPSR_Q
) != 0);
10152 if (mask
& CPSR_T
) {
10153 env
->thumb
= ((val
& CPSR_T
) != 0);
10155 if (mask
& CPSR_IT_0_1
) {
10156 env
->condexec_bits
&= ~3;
10157 env
->condexec_bits
|= (val
>> 25) & 3;
10159 if (mask
& CPSR_IT_2_7
) {
10160 env
->condexec_bits
&= 3;
10161 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10163 if (mask
& CPSR_GE
) {
10164 env
->GE
= (val
>> 16) & 0xf;
10168 * In a V7 implementation that includes the security extensions but does
10169 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10170 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10171 * bits respectively.
10173 * In a V8 implementation, it is permitted for privileged software to
10174 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10176 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10177 arm_feature(env
, ARM_FEATURE_EL3
) &&
10178 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10179 !arm_is_secure(env
)) {
10181 changed_daif
= (env
->daif
^ val
) & mask
;
10183 if (changed_daif
& CPSR_A
) {
10185 * Check to see if we are allowed to change the masking of async
10186 * abort exceptions from a non-secure state.
10188 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10189 qemu_log_mask(LOG_GUEST_ERROR
,
10190 "Ignoring attempt to switch CPSR_A flag from "
10191 "non-secure world with SCR.AW bit clear\n");
10196 if (changed_daif
& CPSR_F
) {
10198 * Check to see if we are allowed to change the masking of FIQ
10199 * exceptions from a non-secure state.
10201 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10202 qemu_log_mask(LOG_GUEST_ERROR
,
10203 "Ignoring attempt to switch CPSR_F flag from "
10204 "non-secure world with SCR.FW bit clear\n");
10209 * Check whether non-maskable FIQ (NMFI) support is enabled.
10210 * If this bit is set software is not allowed to mask
10211 * FIQs, but is allowed to set CPSR_F to 0.
10213 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10215 qemu_log_mask(LOG_GUEST_ERROR
,
10216 "Ignoring attempt to enable CPSR_F flag "
10217 "(non-maskable FIQ [NMFI] support enabled)\n");
10223 env
->daif
&= ~(CPSR_AIF
& mask
);
10224 env
->daif
|= val
& CPSR_AIF
& mask
;
10226 if (write_type
!= CPSRWriteRaw
&&
10227 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10228 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10230 * Note that we can only get here in USR mode if this is a
10231 * gdb stub write; for this case we follow the architectural
10232 * behaviour for guest writes in USR mode of ignoring an attempt
10233 * to switch mode. (Those are caught by translate.c for writes
10234 * triggered by guest instructions.)
10237 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10239 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10240 * v7, and has defined behaviour in v8:
10241 * + leave CPSR.M untouched
10242 * + allow changes to the other CPSR fields
10244 * For user changes via the GDB stub, we don't set PSTATE.IL,
10245 * as this would be unnecessarily harsh for a user error.
10248 if (write_type
!= CPSRWriteByGDBStub
&&
10249 arm_feature(env
, ARM_FEATURE_V8
)) {
10253 qemu_log_mask(LOG_GUEST_ERROR
,
10254 "Illegal AArch32 mode switch attempt from %s to %s\n",
10255 aarch32_mode_name(env
->uncached_cpsr
),
10256 aarch32_mode_name(val
));
10258 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10259 write_type
== CPSRWriteExceptionReturn
?
10260 "Exception return from AArch32" :
10261 "AArch32 mode switch from",
10262 aarch32_mode_name(env
->uncached_cpsr
),
10263 aarch32_mode_name(val
), env
->regs
[15]);
10264 switch_mode(env
, val
& CPSR_M
);
10267 mask
&= ~CACHED_CPSR_BITS
;
10268 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10269 if (tcg_enabled() && rebuild_hflags
) {
10270 arm_rebuild_hflags(env
);
10274 #ifdef CONFIG_USER_ONLY
10276 static void switch_mode(CPUARMState
*env
, int mode
)
10278 ARMCPU
*cpu
= env_archcpu(env
);
10280 if (mode
!= ARM_CPU_MODE_USR
) {
10281 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10285 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10286 uint32_t cur_el
, bool secure
)
10291 void aarch64_sync_64_to_32(CPUARMState
*env
)
10293 g_assert_not_reached();
10298 static void switch_mode(CPUARMState
*env
, int mode
)
10303 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10304 if (mode
== old_mode
) {
10308 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10309 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10310 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10311 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10312 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10313 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10316 i
= bank_number(old_mode
);
10317 env
->banked_r13
[i
] = env
->regs
[13];
10318 env
->banked_spsr
[i
] = env
->spsr
;
10320 i
= bank_number(mode
);
10321 env
->regs
[13] = env
->banked_r13
[i
];
10322 env
->spsr
= env
->banked_spsr
[i
];
10324 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10325 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10329 * Physical Interrupt Target EL Lookup Table
10331 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10333 * The below multi-dimensional table is used for looking up the target
10334 * exception level given numerous condition criteria. Specifically, the
10335 * target EL is based on SCR and HCR routing controls as well as the
10336 * currently executing EL and secure state.
10339 * target_el_table[2][2][2][2][2][4]
10340 * | | | | | +--- Current EL
10341 * | | | | +------ Non-secure(0)/Secure(1)
10342 * | | | +--------- HCR mask override
10343 * | | +------------ SCR exec state control
10344 * | +--------------- SCR mask override
10345 * +------------------ 32-bit(0)/64-bit(1) EL3
10347 * The table values are as such:
10349 * -1 = Cannot occur
10351 * The ARM ARM target EL table includes entries indicating that an "exception
10352 * is not taken". The two cases where this is applicable are:
10353 * 1) An exception is taken from EL3 but the SCR does not have the exception
10355 * 2) An exception is taken from EL2 but the HCR does not have the exception
10357 * In these two cases, the below table contain a target of EL1. This value is
10358 * returned as it is expected that the consumer of the table data will check
10359 * for "target EL >= current EL" to ensure the exception is not taken.
10363 * BIT IRQ IMO Non-secure Secure
10364 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10366 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10367 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10368 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10369 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10370 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10371 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10372 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10373 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10374 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10375 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10376 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10377 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10378 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10379 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10380 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10381 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10382 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10386 * Determine the target EL for physical exceptions
10388 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10389 uint32_t cur_el
, bool secure
)
10391 CPUARMState
*env
= cpu_env(cs
);
10396 /* Is the highest EL AArch64? */
10397 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10400 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10401 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10404 * Either EL2 is the highest EL (and so the EL2 register width
10405 * is given by is64); or there is no EL2 or EL3, in which case
10406 * the value of 'rw' does not affect the table lookup anyway.
10411 hcr_el2
= arm_hcr_el2_eff(env
);
10412 switch (excp_idx
) {
10414 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10415 hcr
= hcr_el2
& HCR_IMO
;
10418 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10419 hcr
= hcr_el2
& HCR_FMO
;
10422 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10423 hcr
= hcr_el2
& HCR_AMO
;
10428 * For these purposes, TGE and AMO/IMO/FMO both force the
10429 * interrupt to EL2. Fold TGE into the bit extracted above.
10431 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10433 /* Perform a table-lookup for the target EL given the current state */
10434 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10436 assert(target_el
> 0);
10441 void arm_log_exception(CPUState
*cs
)
10443 int idx
= cs
->exception_index
;
10445 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10446 const char *exc
= NULL
;
10447 static const char * const excnames
[] = {
10448 [EXCP_UDEF
] = "Undefined Instruction",
10449 [EXCP_SWI
] = "SVC",
10450 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10451 [EXCP_DATA_ABORT
] = "Data Abort",
10452 [EXCP_IRQ
] = "IRQ",
10453 [EXCP_FIQ
] = "FIQ",
10454 [EXCP_BKPT
] = "Breakpoint",
10455 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10456 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10457 [EXCP_HVC
] = "Hypervisor Call",
10458 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10459 [EXCP_SMC
] = "Secure Monitor Call",
10460 [EXCP_VIRQ
] = "Virtual IRQ",
10461 [EXCP_VFIQ
] = "Virtual FIQ",
10462 [EXCP_SEMIHOST
] = "Semihosting call",
10463 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10464 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10465 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10466 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10467 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10468 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10469 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10470 [EXCP_VSERR
] = "Virtual SERR",
10471 [EXCP_GPC
] = "Granule Protection Check",
10474 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10475 exc
= excnames
[idx
];
10480 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10481 idx
, exc
, cs
->cpu_index
);
10486 * Function used to synchronize QEMU's AArch64 register set with AArch32
10487 * register set. This is necessary when switching between AArch32 and AArch64
10490 void aarch64_sync_32_to_64(CPUARMState
*env
)
10493 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10495 /* We can blanket copy R[0:7] to X[0:7] */
10496 for (i
= 0; i
< 8; i
++) {
10497 env
->xregs
[i
] = env
->regs
[i
];
10501 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10502 * Otherwise, they come from the banked user regs.
10504 if (mode
== ARM_CPU_MODE_FIQ
) {
10505 for (i
= 8; i
< 13; i
++) {
10506 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10509 for (i
= 8; i
< 13; i
++) {
10510 env
->xregs
[i
] = env
->regs
[i
];
10515 * Registers x13-x23 are the various mode SP and FP registers. Registers
10516 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10517 * from the mode banked register.
10519 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10520 env
->xregs
[13] = env
->regs
[13];
10521 env
->xregs
[14] = env
->regs
[14];
10523 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10524 /* HYP is an exception in that it is copied from r14 */
10525 if (mode
== ARM_CPU_MODE_HYP
) {
10526 env
->xregs
[14] = env
->regs
[14];
10528 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10532 if (mode
== ARM_CPU_MODE_HYP
) {
10533 env
->xregs
[15] = env
->regs
[13];
10535 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10538 if (mode
== ARM_CPU_MODE_IRQ
) {
10539 env
->xregs
[16] = env
->regs
[14];
10540 env
->xregs
[17] = env
->regs
[13];
10542 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10543 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10546 if (mode
== ARM_CPU_MODE_SVC
) {
10547 env
->xregs
[18] = env
->regs
[14];
10548 env
->xregs
[19] = env
->regs
[13];
10550 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10551 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10554 if (mode
== ARM_CPU_MODE_ABT
) {
10555 env
->xregs
[20] = env
->regs
[14];
10556 env
->xregs
[21] = env
->regs
[13];
10558 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10559 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10562 if (mode
== ARM_CPU_MODE_UND
) {
10563 env
->xregs
[22] = env
->regs
[14];
10564 env
->xregs
[23] = env
->regs
[13];
10566 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10567 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10571 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10572 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10573 * FIQ bank for r8-r14.
10575 if (mode
== ARM_CPU_MODE_FIQ
) {
10576 for (i
= 24; i
< 31; i
++) {
10577 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10580 for (i
= 24; i
< 29; i
++) {
10581 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10583 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10584 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10587 env
->pc
= env
->regs
[15];
10591 * Function used to synchronize QEMU's AArch32 register set with AArch64
10592 * register set. This is necessary when switching between AArch32 and AArch64
10595 void aarch64_sync_64_to_32(CPUARMState
*env
)
10598 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10600 /* We can blanket copy X[0:7] to R[0:7] */
10601 for (i
= 0; i
< 8; i
++) {
10602 env
->regs
[i
] = env
->xregs
[i
];
10606 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10607 * Otherwise, we copy x8-x12 into the banked user regs.
10609 if (mode
== ARM_CPU_MODE_FIQ
) {
10610 for (i
= 8; i
< 13; i
++) {
10611 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10614 for (i
= 8; i
< 13; i
++) {
10615 env
->regs
[i
] = env
->xregs
[i
];
10620 * Registers r13 & r14 depend on the current mode.
10621 * If we are in a given mode, we copy the corresponding x registers to r13
10622 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10625 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10626 env
->regs
[13] = env
->xregs
[13];
10627 env
->regs
[14] = env
->xregs
[14];
10629 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10632 * HYP is an exception in that it does not have its own banked r14 but
10633 * shares the USR r14
10635 if (mode
== ARM_CPU_MODE_HYP
) {
10636 env
->regs
[14] = env
->xregs
[14];
10638 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10642 if (mode
== ARM_CPU_MODE_HYP
) {
10643 env
->regs
[13] = env
->xregs
[15];
10645 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10648 if (mode
== ARM_CPU_MODE_IRQ
) {
10649 env
->regs
[14] = env
->xregs
[16];
10650 env
->regs
[13] = env
->xregs
[17];
10652 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10653 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10656 if (mode
== ARM_CPU_MODE_SVC
) {
10657 env
->regs
[14] = env
->xregs
[18];
10658 env
->regs
[13] = env
->xregs
[19];
10660 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10661 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10664 if (mode
== ARM_CPU_MODE_ABT
) {
10665 env
->regs
[14] = env
->xregs
[20];
10666 env
->regs
[13] = env
->xregs
[21];
10668 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10669 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10672 if (mode
== ARM_CPU_MODE_UND
) {
10673 env
->regs
[14] = env
->xregs
[22];
10674 env
->regs
[13] = env
->xregs
[23];
10676 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10677 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10681 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10682 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10683 * FIQ bank for r8-r14.
10685 if (mode
== ARM_CPU_MODE_FIQ
) {
10686 for (i
= 24; i
< 31; i
++) {
10687 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10690 for (i
= 24; i
< 29; i
++) {
10691 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10693 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10694 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10697 env
->regs
[15] = env
->pc
;
10700 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10701 uint32_t mask
, uint32_t offset
,
10706 /* Change the CPU state so as to actually take the exception. */
10707 switch_mode(env
, new_mode
);
10710 * For exceptions taken to AArch32 we must clear the SS bit in both
10711 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10713 env
->pstate
&= ~PSTATE_SS
;
10714 env
->spsr
= cpsr_read(env
);
10715 /* Clear IT bits. */
10716 env
->condexec_bits
= 0;
10717 /* Switch to the new mode, and to the correct instruction set. */
10718 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10720 /* This must be after mode switching. */
10721 new_el
= arm_current_el(env
);
10723 /* Set new mode endianness */
10724 env
->uncached_cpsr
&= ~CPSR_E
;
10725 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10726 env
->uncached_cpsr
|= CPSR_E
;
10728 /* J and IL must always be cleared for exception entry */
10729 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10732 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10733 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10734 env
->uncached_cpsr
|= CPSR_SSBS
;
10736 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10740 if (new_mode
== ARM_CPU_MODE_HYP
) {
10741 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10742 env
->elr_el
[2] = env
->regs
[15];
10744 /* CPSR.PAN is normally preserved preserved unless... */
10745 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10748 if (!arm_is_secure_below_el3(env
)) {
10749 /* ... the target is EL3, from non-secure state. */
10750 env
->uncached_cpsr
&= ~CPSR_PAN
;
10753 /* ... the target is EL3, from secure state ... */
10756 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10757 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10758 env
->uncached_cpsr
|= CPSR_PAN
;
10764 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10765 * and we should just guard the thumb mode on V4
10767 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10769 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10771 env
->regs
[14] = env
->regs
[15] + offset
;
10773 env
->regs
[15] = newpc
;
10775 if (tcg_enabled()) {
10776 arm_rebuild_hflags(env
);
10780 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10783 * Handle exception entry to Hyp mode; this is sufficiently
10784 * different to entry to other AArch32 modes that we handle it
10787 * The vector table entry used is always the 0x14 Hyp mode entry point,
10788 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10789 * The offset applied to the preferred return address is always zero
10790 * (see DDI0487C.a section G1.12.3).
10791 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10793 uint32_t addr
, mask
;
10794 ARMCPU
*cpu
= ARM_CPU(cs
);
10795 CPUARMState
*env
= &cpu
->env
;
10797 switch (cs
->exception_index
) {
10805 /* Fall through to prefetch abort. */
10806 case EXCP_PREFETCH_ABORT
:
10807 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10808 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10809 (uint32_t)env
->exception
.vaddress
);
10812 case EXCP_DATA_ABORT
:
10813 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10814 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10815 (uint32_t)env
->exception
.vaddress
);
10827 case EXCP_HYP_TRAP
:
10831 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10834 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10835 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10837 * QEMU syndrome values are v8-style. v7 has the IL bit
10838 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10839 * If this is a v7 CPU, squash the IL bit in those cases.
10841 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10842 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10843 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10844 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10845 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10848 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10851 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10856 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10859 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10862 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10866 addr
+= env
->cp15
.hvbar
;
10868 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10871 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10873 ARMCPU
*cpu
= ARM_CPU(cs
);
10874 CPUARMState
*env
= &cpu
->env
;
10881 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10882 switch (syn_get_ec(env
->exception
.syndrome
)) {
10883 case EC_BREAKPOINT
:
10884 case EC_BREAKPOINT_SAME_EL
:
10887 case EC_WATCHPOINT
:
10888 case EC_WATCHPOINT_SAME_EL
:
10894 case EC_VECTORCATCH
:
10903 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10906 if (env
->exception
.target_el
== 2) {
10907 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10911 switch (cs
->exception_index
) {
10913 new_mode
= ARM_CPU_MODE_UND
;
10923 new_mode
= ARM_CPU_MODE_SVC
;
10926 /* The PC already points to the next instruction. */
10930 /* Fall through to prefetch abort. */
10931 case EXCP_PREFETCH_ABORT
:
10932 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10933 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10934 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10935 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10936 new_mode
= ARM_CPU_MODE_ABT
;
10938 mask
= CPSR_A
| CPSR_I
;
10941 case EXCP_DATA_ABORT
:
10942 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10943 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10944 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10945 env
->exception
.fsr
,
10946 (uint32_t)env
->exception
.vaddress
);
10947 new_mode
= ARM_CPU_MODE_ABT
;
10949 mask
= CPSR_A
| CPSR_I
;
10953 new_mode
= ARM_CPU_MODE_IRQ
;
10955 /* Disable IRQ and imprecise data aborts. */
10956 mask
= CPSR_A
| CPSR_I
;
10958 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10959 /* IRQ routed to monitor mode */
10960 new_mode
= ARM_CPU_MODE_MON
;
10965 new_mode
= ARM_CPU_MODE_FIQ
;
10967 /* Disable FIQ, IRQ and imprecise data aborts. */
10968 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10969 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10970 /* FIQ routed to monitor mode */
10971 new_mode
= ARM_CPU_MODE_MON
;
10976 new_mode
= ARM_CPU_MODE_IRQ
;
10978 /* Disable IRQ and imprecise data aborts. */
10979 mask
= CPSR_A
| CPSR_I
;
10983 new_mode
= ARM_CPU_MODE_FIQ
;
10985 /* Disable FIQ, IRQ and imprecise data aborts. */
10986 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10992 * Note that this is reported as a data abort, but the DFAR
10993 * has an UNKNOWN value. Construct the SError syndrome from
10994 * AET and ExT fields.
10996 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10998 if (extended_addresses_enabled(env
)) {
10999 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
11001 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
11003 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
11004 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11005 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
11006 env
->exception
.fsr
);
11008 new_mode
= ARM_CPU_MODE_ABT
;
11010 mask
= CPSR_A
| CPSR_I
;
11015 new_mode
= ARM_CPU_MODE_MON
;
11017 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11021 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11022 return; /* Never happens. Keep compiler happy. */
11025 if (new_mode
== ARM_CPU_MODE_MON
) {
11026 addr
+= env
->cp15
.mvbar
;
11027 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
11028 /* High vectors. When enabled, base address cannot be remapped. */
11029 addr
+= 0xffff0000;
11032 * ARM v7 architectures provide a vector base address register to remap
11033 * the interrupt vector table.
11034 * This register is only followed in non-monitor mode, and is banked.
11035 * Note: only bits 31:5 are valid.
11037 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
11040 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
11041 env
->cp15
.scr_el3
&= ~SCR_NS
;
11044 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
11047 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
11050 * Return the register number of the AArch64 view of the AArch32
11051 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
11052 * be that of the AArch32 mode the exception came from.
11054 int mode
= env
->uncached_cpsr
& CPSR_M
;
11056 switch (aarch32_reg
) {
11058 return aarch32_reg
;
11060 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
11063 case ARM_CPU_MODE_USR
:
11064 case ARM_CPU_MODE_SYS
:
11066 case ARM_CPU_MODE_HYP
:
11068 case ARM_CPU_MODE_IRQ
:
11070 case ARM_CPU_MODE_SVC
:
11072 case ARM_CPU_MODE_ABT
:
11074 case ARM_CPU_MODE_UND
:
11076 case ARM_CPU_MODE_FIQ
:
11079 g_assert_not_reached();
11083 case ARM_CPU_MODE_USR
:
11084 case ARM_CPU_MODE_SYS
:
11085 case ARM_CPU_MODE_HYP
:
11087 case ARM_CPU_MODE_IRQ
:
11089 case ARM_CPU_MODE_SVC
:
11091 case ARM_CPU_MODE_ABT
:
11093 case ARM_CPU_MODE_UND
:
11095 case ARM_CPU_MODE_FIQ
:
11098 g_assert_not_reached();
11103 g_assert_not_reached();
11107 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11109 uint32_t ret
= cpsr_read(env
);
11111 /* Move DIT to the correct location for SPSR_ELx */
11112 if (ret
& CPSR_DIT
) {
11116 /* Merge PSTATE.SS into SPSR_ELx */
11117 ret
|= env
->pstate
& PSTATE_SS
;
11122 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11124 /* Return true if this syndrome value is a synchronous external abort */
11125 switch (syn_get_ec(syndrome
)) {
11127 case EC_INSNABORT_SAME_EL
:
11129 case EC_DATAABORT_SAME_EL
:
11130 /* Look at fault status code for all the synchronous ext abort cases */
11131 switch (syndrome
& 0x3f) {
11147 /* Handle exception entry to a target EL which is using AArch64 */
11148 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11150 ARMCPU
*cpu
= ARM_CPU(cs
);
11151 CPUARMState
*env
= &cpu
->env
;
11152 unsigned int new_el
= env
->exception
.target_el
;
11153 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11154 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11155 unsigned int old_mode
;
11156 unsigned int cur_el
= arm_current_el(env
);
11159 if (tcg_enabled()) {
11161 * Note that new_el can never be 0. If cur_el is 0, then
11162 * el0_a64 is is_a64(), else el0_a64 is ignored.
11164 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11167 if (cur_el
< new_el
) {
11169 * Entry vector offset depends on whether the implemented EL
11170 * immediately lower than the target level is using AArch32 or AArch64
11177 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11180 hcr
= arm_hcr_el2_eff(env
);
11181 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11182 is_aa64
= (hcr
& HCR_RW
) != 0;
11187 is_aa64
= is_a64(env
);
11190 g_assert_not_reached();
11198 } else if (pstate_read(env
) & PSTATE_SP
) {
11202 switch (cs
->exception_index
) {
11204 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11205 env
->cp15
.mfar_el3
);
11207 case EXCP_PREFETCH_ABORT
:
11208 case EXCP_DATA_ABORT
:
11210 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11211 * to be taken to the SError vector entrypoint.
11213 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11214 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11217 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11218 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11219 env
->cp15
.far_el
[new_el
]);
11225 case EXCP_HYP_TRAP
:
11227 switch (syn_get_ec(env
->exception
.syndrome
)) {
11228 case EC_ADVSIMDFPACCESSTRAP
:
11230 * QEMU internal FP/SIMD syndromes from AArch32 include the
11231 * TA and coproc fields which are only exposed if the exception
11232 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11233 * AArch64 format syndrome.
11235 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11237 case EC_CP14RTTRAP
:
11238 case EC_CP15RTTRAP
:
11239 case EC_CP14DTTRAP
:
11241 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11242 * the raw register field from the insn; when taking this to
11243 * AArch64 we must convert it to the AArch64 view of the register
11244 * number. Notice that we read a 4-bit AArch32 register number and
11245 * write back a 5-bit AArch64 one.
11247 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11248 rt
= aarch64_regnum(env
, rt
);
11249 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11252 case EC_CP15RRTTRAP
:
11253 case EC_CP14RRTTRAP
:
11254 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11255 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11256 rt
= aarch64_regnum(env
, rt
);
11257 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11259 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11260 rt
= aarch64_regnum(env
, rt
);
11261 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11265 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11277 /* Construct the SError syndrome from IDS and ISS fields. */
11278 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11279 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11282 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11286 old_mode
= pstate_read(env
);
11287 aarch64_save_sp(env
, arm_current_el(env
));
11288 env
->elr_el
[new_el
] = env
->pc
;
11290 if (cur_el
== 1 && new_el
== 1 &&
11291 ((arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
)) == HCR_NV
)) {
11292 /* I_ZJRNN: report EL2 in the SPSR by setting M[3:2] to 0b10 */
11293 old_mode
= deposit32(old_mode
, 2, 2, 2);
11296 old_mode
= cpsr_read_for_spsr_elx(env
);
11297 env
->elr_el
[new_el
] = env
->regs
[15];
11299 aarch64_sync_32_to_64(env
);
11301 env
->condexec_bits
= 0;
11303 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11305 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11306 env
->elr_el
[new_el
]);
11308 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11309 /* The value of PSTATE.PAN is normally preserved, except when ... */
11310 new_mode
|= old_mode
& PSTATE_PAN
;
11313 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11314 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11315 != (HCR_E2H
| HCR_TGE
)) {
11320 /* ... the target is EL1 ... */
11321 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11322 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11323 new_mode
|= PSTATE_PAN
;
11328 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11329 new_mode
|= PSTATE_TCO
;
11332 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11333 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11334 new_mode
|= PSTATE_SSBS
;
11336 new_mode
&= ~PSTATE_SSBS
;
11340 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11341 env
->aarch64
= true;
11342 aarch64_restore_sp(env
, new_el
);
11344 if (tcg_enabled()) {
11345 helper_rebuild_hflags_a64(env
, new_el
);
11350 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11351 new_el
, env
->pc
, pstate_read(env
));
11355 * Do semihosting call and set the appropriate return value. All the
11356 * permission and validity checks have been done at translate time.
11358 * We only see semihosting exceptions in TCG only as they are not
11359 * trapped to the hypervisor in KVM.
11362 static void tcg_handle_semihosting(CPUState
*cs
)
11364 ARMCPU
*cpu
= ARM_CPU(cs
);
11365 CPUARMState
*env
= &cpu
->env
;
11368 qemu_log_mask(CPU_LOG_INT
,
11369 "...handling as semihosting call 0x%" PRIx64
"\n",
11371 do_common_semihosting(cs
);
11374 qemu_log_mask(CPU_LOG_INT
,
11375 "...handling as semihosting call 0x%x\n",
11377 do_common_semihosting(cs
);
11378 env
->regs
[15] += env
->thumb
? 2 : 4;
11384 * Handle a CPU exception for A and R profile CPUs.
11385 * Do any appropriate logging, handle PSCI calls, and then hand off
11386 * to the AArch64-entry or AArch32-entry function depending on the
11387 * target exception level's register width.
11389 * Note: this is used for both TCG (as the do_interrupt tcg op),
11390 * and KVM to re-inject guest debug exceptions, and to
11391 * inject a Synchronous-External-Abort.
11393 void arm_cpu_do_interrupt(CPUState
*cs
)
11395 ARMCPU
*cpu
= ARM_CPU(cs
);
11396 CPUARMState
*env
= &cpu
->env
;
11397 unsigned int new_el
= env
->exception
.target_el
;
11399 assert(!arm_feature(env
, ARM_FEATURE_M
));
11401 arm_log_exception(cs
);
11402 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11404 if (qemu_loglevel_mask(CPU_LOG_INT
)
11405 && !excp_is_internal(cs
->exception_index
)) {
11406 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11407 syn_get_ec(env
->exception
.syndrome
),
11408 env
->exception
.syndrome
);
11411 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11412 arm_handle_psci_call(cpu
);
11413 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11418 * Semihosting semantics depend on the register width of the code
11419 * that caused the exception, not the target exception level, so
11420 * must be handled here.
11423 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11424 tcg_handle_semihosting(cs
);
11430 * Hooks may change global state so BQL should be held, also the
11431 * BQL needs to be held for any modification of
11432 * cs->interrupt_request.
11434 g_assert(bql_locked());
11436 arm_call_pre_el_change_hook(cpu
);
11438 assert(!excp_is_internal(cs
->exception_index
));
11439 if (arm_el_is_aa64(env
, new_el
)) {
11440 arm_cpu_do_interrupt_aarch64(cs
);
11442 arm_cpu_do_interrupt_aarch32(cs
);
11445 arm_call_el_change_hook(cpu
);
11447 if (!kvm_enabled()) {
11448 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11451 #endif /* !CONFIG_USER_ONLY */
11453 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11455 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11457 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11458 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11460 return env
->cp15
.sctlr_el
[el
];
11463 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11465 if (regime_has_2_ranges(mmu_idx
)) {
11466 return extract64(tcr
, 37, 2);
11467 } else if (regime_is_stage2(mmu_idx
)) {
11468 return 0; /* VTCR_EL2 */
11470 /* Replicate the single TBI bit so we always have 2 bits. */
11471 return extract32(tcr
, 20, 1) * 3;
11475 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11477 if (regime_has_2_ranges(mmu_idx
)) {
11478 return extract64(tcr
, 51, 2);
11479 } else if (regime_is_stage2(mmu_idx
)) {
11480 return 0; /* VTCR_EL2 */
11482 /* Replicate the single TBID bit so we always have 2 bits. */
11483 return extract32(tcr
, 29, 1) * 3;
11487 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11489 if (regime_has_2_ranges(mmu_idx
)) {
11490 return extract64(tcr
, 57, 2);
11492 /* Replicate the single TCMA bit so we always have 2 bits. */
11493 return extract32(tcr
, 30, 1) * 3;
11497 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11507 return GranInvalid
;
11511 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11521 return GranInvalid
;
11525 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11527 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11528 : cpu_isar_feature(aa64_tgran4
, cpu
);
11531 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11533 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11534 : cpu_isar_feature(aa64_tgran16
, cpu
);
11537 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11539 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11540 : cpu_isar_feature(aa64_tgran64
, cpu
);
11543 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11548 if (have4k(cpu
, stage2
)) {
11553 if (have16k(cpu
, stage2
)) {
11558 if (have64k(cpu
, stage2
)) {
11566 * If the guest selects a granule size that isn't implemented,
11567 * the architecture requires that we behave as if it selected one
11568 * that is (with an IMPDEF choice of which one to pick). We choose
11569 * to implement the smallest supported granule size.
11571 if (have4k(cpu
, stage2
)) {
11574 if (have16k(cpu
, stage2
)) {
11577 assert(have64k(cpu
, stage2
));
11581 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11582 ARMMMUIdx mmu_idx
, bool data
,
11585 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11586 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11587 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11588 ARMGranuleSize gran
;
11589 ARMCPU
*cpu
= env_archcpu(env
);
11590 bool stage2
= regime_is_stage2(mmu_idx
);
11592 if (!regime_has_2_ranges(mmu_idx
)) {
11594 tsz
= extract32(tcr
, 0, 6);
11595 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11600 hpd
= extract32(tcr
, 24, 1);
11603 sh
= extract32(tcr
, 12, 2);
11604 ps
= extract32(tcr
, 16, 3);
11605 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11606 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11607 ds
= extract64(tcr
, 32, 1);
11612 * Bit 55 is always between the two regions, and is canonical for
11613 * determining if address tagging is enabled.
11615 select
= extract64(va
, 55, 1);
11617 tsz
= extract32(tcr
, 0, 6);
11618 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11619 epd
= extract32(tcr
, 7, 1);
11620 sh
= extract32(tcr
, 12, 2);
11621 hpd
= extract64(tcr
, 41, 1);
11622 e0pd
= extract64(tcr
, 55, 1);
11624 tsz
= extract32(tcr
, 16, 6);
11625 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11626 epd
= extract32(tcr
, 23, 1);
11627 sh
= extract32(tcr
, 28, 2);
11628 hpd
= extract64(tcr
, 42, 1);
11629 e0pd
= extract64(tcr
, 56, 1);
11631 ps
= extract64(tcr
, 32, 3);
11632 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11633 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11634 ds
= extract64(tcr
, 59, 1);
11636 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11637 regime_is_user(env
, mmu_idx
)) {
11642 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11644 if (cpu_isar_feature(aa64_st
, cpu
)) {
11645 max_tsz
= 48 - (gran
== Gran64K
);
11651 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11652 * adjust the effective value of DS, as documented.
11655 if (gran
== Gran64K
) {
11656 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11661 if (regime_is_stage2(mmu_idx
)) {
11662 if (gran
== Gran16K
) {
11663 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11665 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11668 if (gran
== Gran16K
) {
11669 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11671 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11679 if (stage2
&& el1_is_aa32
) {
11681 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11682 * are loosened: a configured IPA of 40 bits is permitted even if
11683 * the implemented PA is less than that (and so a 40 bit IPA would
11684 * fault for an AArch64 EL1). See R_DTLMN.
11686 min_tsz
= MIN(min_tsz
, 24);
11689 if (tsz
> max_tsz
) {
11692 } else if (tsz
< min_tsz
) {
11699 /* Present TBI as a composite with TBID. */
11700 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11702 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11704 tbi
= (tbi
>> select
) & 1;
11706 return (ARMVAParameters
) {
11714 .tsz_oob
= tsz_oob
,
11723 * Note that signed overflow is undefined in C. The following routines are
11724 * careful to use unsigned types where modulo arithmetic is required.
11725 * Failure to do so _will_ break on newer gcc.
11728 /* Signed saturating arithmetic. */
11730 /* Perform 16-bit signed saturating addition. */
11731 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11736 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11746 /* Perform 8-bit signed saturating addition. */
11747 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11752 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11762 /* Perform 16-bit signed saturating subtraction. */
11763 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11768 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11778 /* Perform 8-bit signed saturating subtraction. */
11779 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11784 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11794 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11795 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11796 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11797 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11800 #include "op_addsub.h"
11802 /* Unsigned saturating arithmetic. */
11803 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11813 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11822 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11832 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11841 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11842 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11843 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11844 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11847 #include "op_addsub.h"
11849 /* Signed modulo arithmetic. */
11850 #define SARITH16(a, b, n, op) do { \
11852 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11853 RESULT(sum, n, 16); \
11855 ge |= 3 << (n * 2); \
11858 #define SARITH8(a, b, n, op) do { \
11860 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11861 RESULT(sum, n, 8); \
11867 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11868 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11869 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11870 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11874 #include "op_addsub.h"
11876 /* Unsigned modulo arithmetic. */
11877 #define ADD16(a, b, n) do { \
11879 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11880 RESULT(sum, n, 16); \
11881 if ((sum >> 16) == 1) \
11882 ge |= 3 << (n * 2); \
11885 #define ADD8(a, b, n) do { \
11887 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11888 RESULT(sum, n, 8); \
11889 if ((sum >> 8) == 1) \
11893 #define SUB16(a, b, n) do { \
11895 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11896 RESULT(sum, n, 16); \
11897 if ((sum >> 16) == 0) \
11898 ge |= 3 << (n * 2); \
11901 #define SUB8(a, b, n) do { \
11903 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11904 RESULT(sum, n, 8); \
11905 if ((sum >> 8) == 0) \
11912 #include "op_addsub.h"
11914 /* Halved signed arithmetic. */
11915 #define ADD16(a, b, n) \
11916 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11917 #define SUB16(a, b, n) \
11918 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11919 #define ADD8(a, b, n) \
11920 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11921 #define SUB8(a, b, n) \
11922 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11925 #include "op_addsub.h"
11927 /* Halved unsigned arithmetic. */
11928 #define ADD16(a, b, n) \
11929 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11930 #define SUB16(a, b, n) \
11931 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11932 #define ADD8(a, b, n) \
11933 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11934 #define SUB8(a, b, n) \
11935 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11938 #include "op_addsub.h"
11940 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11949 /* Unsigned sum of absolute byte differences. */
11950 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11953 sum
= do_usad(a
, b
);
11954 sum
+= do_usad(a
>> 8, b
>> 8);
11955 sum
+= do_usad(a
>> 16, b
>> 16);
11956 sum
+= do_usad(a
>> 24, b
>> 24);
11960 /* For ARMv6 SEL instruction. */
11961 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11976 mask
|= 0xff000000;
11978 return (a
& mask
) | (b
& ~mask
);
11983 * The upper bytes of val (above the number specified by 'bytes') must have
11984 * been zeroed out by the caller.
11986 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11990 stl_le_p(buf
, val
);
11992 /* zlib crc32 converts the accumulator and output to one's complement. */
11993 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11996 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12000 stl_le_p(buf
, val
);
12002 /* Linux crc32c converts the output to one's complement. */
12003 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12007 * Return the exception level to which FP-disabled exceptions should
12008 * be taken, or 0 if FP is enabled.
12010 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12012 #ifndef CONFIG_USER_ONLY
12016 * CPACR and the CPTR registers don't exist before v6, so FP is
12017 * always accessible
12019 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12023 if (arm_feature(env
, ARM_FEATURE_M
)) {
12024 /* CPACR can cause a NOCP UsageFault taken to current security state */
12025 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12029 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12030 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12031 /* FP insns cause a NOCP UsageFault taken to Secure */
12039 hcr_el2
= arm_hcr_el2_eff(env
);
12042 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12043 * 0, 2 : trap EL0 and EL1/PL1 accesses
12044 * 1 : trap only EL0 accesses
12045 * 3 : trap no accesses
12046 * This register is ignored if E2H+TGE are both set.
12048 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12049 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
12059 /* Trap from Secure PL0 or PL1 to Secure PL1. */
12060 if (!arm_el_is_aa64(env
, 3)
12061 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
12072 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12073 * to control non-secure access to the FPU. It doesn't have any
12074 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12076 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12077 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12078 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12079 /* FP insns act as UNDEF */
12080 return cur_el
== 2 ? 2 : 1;
12085 * CPTR_EL2 is present in v7VE or v8, and changes format
12086 * with HCR_EL2.E2H (regardless of TGE).
12089 if (hcr_el2
& HCR_E2H
) {
12090 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
12092 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
12100 } else if (arm_is_el2_enabled(env
)) {
12101 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
12107 /* CPTR_EL3 : present in v8 */
12108 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
12109 /* Trap all FP ops to EL3 */
12116 /* Return the exception level we're running at if this is our mmu_idx */
12117 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12119 if (mmu_idx
& ARM_MMU_IDX_M
) {
12120 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12124 case ARMMMUIdx_E10_0
:
12125 case ARMMMUIdx_E20_0
:
12127 case ARMMMUIdx_E10_1
:
12128 case ARMMMUIdx_E10_1_PAN
:
12131 case ARMMMUIdx_E20_2
:
12132 case ARMMMUIdx_E20_2_PAN
:
12137 g_assert_not_reached();
12142 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12144 g_assert_not_reached();
12148 static bool arm_pan_enabled(CPUARMState
*env
)
12151 return env
->pstate
& PSTATE_PAN
;
12153 return env
->uncached_cpsr
& CPSR_PAN
;
12157 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12162 if (arm_feature(env
, ARM_FEATURE_M
)) {
12163 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12166 /* See ARM pseudo-function ELIsInHost. */
12169 hcr
= arm_hcr_el2_eff(env
);
12170 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12171 idx
= ARMMMUIdx_E20_0
;
12173 idx
= ARMMMUIdx_E10_0
;
12177 if (arm_pan_enabled(env
)) {
12178 idx
= ARMMMUIdx_E10_1_PAN
;
12180 idx
= ARMMMUIdx_E10_1
;
12184 /* Note that TGE does not apply at EL2. */
12185 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12186 if (arm_pan_enabled(env
)) {
12187 idx
= ARMMMUIdx_E20_2_PAN
;
12189 idx
= ARMMMUIdx_E20_2
;
12192 idx
= ARMMMUIdx_E2
;
12196 return ARMMMUIdx_E3
;
12198 g_assert_not_reached();
12204 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12206 return arm_mmu_idx_el(env
, arm_current_el(env
));
12209 static bool mve_no_pred(CPUARMState
*env
)
12212 * Return true if there is definitely no predication of MVE
12213 * instructions by VPR or LTPSIZE. (Returning false even if there
12214 * isn't any predication is OK; generated code will just be
12216 * If the CPU does not implement MVE then this TB flag is always 0.
12218 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12219 * logic in gen_update_fp_context() needs to be updated to match.
12221 * We do not include the effect of the ECI bits here -- they are
12222 * tracked in other TB flags. This simplifies the logic for
12223 * "when did we emit code that changes the MVE_NO_PRED TB flag
12224 * and thus need to end the TB?".
12226 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12229 if (env
->v7m
.vpr
) {
12232 if (env
->v7m
.ltpsize
< 4) {
12238 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12239 uint64_t *cs_base
, uint32_t *pflags
)
12241 CPUARMTBFlags flags
;
12243 assert_hflags_rebuild_correctly(env
);
12244 flags
= env
->hflags
;
12246 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12248 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12249 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12252 *pc
= env
->regs
[15];
12254 if (arm_feature(env
, ARM_FEATURE_M
)) {
12255 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12256 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12257 != env
->v7m
.secure
) {
12258 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12261 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12262 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12263 (env
->v7m
.secure
&&
12264 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12266 * ASPEN is set, but FPCA/SFPA indicate that there is no
12267 * active FP context; we must create a new FP context before
12268 * executing any FP insn.
12270 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12273 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12274 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12275 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12278 if (mve_no_pred(env
)) {
12279 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12283 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12284 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12286 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12287 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12289 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12290 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12292 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12293 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12297 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12298 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12302 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12303 * states defined in the ARM ARM for software singlestep:
12304 * SS_ACTIVE PSTATE.SS State
12305 * 0 x Inactive (the TB flag for SS is always 0)
12306 * 1 0 Active-pending
12307 * 1 1 Active-not-pending
12308 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12310 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12311 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12314 *pflags
= flags
.flags
;
12315 *cs_base
= flags
.flags2
;
12318 #ifdef TARGET_AARCH64
12320 * The manual says that when SVE is enabled and VQ is widened the
12321 * implementation is allowed to zero the previously inaccessible
12322 * portion of the registers. The corollary to that is that when
12323 * SVE is enabled and VQ is narrowed we are also allowed to zero
12324 * the now inaccessible portion of the registers.
12326 * The intent of this is that no predicate bit beyond VQ is ever set.
12327 * Which means that some operations on predicate registers themselves
12328 * may operate on full uint64_t or even unrolled across the maximum
12329 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12330 * may well be cheaper than conditionals to restrict the operation
12331 * to the relevant portion of a uint16_t[16].
12333 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12338 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12339 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12341 /* Zap the high bits of the zregs. */
12342 for (i
= 0; i
< 32; i
++) {
12343 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12346 /* Zap the high bits of the pregs and ffr. */
12349 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12351 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12352 for (i
= 0; i
< 17; ++i
) {
12353 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12359 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12364 exc_el
= sme_exception_el(env
, el
);
12366 exc_el
= sve_exception_el(env
, el
);
12369 return 0; /* disabled */
12371 return sve_vqm1_for_el_sm(env
, el
, sm
);
12375 * Notice a change in SVE vector size when changing EL.
12377 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12378 int new_el
, bool el0_a64
)
12380 ARMCPU
*cpu
= env_archcpu(env
);
12381 int old_len
, new_len
;
12382 bool old_a64
, new_a64
, sm
;
12384 /* Nothing to do if no SVE. */
12385 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12389 /* Nothing to do if FP is disabled in either EL. */
12390 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12394 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12395 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12398 * Both AArch64.TakeException and AArch64.ExceptionReturn
12399 * invoke ResetSVEState when taking an exception from, or
12400 * returning to, AArch32 state when PSTATE.SM is enabled.
12402 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12403 if (old_a64
!= new_a64
&& sm
) {
12404 arm_reset_sve_state(env
);
12409 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12410 * at ELx, or not available because the EL is in AArch32 state, then
12411 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12412 * has an effective value of 0".
12414 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12415 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12416 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12417 * we already have the correct register contents when encountering the
12418 * vq0->vq0 transition between EL0->EL1.
12420 old_len
= new_len
= 0;
12422 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12425 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12428 /* When changing vector length, clear inaccessible state. */
12429 if (new_len
< old_len
) {
12430 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12435 #ifndef CONFIG_USER_ONLY
12436 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12438 if (arm_feature(env
, ARM_FEATURE_M
)) {
12439 return arm_secure_to_space(env
->v7m
.secure
);
12443 * If EL3 is not supported then the secure state is implementation
12444 * defined, in which case QEMU defaults to non-secure.
12446 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12447 return ARMSS_NonSecure
;
12450 /* Check for AArch64 EL3 or AArch32 Mon. */
12452 if (extract32(env
->pstate
, 2, 2) == 3) {
12453 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12456 return ARMSS_Secure
;
12460 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12461 return ARMSS_Secure
;
12465 return arm_security_space_below_el3(env
);
12468 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12470 assert(!arm_feature(env
, ARM_FEATURE_M
));
12473 * If EL3 is not supported then the secure state is implementation
12474 * defined, in which case QEMU defaults to non-secure.
12476 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12477 return ARMSS_NonSecure
;
12481 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12482 * Ignoring NSE when !NS retains consistency without having to
12483 * modify other predicates.
12485 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12486 return ARMSS_Secure
;
12487 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12488 return ARMSS_Realm
;
12490 return ARMSS_NonSecure
;
12493 #endif /* !CONFIG_USER_ONLY */