4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
267 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
269 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
270 const ARMCPRegInfo
*ri
,
273 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
274 arm_is_secure_below_el3(env
)) {
275 return CP_ACCESS_TRAP_UNCATEGORIZED
;
281 * Some secure-only AArch32 registers trap to EL3 if used from
282 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
283 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
284 * We assume that the .access field is set to PL1_RW.
286 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
287 const ARMCPRegInfo
*ri
,
290 if (arm_current_el(env
) == 3) {
293 if (arm_is_secure_below_el3(env
)) {
294 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
295 return CP_ACCESS_TRAP_EL2
;
297 return CP_ACCESS_TRAP_EL3
;
299 /* This will be EL1 NS and EL2 NS, which just UNDEF */
300 return CP_ACCESS_TRAP_UNCATEGORIZED
;
304 * Check for traps to performance monitor registers, which are controlled
305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
307 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
310 int el
= arm_current_el(env
);
311 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
313 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
314 return CP_ACCESS_TRAP_EL2
;
316 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
317 return CP_ACCESS_TRAP_EL3
;
322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
323 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
326 if (arm_current_el(env
) == 1) {
327 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
328 if (arm_hcr_el2_eff(env
) & trap
) {
329 return CP_ACCESS_TRAP_EL2
;
335 /* Check for traps from EL1 due to HCR_EL2.TSW. */
336 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
340 return CP_ACCESS_TRAP_EL2
;
345 /* Check for traps from EL1 due to HCR_EL2.TACR. */
346 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
349 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
350 return CP_ACCESS_TRAP_EL2
;
355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
356 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
359 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
360 return CP_ACCESS_TRAP_EL2
;
365 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
366 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
369 if (arm_current_el(env
) == 1 &&
370 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
371 return CP_ACCESS_TRAP_EL2
;
376 #ifdef TARGET_AARCH64
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
378 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
383 return CP_ACCESS_TRAP_EL2
;
389 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
391 ARMCPU
*cpu
= env_archcpu(env
);
393 raw_write(env
, ri
, value
);
394 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
397 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
399 ARMCPU
*cpu
= env_archcpu(env
);
401 if (raw_read(env
, ri
) != value
) {
403 * Unlike real hardware the qemu TLB uses virtual addresses,
404 * not modified virtual addresses, so this causes a TLB flush.
407 raw_write(env
, ri
, value
);
411 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 ARMCPU
*cpu
= env_archcpu(env
);
416 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
417 && !extended_addresses_enabled(env
)) {
419 * For VMSA (when not using the LPAE long descriptor page table
420 * format) this register includes the ASID, so do a TLB flush.
421 * For PMSA it is purely a process ID and no action is needed.
425 raw_write(env
, ri
, value
);
428 static int alle1_tlbmask(CPUARMState
*env
)
431 * Note that the 'ALL' scope must invalidate both stage 1 and
432 * stage 2 translations, whereas most other scopes only invalidate
433 * stage 1 translations.
435 return (ARMMMUIdxBit_E10_1
|
436 ARMMMUIdxBit_E10_1_PAN
|
438 ARMMMUIdxBit_Stage2
|
439 ARMMMUIdxBit_Stage2_S
);
443 /* IS variants of TLB operations must affect all cores */
444 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
447 CPUState
*cs
= env_cpu(env
);
449 tlb_flush_all_cpus_synced(cs
);
452 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 CPUState
*cs
= env_cpu(env
);
457 tlb_flush_all_cpus_synced(cs
);
460 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
463 CPUState
*cs
= env_cpu(env
);
465 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
468 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
471 CPUState
*cs
= env_cpu(env
);
473 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
477 * Non-IS variants of TLB operations are upgraded to
478 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
479 * force broadcast of these operations.
481 static bool tlb_force_broadcast(CPUARMState
*env
)
483 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
486 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
489 /* Invalidate all (TLBIALL) */
490 CPUState
*cs
= env_cpu(env
);
492 if (tlb_force_broadcast(env
)) {
493 tlb_flush_all_cpus_synced(cs
);
499 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
503 CPUState
*cs
= env_cpu(env
);
505 value
&= TARGET_PAGE_MASK
;
506 if (tlb_force_broadcast(env
)) {
507 tlb_flush_page_all_cpus_synced(cs
, value
);
509 tlb_flush_page(cs
, value
);
513 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
516 /* Invalidate by ASID (TLBIASID) */
517 CPUState
*cs
= env_cpu(env
);
519 if (tlb_force_broadcast(env
)) {
520 tlb_flush_all_cpus_synced(cs
);
526 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530 CPUState
*cs
= env_cpu(env
);
532 value
&= TARGET_PAGE_MASK
;
533 if (tlb_force_broadcast(env
)) {
534 tlb_flush_page_all_cpus_synced(cs
, value
);
536 tlb_flush_page(cs
, value
);
540 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
543 CPUState
*cs
= env_cpu(env
);
545 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
548 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
551 CPUState
*cs
= env_cpu(env
);
553 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
557 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
560 CPUState
*cs
= env_cpu(env
);
562 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
565 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= env_cpu(env
);
570 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
573 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 CPUState
*cs
= env_cpu(env
);
577 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
579 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
582 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
585 CPUState
*cs
= env_cpu(env
);
586 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
588 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
592 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
595 CPUState
*cs
= env_cpu(env
);
596 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
598 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
601 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
604 CPUState
*cs
= env_cpu(env
);
605 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
607 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
610 static const ARMCPRegInfo cp_reginfo
[] = {
612 * Define the secure and non-secure FCSE identifier CP registers
613 * separately because there is no secure bank in V8 (no _EL3). This allows
614 * the secure register to be properly reset and migrated. There is also no
615 * v8 EL1 version of the register so the non-secure instance stands alone.
618 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
619 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
620 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
621 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
622 { .name
= "FCSEIDR_S",
623 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
624 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
625 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
626 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
628 * Define the secure and non-secure context identifier CP registers
629 * separately because there is no secure bank in V8 (no _EL3). This allows
630 * the secure register to be properly reset and migrated. In the
631 * non-secure case, the 32-bit register will have reset and migration
632 * disabled during registration as it is handled by the 64-bit instance.
634 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
635 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
636 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
637 .fgt
= FGT_CONTEXTIDR_EL1
,
638 .secure
= ARM_CP_SECSTATE_NS
,
639 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
640 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
641 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
642 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
643 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
644 .secure
= ARM_CP_SECSTATE_S
,
645 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
646 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
649 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
651 * NB: Some of these registers exist in v8 but with more precise
652 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
654 /* MMU Domain access control / MPU write buffer control */
656 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
657 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
658 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
659 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
660 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
662 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
663 * For v6 and v5, these mappings are overly broad.
665 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
666 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
667 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
668 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
669 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
670 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
671 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
672 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
673 /* Cache maintenance ops; some of this space may be overridden later. */
674 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
675 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
676 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
679 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
681 * Not all pre-v6 cores implemented this WFI, so this is slightly
684 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
685 .access
= PL1_W
, .type
= ARM_CP_WFI
},
688 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
690 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
691 * is UNPREDICTABLE; we choose to NOP as most implementations do).
693 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
694 .access
= PL1_W
, .type
= ARM_CP_WFI
},
696 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
697 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
698 * OMAPCP will override this space.
700 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
701 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
703 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
704 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
706 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
707 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
708 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
711 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
712 * implementing it as RAZ means the "debug architecture version" bits
713 * will read as a reserved value, which should cause Linux to not try
714 * to use the debug hardware.
716 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
717 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
719 * MMU TLB control. Note that the wildcarding means we cover not just
720 * the unified TLB ops but also the dside/iside/inner-shareable variants.
722 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
723 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
724 .type
= ARM_CP_NO_RAW
},
725 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
726 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
727 .type
= ARM_CP_NO_RAW
},
728 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
729 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
730 .type
= ARM_CP_NO_RAW
},
731 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
732 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
733 .type
= ARM_CP_NO_RAW
},
734 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
735 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
736 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
737 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
740 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
745 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
746 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
748 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
749 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
750 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
752 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
753 /* VFP coprocessor: cp10 & cp11 [23:20] */
754 mask
|= R_CPACR_ASEDIS_MASK
|
755 R_CPACR_D32DIS_MASK
|
759 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
760 /* ASEDIS [31] bit is RAO/WI */
761 value
|= R_CPACR_ASEDIS_MASK
;
765 * VFPv3 and upwards with NEON implement 32 double precision
766 * registers (D0-D31).
768 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
769 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
770 value
|= R_CPACR_D32DIS_MASK
;
777 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
778 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
780 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
781 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
782 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
783 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
786 env
->cp15
.cpacr_el1
= value
;
789 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
792 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
793 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
795 uint64_t value
= env
->cp15
.cpacr_el1
;
797 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
798 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
799 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
805 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
808 * Call cpacr_write() so that we reset with the correct RAO bits set
809 * for our CPU features.
811 cpacr_write(env
, ri
, 0);
814 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 if (arm_feature(env
, ARM_FEATURE_V8
)) {
818 /* Check if CPACR accesses are to be trapped to EL2 */
819 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
820 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
821 return CP_ACCESS_TRAP_EL2
;
822 /* Check if CPACR accesses are to be trapped to EL3 */
823 } else if (arm_current_el(env
) < 3 &&
824 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
825 return CP_ACCESS_TRAP_EL3
;
832 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 /* Check if CPTR accesses are set to trap to EL3 */
836 if (arm_current_el(env
) == 2 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
844 static const ARMCPRegInfo v6_cp_reginfo
[] = {
845 /* prefetch by MVA in v6, NOP in v7 */
846 { .name
= "MVA_prefetch",
847 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
850 * We need to break the TB after ISB to execute self-modifying code
851 * correctly and also to take any pending interrupts immediately.
852 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
854 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
855 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
856 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
857 .access
= PL0_W
, .type
= ARM_CP_NOP
},
858 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
859 .access
= PL0_W
, .type
= ARM_CP_NOP
},
860 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
861 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
862 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
863 offsetof(CPUARMState
, cp15
.ifar_ns
) },
866 * Watchpoint Fault Address Register : should actually only be present
867 * for 1136, 1176, 11MPCore.
869 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
870 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
871 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
872 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
873 .fgt
= FGT_CPACR_EL1
,
874 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
875 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
878 typedef struct pm_event
{
879 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
880 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
881 bool (*supported
)(CPUARMState
*);
883 * Retrieve the current count of the underlying event. The programmed
884 * counters hold a difference from the return value from this function
886 uint64_t (*get_count
)(CPUARMState
*);
888 * Return how many nanoseconds it will take (at a minimum) for count events
889 * to occur. A negative value indicates the counter will never overflow, or
890 * that the counter has otherwise arranged for the overflow bit to be set
891 * and the PMU interrupt to be raised on overflow.
893 int64_t (*ns_per_count
)(uint64_t);
896 static bool event_always_supported(CPUARMState
*env
)
901 static uint64_t swinc_get_count(CPUARMState
*env
)
904 * SW_INCR events are written directly to the pmevcntr's by writes to
905 * PMSWINC, so there is no underlying count maintained by the PMU itself
910 static int64_t swinc_ns_per(uint64_t ignored
)
916 * Return the underlying cycle count for the PMU cycle counters. If we're in
917 * usermode, simply return 0.
919 static uint64_t cycles_get_count(CPUARMState
*env
)
921 #ifndef CONFIG_USER_ONLY
922 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
923 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
925 return cpu_get_host_ticks();
929 #ifndef CONFIG_USER_ONLY
930 static int64_t cycles_ns_per(uint64_t cycles
)
932 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
935 static bool instructions_supported(CPUARMState
*env
)
937 return icount_enabled() == 1; /* Precise instruction counting */
940 static uint64_t instructions_get_count(CPUARMState
*env
)
942 return (uint64_t)icount_get_raw();
945 static int64_t instructions_ns_per(uint64_t icount
)
947 return icount_to_ns((int64_t)icount
);
951 static bool pmuv3p1_events_supported(CPUARMState
*env
)
953 /* For events which are supported in any v8.1 PMU */
954 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
957 static bool pmuv3p4_events_supported(CPUARMState
*env
)
959 /* For events which are supported in any v8.1 PMU */
960 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
963 static uint64_t zero_event_get_count(CPUARMState
*env
)
965 /* For events which on QEMU never fire, so their count is always zero */
969 static int64_t zero_event_ns_per(uint64_t cycles
)
971 /* An event which never fires can never overflow */
975 static const pm_event pm_events
[] = {
976 { .number
= 0x000, /* SW_INCR */
977 .supported
= event_always_supported
,
978 .get_count
= swinc_get_count
,
979 .ns_per_count
= swinc_ns_per
,
981 #ifndef CONFIG_USER_ONLY
982 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
983 .supported
= instructions_supported
,
984 .get_count
= instructions_get_count
,
985 .ns_per_count
= instructions_ns_per
,
987 { .number
= 0x011, /* CPU_CYCLES, Cycle */
988 .supported
= event_always_supported
,
989 .get_count
= cycles_get_count
,
990 .ns_per_count
= cycles_ns_per
,
993 { .number
= 0x023, /* STALL_FRONTEND */
994 .supported
= pmuv3p1_events_supported
,
995 .get_count
= zero_event_get_count
,
996 .ns_per_count
= zero_event_ns_per
,
998 { .number
= 0x024, /* STALL_BACKEND */
999 .supported
= pmuv3p1_events_supported
,
1000 .get_count
= zero_event_get_count
,
1001 .ns_per_count
= zero_event_ns_per
,
1003 { .number
= 0x03c, /* STALL */
1004 .supported
= pmuv3p4_events_supported
,
1005 .get_count
= zero_event_get_count
,
1006 .ns_per_count
= zero_event_ns_per
,
1011 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1012 * events (i.e. the statistical profiling extension), this implementation
1013 * should first be updated to something sparse instead of the current
1014 * supported_event_map[] array.
1016 #define MAX_EVENT_ID 0x3c
1017 #define UNSUPPORTED_EVENT UINT16_MAX
1018 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1021 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1022 * of ARM event numbers to indices in our pm_events array.
1024 * Note: Events in the 0x40XX range are not currently supported.
1026 void pmu_init(ARMCPU
*cpu
)
1031 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1034 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1035 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1040 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1041 const pm_event
*cnt
= &pm_events
[i
];
1042 assert(cnt
->number
<= MAX_EVENT_ID
);
1043 /* We do not currently support events in the 0x40xx range */
1044 assert(cnt
->number
<= 0x3f);
1046 if (cnt
->supported(&cpu
->env
)) {
1047 supported_event_map
[cnt
->number
] = i
;
1048 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1049 if (cnt
->number
& 0x20) {
1050 cpu
->pmceid1
|= event_mask
;
1052 cpu
->pmceid0
|= event_mask
;
1059 * Check at runtime whether a PMU event is supported for the current machine
1061 static bool event_supported(uint16_t number
)
1063 if (number
> MAX_EVENT_ID
) {
1066 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1069 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1073 * Performance monitor registers user accessibility is controlled
1074 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1075 * trapping to EL2 or EL3 for other accesses.
1077 int el
= arm_current_el(env
);
1078 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1080 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1081 return CP_ACCESS_TRAP
;
1083 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1084 return CP_ACCESS_TRAP_EL2
;
1086 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1087 return CP_ACCESS_TRAP_EL3
;
1090 return CP_ACCESS_OK
;
1093 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1094 const ARMCPRegInfo
*ri
,
1097 /* ER: event counter read trap control */
1098 if (arm_feature(env
, ARM_FEATURE_V8
)
1099 && arm_current_el(env
) == 0
1100 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1102 return CP_ACCESS_OK
;
1105 return pmreg_access(env
, ri
, isread
);
1108 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1109 const ARMCPRegInfo
*ri
,
1112 /* SW: software increment write trap control */
1113 if (arm_feature(env
, ARM_FEATURE_V8
)
1114 && arm_current_el(env
) == 0
1115 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1117 return CP_ACCESS_OK
;
1120 return pmreg_access(env
, ri
, isread
);
1123 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1124 const ARMCPRegInfo
*ri
,
1127 /* ER: event counter read trap control */
1128 if (arm_feature(env
, ARM_FEATURE_V8
)
1129 && arm_current_el(env
) == 0
1130 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1131 return CP_ACCESS_OK
;
1134 return pmreg_access(env
, ri
, isread
);
1137 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1138 const ARMCPRegInfo
*ri
,
1141 /* CR: cycle counter read trap control */
1142 if (arm_feature(env
, ARM_FEATURE_V8
)
1143 && arm_current_el(env
) == 0
1144 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1146 return CP_ACCESS_OK
;
1149 return pmreg_access(env
, ri
, isread
);
1153 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1154 * We use these to decide whether we need to wrap a write to MDCR_EL2
1155 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1157 #define MDCR_EL2_PMU_ENABLE_BITS \
1158 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1159 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1162 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1163 * the current EL, security state, and register configuration.
1165 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1168 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1169 bool enabled
, prohibited
= false, filtered
;
1170 bool secure
= arm_is_secure(env
);
1171 int el
= arm_current_el(env
);
1172 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1173 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1175 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1179 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1180 (counter
< hpmn
|| counter
== 31)) {
1181 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1183 e
= mdcr_el2
& MDCR_HPME
;
1185 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1187 /* Is event counting prohibited? */
1188 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1189 prohibited
= mdcr_el2
& MDCR_HPMD
;
1192 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1195 if (counter
== 31) {
1197 * The cycle counter defaults to running. PMCR.DP says "disable
1198 * the cycle counter when event counting is prohibited".
1199 * Some MDCR bits disable the cycle counter specifically.
1201 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1202 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1204 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1207 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1212 if (counter
== 31) {
1213 filter
= env
->cp15
.pmccfiltr_el0
;
1215 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1218 p
= filter
& PMXEVTYPER_P
;
1219 u
= filter
& PMXEVTYPER_U
;
1220 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1221 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1222 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1223 m
= arm_el_is_aa64(env
, 1) &&
1224 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1227 filtered
= secure
? u
: u
!= nsu
;
1228 } else if (el
== 1) {
1229 filtered
= secure
? p
: p
!= nsk
;
1230 } else if (el
== 2) {
1236 if (counter
!= 31) {
1238 * If not checking PMCCNTR, ensure the counter is setup to an event we
1241 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1242 if (!event_supported(event
)) {
1247 return enabled
&& !prohibited
&& !filtered
;
1250 static void pmu_update_irq(CPUARMState
*env
)
1252 ARMCPU
*cpu
= env_archcpu(env
);
1253 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1254 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1257 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1260 * Return true if the clock divider is enabled and the cycle counter
1261 * is supposed to tick only once every 64 clock cycles. This is
1262 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1263 * (64-bit) cycle counter PMCR.D has no effect.
1265 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1268 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1270 /* Return true if the specified event counter is configured to be 64 bit */
1272 /* This isn't intended to be used with the cycle counter */
1273 assert(counter
< 31);
1275 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1279 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1281 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1282 * current security state, so we don't use arm_mdcr_el2_eff() here.
1284 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1285 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1287 if (counter
>= hpmn
) {
1291 return env
->cp15
.c9_pmcr
& PMCRLP
;
1295 * Ensure c15_ccnt is the guest-visible count so that operations such as
1296 * enabling/disabling the counter or filtering, modifying the count itself,
1297 * etc. can be done logically. This is essentially a no-op if the counter is
1298 * not enabled at the time of the call.
1300 static void pmccntr_op_start(CPUARMState
*env
)
1302 uint64_t cycles
= cycles_get_count(env
);
1304 if (pmu_counter_enabled(env
, 31)) {
1305 uint64_t eff_cycles
= cycles
;
1306 if (pmccntr_clockdiv_enabled(env
)) {
1310 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1312 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1313 1ull << 63 : 1ull << 31;
1314 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1315 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1316 pmu_update_irq(env
);
1319 env
->cp15
.c15_ccnt
= new_pmccntr
;
1321 env
->cp15
.c15_ccnt_delta
= cycles
;
1325 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1326 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1329 static void pmccntr_op_finish(CPUARMState
*env
)
1331 if (pmu_counter_enabled(env
, 31)) {
1332 #ifndef CONFIG_USER_ONLY
1333 /* Calculate when the counter will next overflow */
1334 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1335 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1336 remaining_cycles
= (uint32_t)remaining_cycles
;
1338 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1340 if (overflow_in
> 0) {
1341 int64_t overflow_at
;
1343 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1344 overflow_in
, &overflow_at
)) {
1345 ARMCPU
*cpu
= env_archcpu(env
);
1346 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1351 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1352 if (pmccntr_clockdiv_enabled(env
)) {
1355 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1359 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1362 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1364 if (event_supported(event
)) {
1365 uint16_t event_idx
= supported_event_map
[event
];
1366 count
= pm_events
[event_idx
].get_count(env
);
1369 if (pmu_counter_enabled(env
, counter
)) {
1370 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1371 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1372 1ULL << 63 : 1ULL << 31;
1374 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1375 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1376 pmu_update_irq(env
);
1378 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1380 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1383 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1385 if (pmu_counter_enabled(env
, counter
)) {
1386 #ifndef CONFIG_USER_ONLY
1387 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1388 uint16_t event_idx
= supported_event_map
[event
];
1389 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1390 int64_t overflow_in
;
1392 if (!pmevcntr_is_64_bit(env
, counter
)) {
1393 delta
= (uint32_t)delta
;
1395 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1397 if (overflow_in
> 0) {
1398 int64_t overflow_at
;
1400 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1401 overflow_in
, &overflow_at
)) {
1402 ARMCPU
*cpu
= env_archcpu(env
);
1403 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1408 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1409 env
->cp15
.c14_pmevcntr
[counter
];
1413 void pmu_op_start(CPUARMState
*env
)
1416 pmccntr_op_start(env
);
1417 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1418 pmevcntr_op_start(env
, i
);
1422 void pmu_op_finish(CPUARMState
*env
)
1425 pmccntr_op_finish(env
);
1426 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1427 pmevcntr_op_finish(env
, i
);
1431 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1433 pmu_op_start(&cpu
->env
);
1436 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1438 pmu_op_finish(&cpu
->env
);
1441 void arm_pmu_timer_cb(void *opaque
)
1443 ARMCPU
*cpu
= opaque
;
1446 * Update all the counter values based on the current underlying counts,
1447 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1448 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1449 * counter may expire.
1451 pmu_op_start(&cpu
->env
);
1452 pmu_op_finish(&cpu
->env
);
1455 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 if (value
& PMCRC
) {
1461 /* The counter has been reset */
1462 env
->cp15
.c15_ccnt
= 0;
1465 if (value
& PMCRP
) {
1467 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1468 env
->cp15
.c14_pmevcntr
[i
] = 0;
1472 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1473 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1478 static uint64_t pmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1480 uint64_t pmcr
= env
->cp15
.c9_pmcr
;
1483 * If EL2 is implemented and enabled for the current security state, reads
1484 * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN.
1486 if (arm_current_el(env
) <= 1 && arm_is_el2_enabled(env
)) {
1487 pmcr
&= ~PMCRN_MASK
;
1488 pmcr
|= (env
->cp15
.mdcr_el2
& MDCR_HPMN
) << PMCRN_SHIFT
;
1494 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1498 uint64_t overflow_mask
, new_pmswinc
;
1500 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1501 /* Increment a counter's count iff: */
1502 if ((value
& (1 << i
)) && /* counter's bit is set */
1503 /* counter is enabled and not filtered */
1504 pmu_counter_enabled(env
, i
) &&
1505 /* counter is SW_INCR */
1506 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1507 pmevcntr_op_start(env
, i
);
1510 * Detect if this write causes an overflow since we can't predict
1511 * PMSWINC overflows like we can for other events
1513 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1515 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1516 1ULL << 63 : 1ULL << 31;
1518 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1519 env
->cp15
.c9_pmovsr
|= (1 << i
);
1520 pmu_update_irq(env
);
1523 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1525 pmevcntr_op_finish(env
, i
);
1530 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1533 pmccntr_op_start(env
);
1534 ret
= env
->cp15
.c15_ccnt
;
1535 pmccntr_op_finish(env
);
1539 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1543 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1544 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1545 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1548 env
->cp15
.c9_pmselr
= value
& 0x1f;
1551 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1554 pmccntr_op_start(env
);
1555 env
->cp15
.c15_ccnt
= value
;
1556 pmccntr_op_finish(env
);
1559 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1562 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1564 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1567 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1570 pmccntr_op_start(env
);
1571 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1572 pmccntr_op_finish(env
);
1575 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1578 pmccntr_op_start(env
);
1579 /* M is not accessible from AArch32 */
1580 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1581 (value
& PMCCFILTR
);
1582 pmccntr_op_finish(env
);
1585 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1587 /* M is not visible in AArch32 */
1588 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1591 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1595 value
&= pmu_counter_mask(env
);
1596 env
->cp15
.c9_pmcnten
|= value
;
1600 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1604 value
&= pmu_counter_mask(env
);
1605 env
->cp15
.c9_pmcnten
&= ~value
;
1609 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1612 value
&= pmu_counter_mask(env
);
1613 env
->cp15
.c9_pmovsr
&= ~value
;
1614 pmu_update_irq(env
);
1617 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1620 value
&= pmu_counter_mask(env
);
1621 env
->cp15
.c9_pmovsr
|= value
;
1622 pmu_update_irq(env
);
1625 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1626 uint64_t value
, const uint8_t counter
)
1628 if (counter
== 31) {
1629 pmccfiltr_write(env
, ri
, value
);
1630 } else if (counter
< pmu_num_counters(env
)) {
1631 pmevcntr_op_start(env
, counter
);
1634 * If this counter's event type is changing, store the current
1635 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1636 * pmevcntr_op_finish has the correct baseline when it converts back to
1639 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1640 PMXEVTYPER_EVTCOUNT
;
1641 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1642 if (old_event
!= new_event
) {
1644 if (event_supported(new_event
)) {
1645 uint16_t event_idx
= supported_event_map
[new_event
];
1646 count
= pm_events
[event_idx
].get_count(env
);
1648 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1651 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1652 pmevcntr_op_finish(env
, counter
);
1655 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1656 * PMSELR value is equal to or greater than the number of implemented
1657 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1661 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1662 const uint8_t counter
)
1664 if (counter
== 31) {
1665 return env
->cp15
.pmccfiltr_el0
;
1666 } else if (counter
< pmu_num_counters(env
)) {
1667 return env
->cp15
.c14_pmevtyper
[counter
];
1670 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1671 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1677 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1680 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1681 pmevtyper_write(env
, ri
, value
, counter
);
1684 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1687 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1688 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1691 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1692 * pmu_op_finish calls when loading saved state for a migration. Because
1693 * we're potentially updating the type of event here, the value written to
1694 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1695 * different counter type. Therefore, we need to set this value to the
1696 * current count for the counter type we're writing so that pmu_op_finish
1697 * has the correct count for its calculation.
1699 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1700 if (event_supported(event
)) {
1701 uint16_t event_idx
= supported_event_map
[event
];
1702 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1703 pm_events
[event_idx
].get_count(env
);
1707 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1709 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1710 return pmevtyper_read(env
, ri
, counter
);
1713 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1716 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1719 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1721 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1724 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1725 uint64_t value
, uint8_t counter
)
1727 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1728 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1729 value
&= MAKE_64BIT_MASK(0, 32);
1731 if (counter
< pmu_num_counters(env
)) {
1732 pmevcntr_op_start(env
, counter
);
1733 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1734 pmevcntr_op_finish(env
, counter
);
1737 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1738 * are CONSTRAINED UNPREDICTABLE.
1742 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1745 if (counter
< pmu_num_counters(env
)) {
1747 pmevcntr_op_start(env
, counter
);
1748 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1749 pmevcntr_op_finish(env
, counter
);
1750 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1751 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1752 ret
&= MAKE_64BIT_MASK(0, 32);
1757 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1758 * are CONSTRAINED UNPREDICTABLE.
1764 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1767 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1768 pmevcntr_write(env
, ri
, value
, counter
);
1771 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1773 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1774 return pmevcntr_read(env
, ri
, counter
);
1777 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1780 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1781 assert(counter
< pmu_num_counters(env
));
1782 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1783 pmevcntr_write(env
, ri
, value
, counter
);
1786 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1788 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1789 assert(counter
< pmu_num_counters(env
));
1790 return env
->cp15
.c14_pmevcntr
[counter
];
1793 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1796 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1799 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1801 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1804 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1807 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1808 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1810 env
->cp15
.c9_pmuserenr
= value
& 1;
1814 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1817 /* We have no event counters so only the C bit can be changed */
1818 value
&= pmu_counter_mask(env
);
1819 env
->cp15
.c9_pminten
|= value
;
1820 pmu_update_irq(env
);
1823 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1826 value
&= pmu_counter_mask(env
);
1827 env
->cp15
.c9_pminten
&= ~value
;
1828 pmu_update_irq(env
);
1831 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1835 * Note that even though the AArch64 view of this register has bits
1836 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1837 * architectural requirements for bits which are RES0 only in some
1838 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1839 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1841 raw_write(env
, ri
, value
& ~0x1FULL
);
1844 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1846 /* Begin with base v8.0 state. */
1847 uint64_t valid_mask
= 0x3fff;
1848 ARMCPU
*cpu
= env_archcpu(env
);
1852 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1853 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1854 * Instead, choose the format based on the mode of EL3.
1856 if (arm_el_is_aa64(env
, 3)) {
1857 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1858 valid_mask
&= ~SCR_NET
; /* RES0 */
1860 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1861 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1862 value
|= SCR_RW
; /* RAO/WI */
1864 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1865 valid_mask
|= SCR_TERR
;
1867 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1868 valid_mask
|= SCR_TLOR
;
1870 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1871 valid_mask
|= SCR_API
| SCR_APK
;
1873 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1874 valid_mask
|= SCR_EEL2
;
1875 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1876 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1879 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1880 valid_mask
|= SCR_ATA
;
1882 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1883 valid_mask
|= SCR_ENSCXT
;
1885 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1886 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1888 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1889 valid_mask
|= SCR_ENTP2
;
1891 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1892 valid_mask
|= SCR_HXEN
;
1894 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1895 valid_mask
|= SCR_FGTEN
;
1897 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1898 valid_mask
|= SCR_NSE
| SCR_GPF
;
1901 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1902 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1903 valid_mask
|= SCR_TERR
;
1907 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1908 valid_mask
&= ~SCR_HCE
;
1911 * On ARMv7, SMD (or SCD as it is called in v7) is only
1912 * supported if EL2 exists. The bit is UNK/SBZP when
1913 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1914 * when EL2 is unavailable.
1915 * On ARMv8, this bit is always available.
1917 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1918 !arm_feature(env
, ARM_FEATURE_V8
)) {
1919 valid_mask
&= ~SCR_SMD
;
1923 /* Clear all-context RES0 bits. */
1924 value
&= valid_mask
;
1925 changed
= env
->cp15
.scr_el3
^ value
;
1926 env
->cp15
.scr_el3
= value
;
1929 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1930 * we must invalidate all TLBs below EL3.
1932 if (changed
& (SCR_NS
| SCR_NSE
)) {
1933 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1934 ARMMMUIdxBit_E20_0
|
1935 ARMMMUIdxBit_E10_1
|
1936 ARMMMUIdxBit_E20_2
|
1937 ARMMMUIdxBit_E10_1_PAN
|
1938 ARMMMUIdxBit_E20_2_PAN
|
1943 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1946 * scr_write will set the RES1 bits on an AArch64-only CPU.
1947 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1949 scr_write(env
, ri
, 0);
1952 static CPAccessResult
access_tid4(CPUARMState
*env
,
1953 const ARMCPRegInfo
*ri
,
1956 if (arm_current_el(env
) == 1 &&
1957 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1958 return CP_ACCESS_TRAP_EL2
;
1961 return CP_ACCESS_OK
;
1964 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1966 ARMCPU
*cpu
= env_archcpu(env
);
1969 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1972 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1973 ri
->secure
& ARM_CP_SECSTATE_S
);
1975 return cpu
->ccsidr
[index
];
1978 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1981 raw_write(env
, ri
, value
& 0xf);
1984 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1986 CPUState
*cs
= env_cpu(env
);
1987 bool el1
= arm_current_el(env
) == 1;
1988 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1991 if (hcr_el2
& HCR_IMO
) {
1992 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1996 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2001 if (hcr_el2
& HCR_FMO
) {
2002 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2006 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2011 if (hcr_el2
& HCR_AMO
) {
2012 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2020 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2023 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2024 return CP_ACCESS_TRAP_EL2
;
2027 return CP_ACCESS_OK
;
2030 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2033 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2034 return access_aa64_tid1(env
, ri
, isread
);
2037 return CP_ACCESS_OK
;
2040 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2041 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2042 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2043 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2045 * Performance monitors are implementation defined in v7,
2046 * but with an ARM recommended set of registers, which we
2049 * Performance registers fall into three categories:
2050 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2051 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2052 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2053 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2054 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2056 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2057 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2058 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2059 .writefn
= pmcntenset_write
,
2060 .accessfn
= pmreg_access
,
2062 .raw_writefn
= raw_write
},
2063 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2064 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2065 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2067 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2068 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2069 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2071 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2072 .accessfn
= pmreg_access
,
2074 .writefn
= pmcntenclr_write
,
2075 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2076 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2077 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2078 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2080 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2082 .writefn
= pmcntenclr_write
},
2083 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2084 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2085 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2086 .accessfn
= pmreg_access
,
2088 .writefn
= pmovsr_write
,
2089 .raw_writefn
= raw_write
},
2090 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2091 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2092 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2094 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2095 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2096 .writefn
= pmovsr_write
,
2097 .raw_writefn
= raw_write
},
2098 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2099 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2100 .fgt
= FGT_PMSWINC_EL0
,
2101 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2102 .writefn
= pmswinc_write
},
2103 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2104 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2105 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2106 .fgt
= FGT_PMSWINC_EL0
,
2107 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2108 .writefn
= pmswinc_write
},
2109 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2110 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2111 .fgt
= FGT_PMSELR_EL0
,
2112 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2113 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2114 .raw_writefn
= raw_write
},
2115 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2116 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2117 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2118 .fgt
= FGT_PMSELR_EL0
,
2119 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2120 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2121 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2122 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2123 .fgt
= FGT_PMCCNTR_EL0
,
2124 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2125 .accessfn
= pmreg_access_ccntr
},
2126 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2127 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2128 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2129 .fgt
= FGT_PMCCNTR_EL0
,
2131 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2132 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2133 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2134 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2135 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2136 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2137 .fgt
= FGT_PMCCFILTR_EL0
,
2138 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2140 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2141 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2142 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2143 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2144 .fgt
= FGT_PMCCFILTR_EL0
,
2146 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2148 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2149 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2150 .accessfn
= pmreg_access
,
2151 .fgt
= FGT_PMEVTYPERN_EL0
,
2152 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2153 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2154 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2155 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2156 .accessfn
= pmreg_access
,
2157 .fgt
= FGT_PMEVTYPERN_EL0
,
2158 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2159 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2160 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2161 .accessfn
= pmreg_access_xevcntr
,
2162 .fgt
= FGT_PMEVCNTRN_EL0
,
2163 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2164 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2165 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2166 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2167 .accessfn
= pmreg_access_xevcntr
,
2168 .fgt
= FGT_PMEVCNTRN_EL0
,
2169 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2170 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2171 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2172 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2174 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2175 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2176 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2177 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2178 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2180 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2181 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2182 .access
= PL1_RW
, .accessfn
= access_tpm
,
2184 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2185 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2187 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2188 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2189 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2190 .access
= PL1_RW
, .accessfn
= access_tpm
,
2193 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2194 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2195 .resetvalue
= 0x0 },
2196 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2197 .access
= PL1_RW
, .accessfn
= access_tpm
,
2199 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2200 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2201 .writefn
= pmintenclr_write
, },
2202 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2203 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2204 .access
= PL1_RW
, .accessfn
= access_tpm
,
2206 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2207 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2208 .writefn
= pmintenclr_write
},
2209 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2210 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2212 .accessfn
= access_tid4
,
2213 .fgt
= FGT_CCSIDR_EL1
,
2214 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2215 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2216 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2218 .accessfn
= access_tid4
,
2219 .fgt
= FGT_CSSELR_EL1
,
2220 .writefn
= csselr_write
, .resetvalue
= 0,
2221 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2222 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2224 * Auxiliary ID register: this actually has an IMPDEF value but for now
2225 * just RAZ for all cores:
2227 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2228 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2229 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2230 .accessfn
= access_aa64_tid1
,
2231 .fgt
= FGT_AIDR_EL1
,
2234 * Auxiliary fault status registers: these also are IMPDEF, and we
2235 * choose to RAZ/WI for all cores.
2237 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2238 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2239 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2240 .fgt
= FGT_AFSR0_EL1
,
2241 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2242 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2243 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2244 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2245 .fgt
= FGT_AFSR1_EL1
,
2246 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2248 * MAIR can just read-as-written because we don't implement caches
2249 * and so don't need to care about memory attributes.
2251 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2252 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2253 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2254 .fgt
= FGT_MAIR_EL1
,
2255 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2257 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2258 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2259 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2262 * For non-long-descriptor page tables these are PRRR and NMRR;
2263 * regardless they still act as reads-as-written for QEMU.
2266 * MAIR0/1 are defined separately from their 64-bit counterpart which
2267 * allows them to assign the correct fieldoffset based on the endianness
2268 * handled in the field definitions.
2270 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2271 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2272 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2273 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2274 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2275 .resetfn
= arm_cp_reset_ignore
},
2276 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2277 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2278 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2279 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2280 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2281 .resetfn
= arm_cp_reset_ignore
},
2282 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2283 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2285 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2286 /* 32 bit ITLB invalidates */
2287 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2288 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2289 .writefn
= tlbiall_write
},
2290 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2291 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2292 .writefn
= tlbimva_write
},
2293 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2294 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2295 .writefn
= tlbiasid_write
},
2296 /* 32 bit DTLB invalidates */
2297 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2298 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2299 .writefn
= tlbiall_write
},
2300 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2301 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2302 .writefn
= tlbimva_write
},
2303 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2304 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2305 .writefn
= tlbiasid_write
},
2306 /* 32 bit TLB invalidates */
2307 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2308 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2309 .writefn
= tlbiall_write
},
2310 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2311 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2312 .writefn
= tlbimva_write
},
2313 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2314 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2315 .writefn
= tlbiasid_write
},
2316 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2317 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2318 .writefn
= tlbimvaa_write
},
2321 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2322 /* 32 bit TLB invalidates, Inner Shareable */
2323 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2324 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2325 .writefn
= tlbiall_is_write
},
2326 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2327 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2328 .writefn
= tlbimva_is_write
},
2329 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2330 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2331 .writefn
= tlbiasid_is_write
},
2332 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2333 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2334 .writefn
= tlbimvaa_is_write
},
2337 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2338 /* PMOVSSET is not implemented in v7 before v7ve */
2339 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2340 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2342 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2343 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2344 .writefn
= pmovsset_write
,
2345 .raw_writefn
= raw_write
},
2346 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2347 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2348 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2350 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2351 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2352 .writefn
= pmovsset_write
,
2353 .raw_writefn
= raw_write
},
2356 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2363 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2367 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2368 * at all, so we don't need to check whether we're v8A.
2370 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2371 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2372 return CP_ACCESS_TRAP_EL2
;
2374 return CP_ACCESS_OK
;
2377 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2380 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2381 return CP_ACCESS_TRAP
;
2383 return teecr_access(env
, ri
, isread
);
2386 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2387 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2388 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2390 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2391 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2392 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2393 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2396 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2397 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2398 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2400 .fgt
= FGT_TPIDR_EL0
,
2401 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2402 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2404 .fgt
= FGT_TPIDR_EL0
,
2405 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2406 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2407 .resetfn
= arm_cp_reset_ignore
},
2408 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2409 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2410 .access
= PL0_R
| PL1_W
,
2411 .fgt
= FGT_TPIDRRO_EL0
,
2412 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2414 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2415 .access
= PL0_R
| PL1_W
,
2416 .fgt
= FGT_TPIDRRO_EL0
,
2417 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2418 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2419 .resetfn
= arm_cp_reset_ignore
},
2420 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2421 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2423 .fgt
= FGT_TPIDR_EL1
,
2424 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2425 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2427 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2428 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2432 #ifndef CONFIG_USER_ONLY
2434 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2438 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2439 * Writable only at the highest implemented exception level.
2441 int el
= arm_current_el(env
);
2447 hcr
= arm_hcr_el2_eff(env
);
2448 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2449 cntkctl
= env
->cp15
.cnthctl_el2
;
2451 cntkctl
= env
->cp15
.c14_cntkctl
;
2453 if (!extract32(cntkctl
, 0, 2)) {
2454 return CP_ACCESS_TRAP
;
2458 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2459 arm_is_secure_below_el3(env
)) {
2460 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2461 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2469 if (!isread
&& el
< arm_highest_el(env
)) {
2470 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2473 return CP_ACCESS_OK
;
2476 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2479 unsigned int cur_el
= arm_current_el(env
);
2480 bool has_el2
= arm_is_el2_enabled(env
);
2481 uint64_t hcr
= arm_hcr_el2_eff(env
);
2485 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2486 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2487 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2488 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2491 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2492 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2493 return CP_ACCESS_TRAP
;
2497 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2498 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2500 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2501 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2502 return CP_ACCESS_TRAP_EL2
;
2506 return CP_ACCESS_OK
;
2509 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2512 unsigned int cur_el
= arm_current_el(env
);
2513 bool has_el2
= arm_is_el2_enabled(env
);
2514 uint64_t hcr
= arm_hcr_el2_eff(env
);
2518 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2519 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2520 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2521 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2525 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2526 * EL0 if EL0[PV]TEN is zero.
2528 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2529 return CP_ACCESS_TRAP
;
2534 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2535 if (hcr
& HCR_E2H
) {
2536 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2537 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2538 return CP_ACCESS_TRAP_EL2
;
2541 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2542 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2543 return CP_ACCESS_TRAP_EL2
;
2549 return CP_ACCESS_OK
;
2552 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2553 const ARMCPRegInfo
*ri
,
2556 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2559 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2560 const ARMCPRegInfo
*ri
,
2563 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2566 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2569 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2572 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2575 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2578 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2579 const ARMCPRegInfo
*ri
,
2583 * The AArch64 register view of the secure physical timer is
2584 * always accessible from EL3, and configurably accessible from
2587 switch (arm_current_el(env
)) {
2589 if (!arm_is_secure(env
)) {
2590 return CP_ACCESS_TRAP
;
2592 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2593 return CP_ACCESS_TRAP_EL3
;
2595 return CP_ACCESS_OK
;
2598 return CP_ACCESS_TRAP
;
2600 return CP_ACCESS_OK
;
2602 g_assert_not_reached();
2606 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2608 ARMCPU
*cpu
= env_archcpu(env
);
2610 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2613 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2615 CPUARMState
*env
= &cpu
->env
;
2616 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2617 ARMSecuritySpace ss
= arm_security_space(env
);
2618 /* ISTATUS && !IMASK */
2619 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2622 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2623 * It is RES0 in Secure and NonSecure state.
2625 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2626 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2627 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2631 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2632 trace_arm_gt_update_irq(timeridx
, irqstate
);
2635 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2638 * Changing security state between Root and Secure/NonSecure, which may
2639 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2640 * mask bits. Update the IRQ state accordingly.
2642 gt_update_irq(cpu
, GTIMER_VIRT
);
2643 gt_update_irq(cpu
, GTIMER_PHYS
);
2646 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2648 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2652 * Timer enabled: calculate and set current ISTATUS, irq, and
2653 * reset timer to when ISTATUS next has to change
2655 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2656 cpu
->env
.cp15
.cntvoff_el2
: 0;
2657 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2658 /* Note that this must be unsigned 64 bit arithmetic: */
2659 int istatus
= count
- offset
>= gt
->cval
;
2662 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2666 * Next transition is when (count - offset) rolls back over to 0.
2667 * If offset > count then this is when count == offset;
2668 * if offset <= count then this is when count == offset + 2^64
2669 * For the latter case we set nexttick to an "as far in future
2670 * as possible" value and let the code below handle it.
2672 if (offset
> count
) {
2675 nexttick
= UINT64_MAX
;
2679 * Next transition is when (count - offset) == cval, i.e.
2680 * when count == (cval + offset).
2681 * If that would overflow, then again we set up the next interrupt
2682 * for "as far in the future as possible" for the code below.
2684 if (uadd64_overflow(gt
->cval
, offset
, &nexttick
)) {
2685 nexttick
= UINT64_MAX
;
2689 * Note that the desired next expiry time might be beyond the
2690 * signed-64-bit range of a QEMUTimer -- in this case we just
2691 * set the timer for as far in the future as possible. When the
2692 * timer expires we will reset the timer for any remaining period.
2694 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2695 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2697 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2699 trace_arm_gt_recalc(timeridx
, nexttick
);
2701 /* Timer disabled: ISTATUS and timer output always clear */
2703 timer_del(cpu
->gt_timer
[timeridx
]);
2704 trace_arm_gt_recalc_disabled(timeridx
);
2706 gt_update_irq(cpu
, timeridx
);
2709 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2712 ARMCPU
*cpu
= env_archcpu(env
);
2714 timer_del(cpu
->gt_timer
[timeridx
]);
2717 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2719 return gt_get_countervalue(env
);
2722 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2726 switch (arm_current_el(env
)) {
2728 hcr
= arm_hcr_el2_eff(env
);
2729 if (hcr
& HCR_E2H
) {
2734 hcr
= arm_hcr_el2_eff(env
);
2735 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2741 return env
->cp15
.cntvoff_el2
;
2744 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2746 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2749 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2753 trace_arm_gt_cval_write(timeridx
, value
);
2754 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2755 gt_recalc_timer(env_archcpu(env
), timeridx
);
2758 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2761 uint64_t offset
= 0;
2765 case GTIMER_HYPVIRT
:
2766 offset
= gt_virt_cnt_offset(env
);
2770 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2771 (gt_get_countervalue(env
) - offset
));
2774 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2778 uint64_t offset
= 0;
2782 case GTIMER_HYPVIRT
:
2783 offset
= gt_virt_cnt_offset(env
);
2787 trace_arm_gt_tval_write(timeridx
, value
);
2788 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2789 sextract64(value
, 0, 32);
2790 gt_recalc_timer(env_archcpu(env
), timeridx
);
2793 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2797 ARMCPU
*cpu
= env_archcpu(env
);
2798 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2800 trace_arm_gt_ctl_write(timeridx
, value
);
2801 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2802 if ((oldval
^ value
) & 1) {
2803 /* Enable toggled */
2804 gt_recalc_timer(cpu
, timeridx
);
2805 } else if ((oldval
^ value
) & 2) {
2807 * IMASK toggled: don't need to recalculate,
2808 * just set the interrupt line based on ISTATUS
2810 trace_arm_gt_imask_toggle(timeridx
);
2811 gt_update_irq(cpu
, timeridx
);
2815 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2817 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2820 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2823 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2826 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2828 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2831 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2834 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2837 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2840 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2843 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2845 switch (arm_mmu_idx(env
)) {
2846 case ARMMMUIdx_E20_0
:
2847 case ARMMMUIdx_E20_2
:
2848 case ARMMMUIdx_E20_2_PAN
:
2855 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2857 switch (arm_mmu_idx(env
)) {
2858 case ARMMMUIdx_E20_0
:
2859 case ARMMMUIdx_E20_2
:
2860 case ARMMMUIdx_E20_2_PAN
:
2861 return GTIMER_HYPVIRT
;
2867 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2868 const ARMCPRegInfo
*ri
)
2870 int timeridx
= gt_phys_redir_timeridx(env
);
2871 return env
->cp15
.c14_timer
[timeridx
].cval
;
2874 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2877 int timeridx
= gt_phys_redir_timeridx(env
);
2878 gt_cval_write(env
, ri
, timeridx
, value
);
2881 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2882 const ARMCPRegInfo
*ri
)
2884 int timeridx
= gt_phys_redir_timeridx(env
);
2885 return gt_tval_read(env
, ri
, timeridx
);
2888 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2891 int timeridx
= gt_phys_redir_timeridx(env
);
2892 gt_tval_write(env
, ri
, timeridx
, value
);
2895 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2896 const ARMCPRegInfo
*ri
)
2898 int timeridx
= gt_phys_redir_timeridx(env
);
2899 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2902 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2905 int timeridx
= gt_phys_redir_timeridx(env
);
2906 gt_ctl_write(env
, ri
, timeridx
, value
);
2909 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2911 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2914 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2917 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2920 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2922 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2925 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2928 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2931 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2934 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2937 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2940 ARMCPU
*cpu
= env_archcpu(env
);
2941 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2943 raw_write(env
, ri
, value
);
2945 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2946 gt_update_irq(cpu
, GTIMER_VIRT
);
2947 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2948 gt_update_irq(cpu
, GTIMER_PHYS
);
2952 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2955 ARMCPU
*cpu
= env_archcpu(env
);
2957 trace_arm_gt_cntvoff_write(value
);
2958 raw_write(env
, ri
, value
);
2959 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2962 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2963 const ARMCPRegInfo
*ri
)
2965 int timeridx
= gt_virt_redir_timeridx(env
);
2966 return env
->cp15
.c14_timer
[timeridx
].cval
;
2969 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2972 int timeridx
= gt_virt_redir_timeridx(env
);
2973 gt_cval_write(env
, ri
, timeridx
, value
);
2976 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2977 const ARMCPRegInfo
*ri
)
2979 int timeridx
= gt_virt_redir_timeridx(env
);
2980 return gt_tval_read(env
, ri
, timeridx
);
2983 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2986 int timeridx
= gt_virt_redir_timeridx(env
);
2987 gt_tval_write(env
, ri
, timeridx
, value
);
2990 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2991 const ARMCPRegInfo
*ri
)
2993 int timeridx
= gt_virt_redir_timeridx(env
);
2994 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2997 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3000 int timeridx
= gt_virt_redir_timeridx(env
);
3001 gt_ctl_write(env
, ri
, timeridx
, value
);
3004 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3006 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3009 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3012 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3015 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3017 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3020 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3023 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3026 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3029 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3032 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3034 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3037 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3040 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3043 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3045 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3048 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3051 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3054 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3057 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3060 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3062 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3065 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3068 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3071 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3073 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3076 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3079 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3082 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3085 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3088 void arm_gt_ptimer_cb(void *opaque
)
3090 ARMCPU
*cpu
= opaque
;
3092 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3095 void arm_gt_vtimer_cb(void *opaque
)
3097 ARMCPU
*cpu
= opaque
;
3099 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3102 void arm_gt_htimer_cb(void *opaque
)
3104 ARMCPU
*cpu
= opaque
;
3106 gt_recalc_timer(cpu
, GTIMER_HYP
);
3109 void arm_gt_stimer_cb(void *opaque
)
3111 ARMCPU
*cpu
= opaque
;
3113 gt_recalc_timer(cpu
, GTIMER_SEC
);
3116 void arm_gt_hvtimer_cb(void *opaque
)
3118 ARMCPU
*cpu
= opaque
;
3120 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3123 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3125 ARMCPU
*cpu
= env_archcpu(env
);
3127 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3130 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3132 * Note that CNTFRQ is purely reads-as-written for the benefit
3133 * of software; writing it doesn't actually change the timer frequency.
3134 * Our reset value matches the fixed frequency we implement the timer at.
3136 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3137 .type
= ARM_CP_ALIAS
,
3138 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3139 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3141 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3142 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3143 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3144 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3145 .resetfn
= arm_gt_cntfrq_reset
,
3147 /* overall control: mostly access permissions */
3148 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3149 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3151 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3154 /* per-timer control */
3155 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3156 .secure
= ARM_CP_SECSTATE_NS
,
3157 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3158 .accessfn
= gt_ptimer_access
,
3159 .fieldoffset
= offsetoflow32(CPUARMState
,
3160 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3161 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3162 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3164 { .name
= "CNTP_CTL_S",
3165 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3166 .secure
= ARM_CP_SECSTATE_S
,
3167 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3168 .accessfn
= gt_ptimer_access
,
3169 .fieldoffset
= offsetoflow32(CPUARMState
,
3170 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3171 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3173 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3174 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3175 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3176 .accessfn
= gt_ptimer_access
,
3177 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3179 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3180 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3182 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3183 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3184 .accessfn
= gt_vtimer_access
,
3185 .fieldoffset
= offsetoflow32(CPUARMState
,
3186 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3187 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3188 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3190 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3191 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3192 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3193 .accessfn
= gt_vtimer_access
,
3194 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3196 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3197 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3199 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3200 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3201 .secure
= ARM_CP_SECSTATE_NS
,
3202 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3203 .accessfn
= gt_ptimer_access
,
3204 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3206 { .name
= "CNTP_TVAL_S",
3207 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3208 .secure
= ARM_CP_SECSTATE_S
,
3209 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3210 .accessfn
= gt_ptimer_access
,
3211 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3213 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3214 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3215 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3216 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3217 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3219 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3220 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3221 .accessfn
= gt_vtimer_access
,
3222 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3224 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3225 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3226 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3227 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3228 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3230 /* The counter itself */
3231 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3232 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3233 .accessfn
= gt_pct_access
,
3234 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3236 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3238 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3239 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3241 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3242 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3243 .accessfn
= gt_vct_access
,
3244 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3246 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3247 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3248 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3249 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3251 /* Comparison value, indicating when the timer goes off */
3252 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3253 .secure
= ARM_CP_SECSTATE_NS
,
3255 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3256 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3257 .accessfn
= gt_ptimer_access
,
3258 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3259 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3261 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3262 .secure
= ARM_CP_SECSTATE_S
,
3264 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3265 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3266 .accessfn
= gt_ptimer_access
,
3267 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3269 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3270 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3273 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3274 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3275 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3276 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3278 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3280 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3281 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3282 .accessfn
= gt_vtimer_access
,
3283 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3284 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3286 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3287 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3291 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3292 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3293 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3296 * Secure timer -- this is actually restricted to only EL3
3297 * and configurably Secure-EL1 via the accessfn.
3299 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3300 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3301 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3302 .accessfn
= gt_stimer_access
,
3303 .readfn
= gt_sec_tval_read
,
3304 .writefn
= gt_sec_tval_write
,
3305 .resetfn
= gt_sec_timer_reset
,
3307 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3308 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3309 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3310 .accessfn
= gt_stimer_access
,
3311 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3313 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3315 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3316 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3317 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3318 .accessfn
= gt_stimer_access
,
3319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3320 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3324 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3327 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3328 return CP_ACCESS_TRAP
;
3330 return CP_ACCESS_OK
;
3336 * In user-mode most of the generic timer registers are inaccessible
3337 * however modern kernels (4.12+) allow access to cntvct_el0
3340 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3342 ARMCPU
*cpu
= env_archcpu(env
);
3345 * Currently we have no support for QEMUTimer in linux-user so we
3346 * can't call gt_get_countervalue(env), instead we directly
3347 * call the lower level functions.
3349 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3352 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3353 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3354 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3355 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3356 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3357 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3359 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3360 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3361 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3362 .readfn
= gt_virt_cnt_read
,
3368 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3370 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3371 raw_write(env
, ri
, value
);
3372 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3373 raw_write(env
, ri
, value
& 0xfffff6ff);
3375 raw_write(env
, ri
, value
& 0xfffff1ff);
3379 #ifndef CONFIG_USER_ONLY
3380 /* get_phys_addr() isn't present for user-mode-only targets */
3382 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3387 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3388 * Secure EL1 (which can only happen if EL3 is AArch64).
3389 * They are simply UNDEF if executed from NS EL1.
3390 * They function normally from EL2 or EL3.
3392 if (arm_current_el(env
) == 1) {
3393 if (arm_is_secure_below_el3(env
)) {
3394 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3395 return CP_ACCESS_TRAP_EL2
;
3397 return CP_ACCESS_TRAP_EL3
;
3399 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3402 return CP_ACCESS_OK
;
3406 static int par_el1_shareability(GetPhysAddrResult
*res
)
3409 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3410 * memory -- see pseudocode PAREncodeShareability().
3412 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3413 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3416 return res
->cacheattrs
.shareability
;
3419 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3420 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3421 ARMSecuritySpace ss
)
3425 bool format64
= false;
3426 ARMMMUFaultInfo fi
= {};
3427 GetPhysAddrResult res
= {};
3430 * I_MXTJT: Granule protection checks are not performed on the final address
3431 * of a successful translation.
3433 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3437 * ATS operations only do S1 or S1+S2 translations, so we never
3438 * have to deal with the ARMCacheAttrs format for S2 only.
3440 assert(!res
.cacheattrs
.is_s2_format
);
3444 * Some kinds of translation fault must cause exceptions rather
3445 * than being reported in the PAR.
3447 int current_el
= arm_current_el(env
);
3449 uint32_t syn
, fsr
, fsc
;
3450 bool take_exc
= false;
3452 if (fi
.s1ptw
&& current_el
== 1
3453 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3455 * Synchronous stage 2 fault on an access made as part of the
3456 * translation table walk for AT S1E0* or AT S1E1* insn
3457 * executed from NS EL1. If this is a synchronous external abort
3458 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3459 * to EL3. Otherwise the fault is taken as an exception to EL2,
3460 * and HPFAR_EL2 holds the faulting IPA.
3462 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3463 (env
->cp15
.scr_el3
& SCR_EA
)) {
3466 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3467 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3468 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3473 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3475 * Synchronous external aborts during a translation table walk
3476 * are taken as Data Abort exceptions.
3479 if (current_el
== 3) {
3485 target_el
= exception_target_el(env
);
3491 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3492 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3493 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3494 fsr
= arm_fi_to_lfsc(&fi
);
3495 fsc
= extract32(fsr
, 0, 6);
3497 fsr
= arm_fi_to_sfsc(&fi
);
3501 * Report exception with ESR indicating a fault due to a
3502 * translation table walk for a cache maintenance instruction.
3504 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3505 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3506 env
->exception
.vaddress
= value
;
3507 env
->exception
.fsr
= fsr
;
3508 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3514 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3517 * * TTBCR.EAE determines whether the result is returned using the
3518 * 32-bit or the 64-bit PAR format
3519 * * Instructions executed in Hyp mode always use the 64bit format
3521 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3522 * * The Non-secure TTBCR.EAE bit is set to 1
3523 * * The implementation includes EL2, and the value of HCR.VM is 1
3525 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3527 * ATS1Hx always uses the 64bit format.
3529 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3531 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3532 if (mmu_idx
== ARMMMUIdx_E10_0
||
3533 mmu_idx
== ARMMMUIdx_E10_1
||
3534 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3535 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3537 format64
|= arm_current_el(env
) == 2;
3543 /* Create a 64-bit PAR */
3544 par64
= (1 << 11); /* LPAE bit always set */
3546 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3547 if (!res
.f
.attrs
.secure
) {
3548 par64
|= (1 << 9); /* NS */
3550 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3551 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3553 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3556 par64
|= (fsr
& 0x3f) << 1; /* FS */
3558 par64
|= (1 << 9); /* S */
3561 par64
|= (1 << 8); /* PTW */
3566 * fsr is a DFSR/IFSR value for the short descriptor
3567 * translation table format (with WnR always clear).
3568 * Convert it to a 32-bit PAR.
3571 /* We do not set any attribute bits in the PAR */
3572 if (res
.f
.lg_page_size
== 24
3573 && arm_feature(env
, ARM_FEATURE_V7
)) {
3574 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3576 par64
= res
.f
.phys_addr
& 0xfffff000;
3578 if (!res
.f
.attrs
.secure
) {
3579 par64
|= (1 << 9); /* NS */
3582 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3584 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3585 ((fsr
& 0xf) << 1) | 1;
3590 #endif /* CONFIG_TCG */
3592 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3595 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3598 int el
= arm_current_el(env
);
3599 ARMSecuritySpace ss
= arm_security_space(env
);
3601 switch (ri
->opc2
& 6) {
3603 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3606 mmu_idx
= ARMMMUIdx_E3
;
3609 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3612 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3613 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3615 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3619 g_assert_not_reached();
3623 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3626 mmu_idx
= ARMMMUIdx_E10_0
;
3629 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3630 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3633 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3636 g_assert_not_reached();
3640 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3641 mmu_idx
= ARMMMUIdx_E10_1
;
3642 ss
= ARMSS_NonSecure
;
3645 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3646 mmu_idx
= ARMMMUIdx_E10_0
;
3647 ss
= ARMSS_NonSecure
;
3650 g_assert_not_reached();
3653 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3655 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3657 /* Handled by hardware accelerator. */
3658 g_assert_not_reached();
3659 #endif /* CONFIG_TCG */
3662 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3666 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3669 /* There is no SecureEL2 for AArch32. */
3670 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3673 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3675 /* Handled by hardware accelerator. */
3676 g_assert_not_reached();
3677 #endif /* CONFIG_TCG */
3680 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3684 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3685 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3686 * only happen when executing at EL3 because that combination also causes an
3687 * illegal exception return. We don't need to check FEAT_RME either, because
3688 * scr_write() ensures that the NSE bit is not set otherwise.
3690 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3691 return CP_ACCESS_TRAP
;
3693 return CP_ACCESS_OK
;
3696 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3699 if (arm_current_el(env
) == 3 &&
3700 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3701 return CP_ACCESS_TRAP
;
3703 return at_e012_access(env
, ri
, isread
);
3706 static CPAccessResult
at_s1e01_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3709 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_AT
)) {
3710 return CP_ACCESS_TRAP_EL2
;
3712 return at_e012_access(env
, ri
, isread
);
3715 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3719 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3721 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3722 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3724 switch (ri
->opc2
& 6) {
3727 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3728 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3729 mmu_idx
= regime_e20
?
3730 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3732 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3735 case 4: /* AT S1E2R, AT S1E2W */
3736 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3738 case 6: /* AT S1E3R, AT S1E3W */
3739 mmu_idx
= ARMMMUIdx_E3
;
3742 g_assert_not_reached();
3745 case 2: /* AT S1E0R, AT S1E0W */
3746 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3748 case 4: /* AT S12E1R, AT S12E1W */
3749 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3751 case 6: /* AT S12E0R, AT S12E0W */
3752 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3755 g_assert_not_reached();
3758 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3759 mmu_idx
, arm_security_space(env
));
3761 /* Handled by hardware accelerator. */
3762 g_assert_not_reached();
3763 #endif /* CONFIG_TCG */
3767 /* Return basic MPU access permission bits. */
3768 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3775 for (i
= 0; i
< 16; i
+= 2) {
3776 ret
|= (val
>> i
) & mask
;
3782 /* Pad basic MPU access permission bits to extended format. */
3783 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3790 for (i
= 0; i
< 16; i
+= 2) {
3791 ret
|= (val
& mask
) << i
;
3797 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3800 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3803 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3805 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3808 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3811 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3814 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3816 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3819 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3821 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3827 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3831 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3834 ARMCPU
*cpu
= env_archcpu(env
);
3835 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3841 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3842 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3846 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3849 ARMCPU
*cpu
= env_archcpu(env
);
3850 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3852 if (value
>= nrgs
) {
3853 qemu_log_mask(LOG_GUEST_ERROR
,
3854 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3855 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3859 raw_write(env
, ri
, value
);
3862 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3865 ARMCPU
*cpu
= env_archcpu(env
);
3867 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3868 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3871 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3873 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3876 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3879 ARMCPU
*cpu
= env_archcpu(env
);
3881 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3882 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3885 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3887 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3890 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3893 ARMCPU
*cpu
= env_archcpu(env
);
3896 * Ignore writes that would select not implemented region.
3897 * This is architecturally UNPREDICTABLE.
3899 if (value
>= cpu
->pmsav7_dregion
) {
3903 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3906 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3909 ARMCPU
*cpu
= env_archcpu(env
);
3911 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3912 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3915 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3917 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3920 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3923 ARMCPU
*cpu
= env_archcpu(env
);
3925 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3926 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3929 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3931 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3934 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3939 ARMCPU
*cpu
= env_archcpu(env
);
3941 /* Ignore writes to unimplemented regions */
3942 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3943 value
&= MAKE_64BIT_MASK(0, rmax
);
3945 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3947 /* Register alias is only valid for first 32 indexes */
3948 for (n
= 0; n
< rmax
; ++n
) {
3949 bit
= extract32(value
, n
, 1);
3950 env
->pmsav8
.hprlar
[n
] = deposit32(
3951 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3955 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3958 uint32_t result
= 0x0;
3959 ARMCPU
*cpu
= env_archcpu(env
);
3961 /* Register alias is only valid for first 32 indexes */
3962 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3963 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3964 result
|= (0x1 << n
);
3970 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3973 ARMCPU
*cpu
= env_archcpu(env
);
3976 * Ignore writes that would select not implemented region.
3977 * This is architecturally UNPREDICTABLE.
3979 if (value
>= cpu
->pmsav8r_hdregion
) {
3983 env
->pmsav8
.hprselr
= value
;
3986 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3989 ARMCPU
*cpu
= env_archcpu(env
);
3990 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3991 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3993 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3996 if (index
>= cpu
->pmsav8r_hdregion
) {
3999 if (ri
->opc2
& 0x1) {
4000 env
->pmsav8
.hprlar
[index
] = value
;
4002 env
->pmsav8
.hprbar
[index
] = value
;
4005 if (index
>= cpu
->pmsav7_dregion
) {
4008 if (ri
->opc2
& 0x1) {
4009 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
4011 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
4016 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4018 ARMCPU
*cpu
= env_archcpu(env
);
4019 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4020 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4023 if (index
>= cpu
->pmsav8r_hdregion
) {
4026 if (ri
->opc2
& 0x1) {
4027 return env
->pmsav8
.hprlar
[index
];
4029 return env
->pmsav8
.hprbar
[index
];
4032 if (index
>= cpu
->pmsav7_dregion
) {
4035 if (ri
->opc2
& 0x1) {
4036 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4038 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4043 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4045 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4046 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4047 .accessfn
= access_tvm_trvm
,
4048 .readfn
= prbar_read
, .writefn
= prbar_write
},
4050 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4051 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4052 .accessfn
= access_tvm_trvm
,
4053 .readfn
= prlar_read
, .writefn
= prlar_write
},
4054 { .name
= "PRSELR", .resetvalue
= 0,
4055 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4056 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4057 .writefn
= prselr_write
,
4058 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4059 { .name
= "HPRBAR", .resetvalue
= 0,
4060 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4061 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4062 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4064 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4065 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4066 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4067 { .name
= "HPRSELR", .resetvalue
= 0,
4068 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4070 .writefn
= hprselr_write
,
4071 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4073 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4074 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4075 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4078 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4080 * Reset for all these registers is handled in arm_cpu_reset(),
4081 * because the PMSAv7 is also used by M-profile CPUs, which do
4082 * not register cpregs but still need the state to be reset.
4084 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4085 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4086 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4087 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4088 .resetfn
= arm_cp_reset_ignore
},
4089 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4090 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4091 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4092 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4093 .resetfn
= arm_cp_reset_ignore
},
4094 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4095 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4096 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4097 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4098 .resetfn
= arm_cp_reset_ignore
},
4099 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4101 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4102 .writefn
= pmsav7_rgnr_write
,
4103 .resetfn
= arm_cp_reset_ignore
},
4106 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4107 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4108 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4109 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4110 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4111 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4112 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4113 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4114 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4115 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4117 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4119 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4121 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4123 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4125 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4126 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4129 /* Protection region base and size registers */
4130 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4131 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4132 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4133 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4134 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4135 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4136 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4137 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4138 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4139 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4140 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4141 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4142 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4143 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4144 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4145 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4146 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4147 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4148 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4149 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4150 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4151 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4152 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4153 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4156 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4159 ARMCPU
*cpu
= env_archcpu(env
);
4161 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4162 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4164 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4165 * using Long-descriptor translation table format
4167 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4168 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4170 * In an implementation that includes the Security Extensions
4171 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4172 * Short-descriptor translation table format.
4174 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4180 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4182 * With LPAE the TTBCR could result in a change of ASID
4183 * via the TTBCR.A1 bit, so do a TLB flush.
4185 tlb_flush(CPU(cpu
));
4187 raw_write(env
, ri
, value
);
4190 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4193 ARMCPU
*cpu
= env_archcpu(env
);
4195 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4196 tlb_flush(CPU(cpu
));
4197 raw_write(env
, ri
, value
);
4200 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4203 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4204 if (cpreg_field_is_64bit(ri
) &&
4205 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4206 ARMCPU
*cpu
= env_archcpu(env
);
4207 tlb_flush(CPU(cpu
));
4209 raw_write(env
, ri
, value
);
4212 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4216 * If we are running with E2&0 regime, then an ASID is active.
4217 * Flush if that might be changing. Note we're not checking
4218 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4219 * holds the active ASID, only checking the field that might.
4221 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4222 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4223 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4224 ARMMMUIdxBit_E20_2_PAN
|
4226 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4228 raw_write(env
, ri
, value
);
4231 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4234 ARMCPU
*cpu
= env_archcpu(env
);
4235 CPUState
*cs
= CPU(cpu
);
4238 * A change in VMID to the stage2 page table (Stage2) invalidates
4239 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4241 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4242 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4244 raw_write(env
, ri
, value
);
4247 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4248 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4249 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4250 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4251 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4252 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4253 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4254 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4255 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4256 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4257 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4258 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4259 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4260 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4261 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4262 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4264 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4268 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4269 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4270 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4271 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4273 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4274 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4275 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4276 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4277 .fgt
= FGT_TTBR0_EL1
,
4278 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4279 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4280 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4281 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4282 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4283 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4284 .fgt
= FGT_TTBR1_EL1
,
4285 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4286 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4287 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4288 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4289 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4290 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4292 .writefn
= vmsa_tcr_el12_write
,
4293 .raw_writefn
= raw_write
,
4295 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4296 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4297 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4298 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4299 .raw_writefn
= raw_write
,
4300 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4301 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4305 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4306 * qemu tlbs nor adjusting cached masks.
4308 static const ARMCPRegInfo ttbcr2_reginfo
= {
4309 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4310 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4311 .type
= ARM_CP_ALIAS
,
4312 .bank_fieldoffsets
= {
4313 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4314 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4318 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4321 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4322 /* The OS_TYPE bit in this register changes the reported CPUID! */
4323 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4324 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4327 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4330 env
->cp15
.c15_threadid
= value
& 0xffff;
4333 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4336 /* Wait-for-interrupt (deprecated) */
4337 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4340 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4344 * On OMAP there are registers indicating the max/min index of dcache lines
4345 * containing a dirty line; cache flush operations have to reset these.
4347 env
->cp15
.c15_i_max
= 0x000;
4348 env
->cp15
.c15_i_min
= 0xff0;
4351 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4352 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4353 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4354 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4356 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4357 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4358 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4360 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4361 .writefn
= omap_ticonfig_write
},
4362 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4364 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4365 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4366 .access
= PL1_RW
, .resetvalue
= 0xff0,
4367 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4368 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4370 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4371 .writefn
= omap_threadid_write
},
4372 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4373 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4374 .type
= ARM_CP_NO_RAW
,
4375 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4377 * TODO: Peripheral port remap register:
4378 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4379 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4382 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4383 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4384 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4385 .writefn
= omap_cachemaint_write
},
4386 { .name
= "C9", .cp
= 15, .crn
= 9,
4387 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4388 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4391 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4394 env
->cp15
.c15_cpar
= value
& 0x3fff;
4397 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4398 { .name
= "XSCALE_CPAR",
4399 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4400 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4401 .writefn
= xscale_cpar_write
, },
4402 { .name
= "XSCALE_AUXCR",
4403 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4404 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4407 * XScale specific cache-lockdown: since we have no cache we NOP these
4408 * and hope the guest does not really rely on cache behaviour.
4410 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4411 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4412 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4413 { .name
= "XSCALE_UNLOCK_ICACHE",
4414 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4415 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4416 { .name
= "XSCALE_DCACHE_LOCK",
4417 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4418 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4419 { .name
= "XSCALE_UNLOCK_DCACHE",
4420 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4421 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4424 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4426 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4427 * implementation of this implementation-defined space.
4428 * Ideally this should eventually disappear in favour of actually
4429 * implementing the correct behaviour for all cores.
4431 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4432 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4434 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4438 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4439 /* Cache status: RAZ because we have no cache so it's always clean */
4440 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4441 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4445 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4446 /* We never have a block transfer operation in progress */
4447 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4448 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4450 /* The cache ops themselves: these all NOP for QEMU */
4451 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4452 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4453 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4454 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4455 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4456 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4457 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4458 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4459 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4460 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4461 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4462 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4465 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4467 * The cache test-and-clean instructions always return (1 << 30)
4468 * to indicate that there are no dirty cache lines.
4470 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4471 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4472 .resetvalue
= (1 << 30) },
4473 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4474 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4475 .resetvalue
= (1 << 30) },
4478 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4479 /* Ignore ReadBuffer accesses */
4480 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4481 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4482 .access
= PL1_RW
, .resetvalue
= 0,
4483 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4486 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4488 unsigned int cur_el
= arm_current_el(env
);
4490 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4491 return env
->cp15
.vpidr_el2
;
4493 return raw_read(env
, ri
);
4496 static uint64_t mpidr_read_val(CPUARMState
*env
)
4498 ARMCPU
*cpu
= env_archcpu(env
);
4499 uint64_t mpidr
= cpu
->mp_affinity
;
4501 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4502 mpidr
|= (1U << 31);
4504 * Cores which are uniprocessor (non-coherent)
4505 * but still implement the MP extensions set
4506 * bit 30. (For instance, Cortex-R5).
4508 if (cpu
->mp_is_up
) {
4509 mpidr
|= (1u << 30);
4515 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4517 unsigned int cur_el
= arm_current_el(env
);
4519 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4520 return env
->cp15
.vmpidr_el2
;
4522 return mpidr_read_val(env
);
4525 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4527 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4528 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4529 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4530 .fgt
= FGT_AMAIR_EL1
,
4531 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4532 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4533 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4534 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4535 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4536 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4537 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4538 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4539 offsetof(CPUARMState
, cp15
.par_ns
)} },
4540 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4541 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4542 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4543 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4544 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4545 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4546 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4547 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4548 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4549 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4550 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4551 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4554 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4556 return vfp_get_fpcr(env
);
4559 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4562 vfp_set_fpcr(env
, value
);
4565 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4567 return vfp_get_fpsr(env
);
4570 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4573 vfp_set_fpsr(env
, value
);
4576 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4579 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4580 return CP_ACCESS_TRAP
;
4582 return CP_ACCESS_OK
;
4585 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4588 env
->daif
= value
& PSTATE_DAIF
;
4591 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4593 return env
->pstate
& PSTATE_PAN
;
4596 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4599 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4602 static const ARMCPRegInfo pan_reginfo
= {
4603 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4604 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4605 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4606 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4609 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4611 return env
->pstate
& PSTATE_UAO
;
4614 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4617 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4620 static const ARMCPRegInfo uao_reginfo
= {
4621 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4622 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4623 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4624 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4627 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4629 return env
->pstate
& PSTATE_DIT
;
4632 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4635 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4638 static const ARMCPRegInfo dit_reginfo
= {
4639 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4640 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4641 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4642 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4645 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4647 return env
->pstate
& PSTATE_SSBS
;
4650 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4653 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4656 static const ARMCPRegInfo ssbs_reginfo
= {
4657 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4658 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4659 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4660 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4663 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4664 const ARMCPRegInfo
*ri
,
4667 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4668 switch (arm_current_el(env
)) {
4670 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4671 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4672 return CP_ACCESS_TRAP
;
4676 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4677 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4678 return CP_ACCESS_TRAP_EL2
;
4682 return CP_ACCESS_OK
;
4685 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4687 /* Cache invalidate/clean to Point of Unification... */
4688 switch (arm_current_el(env
)) {
4690 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4691 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4692 return CP_ACCESS_TRAP
;
4696 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4697 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4698 return CP_ACCESS_TRAP_EL2
;
4702 return CP_ACCESS_OK
;
4705 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4708 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4711 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4714 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4718 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4719 * Page D4-1736 (DDI0487A.b)
4722 static int vae1_tlbmask(CPUARMState
*env
)
4724 uint64_t hcr
= arm_hcr_el2_eff(env
);
4727 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4728 mask
= ARMMMUIdxBit_E20_2
|
4729 ARMMMUIdxBit_E20_2_PAN
|
4732 mask
= ARMMMUIdxBit_E10_1
|
4733 ARMMMUIdxBit_E10_1_PAN
|
4739 static int vae2_tlbmask(CPUARMState
*env
)
4741 uint64_t hcr
= arm_hcr_el2_eff(env
);
4744 if (hcr
& HCR_E2H
) {
4745 mask
= ARMMMUIdxBit_E20_2
|
4746 ARMMMUIdxBit_E20_2_PAN
|
4749 mask
= ARMMMUIdxBit_E2
;
4754 /* Return 56 if TBI is enabled, 64 otherwise. */
4755 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4758 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4759 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4760 int select
= extract64(addr
, 55, 1);
4762 return (tbi
>> select
) & 1 ? 56 : 64;
4765 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4767 uint64_t hcr
= arm_hcr_el2_eff(env
);
4770 /* Only the regime of the mmu_idx below is significant. */
4771 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4772 mmu_idx
= ARMMMUIdx_E20_0
;
4774 mmu_idx
= ARMMMUIdx_E10_0
;
4777 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4780 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4782 uint64_t hcr
= arm_hcr_el2_eff(env
);
4786 * Only the regime of the mmu_idx below is significant.
4787 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4790 if (hcr
& HCR_E2H
) {
4791 mmu_idx
= ARMMMUIdx_E20_2
;
4793 mmu_idx
= ARMMMUIdx_E2
;
4796 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4799 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4802 CPUState
*cs
= env_cpu(env
);
4803 int mask
= vae1_tlbmask(env
);
4805 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4808 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4811 CPUState
*cs
= env_cpu(env
);
4812 int mask
= vae1_tlbmask(env
);
4814 if (tlb_force_broadcast(env
)) {
4815 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4817 tlb_flush_by_mmuidx(cs
, mask
);
4821 static int e2_tlbmask(CPUARMState
*env
)
4823 return (ARMMMUIdxBit_E20_0
|
4824 ARMMMUIdxBit_E20_2
|
4825 ARMMMUIdxBit_E20_2_PAN
|
4829 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4832 CPUState
*cs
= env_cpu(env
);
4833 int mask
= alle1_tlbmask(env
);
4835 tlb_flush_by_mmuidx(cs
, mask
);
4838 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4841 CPUState
*cs
= env_cpu(env
);
4842 int mask
= e2_tlbmask(env
);
4844 tlb_flush_by_mmuidx(cs
, mask
);
4847 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4850 ARMCPU
*cpu
= env_archcpu(env
);
4851 CPUState
*cs
= CPU(cpu
);
4853 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4856 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4859 CPUState
*cs
= env_cpu(env
);
4860 int mask
= alle1_tlbmask(env
);
4862 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4865 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4868 CPUState
*cs
= env_cpu(env
);
4869 int mask
= e2_tlbmask(env
);
4871 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4874 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4877 CPUState
*cs
= env_cpu(env
);
4879 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4882 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4886 * Invalidate by VA, EL2
4887 * Currently handles both VAE2 and VALE2, since we don't support
4888 * flush-last-level-only.
4890 CPUState
*cs
= env_cpu(env
);
4891 int mask
= vae2_tlbmask(env
);
4892 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4893 int bits
= vae2_tlbbits(env
, pageaddr
);
4895 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4898 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4902 * Invalidate by VA, EL3
4903 * Currently handles both VAE3 and VALE3, since we don't support
4904 * flush-last-level-only.
4906 ARMCPU
*cpu
= env_archcpu(env
);
4907 CPUState
*cs
= CPU(cpu
);
4908 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4910 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4913 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4916 CPUState
*cs
= env_cpu(env
);
4917 int mask
= vae1_tlbmask(env
);
4918 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4919 int bits
= vae1_tlbbits(env
, pageaddr
);
4921 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4924 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4928 * Invalidate by VA, EL1&0 (AArch64 version).
4929 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4930 * since we don't support flush-for-specific-ASID-only or
4931 * flush-last-level-only.
4933 CPUState
*cs
= env_cpu(env
);
4934 int mask
= vae1_tlbmask(env
);
4935 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4936 int bits
= vae1_tlbbits(env
, pageaddr
);
4938 if (tlb_force_broadcast(env
)) {
4939 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4941 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4945 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4948 CPUState
*cs
= env_cpu(env
);
4949 int mask
= vae2_tlbmask(env
);
4950 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4951 int bits
= vae2_tlbbits(env
, pageaddr
);
4953 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4956 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4959 CPUState
*cs
= env_cpu(env
);
4960 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4961 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4963 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4964 ARMMMUIdxBit_E3
, bits
);
4967 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4970 * The MSB of value is the NS field, which only applies if SEL2
4971 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4974 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4975 && arm_is_secure_below_el3(env
)
4976 ? ARMMMUIdxBit_Stage2_S
4977 : ARMMMUIdxBit_Stage2
);
4980 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4983 CPUState
*cs
= env_cpu(env
);
4984 int mask
= ipas2e1_tlbmask(env
, value
);
4985 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4987 if (tlb_force_broadcast(env
)) {
4988 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4990 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4994 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4997 CPUState
*cs
= env_cpu(env
);
4998 int mask
= ipas2e1_tlbmask(env
, value
);
4999 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5001 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5004 #ifdef TARGET_AARCH64
5010 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
5013 * Note that the TLBI range TG field encoding differs from both
5014 * TG0 and TG1 encodings.
5028 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5031 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5032 /* Extract one bit to represent the va selector in use. */
5033 uint64_t select
= sextract64(value
, 36, 1);
5034 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5035 TLBIRange ret
= { };
5036 ARMGranuleSize gran
;
5038 page_size_granule
= extract64(value
, 46, 2);
5039 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5041 /* The granule encoded in value must match the granule in use. */
5042 if (gran
!= param
.gran
) {
5043 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5048 page_shift
= arm_granule_bits(gran
);
5049 num
= extract64(value
, 39, 5);
5050 scale
= extract64(value
, 44, 2);
5051 exponent
= (5 * scale
) + 1;
5053 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5056 ret
.base
= sextract64(value
, 0, 37);
5058 ret
.base
= extract64(value
, 0, 37);
5062 * With DS=1, BaseADDR is always shifted 16 so that it is able
5063 * to address all 52 va bits. The input address is perforce
5064 * aligned on a 64k boundary regardless of translation granule.
5068 ret
.base
<<= page_shift
;
5073 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5074 int idxmap
, bool synced
)
5076 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5080 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5081 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5084 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5090 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5091 range
.length
, idxmap
, bits
);
5095 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5096 const ARMCPRegInfo
*ri
,
5100 * Invalidate by VA range, EL1&0.
5101 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5102 * since we don't support flush-for-specific-ASID-only or
5103 * flush-last-level-only.
5106 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5107 tlb_force_broadcast(env
));
5110 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5111 const ARMCPRegInfo
*ri
,
5115 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5116 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5117 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5118 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5119 * shareable specific flushes.
5122 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5125 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5126 const ARMCPRegInfo
*ri
,
5130 * Invalidate by VA range, EL2.
5131 * Currently handles all of RVAE2 and RVALE2,
5132 * since we don't support flush-for-specific-ASID-only or
5133 * flush-last-level-only.
5136 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5137 tlb_force_broadcast(env
));
5142 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5143 const ARMCPRegInfo
*ri
,
5147 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5148 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5149 * since we don't support flush-for-specific-ASID-only,
5150 * flush-last-level-only or inner/outer shareable specific flushes.
5153 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5157 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5158 const ARMCPRegInfo
*ri
,
5162 * Invalidate by VA range, EL3.
5163 * Currently handles all of RVAE3 and RVALE3,
5164 * since we don't support flush-for-specific-ASID-only or
5165 * flush-last-level-only.
5168 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5171 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5172 const ARMCPRegInfo
*ri
,
5176 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5177 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5178 * since we don't support flush-for-specific-ASID-only,
5179 * flush-last-level-only or inner/outer specific flushes.
5182 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5185 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5188 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5189 tlb_force_broadcast(env
));
5192 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5193 const ARMCPRegInfo
*ri
,
5196 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5200 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5203 int cur_el
= arm_current_el(env
);
5206 uint64_t hcr
= arm_hcr_el2_eff(env
);
5209 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5210 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5211 return CP_ACCESS_TRAP_EL2
;
5214 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5215 return CP_ACCESS_TRAP
;
5217 if (hcr
& HCR_TDZ
) {
5218 return CP_ACCESS_TRAP_EL2
;
5221 } else if (hcr
& HCR_TDZ
) {
5222 return CP_ACCESS_TRAP_EL2
;
5225 return CP_ACCESS_OK
;
5228 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5230 ARMCPU
*cpu
= env_archcpu(env
);
5231 int dzp_bit
= 1 << 4;
5233 /* DZP indicates whether DC ZVA access is allowed */
5234 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5237 return cpu
->dcz_blocksize
| dzp_bit
;
5240 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5243 if (!(env
->pstate
& PSTATE_SP
)) {
5245 * Access to SP_EL0 is undefined if it's being used as
5246 * the stack pointer.
5248 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5250 return CP_ACCESS_OK
;
5253 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5255 return env
->pstate
& PSTATE_SP
;
5258 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5260 update_spsel(env
, val
);
5263 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5266 ARMCPU
*cpu
= env_archcpu(env
);
5268 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5269 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5273 /* ??? Lots of these bits are not implemented. */
5275 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5276 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5277 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5279 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5280 SCTLR_ATA0
| SCTLR_ATA
);
5284 if (raw_read(env
, ri
) == value
) {
5286 * Skip the TLB flush if nothing actually changed; Linux likes
5287 * to do a lot of pointless SCTLR writes.
5292 raw_write(env
, ri
, value
);
5294 /* This may enable/disable the MMU, so do a TLB flush. */
5295 tlb_flush(CPU(cpu
));
5297 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5299 * Normally we would always end the TB on an SCTLR write; see the
5300 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5301 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5302 * of hflags from the translator, so do it here.
5304 arm_rebuild_hflags(env
);
5308 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5312 * Some MDCR_EL3 bits affect whether PMU counters are running:
5313 * if we are trying to change any of those then we must
5314 * bracket this update with PMU start/finish calls.
5316 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5321 env
->cp15
.mdcr_el3
= value
;
5327 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5330 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5331 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5334 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5338 * Some MDCR_EL2 bits affect whether PMU counters are running:
5339 * if we are trying to change any of those then we must
5340 * bracket this update with PMU start/finish calls.
5342 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5347 env
->cp15
.mdcr_el2
= value
;
5353 #ifdef CONFIG_USER_ONLY
5355 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5356 * code to get around W^X restrictions, where one region is writable and the
5357 * other is executable.
5359 * Since the executable region is never written to we cannot detect code
5360 * changes when running in user mode, and rely on the emulated JIT telling us
5361 * that the code has changed by executing this instruction.
5363 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5366 uint64_t icache_line_mask
, start_address
, end_address
;
5369 cpu
= env_archcpu(env
);
5371 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5372 start_address
= value
& ~icache_line_mask
;
5373 end_address
= value
| icache_line_mask
;
5377 tb_invalidate_phys_range(start_address
, end_address
);
5383 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5385 * Minimal set of EL0-visible registers. This will need to be expanded
5386 * significantly for system emulation of AArch64 CPUs.
5388 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5389 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5390 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5391 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5392 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5393 .type
= ARM_CP_NO_RAW
,
5394 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5395 .fieldoffset
= offsetof(CPUARMState
, daif
),
5396 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5397 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5398 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5399 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5400 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5401 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5402 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5403 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5404 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5405 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5406 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5407 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5408 .fgt
= FGT_DCZID_EL0
,
5409 .readfn
= aa64_dczid_read
},
5410 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5411 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5412 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5413 #ifndef CONFIG_USER_ONLY
5414 /* Avoid overhead of an access check that always passes in user-mode */
5415 .accessfn
= aa64_zva_access
,
5419 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5420 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5421 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5423 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5424 * don't emulate caches.
5426 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5427 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5428 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5429 .fgt
= FGT_ICIALLUIS
,
5430 .accessfn
= access_ticab
},
5431 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5432 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5433 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5435 .accessfn
= access_tocu
},
5436 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5437 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5440 .accessfn
= access_tocu
,
5441 #ifdef CONFIG_USER_ONLY
5442 .type
= ARM_CP_NO_RAW
,
5443 .writefn
= ic_ivau_write
5448 /* Cache ops: all NOPs since we don't emulate caches */
5449 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5450 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5451 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5453 .type
= ARM_CP_NOP
},
5454 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5455 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5457 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5458 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5459 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5460 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5462 .accessfn
= aa64_cacheop_poc_access
},
5463 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5464 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5466 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5467 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5468 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5469 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5471 .accessfn
= access_tocu
},
5472 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5473 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5474 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5476 .accessfn
= aa64_cacheop_poc_access
},
5477 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5478 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5480 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5481 /* TLBI operations */
5482 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5483 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5484 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5485 .fgt
= FGT_TLBIVMALLE1IS
,
5486 .writefn
= tlbi_aa64_vmalle1is_write
},
5487 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5488 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5489 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5490 .fgt
= FGT_TLBIVAE1IS
,
5491 .writefn
= tlbi_aa64_vae1is_write
},
5492 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5493 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5494 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5495 .fgt
= FGT_TLBIASIDE1IS
,
5496 .writefn
= tlbi_aa64_vmalle1is_write
},
5497 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5498 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5499 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5500 .fgt
= FGT_TLBIVAAE1IS
,
5501 .writefn
= tlbi_aa64_vae1is_write
},
5502 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5503 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5504 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5505 .fgt
= FGT_TLBIVALE1IS
,
5506 .writefn
= tlbi_aa64_vae1is_write
},
5507 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5508 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5509 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5510 .fgt
= FGT_TLBIVAALE1IS
,
5511 .writefn
= tlbi_aa64_vae1is_write
},
5512 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5513 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5514 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5515 .fgt
= FGT_TLBIVMALLE1
,
5516 .writefn
= tlbi_aa64_vmalle1_write
},
5517 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5518 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5519 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5520 .fgt
= FGT_TLBIVAE1
,
5521 .writefn
= tlbi_aa64_vae1_write
},
5522 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5523 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5524 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5525 .fgt
= FGT_TLBIASIDE1
,
5526 .writefn
= tlbi_aa64_vmalle1_write
},
5527 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5528 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5529 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5530 .fgt
= FGT_TLBIVAAE1
,
5531 .writefn
= tlbi_aa64_vae1_write
},
5532 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5533 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5534 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5535 .fgt
= FGT_TLBIVALE1
,
5536 .writefn
= tlbi_aa64_vae1_write
},
5537 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5538 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5539 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5540 .fgt
= FGT_TLBIVAALE1
,
5541 .writefn
= tlbi_aa64_vae1_write
},
5542 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5543 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5544 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5545 .writefn
= tlbi_aa64_ipas2e1is_write
},
5546 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5547 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5548 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5549 .writefn
= tlbi_aa64_ipas2e1is_write
},
5550 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5551 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5552 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5553 .writefn
= tlbi_aa64_alle1is_write
},
5554 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5555 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5556 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5557 .writefn
= tlbi_aa64_alle1is_write
},
5558 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5559 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5560 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5561 .writefn
= tlbi_aa64_ipas2e1_write
},
5562 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5563 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5564 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5565 .writefn
= tlbi_aa64_ipas2e1_write
},
5566 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5567 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5568 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5569 .writefn
= tlbi_aa64_alle1_write
},
5570 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5571 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5572 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5573 .writefn
= tlbi_aa64_alle1is_write
},
5574 #ifndef CONFIG_USER_ONLY
5575 /* 64 bit address translation operations */
5576 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5578 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5580 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5581 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5582 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5583 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5585 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5586 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5587 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5588 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5590 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5591 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5592 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5593 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5595 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5596 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5597 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5598 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5599 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5600 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5601 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5602 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5603 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5604 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5605 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5606 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5607 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5608 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5609 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5610 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5611 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5612 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5613 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5614 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5615 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5616 .writefn
= ats_write64
},
5617 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5618 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5619 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5620 .writefn
= ats_write64
},
5621 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5622 .type
= ARM_CP_ALIAS
,
5623 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5624 .access
= PL1_RW
, .resetvalue
= 0,
5626 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5627 .writefn
= par_write
},
5629 /* TLB invalidate last level of translation table walk */
5630 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5631 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5632 .writefn
= tlbimva_is_write
},
5633 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5634 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5635 .writefn
= tlbimvaa_is_write
},
5636 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5637 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5638 .writefn
= tlbimva_write
},
5639 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5640 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5641 .writefn
= tlbimvaa_write
},
5642 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5643 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5644 .writefn
= tlbimva_hyp_write
},
5645 { .name
= "TLBIMVALHIS",
5646 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5647 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5648 .writefn
= tlbimva_hyp_is_write
},
5649 { .name
= "TLBIIPAS2",
5650 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5651 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5652 .writefn
= tlbiipas2_hyp_write
},
5653 { .name
= "TLBIIPAS2IS",
5654 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5655 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5656 .writefn
= tlbiipas2is_hyp_write
},
5657 { .name
= "TLBIIPAS2L",
5658 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5659 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5660 .writefn
= tlbiipas2_hyp_write
},
5661 { .name
= "TLBIIPAS2LIS",
5662 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5663 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5664 .writefn
= tlbiipas2is_hyp_write
},
5665 /* 32 bit cache operations */
5666 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5667 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5668 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5669 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5670 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5671 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5672 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5673 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5674 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5675 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5676 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5677 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5678 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5679 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5680 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5681 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5682 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5683 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5684 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5685 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5686 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5687 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5688 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5689 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5690 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5691 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5692 /* MMU Domain access control / MPU write buffer control */
5693 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5694 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5695 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5696 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5697 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5698 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5699 .type
= ARM_CP_ALIAS
,
5700 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5702 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5703 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5704 .type
= ARM_CP_ALIAS
,
5705 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5707 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5709 * We rely on the access checks not allowing the guest to write to the
5710 * state field when SPSel indicates that it's being used as the stack
5713 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5714 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5715 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5716 .type
= ARM_CP_ALIAS
,
5717 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5718 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5719 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5720 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5721 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5722 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5723 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5724 .type
= ARM_CP_NO_RAW
,
5725 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5726 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5727 .type
= ARM_CP_ALIAS
,
5728 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5730 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5731 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5732 .type
= ARM_CP_ALIAS
,
5733 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5735 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5736 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5737 .type
= ARM_CP_ALIAS
,
5738 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5740 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5741 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5742 .type
= ARM_CP_ALIAS
,
5743 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5745 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5746 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5748 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5751 .writefn
= mdcr_el3_write
,
5752 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5753 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5754 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5755 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5756 .writefn
= sdcr_write
,
5757 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5760 /* These are present only when EL1 supports AArch32 */
5761 static const ARMCPRegInfo v8_aa32_el1_reginfo
[] = {
5762 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5763 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5765 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5766 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5767 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5768 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5769 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5770 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5771 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5772 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5773 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5774 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5775 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5778 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5780 ARMCPU
*cpu
= env_archcpu(env
);
5782 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5783 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5785 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5788 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5789 valid_mask
&= ~HCR_HCD
;
5790 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5792 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5793 * However, if we're using the SMC PSCI conduit then QEMU is
5794 * effectively acting like EL3 firmware and so the guest at
5795 * EL2 should retain the ability to prevent EL1 from being
5796 * able to make SMC calls into the ersatz firmware, so in
5797 * that case HCR.TSC should be read/write.
5799 valid_mask
&= ~HCR_TSC
;
5802 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5803 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5804 valid_mask
|= HCR_E2H
;
5806 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5807 valid_mask
|= HCR_TERR
| HCR_TEA
;
5809 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5810 valid_mask
|= HCR_TLOR
;
5812 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5813 valid_mask
|= HCR_API
| HCR_APK
;
5815 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5816 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5818 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5819 valid_mask
|= HCR_ENSCXT
;
5821 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5822 valid_mask
|= HCR_FWB
;
5824 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5825 valid_mask
|= HCR_GPF
;
5827 if (cpu_isar_feature(aa64_nv
, cpu
)) {
5828 valid_mask
|= HCR_NV
| HCR_NV1
| HCR_AT
;
5832 if (cpu_isar_feature(any_evt
, cpu
)) {
5833 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5834 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5835 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5838 /* Clear RES0 bits. */
5839 value
&= valid_mask
;
5842 * These bits change the MMU setup:
5843 * HCR_VM enables stage 2 translation
5844 * HCR_PTW forbids certain page-table setups
5845 * HCR_DC disables stage1 and enables stage2 translation
5846 * HCR_DCT enables tagging on (disabled) stage1 translation
5847 * HCR_FWB changes the interpretation of stage2 descriptor bits
5848 * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
5850 if ((env
->cp15
.hcr_el2
^ value
) &
5851 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
| HCR_NV
| HCR_NV1
)) {
5852 tlb_flush(CPU(cpu
));
5854 env
->cp15
.hcr_el2
= value
;
5857 * Updates to VI and VF require us to update the status of
5858 * virtual interrupts, which are the logical OR of these bits
5859 * and the state of the input lines from the GIC. (This requires
5860 * that we have the BQL, which is done by marking the
5861 * reginfo structs as ARM_CP_IO.)
5862 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5863 * possible for it to be taken immediately, because VIRQ and
5864 * VFIQ are masked unless running at EL0 or EL1, and HCR
5865 * can only be written at EL2.
5867 g_assert(bql_locked());
5868 arm_cpu_update_virq(cpu
);
5869 arm_cpu_update_vfiq(cpu
);
5870 arm_cpu_update_vserr(cpu
);
5873 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5875 do_hcr_write(env
, value
, 0);
5878 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5881 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5882 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5883 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5886 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5889 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5890 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5891 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5895 * Return the effective value of HCR_EL2, at the given security state.
5896 * Bits that are not included here:
5897 * RW (read from SCR_EL3.RW as needed)
5899 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5901 uint64_t ret
= env
->cp15
.hcr_el2
;
5903 assert(space
!= ARMSS_Root
);
5905 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5907 * "This register has no effect if EL2 is not enabled in the
5908 * current Security state". This is ARMv8.4-SecEL2 speak for
5909 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5911 * Prior to that, the language was "In an implementation that
5912 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5913 * as if this field is 0 for all purposes other than a direct
5914 * read or write access of HCR_EL2". With lots of enumeration
5915 * on a per-field basis. In current QEMU, this is condition
5916 * is arm_is_secure_below_el3.
5918 * Since the v8.4 language applies to the entire register, and
5919 * appears to be backward compatible, use that.
5925 * For a cpu that supports both aarch64 and aarch32, we can set bits
5926 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5927 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5929 if (!arm_el_is_aa64(env
, 2)) {
5930 uint64_t aa32_valid
;
5933 * These bits are up-to-date as of ARMv8.6.
5934 * For HCR, it's easiest to list just the 2 bits that are invalid.
5935 * For HCR2, list those that are valid.
5937 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5938 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5939 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5943 if (ret
& HCR_TGE
) {
5944 /* These bits are up-to-date as of ARMv8.6. */
5945 if (ret
& HCR_E2H
) {
5946 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5947 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5948 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5949 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5950 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5951 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5953 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5955 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5956 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5957 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5964 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5966 if (arm_feature(env
, ARM_FEATURE_M
)) {
5969 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
5973 * Corresponds to ARM pseudocode function ELIsInHost().
5975 bool el_is_in_host(CPUARMState
*env
, int el
)
5980 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5981 * Perform the simplest bit tests first, and validate EL2 afterward.
5984 return false; /* EL1 or EL3 */
5988 * Note that hcr_write() checks isar_feature_aa64_vh(),
5989 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5991 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5992 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5996 /* TGE and/or E2H set: double check those bits are currently legal. */
5997 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
6000 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6003 uint64_t valid_mask
= 0;
6005 /* FEAT_MOPS adds MSCEn and MCE2 */
6006 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6007 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
6010 /* Clear RES0 bits. */
6011 env
->cp15
.hcrx_el2
= value
& valid_mask
;
6014 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6017 if (arm_current_el(env
) < 3
6018 && arm_feature(env
, ARM_FEATURE_EL3
)
6019 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6020 return CP_ACCESS_TRAP_EL3
;
6022 return CP_ACCESS_OK
;
6025 static const ARMCPRegInfo hcrx_el2_reginfo
= {
6026 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
6027 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
6028 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
6029 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
6032 /* Return the effective value of HCRX_EL2. */
6033 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
6036 * The bits in this register behave as 0 for all purposes other than
6037 * direct reads of the register if SCR_EL3.HXEn is 0.
6038 * If EL2 is not enabled in the current security state, then the
6039 * bit may behave as if 0, or as if 1, depending on the bit.
6040 * For the moment, we treat the EL2-disabled case as taking
6041 * priority over the HXEn-disabled case. This is true for the only
6042 * bit for a feature which we implement where the answer is different
6043 * for the two cases (MSCEn for FEAT_MOPS).
6044 * This may need to be revisited for future bits.
6046 if (!arm_is_el2_enabled(env
)) {
6048 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6049 /* MSCEn behaves as 1 if EL2 is not enabled */
6054 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6057 return env
->cp15
.hcrx_el2
;
6060 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6064 * For A-profile AArch32 EL3, if NSACR.CP10
6065 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6067 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6068 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6069 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6070 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6072 env
->cp15
.cptr_el
[2] = value
;
6075 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6078 * For A-profile AArch32 EL3, if NSACR.CP10
6079 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6081 uint64_t value
= env
->cp15
.cptr_el
[2];
6083 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6084 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6085 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6090 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6091 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6093 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6094 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6095 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6096 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6097 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6098 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6099 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6100 .writefn
= hcr_writelow
},
6101 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6102 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6103 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6104 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6105 .type
= ARM_CP_ALIAS
,
6106 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6108 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6109 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6110 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6111 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6112 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6113 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6114 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6115 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6116 .type
= ARM_CP_ALIAS
,
6117 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6119 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6120 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6121 .type
= ARM_CP_ALIAS
,
6122 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6124 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6125 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6126 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6127 .access
= PL2_RW
, .writefn
= vbar_write
,
6128 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6130 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6131 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6132 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6133 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6134 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6135 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6136 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6137 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6138 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6139 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6140 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6141 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6143 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6144 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6145 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6146 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6147 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6148 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6149 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6151 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6152 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6153 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6154 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6156 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6157 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6158 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6160 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6161 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6162 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6164 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6165 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6166 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6167 .raw_writefn
= raw_write
,
6168 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6169 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6170 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6171 .type
= ARM_CP_ALIAS
,
6172 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6173 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6174 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6175 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6177 /* no .writefn needed as this can't cause an ASID change */
6178 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6179 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6180 .cp
= 15, .opc1
= 6, .crm
= 2,
6181 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6182 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6183 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6184 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6185 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6186 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6187 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6188 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6189 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6190 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6191 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6192 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6193 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6194 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6195 .access
= PL2_RW
, .resetvalue
= 0,
6196 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6197 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6198 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6199 .access
= PL2_RW
, .resetvalue
= 0,
6200 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6201 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6202 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6203 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6204 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6205 { .name
= "TLBIALLNSNH",
6206 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6207 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6208 .writefn
= tlbiall_nsnh_write
},
6209 { .name
= "TLBIALLNSNHIS",
6210 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6211 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6212 .writefn
= tlbiall_nsnh_is_write
},
6213 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6214 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6215 .writefn
= tlbiall_hyp_write
},
6216 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6217 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6218 .writefn
= tlbiall_hyp_is_write
},
6219 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6220 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6221 .writefn
= tlbimva_hyp_write
},
6222 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6223 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6224 .writefn
= tlbimva_hyp_is_write
},
6225 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6226 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6227 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6228 .writefn
= tlbi_aa64_alle2_write
},
6229 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6230 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6231 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6232 .writefn
= tlbi_aa64_vae2_write
},
6233 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6234 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6235 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6236 .writefn
= tlbi_aa64_vae2_write
},
6237 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6238 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6239 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6240 .writefn
= tlbi_aa64_alle2is_write
},
6241 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6242 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6243 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6244 .writefn
= tlbi_aa64_vae2is_write
},
6245 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6246 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6247 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6248 .writefn
= tlbi_aa64_vae2is_write
},
6249 #ifndef CONFIG_USER_ONLY
6251 * Unlike the other EL2-related AT operations, these must
6252 * UNDEF from EL3 if EL2 is not implemented, which is why we
6253 * define them here rather than with the rest of the AT ops.
6255 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6256 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6257 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6258 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6259 .writefn
= ats_write64
},
6260 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6261 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6262 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6263 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6264 .writefn
= ats_write64
},
6266 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6267 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6268 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6269 * to behave as if SCR.NS was 1.
6271 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6273 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6274 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6276 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6277 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6278 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6280 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6281 * reset values as IMPDEF. We choose to reset to 3 to comply with
6282 * both ARMv7 and ARMv8.
6284 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6285 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6286 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6287 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6288 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6289 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6290 .writefn
= gt_cntvoff_write
,
6291 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6292 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6293 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6294 .writefn
= gt_cntvoff_write
,
6295 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6296 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6297 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6298 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6299 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6300 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6301 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6302 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6303 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6304 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6305 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6306 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6307 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6308 .resetfn
= gt_hyp_timer_reset
,
6309 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6310 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6312 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6314 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6316 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6318 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6319 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6320 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6321 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6322 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6323 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6325 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6326 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6327 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6329 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6332 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6333 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6334 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6335 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6337 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6338 .writefn
= hcr_writehigh
},
6341 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6344 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6345 return CP_ACCESS_OK
;
6347 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6350 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6351 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6352 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6353 .access
= PL2_RW
, .accessfn
= sel2_access
,
6354 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6355 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6356 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6357 .access
= PL2_RW
, .accessfn
= sel2_access
,
6358 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6361 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6365 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6366 * At Secure EL1 it traps to EL3 or EL2.
6368 if (arm_current_el(env
) == 3) {
6369 return CP_ACCESS_OK
;
6371 if (arm_is_secure_below_el3(env
)) {
6372 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6373 return CP_ACCESS_TRAP_EL2
;
6375 return CP_ACCESS_TRAP_EL3
;
6377 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6379 return CP_ACCESS_OK
;
6381 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6384 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6385 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6386 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6387 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6388 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6389 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6390 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6391 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6392 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6393 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6394 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6395 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6396 .access
= PL3_RW
, .resetvalue
= 0,
6397 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6399 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6400 .access
= PL3_RW
, .resetvalue
= 0,
6401 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6402 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6403 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6404 .writefn
= vbar_write
, .resetvalue
= 0,
6405 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6406 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6407 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6408 .access
= PL3_RW
, .resetvalue
= 0,
6409 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6410 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6411 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6413 /* no .writefn needed as this can't cause an ASID change */
6415 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6416 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6417 .type
= ARM_CP_ALIAS
,
6418 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6420 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6421 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6422 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6423 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6424 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6425 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6426 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6427 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6428 .type
= ARM_CP_ALIAS
,
6429 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6431 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6432 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6433 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6434 .access
= PL3_RW
, .writefn
= vbar_write
,
6435 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6437 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6438 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6439 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6440 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6441 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6442 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6443 .access
= PL3_RW
, .resetvalue
= 0,
6444 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6445 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6446 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6447 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6449 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6450 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6451 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6453 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6454 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6455 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6457 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6458 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6459 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6460 .writefn
= tlbi_aa64_alle3is_write
},
6461 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6462 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6463 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6464 .writefn
= tlbi_aa64_vae3is_write
},
6465 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6466 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6467 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6468 .writefn
= tlbi_aa64_vae3is_write
},
6469 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6470 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6471 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6472 .writefn
= tlbi_aa64_alle3_write
},
6473 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6474 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6475 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6476 .writefn
= tlbi_aa64_vae3_write
},
6477 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6478 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6479 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6480 .writefn
= tlbi_aa64_vae3_write
},
6483 #ifndef CONFIG_USER_ONLY
6484 /* Test if system register redirection is to occur in the current state. */
6485 static bool redirect_for_e2h(CPUARMState
*env
)
6487 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6490 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6494 if (redirect_for_e2h(env
)) {
6495 /* Switch to the saved EL2 version of the register. */
6497 readfn
= ri
->readfn
;
6499 readfn
= ri
->orig_readfn
;
6501 if (readfn
== NULL
) {
6504 return readfn(env
, ri
);
6507 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6512 if (redirect_for_e2h(env
)) {
6513 /* Switch to the saved EL2 version of the register. */
6515 writefn
= ri
->writefn
;
6517 writefn
= ri
->orig_writefn
;
6519 if (writefn
== NULL
) {
6520 writefn
= raw_write
;
6522 writefn(env
, ri
, value
);
6525 static uint64_t el2_e2h_e12_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6527 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6528 return ri
->orig_readfn(env
, ri
->opaque
);
6531 static void el2_e2h_e12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6534 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6535 return ri
->orig_writefn(env
, ri
->opaque
, value
);
6538 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6541 uint32_t src_key
, dst_key
, new_key
;
6542 const char *src_name
, *dst_name
, *new_name
;
6543 bool (*feature
)(const ARMISARegisters
*id
);
6546 #define K(op0, op1, crn, crm, op2) \
6547 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6549 static const struct E2HAlias aliases
[] = {
6550 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6551 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6552 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6553 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6554 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6555 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6556 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6557 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6558 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6559 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6560 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6561 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6562 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6563 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6564 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6565 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6566 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6567 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6568 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6569 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6570 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6571 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6572 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6573 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6574 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6575 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6576 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6577 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6578 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6579 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6580 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6581 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6584 * Note that redirection of ZCR is mentioned in the description
6585 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6586 * not in the summary table.
6588 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6589 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6590 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6591 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6593 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6594 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6596 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6597 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6598 isar_feature_aa64_scxtnum
},
6600 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6601 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6607 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6608 const struct E2HAlias
*a
= &aliases
[i
];
6609 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6612 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6616 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6617 (gpointer
)(uintptr_t)a
->src_key
);
6618 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6619 (gpointer
)(uintptr_t)a
->dst_key
);
6620 g_assert(src_reg
!= NULL
);
6621 g_assert(dst_reg
!= NULL
);
6623 /* Cross-compare names to detect typos in the keys. */
6624 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6625 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6627 /* None of the core system registers use opaque; we will. */
6628 g_assert(src_reg
->opaque
== NULL
);
6630 /* Create alias before redirection so we dup the right data. */
6631 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6633 new_reg
->name
= a
->new_name
;
6634 new_reg
->type
|= ARM_CP_ALIAS
;
6635 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6636 new_reg
->access
&= PL2_RW
| PL3_RW
;
6637 /* The new_reg op fields are as per new_key, not the target reg */
6638 new_reg
->crn
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRN_MASK
)
6639 >> CP_REG_ARM64_SYSREG_CRN_SHIFT
;
6640 new_reg
->crm
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRM_MASK
)
6641 >> CP_REG_ARM64_SYSREG_CRM_SHIFT
;
6642 new_reg
->opc0
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP0_MASK
)
6643 >> CP_REG_ARM64_SYSREG_OP0_SHIFT
;
6644 new_reg
->opc1
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP1_MASK
)
6645 >> CP_REG_ARM64_SYSREG_OP1_SHIFT
;
6646 new_reg
->opc2
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP2_MASK
)
6647 >> CP_REG_ARM64_SYSREG_OP2_SHIFT
;
6648 new_reg
->opaque
= src_reg
;
6649 new_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6650 new_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6651 if (!new_reg
->raw_readfn
) {
6652 new_reg
->raw_readfn
= raw_read
;
6654 if (!new_reg
->raw_writefn
) {
6655 new_reg
->raw_writefn
= raw_write
;
6657 new_reg
->readfn
= el2_e2h_e12_read
;
6658 new_reg
->writefn
= el2_e2h_e12_write
;
6660 ok
= g_hash_table_insert(cpu
->cp_regs
,
6661 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6664 src_reg
->opaque
= dst_reg
;
6665 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6666 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6667 if (!src_reg
->raw_readfn
) {
6668 src_reg
->raw_readfn
= raw_read
;
6670 if (!src_reg
->raw_writefn
) {
6671 src_reg
->raw_writefn
= raw_write
;
6673 src_reg
->readfn
= el2_e2h_read
;
6674 src_reg
->writefn
= el2_e2h_write
;
6679 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6682 int cur_el
= arm_current_el(env
);
6685 uint64_t hcr
= arm_hcr_el2_eff(env
);
6688 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6689 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6690 return CP_ACCESS_TRAP_EL2
;
6693 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6694 return CP_ACCESS_TRAP
;
6696 if (hcr
& HCR_TID2
) {
6697 return CP_ACCESS_TRAP_EL2
;
6700 } else if (hcr
& HCR_TID2
) {
6701 return CP_ACCESS_TRAP_EL2
;
6705 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6706 return CP_ACCESS_TRAP_EL2
;
6709 return CP_ACCESS_OK
;
6713 * Check for traps to RAS registers, which are controlled
6714 * by HCR_EL2.TERR and SCR_EL3.TERR.
6716 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6719 int el
= arm_current_el(env
);
6721 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6722 return CP_ACCESS_TRAP_EL2
;
6724 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6725 return CP_ACCESS_TRAP_EL3
;
6727 return CP_ACCESS_OK
;
6730 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6732 int el
= arm_current_el(env
);
6734 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6735 return env
->cp15
.vdisr_el2
;
6737 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6738 return 0; /* RAZ/WI */
6740 return env
->cp15
.disr_el1
;
6743 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6745 int el
= arm_current_el(env
);
6747 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6748 env
->cp15
.vdisr_el2
= val
;
6751 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6752 return; /* RAZ/WI */
6754 env
->cp15
.disr_el1
= val
;
6758 * Minimal RAS implementation with no Error Records.
6759 * Which means that all of the Error Record registers:
6767 * ERXPFGCDN_EL1 (RASv1p1)
6768 * ERXPFGCTL_EL1 (RASv1p1)
6769 * ERXPFGF_EL1 (RASv1p1)
6773 * may generate UNDEFINED, which is the effect we get by not
6774 * listing them at all.
6776 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6777 * is higher priority than FGT-to-EL2 so we do not need to list them
6778 * in order to check for an FGT.
6780 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6781 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6782 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6783 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6784 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6785 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6786 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6787 .access
= PL1_R
, .accessfn
= access_terr
,
6788 .fgt
= FGT_ERRIDR_EL1
,
6789 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6790 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6791 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6792 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6793 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6794 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6795 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6799 * Return the exception level to which exceptions should be taken
6800 * via SVEAccessTrap. This excludes the check for whether the exception
6801 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6802 * be found by testing 0 < fp_exception_el < sve_exception_el.
6804 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6805 * pseudocode does *not* separate out the FP trap checks, but has them
6806 * all in one function.
6808 int sve_exception_el(CPUARMState
*env
, int el
)
6810 #ifndef CONFIG_USER_ONLY
6811 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6812 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6824 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6825 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6826 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6827 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6829 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6838 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6844 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6845 if (arm_feature(env
, ARM_FEATURE_EL3
)
6846 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6854 * Return the exception level to which exceptions should be taken for SME.
6855 * C.f. the ARM pseudocode function CheckSMEAccess.
6857 int sme_exception_el(CPUARMState
*env
, int el
)
6859 #ifndef CONFIG_USER_ONLY
6860 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6861 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6873 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6874 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6875 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6876 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6878 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6887 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6893 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6894 if (arm_feature(env
, ARM_FEATURE_EL3
)
6895 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6903 * Given that SVE is enabled, return the vector length for EL.
6905 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6907 ARMCPU
*cpu
= env_archcpu(env
);
6908 uint64_t *cr
= env
->vfp
.zcr_el
;
6909 uint32_t map
= cpu
->sve_vq
.map
;
6910 uint32_t len
= ARM_MAX_VQ
- 1;
6913 cr
= env
->vfp
.smcr_el
;
6914 map
= cpu
->sme_vq
.map
;
6917 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6918 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6920 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6921 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6923 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6924 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6927 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6929 return 31 - clz32(map
);
6932 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6934 return ctz32(cpu
->sme_vq
.map
);
6937 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6939 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6942 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6945 int cur_el
= arm_current_el(env
);
6946 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6949 /* Bits other than [3:0] are RAZ/WI. */
6950 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6951 raw_write(env
, ri
, value
& 0xf);
6954 * Because we arrived here, we know both FP and SVE are enabled;
6955 * otherwise we would have trapped access to the ZCR_ELn register.
6957 new_len
= sve_vqm1_for_el(env
, cur_el
);
6958 if (new_len
< old_len
) {
6959 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6963 static const ARMCPRegInfo zcr_reginfo
[] = {
6964 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6965 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6966 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6967 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6968 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6969 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6970 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6971 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6972 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6973 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6974 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6975 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6976 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6977 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6978 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6981 #ifdef TARGET_AARCH64
6982 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6985 int el
= arm_current_el(env
);
6988 uint64_t sctlr
= arm_sctlr(env
, el
);
6989 if (!(sctlr
& SCTLR_EnTP2
)) {
6990 return CP_ACCESS_TRAP
;
6993 /* TODO: FEAT_FGT */
6995 && arm_feature(env
, ARM_FEATURE_EL3
)
6996 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6997 return CP_ACCESS_TRAP_EL3
;
6999 return CP_ACCESS_OK
;
7002 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7005 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
7006 if (arm_current_el(env
) < 3
7007 && arm_feature(env
, ARM_FEATURE_EL3
)
7008 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7009 return CP_ACCESS_TRAP_EL3
;
7011 return CP_ACCESS_OK
;
7015 static void arm_reset_sve_state(CPUARMState
*env
)
7017 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
7018 /* Recall that FFR is stored as pregs[16]. */
7019 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
7020 vfp_set_fpcr(env
, 0x0800009f);
7023 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
7025 uint64_t change
= (env
->svcr
^ new) & mask
;
7030 env
->svcr
^= change
;
7032 if (change
& R_SVCR_SM_MASK
) {
7033 arm_reset_sve_state(env
);
7039 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
7040 * on enable: while disabled, the storage is inaccessible and the
7041 * value does not matter. We're not saving the storage in vmstate
7042 * when disabled either.
7044 if (change
& new & R_SVCR_ZA_MASK
) {
7045 memset(env
->zarray
, 0, sizeof(env
->zarray
));
7048 if (tcg_enabled()) {
7049 arm_rebuild_hflags(env
);
7053 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7056 aarch64_set_svcr(env
, value
, -1);
7059 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7062 int cur_el
= arm_current_el(env
);
7063 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7066 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
7067 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
7068 raw_write(env
, ri
, value
);
7071 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7072 * when SVL is widened (old values kept, or zeros). Choose to keep the
7073 * current values for simplicity. But for QEMU internals, we must still
7074 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7075 * above aarch64_sve_narrow_vq.
7077 new_len
= sve_vqm1_for_el(env
, cur_el
);
7078 if (new_len
< old_len
) {
7079 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7083 static const ARMCPRegInfo sme_reginfo
[] = {
7084 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7085 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7086 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7087 .fgt
= FGT_NTPIDR2_EL0
,
7088 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7089 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7090 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7091 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7092 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7093 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7094 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7095 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7096 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7097 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7098 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7099 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7100 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7101 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7102 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7103 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7104 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7105 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7106 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7107 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7108 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7109 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7110 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7111 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7113 * IMPLEMENTOR = 0 (software)
7114 * REVISION = 0 (implementation defined)
7115 * SMPS = 0 (no streaming execution priority in QEMU)
7116 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7118 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7120 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7122 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7123 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7124 .access
= PL1_RW
, .accessfn
= access_esm
,
7125 .fgt
= FGT_NSMPRI_EL1
,
7126 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7127 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7128 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7129 .access
= PL2_RW
, .accessfn
= access_esm
,
7130 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7133 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7136 CPUState
*cs
= env_cpu(env
);
7141 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7144 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7145 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7146 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7147 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7149 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7152 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7154 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7155 env_archcpu(env
)->reset_l0gptsz
);
7158 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7161 CPUState
*cs
= env_cpu(env
);
7163 tlb_flush_all_cpus_synced(cs
);
7166 static const ARMCPRegInfo rme_reginfo
[] = {
7167 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7168 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7169 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7170 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7171 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7172 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7173 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7174 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7175 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7176 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7177 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7178 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7179 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7180 .writefn
= tlbi_aa64_paall_write
},
7181 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7182 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7183 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7184 .writefn
= tlbi_aa64_paallos_write
},
7186 * QEMU does not have a way to invalidate by physical address, thus
7187 * invalidating a range of physical addresses is accomplished by
7188 * flushing all tlb entries in the outer shareable domain,
7189 * just like PAALLOS.
7191 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7192 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7193 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7194 .writefn
= tlbi_aa64_paallos_write
},
7195 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7196 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7197 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7198 .writefn
= tlbi_aa64_paallos_write
},
7199 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7200 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7201 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7204 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7205 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7206 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7207 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7209 #endif /* TARGET_AARCH64 */
7211 static void define_pmu_regs(ARMCPU
*cpu
)
7214 * v7 performance monitor control register: same implementor
7215 * field as main ID register, and we implement four counters in
7216 * addition to the cycle count register.
7218 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7219 ARMCPRegInfo pmcr
= {
7220 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7222 .fgt
= FGT_PMCR_EL0
,
7223 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7224 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7225 .accessfn
= pmreg_access
,
7226 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7227 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7229 ARMCPRegInfo pmcr64
= {
7230 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7231 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7232 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7233 .fgt
= FGT_PMCR_EL0
,
7235 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7236 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7237 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7238 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7241 define_one_arm_cp_reg(cpu
, &pmcr
);
7242 define_one_arm_cp_reg(cpu
, &pmcr64
);
7243 for (i
= 0; i
< pmcrn
; i
++) {
7244 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7245 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7246 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7247 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7248 ARMCPRegInfo pmev_regs
[] = {
7249 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7250 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7251 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7252 .fgt
= FGT_PMEVCNTRN_EL0
,
7253 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7254 .accessfn
= pmreg_access_xevcntr
},
7255 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7256 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7257 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7259 .fgt
= FGT_PMEVCNTRN_EL0
,
7260 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7261 .raw_readfn
= pmevcntr_rawread
,
7262 .raw_writefn
= pmevcntr_rawwrite
},
7263 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7264 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7265 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7266 .fgt
= FGT_PMEVTYPERN_EL0
,
7267 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7268 .accessfn
= pmreg_access
},
7269 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7270 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7271 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7272 .fgt
= FGT_PMEVTYPERN_EL0
,
7274 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7275 .raw_writefn
= pmevtyper_rawwrite
},
7277 define_arm_cp_regs(cpu
, pmev_regs
);
7278 g_free(pmevcntr_name
);
7279 g_free(pmevcntr_el0_name
);
7280 g_free(pmevtyper_name
);
7281 g_free(pmevtyper_el0_name
);
7283 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7284 ARMCPRegInfo v81_pmu_regs
[] = {
7285 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7286 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7287 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7288 .fgt
= FGT_PMCEIDN_EL0
,
7289 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7290 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7291 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7292 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7293 .fgt
= FGT_PMCEIDN_EL0
,
7294 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7296 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7298 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7299 static const ARMCPRegInfo v84_pmmir
= {
7300 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7301 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7302 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7303 .fgt
= FGT_PMMIR_EL1
,
7306 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7310 #ifndef CONFIG_USER_ONLY
7312 * We don't know until after realize whether there's a GICv3
7313 * attached, and that is what registers the gicv3 sysregs.
7314 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7317 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7319 ARMCPU
*cpu
= env_archcpu(env
);
7320 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7322 if (env
->gicv3state
) {
7328 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7330 ARMCPU
*cpu
= env_archcpu(env
);
7331 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7333 if (env
->gicv3state
) {
7341 * Shared logic between LORID and the rest of the LOR* registers.
7342 * Secure state exclusion has already been dealt with.
7344 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7345 const ARMCPRegInfo
*ri
, bool isread
)
7347 int el
= arm_current_el(env
);
7349 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7350 return CP_ACCESS_TRAP_EL2
;
7352 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7353 return CP_ACCESS_TRAP_EL3
;
7355 return CP_ACCESS_OK
;
7358 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7359 const ARMCPRegInfo
*ri
, bool isread
)
7361 if (arm_is_secure_below_el3(env
)) {
7362 /* Access denied in secure mode. */
7363 return CP_ACCESS_TRAP
;
7365 return access_lor_ns(env
, ri
, isread
);
7369 * A trivial implementation of ARMv8.1-LOR leaves all of these
7370 * registers fixed at 0, which indicates that there are zero
7371 * supported Limited Ordering regions.
7373 static const ARMCPRegInfo lor_reginfo
[] = {
7374 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7375 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7376 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7377 .fgt
= FGT_LORSA_EL1
,
7378 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7379 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7380 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7381 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7382 .fgt
= FGT_LOREA_EL1
,
7383 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7384 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7385 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7386 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7387 .fgt
= FGT_LORN_EL1
,
7388 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7389 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7390 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7391 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7392 .fgt
= FGT_LORC_EL1
,
7393 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7394 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7395 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7396 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7397 .fgt
= FGT_LORID_EL1
,
7398 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7401 #ifdef TARGET_AARCH64
7402 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7405 int el
= arm_current_el(env
);
7408 arm_is_el2_enabled(env
) &&
7409 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7410 return CP_ACCESS_TRAP_EL2
;
7413 arm_feature(env
, ARM_FEATURE_EL3
) &&
7414 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7415 return CP_ACCESS_TRAP_EL3
;
7417 return CP_ACCESS_OK
;
7420 static const ARMCPRegInfo pauth_reginfo
[] = {
7421 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7422 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7423 .access
= PL1_RW
, .accessfn
= access_pauth
,
7425 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7426 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7427 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7428 .access
= PL1_RW
, .accessfn
= access_pauth
,
7430 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7431 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7432 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7433 .access
= PL1_RW
, .accessfn
= access_pauth
,
7435 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7436 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7437 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7438 .access
= PL1_RW
, .accessfn
= access_pauth
,
7440 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7441 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7442 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7443 .access
= PL1_RW
, .accessfn
= access_pauth
,
7445 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7446 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7447 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7448 .access
= PL1_RW
, .accessfn
= access_pauth
,
7450 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7451 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7452 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7453 .access
= PL1_RW
, .accessfn
= access_pauth
,
7455 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7456 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7457 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7458 .access
= PL1_RW
, .accessfn
= access_pauth
,
7460 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7461 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7462 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7463 .access
= PL1_RW
, .accessfn
= access_pauth
,
7465 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7466 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7467 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7468 .access
= PL1_RW
, .accessfn
= access_pauth
,
7470 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7473 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7474 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7475 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7476 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7477 .fgt
= FGT_TLBIRVAE1IS
,
7478 .writefn
= tlbi_aa64_rvae1is_write
},
7479 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7480 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7481 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7482 .fgt
= FGT_TLBIRVAAE1IS
,
7483 .writefn
= tlbi_aa64_rvae1is_write
},
7484 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7485 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7486 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7487 .fgt
= FGT_TLBIRVALE1IS
,
7488 .writefn
= tlbi_aa64_rvae1is_write
},
7489 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7490 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7491 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7492 .fgt
= FGT_TLBIRVAALE1IS
,
7493 .writefn
= tlbi_aa64_rvae1is_write
},
7494 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7495 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7496 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7497 .fgt
= FGT_TLBIRVAE1OS
,
7498 .writefn
= tlbi_aa64_rvae1is_write
},
7499 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7500 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7501 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7502 .fgt
= FGT_TLBIRVAAE1OS
,
7503 .writefn
= tlbi_aa64_rvae1is_write
},
7504 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7505 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7506 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7507 .fgt
= FGT_TLBIRVALE1OS
,
7508 .writefn
= tlbi_aa64_rvae1is_write
},
7509 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7510 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7511 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7512 .fgt
= FGT_TLBIRVAALE1OS
,
7513 .writefn
= tlbi_aa64_rvae1is_write
},
7514 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7515 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7516 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7517 .fgt
= FGT_TLBIRVAE1
,
7518 .writefn
= tlbi_aa64_rvae1_write
},
7519 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7520 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7521 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7522 .fgt
= FGT_TLBIRVAAE1
,
7523 .writefn
= tlbi_aa64_rvae1_write
},
7524 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7525 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7526 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7527 .fgt
= FGT_TLBIRVALE1
,
7528 .writefn
= tlbi_aa64_rvae1_write
},
7529 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7530 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7531 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7532 .fgt
= FGT_TLBIRVAALE1
,
7533 .writefn
= tlbi_aa64_rvae1_write
},
7534 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7535 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7536 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7537 .writefn
= tlbi_aa64_ripas2e1is_write
},
7538 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7539 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7540 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7541 .writefn
= tlbi_aa64_ripas2e1is_write
},
7542 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7543 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7544 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7545 .writefn
= tlbi_aa64_rvae2is_write
},
7546 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7547 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7548 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7549 .writefn
= tlbi_aa64_rvae2is_write
},
7550 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7551 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7552 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7553 .writefn
= tlbi_aa64_ripas2e1_write
},
7554 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7555 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7556 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7557 .writefn
= tlbi_aa64_ripas2e1_write
},
7558 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7559 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7560 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7561 .writefn
= tlbi_aa64_rvae2is_write
},
7562 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7563 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7564 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7565 .writefn
= tlbi_aa64_rvae2is_write
},
7566 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7567 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7568 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7569 .writefn
= tlbi_aa64_rvae2_write
},
7570 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7571 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7572 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7573 .writefn
= tlbi_aa64_rvae2_write
},
7574 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7575 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7576 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7577 .writefn
= tlbi_aa64_rvae3is_write
},
7578 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7579 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7580 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7581 .writefn
= tlbi_aa64_rvae3is_write
},
7582 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7583 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7584 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7585 .writefn
= tlbi_aa64_rvae3is_write
},
7586 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7587 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7588 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7589 .writefn
= tlbi_aa64_rvae3is_write
},
7590 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7591 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7592 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7593 .writefn
= tlbi_aa64_rvae3_write
},
7594 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7595 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7596 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7597 .writefn
= tlbi_aa64_rvae3_write
},
7600 static const ARMCPRegInfo tlbios_reginfo
[] = {
7601 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7602 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7603 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7604 .fgt
= FGT_TLBIVMALLE1OS
,
7605 .writefn
= tlbi_aa64_vmalle1is_write
},
7606 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7607 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7608 .fgt
= FGT_TLBIVAE1OS
,
7609 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7610 .writefn
= tlbi_aa64_vae1is_write
},
7611 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7612 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7613 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7614 .fgt
= FGT_TLBIASIDE1OS
,
7615 .writefn
= tlbi_aa64_vmalle1is_write
},
7616 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7617 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7618 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7619 .fgt
= FGT_TLBIVAAE1OS
,
7620 .writefn
= tlbi_aa64_vae1is_write
},
7621 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7622 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7623 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7624 .fgt
= FGT_TLBIVALE1OS
,
7625 .writefn
= tlbi_aa64_vae1is_write
},
7626 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7627 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7628 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7629 .fgt
= FGT_TLBIVAALE1OS
,
7630 .writefn
= tlbi_aa64_vae1is_write
},
7631 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7632 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7633 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7634 .writefn
= tlbi_aa64_alle2is_write
},
7635 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7636 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7637 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7638 .writefn
= tlbi_aa64_vae2is_write
},
7639 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7640 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7641 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7642 .writefn
= tlbi_aa64_alle1is_write
},
7643 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7644 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7645 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7646 .writefn
= tlbi_aa64_vae2is_write
},
7647 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7648 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7649 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7650 .writefn
= tlbi_aa64_alle1is_write
},
7651 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7652 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7653 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7654 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7655 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7656 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7657 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7658 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7659 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7660 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7661 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7662 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7663 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7664 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7665 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7666 .writefn
= tlbi_aa64_alle3is_write
},
7667 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7668 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7669 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7670 .writefn
= tlbi_aa64_vae3is_write
},
7671 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7672 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7673 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7674 .writefn
= tlbi_aa64_vae3is_write
},
7677 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7682 /* Success sets NZCV = 0000. */
7683 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7685 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7687 * ??? Failed, for unknown reasons in the crypto subsystem.
7688 * The best we can do is log the reason and return the
7689 * timed-out indication to the guest. There is no reason
7690 * we know to expect this failure to be transitory, so the
7691 * guest may well hang retrying the operation.
7693 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7694 ri
->name
, error_get_pretty(err
));
7697 env
->ZF
= 0; /* NZCF = 0100 */
7703 /* We do not support re-seeding, so the two registers operate the same. */
7704 static const ARMCPRegInfo rndr_reginfo
[] = {
7705 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7706 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7707 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7708 .access
= PL0_R
, .readfn
= rndr_readfn
},
7709 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7710 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7711 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7712 .access
= PL0_R
, .readfn
= rndr_readfn
},
7715 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7719 ARMCPU
*cpu
= env_archcpu(env
);
7720 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7721 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7722 uint64_t vaddr_in
= (uint64_t) value
;
7723 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7725 int mem_idx
= cpu_mmu_index(env
, false);
7727 /* This won't be crossing page boundaries */
7728 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7730 #ifndef CONFIG_USER_ONLY
7735 /* RCU lock is already being held */
7736 mr
= memory_region_from_host(haddr
, &offset
);
7739 memory_region_writeback(mr
, offset
, dline_size
);
7741 #endif /*CONFIG_USER_ONLY*/
7744 /* Handled by hardware accelerator. */
7745 g_assert_not_reached();
7746 #endif /* CONFIG_TCG */
7749 static const ARMCPRegInfo dcpop_reg
[] = {
7750 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7751 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7752 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7754 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7757 static const ARMCPRegInfo dcpodp_reg
[] = {
7758 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7759 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7760 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7762 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7765 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7768 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7769 return CP_ACCESS_TRAP_EL2
;
7772 return CP_ACCESS_OK
;
7775 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7778 int el
= arm_current_el(env
);
7780 if (el
< 2 && arm_is_el2_enabled(env
)) {
7781 uint64_t hcr
= arm_hcr_el2_eff(env
);
7782 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7783 return CP_ACCESS_TRAP_EL2
;
7787 arm_feature(env
, ARM_FEATURE_EL3
) &&
7788 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7789 return CP_ACCESS_TRAP_EL3
;
7791 return CP_ACCESS_OK
;
7794 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7796 return env
->pstate
& PSTATE_TCO
;
7799 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7801 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7804 static const ARMCPRegInfo mte_reginfo
[] = {
7805 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7806 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7807 .access
= PL1_RW
, .accessfn
= access_mte
,
7808 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7809 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7810 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7811 .access
= PL1_RW
, .accessfn
= access_mte
,
7812 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7813 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7814 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7815 .access
= PL2_RW
, .accessfn
= access_mte
,
7816 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7817 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7818 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7820 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7821 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7822 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7823 .access
= PL1_RW
, .accessfn
= access_mte
,
7824 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7825 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7826 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7827 .access
= PL1_RW
, .accessfn
= access_mte
,
7828 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7829 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7830 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7831 .type
= ARM_CP_NO_RAW
,
7832 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7833 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7834 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7835 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7837 .accessfn
= aa64_cacheop_poc_access
},
7838 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7839 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7841 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7842 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7843 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7844 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7846 .accessfn
= aa64_cacheop_poc_access
},
7847 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7848 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7850 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7851 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7852 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7854 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7855 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7856 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7858 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7859 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7860 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7862 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7863 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7864 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7866 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7869 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7870 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7871 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7872 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7875 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7876 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7877 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7878 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7880 .accessfn
= aa64_cacheop_poc_access
},
7881 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7882 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7883 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7885 .accessfn
= aa64_cacheop_poc_access
},
7886 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7887 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7888 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7890 .accessfn
= aa64_cacheop_poc_access
},
7891 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7892 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7893 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7895 .accessfn
= aa64_cacheop_poc_access
},
7896 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7897 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7898 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7900 .accessfn
= aa64_cacheop_poc_access
},
7901 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7902 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7903 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7905 .accessfn
= aa64_cacheop_poc_access
},
7906 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7907 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7908 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7910 .accessfn
= aa64_cacheop_poc_access
},
7911 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7912 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7913 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7915 .accessfn
= aa64_cacheop_poc_access
},
7916 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7917 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7918 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7919 #ifndef CONFIG_USER_ONLY
7920 /* Avoid overhead of an access check that always passes in user-mode */
7921 .accessfn
= aa64_zva_access
,
7925 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7926 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7927 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7928 #ifndef CONFIG_USER_ONLY
7929 /* Avoid overhead of an access check that always passes in user-mode */
7930 .accessfn
= aa64_zva_access
,
7936 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7939 uint64_t hcr
= arm_hcr_el2_eff(env
);
7940 int el
= arm_current_el(env
);
7942 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7943 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7944 if (hcr
& HCR_TGE
) {
7945 return CP_ACCESS_TRAP_EL2
;
7947 return CP_ACCESS_TRAP
;
7949 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7950 return CP_ACCESS_TRAP_EL2
;
7952 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7953 return CP_ACCESS_TRAP_EL2
;
7956 && arm_feature(env
, ARM_FEATURE_EL3
)
7957 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7958 return CP_ACCESS_TRAP_EL3
;
7960 return CP_ACCESS_OK
;
7963 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7964 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7965 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7966 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7967 .fgt
= FGT_SCXTNUM_EL0
,
7968 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7969 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7970 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7971 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7972 .fgt
= FGT_SCXTNUM_EL1
,
7973 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7974 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7975 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7976 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7977 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7978 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7979 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7981 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7984 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7987 if (arm_current_el(env
) == 2 &&
7988 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
7989 return CP_ACCESS_TRAP_EL3
;
7991 return CP_ACCESS_OK
;
7994 static const ARMCPRegInfo fgt_reginfo
[] = {
7995 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7996 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
7997 .access
= PL2_RW
, .accessfn
= access_fgt
,
7998 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
7999 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8000 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
8001 .access
= PL2_RW
, .accessfn
= access_fgt
,
8002 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
8003 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8004 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
8005 .access
= PL2_RW
, .accessfn
= access_fgt
,
8006 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
8007 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8008 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
8009 .access
= PL2_RW
, .accessfn
= access_fgt
,
8010 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
8011 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
8012 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
8013 .access
= PL2_RW
, .accessfn
= access_fgt
,
8014 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
8016 #endif /* TARGET_AARCH64 */
8018 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8021 int el
= arm_current_el(env
);
8024 uint64_t sctlr
= arm_sctlr(env
, el
);
8025 if (!(sctlr
& SCTLR_EnRCTX
)) {
8026 return CP_ACCESS_TRAP
;
8028 } else if (el
== 1) {
8029 uint64_t hcr
= arm_hcr_el2_eff(env
);
8031 return CP_ACCESS_TRAP_EL2
;
8034 return CP_ACCESS_OK
;
8037 static const ARMCPRegInfo predinv_reginfo
[] = {
8038 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
8039 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
8041 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8042 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
8043 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
8045 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8046 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
8047 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
8049 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8051 * Note the AArch32 opcodes have a different OPC1.
8053 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
8054 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
8056 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8057 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
8058 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
8060 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8061 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
8062 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
8064 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8067 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8069 /* Read the high 32 bits of the current CCSIDR */
8070 return extract64(ccsidr_read(env
, ri
), 32, 32);
8073 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
8074 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
8075 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
8077 .accessfn
= access_tid4
,
8078 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8081 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8084 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8085 return CP_ACCESS_TRAP_EL2
;
8088 return CP_ACCESS_OK
;
8091 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8094 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8095 return access_aa64_tid3(env
, ri
, isread
);
8098 return CP_ACCESS_OK
;
8101 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8104 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8105 return CP_ACCESS_TRAP_EL2
;
8108 return CP_ACCESS_OK
;
8111 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8112 const ARMCPRegInfo
*ri
, bool isread
)
8115 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8116 * in v7A, not in v8A.
8118 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8119 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8120 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8121 return CP_ACCESS_TRAP_EL2
;
8123 return CP_ACCESS_OK
;
8126 static const ARMCPRegInfo jazelle_regs
[] = {
8128 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8129 .access
= PL1_R
, .accessfn
= access_jazelle
,
8130 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8132 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8133 .accessfn
= access_joscr_jmcr
,
8134 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8136 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8137 .accessfn
= access_joscr_jmcr
,
8138 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8141 static const ARMCPRegInfo contextidr_el2
= {
8142 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8143 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8145 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8148 static const ARMCPRegInfo vhe_reginfo
[] = {
8149 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8150 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8151 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8152 .raw_writefn
= raw_write
,
8153 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8154 #ifndef CONFIG_USER_ONLY
8155 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8156 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8158 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8159 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8160 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8161 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8162 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8163 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8164 .resetfn
= gt_hv_timer_reset
,
8165 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8166 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8168 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8171 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8172 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8173 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8174 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8175 .access
= PL2_RW
, .accessfn
= e2h_access
,
8176 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8177 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8178 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8179 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8180 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8181 .access
= PL2_RW
, .accessfn
= e2h_access
,
8182 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8183 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8184 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8185 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8186 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8187 .access
= PL2_RW
, .accessfn
= e2h_access
,
8188 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8189 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8190 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8191 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8192 .access
= PL2_RW
, .accessfn
= e2h_access
,
8193 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8194 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8195 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8196 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8197 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8198 .access
= PL2_RW
, .accessfn
= e2h_access
,
8199 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8200 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8201 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8202 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8203 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8204 .access
= PL2_RW
, .accessfn
= e2h_access
,
8205 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8209 #ifndef CONFIG_USER_ONLY
8210 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8211 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8212 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8213 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8214 .fgt
= FGT_ATS1E1RP
,
8215 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8216 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8217 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8218 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8219 .fgt
= FGT_ATS1E1WP
,
8220 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8223 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8224 { .name
= "ATS1CPRP",
8225 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8226 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8227 .writefn
= ats_write
},
8228 { .name
= "ATS1CPWP",
8229 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8230 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8231 .writefn
= ats_write
},
8236 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8237 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8238 * is non-zero, which is never for ARMv7, optionally in ARMv8
8239 * and mandatorily for ARMv8.2 and up.
8240 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8241 * implementation is RAZ/WI we can ignore this detail, as we
8244 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8245 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8246 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8247 .access
= PL1_RW
, .accessfn
= access_tacr
,
8248 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8249 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8250 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8251 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8255 void register_cp_regs_for_features(ARMCPU
*cpu
)
8257 /* Register all the coprocessor registers based on feature bits */
8258 CPUARMState
*env
= &cpu
->env
;
8259 if (arm_feature(env
, ARM_FEATURE_M
)) {
8260 /* M profile has no coprocessor registers */
8264 define_arm_cp_regs(cpu
, cp_reginfo
);
8265 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8267 * Must go early as it is full of wildcards that may be
8268 * overridden by later definitions.
8270 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8273 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8274 /* The ID registers all have impdef reset values */
8275 ARMCPRegInfo v6_idregs
[] = {
8276 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8277 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8278 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8279 .accessfn
= access_aa32_tid3
,
8280 .resetvalue
= cpu
->isar
.id_pfr0
},
8282 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8283 * the value of the GIC field until after we define these regs.
8285 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8286 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8287 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8288 .accessfn
= access_aa32_tid3
,
8289 #ifdef CONFIG_USER_ONLY
8290 .type
= ARM_CP_CONST
,
8291 .resetvalue
= cpu
->isar
.id_pfr1
,
8293 .type
= ARM_CP_NO_RAW
,
8294 .accessfn
= access_aa32_tid3
,
8295 .readfn
= id_pfr1_read
,
8296 .writefn
= arm_cp_write_ignore
8299 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8300 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8301 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8302 .accessfn
= access_aa32_tid3
,
8303 .resetvalue
= cpu
->isar
.id_dfr0
},
8304 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8305 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8306 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8307 .accessfn
= access_aa32_tid3
,
8308 .resetvalue
= cpu
->id_afr0
},
8309 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8310 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8311 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8312 .accessfn
= access_aa32_tid3
,
8313 .resetvalue
= cpu
->isar
.id_mmfr0
},
8314 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8315 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8316 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8317 .accessfn
= access_aa32_tid3
,
8318 .resetvalue
= cpu
->isar
.id_mmfr1
},
8319 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8320 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8321 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8322 .accessfn
= access_aa32_tid3
,
8323 .resetvalue
= cpu
->isar
.id_mmfr2
},
8324 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8325 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8326 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8327 .accessfn
= access_aa32_tid3
,
8328 .resetvalue
= cpu
->isar
.id_mmfr3
},
8329 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8330 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8331 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8332 .accessfn
= access_aa32_tid3
,
8333 .resetvalue
= cpu
->isar
.id_isar0
},
8334 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8335 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8336 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8337 .accessfn
= access_aa32_tid3
,
8338 .resetvalue
= cpu
->isar
.id_isar1
},
8339 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8340 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8341 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8342 .accessfn
= access_aa32_tid3
,
8343 .resetvalue
= cpu
->isar
.id_isar2
},
8344 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8345 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8346 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8347 .accessfn
= access_aa32_tid3
,
8348 .resetvalue
= cpu
->isar
.id_isar3
},
8349 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8350 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8351 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8352 .accessfn
= access_aa32_tid3
,
8353 .resetvalue
= cpu
->isar
.id_isar4
},
8354 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8355 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8356 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8357 .accessfn
= access_aa32_tid3
,
8358 .resetvalue
= cpu
->isar
.id_isar5
},
8359 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8360 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8361 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8362 .accessfn
= access_aa32_tid3
,
8363 .resetvalue
= cpu
->isar
.id_mmfr4
},
8364 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8365 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8366 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8367 .accessfn
= access_aa32_tid3
,
8368 .resetvalue
= cpu
->isar
.id_isar6
},
8370 define_arm_cp_regs(cpu
, v6_idregs
);
8371 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8373 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8375 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8376 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8378 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8379 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8380 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8382 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8383 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8385 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8386 ARMCPRegInfo clidr
= {
8387 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8388 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8389 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8390 .accessfn
= access_tid4
,
8391 .fgt
= FGT_CLIDR_EL1
,
8392 .resetvalue
= cpu
->clidr
8394 define_one_arm_cp_reg(cpu
, &clidr
);
8395 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8396 define_debug_regs(cpu
);
8397 define_pmu_regs(cpu
);
8399 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8401 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8403 * v8 ID registers, which all have impdef reset values.
8404 * Note that within the ID register ranges the unused slots
8405 * must all RAZ, not UNDEF; future architecture versions may
8406 * define new registers here.
8407 * ID registers which are AArch64 views of the AArch32 ID registers
8408 * which already existed in v6 and v7 are handled elsewhere,
8412 ARMCPRegInfo v8_idregs
[] = {
8414 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8415 * emulation because we don't know the right value for the
8416 * GIC field until after we define these regs.
8418 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8419 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8421 #ifdef CONFIG_USER_ONLY
8422 .type
= ARM_CP_CONST
,
8423 .resetvalue
= cpu
->isar
.id_aa64pfr0
8425 .type
= ARM_CP_NO_RAW
,
8426 .accessfn
= access_aa64_tid3
,
8427 .readfn
= id_aa64pfr0_read
,
8428 .writefn
= arm_cp_write_ignore
8431 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8432 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8433 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8434 .accessfn
= access_aa64_tid3
,
8435 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8436 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8437 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8438 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8439 .accessfn
= access_aa64_tid3
,
8441 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8442 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8443 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8444 .accessfn
= access_aa64_tid3
,
8446 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8447 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8448 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8449 .accessfn
= access_aa64_tid3
,
8450 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8451 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8452 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8453 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8454 .accessfn
= access_aa64_tid3
,
8455 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8456 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8457 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8458 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8459 .accessfn
= access_aa64_tid3
,
8461 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8462 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8463 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8464 .accessfn
= access_aa64_tid3
,
8466 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8467 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8468 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8469 .accessfn
= access_aa64_tid3
,
8470 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8471 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8472 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8473 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8474 .accessfn
= access_aa64_tid3
,
8475 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8476 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8477 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8478 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8479 .accessfn
= access_aa64_tid3
,
8481 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8482 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8483 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8484 .accessfn
= access_aa64_tid3
,
8486 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8487 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8488 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8489 .accessfn
= access_aa64_tid3
,
8490 .resetvalue
= cpu
->id_aa64afr0
},
8491 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8492 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8493 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8494 .accessfn
= access_aa64_tid3
,
8495 .resetvalue
= cpu
->id_aa64afr1
},
8496 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8497 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8498 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8499 .accessfn
= access_aa64_tid3
,
8501 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8502 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8503 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8504 .accessfn
= access_aa64_tid3
,
8506 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8507 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8508 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8509 .accessfn
= access_aa64_tid3
,
8510 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8511 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8512 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8513 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8514 .accessfn
= access_aa64_tid3
,
8515 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8516 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8517 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8518 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8519 .accessfn
= access_aa64_tid3
,
8520 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8521 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8522 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8523 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8524 .accessfn
= access_aa64_tid3
,
8526 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8527 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8528 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8529 .accessfn
= access_aa64_tid3
,
8531 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8532 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8533 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8534 .accessfn
= access_aa64_tid3
,
8536 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8537 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8538 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8539 .accessfn
= access_aa64_tid3
,
8541 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8542 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8543 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8544 .accessfn
= access_aa64_tid3
,
8546 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8547 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8548 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8549 .accessfn
= access_aa64_tid3
,
8550 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8551 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8552 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8553 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8554 .accessfn
= access_aa64_tid3
,
8555 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8556 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8557 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8558 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8559 .accessfn
= access_aa64_tid3
,
8560 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8561 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8562 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8563 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8564 .accessfn
= access_aa64_tid3
,
8566 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8567 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8568 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8569 .accessfn
= access_aa64_tid3
,
8571 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8572 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8573 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8574 .accessfn
= access_aa64_tid3
,
8576 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8577 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8578 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8579 .accessfn
= access_aa64_tid3
,
8581 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8582 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8583 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8584 .accessfn
= access_aa64_tid3
,
8586 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8587 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8588 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8589 .accessfn
= access_aa64_tid3
,
8590 .resetvalue
= cpu
->isar
.mvfr0
},
8591 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8592 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8593 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8594 .accessfn
= access_aa64_tid3
,
8595 .resetvalue
= cpu
->isar
.mvfr1
},
8596 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8597 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8598 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8599 .accessfn
= access_aa64_tid3
,
8600 .resetvalue
= cpu
->isar
.mvfr2
},
8602 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8603 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8604 * as RAZ, since it is in the "reserved for future ID
8605 * registers, RAZ" part of the AArch32 encoding space.
8607 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8608 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8609 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8610 .accessfn
= access_aa64_tid3
,
8612 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8613 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8614 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8615 .accessfn
= access_aa64_tid3
,
8617 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8618 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8619 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8620 .accessfn
= access_aa64_tid3
,
8623 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8624 * they're also RAZ for AArch64, and in v8 are gradually
8625 * being filled with AArch64-view-of-AArch32-ID-register
8626 * for new ID registers.
8628 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8629 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8630 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8631 .accessfn
= access_aa64_tid3
,
8633 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8634 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8635 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8636 .accessfn
= access_aa64_tid3
,
8637 .resetvalue
= cpu
->isar
.id_pfr2
},
8638 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8639 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8640 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8641 .accessfn
= access_aa64_tid3
,
8642 .resetvalue
= cpu
->isar
.id_dfr1
},
8643 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8644 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8645 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8646 .accessfn
= access_aa64_tid3
,
8647 .resetvalue
= cpu
->isar
.id_mmfr5
},
8648 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8649 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8650 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8651 .accessfn
= access_aa64_tid3
,
8653 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8654 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8655 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8656 .fgt
= FGT_PMCEIDN_EL0
,
8657 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8658 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8659 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8660 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8661 .fgt
= FGT_PMCEIDN_EL0
,
8662 .resetvalue
= cpu
->pmceid0
},
8663 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8664 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8665 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8666 .fgt
= FGT_PMCEIDN_EL0
,
8667 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8668 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8669 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8670 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8671 .fgt
= FGT_PMCEIDN_EL0
,
8672 .resetvalue
= cpu
->pmceid1
},
8674 #ifdef CONFIG_USER_ONLY
8675 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8676 { .name
= "ID_AA64PFR0_EL1",
8677 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8678 R_ID_AA64PFR0_ADVSIMD_MASK
|
8679 R_ID_AA64PFR0_SVE_MASK
|
8680 R_ID_AA64PFR0_DIT_MASK
,
8681 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8682 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8683 { .name
= "ID_AA64PFR1_EL1",
8684 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8685 R_ID_AA64PFR1_SSBS_MASK
|
8686 R_ID_AA64PFR1_MTE_MASK
|
8687 R_ID_AA64PFR1_SME_MASK
},
8688 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8690 { .name
= "ID_AA64ZFR0_EL1",
8691 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8692 R_ID_AA64ZFR0_AES_MASK
|
8693 R_ID_AA64ZFR0_BITPERM_MASK
|
8694 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8695 R_ID_AA64ZFR0_SHA3_MASK
|
8696 R_ID_AA64ZFR0_SM4_MASK
|
8697 R_ID_AA64ZFR0_I8MM_MASK
|
8698 R_ID_AA64ZFR0_F32MM_MASK
|
8699 R_ID_AA64ZFR0_F64MM_MASK
},
8700 { .name
= "ID_AA64SMFR0_EL1",
8701 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8702 R_ID_AA64SMFR0_BI32I32_MASK
|
8703 R_ID_AA64SMFR0_B16F32_MASK
|
8704 R_ID_AA64SMFR0_F16F32_MASK
|
8705 R_ID_AA64SMFR0_I8I32_MASK
|
8706 R_ID_AA64SMFR0_F16F16_MASK
|
8707 R_ID_AA64SMFR0_B16B16_MASK
|
8708 R_ID_AA64SMFR0_I16I32_MASK
|
8709 R_ID_AA64SMFR0_F64F64_MASK
|
8710 R_ID_AA64SMFR0_I16I64_MASK
|
8711 R_ID_AA64SMFR0_SMEVER_MASK
|
8712 R_ID_AA64SMFR0_FA64_MASK
},
8713 { .name
= "ID_AA64MMFR0_EL1",
8714 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8715 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8716 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8717 { .name
= "ID_AA64MMFR1_EL1",
8718 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8719 { .name
= "ID_AA64MMFR2_EL1",
8720 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8721 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8723 { .name
= "ID_AA64DFR0_EL1",
8724 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8725 { .name
= "ID_AA64DFR1_EL1" },
8726 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8728 { .name
= "ID_AA64AFR*",
8730 { .name
= "ID_AA64ISAR0_EL1",
8731 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8732 R_ID_AA64ISAR0_SHA1_MASK
|
8733 R_ID_AA64ISAR0_SHA2_MASK
|
8734 R_ID_AA64ISAR0_CRC32_MASK
|
8735 R_ID_AA64ISAR0_ATOMIC_MASK
|
8736 R_ID_AA64ISAR0_RDM_MASK
|
8737 R_ID_AA64ISAR0_SHA3_MASK
|
8738 R_ID_AA64ISAR0_SM3_MASK
|
8739 R_ID_AA64ISAR0_SM4_MASK
|
8740 R_ID_AA64ISAR0_DP_MASK
|
8741 R_ID_AA64ISAR0_FHM_MASK
|
8742 R_ID_AA64ISAR0_TS_MASK
|
8743 R_ID_AA64ISAR0_RNDR_MASK
},
8744 { .name
= "ID_AA64ISAR1_EL1",
8745 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8746 R_ID_AA64ISAR1_APA_MASK
|
8747 R_ID_AA64ISAR1_API_MASK
|
8748 R_ID_AA64ISAR1_JSCVT_MASK
|
8749 R_ID_AA64ISAR1_FCMA_MASK
|
8750 R_ID_AA64ISAR1_LRCPC_MASK
|
8751 R_ID_AA64ISAR1_GPA_MASK
|
8752 R_ID_AA64ISAR1_GPI_MASK
|
8753 R_ID_AA64ISAR1_FRINTTS_MASK
|
8754 R_ID_AA64ISAR1_SB_MASK
|
8755 R_ID_AA64ISAR1_BF16_MASK
|
8756 R_ID_AA64ISAR1_DGH_MASK
|
8757 R_ID_AA64ISAR1_I8MM_MASK
},
8758 { .name
= "ID_AA64ISAR2_EL1",
8759 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8760 R_ID_AA64ISAR2_RPRES_MASK
|
8761 R_ID_AA64ISAR2_GPA3_MASK
|
8762 R_ID_AA64ISAR2_APA3_MASK
|
8763 R_ID_AA64ISAR2_MOPS_MASK
|
8764 R_ID_AA64ISAR2_BC_MASK
|
8765 R_ID_AA64ISAR2_RPRFM_MASK
|
8766 R_ID_AA64ISAR2_CSSC_MASK
},
8767 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8770 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8773 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8774 * TODO: For RMR, a write with bit 1 set should do something with
8775 * cpu_reset(). In the meantime, "the bit is strictly a request",
8776 * so we are in spec just ignoring writes.
8778 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8779 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8780 ARMCPRegInfo el1_reset_regs
[] = {
8781 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8782 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8784 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8785 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8786 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8787 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8788 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8790 define_arm_cp_regs(cpu
, el1_reset_regs
);
8792 define_arm_cp_regs(cpu
, v8_idregs
);
8793 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8794 if (cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
8795 define_arm_cp_regs(cpu
, v8_aa32_el1_reginfo
);
8798 for (i
= 4; i
< 16; i
++) {
8800 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8801 * For pre-v8 cores there are RAZ patterns for these in
8802 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8803 * v8 extends the "must RAZ" part of the ID register space
8804 * to also cover c0, 0, c{8-15}, {0-7}.
8805 * These are STATE_AA32 because in the AArch64 sysreg space
8806 * c4-c7 is where the AArch64 ID registers live (and we've
8807 * already defined those in v8_idregs[]), and c8-c15 are not
8808 * "must RAZ" for AArch64.
8810 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8811 ARMCPRegInfo v8_aa32_raz_idregs
= {
8813 .state
= ARM_CP_STATE_AA32
,
8814 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8815 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8816 .accessfn
= access_aa64_tid3
,
8818 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8823 * Register the base EL2 cpregs.
8824 * Pre v8, these registers are implemented only as part of the
8825 * Virtualization Extensions (EL2 present). Beginning with v8,
8826 * if EL2 is missing but EL3 is enabled, mostly these become
8827 * RES0 from EL3, with some specific exceptions.
8829 if (arm_feature(env
, ARM_FEATURE_EL2
)
8830 || (arm_feature(env
, ARM_FEATURE_EL3
)
8831 && arm_feature(env
, ARM_FEATURE_V8
))) {
8832 uint64_t vmpidr_def
= mpidr_read_val(env
);
8833 ARMCPRegInfo vpidr_regs
[] = {
8834 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8835 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8836 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8837 .resetvalue
= cpu
->midr
,
8838 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8839 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8840 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8841 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8842 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8843 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8844 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8845 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8846 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8847 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8848 .resetvalue
= vmpidr_def
,
8849 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8850 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8851 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8852 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8853 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8854 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8855 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8858 * The only field of MDCR_EL2 that has a defined architectural reset
8859 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8861 ARMCPRegInfo mdcr_el2
= {
8862 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8863 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8864 .writefn
= mdcr_el2_write
,
8865 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8866 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8868 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8869 define_arm_cp_regs(cpu
, vpidr_regs
);
8870 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8871 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8872 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8874 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8875 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8878 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
8879 * See commentary near RMR_EL1.
8881 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8882 static const ARMCPRegInfo el2_reset_regs
[] = {
8883 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8884 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8886 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8887 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8888 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8890 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8891 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
8892 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
8893 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8895 define_arm_cp_regs(cpu
, el2_reset_regs
);
8899 /* Register the base EL3 cpregs. */
8900 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8901 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8902 ARMCPRegInfo el3_regs
[] = {
8903 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8904 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8906 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
8907 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
8908 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
8909 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8910 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
8911 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8912 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8913 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
8914 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8915 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8917 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8918 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8919 .resetvalue
= cpu
->reset_sctlr
},
8922 define_arm_cp_regs(cpu
, el3_regs
);
8925 * The behaviour of NSACR is sufficiently various that we don't
8926 * try to describe it in a single reginfo:
8927 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8928 * reads as constant 0xc00 from NS EL1 and NS EL2
8929 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8930 * if v7 without EL3, register doesn't exist
8931 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8933 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8934 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8935 static const ARMCPRegInfo nsacr
= {
8936 .name
= "NSACR", .type
= ARM_CP_CONST
,
8937 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8938 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8941 define_one_arm_cp_reg(cpu
, &nsacr
);
8943 static const ARMCPRegInfo nsacr
= {
8945 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8946 .access
= PL3_RW
| PL1_R
,
8948 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8950 define_one_arm_cp_reg(cpu
, &nsacr
);
8953 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8954 static const ARMCPRegInfo nsacr
= {
8955 .name
= "NSACR", .type
= ARM_CP_CONST
,
8956 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8960 define_one_arm_cp_reg(cpu
, &nsacr
);
8964 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8965 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8966 /* PMSAv6 not implemented */
8967 assert(arm_feature(env
, ARM_FEATURE_V7
));
8968 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8969 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8971 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8974 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8975 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8976 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8977 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8978 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8981 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8982 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8984 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8985 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8987 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8988 ARMCPRegInfo vapa_cp_reginfo
[] = {
8989 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
8990 .access
= PL1_RW
, .resetvalue
= 0,
8991 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
8992 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
8993 .writefn
= par_write
},
8994 #ifndef CONFIG_USER_ONLY
8995 /* This underdecoding is safe because the reginfo is NO_RAW. */
8996 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
8997 .access
= PL1_W
, .accessfn
= ats_access
,
8998 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
9003 * When LPAE exists this 32-bit PAR register is an alias of the
9004 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
9006 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9007 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9009 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
9011 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
9012 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
9014 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
9015 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
9017 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
9018 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
9020 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
9021 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
9023 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9024 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
9026 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9027 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
9029 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
9030 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
9032 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9033 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
9035 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
9036 define_arm_cp_regs(cpu
, jazelle_regs
);
9039 * Slightly awkwardly, the OMAP and StrongARM cores need all of
9040 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
9041 * be read-only (ie write causes UNDEF exception).
9044 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
9046 * Pre-v8 MIDR space.
9047 * Note that the MIDR isn't a simple constant register because
9048 * of the TI925 behaviour where writes to another register can
9049 * cause the MIDR value to change.
9051 * Unimplemented registers in the c15 0 0 0 space default to
9052 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
9053 * and friends override accordingly.
9056 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
9057 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
9058 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
9059 .readfn
= midr_read
,
9060 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9061 .type
= ARM_CP_OVERRIDE
},
9062 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
9064 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
9065 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9067 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
9068 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9070 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
9071 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9073 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
9074 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9076 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
9077 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9079 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
9080 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9081 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
9082 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
9083 .fgt
= FGT_MIDR_EL1
,
9084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9085 .readfn
= midr_read
},
9086 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
9087 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
9088 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
9089 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
9090 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9091 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
9093 .accessfn
= access_aa64_tid1
,
9094 .fgt
= FGT_REVIDR_EL1
,
9095 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9097 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9098 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9099 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9100 .access
= PL1_R
, .resetvalue
= cpu
->midr
9102 ARMCPRegInfo id_cp_reginfo
[] = {
9103 /* These are common to v8 and pre-v8 */
9105 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9106 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9107 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9108 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9109 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9110 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9112 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9113 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9115 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9117 .accessfn
= access_aa32_tid1
,
9118 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9120 /* TLBTR is specific to VMSA */
9121 ARMCPRegInfo id_tlbtr_reginfo
= {
9123 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9125 .accessfn
= access_aa32_tid1
,
9126 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9128 /* MPUIR is specific to PMSA V6+ */
9129 ARMCPRegInfo id_mpuir_reginfo
= {
9131 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9132 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9133 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9135 /* HMPUIR is specific to PMSA V8 */
9136 ARMCPRegInfo id_hmpuir_reginfo
= {
9138 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9139 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9140 .resetvalue
= cpu
->pmsav8r_hdregion
9142 static const ARMCPRegInfo crn0_wi_reginfo
= {
9143 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9144 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9145 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9147 #ifdef CONFIG_USER_ONLY
9148 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9149 { .name
= "MIDR_EL1",
9150 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9151 R_MIDR_EL1_PARTNUM_MASK
|
9152 R_MIDR_EL1_ARCHITECTURE_MASK
|
9153 R_MIDR_EL1_VARIANT_MASK
|
9154 R_MIDR_EL1_IMPLEMENTER_MASK
},
9155 { .name
= "REVIDR_EL1" },
9157 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9159 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9160 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9163 * Register the blanket "writes ignored" value first to cover the
9164 * whole space. Then update the specific ID registers to allow write
9165 * access, so that they ignore writes rather than causing them to
9168 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9169 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9170 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9172 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9173 id_cp_reginfo
[i
].access
= PL1_RW
;
9175 id_mpuir_reginfo
.access
= PL1_RW
;
9176 id_tlbtr_reginfo
.access
= PL1_RW
;
9178 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9179 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9180 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9181 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9184 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9186 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9187 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9188 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9189 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9190 arm_feature(env
, ARM_FEATURE_V8
)) {
9194 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9195 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9196 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9198 /* Register alias is only valid for first 32 indexes */
9199 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9200 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9201 uint8_t opc1
= extract32(i
, 4, 1);
9202 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9204 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9205 ARMCPRegInfo tmp_prbarn_reginfo
= {
9206 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9207 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9208 .access
= PL1_RW
, .resetvalue
= 0,
9209 .accessfn
= access_tvm_trvm
,
9210 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9212 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9215 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9216 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9217 ARMCPRegInfo tmp_prlarn_reginfo
= {
9218 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9219 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9220 .access
= PL1_RW
, .resetvalue
= 0,
9221 .accessfn
= access_tvm_trvm
,
9222 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9224 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9228 /* Register alias is only valid for first 32 indexes */
9229 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9230 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9231 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9232 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9234 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9235 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9237 .type
= ARM_CP_NO_RAW
,
9238 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9239 .access
= PL2_RW
, .resetvalue
= 0,
9240 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9242 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9245 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9246 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9247 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9249 .type
= ARM_CP_NO_RAW
,
9250 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9251 .access
= PL2_RW
, .resetvalue
= 0,
9252 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9254 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9257 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9258 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9262 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9263 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9264 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9265 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9266 .fgt
= FGT_MPIDR_EL1
,
9267 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9269 #ifdef CONFIG_USER_ONLY
9270 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9271 { .name
= "MPIDR_EL1",
9272 .fixed_bits
= 0x0000000080000000 },
9274 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9276 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9279 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9280 ARMCPRegInfo auxcr_reginfo
[] = {
9281 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9282 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9283 .access
= PL1_RW
, .accessfn
= access_tacr
,
9284 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9285 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9286 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9287 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9289 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9290 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9291 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9294 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9295 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9296 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9300 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9302 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9303 * There are two flavours:
9304 * (1) older 32-bit only cores have a simple 32-bit CBAR
9305 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9306 * 32-bit register visible to AArch32 at a different encoding
9307 * to the "flavour 1" register and with the bits rearranged to
9308 * be able to squash a 64-bit address into the 32-bit view.
9309 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9310 * in future if we support AArch32-only configs of some of the
9311 * AArch64 cores we might need to add a specific feature flag
9312 * to indicate cores with "flavour 2" CBAR.
9314 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9315 /* 32 bit view is [31:18] 0...0 [43:32]. */
9316 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9317 | extract64(cpu
->reset_cbar
, 32, 12);
9318 ARMCPRegInfo cbar_reginfo
[] = {
9320 .type
= ARM_CP_CONST
,
9321 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9322 .access
= PL1_R
, .resetvalue
= cbar32
},
9323 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9324 .type
= ARM_CP_CONST
,
9325 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9326 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9328 /* We don't implement a r/w 64 bit CBAR currently */
9329 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9330 define_arm_cp_regs(cpu
, cbar_reginfo
);
9332 ARMCPRegInfo cbar
= {
9334 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9335 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9336 .fieldoffset
= offsetof(CPUARMState
,
9337 cp15
.c15_config_base_address
)
9339 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9340 cbar
.access
= PL1_R
;
9341 cbar
.fieldoffset
= 0;
9342 cbar
.type
= ARM_CP_CONST
;
9344 define_one_arm_cp_reg(cpu
, &cbar
);
9348 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9349 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9350 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9351 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9352 .access
= PL1_RW
, .writefn
= vbar_write
,
9353 .fgt
= FGT_VBAR_EL1
,
9354 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9355 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9358 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9361 /* Generic registers whose values depend on the implementation */
9363 ARMCPRegInfo sctlr
= {
9364 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9365 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9366 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9367 .fgt
= FGT_SCTLR_EL1
,
9368 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9369 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9370 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9371 .raw_writefn
= raw_write
,
9373 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9375 * Normally we would always end the TB on an SCTLR write, but Linux
9376 * arch/arm/mach-pxa/sleep.S expects two instructions following
9377 * an MMU enable to execute from cache. Imitate this behaviour.
9379 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9381 define_one_arm_cp_reg(cpu
, &sctlr
);
9383 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9384 arm_feature(env
, ARM_FEATURE_V8
)) {
9385 ARMCPRegInfo vsctlr
= {
9386 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9387 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9388 .access
= PL2_RW
, .resetvalue
= 0x0,
9389 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9391 define_one_arm_cp_reg(cpu
, &vsctlr
);
9395 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9396 define_arm_cp_regs(cpu
, lor_reginfo
);
9398 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9399 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9401 #ifndef CONFIG_USER_ONLY
9402 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9403 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9405 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9406 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9409 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9410 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9413 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9414 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9416 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9417 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9419 if (cpu_isar_feature(any_ras
, cpu
)) {
9420 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9423 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9424 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9425 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9427 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9428 define_arm_cp_regs(cpu
, vhe_reginfo
);
9431 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9432 define_arm_cp_regs(cpu
, zcr_reginfo
);
9435 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9436 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9439 #ifdef TARGET_AARCH64
9440 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9441 define_arm_cp_regs(cpu
, sme_reginfo
);
9443 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9444 define_arm_cp_regs(cpu
, pauth_reginfo
);
9446 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9447 define_arm_cp_regs(cpu
, rndr_reginfo
);
9449 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9450 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9452 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9453 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9455 /* Data Cache clean instructions up to PoP */
9456 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9457 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9459 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9460 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9465 * If full MTE is enabled, add all of the system registers.
9466 * If only "instructions available at EL0" are enabled,
9467 * then define only a RAZ/WI version of PSTATE.TCO.
9469 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9470 ARMCPRegInfo gmid_reginfo
= {
9471 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9472 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9473 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9474 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9476 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9477 define_arm_cp_regs(cpu
, mte_reginfo
);
9478 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9479 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9480 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9481 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9484 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9485 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9488 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9489 define_arm_cp_regs(cpu
, fgt_reginfo
);
9492 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9493 define_arm_cp_regs(cpu
, rme_reginfo
);
9494 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9495 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9500 if (cpu_isar_feature(any_predinv
, cpu
)) {
9501 define_arm_cp_regs(cpu
, predinv_reginfo
);
9504 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9505 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9508 #ifndef CONFIG_USER_ONLY
9510 * Register redirections and aliases must be done last,
9511 * after the registers from the other extensions have been defined.
9513 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9514 define_arm_vh_e2h_redirects_aliases(cpu
);
9520 * Private utility function for define_one_arm_cp_reg_with_opaque():
9521 * add a single reginfo struct to the hash table.
9523 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9524 void *opaque
, CPState state
,
9525 CPSecureState secstate
,
9526 int crm
, int opc1
, int opc2
,
9529 CPUARMState
*env
= &cpu
->env
;
9532 bool is64
= r
->type
& ARM_CP_64BIT
;
9533 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9539 case ARM_CP_STATE_AA32
:
9540 /* We assume it is a cp15 register if the .cp field is left unset. */
9541 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9544 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9546 case ARM_CP_STATE_AA64
:
9548 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9549 * cp == 0 as equivalent to the value for "standard guest-visible
9550 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9551 * in their AArch64 view (the .cp value may be non-zero for the
9552 * benefit of the AArch32 view).
9554 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9555 cp
= CP_REG_ARM64_SYSREG_CP
;
9557 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9560 g_assert_not_reached();
9563 /* Overriding of an existing definition must be explicitly requested. */
9564 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9565 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9567 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9572 * Eliminate registers that are not present because the EL is missing.
9573 * Doing this here makes it easier to put all registers for a given
9574 * feature into the same ARMCPRegInfo array and define them all at once.
9577 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9579 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9580 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9582 int min_el
= ctz32(r
->access
) / 2;
9583 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9584 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9587 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9590 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9592 if ((r
->access
& max_el
) == 0) {
9597 /* Combine cpreg and name into one allocation. */
9598 name_len
= strlen(name
) + 1;
9599 r2
= g_malloc(sizeof(*r2
) + name_len
);
9601 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9604 * Update fields to match the instantiation, overwiting wildcards
9605 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9612 r2
->secure
= secstate
;
9614 r2
->opaque
= opaque
;
9618 /* This should not have been a very special register to begin. */
9619 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9620 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9622 * Set the special function to CONST, retaining the other flags.
9623 * This is important for e.g. ARM_CP_SVE so that we still
9624 * take the SVE trap if CPTR_EL3.EZ == 0.
9626 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9628 * Usually, these registers become RES0, but there are a few
9629 * special cases like VPIDR_EL2 which have a constant non-zero
9630 * value with writes ignored.
9632 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9636 * ARM_CP_CONST has precedence, so removing the callbacks and
9637 * offsets are not strictly necessary, but it is potentially
9638 * less confusing to debug later.
9642 r2
->raw_readfn
= NULL
;
9643 r2
->raw_writefn
= NULL
;
9645 r2
->fieldoffset
= 0;
9646 r2
->bank_fieldoffsets
[0] = 0;
9647 r2
->bank_fieldoffsets
[1] = 0;
9649 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9653 * Register is banked (using both entries in array).
9654 * Overwriting fieldoffset as the array is only used to define
9655 * banked registers but later only fieldoffset is used.
9657 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9659 if (state
== ARM_CP_STATE_AA32
) {
9662 * If the register is banked then we don't need to migrate or
9663 * reset the 32-bit instance in certain cases:
9665 * 1) If the register has both 32-bit and 64-bit instances
9666 * then we can count on the 64-bit instance taking care
9667 * of the non-secure bank.
9668 * 2) If ARMv8 is enabled then we can count on a 64-bit
9669 * version taking care of the secure bank. This requires
9670 * that separate 32 and 64-bit definitions are provided.
9672 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9673 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9674 r2
->type
|= ARM_CP_ALIAS
;
9676 } else if ((secstate
!= r
->secure
) && !ns
) {
9678 * The register is not banked so we only want to allow
9679 * migration of the non-secure instance.
9681 r2
->type
|= ARM_CP_ALIAS
;
9684 if (HOST_BIG_ENDIAN
&&
9685 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9686 r2
->fieldoffset
+= sizeof(uint32_t);
9692 * By convention, for wildcarded registers only the first
9693 * entry is used for migration; the others are marked as
9694 * ALIAS so we don't try to transfer the register
9695 * multiple times. Special registers (ie NOP/WFI) are
9696 * never migratable and not even raw-accessible.
9698 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9699 r2
->type
|= ARM_CP_NO_RAW
;
9701 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9702 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9703 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9704 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9708 * Check that raw accesses are either forbidden or handled. Note that
9709 * we can't assert this earlier because the setup of fieldoffset for
9710 * banked registers has to be done first.
9712 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9713 assert(!raw_accessors_invalid(r2
));
9716 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9720 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9721 const ARMCPRegInfo
*r
, void *opaque
)
9724 * Define implementations of coprocessor registers.
9725 * We store these in a hashtable because typically
9726 * there are less than 150 registers in a space which
9727 * is 16*16*16*8*8 = 262144 in size.
9728 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9729 * If a register is defined twice then the second definition is
9730 * used, so this can be used to define some generic registers and
9731 * then override them with implementation specific variations.
9732 * At least one of the original and the second definition should
9733 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9734 * against accidental use.
9736 * The state field defines whether the register is to be
9737 * visible in the AArch32 or AArch64 execution state. If the
9738 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9739 * reginfo structure for the AArch32 view, which sees the lower
9740 * 32 bits of the 64 bit register.
9742 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9743 * be wildcarded. AArch64 registers are always considered to be 64
9744 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9745 * the register, if any.
9747 int crm
, opc1
, opc2
;
9748 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9749 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9750 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9751 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9752 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9753 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9756 /* 64 bit registers have only CRm and Opc1 fields */
9757 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9758 /* op0 only exists in the AArch64 encodings */
9759 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9760 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9761 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9763 * This API is only for Arm's system coprocessors (14 and 15) or
9764 * (M-profile or v7A-and-earlier only) for implementation defined
9765 * coprocessors in the range 0..7. Our decode assumes this, since
9766 * 8..13 can be used for other insns including VFP and Neon. See
9767 * valid_cp() in translate.c. Assert here that we haven't tried
9768 * to use an invalid coprocessor number.
9771 case ARM_CP_STATE_BOTH
:
9772 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9777 case ARM_CP_STATE_AA32
:
9778 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9779 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9780 assert(r
->cp
>= 14 && r
->cp
<= 15);
9782 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9785 case ARM_CP_STATE_AA64
:
9786 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9789 g_assert_not_reached();
9792 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9793 * encodes a minimum access level for the register. We roll this
9794 * runtime check into our general permission check code, so check
9795 * here that the reginfo's specified permissions are strict enough
9796 * to encompass the generic architectural permission check.
9798 if (r
->state
!= ARM_CP_STATE_AA32
) {
9799 CPAccessRights mask
;
9802 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9803 mask
= PL0U_R
| PL1_RW
;
9823 /* min_EL EL1, secure mode only (we don't check the latter) */
9827 /* broken reginfo with out-of-range opc1 */
9828 g_assert_not_reached();
9830 /* assert our permissions are not too lax (stricter is fine) */
9831 assert((r
->access
& ~mask
) == 0);
9835 * Check that the register definition has enough info to handle
9836 * reads and writes if they are permitted.
9838 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9839 if (r
->access
& PL3_R
) {
9840 assert((r
->fieldoffset
||
9841 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9844 if (r
->access
& PL3_W
) {
9845 assert((r
->fieldoffset
||
9846 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9851 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9852 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9853 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9854 for (state
= ARM_CP_STATE_AA32
;
9855 state
<= ARM_CP_STATE_AA64
; state
++) {
9856 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9859 if (state
== ARM_CP_STATE_AA32
) {
9861 * Under AArch32 CP registers can be common
9862 * (same for secure and non-secure world) or banked.
9866 switch (r
->secure
) {
9867 case ARM_CP_SECSTATE_S
:
9868 case ARM_CP_SECSTATE_NS
:
9869 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9870 r
->secure
, crm
, opc1
, opc2
,
9873 case ARM_CP_SECSTATE_BOTH
:
9874 name
= g_strdup_printf("%s_S", r
->name
);
9875 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9877 crm
, opc1
, opc2
, name
);
9879 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9881 crm
, opc1
, opc2
, r
->name
);
9884 g_assert_not_reached();
9888 * AArch64 registers get mapped to non-secure instance
9891 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9893 crm
, opc1
, opc2
, r
->name
);
9901 /* Define a whole list of registers */
9902 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
9903 void *opaque
, size_t len
)
9906 for (i
= 0; i
< len
; ++i
) {
9907 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
9912 * Modify ARMCPRegInfo for access from userspace.
9914 * This is a data driven modification directed by
9915 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9916 * user-space cannot alter any values and dynamic values pertaining to
9917 * execution state are hidden from user space view anyway.
9919 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
9920 const ARMCPRegUserSpaceInfo
*mods
,
9923 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9924 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9925 GPatternSpec
*pat
= NULL
;
9928 pat
= g_pattern_spec_new(m
->name
);
9930 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9931 ARMCPRegInfo
*r
= regs
+ ri
;
9933 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9934 r
->type
= ARM_CP_CONST
;
9938 } else if (strcmp(r
->name
, m
->name
) == 0) {
9939 r
->type
= ARM_CP_CONST
;
9941 r
->resetvalue
&= m
->exported_bits
;
9942 r
->resetvalue
|= m
->fixed_bits
;
9947 g_pattern_spec_free(pat
);
9952 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9954 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9957 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9960 /* Helper coprocessor write function for write-ignore registers */
9963 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9965 /* Helper coprocessor write function for read-as-zero registers */
9969 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9971 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9974 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9977 * Return true if it is not valid for us to switch to
9978 * this CPU mode (ie all the UNPREDICTABLE cases in
9979 * the ARM ARM CPSRWriteByInstr pseudocode).
9982 /* Changes to or from Hyp via MSR and CPS are illegal. */
9983 if (write_type
== CPSRWriteByInstr
&&
9984 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9985 mode
== ARM_CPU_MODE_HYP
)) {
9990 case ARM_CPU_MODE_USR
:
9992 case ARM_CPU_MODE_SYS
:
9993 case ARM_CPU_MODE_SVC
:
9994 case ARM_CPU_MODE_ABT
:
9995 case ARM_CPU_MODE_UND
:
9996 case ARM_CPU_MODE_IRQ
:
9997 case ARM_CPU_MODE_FIQ
:
9999 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
10000 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
10003 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
10004 * and CPS are treated as illegal mode changes.
10006 if (write_type
== CPSRWriteByInstr
&&
10007 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
10008 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
10012 case ARM_CPU_MODE_HYP
:
10013 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
10014 case ARM_CPU_MODE_MON
:
10015 return arm_current_el(env
) < 3;
10021 uint32_t cpsr_read(CPUARMState
*env
)
10024 ZF
= (env
->ZF
== 0);
10025 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
10026 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
10027 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
10028 | ((env
->condexec_bits
& 0xfc) << 8)
10029 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
10032 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
10033 CPSRWriteType write_type
)
10035 uint32_t changed_daif
;
10036 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
10037 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
10039 if (mask
& CPSR_NZCV
) {
10040 env
->ZF
= (~val
) & CPSR_Z
;
10042 env
->CF
= (val
>> 29) & 1;
10043 env
->VF
= (val
<< 3) & 0x80000000;
10045 if (mask
& CPSR_Q
) {
10046 env
->QF
= ((val
& CPSR_Q
) != 0);
10048 if (mask
& CPSR_T
) {
10049 env
->thumb
= ((val
& CPSR_T
) != 0);
10051 if (mask
& CPSR_IT_0_1
) {
10052 env
->condexec_bits
&= ~3;
10053 env
->condexec_bits
|= (val
>> 25) & 3;
10055 if (mask
& CPSR_IT_2_7
) {
10056 env
->condexec_bits
&= 3;
10057 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10059 if (mask
& CPSR_GE
) {
10060 env
->GE
= (val
>> 16) & 0xf;
10064 * In a V7 implementation that includes the security extensions but does
10065 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10066 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10067 * bits respectively.
10069 * In a V8 implementation, it is permitted for privileged software to
10070 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10072 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10073 arm_feature(env
, ARM_FEATURE_EL3
) &&
10074 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10075 !arm_is_secure(env
)) {
10077 changed_daif
= (env
->daif
^ val
) & mask
;
10079 if (changed_daif
& CPSR_A
) {
10081 * Check to see if we are allowed to change the masking of async
10082 * abort exceptions from a non-secure state.
10084 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10085 qemu_log_mask(LOG_GUEST_ERROR
,
10086 "Ignoring attempt to switch CPSR_A flag from "
10087 "non-secure world with SCR.AW bit clear\n");
10092 if (changed_daif
& CPSR_F
) {
10094 * Check to see if we are allowed to change the masking of FIQ
10095 * exceptions from a non-secure state.
10097 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10098 qemu_log_mask(LOG_GUEST_ERROR
,
10099 "Ignoring attempt to switch CPSR_F flag from "
10100 "non-secure world with SCR.FW bit clear\n");
10105 * Check whether non-maskable FIQ (NMFI) support is enabled.
10106 * If this bit is set software is not allowed to mask
10107 * FIQs, but is allowed to set CPSR_F to 0.
10109 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10111 qemu_log_mask(LOG_GUEST_ERROR
,
10112 "Ignoring attempt to enable CPSR_F flag "
10113 "(non-maskable FIQ [NMFI] support enabled)\n");
10119 env
->daif
&= ~(CPSR_AIF
& mask
);
10120 env
->daif
|= val
& CPSR_AIF
& mask
;
10122 if (write_type
!= CPSRWriteRaw
&&
10123 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10124 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10126 * Note that we can only get here in USR mode if this is a
10127 * gdb stub write; for this case we follow the architectural
10128 * behaviour for guest writes in USR mode of ignoring an attempt
10129 * to switch mode. (Those are caught by translate.c for writes
10130 * triggered by guest instructions.)
10133 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10135 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10136 * v7, and has defined behaviour in v8:
10137 * + leave CPSR.M untouched
10138 * + allow changes to the other CPSR fields
10140 * For user changes via the GDB stub, we don't set PSTATE.IL,
10141 * as this would be unnecessarily harsh for a user error.
10144 if (write_type
!= CPSRWriteByGDBStub
&&
10145 arm_feature(env
, ARM_FEATURE_V8
)) {
10149 qemu_log_mask(LOG_GUEST_ERROR
,
10150 "Illegal AArch32 mode switch attempt from %s to %s\n",
10151 aarch32_mode_name(env
->uncached_cpsr
),
10152 aarch32_mode_name(val
));
10154 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10155 write_type
== CPSRWriteExceptionReturn
?
10156 "Exception return from AArch32" :
10157 "AArch32 mode switch from",
10158 aarch32_mode_name(env
->uncached_cpsr
),
10159 aarch32_mode_name(val
), env
->regs
[15]);
10160 switch_mode(env
, val
& CPSR_M
);
10163 mask
&= ~CACHED_CPSR_BITS
;
10164 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10165 if (tcg_enabled() && rebuild_hflags
) {
10166 arm_rebuild_hflags(env
);
10170 #ifdef CONFIG_USER_ONLY
10172 static void switch_mode(CPUARMState
*env
, int mode
)
10174 ARMCPU
*cpu
= env_archcpu(env
);
10176 if (mode
!= ARM_CPU_MODE_USR
) {
10177 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10181 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10182 uint32_t cur_el
, bool secure
)
10187 void aarch64_sync_64_to_32(CPUARMState
*env
)
10189 g_assert_not_reached();
10194 static void switch_mode(CPUARMState
*env
, int mode
)
10199 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10200 if (mode
== old_mode
) {
10204 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10205 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10206 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10207 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10208 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10209 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10212 i
= bank_number(old_mode
);
10213 env
->banked_r13
[i
] = env
->regs
[13];
10214 env
->banked_spsr
[i
] = env
->spsr
;
10216 i
= bank_number(mode
);
10217 env
->regs
[13] = env
->banked_r13
[i
];
10218 env
->spsr
= env
->banked_spsr
[i
];
10220 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10221 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10225 * Physical Interrupt Target EL Lookup Table
10227 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10229 * The below multi-dimensional table is used for looking up the target
10230 * exception level given numerous condition criteria. Specifically, the
10231 * target EL is based on SCR and HCR routing controls as well as the
10232 * currently executing EL and secure state.
10235 * target_el_table[2][2][2][2][2][4]
10236 * | | | | | +--- Current EL
10237 * | | | | +------ Non-secure(0)/Secure(1)
10238 * | | | +--------- HCR mask override
10239 * | | +------------ SCR exec state control
10240 * | +--------------- SCR mask override
10241 * +------------------ 32-bit(0)/64-bit(1) EL3
10243 * The table values are as such:
10245 * -1 = Cannot occur
10247 * The ARM ARM target EL table includes entries indicating that an "exception
10248 * is not taken". The two cases where this is applicable are:
10249 * 1) An exception is taken from EL3 but the SCR does not have the exception
10251 * 2) An exception is taken from EL2 but the HCR does not have the exception
10253 * In these two cases, the below table contain a target of EL1. This value is
10254 * returned as it is expected that the consumer of the table data will check
10255 * for "target EL >= current EL" to ensure the exception is not taken.
10259 * BIT IRQ IMO Non-secure Secure
10260 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10262 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10263 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10264 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10265 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10266 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10267 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10268 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10269 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10270 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10271 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10272 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10273 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10274 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10275 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10276 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10277 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10278 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10282 * Determine the target EL for physical exceptions
10284 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10285 uint32_t cur_el
, bool secure
)
10287 CPUARMState
*env
= cpu_env(cs
);
10292 /* Is the highest EL AArch64? */
10293 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10296 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10297 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10300 * Either EL2 is the highest EL (and so the EL2 register width
10301 * is given by is64); or there is no EL2 or EL3, in which case
10302 * the value of 'rw' does not affect the table lookup anyway.
10307 hcr_el2
= arm_hcr_el2_eff(env
);
10308 switch (excp_idx
) {
10310 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10311 hcr
= hcr_el2
& HCR_IMO
;
10314 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10315 hcr
= hcr_el2
& HCR_FMO
;
10318 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10319 hcr
= hcr_el2
& HCR_AMO
;
10324 * For these purposes, TGE and AMO/IMO/FMO both force the
10325 * interrupt to EL2. Fold TGE into the bit extracted above.
10327 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10329 /* Perform a table-lookup for the target EL given the current state */
10330 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10332 assert(target_el
> 0);
10337 void arm_log_exception(CPUState
*cs
)
10339 int idx
= cs
->exception_index
;
10341 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10342 const char *exc
= NULL
;
10343 static const char * const excnames
[] = {
10344 [EXCP_UDEF
] = "Undefined Instruction",
10345 [EXCP_SWI
] = "SVC",
10346 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10347 [EXCP_DATA_ABORT
] = "Data Abort",
10348 [EXCP_IRQ
] = "IRQ",
10349 [EXCP_FIQ
] = "FIQ",
10350 [EXCP_BKPT
] = "Breakpoint",
10351 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10352 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10353 [EXCP_HVC
] = "Hypervisor Call",
10354 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10355 [EXCP_SMC
] = "Secure Monitor Call",
10356 [EXCP_VIRQ
] = "Virtual IRQ",
10357 [EXCP_VFIQ
] = "Virtual FIQ",
10358 [EXCP_SEMIHOST
] = "Semihosting call",
10359 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10360 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10361 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10362 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10363 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10364 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10365 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10366 [EXCP_VSERR
] = "Virtual SERR",
10367 [EXCP_GPC
] = "Granule Protection Check",
10370 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10371 exc
= excnames
[idx
];
10376 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10377 idx
, exc
, cs
->cpu_index
);
10382 * Function used to synchronize QEMU's AArch64 register set with AArch32
10383 * register set. This is necessary when switching between AArch32 and AArch64
10386 void aarch64_sync_32_to_64(CPUARMState
*env
)
10389 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10391 /* We can blanket copy R[0:7] to X[0:7] */
10392 for (i
= 0; i
< 8; i
++) {
10393 env
->xregs
[i
] = env
->regs
[i
];
10397 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10398 * Otherwise, they come from the banked user regs.
10400 if (mode
== ARM_CPU_MODE_FIQ
) {
10401 for (i
= 8; i
< 13; i
++) {
10402 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10405 for (i
= 8; i
< 13; i
++) {
10406 env
->xregs
[i
] = env
->regs
[i
];
10411 * Registers x13-x23 are the various mode SP and FP registers. Registers
10412 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10413 * from the mode banked register.
10415 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10416 env
->xregs
[13] = env
->regs
[13];
10417 env
->xregs
[14] = env
->regs
[14];
10419 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10420 /* HYP is an exception in that it is copied from r14 */
10421 if (mode
== ARM_CPU_MODE_HYP
) {
10422 env
->xregs
[14] = env
->regs
[14];
10424 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10428 if (mode
== ARM_CPU_MODE_HYP
) {
10429 env
->xregs
[15] = env
->regs
[13];
10431 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10434 if (mode
== ARM_CPU_MODE_IRQ
) {
10435 env
->xregs
[16] = env
->regs
[14];
10436 env
->xregs
[17] = env
->regs
[13];
10438 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10439 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10442 if (mode
== ARM_CPU_MODE_SVC
) {
10443 env
->xregs
[18] = env
->regs
[14];
10444 env
->xregs
[19] = env
->regs
[13];
10446 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10447 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10450 if (mode
== ARM_CPU_MODE_ABT
) {
10451 env
->xregs
[20] = env
->regs
[14];
10452 env
->xregs
[21] = env
->regs
[13];
10454 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10455 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10458 if (mode
== ARM_CPU_MODE_UND
) {
10459 env
->xregs
[22] = env
->regs
[14];
10460 env
->xregs
[23] = env
->regs
[13];
10462 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10463 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10467 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10468 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10469 * FIQ bank for r8-r14.
10471 if (mode
== ARM_CPU_MODE_FIQ
) {
10472 for (i
= 24; i
< 31; i
++) {
10473 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10476 for (i
= 24; i
< 29; i
++) {
10477 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10479 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10480 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10483 env
->pc
= env
->regs
[15];
10487 * Function used to synchronize QEMU's AArch32 register set with AArch64
10488 * register set. This is necessary when switching between AArch32 and AArch64
10491 void aarch64_sync_64_to_32(CPUARMState
*env
)
10494 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10496 /* We can blanket copy X[0:7] to R[0:7] */
10497 for (i
= 0; i
< 8; i
++) {
10498 env
->regs
[i
] = env
->xregs
[i
];
10502 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10503 * Otherwise, we copy x8-x12 into the banked user regs.
10505 if (mode
== ARM_CPU_MODE_FIQ
) {
10506 for (i
= 8; i
< 13; i
++) {
10507 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10510 for (i
= 8; i
< 13; i
++) {
10511 env
->regs
[i
] = env
->xregs
[i
];
10516 * Registers r13 & r14 depend on the current mode.
10517 * If we are in a given mode, we copy the corresponding x registers to r13
10518 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10521 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10522 env
->regs
[13] = env
->xregs
[13];
10523 env
->regs
[14] = env
->xregs
[14];
10525 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10528 * HYP is an exception in that it does not have its own banked r14 but
10529 * shares the USR r14
10531 if (mode
== ARM_CPU_MODE_HYP
) {
10532 env
->regs
[14] = env
->xregs
[14];
10534 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10538 if (mode
== ARM_CPU_MODE_HYP
) {
10539 env
->regs
[13] = env
->xregs
[15];
10541 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10544 if (mode
== ARM_CPU_MODE_IRQ
) {
10545 env
->regs
[14] = env
->xregs
[16];
10546 env
->regs
[13] = env
->xregs
[17];
10548 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10549 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10552 if (mode
== ARM_CPU_MODE_SVC
) {
10553 env
->regs
[14] = env
->xregs
[18];
10554 env
->regs
[13] = env
->xregs
[19];
10556 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10557 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10560 if (mode
== ARM_CPU_MODE_ABT
) {
10561 env
->regs
[14] = env
->xregs
[20];
10562 env
->regs
[13] = env
->xregs
[21];
10564 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10565 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10568 if (mode
== ARM_CPU_MODE_UND
) {
10569 env
->regs
[14] = env
->xregs
[22];
10570 env
->regs
[13] = env
->xregs
[23];
10572 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10573 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10577 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10578 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10579 * FIQ bank for r8-r14.
10581 if (mode
== ARM_CPU_MODE_FIQ
) {
10582 for (i
= 24; i
< 31; i
++) {
10583 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10586 for (i
= 24; i
< 29; i
++) {
10587 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10589 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10590 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10593 env
->regs
[15] = env
->pc
;
10596 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10597 uint32_t mask
, uint32_t offset
,
10602 /* Change the CPU state so as to actually take the exception. */
10603 switch_mode(env
, new_mode
);
10606 * For exceptions taken to AArch32 we must clear the SS bit in both
10607 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10609 env
->pstate
&= ~PSTATE_SS
;
10610 env
->spsr
= cpsr_read(env
);
10611 /* Clear IT bits. */
10612 env
->condexec_bits
= 0;
10613 /* Switch to the new mode, and to the correct instruction set. */
10614 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10616 /* This must be after mode switching. */
10617 new_el
= arm_current_el(env
);
10619 /* Set new mode endianness */
10620 env
->uncached_cpsr
&= ~CPSR_E
;
10621 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10622 env
->uncached_cpsr
|= CPSR_E
;
10624 /* J and IL must always be cleared for exception entry */
10625 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10628 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10629 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10630 env
->uncached_cpsr
|= CPSR_SSBS
;
10632 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10636 if (new_mode
== ARM_CPU_MODE_HYP
) {
10637 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10638 env
->elr_el
[2] = env
->regs
[15];
10640 /* CPSR.PAN is normally preserved preserved unless... */
10641 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10644 if (!arm_is_secure_below_el3(env
)) {
10645 /* ... the target is EL3, from non-secure state. */
10646 env
->uncached_cpsr
&= ~CPSR_PAN
;
10649 /* ... the target is EL3, from secure state ... */
10652 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10653 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10654 env
->uncached_cpsr
|= CPSR_PAN
;
10660 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10661 * and we should just guard the thumb mode on V4
10663 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10665 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10667 env
->regs
[14] = env
->regs
[15] + offset
;
10669 env
->regs
[15] = newpc
;
10671 if (tcg_enabled()) {
10672 arm_rebuild_hflags(env
);
10676 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10679 * Handle exception entry to Hyp mode; this is sufficiently
10680 * different to entry to other AArch32 modes that we handle it
10683 * The vector table entry used is always the 0x14 Hyp mode entry point,
10684 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10685 * The offset applied to the preferred return address is always zero
10686 * (see DDI0487C.a section G1.12.3).
10687 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10689 uint32_t addr
, mask
;
10690 ARMCPU
*cpu
= ARM_CPU(cs
);
10691 CPUARMState
*env
= &cpu
->env
;
10693 switch (cs
->exception_index
) {
10701 /* Fall through to prefetch abort. */
10702 case EXCP_PREFETCH_ABORT
:
10703 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10704 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10705 (uint32_t)env
->exception
.vaddress
);
10708 case EXCP_DATA_ABORT
:
10709 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10710 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10711 (uint32_t)env
->exception
.vaddress
);
10723 case EXCP_HYP_TRAP
:
10727 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10730 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10731 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10733 * QEMU syndrome values are v8-style. v7 has the IL bit
10734 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10735 * If this is a v7 CPU, squash the IL bit in those cases.
10737 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10738 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10739 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10740 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10741 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10744 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10747 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10752 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10755 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10758 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10762 addr
+= env
->cp15
.hvbar
;
10764 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10767 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10769 ARMCPU
*cpu
= ARM_CPU(cs
);
10770 CPUARMState
*env
= &cpu
->env
;
10777 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10778 switch (syn_get_ec(env
->exception
.syndrome
)) {
10779 case EC_BREAKPOINT
:
10780 case EC_BREAKPOINT_SAME_EL
:
10783 case EC_WATCHPOINT
:
10784 case EC_WATCHPOINT_SAME_EL
:
10790 case EC_VECTORCATCH
:
10799 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10802 if (env
->exception
.target_el
== 2) {
10803 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10807 switch (cs
->exception_index
) {
10809 new_mode
= ARM_CPU_MODE_UND
;
10819 new_mode
= ARM_CPU_MODE_SVC
;
10822 /* The PC already points to the next instruction. */
10826 /* Fall through to prefetch abort. */
10827 case EXCP_PREFETCH_ABORT
:
10828 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10829 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10830 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10831 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10832 new_mode
= ARM_CPU_MODE_ABT
;
10834 mask
= CPSR_A
| CPSR_I
;
10837 case EXCP_DATA_ABORT
:
10838 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10839 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10840 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10841 env
->exception
.fsr
,
10842 (uint32_t)env
->exception
.vaddress
);
10843 new_mode
= ARM_CPU_MODE_ABT
;
10845 mask
= CPSR_A
| CPSR_I
;
10849 new_mode
= ARM_CPU_MODE_IRQ
;
10851 /* Disable IRQ and imprecise data aborts. */
10852 mask
= CPSR_A
| CPSR_I
;
10854 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10855 /* IRQ routed to monitor mode */
10856 new_mode
= ARM_CPU_MODE_MON
;
10861 new_mode
= ARM_CPU_MODE_FIQ
;
10863 /* Disable FIQ, IRQ and imprecise data aborts. */
10864 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10865 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10866 /* FIQ routed to monitor mode */
10867 new_mode
= ARM_CPU_MODE_MON
;
10872 new_mode
= ARM_CPU_MODE_IRQ
;
10874 /* Disable IRQ and imprecise data aborts. */
10875 mask
= CPSR_A
| CPSR_I
;
10879 new_mode
= ARM_CPU_MODE_FIQ
;
10881 /* Disable FIQ, IRQ and imprecise data aborts. */
10882 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10888 * Note that this is reported as a data abort, but the DFAR
10889 * has an UNKNOWN value. Construct the SError syndrome from
10890 * AET and ExT fields.
10892 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10894 if (extended_addresses_enabled(env
)) {
10895 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10897 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10899 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10900 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10901 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10902 env
->exception
.fsr
);
10904 new_mode
= ARM_CPU_MODE_ABT
;
10906 mask
= CPSR_A
| CPSR_I
;
10911 new_mode
= ARM_CPU_MODE_MON
;
10913 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10917 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10918 return; /* Never happens. Keep compiler happy. */
10921 if (new_mode
== ARM_CPU_MODE_MON
) {
10922 addr
+= env
->cp15
.mvbar
;
10923 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10924 /* High vectors. When enabled, base address cannot be remapped. */
10925 addr
+= 0xffff0000;
10928 * ARM v7 architectures provide a vector base address register to remap
10929 * the interrupt vector table.
10930 * This register is only followed in non-monitor mode, and is banked.
10931 * Note: only bits 31:5 are valid.
10933 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10936 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10937 env
->cp15
.scr_el3
&= ~SCR_NS
;
10940 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10943 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10946 * Return the register number of the AArch64 view of the AArch32
10947 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10948 * be that of the AArch32 mode the exception came from.
10950 int mode
= env
->uncached_cpsr
& CPSR_M
;
10952 switch (aarch32_reg
) {
10954 return aarch32_reg
;
10956 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10959 case ARM_CPU_MODE_USR
:
10960 case ARM_CPU_MODE_SYS
:
10962 case ARM_CPU_MODE_HYP
:
10964 case ARM_CPU_MODE_IRQ
:
10966 case ARM_CPU_MODE_SVC
:
10968 case ARM_CPU_MODE_ABT
:
10970 case ARM_CPU_MODE_UND
:
10972 case ARM_CPU_MODE_FIQ
:
10975 g_assert_not_reached();
10979 case ARM_CPU_MODE_USR
:
10980 case ARM_CPU_MODE_SYS
:
10981 case ARM_CPU_MODE_HYP
:
10983 case ARM_CPU_MODE_IRQ
:
10985 case ARM_CPU_MODE_SVC
:
10987 case ARM_CPU_MODE_ABT
:
10989 case ARM_CPU_MODE_UND
:
10991 case ARM_CPU_MODE_FIQ
:
10994 g_assert_not_reached();
10999 g_assert_not_reached();
11003 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11005 uint32_t ret
= cpsr_read(env
);
11007 /* Move DIT to the correct location for SPSR_ELx */
11008 if (ret
& CPSR_DIT
) {
11012 /* Merge PSTATE.SS into SPSR_ELx */
11013 ret
|= env
->pstate
& PSTATE_SS
;
11018 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11020 /* Return true if this syndrome value is a synchronous external abort */
11021 switch (syn_get_ec(syndrome
)) {
11023 case EC_INSNABORT_SAME_EL
:
11025 case EC_DATAABORT_SAME_EL
:
11026 /* Look at fault status code for all the synchronous ext abort cases */
11027 switch (syndrome
& 0x3f) {
11043 /* Handle exception entry to a target EL which is using AArch64 */
11044 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11046 ARMCPU
*cpu
= ARM_CPU(cs
);
11047 CPUARMState
*env
= &cpu
->env
;
11048 unsigned int new_el
= env
->exception
.target_el
;
11049 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11050 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11051 unsigned int old_mode
;
11052 unsigned int cur_el
= arm_current_el(env
);
11055 if (tcg_enabled()) {
11057 * Note that new_el can never be 0. If cur_el is 0, then
11058 * el0_a64 is is_a64(), else el0_a64 is ignored.
11060 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11063 if (cur_el
< new_el
) {
11065 * Entry vector offset depends on whether the implemented EL
11066 * immediately lower than the target level is using AArch32 or AArch64
11073 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11076 hcr
= arm_hcr_el2_eff(env
);
11077 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11078 is_aa64
= (hcr
& HCR_RW
) != 0;
11083 is_aa64
= is_a64(env
);
11086 g_assert_not_reached();
11094 } else if (pstate_read(env
) & PSTATE_SP
) {
11098 switch (cs
->exception_index
) {
11100 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11101 env
->cp15
.mfar_el3
);
11103 case EXCP_PREFETCH_ABORT
:
11104 case EXCP_DATA_ABORT
:
11106 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11107 * to be taken to the SError vector entrypoint.
11109 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11110 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11113 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11114 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11115 env
->cp15
.far_el
[new_el
]);
11121 case EXCP_HYP_TRAP
:
11123 switch (syn_get_ec(env
->exception
.syndrome
)) {
11124 case EC_ADVSIMDFPACCESSTRAP
:
11126 * QEMU internal FP/SIMD syndromes from AArch32 include the
11127 * TA and coproc fields which are only exposed if the exception
11128 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11129 * AArch64 format syndrome.
11131 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11133 case EC_CP14RTTRAP
:
11134 case EC_CP15RTTRAP
:
11135 case EC_CP14DTTRAP
:
11137 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11138 * the raw register field from the insn; when taking this to
11139 * AArch64 we must convert it to the AArch64 view of the register
11140 * number. Notice that we read a 4-bit AArch32 register number and
11141 * write back a 5-bit AArch64 one.
11143 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11144 rt
= aarch64_regnum(env
, rt
);
11145 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11148 case EC_CP15RRTTRAP
:
11149 case EC_CP14RRTTRAP
:
11150 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11151 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11152 rt
= aarch64_regnum(env
, rt
);
11153 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11155 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11156 rt
= aarch64_regnum(env
, rt
);
11157 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11161 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11173 /* Construct the SError syndrome from IDS and ISS fields. */
11174 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11175 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11178 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11182 old_mode
= pstate_read(env
);
11183 aarch64_save_sp(env
, arm_current_el(env
));
11184 env
->elr_el
[new_el
] = env
->pc
;
11186 old_mode
= cpsr_read_for_spsr_elx(env
);
11187 env
->elr_el
[new_el
] = env
->regs
[15];
11189 aarch64_sync_32_to_64(env
);
11191 env
->condexec_bits
= 0;
11193 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11195 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11196 env
->elr_el
[new_el
]);
11198 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11199 /* The value of PSTATE.PAN is normally preserved, except when ... */
11200 new_mode
|= old_mode
& PSTATE_PAN
;
11203 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11204 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11205 != (HCR_E2H
| HCR_TGE
)) {
11210 /* ... the target is EL1 ... */
11211 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11212 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11213 new_mode
|= PSTATE_PAN
;
11218 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11219 new_mode
|= PSTATE_TCO
;
11222 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11223 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11224 new_mode
|= PSTATE_SSBS
;
11226 new_mode
&= ~PSTATE_SSBS
;
11230 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11231 env
->aarch64
= true;
11232 aarch64_restore_sp(env
, new_el
);
11234 if (tcg_enabled()) {
11235 helper_rebuild_hflags_a64(env
, new_el
);
11240 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11241 new_el
, env
->pc
, pstate_read(env
));
11245 * Do semihosting call and set the appropriate return value. All the
11246 * permission and validity checks have been done at translate time.
11248 * We only see semihosting exceptions in TCG only as they are not
11249 * trapped to the hypervisor in KVM.
11252 static void tcg_handle_semihosting(CPUState
*cs
)
11254 ARMCPU
*cpu
= ARM_CPU(cs
);
11255 CPUARMState
*env
= &cpu
->env
;
11258 qemu_log_mask(CPU_LOG_INT
,
11259 "...handling as semihosting call 0x%" PRIx64
"\n",
11261 do_common_semihosting(cs
);
11264 qemu_log_mask(CPU_LOG_INT
,
11265 "...handling as semihosting call 0x%x\n",
11267 do_common_semihosting(cs
);
11268 env
->regs
[15] += env
->thumb
? 2 : 4;
11274 * Handle a CPU exception for A and R profile CPUs.
11275 * Do any appropriate logging, handle PSCI calls, and then hand off
11276 * to the AArch64-entry or AArch32-entry function depending on the
11277 * target exception level's register width.
11279 * Note: this is used for both TCG (as the do_interrupt tcg op),
11280 * and KVM to re-inject guest debug exceptions, and to
11281 * inject a Synchronous-External-Abort.
11283 void arm_cpu_do_interrupt(CPUState
*cs
)
11285 ARMCPU
*cpu
= ARM_CPU(cs
);
11286 CPUARMState
*env
= &cpu
->env
;
11287 unsigned int new_el
= env
->exception
.target_el
;
11289 assert(!arm_feature(env
, ARM_FEATURE_M
));
11291 arm_log_exception(cs
);
11292 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11294 if (qemu_loglevel_mask(CPU_LOG_INT
)
11295 && !excp_is_internal(cs
->exception_index
)) {
11296 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11297 syn_get_ec(env
->exception
.syndrome
),
11298 env
->exception
.syndrome
);
11301 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11302 arm_handle_psci_call(cpu
);
11303 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11308 * Semihosting semantics depend on the register width of the code
11309 * that caused the exception, not the target exception level, so
11310 * must be handled here.
11313 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11314 tcg_handle_semihosting(cs
);
11320 * Hooks may change global state so BQL should be held, also the
11321 * BQL needs to be held for any modification of
11322 * cs->interrupt_request.
11324 g_assert(bql_locked());
11326 arm_call_pre_el_change_hook(cpu
);
11328 assert(!excp_is_internal(cs
->exception_index
));
11329 if (arm_el_is_aa64(env
, new_el
)) {
11330 arm_cpu_do_interrupt_aarch64(cs
);
11332 arm_cpu_do_interrupt_aarch32(cs
);
11335 arm_call_el_change_hook(cpu
);
11337 if (!kvm_enabled()) {
11338 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11341 #endif /* !CONFIG_USER_ONLY */
11343 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11345 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11347 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11348 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11350 return env
->cp15
.sctlr_el
[el
];
11353 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11355 if (regime_has_2_ranges(mmu_idx
)) {
11356 return extract64(tcr
, 37, 2);
11357 } else if (regime_is_stage2(mmu_idx
)) {
11358 return 0; /* VTCR_EL2 */
11360 /* Replicate the single TBI bit so we always have 2 bits. */
11361 return extract32(tcr
, 20, 1) * 3;
11365 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11367 if (regime_has_2_ranges(mmu_idx
)) {
11368 return extract64(tcr
, 51, 2);
11369 } else if (regime_is_stage2(mmu_idx
)) {
11370 return 0; /* VTCR_EL2 */
11372 /* Replicate the single TBID bit so we always have 2 bits. */
11373 return extract32(tcr
, 29, 1) * 3;
11377 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11379 if (regime_has_2_ranges(mmu_idx
)) {
11380 return extract64(tcr
, 57, 2);
11382 /* Replicate the single TCMA bit so we always have 2 bits. */
11383 return extract32(tcr
, 30, 1) * 3;
11387 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11397 return GranInvalid
;
11401 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11411 return GranInvalid
;
11415 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11417 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11418 : cpu_isar_feature(aa64_tgran4
, cpu
);
11421 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11423 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11424 : cpu_isar_feature(aa64_tgran16
, cpu
);
11427 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11429 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11430 : cpu_isar_feature(aa64_tgran64
, cpu
);
11433 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11438 if (have4k(cpu
, stage2
)) {
11443 if (have16k(cpu
, stage2
)) {
11448 if (have64k(cpu
, stage2
)) {
11456 * If the guest selects a granule size that isn't implemented,
11457 * the architecture requires that we behave as if it selected one
11458 * that is (with an IMPDEF choice of which one to pick). We choose
11459 * to implement the smallest supported granule size.
11461 if (have4k(cpu
, stage2
)) {
11464 if (have16k(cpu
, stage2
)) {
11467 assert(have64k(cpu
, stage2
));
11471 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11472 ARMMMUIdx mmu_idx
, bool data
,
11475 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11476 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11477 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11478 ARMGranuleSize gran
;
11479 ARMCPU
*cpu
= env_archcpu(env
);
11480 bool stage2
= regime_is_stage2(mmu_idx
);
11482 if (!regime_has_2_ranges(mmu_idx
)) {
11484 tsz
= extract32(tcr
, 0, 6);
11485 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11490 hpd
= extract32(tcr
, 24, 1);
11493 sh
= extract32(tcr
, 12, 2);
11494 ps
= extract32(tcr
, 16, 3);
11495 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11496 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11497 ds
= extract64(tcr
, 32, 1);
11502 * Bit 55 is always between the two regions, and is canonical for
11503 * determining if address tagging is enabled.
11505 select
= extract64(va
, 55, 1);
11507 tsz
= extract32(tcr
, 0, 6);
11508 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11509 epd
= extract32(tcr
, 7, 1);
11510 sh
= extract32(tcr
, 12, 2);
11511 hpd
= extract64(tcr
, 41, 1);
11512 e0pd
= extract64(tcr
, 55, 1);
11514 tsz
= extract32(tcr
, 16, 6);
11515 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11516 epd
= extract32(tcr
, 23, 1);
11517 sh
= extract32(tcr
, 28, 2);
11518 hpd
= extract64(tcr
, 42, 1);
11519 e0pd
= extract64(tcr
, 56, 1);
11521 ps
= extract64(tcr
, 32, 3);
11522 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11523 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11524 ds
= extract64(tcr
, 59, 1);
11526 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11527 regime_is_user(env
, mmu_idx
)) {
11532 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11534 if (cpu_isar_feature(aa64_st
, cpu
)) {
11535 max_tsz
= 48 - (gran
== Gran64K
);
11541 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11542 * adjust the effective value of DS, as documented.
11545 if (gran
== Gran64K
) {
11546 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11551 if (regime_is_stage2(mmu_idx
)) {
11552 if (gran
== Gran16K
) {
11553 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11555 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11558 if (gran
== Gran16K
) {
11559 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11561 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11569 if (stage2
&& el1_is_aa32
) {
11571 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11572 * are loosened: a configured IPA of 40 bits is permitted even if
11573 * the implemented PA is less than that (and so a 40 bit IPA would
11574 * fault for an AArch64 EL1). See R_DTLMN.
11576 min_tsz
= MIN(min_tsz
, 24);
11579 if (tsz
> max_tsz
) {
11582 } else if (tsz
< min_tsz
) {
11589 /* Present TBI as a composite with TBID. */
11590 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11592 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11594 tbi
= (tbi
>> select
) & 1;
11596 return (ARMVAParameters
) {
11604 .tsz_oob
= tsz_oob
,
11613 * Note that signed overflow is undefined in C. The following routines are
11614 * careful to use unsigned types where modulo arithmetic is required.
11615 * Failure to do so _will_ break on newer gcc.
11618 /* Signed saturating arithmetic. */
11620 /* Perform 16-bit signed saturating addition. */
11621 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11626 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11636 /* Perform 8-bit signed saturating addition. */
11637 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11642 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11652 /* Perform 16-bit signed saturating subtraction. */
11653 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11658 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11668 /* Perform 8-bit signed saturating subtraction. */
11669 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11674 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11684 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11685 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11686 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11687 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11690 #include "op_addsub.h"
11692 /* Unsigned saturating arithmetic. */
11693 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11703 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11712 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11722 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11731 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11732 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11733 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11734 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11737 #include "op_addsub.h"
11739 /* Signed modulo arithmetic. */
11740 #define SARITH16(a, b, n, op) do { \
11742 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11743 RESULT(sum, n, 16); \
11745 ge |= 3 << (n * 2); \
11748 #define SARITH8(a, b, n, op) do { \
11750 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11751 RESULT(sum, n, 8); \
11757 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11758 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11759 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11760 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11764 #include "op_addsub.h"
11766 /* Unsigned modulo arithmetic. */
11767 #define ADD16(a, b, n) do { \
11769 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11770 RESULT(sum, n, 16); \
11771 if ((sum >> 16) == 1) \
11772 ge |= 3 << (n * 2); \
11775 #define ADD8(a, b, n) do { \
11777 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11778 RESULT(sum, n, 8); \
11779 if ((sum >> 8) == 1) \
11783 #define SUB16(a, b, n) do { \
11785 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11786 RESULT(sum, n, 16); \
11787 if ((sum >> 16) == 0) \
11788 ge |= 3 << (n * 2); \
11791 #define SUB8(a, b, n) do { \
11793 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11794 RESULT(sum, n, 8); \
11795 if ((sum >> 8) == 0) \
11802 #include "op_addsub.h"
11804 /* Halved signed arithmetic. */
11805 #define ADD16(a, b, n) \
11806 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11807 #define SUB16(a, b, n) \
11808 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11809 #define ADD8(a, b, n) \
11810 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11811 #define SUB8(a, b, n) \
11812 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11815 #include "op_addsub.h"
11817 /* Halved unsigned arithmetic. */
11818 #define ADD16(a, b, n) \
11819 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11820 #define SUB16(a, b, n) \
11821 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11822 #define ADD8(a, b, n) \
11823 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11824 #define SUB8(a, b, n) \
11825 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11828 #include "op_addsub.h"
11830 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11839 /* Unsigned sum of absolute byte differences. */
11840 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11843 sum
= do_usad(a
, b
);
11844 sum
+= do_usad(a
>> 8, b
>> 8);
11845 sum
+= do_usad(a
>> 16, b
>> 16);
11846 sum
+= do_usad(a
>> 24, b
>> 24);
11850 /* For ARMv6 SEL instruction. */
11851 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11866 mask
|= 0xff000000;
11868 return (a
& mask
) | (b
& ~mask
);
11873 * The upper bytes of val (above the number specified by 'bytes') must have
11874 * been zeroed out by the caller.
11876 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11880 stl_le_p(buf
, val
);
11882 /* zlib crc32 converts the accumulator and output to one's complement. */
11883 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11886 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11890 stl_le_p(buf
, val
);
11892 /* Linux crc32c converts the output to one's complement. */
11893 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11897 * Return the exception level to which FP-disabled exceptions should
11898 * be taken, or 0 if FP is enabled.
11900 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11902 #ifndef CONFIG_USER_ONLY
11906 * CPACR and the CPTR registers don't exist before v6, so FP is
11907 * always accessible
11909 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11913 if (arm_feature(env
, ARM_FEATURE_M
)) {
11914 /* CPACR can cause a NOCP UsageFault taken to current security state */
11915 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11919 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11920 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11921 /* FP insns cause a NOCP UsageFault taken to Secure */
11929 hcr_el2
= arm_hcr_el2_eff(env
);
11932 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11933 * 0, 2 : trap EL0 and EL1/PL1 accesses
11934 * 1 : trap only EL0 accesses
11935 * 3 : trap no accesses
11936 * This register is ignored if E2H+TGE are both set.
11938 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11939 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
11949 /* Trap from Secure PL0 or PL1 to Secure PL1. */
11950 if (!arm_el_is_aa64(env
, 3)
11951 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
11962 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11963 * to control non-secure access to the FPU. It doesn't have any
11964 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11966 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11967 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11968 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11969 /* FP insns act as UNDEF */
11970 return cur_el
== 2 ? 2 : 1;
11975 * CPTR_EL2 is present in v7VE or v8, and changes format
11976 * with HCR_EL2.E2H (regardless of TGE).
11979 if (hcr_el2
& HCR_E2H
) {
11980 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
11982 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
11990 } else if (arm_is_el2_enabled(env
)) {
11991 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
11997 /* CPTR_EL3 : present in v8 */
11998 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
11999 /* Trap all FP ops to EL3 */
12006 /* Return the exception level we're running at if this is our mmu_idx */
12007 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12009 if (mmu_idx
& ARM_MMU_IDX_M
) {
12010 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12014 case ARMMMUIdx_E10_0
:
12015 case ARMMMUIdx_E20_0
:
12017 case ARMMMUIdx_E10_1
:
12018 case ARMMMUIdx_E10_1_PAN
:
12021 case ARMMMUIdx_E20_2
:
12022 case ARMMMUIdx_E20_2_PAN
:
12027 g_assert_not_reached();
12032 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12034 g_assert_not_reached();
12038 static bool arm_pan_enabled(CPUARMState
*env
)
12041 return env
->pstate
& PSTATE_PAN
;
12043 return env
->uncached_cpsr
& CPSR_PAN
;
12047 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12052 if (arm_feature(env
, ARM_FEATURE_M
)) {
12053 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12056 /* See ARM pseudo-function ELIsInHost. */
12059 hcr
= arm_hcr_el2_eff(env
);
12060 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12061 idx
= ARMMMUIdx_E20_0
;
12063 idx
= ARMMMUIdx_E10_0
;
12067 if (arm_pan_enabled(env
)) {
12068 idx
= ARMMMUIdx_E10_1_PAN
;
12070 idx
= ARMMMUIdx_E10_1
;
12074 /* Note that TGE does not apply at EL2. */
12075 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12076 if (arm_pan_enabled(env
)) {
12077 idx
= ARMMMUIdx_E20_2_PAN
;
12079 idx
= ARMMMUIdx_E20_2
;
12082 idx
= ARMMMUIdx_E2
;
12086 return ARMMMUIdx_E3
;
12088 g_assert_not_reached();
12094 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12096 return arm_mmu_idx_el(env
, arm_current_el(env
));
12099 static bool mve_no_pred(CPUARMState
*env
)
12102 * Return true if there is definitely no predication of MVE
12103 * instructions by VPR or LTPSIZE. (Returning false even if there
12104 * isn't any predication is OK; generated code will just be
12106 * If the CPU does not implement MVE then this TB flag is always 0.
12108 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12109 * logic in gen_update_fp_context() needs to be updated to match.
12111 * We do not include the effect of the ECI bits here -- they are
12112 * tracked in other TB flags. This simplifies the logic for
12113 * "when did we emit code that changes the MVE_NO_PRED TB flag
12114 * and thus need to end the TB?".
12116 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12119 if (env
->v7m
.vpr
) {
12122 if (env
->v7m
.ltpsize
< 4) {
12128 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12129 uint64_t *cs_base
, uint32_t *pflags
)
12131 CPUARMTBFlags flags
;
12133 assert_hflags_rebuild_correctly(env
);
12134 flags
= env
->hflags
;
12136 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12138 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12139 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12142 *pc
= env
->regs
[15];
12144 if (arm_feature(env
, ARM_FEATURE_M
)) {
12145 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12146 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12147 != env
->v7m
.secure
) {
12148 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12151 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12152 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12153 (env
->v7m
.secure
&&
12154 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12156 * ASPEN is set, but FPCA/SFPA indicate that there is no
12157 * active FP context; we must create a new FP context before
12158 * executing any FP insn.
12160 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12163 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12164 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12165 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12168 if (mve_no_pred(env
)) {
12169 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12173 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12174 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12176 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12177 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12179 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12180 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12182 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12183 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12187 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12188 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12192 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12193 * states defined in the ARM ARM for software singlestep:
12194 * SS_ACTIVE PSTATE.SS State
12195 * 0 x Inactive (the TB flag for SS is always 0)
12196 * 1 0 Active-pending
12197 * 1 1 Active-not-pending
12198 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12200 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12201 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12204 *pflags
= flags
.flags
;
12205 *cs_base
= flags
.flags2
;
12208 #ifdef TARGET_AARCH64
12210 * The manual says that when SVE is enabled and VQ is widened the
12211 * implementation is allowed to zero the previously inaccessible
12212 * portion of the registers. The corollary to that is that when
12213 * SVE is enabled and VQ is narrowed we are also allowed to zero
12214 * the now inaccessible portion of the registers.
12216 * The intent of this is that no predicate bit beyond VQ is ever set.
12217 * Which means that some operations on predicate registers themselves
12218 * may operate on full uint64_t or even unrolled across the maximum
12219 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12220 * may well be cheaper than conditionals to restrict the operation
12221 * to the relevant portion of a uint16_t[16].
12223 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12228 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12229 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12231 /* Zap the high bits of the zregs. */
12232 for (i
= 0; i
< 32; i
++) {
12233 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12236 /* Zap the high bits of the pregs and ffr. */
12239 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12241 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12242 for (i
= 0; i
< 17; ++i
) {
12243 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12249 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12254 exc_el
= sme_exception_el(env
, el
);
12256 exc_el
= sve_exception_el(env
, el
);
12259 return 0; /* disabled */
12261 return sve_vqm1_for_el_sm(env
, el
, sm
);
12265 * Notice a change in SVE vector size when changing EL.
12267 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12268 int new_el
, bool el0_a64
)
12270 ARMCPU
*cpu
= env_archcpu(env
);
12271 int old_len
, new_len
;
12272 bool old_a64
, new_a64
, sm
;
12274 /* Nothing to do if no SVE. */
12275 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12279 /* Nothing to do if FP is disabled in either EL. */
12280 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12284 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12285 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12288 * Both AArch64.TakeException and AArch64.ExceptionReturn
12289 * invoke ResetSVEState when taking an exception from, or
12290 * returning to, AArch32 state when PSTATE.SM is enabled.
12292 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12293 if (old_a64
!= new_a64
&& sm
) {
12294 arm_reset_sve_state(env
);
12299 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12300 * at ELx, or not available because the EL is in AArch32 state, then
12301 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12302 * has an effective value of 0".
12304 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12305 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12306 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12307 * we already have the correct register contents when encountering the
12308 * vq0->vq0 transition between EL0->EL1.
12310 old_len
= new_len
= 0;
12312 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12315 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12318 /* When changing vector length, clear inaccessible state. */
12319 if (new_len
< old_len
) {
12320 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12325 #ifndef CONFIG_USER_ONLY
12326 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12328 if (arm_feature(env
, ARM_FEATURE_M
)) {
12329 return arm_secure_to_space(env
->v7m
.secure
);
12333 * If EL3 is not supported then the secure state is implementation
12334 * defined, in which case QEMU defaults to non-secure.
12336 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12337 return ARMSS_NonSecure
;
12340 /* Check for AArch64 EL3 or AArch32 Mon. */
12342 if (extract32(env
->pstate
, 2, 2) == 3) {
12343 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12346 return ARMSS_Secure
;
12350 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12351 return ARMSS_Secure
;
12355 return arm_security_space_below_el3(env
);
12358 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12360 assert(!arm_feature(env
, ARM_FEATURE_M
));
12363 * If EL3 is not supported then the secure state is implementation
12364 * defined, in which case QEMU defaults to non-secure.
12366 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12367 return ARMSS_NonSecure
;
12371 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12372 * Ignoring NSE when !NS retains consistency without having to
12373 * modify other predicates.
12375 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12376 return ARMSS_Secure
;
12377 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12378 return ARMSS_Realm
;
12380 return ARMSS_NonSecure
;
12383 #endif /* !CONFIG_USER_ONLY */