1 #include "qemu/osdep.h"
5 #include "exec/gdbstub.h"
6 #include "exec/helper-proto.h"
7 #include "qemu/host-utils.h"
8 #include "sysemu/arch_init.h"
9 #include "sysemu/sysemu.h"
10 #include "qemu/bitops.h"
11 #include "qemu/crc32c.h"
12 #include "exec/exec-all.h"
13 #include "exec/cpu_ldst.h"
15 #include <zlib.h> /* For crc32 */
16 #include "exec/semihost.h"
17 #include "sysemu/kvm.h"
19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
21 #ifndef CONFIG_USER_ONLY
22 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
23 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
24 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
25 target_ulong
*page_size
, uint32_t *fsr
,
28 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
29 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
30 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
31 target_ulong
*page_size_ptr
, uint32_t *fsr
,
34 /* Security attributes for an address, as returned by v8m_security_lookup. */
35 typedef struct V8M_SAttributes
{
44 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
45 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
46 V8M_SAttributes
*sattrs
);
48 /* Definitions for the PMCCNTR and PMCR registers */
54 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
58 /* VFP data registers are always little-endian. */
59 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
61 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
64 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
65 /* Aliases for Q regs. */
68 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
69 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
73 switch (reg
- nregs
) {
74 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
75 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
76 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
81 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
85 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
87 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
90 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
93 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
94 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
98 switch (reg
- nregs
) {
99 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
100 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
101 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
106 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
110 /* 128 bit FP register */
111 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
112 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
116 stl_p(buf
, vfp_get_fpsr(env
));
120 stl_p(buf
, vfp_get_fpcr(env
));
127 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
131 /* 128 bit FP register */
132 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
133 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
137 vfp_set_fpsr(env
, ldl_p(buf
));
141 vfp_set_fpcr(env
, ldl_p(buf
));
148 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
150 assert(ri
->fieldoffset
);
151 if (cpreg_field_is_64bit(ri
)) {
152 return CPREG_FIELD64(env
, ri
);
154 return CPREG_FIELD32(env
, ri
);
158 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
161 assert(ri
->fieldoffset
);
162 if (cpreg_field_is_64bit(ri
)) {
163 CPREG_FIELD64(env
, ri
) = value
;
165 CPREG_FIELD32(env
, ri
) = value
;
169 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
171 return (char *)env
+ ri
->fieldoffset
;
174 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
176 /* Raw read of a coprocessor register (as needed for migration, etc). */
177 if (ri
->type
& ARM_CP_CONST
) {
178 return ri
->resetvalue
;
179 } else if (ri
->raw_readfn
) {
180 return ri
->raw_readfn(env
, ri
);
181 } else if (ri
->readfn
) {
182 return ri
->readfn(env
, ri
);
184 return raw_read(env
, ri
);
188 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
191 /* Raw write of a coprocessor register (as needed for migration, etc).
192 * Note that constant registers are treated as write-ignored; the
193 * caller should check for success by whether a readback gives the
196 if (ri
->type
& ARM_CP_CONST
) {
198 } else if (ri
->raw_writefn
) {
199 ri
->raw_writefn(env
, ri
, v
);
200 } else if (ri
->writefn
) {
201 ri
->writefn(env
, ri
, v
);
203 raw_write(env
, ri
, v
);
207 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
209 /* Return true if the regdef would cause an assertion if you called
210 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
211 * program bug for it not to have the NO_RAW flag).
212 * NB that returning false here doesn't necessarily mean that calling
213 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
214 * read/write access functions which are safe for raw use" from "has
215 * read/write access functions which have side effects but has forgotten
216 * to provide raw access functions".
217 * The tests here line up with the conditions in read/write_raw_cp_reg()
218 * and assertions in raw_read()/raw_write().
220 if ((ri
->type
& ARM_CP_CONST
) ||
222 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
228 bool write_cpustate_to_list(ARMCPU
*cpu
)
230 /* Write the coprocessor state from cpu->env to the (index,value) list. */
234 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
235 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
236 const ARMCPRegInfo
*ri
;
238 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
243 if (ri
->type
& ARM_CP_NO_RAW
) {
246 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
251 bool write_list_to_cpustate(ARMCPU
*cpu
)
256 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
257 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
258 uint64_t v
= cpu
->cpreg_values
[i
];
259 const ARMCPRegInfo
*ri
;
261 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
266 if (ri
->type
& ARM_CP_NO_RAW
) {
269 /* Write value and confirm it reads back as written
270 * (to catch read-only registers and partially read-only
271 * registers where the incoming migration value doesn't match)
273 write_raw_cp_reg(&cpu
->env
, ri
, v
);
274 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
281 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
283 ARMCPU
*cpu
= opaque
;
285 const ARMCPRegInfo
*ri
;
287 regidx
= *(uint32_t *)key
;
288 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
290 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
291 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
292 /* The value array need not be initialized at this point */
293 cpu
->cpreg_array_len
++;
297 static void count_cpreg(gpointer key
, gpointer opaque
)
299 ARMCPU
*cpu
= opaque
;
301 const ARMCPRegInfo
*ri
;
303 regidx
= *(uint32_t *)key
;
304 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
306 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
307 cpu
->cpreg_array_len
++;
311 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
313 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
314 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
325 void init_cpreg_list(ARMCPU
*cpu
)
327 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
328 * Note that we require cpreg_tuples[] to be sorted by key ID.
333 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
334 keys
= g_list_sort(keys
, cpreg_key_compare
);
336 cpu
->cpreg_array_len
= 0;
338 g_list_foreach(keys
, count_cpreg
, cpu
);
340 arraylen
= cpu
->cpreg_array_len
;
341 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
342 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
343 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
344 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
345 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
346 cpu
->cpreg_array_len
= 0;
348 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
350 assert(cpu
->cpreg_array_len
== arraylen
);
356 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
357 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
359 * access_el3_aa32ns: Used to check AArch32 register views.
360 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
362 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
363 const ARMCPRegInfo
*ri
,
366 bool secure
= arm_is_secure_below_el3(env
);
368 assert(!arm_el_is_aa64(env
, 3));
370 return CP_ACCESS_TRAP_UNCATEGORIZED
;
375 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
376 const ARMCPRegInfo
*ri
,
379 if (!arm_el_is_aa64(env
, 3)) {
380 return access_el3_aa32ns(env
, ri
, isread
);
385 /* Some secure-only AArch32 registers trap to EL3 if used from
386 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
387 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
388 * We assume that the .access field is set to PL1_RW.
390 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
391 const ARMCPRegInfo
*ri
,
394 if (arm_current_el(env
) == 3) {
397 if (arm_is_secure_below_el3(env
)) {
398 return CP_ACCESS_TRAP_EL3
;
400 /* This will be EL1 NS and EL2 NS, which just UNDEF */
401 return CP_ACCESS_TRAP_UNCATEGORIZED
;
404 /* Check for traps to "powerdown debug" registers, which are controlled
407 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
410 int el
= arm_current_el(env
);
412 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDOSA
)
413 && !arm_is_secure_below_el3(env
)) {
414 return CP_ACCESS_TRAP_EL2
;
416 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
417 return CP_ACCESS_TRAP_EL3
;
422 /* Check for traps to "debug ROM" registers, which are controlled
423 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
425 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
428 int el
= arm_current_el(env
);
430 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDRA
)
431 && !arm_is_secure_below_el3(env
)) {
432 return CP_ACCESS_TRAP_EL2
;
434 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
435 return CP_ACCESS_TRAP_EL3
;
440 /* Check for traps to general debug registers, which are controlled
441 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
443 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
446 int el
= arm_current_el(env
);
448 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDA
)
449 && !arm_is_secure_below_el3(env
)) {
450 return CP_ACCESS_TRAP_EL2
;
452 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
453 return CP_ACCESS_TRAP_EL3
;
458 /* Check for traps to performance monitor registers, which are controlled
459 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
461 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
464 int el
= arm_current_el(env
);
466 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
467 && !arm_is_secure_below_el3(env
)) {
468 return CP_ACCESS_TRAP_EL2
;
470 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
471 return CP_ACCESS_TRAP_EL3
;
476 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
478 ARMCPU
*cpu
= arm_env_get_cpu(env
);
480 raw_write(env
, ri
, value
);
481 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
484 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
486 ARMCPU
*cpu
= arm_env_get_cpu(env
);
488 if (raw_read(env
, ri
) != value
) {
489 /* Unlike real hardware the qemu TLB uses virtual addresses,
490 * not modified virtual addresses, so this causes a TLB flush.
493 raw_write(env
, ri
, value
);
497 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
500 ARMCPU
*cpu
= arm_env_get_cpu(env
);
502 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
503 && !extended_addresses_enabled(env
)) {
504 /* For VMSA (when not using the LPAE long descriptor page table
505 * format) this register includes the ASID, so do a TLB flush.
506 * For PMSA it is purely a process ID and no action is needed.
510 raw_write(env
, ri
, value
);
513 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
516 /* Invalidate all (TLBIALL) */
517 ARMCPU
*cpu
= arm_env_get_cpu(env
);
522 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
525 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
526 ARMCPU
*cpu
= arm_env_get_cpu(env
);
528 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
531 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
534 /* Invalidate by ASID (TLBIASID) */
535 ARMCPU
*cpu
= arm_env_get_cpu(env
);
540 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
543 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
544 ARMCPU
*cpu
= arm_env_get_cpu(env
);
546 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
549 /* IS variants of TLB operations must affect all cores */
550 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
553 CPUState
*cs
= ENV_GET_CPU(env
);
555 tlb_flush_all_cpus_synced(cs
);
558 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
561 CPUState
*cs
= ENV_GET_CPU(env
);
563 tlb_flush_all_cpus_synced(cs
);
566 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
569 CPUState
*cs
= ENV_GET_CPU(env
);
571 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
574 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
577 CPUState
*cs
= ENV_GET_CPU(env
);
579 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
582 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
585 CPUState
*cs
= ENV_GET_CPU(env
);
587 tlb_flush_by_mmuidx(cs
,
588 ARMMMUIdxBit_S12NSE1
|
589 ARMMMUIdxBit_S12NSE0
|
593 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
596 CPUState
*cs
= ENV_GET_CPU(env
);
598 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
599 ARMMMUIdxBit_S12NSE1
|
600 ARMMMUIdxBit_S12NSE0
|
604 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 /* Invalidate by IPA. This has to invalidate any structures that
608 * contain only stage 2 translation information, but does not need
609 * to apply to structures that contain combined stage 1 and stage 2
610 * translation information.
611 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
613 CPUState
*cs
= ENV_GET_CPU(env
);
616 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
620 pageaddr
= sextract64(value
<< 12, 0, 40);
622 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
625 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
628 CPUState
*cs
= ENV_GET_CPU(env
);
631 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
635 pageaddr
= sextract64(value
<< 12, 0, 40);
637 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
641 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
644 CPUState
*cs
= ENV_GET_CPU(env
);
646 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
649 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
652 CPUState
*cs
= ENV_GET_CPU(env
);
654 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
657 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
660 CPUState
*cs
= ENV_GET_CPU(env
);
661 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
663 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
666 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
669 CPUState
*cs
= ENV_GET_CPU(env
);
670 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
672 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
676 static const ARMCPRegInfo cp_reginfo
[] = {
677 /* Define the secure and non-secure FCSE identifier CP registers
678 * separately because there is no secure bank in V8 (no _EL3). This allows
679 * the secure register to be properly reset and migrated. There is also no
680 * v8 EL1 version of the register so the non-secure instance stands alone.
682 { .name
= "FCSEIDR(NS)",
683 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
684 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
685 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
686 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
687 { .name
= "FCSEIDR(S)",
688 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
689 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
690 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
691 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
692 /* Define the secure and non-secure context identifier CP registers
693 * separately because there is no secure bank in V8 (no _EL3). This allows
694 * the secure register to be properly reset and migrated. In the
695 * non-secure case, the 32-bit register will have reset and migration
696 * disabled during registration as it is handled by the 64-bit instance.
698 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
699 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
700 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
701 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
702 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
703 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
704 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
705 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
706 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
707 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
711 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
712 /* NB: Some of these registers exist in v8 but with more precise
713 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
715 /* MMU Domain access control / MPU write buffer control */
717 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
718 .access
= PL1_RW
, .resetvalue
= 0,
719 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
720 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
721 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
722 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
723 * For v6 and v5, these mappings are overly broad.
725 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
726 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
727 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
728 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
729 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
730 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
731 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
732 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
733 /* Cache maintenance ops; some of this space may be overridden later. */
734 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
735 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
736 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
740 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
741 /* Not all pre-v6 cores implemented this WFI, so this is slightly
744 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
745 .access
= PL1_W
, .type
= ARM_CP_WFI
},
749 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
750 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
751 * is UNPREDICTABLE; we choose to NOP as most implementations do).
753 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
754 .access
= PL1_W
, .type
= ARM_CP_WFI
},
755 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
756 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
757 * OMAPCP will override this space.
759 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
760 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
762 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
763 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
765 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
766 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
767 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
769 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
770 * implementing it as RAZ means the "debug architecture version" bits
771 * will read as a reserved value, which should cause Linux to not try
772 * to use the debug hardware.
774 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
775 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
776 /* MMU TLB control. Note that the wildcarding means we cover not just
777 * the unified TLB ops but also the dside/iside/inner-shareable variants.
779 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
780 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
781 .type
= ARM_CP_NO_RAW
},
782 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
783 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
784 .type
= ARM_CP_NO_RAW
},
785 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
786 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
787 .type
= ARM_CP_NO_RAW
},
788 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
789 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
790 .type
= ARM_CP_NO_RAW
},
791 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
792 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
793 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
794 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
798 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
803 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
804 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
805 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
806 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
807 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
809 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
810 /* VFP coprocessor: cp10 & cp11 [23:20] */
811 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
813 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
814 /* ASEDIS [31] bit is RAO/WI */
818 /* VFPv3 and upwards with NEON implement 32 double precision
819 * registers (D0-D31).
821 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
822 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
823 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
829 env
->cp15
.cpacr_el1
= value
;
832 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 if (arm_feature(env
, ARM_FEATURE_V8
)) {
836 /* Check if CPACR accesses are to be trapped to EL2 */
837 if (arm_current_el(env
) == 1 &&
838 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
839 return CP_ACCESS_TRAP_EL2
;
840 /* Check if CPACR accesses are to be trapped to EL3 */
841 } else if (arm_current_el(env
) < 3 &&
842 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
843 return CP_ACCESS_TRAP_EL3
;
850 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
853 /* Check if CPTR accesses are set to trap to EL3 */
854 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
855 return CP_ACCESS_TRAP_EL3
;
861 static const ARMCPRegInfo v6_cp_reginfo
[] = {
862 /* prefetch by MVA in v6, NOP in v7 */
863 { .name
= "MVA_prefetch",
864 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
865 .access
= PL1_W
, .type
= ARM_CP_NOP
},
866 /* We need to break the TB after ISB to execute self-modifying code
867 * correctly and also to take any pending interrupts immediately.
868 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
870 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
871 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
872 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
873 .access
= PL0_W
, .type
= ARM_CP_NOP
},
874 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
875 .access
= PL0_W
, .type
= ARM_CP_NOP
},
876 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
878 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
879 offsetof(CPUARMState
, cp15
.ifar_ns
) },
881 /* Watchpoint Fault Address Register : should actually only be present
882 * for 1136, 1176, 11MPCore.
884 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
885 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
886 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
887 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
888 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
889 .resetvalue
= 0, .writefn
= cpacr_write
},
893 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
896 /* Performance monitor registers user accessibility is controlled
897 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
898 * trapping to EL2 or EL3 for other accesses.
900 int el
= arm_current_el(env
);
902 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
903 return CP_ACCESS_TRAP
;
905 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
906 && !arm_is_secure_below_el3(env
)) {
907 return CP_ACCESS_TRAP_EL2
;
909 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
910 return CP_ACCESS_TRAP_EL3
;
916 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
917 const ARMCPRegInfo
*ri
,
920 /* ER: event counter read trap control */
921 if (arm_feature(env
, ARM_FEATURE_V8
)
922 && arm_current_el(env
) == 0
923 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
928 return pmreg_access(env
, ri
, isread
);
931 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
932 const ARMCPRegInfo
*ri
,
935 /* SW: software increment write trap control */
936 if (arm_feature(env
, ARM_FEATURE_V8
)
937 && arm_current_el(env
) == 0
938 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
943 return pmreg_access(env
, ri
, isread
);
946 #ifndef CONFIG_USER_ONLY
948 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
949 const ARMCPRegInfo
*ri
,
952 /* ER: event counter read trap control */
953 if (arm_feature(env
, ARM_FEATURE_V8
)
954 && arm_current_el(env
) == 0
955 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
959 return pmreg_access(env
, ri
, isread
);
962 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
963 const ARMCPRegInfo
*ri
,
966 /* CR: cycle counter read trap control */
967 if (arm_feature(env
, ARM_FEATURE_V8
)
968 && arm_current_el(env
) == 0
969 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
974 return pmreg_access(env
, ri
, isread
);
977 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
979 /* This does not support checking PMCCFILTR_EL0 register */
981 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
988 void pmccntr_sync(CPUARMState
*env
)
992 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
993 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
995 if (env
->cp15
.c9_pmcr
& PMCRD
) {
996 /* Increment once every 64 processor clock cycles */
1000 if (arm_ccnt_enabled(env
)) {
1001 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
1005 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1010 if (value
& PMCRC
) {
1011 /* The counter has been reset */
1012 env
->cp15
.c15_ccnt
= 0;
1015 /* only the DP, X, D and E bits are writable */
1016 env
->cp15
.c9_pmcr
&= ~0x39;
1017 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1022 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1024 uint64_t total_ticks
;
1026 if (!arm_ccnt_enabled(env
)) {
1027 /* Counter is disabled, do not change value */
1028 return env
->cp15
.c15_ccnt
;
1031 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1032 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1034 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1035 /* Increment once every 64 processor clock cycles */
1038 return total_ticks
- env
->cp15
.c15_ccnt
;
1041 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1044 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1045 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1046 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1049 env
->cp15
.c9_pmselr
= value
& 0x1f;
1052 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1055 uint64_t total_ticks
;
1057 if (!arm_ccnt_enabled(env
)) {
1058 /* Counter is disabled, set the absolute value */
1059 env
->cp15
.c15_ccnt
= value
;
1063 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1064 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1066 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1067 /* Increment once every 64 processor clock cycles */
1070 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1073 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1076 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1078 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1081 #else /* CONFIG_USER_ONLY */
1083 void pmccntr_sync(CPUARMState
*env
)
1089 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1093 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
1097 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1101 env
->cp15
.c9_pmcnten
|= value
;
1104 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1108 env
->cp15
.c9_pmcnten
&= ~value
;
1111 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1114 env
->cp15
.c9_pmovsr
&= ~value
;
1117 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1120 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1121 * PMSELR value is equal to or greater than the number of implemented
1122 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1124 if (env
->cp15
.c9_pmselr
== 0x1f) {
1125 pmccfiltr_write(env
, ri
, value
);
1129 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1131 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1132 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1134 if (env
->cp15
.c9_pmselr
== 0x1f) {
1135 return env
->cp15
.pmccfiltr_el0
;
1141 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1144 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1145 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1147 env
->cp15
.c9_pmuserenr
= value
& 1;
1151 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1154 /* We have no event counters so only the C bit can be changed */
1156 env
->cp15
.c9_pminten
|= value
;
1159 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1163 env
->cp15
.c9_pminten
&= ~value
;
1166 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1169 /* Note that even though the AArch64 view of this register has bits
1170 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1171 * architectural requirements for bits which are RES0 only in some
1172 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1173 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1175 raw_write(env
, ri
, value
& ~0x1FULL
);
1178 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1180 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1181 * For bits that vary between AArch32/64, code needs to check the
1182 * current execution mode before directly using the feature bit.
1184 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1186 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1187 valid_mask
&= ~SCR_HCE
;
1189 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1190 * supported if EL2 exists. The bit is UNK/SBZP when
1191 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1192 * when EL2 is unavailable.
1193 * On ARMv8, this bit is always available.
1195 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1196 !arm_feature(env
, ARM_FEATURE_V8
)) {
1197 valid_mask
&= ~SCR_SMD
;
1201 /* Clear all-context RES0 bits. */
1202 value
&= valid_mask
;
1203 raw_write(env
, ri
, value
);
1206 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1208 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1210 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1213 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1214 ri
->secure
& ARM_CP_SECSTATE_S
);
1216 return cpu
->ccsidr
[index
];
1219 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1222 raw_write(env
, ri
, value
& 0xf);
1225 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1227 CPUState
*cs
= ENV_GET_CPU(env
);
1230 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1233 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1236 /* External aborts are not possible in QEMU so A bit is always clear */
1240 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1241 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1242 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1243 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1244 /* Performance monitors are implementation defined in v7,
1245 * but with an ARM recommended set of registers, which we
1246 * follow (although we don't actually implement any counters)
1248 * Performance registers fall into three categories:
1249 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1250 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1251 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1252 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1253 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1255 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1256 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1257 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1258 .writefn
= pmcntenset_write
,
1259 .accessfn
= pmreg_access
,
1260 .raw_writefn
= raw_write
},
1261 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1262 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1263 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1264 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1265 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1266 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1268 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1269 .accessfn
= pmreg_access
,
1270 .writefn
= pmcntenclr_write
,
1271 .type
= ARM_CP_ALIAS
},
1272 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1273 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1274 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1275 .type
= ARM_CP_ALIAS
,
1276 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1277 .writefn
= pmcntenclr_write
},
1278 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1279 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1280 .accessfn
= pmreg_access
,
1281 .writefn
= pmovsr_write
,
1282 .raw_writefn
= raw_write
},
1283 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1284 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1285 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1286 .type
= ARM_CP_ALIAS
,
1287 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1288 .writefn
= pmovsr_write
,
1289 .raw_writefn
= raw_write
},
1290 /* Unimplemented so WI. */
1291 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1292 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
, .type
= ARM_CP_NOP
},
1293 #ifndef CONFIG_USER_ONLY
1294 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1295 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1296 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1297 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1298 .raw_writefn
= raw_write
},
1299 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1300 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1301 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1302 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1303 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1304 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1305 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
1306 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1307 .accessfn
= pmreg_access_ccntr
},
1308 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1309 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1310 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1312 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1314 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1315 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1316 .writefn
= pmccfiltr_write
,
1317 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1319 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1321 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1322 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1323 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1324 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1325 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1326 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1327 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1328 /* Unimplemented, RAZ/WI. */
1329 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1330 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1331 .accessfn
= pmreg_access_xevcntr
},
1332 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1333 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1334 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1336 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1337 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1338 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1339 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1340 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1342 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1343 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1344 .access
= PL1_RW
, .accessfn
= access_tpm
,
1345 .type
= ARM_CP_ALIAS
,
1346 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1348 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1349 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1350 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1351 .access
= PL1_RW
, .accessfn
= access_tpm
,
1353 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1354 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1355 .resetvalue
= 0x0 },
1356 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1357 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1358 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1359 .writefn
= pmintenclr_write
, },
1360 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1361 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1362 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1363 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1364 .writefn
= pmintenclr_write
},
1365 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1366 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1367 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1368 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1369 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1370 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1371 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1372 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1373 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1374 * just RAZ for all cores:
1376 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1377 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1378 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1379 /* Auxiliary fault status registers: these also are IMPDEF, and we
1380 * choose to RAZ/WI for all cores.
1382 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1383 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1384 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1385 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1386 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1387 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1388 /* MAIR can just read-as-written because we don't implement caches
1389 * and so don't need to care about memory attributes.
1391 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1392 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1393 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1395 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1396 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1397 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1399 /* For non-long-descriptor page tables these are PRRR and NMRR;
1400 * regardless they still act as reads-as-written for QEMU.
1402 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1403 * allows them to assign the correct fieldoffset based on the endianness
1404 * handled in the field definitions.
1406 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1407 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1408 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1409 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1410 .resetfn
= arm_cp_reset_ignore
},
1411 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1412 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1413 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1414 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1415 .resetfn
= arm_cp_reset_ignore
},
1416 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1417 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1418 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1419 /* 32 bit ITLB invalidates */
1420 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1421 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1422 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1423 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1424 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1425 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1426 /* 32 bit DTLB invalidates */
1427 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1428 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1429 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1430 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1431 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1432 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1433 /* 32 bit TLB invalidates */
1434 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1435 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1436 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1437 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1438 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1439 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1440 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1441 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1445 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1446 /* 32 bit TLB invalidates, Inner Shareable */
1447 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1448 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1449 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1450 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1451 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1452 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1453 .writefn
= tlbiasid_is_write
},
1454 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1455 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1456 .writefn
= tlbimvaa_is_write
},
1460 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1467 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1470 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1471 return CP_ACCESS_TRAP
;
1473 return CP_ACCESS_OK
;
1476 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1477 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1478 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1480 .writefn
= teecr_write
},
1481 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1482 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1483 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1487 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1488 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1489 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1491 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1492 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1494 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1495 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1496 .resetfn
= arm_cp_reset_ignore
},
1497 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1498 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1499 .access
= PL0_R
|PL1_W
,
1500 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1502 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1503 .access
= PL0_R
|PL1_W
,
1504 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1505 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1506 .resetfn
= arm_cp_reset_ignore
},
1507 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1508 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1510 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1511 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1513 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1514 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1519 #ifndef CONFIG_USER_ONLY
1521 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1524 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1525 * Writable only at the highest implemented exception level.
1527 int el
= arm_current_el(env
);
1531 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1532 return CP_ACCESS_TRAP
;
1536 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1537 arm_is_secure_below_el3(env
)) {
1538 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1539 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1547 if (!isread
&& el
< arm_highest_el(env
)) {
1548 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1551 return CP_ACCESS_OK
;
1554 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1557 unsigned int cur_el
= arm_current_el(env
);
1558 bool secure
= arm_is_secure(env
);
1560 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1562 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1563 return CP_ACCESS_TRAP
;
1566 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1567 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1568 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1569 return CP_ACCESS_TRAP_EL2
;
1571 return CP_ACCESS_OK
;
1574 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1577 unsigned int cur_el
= arm_current_el(env
);
1578 bool secure
= arm_is_secure(env
);
1580 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1581 * EL0[PV]TEN is zero.
1584 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1585 return CP_ACCESS_TRAP
;
1588 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1589 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1590 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1591 return CP_ACCESS_TRAP_EL2
;
1593 return CP_ACCESS_OK
;
1596 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1597 const ARMCPRegInfo
*ri
,
1600 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1603 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1604 const ARMCPRegInfo
*ri
,
1607 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1610 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1613 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1616 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1619 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1622 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1623 const ARMCPRegInfo
*ri
,
1626 /* The AArch64 register view of the secure physical timer is
1627 * always accessible from EL3, and configurably accessible from
1630 switch (arm_current_el(env
)) {
1632 if (!arm_is_secure(env
)) {
1633 return CP_ACCESS_TRAP
;
1635 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1636 return CP_ACCESS_TRAP_EL3
;
1638 return CP_ACCESS_OK
;
1641 return CP_ACCESS_TRAP
;
1643 return CP_ACCESS_OK
;
1645 g_assert_not_reached();
1649 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1651 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1654 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1656 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1659 /* Timer enabled: calculate and set current ISTATUS, irq, and
1660 * reset timer to when ISTATUS next has to change
1662 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1663 cpu
->env
.cp15
.cntvoff_el2
: 0;
1664 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1665 /* Note that this must be unsigned 64 bit arithmetic: */
1666 int istatus
= count
- offset
>= gt
->cval
;
1670 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1672 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1673 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1676 /* Next transition is when count rolls back over to zero */
1677 nexttick
= UINT64_MAX
;
1679 /* Next transition is when we hit cval */
1680 nexttick
= gt
->cval
+ offset
;
1682 /* Note that the desired next expiry time might be beyond the
1683 * signed-64-bit range of a QEMUTimer -- in this case we just
1684 * set the timer for as far in the future as possible. When the
1685 * timer expires we will reset the timer for any remaining period.
1687 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1688 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1690 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1691 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1693 /* Timer disabled: ISTATUS and timer output always clear */
1695 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1696 timer_del(cpu
->gt_timer
[timeridx
]);
1697 trace_arm_gt_recalc_disabled(timeridx
);
1701 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1704 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1706 timer_del(cpu
->gt_timer
[timeridx
]);
1709 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1711 return gt_get_countervalue(env
);
1714 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1716 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1719 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1723 trace_arm_gt_cval_write(timeridx
, value
);
1724 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1725 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1728 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1731 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1733 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1734 (gt_get_countervalue(env
) - offset
));
1737 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1741 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1743 trace_arm_gt_tval_write(timeridx
, value
);
1744 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1745 sextract64(value
, 0, 32);
1746 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1749 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1753 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1754 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1756 trace_arm_gt_ctl_write(timeridx
, value
);
1757 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1758 if ((oldval
^ value
) & 1) {
1759 /* Enable toggled */
1760 gt_recalc_timer(cpu
, timeridx
);
1761 } else if ((oldval
^ value
) & 2) {
1762 /* IMASK toggled: don't need to recalculate,
1763 * just set the interrupt line based on ISTATUS
1765 int irqstate
= (oldval
& 4) && !(value
& 2);
1767 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1768 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1772 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1774 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1777 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1780 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1783 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1785 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1788 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1791 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1794 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1797 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1800 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1802 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1805 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1808 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1811 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1813 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1816 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1819 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1822 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1825 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1828 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1831 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1833 trace_arm_gt_cntvoff_write(value
);
1834 raw_write(env
, ri
, value
);
1835 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1838 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1840 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1843 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1846 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1849 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1851 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1854 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1857 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1860 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1863 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1866 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1868 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1871 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1874 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1877 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1879 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1882 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1885 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1888 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1891 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1894 void arm_gt_ptimer_cb(void *opaque
)
1896 ARMCPU
*cpu
= opaque
;
1898 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1901 void arm_gt_vtimer_cb(void *opaque
)
1903 ARMCPU
*cpu
= opaque
;
1905 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1908 void arm_gt_htimer_cb(void *opaque
)
1910 ARMCPU
*cpu
= opaque
;
1912 gt_recalc_timer(cpu
, GTIMER_HYP
);
1915 void arm_gt_stimer_cb(void *opaque
)
1917 ARMCPU
*cpu
= opaque
;
1919 gt_recalc_timer(cpu
, GTIMER_SEC
);
1922 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1923 /* Note that CNTFRQ is purely reads-as-written for the benefit
1924 * of software; writing it doesn't actually change the timer frequency.
1925 * Our reset value matches the fixed frequency we implement the timer at.
1927 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1928 .type
= ARM_CP_ALIAS
,
1929 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1930 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1932 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1933 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1934 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1935 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1936 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1938 /* overall control: mostly access permissions */
1939 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1940 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1942 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1945 /* per-timer control */
1946 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1947 .secure
= ARM_CP_SECSTATE_NS
,
1948 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1949 .accessfn
= gt_ptimer_access
,
1950 .fieldoffset
= offsetoflow32(CPUARMState
,
1951 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1952 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1954 { .name
= "CNTP_CTL(S)",
1955 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1956 .secure
= ARM_CP_SECSTATE_S
,
1957 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1958 .accessfn
= gt_ptimer_access
,
1959 .fieldoffset
= offsetoflow32(CPUARMState
,
1960 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1961 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1963 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1964 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1965 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1966 .accessfn
= gt_ptimer_access
,
1967 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1969 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1971 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1972 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1973 .accessfn
= gt_vtimer_access
,
1974 .fieldoffset
= offsetoflow32(CPUARMState
,
1975 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1976 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1978 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1979 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1980 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1981 .accessfn
= gt_vtimer_access
,
1982 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1984 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1986 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1987 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1988 .secure
= ARM_CP_SECSTATE_NS
,
1989 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1990 .accessfn
= gt_ptimer_access
,
1991 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1993 { .name
= "CNTP_TVAL(S)",
1994 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1995 .secure
= ARM_CP_SECSTATE_S
,
1996 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1997 .accessfn
= gt_ptimer_access
,
1998 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2000 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2001 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2002 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2003 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2004 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2006 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2007 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2008 .accessfn
= gt_vtimer_access
,
2009 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2011 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2012 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2013 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2014 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2015 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2017 /* The counter itself */
2018 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2019 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2020 .accessfn
= gt_pct_access
,
2021 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2023 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2024 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2025 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2026 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2028 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2029 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2030 .accessfn
= gt_vct_access
,
2031 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2033 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2034 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2035 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2036 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2038 /* Comparison value, indicating when the timer goes off */
2039 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2040 .secure
= ARM_CP_SECSTATE_NS
,
2041 .access
= PL1_RW
| PL0_R
,
2042 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2043 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2044 .accessfn
= gt_ptimer_access
,
2045 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2047 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
2048 .secure
= ARM_CP_SECSTATE_S
,
2049 .access
= PL1_RW
| PL0_R
,
2050 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2051 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2052 .accessfn
= gt_ptimer_access
,
2053 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2055 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2056 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2057 .access
= PL1_RW
| PL0_R
,
2059 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2060 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2061 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2063 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2064 .access
= PL1_RW
| PL0_R
,
2065 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2066 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2067 .accessfn
= gt_vtimer_access
,
2068 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2070 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2071 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2072 .access
= PL1_RW
| PL0_R
,
2074 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2075 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2076 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2078 /* Secure timer -- this is actually restricted to only EL3
2079 * and configurably Secure-EL1 via the accessfn.
2081 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2082 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2083 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2084 .accessfn
= gt_stimer_access
,
2085 .readfn
= gt_sec_tval_read
,
2086 .writefn
= gt_sec_tval_write
,
2087 .resetfn
= gt_sec_timer_reset
,
2089 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2090 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2091 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2092 .accessfn
= gt_stimer_access
,
2093 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2095 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2097 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2098 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2099 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2100 .accessfn
= gt_stimer_access
,
2101 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2102 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2108 /* In user-mode none of the generic timer registers are accessible,
2109 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
2110 * so instead just don't register any of them.
2112 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2118 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2120 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2121 raw_write(env
, ri
, value
);
2122 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2123 raw_write(env
, ri
, value
& 0xfffff6ff);
2125 raw_write(env
, ri
, value
& 0xfffff1ff);
2129 #ifndef CONFIG_USER_ONLY
2130 /* get_phys_addr() isn't present for user-mode-only targets */
2132 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2136 /* The ATS12NSO* operations must trap to EL3 if executed in
2137 * Secure EL1 (which can only happen if EL3 is AArch64).
2138 * They are simply UNDEF if executed from NS EL1.
2139 * They function normally from EL2 or EL3.
2141 if (arm_current_el(env
) == 1) {
2142 if (arm_is_secure_below_el3(env
)) {
2143 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2145 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2148 return CP_ACCESS_OK
;
2151 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2152 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2155 target_ulong page_size
;
2160 MemTxAttrs attrs
= {};
2161 ARMMMUFaultInfo fi
= {};
2163 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
2164 &phys_addr
, &attrs
, &prot
, &page_size
, &fsr
, &fi
);
2165 if (extended_addresses_enabled(env
)) {
2166 /* fsr is a DFSR/IFSR value for the long descriptor
2167 * translation table format, but with WnR always clear.
2168 * Convert it to a 64-bit PAR.
2170 par64
= (1 << 11); /* LPAE bit always set */
2172 par64
|= phys_addr
& ~0xfffULL
;
2173 if (!attrs
.secure
) {
2174 par64
|= (1 << 9); /* NS */
2176 /* We don't set the ATTR or SH fields in the PAR. */
2179 par64
|= (fsr
& 0x3f) << 1; /* FS */
2180 /* Note that S2WLK and FSTAGE are always zero, because we don't
2181 * implement virtualization and therefore there can't be a stage 2
2186 /* fsr is a DFSR/IFSR value for the short descriptor
2187 * translation table format (with WnR always clear).
2188 * Convert it to a 32-bit PAR.
2191 /* We do not set any attribute bits in the PAR */
2192 if (page_size
== (1 << 24)
2193 && arm_feature(env
, ARM_FEATURE_V7
)) {
2194 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2196 par64
= phys_addr
& 0xfffff000;
2198 if (!attrs
.secure
) {
2199 par64
|= (1 << 9); /* NS */
2202 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2203 ((fsr
& 0xf) << 1) | 1;
2209 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2211 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2214 int el
= arm_current_el(env
);
2215 bool secure
= arm_is_secure_below_el3(env
);
2217 switch (ri
->opc2
& 6) {
2219 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2222 mmu_idx
= ARMMMUIdx_S1E3
;
2225 mmu_idx
= ARMMMUIdx_S1NSE1
;
2228 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2231 g_assert_not_reached();
2235 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2238 mmu_idx
= ARMMMUIdx_S1SE0
;
2241 mmu_idx
= ARMMMUIdx_S1NSE0
;
2244 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2247 g_assert_not_reached();
2251 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2252 mmu_idx
= ARMMMUIdx_S12NSE1
;
2255 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2256 mmu_idx
= ARMMMUIdx_S12NSE0
;
2259 g_assert_not_reached();
2262 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2264 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2267 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2270 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2273 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2275 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2278 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2281 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2282 return CP_ACCESS_TRAP
;
2284 return CP_ACCESS_OK
;
2287 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2290 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2292 int secure
= arm_is_secure_below_el3(env
);
2294 switch (ri
->opc2
& 6) {
2297 case 0: /* AT S1E1R, AT S1E1W */
2298 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2300 case 4: /* AT S1E2R, AT S1E2W */
2301 mmu_idx
= ARMMMUIdx_S1E2
;
2303 case 6: /* AT S1E3R, AT S1E3W */
2304 mmu_idx
= ARMMMUIdx_S1E3
;
2307 g_assert_not_reached();
2310 case 2: /* AT S1E0R, AT S1E0W */
2311 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2313 case 4: /* AT S12E1R, AT S12E1W */
2314 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2316 case 6: /* AT S12E0R, AT S12E0W */
2317 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2320 g_assert_not_reached();
2323 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2327 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2328 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2329 .access
= PL1_RW
, .resetvalue
= 0,
2330 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2331 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2332 .writefn
= par_write
},
2333 #ifndef CONFIG_USER_ONLY
2334 /* This underdecoding is safe because the reginfo is NO_RAW. */
2335 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2336 .access
= PL1_W
, .accessfn
= ats_access
,
2337 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2342 /* Return basic MPU access permission bits. */
2343 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2350 for (i
= 0; i
< 16; i
+= 2) {
2351 ret
|= (val
>> i
) & mask
;
2357 /* Pad basic MPU access permission bits to extended format. */
2358 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2365 for (i
= 0; i
< 16; i
+= 2) {
2366 ret
|= (val
& mask
) << i
;
2372 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2375 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2378 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2380 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2383 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2386 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2389 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2391 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2394 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2396 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2402 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2406 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2409 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2410 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2416 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2417 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2421 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2424 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2425 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2427 if (value
>= nrgs
) {
2428 qemu_log_mask(LOG_GUEST_ERROR
,
2429 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2430 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2434 raw_write(env
, ri
, value
);
2437 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2438 /* Reset for all these registers is handled in arm_cpu_reset(),
2439 * because the PMSAv7 is also used by M-profile CPUs, which do
2440 * not register cpregs but still need the state to be reset.
2442 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2443 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2444 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2445 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2446 .resetfn
= arm_cp_reset_ignore
},
2447 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2448 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2449 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2450 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2451 .resetfn
= arm_cp_reset_ignore
},
2452 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2453 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2454 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2455 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2456 .resetfn
= arm_cp_reset_ignore
},
2457 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2459 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
2460 .writefn
= pmsav7_rgnr_write
,
2461 .resetfn
= arm_cp_reset_ignore
},
2465 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2466 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2467 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2468 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2469 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2470 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2471 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2472 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2473 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2474 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2476 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2478 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2480 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2482 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2484 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2485 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2487 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2488 /* Protection region base and size registers */
2489 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2490 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2491 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2492 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2493 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2494 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2495 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2496 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2497 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2498 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2499 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2500 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2501 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2502 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2503 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2504 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2505 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2506 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2507 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2508 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2509 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2510 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2511 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2512 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2516 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2519 TCR
*tcr
= raw_ptr(env
, ri
);
2520 int maskshift
= extract32(value
, 0, 3);
2522 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2523 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2524 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2525 * using Long-desciptor translation table format */
2526 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2527 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2528 /* In an implementation that includes the Security Extensions
2529 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2530 * Short-descriptor translation table format.
2532 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2538 /* Update the masks corresponding to the TCR bank being written
2539 * Note that we always calculate mask and base_mask, but
2540 * they are only used for short-descriptor tables (ie if EAE is 0);
2541 * for long-descriptor tables the TCR fields are used differently
2542 * and the mask and base_mask values are meaningless.
2544 tcr
->raw_tcr
= value
;
2545 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2546 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2549 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2552 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2554 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2555 /* With LPAE the TTBCR could result in a change of ASID
2556 * via the TTBCR.A1 bit, so do a TLB flush.
2558 tlb_flush(CPU(cpu
));
2560 vmsa_ttbcr_raw_write(env
, ri
, value
);
2563 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2565 TCR
*tcr
= raw_ptr(env
, ri
);
2567 /* Reset both the TCR as well as the masks corresponding to the bank of
2568 * the TCR being reset.
2572 tcr
->base_mask
= 0xffffc000u
;
2575 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2578 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2579 TCR
*tcr
= raw_ptr(env
, ri
);
2581 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2582 tlb_flush(CPU(cpu
));
2583 tcr
->raw_tcr
= value
;
2586 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2589 /* 64 bit accesses to the TTBRs can change the ASID and so we
2590 * must flush the TLB.
2592 if (cpreg_field_is_64bit(ri
)) {
2593 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2595 tlb_flush(CPU(cpu
));
2597 raw_write(env
, ri
, value
);
2600 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2603 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2604 CPUState
*cs
= CPU(cpu
);
2606 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2607 if (raw_read(env
, ri
) != value
) {
2608 tlb_flush_by_mmuidx(cs
,
2609 ARMMMUIdxBit_S12NSE1
|
2610 ARMMMUIdxBit_S12NSE0
|
2612 raw_write(env
, ri
, value
);
2616 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2617 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2618 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2619 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2620 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2621 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2622 .access
= PL1_RW
, .resetvalue
= 0,
2623 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2624 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2625 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2626 .access
= PL1_RW
, .resetvalue
= 0,
2627 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2628 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2629 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2630 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2631 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2636 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2637 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2638 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2640 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2641 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2642 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2643 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2644 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2645 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2646 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2647 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2648 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2649 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2650 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2651 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2652 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2653 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2654 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2655 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2656 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2657 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2658 .raw_writefn
= vmsa_ttbcr_raw_write
,
2659 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2660 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2664 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2667 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2668 /* The OS_TYPE bit in this register changes the reported CPUID! */
2669 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2670 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2673 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2676 env
->cp15
.c15_threadid
= value
& 0xffff;
2679 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2682 /* Wait-for-interrupt (deprecated) */
2683 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2686 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2689 /* On OMAP there are registers indicating the max/min index of dcache lines
2690 * containing a dirty line; cache flush operations have to reset these.
2692 env
->cp15
.c15_i_max
= 0x000;
2693 env
->cp15
.c15_i_min
= 0xff0;
2696 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2697 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2698 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2699 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2701 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2702 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2703 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2705 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2706 .writefn
= omap_ticonfig_write
},
2707 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2709 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2710 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2711 .access
= PL1_RW
, .resetvalue
= 0xff0,
2712 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2713 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2715 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2716 .writefn
= omap_threadid_write
},
2717 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2718 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2719 .type
= ARM_CP_NO_RAW
,
2720 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2721 /* TODO: Peripheral port remap register:
2722 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2723 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2726 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2727 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2728 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2729 .writefn
= omap_cachemaint_write
},
2730 { .name
= "C9", .cp
= 15, .crn
= 9,
2731 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2732 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2736 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2739 env
->cp15
.c15_cpar
= value
& 0x3fff;
2742 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2743 { .name
= "XSCALE_CPAR",
2744 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2745 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2746 .writefn
= xscale_cpar_write
, },
2747 { .name
= "XSCALE_AUXCR",
2748 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2749 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2751 /* XScale specific cache-lockdown: since we have no cache we NOP these
2752 * and hope the guest does not really rely on cache behaviour.
2754 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2755 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2756 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2757 { .name
= "XSCALE_UNLOCK_ICACHE",
2758 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2759 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2760 { .name
= "XSCALE_DCACHE_LOCK",
2761 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2762 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2763 { .name
= "XSCALE_UNLOCK_DCACHE",
2764 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2765 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2769 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2770 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2771 * implementation of this implementation-defined space.
2772 * Ideally this should eventually disappear in favour of actually
2773 * implementing the correct behaviour for all cores.
2775 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2776 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2778 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2783 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2784 /* Cache status: RAZ because we have no cache so it's always clean */
2785 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2786 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2791 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2792 /* We never have a a block transfer operation in progress */
2793 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2794 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2796 /* The cache ops themselves: these all NOP for QEMU */
2797 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2798 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2799 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2800 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2801 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2802 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2803 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2804 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2805 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2806 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2807 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2808 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2812 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2813 /* The cache test-and-clean instructions always return (1 << 30)
2814 * to indicate that there are no dirty cache lines.
2816 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2817 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2818 .resetvalue
= (1 << 30) },
2819 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2820 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2821 .resetvalue
= (1 << 30) },
2825 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2826 /* Ignore ReadBuffer accesses */
2827 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2828 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2829 .access
= PL1_RW
, .resetvalue
= 0,
2830 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2834 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2836 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2837 unsigned int cur_el
= arm_current_el(env
);
2838 bool secure
= arm_is_secure(env
);
2840 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2841 return env
->cp15
.vpidr_el2
;
2843 return raw_read(env
, ri
);
2846 static uint64_t mpidr_read_val(CPUARMState
*env
)
2848 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2849 uint64_t mpidr
= cpu
->mp_affinity
;
2851 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2852 mpidr
|= (1U << 31);
2853 /* Cores which are uniprocessor (non-coherent)
2854 * but still implement the MP extensions set
2855 * bit 30. (For instance, Cortex-R5).
2857 if (cpu
->mp_is_up
) {
2858 mpidr
|= (1u << 30);
2864 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2866 unsigned int cur_el
= arm_current_el(env
);
2867 bool secure
= arm_is_secure(env
);
2869 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2870 return env
->cp15
.vmpidr_el2
;
2872 return mpidr_read_val(env
);
2875 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2876 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2877 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2878 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2882 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2884 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2885 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2886 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2888 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2889 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2890 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2892 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2893 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2894 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2895 offsetof(CPUARMState
, cp15
.par_ns
)} },
2896 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2897 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2898 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2899 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2900 .writefn
= vmsa_ttbr_write
, },
2901 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2902 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2903 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2904 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2905 .writefn
= vmsa_ttbr_write
, },
2909 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2911 return vfp_get_fpcr(env
);
2914 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2917 vfp_set_fpcr(env
, value
);
2920 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2922 return vfp_get_fpsr(env
);
2925 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2928 vfp_set_fpsr(env
, value
);
2931 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2934 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2935 return CP_ACCESS_TRAP
;
2937 return CP_ACCESS_OK
;
2940 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2943 env
->daif
= value
& PSTATE_DAIF
;
2946 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2947 const ARMCPRegInfo
*ri
,
2950 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2951 * SCTLR_EL1.UCI is set.
2953 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2954 return CP_ACCESS_TRAP
;
2956 return CP_ACCESS_OK
;
2959 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2960 * Page D4-1736 (DDI0487A.b)
2963 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2966 CPUState
*cs
= ENV_GET_CPU(env
);
2968 if (arm_is_secure_below_el3(env
)) {
2969 tlb_flush_by_mmuidx(cs
,
2970 ARMMMUIdxBit_S1SE1
|
2971 ARMMMUIdxBit_S1SE0
);
2973 tlb_flush_by_mmuidx(cs
,
2974 ARMMMUIdxBit_S12NSE1
|
2975 ARMMMUIdxBit_S12NSE0
);
2979 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2982 CPUState
*cs
= ENV_GET_CPU(env
);
2983 bool sec
= arm_is_secure_below_el3(env
);
2986 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
2987 ARMMMUIdxBit_S1SE1
|
2988 ARMMMUIdxBit_S1SE0
);
2990 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
2991 ARMMMUIdxBit_S12NSE1
|
2992 ARMMMUIdxBit_S12NSE0
);
2996 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2999 /* Note that the 'ALL' scope must invalidate both stage 1 and
3000 * stage 2 translations, whereas most other scopes only invalidate
3001 * stage 1 translations.
3003 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3004 CPUState
*cs
= CPU(cpu
);
3006 if (arm_is_secure_below_el3(env
)) {
3007 tlb_flush_by_mmuidx(cs
,
3008 ARMMMUIdxBit_S1SE1
|
3009 ARMMMUIdxBit_S1SE0
);
3011 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3012 tlb_flush_by_mmuidx(cs
,
3013 ARMMMUIdxBit_S12NSE1
|
3014 ARMMMUIdxBit_S12NSE0
|
3017 tlb_flush_by_mmuidx(cs
,
3018 ARMMMUIdxBit_S12NSE1
|
3019 ARMMMUIdxBit_S12NSE0
);
3024 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3027 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3028 CPUState
*cs
= CPU(cpu
);
3030 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3033 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3036 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3037 CPUState
*cs
= CPU(cpu
);
3039 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3042 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3045 /* Note that the 'ALL' scope must invalidate both stage 1 and
3046 * stage 2 translations, whereas most other scopes only invalidate
3047 * stage 1 translations.
3049 CPUState
*cs
= ENV_GET_CPU(env
);
3050 bool sec
= arm_is_secure_below_el3(env
);
3051 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3054 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3055 ARMMMUIdxBit_S1SE1
|
3056 ARMMMUIdxBit_S1SE0
);
3057 } else if (has_el2
) {
3058 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3059 ARMMMUIdxBit_S12NSE1
|
3060 ARMMMUIdxBit_S12NSE0
|
3063 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3064 ARMMMUIdxBit_S12NSE1
|
3065 ARMMMUIdxBit_S12NSE0
);
3069 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3072 CPUState
*cs
= ENV_GET_CPU(env
);
3074 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3077 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3080 CPUState
*cs
= ENV_GET_CPU(env
);
3082 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3085 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3088 /* Invalidate by VA, EL1&0 (AArch64 version).
3089 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3090 * since we don't support flush-for-specific-ASID-only or
3091 * flush-last-level-only.
3093 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3094 CPUState
*cs
= CPU(cpu
);
3095 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3097 if (arm_is_secure_below_el3(env
)) {
3098 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3099 ARMMMUIdxBit_S1SE1
|
3100 ARMMMUIdxBit_S1SE0
);
3102 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3103 ARMMMUIdxBit_S12NSE1
|
3104 ARMMMUIdxBit_S12NSE0
);
3108 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3111 /* Invalidate by VA, EL2
3112 * Currently handles both VAE2 and VALE2, since we don't support
3113 * flush-last-level-only.
3115 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3116 CPUState
*cs
= CPU(cpu
);
3117 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3119 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3122 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3125 /* Invalidate by VA, EL3
3126 * Currently handles both VAE3 and VALE3, since we don't support
3127 * flush-last-level-only.
3129 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3130 CPUState
*cs
= CPU(cpu
);
3131 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3133 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3136 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3139 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3140 CPUState
*cs
= CPU(cpu
);
3141 bool sec
= arm_is_secure_below_el3(env
);
3142 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3145 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3146 ARMMMUIdxBit_S1SE1
|
3147 ARMMMUIdxBit_S1SE0
);
3149 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3150 ARMMMUIdxBit_S12NSE1
|
3151 ARMMMUIdxBit_S12NSE0
);
3155 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3158 CPUState
*cs
= ENV_GET_CPU(env
);
3159 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3161 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3165 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3168 CPUState
*cs
= ENV_GET_CPU(env
);
3169 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3171 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3175 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3178 /* Invalidate by IPA. This has to invalidate any structures that
3179 * contain only stage 2 translation information, but does not need
3180 * to apply to structures that contain combined stage 1 and stage 2
3181 * translation information.
3182 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3184 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3185 CPUState
*cs
= CPU(cpu
);
3188 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3192 pageaddr
= sextract64(value
<< 12, 0, 48);
3194 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3197 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3200 CPUState
*cs
= ENV_GET_CPU(env
);
3203 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3207 pageaddr
= sextract64(value
<< 12, 0, 48);
3209 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3213 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3216 /* We don't implement EL2, so the only control on DC ZVA is the
3217 * bit in the SCTLR which can prohibit access for EL0.
3219 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3220 return CP_ACCESS_TRAP
;
3222 return CP_ACCESS_OK
;
3225 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3227 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3228 int dzp_bit
= 1 << 4;
3230 /* DZP indicates whether DC ZVA access is allowed */
3231 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3234 return cpu
->dcz_blocksize
| dzp_bit
;
3237 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3240 if (!(env
->pstate
& PSTATE_SP
)) {
3241 /* Access to SP_EL0 is undefined if it's being used as
3242 * the stack pointer.
3244 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3246 return CP_ACCESS_OK
;
3249 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3251 return env
->pstate
& PSTATE_SP
;
3254 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3256 update_spsel(env
, val
);
3259 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3262 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3264 if (raw_read(env
, ri
) == value
) {
3265 /* Skip the TLB flush if nothing actually changed; Linux likes
3266 * to do a lot of pointless SCTLR writes.
3271 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
3272 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3276 raw_write(env
, ri
, value
);
3277 /* ??? Lots of these bits are not implemented. */
3278 /* This may enable/disable the MMU, so do a TLB flush. */
3279 tlb_flush(CPU(cpu
));
3282 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3285 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3286 return CP_ACCESS_TRAP_FP_EL2
;
3288 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3289 return CP_ACCESS_TRAP_FP_EL3
;
3291 return CP_ACCESS_OK
;
3294 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3297 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3300 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3301 /* Minimal set of EL0-visible registers. This will need to be expanded
3302 * significantly for system emulation of AArch64 CPUs.
3304 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3305 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3306 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3307 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3308 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3309 .type
= ARM_CP_NO_RAW
,
3310 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3311 .fieldoffset
= offsetof(CPUARMState
, daif
),
3312 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3313 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3314 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3315 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3316 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3317 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3318 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3319 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3320 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3321 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3322 .readfn
= aa64_dczid_read
},
3323 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3324 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3325 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3326 #ifndef CONFIG_USER_ONLY
3327 /* Avoid overhead of an access check that always passes in user-mode */
3328 .accessfn
= aa64_zva_access
,
3331 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3333 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3334 /* Cache ops: all NOPs since we don't emulate caches */
3335 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3336 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3337 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3338 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3339 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3340 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3341 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3342 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3343 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3344 .accessfn
= aa64_cacheop_access
},
3345 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3346 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3347 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3348 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3349 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3350 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3351 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3352 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3353 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3354 .accessfn
= aa64_cacheop_access
},
3355 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3356 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3357 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3358 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3359 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3360 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3361 .accessfn
= aa64_cacheop_access
},
3362 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3363 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3364 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3365 .accessfn
= aa64_cacheop_access
},
3366 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3367 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3368 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3369 /* TLBI operations */
3370 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3371 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3372 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3373 .writefn
= tlbi_aa64_vmalle1is_write
},
3374 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3375 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3376 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3377 .writefn
= tlbi_aa64_vae1is_write
},
3378 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3379 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3380 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3381 .writefn
= tlbi_aa64_vmalle1is_write
},
3382 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3383 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3384 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3385 .writefn
= tlbi_aa64_vae1is_write
},
3386 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3387 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3388 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3389 .writefn
= tlbi_aa64_vae1is_write
},
3390 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3391 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3392 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3393 .writefn
= tlbi_aa64_vae1is_write
},
3394 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3395 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3396 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3397 .writefn
= tlbi_aa64_vmalle1_write
},
3398 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3399 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3400 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3401 .writefn
= tlbi_aa64_vae1_write
},
3402 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3403 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3404 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3405 .writefn
= tlbi_aa64_vmalle1_write
},
3406 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3407 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3408 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3409 .writefn
= tlbi_aa64_vae1_write
},
3410 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3411 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3412 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3413 .writefn
= tlbi_aa64_vae1_write
},
3414 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3415 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3416 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3417 .writefn
= tlbi_aa64_vae1_write
},
3418 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3419 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3420 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3421 .writefn
= tlbi_aa64_ipas2e1is_write
},
3422 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3423 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3424 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3425 .writefn
= tlbi_aa64_ipas2e1is_write
},
3426 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3427 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3428 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3429 .writefn
= tlbi_aa64_alle1is_write
},
3430 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3431 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3432 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3433 .writefn
= tlbi_aa64_alle1is_write
},
3434 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3435 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3436 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3437 .writefn
= tlbi_aa64_ipas2e1_write
},
3438 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3439 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3440 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3441 .writefn
= tlbi_aa64_ipas2e1_write
},
3442 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3443 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3444 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3445 .writefn
= tlbi_aa64_alle1_write
},
3446 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3447 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3448 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3449 .writefn
= tlbi_aa64_alle1is_write
},
3450 #ifndef CONFIG_USER_ONLY
3451 /* 64 bit address translation operations */
3452 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3453 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3454 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3455 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3456 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3457 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3458 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3459 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3460 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3461 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3462 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3463 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3464 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3465 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3466 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3467 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3468 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3469 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3470 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3471 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3472 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3473 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3474 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3475 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3476 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3477 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3478 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3479 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3480 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3481 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3482 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3483 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3484 .type
= ARM_CP_ALIAS
,
3485 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3486 .access
= PL1_RW
, .resetvalue
= 0,
3487 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3488 .writefn
= par_write
},
3490 /* TLB invalidate last level of translation table walk */
3491 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3492 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3493 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3494 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3495 .writefn
= tlbimvaa_is_write
},
3496 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3497 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3498 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3499 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3500 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3501 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3502 .writefn
= tlbimva_hyp_write
},
3503 { .name
= "TLBIMVALHIS",
3504 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3505 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3506 .writefn
= tlbimva_hyp_is_write
},
3507 { .name
= "TLBIIPAS2",
3508 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3509 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3510 .writefn
= tlbiipas2_write
},
3511 { .name
= "TLBIIPAS2IS",
3512 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3513 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3514 .writefn
= tlbiipas2_is_write
},
3515 { .name
= "TLBIIPAS2L",
3516 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3517 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3518 .writefn
= tlbiipas2_write
},
3519 { .name
= "TLBIIPAS2LIS",
3520 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3521 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3522 .writefn
= tlbiipas2_is_write
},
3523 /* 32 bit cache operations */
3524 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3525 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3526 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3527 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3528 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3529 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3530 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3531 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3532 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3533 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3534 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3535 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3536 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3537 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3538 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3539 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3540 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3541 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3542 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3543 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3544 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3545 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3546 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3547 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3548 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3549 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3550 /* MMU Domain access control / MPU write buffer control */
3551 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3552 .access
= PL1_RW
, .resetvalue
= 0,
3553 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3554 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3555 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3556 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3557 .type
= ARM_CP_ALIAS
,
3558 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3560 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3561 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3562 .type
= ARM_CP_ALIAS
,
3563 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3565 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3566 /* We rely on the access checks not allowing the guest to write to the
3567 * state field when SPSel indicates that it's being used as the stack
3570 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3571 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3572 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3573 .type
= ARM_CP_ALIAS
,
3574 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3575 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3576 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3577 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3578 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3579 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3580 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3581 .type
= ARM_CP_NO_RAW
,
3582 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3583 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3584 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3585 .type
= ARM_CP_ALIAS
,
3586 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3587 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3588 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3589 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3590 .access
= PL2_RW
, .resetvalue
= 0,
3591 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3592 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3593 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3594 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3595 .access
= PL2_RW
, .resetvalue
= 0,
3596 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3597 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3598 .type
= ARM_CP_ALIAS
,
3599 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3601 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3602 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3603 .type
= ARM_CP_ALIAS
,
3604 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3606 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3607 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3608 .type
= ARM_CP_ALIAS
,
3609 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3611 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3612 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3613 .type
= ARM_CP_ALIAS
,
3614 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3616 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3617 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3618 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3620 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3621 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3622 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3623 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3624 .writefn
= sdcr_write
,
3625 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3629 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3630 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3631 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3632 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3634 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3635 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3636 .type
= ARM_CP_NO_RAW
,
3637 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3639 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3640 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3641 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3642 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3643 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3644 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3645 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3647 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3648 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3649 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3650 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3651 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3652 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3654 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3655 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3656 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3658 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3659 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3660 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3662 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3663 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3664 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3666 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3667 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3668 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3669 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3670 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3671 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3672 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3673 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3674 .cp
= 15, .opc1
= 6, .crm
= 2,
3675 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3676 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3677 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3678 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3679 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3680 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3681 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3682 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3683 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3684 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3685 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3686 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3687 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3688 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3689 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3690 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3692 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3693 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3694 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3695 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3696 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3697 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3698 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3699 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3701 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3702 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3703 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3704 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3705 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3707 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3708 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3709 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3710 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3711 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3712 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3713 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3714 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3715 .access
= PL2_RW
, .accessfn
= access_tda
,
3716 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3717 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3718 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3719 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3720 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3721 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3722 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3723 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3727 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3729 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3730 uint64_t valid_mask
= HCR_MASK
;
3732 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3733 valid_mask
&= ~HCR_HCD
;
3734 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
3735 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3736 * However, if we're using the SMC PSCI conduit then QEMU is
3737 * effectively acting like EL3 firmware and so the guest at
3738 * EL2 should retain the ability to prevent EL1 from being
3739 * able to make SMC calls into the ersatz firmware, so in
3740 * that case HCR.TSC should be read/write.
3742 valid_mask
&= ~HCR_TSC
;
3745 /* Clear RES0 bits. */
3746 value
&= valid_mask
;
3748 /* These bits change the MMU setup:
3749 * HCR_VM enables stage 2 translation
3750 * HCR_PTW forbids certain page-table setups
3751 * HCR_DC Disables stage1 and enables stage2 translation
3753 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3754 tlb_flush(CPU(cpu
));
3756 raw_write(env
, ri
, value
);
3759 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3760 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3761 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3762 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3763 .writefn
= hcr_write
},
3764 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3765 .type
= ARM_CP_ALIAS
,
3766 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3768 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3769 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3770 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3771 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3772 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3773 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3774 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3775 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3776 .type
= ARM_CP_ALIAS
,
3777 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3779 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3780 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3781 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3782 .access
= PL2_RW
, .writefn
= vbar_write
,
3783 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3785 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3786 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3787 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3788 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3789 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3790 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3791 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3792 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3793 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3794 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3795 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3797 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3798 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3799 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3800 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3801 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3802 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3803 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3805 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3806 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3807 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3808 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3810 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3811 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3812 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3814 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3815 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3816 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3818 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3819 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3821 /* no .writefn needed as this can't cause an ASID change;
3822 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3824 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3825 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3826 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3827 .type
= ARM_CP_ALIAS
,
3828 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3829 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3830 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3831 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3833 /* no .writefn needed as this can't cause an ASID change;
3834 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3836 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3837 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3838 .cp
= 15, .opc1
= 6, .crm
= 2,
3839 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3840 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3841 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3842 .writefn
= vttbr_write
},
3843 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3844 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3845 .access
= PL2_RW
, .writefn
= vttbr_write
,
3846 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3847 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3848 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3849 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3850 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3851 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3852 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3853 .access
= PL2_RW
, .resetvalue
= 0,
3854 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3855 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3856 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3857 .access
= PL2_RW
, .resetvalue
= 0,
3858 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3859 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3860 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3861 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3862 { .name
= "TLBIALLNSNH",
3863 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3864 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3865 .writefn
= tlbiall_nsnh_write
},
3866 { .name
= "TLBIALLNSNHIS",
3867 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3868 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3869 .writefn
= tlbiall_nsnh_is_write
},
3870 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3871 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3872 .writefn
= tlbiall_hyp_write
},
3873 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3874 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3875 .writefn
= tlbiall_hyp_is_write
},
3876 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3877 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3878 .writefn
= tlbimva_hyp_write
},
3879 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3880 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3881 .writefn
= tlbimva_hyp_is_write
},
3882 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3883 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3884 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3885 .writefn
= tlbi_aa64_alle2_write
},
3886 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3887 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3888 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3889 .writefn
= tlbi_aa64_vae2_write
},
3890 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3891 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3892 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3893 .writefn
= tlbi_aa64_vae2_write
},
3894 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3895 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3896 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3897 .writefn
= tlbi_aa64_alle2is_write
},
3898 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3899 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3900 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3901 .writefn
= tlbi_aa64_vae2is_write
},
3902 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3903 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3904 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3905 .writefn
= tlbi_aa64_vae2is_write
},
3906 #ifndef CONFIG_USER_ONLY
3907 /* Unlike the other EL2-related AT operations, these must
3908 * UNDEF from EL3 if EL2 is not implemented, which is why we
3909 * define them here rather than with the rest of the AT ops.
3911 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3912 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3913 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3914 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3915 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3916 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3917 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3918 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3919 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3920 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3921 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3922 * to behave as if SCR.NS was 1.
3924 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3926 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3927 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3929 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3930 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3931 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3932 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3933 * reset values as IMPDEF. We choose to reset to 3 to comply with
3934 * both ARMv7 and ARMv8.
3936 .access
= PL2_RW
, .resetvalue
= 3,
3937 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3938 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3939 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3940 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3941 .writefn
= gt_cntvoff_write
,
3942 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3943 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3944 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3945 .writefn
= gt_cntvoff_write
,
3946 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3947 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3948 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3949 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3950 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3951 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3952 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3953 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3954 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
3955 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3956 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3957 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3958 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
3959 .resetfn
= gt_hyp_timer_reset
,
3960 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
3961 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3963 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3965 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
3967 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
3969 /* The only field of MDCR_EL2 that has a defined architectural reset value
3970 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3971 * don't impelment any PMU event counters, so using zero as a reset
3972 * value for MDCR_EL2 is okay
3974 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3975 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3976 .access
= PL2_RW
, .resetvalue
= 0,
3977 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
3978 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
3979 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3980 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3981 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3982 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
3983 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3985 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3986 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3987 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3989 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
3993 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3996 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3997 * At Secure EL1 it traps to EL3.
3999 if (arm_current_el(env
) == 3) {
4000 return CP_ACCESS_OK
;
4002 if (arm_is_secure_below_el3(env
)) {
4003 return CP_ACCESS_TRAP_EL3
;
4005 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4007 return CP_ACCESS_OK
;
4009 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4012 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4013 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4014 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4015 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4016 .resetvalue
= 0, .writefn
= scr_write
},
4017 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4018 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4019 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4020 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4021 .writefn
= scr_write
},
4022 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4023 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4024 .access
= PL3_RW
, .resetvalue
= 0,
4025 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4027 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4028 .access
= PL3_RW
, .resetvalue
= 0,
4029 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4030 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4031 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4032 .writefn
= vbar_write
, .resetvalue
= 0,
4033 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4034 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4035 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4036 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4037 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4038 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4039 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4041 /* no .writefn needed as this can't cause an ASID change;
4042 * we must provide a .raw_writefn and .resetfn because we handle
4043 * reset and migration for the AArch32 TTBCR(S), which might be
4044 * using mask and base_mask.
4046 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4047 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4048 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4049 .type
= ARM_CP_ALIAS
,
4050 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4052 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4053 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4054 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4055 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4056 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4057 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4058 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4059 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4060 .type
= ARM_CP_ALIAS
,
4061 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4063 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4064 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4065 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4066 .access
= PL3_RW
, .writefn
= vbar_write
,
4067 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4069 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4070 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4071 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4072 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4073 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4074 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4075 .access
= PL3_RW
, .resetvalue
= 0,
4076 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4077 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4078 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4079 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4081 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4082 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4083 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4085 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4086 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4087 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4089 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4090 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4091 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4092 .writefn
= tlbi_aa64_alle3is_write
},
4093 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4094 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4095 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4096 .writefn
= tlbi_aa64_vae3is_write
},
4097 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4098 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4099 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4100 .writefn
= tlbi_aa64_vae3is_write
},
4101 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4102 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4103 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4104 .writefn
= tlbi_aa64_alle3_write
},
4105 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4106 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4107 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4108 .writefn
= tlbi_aa64_vae3_write
},
4109 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4110 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4111 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4112 .writefn
= tlbi_aa64_vae3_write
},
4116 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4119 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4120 * but the AArch32 CTR has its own reginfo struct)
4122 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4123 return CP_ACCESS_TRAP
;
4125 return CP_ACCESS_OK
;
4128 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4131 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4132 * read via a bit in OSLSR_EL1.
4136 if (ri
->state
== ARM_CP_STATE_AA32
) {
4137 oslock
= (value
== 0xC5ACCE55);
4142 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4145 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4146 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4147 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4148 * unlike DBGDRAR it is never accessible from EL0.
4149 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4152 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4153 .access
= PL0_R
, .accessfn
= access_tdra
,
4154 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4155 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4156 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4157 .access
= PL1_R
, .accessfn
= access_tdra
,
4158 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4159 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4160 .access
= PL0_R
, .accessfn
= access_tdra
,
4161 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4162 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4163 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4164 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4165 .access
= PL1_RW
, .accessfn
= access_tda
,
4166 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4168 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4169 * We don't implement the configurable EL0 access.
4171 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4172 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4173 .type
= ARM_CP_ALIAS
,
4174 .access
= PL1_R
, .accessfn
= access_tda
,
4175 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4176 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4177 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4178 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4179 .accessfn
= access_tdosa
,
4180 .writefn
= oslar_write
},
4181 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4182 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4183 .access
= PL1_R
, .resetvalue
= 10,
4184 .accessfn
= access_tdosa
,
4185 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4186 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4187 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4188 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4189 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4190 .type
= ARM_CP_NOP
},
4191 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4192 * implement vector catch debug events yet.
4195 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4196 .access
= PL1_RW
, .accessfn
= access_tda
,
4197 .type
= ARM_CP_NOP
},
4198 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4199 * to save and restore a 32-bit guest's DBGVCR)
4201 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4202 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4203 .access
= PL2_RW
, .accessfn
= access_tda
,
4204 .type
= ARM_CP_NOP
},
4205 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4206 * Channel but Linux may try to access this register. The 32-bit
4207 * alias is DBGDCCINT.
4209 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4210 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4211 .access
= PL1_RW
, .accessfn
= access_tda
,
4212 .type
= ARM_CP_NOP
},
4216 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4217 /* 64 bit access versions of the (dummy) debug registers */
4218 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4219 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4220 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4221 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4225 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4227 CPUARMState
*env
= &cpu
->env
;
4229 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4230 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4232 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4234 if (env
->cpu_watchpoint
[n
]) {
4235 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4236 env
->cpu_watchpoint
[n
] = NULL
;
4239 if (!extract64(wcr
, 0, 1)) {
4240 /* E bit clear : watchpoint disabled */
4244 switch (extract64(wcr
, 3, 2)) {
4246 /* LSC 00 is reserved and must behave as if the wp is disabled */
4249 flags
|= BP_MEM_READ
;
4252 flags
|= BP_MEM_WRITE
;
4255 flags
|= BP_MEM_ACCESS
;
4259 /* Attempts to use both MASK and BAS fields simultaneously are
4260 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4261 * thus generating a watchpoint for every byte in the masked region.
4263 mask
= extract64(wcr
, 24, 4);
4264 if (mask
== 1 || mask
== 2) {
4265 /* Reserved values of MASK; we must act as if the mask value was
4266 * some non-reserved value, or as if the watchpoint were disabled.
4267 * We choose the latter.
4271 /* Watchpoint covers an aligned area up to 2GB in size */
4273 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4274 * whether the watchpoint fires when the unmasked bits match; we opt
4275 * to generate the exceptions.
4279 /* Watchpoint covers bytes defined by the byte address select bits */
4280 int bas
= extract64(wcr
, 5, 8);
4284 /* This must act as if the watchpoint is disabled */
4288 if (extract64(wvr
, 2, 1)) {
4289 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4290 * ignored, and BAS[3:0] define which bytes to watch.
4294 /* The BAS bits are supposed to be programmed to indicate a contiguous
4295 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4296 * we fire for each byte in the word/doubleword addressed by the WVR.
4297 * We choose to ignore any non-zero bits after the first range of 1s.
4299 basstart
= ctz32(bas
);
4300 len
= cto32(bas
>> basstart
);
4304 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4305 &env
->cpu_watchpoint
[n
]);
4308 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4311 CPUARMState
*env
= &cpu
->env
;
4313 /* Completely clear out existing QEMU watchpoints and our array, to
4314 * avoid possible stale entries following migration load.
4316 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4317 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4319 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4320 hw_watchpoint_update(cpu
, i
);
4324 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4327 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4330 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4331 * register reads and behaves as if values written are sign extended.
4332 * Bits [1:0] are RES0.
4334 value
= sextract64(value
, 0, 49) & ~3ULL;
4336 raw_write(env
, ri
, value
);
4337 hw_watchpoint_update(cpu
, i
);
4340 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4343 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4346 raw_write(env
, ri
, value
);
4347 hw_watchpoint_update(cpu
, i
);
4350 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4352 CPUARMState
*env
= &cpu
->env
;
4353 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4354 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4359 if (env
->cpu_breakpoint
[n
]) {
4360 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4361 env
->cpu_breakpoint
[n
] = NULL
;
4364 if (!extract64(bcr
, 0, 1)) {
4365 /* E bit clear : watchpoint disabled */
4369 bt
= extract64(bcr
, 20, 4);
4372 case 4: /* unlinked address mismatch (reserved if AArch64) */
4373 case 5: /* linked address mismatch (reserved if AArch64) */
4374 qemu_log_mask(LOG_UNIMP
,
4375 "arm: address mismatch breakpoint types not implemented");
4377 case 0: /* unlinked address match */
4378 case 1: /* linked address match */
4380 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4381 * we behave as if the register was sign extended. Bits [1:0] are
4382 * RES0. The BAS field is used to allow setting breakpoints on 16
4383 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4384 * a bp will fire if the addresses covered by the bp and the addresses
4385 * covered by the insn overlap but the insn doesn't start at the
4386 * start of the bp address range. We choose to require the insn and
4387 * the bp to have the same address. The constraints on writing to
4388 * BAS enforced in dbgbcr_write mean we have only four cases:
4389 * 0b0000 => no breakpoint
4390 * 0b0011 => breakpoint on addr
4391 * 0b1100 => breakpoint on addr + 2
4392 * 0b1111 => breakpoint on addr
4393 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4395 int bas
= extract64(bcr
, 5, 4);
4396 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4405 case 2: /* unlinked context ID match */
4406 case 8: /* unlinked VMID match (reserved if no EL2) */
4407 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4408 qemu_log_mask(LOG_UNIMP
,
4409 "arm: unlinked context breakpoint types not implemented");
4411 case 9: /* linked VMID match (reserved if no EL2) */
4412 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4413 case 3: /* linked context ID match */
4415 /* We must generate no events for Linked context matches (unless
4416 * they are linked to by some other bp/wp, which is handled in
4417 * updates for the linking bp/wp). We choose to also generate no events
4418 * for reserved values.
4423 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4426 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4429 CPUARMState
*env
= &cpu
->env
;
4431 /* Completely clear out existing QEMU breakpoints and our array, to
4432 * avoid possible stale entries following migration load.
4434 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4435 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4437 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4438 hw_breakpoint_update(cpu
, i
);
4442 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4445 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4448 raw_write(env
, ri
, value
);
4449 hw_breakpoint_update(cpu
, i
);
4452 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4455 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4458 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4461 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4462 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4464 raw_write(env
, ri
, value
);
4465 hw_breakpoint_update(cpu
, i
);
4468 static void define_debug_regs(ARMCPU
*cpu
)
4470 /* Define v7 and v8 architectural debug registers.
4471 * These are just dummy implementations for now.
4474 int wrps
, brps
, ctx_cmps
;
4475 ARMCPRegInfo dbgdidr
= {
4476 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4477 .access
= PL0_R
, .accessfn
= access_tda
,
4478 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4481 /* Note that all these register fields hold "number of Xs minus 1". */
4482 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4483 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4484 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4486 assert(ctx_cmps
<= brps
);
4488 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4489 * of the debug registers such as number of breakpoints;
4490 * check that if they both exist then they agree.
4492 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4493 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4494 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4495 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4498 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4499 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4501 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4502 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4505 for (i
= 0; i
< brps
+ 1; i
++) {
4506 ARMCPRegInfo dbgregs
[] = {
4507 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4508 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4509 .access
= PL1_RW
, .accessfn
= access_tda
,
4510 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4511 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4513 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4514 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4515 .access
= PL1_RW
, .accessfn
= access_tda
,
4516 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4517 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4521 define_arm_cp_regs(cpu
, dbgregs
);
4524 for (i
= 0; i
< wrps
+ 1; i
++) {
4525 ARMCPRegInfo dbgregs
[] = {
4526 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4527 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4528 .access
= PL1_RW
, .accessfn
= access_tda
,
4529 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4530 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4532 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4533 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4534 .access
= PL1_RW
, .accessfn
= access_tda
,
4535 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4536 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4540 define_arm_cp_regs(cpu
, dbgregs
);
4544 void register_cp_regs_for_features(ARMCPU
*cpu
)
4546 /* Register all the coprocessor registers based on feature bits */
4547 CPUARMState
*env
= &cpu
->env
;
4548 if (arm_feature(env
, ARM_FEATURE_M
)) {
4549 /* M profile has no coprocessor registers */
4553 define_arm_cp_regs(cpu
, cp_reginfo
);
4554 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4555 /* Must go early as it is full of wildcards that may be
4556 * overridden by later definitions.
4558 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4561 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4562 /* The ID registers all have impdef reset values */
4563 ARMCPRegInfo v6_idregs
[] = {
4564 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4565 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4566 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4567 .resetvalue
= cpu
->id_pfr0
},
4568 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4569 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4570 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4571 .resetvalue
= cpu
->id_pfr1
},
4572 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4573 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4574 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4575 .resetvalue
= cpu
->id_dfr0
},
4576 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4577 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4578 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4579 .resetvalue
= cpu
->id_afr0
},
4580 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4581 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4582 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4583 .resetvalue
= cpu
->id_mmfr0
},
4584 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4585 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4586 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4587 .resetvalue
= cpu
->id_mmfr1
},
4588 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4589 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4590 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4591 .resetvalue
= cpu
->id_mmfr2
},
4592 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4593 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4594 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4595 .resetvalue
= cpu
->id_mmfr3
},
4596 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4597 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4598 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4599 .resetvalue
= cpu
->id_isar0
},
4600 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4601 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4602 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4603 .resetvalue
= cpu
->id_isar1
},
4604 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4605 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4606 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4607 .resetvalue
= cpu
->id_isar2
},
4608 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4609 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4610 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4611 .resetvalue
= cpu
->id_isar3
},
4612 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4613 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4614 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4615 .resetvalue
= cpu
->id_isar4
},
4616 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4617 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4618 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4619 .resetvalue
= cpu
->id_isar5
},
4620 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4621 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4622 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4623 .resetvalue
= cpu
->id_mmfr4
},
4624 /* 7 is as yet unallocated and must RAZ */
4625 { .name
= "ID_ISAR7_RESERVED", .state
= ARM_CP_STATE_BOTH
,
4626 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4627 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4631 define_arm_cp_regs(cpu
, v6_idregs
);
4632 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4634 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4636 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4637 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4639 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4640 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
4641 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4643 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4644 /* v7 performance monitor control register: same implementor
4645 * field as main ID register, and we implement only the cycle
4648 #ifndef CONFIG_USER_ONLY
4649 ARMCPRegInfo pmcr
= {
4650 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4652 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4653 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4654 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4655 .raw_writefn
= raw_write
,
4657 ARMCPRegInfo pmcr64
= {
4658 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4659 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4660 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4662 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4663 .resetvalue
= cpu
->midr
& 0xff000000,
4664 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4666 define_one_arm_cp_reg(cpu
, &pmcr
);
4667 define_one_arm_cp_reg(cpu
, &pmcr64
);
4669 ARMCPRegInfo clidr
= {
4670 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4671 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4672 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4674 define_one_arm_cp_reg(cpu
, &clidr
);
4675 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4676 define_debug_regs(cpu
);
4678 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4680 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4681 /* AArch64 ID registers, which all have impdef reset values.
4682 * Note that within the ID register ranges the unused slots
4683 * must all RAZ, not UNDEF; future architecture versions may
4684 * define new registers here.
4686 ARMCPRegInfo v8_idregs
[] = {
4687 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4688 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4689 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4690 .resetvalue
= cpu
->id_aa64pfr0
},
4691 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4692 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4693 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4694 .resetvalue
= cpu
->id_aa64pfr1
},
4695 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4696 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
4697 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4699 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4700 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
4701 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4703 { .name
= "ID_AA64PFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4704 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
4705 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4707 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4708 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
4709 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4711 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4712 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
4713 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4715 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4716 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
4717 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4719 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4720 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4721 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4722 .resetvalue
= cpu
->id_aa64dfr0
},
4723 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4724 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4725 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4726 .resetvalue
= cpu
->id_aa64dfr1
},
4727 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4728 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
4729 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4731 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4732 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
4733 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4735 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4736 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4737 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4738 .resetvalue
= cpu
->id_aa64afr0
},
4739 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4740 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4741 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4742 .resetvalue
= cpu
->id_aa64afr1
},
4743 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4744 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
4745 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4747 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4748 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
4749 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4751 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4752 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4753 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4754 .resetvalue
= cpu
->id_aa64isar0
},
4755 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4756 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4757 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4758 .resetvalue
= cpu
->id_aa64isar1
},
4759 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4760 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
4761 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4763 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4764 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
4765 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4767 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4768 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
4769 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4771 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4772 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
4773 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4775 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4776 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
4777 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4779 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4780 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
4781 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4783 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4784 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4785 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4786 .resetvalue
= cpu
->id_aa64mmfr0
},
4787 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4788 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4789 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4790 .resetvalue
= cpu
->id_aa64mmfr1
},
4791 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4792 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
4793 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4795 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4796 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
4797 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4799 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4800 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
4801 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4803 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4804 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
4805 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4807 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4808 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
4809 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4811 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4812 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
4813 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4815 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4816 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
4817 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4818 .resetvalue
= cpu
->mvfr0
},
4819 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4820 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
4821 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4822 .resetvalue
= cpu
->mvfr1
},
4823 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
4824 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
4825 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4826 .resetvalue
= cpu
->mvfr2
},
4827 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4828 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
4829 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4831 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4832 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
4833 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4835 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4836 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
4837 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4839 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4840 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
4841 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4843 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4844 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
4845 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4847 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
4848 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
4849 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4850 .resetvalue
= cpu
->pmceid0
},
4851 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
4852 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
4853 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4854 .resetvalue
= cpu
->pmceid0
},
4855 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
4856 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
4857 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4858 .resetvalue
= cpu
->pmceid1
},
4859 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
4860 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
4861 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4862 .resetvalue
= cpu
->pmceid1
},
4865 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4866 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
4867 !arm_feature(env
, ARM_FEATURE_EL2
)) {
4868 ARMCPRegInfo rvbar
= {
4869 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4870 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4871 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
4873 define_one_arm_cp_reg(cpu
, &rvbar
);
4875 define_arm_cp_regs(cpu
, v8_idregs
);
4876 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
4878 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4879 uint64_t vmpidr_def
= mpidr_read_val(env
);
4880 ARMCPRegInfo vpidr_regs
[] = {
4881 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
4882 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4883 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4884 .resetvalue
= cpu
->midr
,
4885 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4886 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4888 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
4889 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4890 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
4891 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4892 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4893 .resetvalue
= vmpidr_def
,
4894 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4895 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4896 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4898 .resetvalue
= vmpidr_def
,
4899 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4902 define_arm_cp_regs(cpu
, vpidr_regs
);
4903 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
4904 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4905 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
4906 ARMCPRegInfo rvbar
= {
4907 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
4908 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
4909 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
4911 define_one_arm_cp_reg(cpu
, &rvbar
);
4914 /* If EL2 is missing but higher ELs are enabled, we need to
4915 * register the no_el2 reginfos.
4917 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4918 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4919 * of MIDR_EL1 and MPIDR_EL1.
4921 ARMCPRegInfo vpidr_regs
[] = {
4922 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4923 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4924 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4925 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
4926 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4927 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4928 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4929 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4930 .type
= ARM_CP_NO_RAW
,
4931 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
4934 define_arm_cp_regs(cpu
, vpidr_regs
);
4935 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
4938 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4939 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
4940 ARMCPRegInfo el3_regs
[] = {
4941 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4942 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
4943 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
4944 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
4945 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
4947 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4948 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
4949 .resetvalue
= cpu
->reset_sctlr
},
4953 define_arm_cp_regs(cpu
, el3_regs
);
4955 /* The behaviour of NSACR is sufficiently various that we don't
4956 * try to describe it in a single reginfo:
4957 * if EL3 is 64 bit, then trap to EL3 from S EL1,
4958 * reads as constant 0xc00 from NS EL1 and NS EL2
4959 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4960 * if v7 without EL3, register doesn't exist
4961 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4963 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4964 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4965 ARMCPRegInfo nsacr
= {
4966 .name
= "NSACR", .type
= ARM_CP_CONST
,
4967 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4968 .access
= PL1_RW
, .accessfn
= nsacr_access
,
4971 define_one_arm_cp_reg(cpu
, &nsacr
);
4973 ARMCPRegInfo nsacr
= {
4975 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4976 .access
= PL3_RW
| PL1_R
,
4978 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
4980 define_one_arm_cp_reg(cpu
, &nsacr
);
4983 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4984 ARMCPRegInfo nsacr
= {
4985 .name
= "NSACR", .type
= ARM_CP_CONST
,
4986 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4990 define_one_arm_cp_reg(cpu
, &nsacr
);
4994 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
4995 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4996 /* PMSAv6 not implemented */
4997 assert(arm_feature(env
, ARM_FEATURE_V7
));
4998 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4999 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
5001 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
5004 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5005 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
5007 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5008 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
5010 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
5011 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
5013 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
5014 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
5016 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
5017 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
5019 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
5020 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
5022 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
5023 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
5025 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
5026 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
5028 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5029 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
5031 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5032 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
5034 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
5035 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
5037 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
5038 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
5040 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5041 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5042 * be read-only (ie write causes UNDEF exception).
5045 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
5046 /* Pre-v8 MIDR space.
5047 * Note that the MIDR isn't a simple constant register because
5048 * of the TI925 behaviour where writes to another register can
5049 * cause the MIDR value to change.
5051 * Unimplemented registers in the c15 0 0 0 space default to
5052 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5053 * and friends override accordingly.
5056 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
5057 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5058 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5059 .readfn
= midr_read
,
5060 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5061 .type
= ARM_CP_OVERRIDE
},
5062 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5064 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5065 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5067 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5068 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5070 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5071 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5073 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5074 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5076 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5077 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5080 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5081 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5082 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5083 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5085 .readfn
= midr_read
},
5086 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5087 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5088 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5089 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5090 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5091 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5092 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5093 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5094 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5095 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5098 ARMCPRegInfo id_cp_reginfo
[] = {
5099 /* These are common to v8 and pre-v8 */
5101 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5102 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5103 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5104 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5105 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5106 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5107 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5109 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5110 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5113 /* TLBTR is specific to VMSA */
5114 ARMCPRegInfo id_tlbtr_reginfo
= {
5116 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5117 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5119 /* MPUIR is specific to PMSA V6+ */
5120 ARMCPRegInfo id_mpuir_reginfo
= {
5122 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5123 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5124 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5126 ARMCPRegInfo crn0_wi_reginfo
= {
5127 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5128 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5129 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5131 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5132 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5134 /* Register the blanket "writes ignored" value first to cover the
5135 * whole space. Then update the specific ID registers to allow write
5136 * access, so that they ignore writes rather than causing them to
5139 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5140 for (r
= id_pre_v8_midr_cp_reginfo
;
5141 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5144 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5147 id_tlbtr_reginfo
.access
= PL1_RW
;
5148 id_tlbtr_reginfo
.access
= PL1_RW
;
5150 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5151 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5153 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5155 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5156 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
5157 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5158 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5159 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5163 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5164 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5167 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5168 ARMCPRegInfo auxcr_reginfo
[] = {
5169 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5170 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5171 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5172 .resetvalue
= cpu
->reset_auxcr
},
5173 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5174 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5175 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5177 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5178 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5179 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5183 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5186 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5187 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5188 /* 32 bit view is [31:18] 0...0 [43:32]. */
5189 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5190 | extract64(cpu
->reset_cbar
, 32, 12);
5191 ARMCPRegInfo cbar_reginfo
[] = {
5193 .type
= ARM_CP_CONST
,
5194 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5195 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5196 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5197 .type
= ARM_CP_CONST
,
5198 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5199 .access
= PL1_R
, .resetvalue
= cbar32
},
5202 /* We don't implement a r/w 64 bit CBAR currently */
5203 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5204 define_arm_cp_regs(cpu
, cbar_reginfo
);
5206 ARMCPRegInfo cbar
= {
5208 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5209 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5210 .fieldoffset
= offsetof(CPUARMState
,
5211 cp15
.c15_config_base_address
)
5213 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5214 cbar
.access
= PL1_R
;
5215 cbar
.fieldoffset
= 0;
5216 cbar
.type
= ARM_CP_CONST
;
5218 define_one_arm_cp_reg(cpu
, &cbar
);
5222 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5223 ARMCPRegInfo vbar_cp_reginfo
[] = {
5224 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5225 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5226 .access
= PL1_RW
, .writefn
= vbar_write
,
5227 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5228 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5232 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5235 /* Generic registers whose values depend on the implementation */
5237 ARMCPRegInfo sctlr
= {
5238 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5239 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5241 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5242 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5243 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5244 .raw_writefn
= raw_write
,
5246 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5247 /* Normally we would always end the TB on an SCTLR write, but Linux
5248 * arch/arm/mach-pxa/sleep.S expects two instructions following
5249 * an MMU enable to execute from cache. Imitate this behaviour.
5251 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5253 define_one_arm_cp_reg(cpu
, &sctlr
);
5257 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5259 CPUState
*cs
= CPU(cpu
);
5260 CPUARMState
*env
= &cpu
->env
;
5262 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5263 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5264 aarch64_fpu_gdb_set_reg
,
5265 34, "aarch64-fpu.xml", 0);
5266 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5267 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5268 51, "arm-neon.xml", 0);
5269 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5270 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5271 35, "arm-vfp3.xml", 0);
5272 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5273 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5274 19, "arm-vfp.xml", 0);
5278 /* Sort alphabetically by type name, except for "any". */
5279 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5281 ObjectClass
*class_a
= (ObjectClass
*)a
;
5282 ObjectClass
*class_b
= (ObjectClass
*)b
;
5283 const char *name_a
, *name_b
;
5285 name_a
= object_class_get_name(class_a
);
5286 name_b
= object_class_get_name(class_b
);
5287 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5289 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5292 return strcmp(name_a
, name_b
);
5296 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5298 ObjectClass
*oc
= data
;
5299 CPUListState
*s
= user_data
;
5300 const char *typename
;
5303 typename
= object_class_get_name(oc
);
5304 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5305 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5310 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5314 .cpu_fprintf
= cpu_fprintf
,
5318 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5319 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5320 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5321 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5324 /* The 'host' CPU type is dynamically registered only if KVM is
5325 * enabled, so we have to special-case it here:
5327 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
5331 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5333 ObjectClass
*oc
= data
;
5334 CpuDefinitionInfoList
**cpu_list
= user_data
;
5335 CpuDefinitionInfoList
*entry
;
5336 CpuDefinitionInfo
*info
;
5337 const char *typename
;
5339 typename
= object_class_get_name(oc
);
5340 info
= g_malloc0(sizeof(*info
));
5341 info
->name
= g_strndup(typename
,
5342 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5343 info
->q_typename
= g_strdup(typename
);
5345 entry
= g_malloc0(sizeof(*entry
));
5346 entry
->value
= info
;
5347 entry
->next
= *cpu_list
;
5351 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5353 CpuDefinitionInfoList
*cpu_list
= NULL
;
5356 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5357 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5363 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5364 void *opaque
, int state
, int secstate
,
5365 int crm
, int opc1
, int opc2
)
5367 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5368 * add a single reginfo struct to the hash table.
5370 uint32_t *key
= g_new(uint32_t, 1);
5371 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5372 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5373 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5375 /* Reset the secure state to the specific incoming state. This is
5376 * necessary as the register may have been defined with both states.
5378 r2
->secure
= secstate
;
5380 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5381 /* Register is banked (using both entries in array).
5382 * Overwriting fieldoffset as the array is only used to define
5383 * banked registers but later only fieldoffset is used.
5385 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5388 if (state
== ARM_CP_STATE_AA32
) {
5389 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5390 /* If the register is banked then we don't need to migrate or
5391 * reset the 32-bit instance in certain cases:
5393 * 1) If the register has both 32-bit and 64-bit instances then we
5394 * can count on the 64-bit instance taking care of the
5396 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5397 * taking care of the secure bank. This requires that separate
5398 * 32 and 64-bit definitions are provided.
5400 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5401 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5402 r2
->type
|= ARM_CP_ALIAS
;
5404 } else if ((secstate
!= r
->secure
) && !ns
) {
5405 /* The register is not banked so we only want to allow migration of
5406 * the non-secure instance.
5408 r2
->type
|= ARM_CP_ALIAS
;
5411 if (r
->state
== ARM_CP_STATE_BOTH
) {
5412 /* We assume it is a cp15 register if the .cp field is left unset.
5418 #ifdef HOST_WORDS_BIGENDIAN
5419 if (r2
->fieldoffset
) {
5420 r2
->fieldoffset
+= sizeof(uint32_t);
5425 if (state
== ARM_CP_STATE_AA64
) {
5426 /* To allow abbreviation of ARMCPRegInfo
5427 * definitions, we treat cp == 0 as equivalent to
5428 * the value for "standard guest-visible sysreg".
5429 * STATE_BOTH definitions are also always "standard
5430 * sysreg" in their AArch64 view (the .cp value may
5431 * be non-zero for the benefit of the AArch32 view).
5433 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5434 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5436 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5437 r2
->opc0
, opc1
, opc2
);
5439 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5442 r2
->opaque
= opaque
;
5444 /* reginfo passed to helpers is correct for the actual access,
5445 * and is never ARM_CP_STATE_BOTH:
5448 /* Make sure reginfo passed to helpers for wildcarded regs
5449 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5454 /* By convention, for wildcarded registers only the first
5455 * entry is used for migration; the others are marked as
5456 * ALIAS so we don't try to transfer the register
5457 * multiple times. Special registers (ie NOP/WFI) are
5458 * never migratable and not even raw-accessible.
5460 if ((r
->type
& ARM_CP_SPECIAL
)) {
5461 r2
->type
|= ARM_CP_NO_RAW
;
5463 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5464 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5465 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5466 r2
->type
|= ARM_CP_ALIAS
;
5469 /* Check that raw accesses are either forbidden or handled. Note that
5470 * we can't assert this earlier because the setup of fieldoffset for
5471 * banked registers has to be done first.
5473 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5474 assert(!raw_accessors_invalid(r2
));
5477 /* Overriding of an existing definition must be explicitly
5480 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5481 ARMCPRegInfo
*oldreg
;
5482 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5483 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5484 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5485 "crn=%d crm=%d opc1=%d opc2=%d, "
5486 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5487 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5488 oldreg
->name
, r2
->name
);
5489 g_assert_not_reached();
5492 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5496 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5497 const ARMCPRegInfo
*r
, void *opaque
)
5499 /* Define implementations of coprocessor registers.
5500 * We store these in a hashtable because typically
5501 * there are less than 150 registers in a space which
5502 * is 16*16*16*8*8 = 262144 in size.
5503 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5504 * If a register is defined twice then the second definition is
5505 * used, so this can be used to define some generic registers and
5506 * then override them with implementation specific variations.
5507 * At least one of the original and the second definition should
5508 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5509 * against accidental use.
5511 * The state field defines whether the register is to be
5512 * visible in the AArch32 or AArch64 execution state. If the
5513 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5514 * reginfo structure for the AArch32 view, which sees the lower
5515 * 32 bits of the 64 bit register.
5517 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5518 * be wildcarded. AArch64 registers are always considered to be 64
5519 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5520 * the register, if any.
5522 int crm
, opc1
, opc2
, state
;
5523 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5524 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5525 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5526 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5527 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5528 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5529 /* 64 bit registers have only CRm and Opc1 fields */
5530 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5531 /* op0 only exists in the AArch64 encodings */
5532 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5533 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5534 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5535 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5536 * encodes a minimum access level for the register. We roll this
5537 * runtime check into our general permission check code, so check
5538 * here that the reginfo's specified permissions are strict enough
5539 * to encompass the generic architectural permission check.
5541 if (r
->state
!= ARM_CP_STATE_AA32
) {
5544 case 0: case 1: case 2:
5557 /* unallocated encoding, so not possible */
5565 /* min_EL EL1, secure mode only (we don't check the latter) */
5569 /* broken reginfo with out-of-range opc1 */
5573 /* assert our permissions are not too lax (stricter is fine) */
5574 assert((r
->access
& ~mask
) == 0);
5577 /* Check that the register definition has enough info to handle
5578 * reads and writes if they are permitted.
5580 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5581 if (r
->access
& PL3_R
) {
5582 assert((r
->fieldoffset
||
5583 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5586 if (r
->access
& PL3_W
) {
5587 assert((r
->fieldoffset
||
5588 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5592 /* Bad type field probably means missing sentinel at end of reg list */
5593 assert(cptype_valid(r
->type
));
5594 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5595 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5596 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5597 for (state
= ARM_CP_STATE_AA32
;
5598 state
<= ARM_CP_STATE_AA64
; state
++) {
5599 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5602 if (state
== ARM_CP_STATE_AA32
) {
5603 /* Under AArch32 CP registers can be common
5604 * (same for secure and non-secure world) or banked.
5606 switch (r
->secure
) {
5607 case ARM_CP_SECSTATE_S
:
5608 case ARM_CP_SECSTATE_NS
:
5609 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5610 r
->secure
, crm
, opc1
, opc2
);
5613 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5616 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5622 /* AArch64 registers get mapped to non-secure instance
5624 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5634 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
5635 const ARMCPRegInfo
*regs
, void *opaque
)
5637 /* Define a whole list of registers */
5638 const ARMCPRegInfo
*r
;
5639 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5640 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
5644 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
5646 return g_hash_table_lookup(cpregs
, &encoded_cp
);
5649 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5652 /* Helper coprocessor write function for write-ignore registers */
5655 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5657 /* Helper coprocessor write function for read-as-zero registers */
5661 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
5663 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5666 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
5668 /* Return true if it is not valid for us to switch to
5669 * this CPU mode (ie all the UNPREDICTABLE cases in
5670 * the ARM ARM CPSRWriteByInstr pseudocode).
5673 /* Changes to or from Hyp via MSR and CPS are illegal. */
5674 if (write_type
== CPSRWriteByInstr
&&
5675 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
5676 mode
== ARM_CPU_MODE_HYP
)) {
5681 case ARM_CPU_MODE_USR
:
5683 case ARM_CPU_MODE_SYS
:
5684 case ARM_CPU_MODE_SVC
:
5685 case ARM_CPU_MODE_ABT
:
5686 case ARM_CPU_MODE_UND
:
5687 case ARM_CPU_MODE_IRQ
:
5688 case ARM_CPU_MODE_FIQ
:
5689 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5690 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5692 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5693 * and CPS are treated as illegal mode changes.
5695 if (write_type
== CPSRWriteByInstr
&&
5696 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
5697 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
5698 !arm_is_secure_below_el3(env
)) {
5702 case ARM_CPU_MODE_HYP
:
5703 return !arm_feature(env
, ARM_FEATURE_EL2
)
5704 || arm_current_el(env
) < 2 || arm_is_secure(env
);
5705 case ARM_CPU_MODE_MON
:
5706 return arm_current_el(env
) < 3;
5712 uint32_t cpsr_read(CPUARMState
*env
)
5715 ZF
= (env
->ZF
== 0);
5716 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
5717 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
5718 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
5719 | ((env
->condexec_bits
& 0xfc) << 8)
5720 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
5723 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
5724 CPSRWriteType write_type
)
5726 uint32_t changed_daif
;
5728 if (mask
& CPSR_NZCV
) {
5729 env
->ZF
= (~val
) & CPSR_Z
;
5731 env
->CF
= (val
>> 29) & 1;
5732 env
->VF
= (val
<< 3) & 0x80000000;
5735 env
->QF
= ((val
& CPSR_Q
) != 0);
5737 env
->thumb
= ((val
& CPSR_T
) != 0);
5738 if (mask
& CPSR_IT_0_1
) {
5739 env
->condexec_bits
&= ~3;
5740 env
->condexec_bits
|= (val
>> 25) & 3;
5742 if (mask
& CPSR_IT_2_7
) {
5743 env
->condexec_bits
&= 3;
5744 env
->condexec_bits
|= (val
>> 8) & 0xfc;
5746 if (mask
& CPSR_GE
) {
5747 env
->GE
= (val
>> 16) & 0xf;
5750 /* In a V7 implementation that includes the security extensions but does
5751 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5752 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5753 * bits respectively.
5755 * In a V8 implementation, it is permitted for privileged software to
5756 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5758 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
5759 arm_feature(env
, ARM_FEATURE_EL3
) &&
5760 !arm_feature(env
, ARM_FEATURE_EL2
) &&
5761 !arm_is_secure(env
)) {
5763 changed_daif
= (env
->daif
^ val
) & mask
;
5765 if (changed_daif
& CPSR_A
) {
5766 /* Check to see if we are allowed to change the masking of async
5767 * abort exceptions from a non-secure state.
5769 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
5770 qemu_log_mask(LOG_GUEST_ERROR
,
5771 "Ignoring attempt to switch CPSR_A flag from "
5772 "non-secure world with SCR.AW bit clear\n");
5777 if (changed_daif
& CPSR_F
) {
5778 /* Check to see if we are allowed to change the masking of FIQ
5779 * exceptions from a non-secure state.
5781 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
5782 qemu_log_mask(LOG_GUEST_ERROR
,
5783 "Ignoring attempt to switch CPSR_F flag from "
5784 "non-secure world with SCR.FW bit clear\n");
5788 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5789 * If this bit is set software is not allowed to mask
5790 * FIQs, but is allowed to set CPSR_F to 0.
5792 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
5794 qemu_log_mask(LOG_GUEST_ERROR
,
5795 "Ignoring attempt to enable CPSR_F flag "
5796 "(non-maskable FIQ [NMFI] support enabled)\n");
5802 env
->daif
&= ~(CPSR_AIF
& mask
);
5803 env
->daif
|= val
& CPSR_AIF
& mask
;
5805 if (write_type
!= CPSRWriteRaw
&&
5806 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
5807 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
5808 /* Note that we can only get here in USR mode if this is a
5809 * gdb stub write; for this case we follow the architectural
5810 * behaviour for guest writes in USR mode of ignoring an attempt
5811 * to switch mode. (Those are caught by translate.c for writes
5812 * triggered by guest instructions.)
5815 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
5816 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5817 * v7, and has defined behaviour in v8:
5818 * + leave CPSR.M untouched
5819 * + allow changes to the other CPSR fields
5821 * For user changes via the GDB stub, we don't set PSTATE.IL,
5822 * as this would be unnecessarily harsh for a user error.
5825 if (write_type
!= CPSRWriteByGDBStub
&&
5826 arm_feature(env
, ARM_FEATURE_V8
)) {
5831 switch_mode(env
, val
& CPSR_M
);
5834 mask
&= ~CACHED_CPSR_BITS
;
5835 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
5838 /* Sign/zero extend */
5839 uint32_t HELPER(sxtb16
)(uint32_t x
)
5842 res
= (uint16_t)(int8_t)x
;
5843 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
5847 uint32_t HELPER(uxtb16
)(uint32_t x
)
5850 res
= (uint16_t)(uint8_t)x
;
5851 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
5855 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
5859 if (num
== INT_MIN
&& den
== -1)
5864 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
5871 uint32_t HELPER(rbit
)(uint32_t x
)
5876 #if defined(CONFIG_USER_ONLY)
5878 /* These should probably raise undefined insn exceptions. */
5879 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
5881 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5883 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
5886 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5888 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5890 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
5894 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
5896 /* translate.c should never generate calls here in user-only mode */
5897 g_assert_not_reached();
5900 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
5902 /* translate.c should never generate calls here in user-only mode */
5903 g_assert_not_reached();
5906 void switch_mode(CPUARMState
*env
, int mode
)
5908 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5910 if (mode
!= ARM_CPU_MODE_USR
) {
5911 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
5915 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5916 uint32_t cur_el
, bool secure
)
5921 void aarch64_sync_64_to_32(CPUARMState
*env
)
5923 g_assert_not_reached();
5928 void switch_mode(CPUARMState
*env
, int mode
)
5933 old_mode
= env
->uncached_cpsr
& CPSR_M
;
5934 if (mode
== old_mode
)
5937 if (old_mode
== ARM_CPU_MODE_FIQ
) {
5938 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5939 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
5940 } else if (mode
== ARM_CPU_MODE_FIQ
) {
5941 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5942 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
5945 i
= bank_number(old_mode
);
5946 env
->banked_r13
[i
] = env
->regs
[13];
5947 env
->banked_r14
[i
] = env
->regs
[14];
5948 env
->banked_spsr
[i
] = env
->spsr
;
5950 i
= bank_number(mode
);
5951 env
->regs
[13] = env
->banked_r13
[i
];
5952 env
->regs
[14] = env
->banked_r14
[i
];
5953 env
->spsr
= env
->banked_spsr
[i
];
5956 /* Physical Interrupt Target EL Lookup Table
5958 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5960 * The below multi-dimensional table is used for looking up the target
5961 * exception level given numerous condition criteria. Specifically, the
5962 * target EL is based on SCR and HCR routing controls as well as the
5963 * currently executing EL and secure state.
5966 * target_el_table[2][2][2][2][2][4]
5967 * | | | | | +--- Current EL
5968 * | | | | +------ Non-secure(0)/Secure(1)
5969 * | | | +--------- HCR mask override
5970 * | | +------------ SCR exec state control
5971 * | +--------------- SCR mask override
5972 * +------------------ 32-bit(0)/64-bit(1) EL3
5974 * The table values are as such:
5978 * The ARM ARM target EL table includes entries indicating that an "exception
5979 * is not taken". The two cases where this is applicable are:
5980 * 1) An exception is taken from EL3 but the SCR does not have the exception
5982 * 2) An exception is taken from EL2 but the HCR does not have the exception
5984 * In these two cases, the below table contain a target of EL1. This value is
5985 * returned as it is expected that the consumer of the table data will check
5986 * for "target EL >= current EL" to ensure the exception is not taken.
5990 * BIT IRQ IMO Non-secure Secure
5991 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5993 static const int8_t target_el_table
[2][2][2][2][2][4] = {
5994 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5995 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5996 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5997 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5998 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5999 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
6000 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6001 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
6002 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
6003 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
6004 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
6005 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
6006 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6007 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
6008 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6009 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
6013 * Determine the target EL for physical exceptions
6015 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6016 uint32_t cur_el
, bool secure
)
6018 CPUARMState
*env
= cs
->env_ptr
;
6023 /* Is the highest EL AArch64? */
6024 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
6026 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6027 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
6029 /* Either EL2 is the highest EL (and so the EL2 register width
6030 * is given by is64); or there is no EL2 or EL3, in which case
6031 * the value of 'rw' does not affect the table lookup anyway.
6038 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
6039 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
6042 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
6043 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
6046 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
6047 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
6051 /* If HCR.TGE is set then HCR is treated as being 1 */
6052 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
6054 /* Perform a table-lookup for the target EL given the current state */
6055 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
6057 assert(target_el
> 0);
6062 static void v7m_push(CPUARMState
*env
, uint32_t val
)
6064 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6067 stl_phys(cs
->as
, env
->regs
[13], val
);
6070 /* Return true if we're using the process stack pointer (not the MSP) */
6071 static bool v7m_using_psp(CPUARMState
*env
)
6073 /* Handler mode always uses the main stack; for thread mode
6074 * the CONTROL.SPSEL bit determines the answer.
6075 * Note that in v7M it is not possible to be in Handler mode with
6076 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
6078 return !arm_v7m_is_handler_mode(env
) &&
6079 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
6082 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6083 * This may change the current stack pointer between Main and Process
6084 * stack pointers if it is done for the CONTROL register for the current
6087 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
6091 bool old_is_psp
= v7m_using_psp(env
);
6093 env
->v7m
.control
[secstate
] =
6094 deposit32(env
->v7m
.control
[secstate
],
6095 R_V7M_CONTROL_SPSEL_SHIFT
,
6096 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6098 if (secstate
== env
->v7m
.secure
) {
6099 bool new_is_psp
= v7m_using_psp(env
);
6102 if (old_is_psp
!= new_is_psp
) {
6103 tmp
= env
->v7m
.other_sp
;
6104 env
->v7m
.other_sp
= env
->regs
[13];
6105 env
->regs
[13] = tmp
;
6110 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6111 * stack pointer between Main and Process stack pointers.
6113 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
6115 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
6118 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
6120 /* Write a new value to v7m.exception, thus transitioning into or out
6121 * of Handler mode; this may result in a change of active stack pointer.
6123 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
6126 env
->v7m
.exception
= new_exc
;
6128 new_is_psp
= v7m_using_psp(env
);
6130 if (old_is_psp
!= new_is_psp
) {
6131 tmp
= env
->v7m
.other_sp
;
6132 env
->v7m
.other_sp
= env
->regs
[13];
6133 env
->regs
[13] = tmp
;
6137 /* Switch M profile security state between NS and S */
6138 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
6140 uint32_t new_ss_msp
, new_ss_psp
;
6142 if (env
->v7m
.secure
== new_secstate
) {
6146 /* All the banked state is accessed by looking at env->v7m.secure
6147 * except for the stack pointer; rearrange the SP appropriately.
6149 new_ss_msp
= env
->v7m
.other_ss_msp
;
6150 new_ss_psp
= env
->v7m
.other_ss_psp
;
6152 if (v7m_using_psp(env
)) {
6153 env
->v7m
.other_ss_psp
= env
->regs
[13];
6154 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
6156 env
->v7m
.other_ss_msp
= env
->regs
[13];
6157 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
6160 env
->v7m
.secure
= new_secstate
;
6162 if (v7m_using_psp(env
)) {
6163 env
->regs
[13] = new_ss_psp
;
6164 env
->v7m
.other_sp
= new_ss_msp
;
6166 env
->regs
[13] = new_ss_msp
;
6167 env
->v7m
.other_sp
= new_ss_psp
;
6171 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6174 * - if the return value is a magic value, do exception return (like BX)
6175 * - otherwise bit 0 of the return value is the target security state
6179 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6180 /* Covers FNC_RETURN and EXC_RETURN magic */
6181 min_magic
= FNC_RETURN_MIN_MAGIC
;
6183 /* EXC_RETURN magic only */
6184 min_magic
= EXC_RETURN_MIN_MAGIC
;
6187 if (dest
>= min_magic
) {
6188 /* This is an exception return magic value; put it where
6189 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6190 * Note that if we ever add gen_ss_advance() singlestep support to
6191 * M profile this should count as an "instruction execution complete"
6192 * event (compare gen_bx_excret_final_code()).
6194 env
->regs
[15] = dest
& ~1;
6195 env
->thumb
= dest
& 1;
6196 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
6200 /* translate.c should have made BXNS UNDEF unless we're secure */
6201 assert(env
->v7m
.secure
);
6203 switch_v7m_security_state(env
, dest
& 1);
6205 env
->regs
[15] = dest
& ~1;
6208 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6210 /* Handle v7M BLXNS:
6211 * - bit 0 of the destination address is the target security state
6214 /* At this point regs[15] is the address just after the BLXNS */
6215 uint32_t nextinst
= env
->regs
[15] | 1;
6216 uint32_t sp
= env
->regs
[13] - 8;
6219 /* translate.c will have made BLXNS UNDEF unless we're secure */
6220 assert(env
->v7m
.secure
);
6223 /* target is Secure, so this is just a normal BLX,
6224 * except that the low bit doesn't indicate Thumb/not.
6226 env
->regs
[14] = nextinst
;
6228 env
->regs
[15] = dest
& ~1;
6232 /* Target is non-secure: first push a stack frame */
6233 if (!QEMU_IS_ALIGNED(sp
, 8)) {
6234 qemu_log_mask(LOG_GUEST_ERROR
,
6235 "BLXNS with misaligned SP is UNPREDICTABLE\n");
6238 saved_psr
= env
->v7m
.exception
;
6239 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
6240 saved_psr
|= XPSR_SFPA
;
6243 /* Note that these stores can throw exceptions on MPU faults */
6244 cpu_stl_data(env
, sp
, nextinst
);
6245 cpu_stl_data(env
, sp
+ 4, saved_psr
);
6248 env
->regs
[14] = 0xfeffffff;
6249 if (arm_v7m_is_handler_mode(env
)) {
6250 /* Write a dummy value to IPSR, to avoid leaking the current secure
6251 * exception number to non-secure code. This is guaranteed not
6252 * to cause write_v7m_exception() to actually change stacks.
6254 write_v7m_exception(env
, 1);
6256 switch_v7m_security_state(env
, 0);
6258 env
->regs
[15] = dest
;
6261 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
6264 /* Return a pointer to the location where we currently store the
6265 * stack pointer for the requested security state and thread mode.
6266 * This pointer will become invalid if the CPU state is updated
6267 * such that the stack pointers are switched around (eg changing
6268 * the SPSEL control bit).
6269 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6270 * Unlike that pseudocode, we require the caller to pass us in the
6271 * SPSEL control bit value; this is because we also use this
6272 * function in handling of pushing of the callee-saves registers
6273 * part of the v8M stack frame (pseudocode PushCalleeStack()),
6274 * and in the tailchain codepath the SPSEL bit comes from the exception
6275 * return magic LR value from the previous exception. The pseudocode
6276 * opencodes the stack-selection in PushCalleeStack(), but we prefer
6277 * to make this utility function generic enough to do the job.
6279 bool want_psp
= threadmode
&& spsel
;
6281 if (secure
== env
->v7m
.secure
) {
6282 if (want_psp
== v7m_using_psp(env
)) {
6283 return &env
->regs
[13];
6285 return &env
->v7m
.other_sp
;
6289 return &env
->v7m
.other_ss_psp
;
6291 return &env
->v7m
.other_ss_msp
;
6296 static uint32_t arm_v7m_load_vector(ARMCPU
*cpu
, bool targets_secure
)
6298 CPUState
*cs
= CPU(cpu
);
6299 CPUARMState
*env
= &cpu
->env
;
6301 hwaddr vec
= env
->v7m
.vecbase
[targets_secure
] + env
->v7m
.exception
* 4;
6304 addr
= address_space_ldl(cs
->as
, vec
,
6305 MEMTXATTRS_UNSPECIFIED
, &result
);
6306 if (result
!= MEMTX_OK
) {
6307 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
6308 * which would then be immediately followed by our failing to load
6309 * the entry vector for that HardFault, which is a Lockup case.
6310 * Since we don't model Lockup, we just report this guest error
6313 cpu_abort(cs
, "Failed to read from %s exception vector table "
6314 "entry %08x\n", targets_secure
? "secure" : "nonsecure",
6320 static void v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
)
6322 /* For v8M, push the callee-saves register part of the stack frame.
6323 * Compare the v8M pseudocode PushCalleeStack().
6324 * In the tailchaining case this may not be the current stack.
6326 CPUARMState
*env
= &cpu
->env
;
6327 CPUState
*cs
= CPU(cpu
);
6328 uint32_t *frame_sp_p
;
6332 frame_sp_p
= get_v7m_sp_ptr(env
, true,
6333 lr
& R_V7M_EXCRET_MODE_MASK
,
6334 lr
& R_V7M_EXCRET_SPSEL_MASK
);
6336 frame_sp_p
= &env
->regs
[13];
6339 frameptr
= *frame_sp_p
- 0x28;
6341 stl_phys(cs
->as
, frameptr
, 0xfefa125b);
6342 stl_phys(cs
->as
, frameptr
+ 0x8, env
->regs
[4]);
6343 stl_phys(cs
->as
, frameptr
+ 0xc, env
->regs
[5]);
6344 stl_phys(cs
->as
, frameptr
+ 0x10, env
->regs
[6]);
6345 stl_phys(cs
->as
, frameptr
+ 0x14, env
->regs
[7]);
6346 stl_phys(cs
->as
, frameptr
+ 0x18, env
->regs
[8]);
6347 stl_phys(cs
->as
, frameptr
+ 0x1c, env
->regs
[9]);
6348 stl_phys(cs
->as
, frameptr
+ 0x20, env
->regs
[10]);
6349 stl_phys(cs
->as
, frameptr
+ 0x24, env
->regs
[11]);
6351 *frame_sp_p
= frameptr
;
6354 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
)
6356 /* Do the "take the exception" parts of exception entry,
6357 * but not the pushing of state to the stack. This is
6358 * similar to the pseudocode ExceptionTaken() function.
6360 CPUARMState
*env
= &cpu
->env
;
6362 bool targets_secure
;
6364 targets_secure
= armv7m_nvic_acknowledge_irq(env
->nvic
);
6366 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6367 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6368 (lr
& R_V7M_EXCRET_S_MASK
)) {
6369 /* The background code (the owner of the registers in the
6370 * exception frame) is Secure. This means it may either already
6371 * have or now needs to push callee-saves registers.
6373 if (targets_secure
) {
6374 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
6375 /* We took an exception from Secure to NonSecure
6376 * (which means the callee-saved registers got stacked)
6377 * and are now tailchaining to a Secure exception.
6378 * Clear DCRS so eventual return from this Secure
6379 * exception unstacks the callee-saved registers.
6381 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
6384 /* We're going to a non-secure exception; push the
6385 * callee-saves registers to the stack now, if they're
6386 * not already saved.
6388 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
6389 !(dotailchain
&& (lr
& R_V7M_EXCRET_ES_MASK
))) {
6390 v7m_push_callee_stack(cpu
, lr
, dotailchain
);
6392 lr
|= R_V7M_EXCRET_DCRS_MASK
;
6396 lr
&= ~R_V7M_EXCRET_ES_MASK
;
6397 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6398 lr
|= R_V7M_EXCRET_ES_MASK
;
6400 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
6401 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
6402 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
6405 /* Clear registers if necessary to prevent non-secure exception
6406 * code being able to see register values from secure code.
6407 * Where register values become architecturally UNKNOWN we leave
6408 * them with their previous values.
6410 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6411 if (!targets_secure
) {
6412 /* Always clear the caller-saved registers (they have been
6413 * pushed to the stack earlier in v7m_push_stack()).
6414 * Clear callee-saved registers if the background code is
6415 * Secure (in which case these regs were saved in
6416 * v7m_push_callee_stack()).
6420 for (i
= 0; i
< 13; i
++) {
6421 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
6422 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
6427 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
6432 /* Switch to target security state -- must do this before writing SPSEL */
6433 switch_v7m_security_state(env
, targets_secure
);
6434 write_v7m_control_spsel(env
, 0);
6435 arm_clear_exclusive(env
);
6437 env
->condexec_bits
= 0;
6439 addr
= arm_v7m_load_vector(cpu
, targets_secure
);
6440 env
->regs
[15] = addr
& 0xfffffffe;
6441 env
->thumb
= addr
& 1;
6444 static void v7m_push_stack(ARMCPU
*cpu
)
6446 /* Do the "set up stack frame" part of exception entry,
6447 * similar to pseudocode PushStack().
6449 CPUARMState
*env
= &cpu
->env
;
6450 uint32_t xpsr
= xpsr_read(env
);
6452 /* Align stack pointer if the guest wants that */
6453 if ((env
->regs
[13] & 4) &&
6454 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
6456 xpsr
|= XPSR_SPREALIGN
;
6458 /* Switch to the handler mode. */
6459 v7m_push(env
, xpsr
);
6460 v7m_push(env
, env
->regs
[15]);
6461 v7m_push(env
, env
->regs
[14]);
6462 v7m_push(env
, env
->regs
[12]);
6463 v7m_push(env
, env
->regs
[3]);
6464 v7m_push(env
, env
->regs
[2]);
6465 v7m_push(env
, env
->regs
[1]);
6466 v7m_push(env
, env
->regs
[0]);
6469 static void do_v7m_exception_exit(ARMCPU
*cpu
)
6471 CPUARMState
*env
= &cpu
->env
;
6472 CPUState
*cs
= CPU(cpu
);
6475 bool ufault
= false;
6476 bool sfault
= false;
6477 bool return_to_sp_process
;
6478 bool return_to_handler
;
6479 bool rettobase
= false;
6480 bool exc_secure
= false;
6481 bool return_to_secure
;
6483 /* If we're not in Handler mode then jumps to magic exception-exit
6484 * addresses don't have magic behaviour. However for the v8M
6485 * security extensions the magic secure-function-return has to
6486 * work in thread mode too, so to avoid doing an extra check in
6487 * the generated code we allow exception-exit magic to also cause the
6488 * internal exception and bring us here in thread mode. Correct code
6489 * will never try to do this (the following insn fetch will always
6490 * fault) so we the overhead of having taken an unnecessary exception
6493 if (!arm_v7m_is_handler_mode(env
)) {
6497 /* In the spec pseudocode ExceptionReturn() is called directly
6498 * from BXWritePC() and gets the full target PC value including
6499 * bit zero. In QEMU's implementation we treat it as a normal
6500 * jump-to-register (which is then caught later on), and so split
6501 * the target value up between env->regs[15] and env->thumb in
6502 * gen_bx(). Reconstitute it.
6504 excret
= env
->regs
[15];
6509 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
6510 " previous exception %d\n",
6511 excret
, env
->v7m
.exception
);
6513 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
6514 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
6515 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
6519 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6520 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
6521 * we pick which FAULTMASK to clear.
6523 if (!env
->v7m
.secure
&&
6524 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
6525 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
6527 /* For all other purposes, treat ES as 0 (R_HXSR) */
6528 excret
&= ~R_V7M_EXCRET_ES_MASK
;
6532 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
6533 /* Auto-clear FAULTMASK on return from other than NMI.
6534 * If the security extension is implemented then this only
6535 * happens if the raw execution priority is >= 0; the
6536 * value of the ES bit in the exception return value indicates
6537 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
6539 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6540 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
6541 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
6542 env
->v7m
.faultmask
[exc_secure
] = 0;
6545 env
->v7m
.faultmask
[M_REG_NS
] = 0;
6549 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
6552 /* attempt to exit an exception that isn't active */
6556 /* still an irq active now */
6559 /* we returned to base exception level, no nesting.
6560 * (In the pseudocode this is written using "NestedActivation != 1"
6561 * where we have 'rettobase == false'.)
6566 g_assert_not_reached();
6569 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
6570 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
6571 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6572 (excret
& R_V7M_EXCRET_S_MASK
);
6574 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6575 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6576 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
6577 * we choose to take the UsageFault.
6579 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
6580 (excret
& R_V7M_EXCRET_ES_MASK
) ||
6581 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
6585 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
6589 /* For v7M we only recognize certain combinations of the low bits */
6590 switch (excret
& 0xf) {
6591 case 1: /* Return to Handler */
6593 case 13: /* Return to Thread using Process stack */
6594 case 9: /* Return to Thread using Main stack */
6595 /* We only need to check NONBASETHRDENA for v7M, because in
6596 * v8M this bit does not exist (it is RES1).
6599 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
6600 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
6610 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
6611 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
6612 v7m_exception_taken(cpu
, excret
, true);
6613 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
6614 "stackframe: failed EXC_RETURN.ES validity check\n");
6619 /* Bad exception return: instead of popping the exception
6620 * stack, directly take a usage fault on the current stack.
6622 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6623 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
6624 v7m_exception_taken(cpu
, excret
, true);
6625 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
6626 "stackframe: failed exception return integrity check\n");
6630 /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
6631 * Handler mode (and will be until we write the new XPSR.Interrupt
6632 * field) this does not switch around the current stack pointer.
6634 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
6636 switch_v7m_security_state(env
, return_to_secure
);
6639 /* The stack pointer we should be reading the exception frame from
6640 * depends on bits in the magic exception return type value (and
6641 * for v8M isn't necessarily the stack pointer we will eventually
6642 * end up resuming execution with). Get a pointer to the location
6643 * in the CPU state struct where the SP we need is currently being
6644 * stored; we will use and modify it in place.
6645 * We use this limited C variable scope so we don't accidentally
6646 * use 'frame_sp_p' after we do something that makes it invalid.
6648 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
6651 return_to_sp_process
);
6652 uint32_t frameptr
= *frame_sp_p
;
6654 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
6655 arm_feature(env
, ARM_FEATURE_V8
)) {
6656 qemu_log_mask(LOG_GUEST_ERROR
,
6657 "M profile exception return with non-8-aligned SP "
6658 "for destination state is UNPREDICTABLE\n");
6661 /* Do we need to pop callee-saved registers? */
6662 if (return_to_secure
&&
6663 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
6664 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
6665 uint32_t expected_sig
= 0xfefa125b;
6666 uint32_t actual_sig
= ldl_phys(cs
->as
, frameptr
);
6668 if (expected_sig
!= actual_sig
) {
6669 /* Take a SecureFault on the current stack */
6670 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
6671 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
6672 v7m_exception_taken(cpu
, excret
, true);
6673 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
6674 "stackframe: failed exception return integrity "
6675 "signature check\n");
6679 env
->regs
[4] = ldl_phys(cs
->as
, frameptr
+ 0x8);
6680 env
->regs
[5] = ldl_phys(cs
->as
, frameptr
+ 0xc);
6681 env
->regs
[6] = ldl_phys(cs
->as
, frameptr
+ 0x10);
6682 env
->regs
[7] = ldl_phys(cs
->as
, frameptr
+ 0x14);
6683 env
->regs
[8] = ldl_phys(cs
->as
, frameptr
+ 0x18);
6684 env
->regs
[9] = ldl_phys(cs
->as
, frameptr
+ 0x1c);
6685 env
->regs
[10] = ldl_phys(cs
->as
, frameptr
+ 0x20);
6686 env
->regs
[11] = ldl_phys(cs
->as
, frameptr
+ 0x24);
6691 /* Pop registers. TODO: make these accesses use the correct
6692 * attributes and address space (S/NS, priv/unpriv) and handle
6693 * memory transaction failures.
6695 env
->regs
[0] = ldl_phys(cs
->as
, frameptr
);
6696 env
->regs
[1] = ldl_phys(cs
->as
, frameptr
+ 0x4);
6697 env
->regs
[2] = ldl_phys(cs
->as
, frameptr
+ 0x8);
6698 env
->regs
[3] = ldl_phys(cs
->as
, frameptr
+ 0xc);
6699 env
->regs
[12] = ldl_phys(cs
->as
, frameptr
+ 0x10);
6700 env
->regs
[14] = ldl_phys(cs
->as
, frameptr
+ 0x14);
6701 env
->regs
[15] = ldl_phys(cs
->as
, frameptr
+ 0x18);
6703 /* Returning from an exception with a PC with bit 0 set is defined
6704 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
6705 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
6706 * the lsbit, and there are several RTOSes out there which incorrectly
6707 * assume the r15 in the stack frame should be a Thumb-style "lsbit
6708 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
6709 * complain about the badly behaved guest.
6711 if (env
->regs
[15] & 1) {
6712 env
->regs
[15] &= ~1U;
6713 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
6714 qemu_log_mask(LOG_GUEST_ERROR
,
6715 "M profile return from interrupt with misaligned "
6716 "PC is UNPREDICTABLE on v7M\n");
6720 xpsr
= ldl_phys(cs
->as
, frameptr
+ 0x1c);
6722 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6723 /* For v8M we have to check whether the xPSR exception field
6724 * matches the EXCRET value for return to handler/thread
6725 * before we commit to changing the SP and xPSR.
6727 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
6728 if (return_to_handler
!= will_be_handler
) {
6729 /* Take an INVPC UsageFault on the current stack.
6730 * By this point we will have switched to the security state
6731 * for the background state, so this UsageFault will target
6734 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
6736 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6737 v7m_exception_taken(cpu
, excret
, true);
6738 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
6739 "stackframe: failed exception return integrity "
6745 /* Commit to consuming the stack frame */
6747 /* Undo stack alignment (the SPREALIGN bit indicates that the original
6748 * pre-exception SP was not 8-aligned and we added a padding word to
6749 * align it, so we undo this by ORing in the bit that increases it
6750 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
6751 * would work too but a logical OR is how the pseudocode specifies it.)
6753 if (xpsr
& XPSR_SPREALIGN
) {
6756 *frame_sp_p
= frameptr
;
6758 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
6759 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
6761 /* The restored xPSR exception field will be zero if we're
6762 * resuming in Thread mode. If that doesn't match what the
6763 * exception return excret specified then this is a UsageFault.
6764 * v7M requires we make this check here; v8M did it earlier.
6766 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
6767 /* Take an INVPC UsageFault by pushing the stack again;
6768 * we know we're v7M so this is never a Secure UsageFault.
6770 assert(!arm_feature(env
, ARM_FEATURE_V8
));
6771 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
6772 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6773 v7m_push_stack(cpu
);
6774 v7m_exception_taken(cpu
, excret
, false);
6775 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
6776 "failed exception return integrity check\n");
6780 /* Otherwise, we have a successful exception exit. */
6781 arm_clear_exclusive(env
);
6782 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
6785 static bool do_v7m_function_return(ARMCPU
*cpu
)
6787 /* v8M security extensions magic function return.
6789 * (1) throw an exception (longjump)
6790 * (2) return true if we successfully handled the function return
6791 * (3) return false if we failed a consistency check and have
6792 * pended a UsageFault that needs to be taken now
6794 * At this point the magic return value is split between env->regs[15]
6795 * and env->thumb. We don't bother to reconstitute it because we don't
6796 * need it (all values are handled the same way).
6798 CPUARMState
*env
= &cpu
->env
;
6799 uint32_t newpc
, newpsr
, newpsr_exc
;
6801 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
6804 bool threadmode
, spsel
;
6807 uint32_t *frame_sp_p
;
6810 /* Pull the return address and IPSR from the Secure stack */
6811 threadmode
= !arm_v7m_is_handler_mode(env
);
6812 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
6814 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
6815 frameptr
= *frame_sp_p
;
6817 /* These loads may throw an exception (for MPU faults). We want to
6818 * do them as secure, so work out what MMU index that is.
6820 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
6821 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
6822 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
6823 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
6825 /* Consistency checks on new IPSR */
6826 newpsr_exc
= newpsr
& XPSR_EXCP
;
6827 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
6828 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
6829 /* Pend the fault and tell our caller to take it */
6830 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6831 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
6833 qemu_log_mask(CPU_LOG_INT
,
6834 "...taking INVPC UsageFault: "
6835 "IPSR consistency check failed\n");
6839 *frame_sp_p
= frameptr
+ 8;
6842 /* This invalidates frame_sp_p */
6843 switch_v7m_security_state(env
, true);
6844 env
->v7m
.exception
= newpsr_exc
;
6845 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
6846 if (newpsr
& XPSR_SFPA
) {
6847 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
6849 xpsr_write(env
, 0, XPSR_IT
);
6850 env
->thumb
= newpc
& 1;
6851 env
->regs
[15] = newpc
& ~1;
6853 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
6857 static void arm_log_exception(int idx
)
6859 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
6860 const char *exc
= NULL
;
6861 static const char * const excnames
[] = {
6862 [EXCP_UDEF
] = "Undefined Instruction",
6864 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
6865 [EXCP_DATA_ABORT
] = "Data Abort",
6868 [EXCP_BKPT
] = "Breakpoint",
6869 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
6870 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
6871 [EXCP_HVC
] = "Hypervisor Call",
6872 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
6873 [EXCP_SMC
] = "Secure Monitor Call",
6874 [EXCP_VIRQ
] = "Virtual IRQ",
6875 [EXCP_VFIQ
] = "Virtual FIQ",
6876 [EXCP_SEMIHOST
] = "Semihosting call",
6877 [EXCP_NOCP
] = "v7M NOCP UsageFault",
6878 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
6881 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
6882 exc
= excnames
[idx
];
6887 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
6891 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
6892 uint32_t addr
, uint16_t *insn
)
6894 /* Load a 16-bit portion of a v7M instruction, returning true on success,
6895 * or false on failure (in which case we will have pended the appropriate
6897 * We need to do the instruction fetch's MPU and SAU checks
6898 * like this because there is no MMU index that would allow
6899 * doing the load with a single function call. Instead we must
6900 * first check that the security attributes permit the load
6901 * and that they don't mismatch on the two halves of the instruction,
6902 * and then we do the load as a secure load (ie using the security
6903 * attributes of the address, not the CPU, as architecturally required).
6905 CPUState
*cs
= CPU(cpu
);
6906 CPUARMState
*env
= &cpu
->env
;
6907 V8M_SAttributes sattrs
= {};
6908 MemTxAttrs attrs
= {};
6909 ARMMMUFaultInfo fi
= {};
6911 target_ulong page_size
;
6916 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
6917 if (!sattrs
.nsc
|| sattrs
.ns
) {
6918 /* This must be the second half of the insn, and it straddles a
6919 * region boundary with the second half not being S&NSC.
6921 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
6922 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
6923 qemu_log_mask(CPU_LOG_INT
,
6924 "...really SecureFault with SFSR.INVEP\n");
6927 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
6928 &physaddr
, &attrs
, &prot
, &page_size
, &fsr
, &fi
)) {
6929 /* the MPU lookup failed */
6930 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
6931 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
6932 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
6935 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
6937 if (txres
!= MEMTX_OK
) {
6938 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
6939 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
6940 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
6946 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
6948 /* Check whether this attempt to execute code in a Secure & NS-Callable
6949 * memory region is for an SG instruction; if so, then emulate the
6950 * effect of the SG instruction and return true. Otherwise pend
6951 * the correct kind of exception and return false.
6953 CPUARMState
*env
= &cpu
->env
;
6957 /* We should never get here unless get_phys_addr_pmsav8() caused
6958 * an exception for NS executing in S&NSC memory.
6960 assert(!env
->v7m
.secure
);
6961 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
6963 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
6964 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
6966 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
6974 if (insn
!= 0xe97f) {
6975 /* Not an SG instruction first half (we choose the IMPDEF
6976 * early-SG-check option).
6981 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
6985 if (insn
!= 0xe97f) {
6986 /* Not an SG instruction second half (yes, both halves of the SG
6987 * insn have the same hex value)
6992 /* OK, we have confirmed that we really have an SG instruction.
6993 * We know we're NS in S memory so don't need to repeat those checks.
6995 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
6996 ", executing it\n", env
->regs
[15]);
6997 env
->regs
[14] &= ~1;
6998 switch_v7m_security_state(env
, true);
6999 xpsr_write(env
, 0, XPSR_IT
);
7004 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7005 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7006 qemu_log_mask(CPU_LOG_INT
,
7007 "...really SecureFault with SFSR.INVEP\n");
7011 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
7013 ARMCPU
*cpu
= ARM_CPU(cs
);
7014 CPUARMState
*env
= &cpu
->env
;
7017 arm_log_exception(cs
->exception_index
);
7019 /* For exceptions we just mark as pending on the NVIC, and let that
7021 switch (cs
->exception_index
) {
7023 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7024 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
7027 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7028 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
7031 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7032 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
7035 /* The PC already points to the next instruction. */
7036 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
7038 case EXCP_PREFETCH_ABORT
:
7039 case EXCP_DATA_ABORT
:
7040 /* Note that for M profile we don't have a guest facing FSR, but
7041 * the env->exception.fsr will be populated by the code that
7042 * raises the fault, in the A profile short-descriptor format.
7044 switch (env
->exception
.fsr
& 0xf) {
7045 case M_FAKE_FSR_NSC_EXEC
:
7046 /* Exception generated when we try to execute code at an address
7047 * which is marked as Secure & Non-Secure Callable and the CPU
7048 * is in the Non-Secure state. The only instruction which can
7049 * be executed like this is SG (and that only if both halves of
7050 * the SG instruction have the same security attributes.)
7051 * Everything else must generate an INVEP SecureFault, so we
7052 * emulate the SG instruction here.
7054 if (v7m_handle_execute_nsc(cpu
)) {
7058 case M_FAKE_FSR_SFAULT
:
7059 /* Various flavours of SecureFault for attempts to execute or
7060 * access data in the wrong security state.
7062 switch (cs
->exception_index
) {
7063 case EXCP_PREFETCH_ABORT
:
7064 if (env
->v7m
.secure
) {
7065 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
7066 qemu_log_mask(CPU_LOG_INT
,
7067 "...really SecureFault with SFSR.INVTRAN\n");
7069 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7070 qemu_log_mask(CPU_LOG_INT
,
7071 "...really SecureFault with SFSR.INVEP\n");
7074 case EXCP_DATA_ABORT
:
7075 /* This must be an NS access to S memory */
7076 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
7077 qemu_log_mask(CPU_LOG_INT
,
7078 "...really SecureFault with SFSR.AUVIOL\n");
7081 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7083 case 0x8: /* External Abort */
7084 switch (cs
->exception_index
) {
7085 case EXCP_PREFETCH_ABORT
:
7086 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7087 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
7089 case EXCP_DATA_ABORT
:
7090 env
->v7m
.cfsr
[M_REG_NS
] |=
7091 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
7092 env
->v7m
.bfar
= env
->exception
.vaddress
;
7093 qemu_log_mask(CPU_LOG_INT
,
7094 "...with CFSR.PRECISERR and BFAR 0x%x\n",
7098 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7101 /* All other FSR values are either MPU faults or "can't happen
7102 * for M profile" cases.
7104 switch (cs
->exception_index
) {
7105 case EXCP_PREFETCH_ABORT
:
7106 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7107 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
7109 case EXCP_DATA_ABORT
:
7110 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
7111 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
7112 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
7113 qemu_log_mask(CPU_LOG_INT
,
7114 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
7115 env
->v7m
.mmfar
[env
->v7m
.secure
]);
7118 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
7124 if (semihosting_enabled()) {
7126 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
7129 qemu_log_mask(CPU_LOG_INT
,
7130 "...handling as semihosting call 0x%x\n",
7132 env
->regs
[0] = do_arm_semihosting(env
);
7136 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
7140 case EXCP_EXCEPTION_EXIT
:
7141 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
7142 /* Must be v8M security extension function return */
7143 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
7144 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7145 if (do_v7m_function_return(cpu
)) {
7149 do_v7m_exception_exit(cpu
);
7154 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7155 return; /* Never happens. Keep compiler happy. */
7158 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7159 lr
= R_V7M_EXCRET_RES1_MASK
|
7160 R_V7M_EXCRET_DCRS_MASK
|
7161 R_V7M_EXCRET_FTYPE_MASK
;
7162 /* The S bit indicates whether we should return to Secure
7163 * or NonSecure (ie our current state).
7164 * The ES bit indicates whether we're taking this exception
7165 * to Secure or NonSecure (ie our target state). We set it
7166 * later, in v7m_exception_taken().
7167 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
7168 * This corresponds to the ARM ARM pseudocode for v8M setting
7169 * some LR bits in PushStack() and some in ExceptionTaken();
7170 * the distinction matters for the tailchain cases where we
7171 * can take an exception without pushing the stack.
7173 if (env
->v7m
.secure
) {
7174 lr
|= R_V7M_EXCRET_S_MASK
;
7177 lr
= R_V7M_EXCRET_RES1_MASK
|
7178 R_V7M_EXCRET_S_MASK
|
7179 R_V7M_EXCRET_DCRS_MASK
|
7180 R_V7M_EXCRET_FTYPE_MASK
|
7181 R_V7M_EXCRET_ES_MASK
;
7182 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
7183 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
7186 if (!arm_v7m_is_handler_mode(env
)) {
7187 lr
|= R_V7M_EXCRET_MODE_MASK
;
7190 v7m_push_stack(cpu
);
7191 v7m_exception_taken(cpu
, lr
, false);
7192 qemu_log_mask(CPU_LOG_INT
, "... as %d\n", env
->v7m
.exception
);
7195 /* Function used to synchronize QEMU's AArch64 register set with AArch32
7196 * register set. This is necessary when switching between AArch32 and AArch64
7199 void aarch64_sync_32_to_64(CPUARMState
*env
)
7202 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7204 /* We can blanket copy R[0:7] to X[0:7] */
7205 for (i
= 0; i
< 8; i
++) {
7206 env
->xregs
[i
] = env
->regs
[i
];
7209 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7210 * Otherwise, they come from the banked user regs.
7212 if (mode
== ARM_CPU_MODE_FIQ
) {
7213 for (i
= 8; i
< 13; i
++) {
7214 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7217 for (i
= 8; i
< 13; i
++) {
7218 env
->xregs
[i
] = env
->regs
[i
];
7222 /* Registers x13-x23 are the various mode SP and FP registers. Registers
7223 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7224 * from the mode banked register.
7226 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7227 env
->xregs
[13] = env
->regs
[13];
7228 env
->xregs
[14] = env
->regs
[14];
7230 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7231 /* HYP is an exception in that it is copied from r14 */
7232 if (mode
== ARM_CPU_MODE_HYP
) {
7233 env
->xregs
[14] = env
->regs
[14];
7235 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
7239 if (mode
== ARM_CPU_MODE_HYP
) {
7240 env
->xregs
[15] = env
->regs
[13];
7242 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7245 if (mode
== ARM_CPU_MODE_IRQ
) {
7246 env
->xregs
[16] = env
->regs
[14];
7247 env
->xregs
[17] = env
->regs
[13];
7249 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
7250 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7253 if (mode
== ARM_CPU_MODE_SVC
) {
7254 env
->xregs
[18] = env
->regs
[14];
7255 env
->xregs
[19] = env
->regs
[13];
7257 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
7258 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7261 if (mode
== ARM_CPU_MODE_ABT
) {
7262 env
->xregs
[20] = env
->regs
[14];
7263 env
->xregs
[21] = env
->regs
[13];
7265 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
7266 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
7269 if (mode
== ARM_CPU_MODE_UND
) {
7270 env
->xregs
[22] = env
->regs
[14];
7271 env
->xregs
[23] = env
->regs
[13];
7273 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
7274 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
7277 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7278 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7279 * FIQ bank for r8-r14.
7281 if (mode
== ARM_CPU_MODE_FIQ
) {
7282 for (i
= 24; i
< 31; i
++) {
7283 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
7286 for (i
= 24; i
< 29; i
++) {
7287 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
7289 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
7290 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
7293 env
->pc
= env
->regs
[15];
7296 /* Function used to synchronize QEMU's AArch32 register set with AArch64
7297 * register set. This is necessary when switching between AArch32 and AArch64
7300 void aarch64_sync_64_to_32(CPUARMState
*env
)
7303 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7305 /* We can blanket copy X[0:7] to R[0:7] */
7306 for (i
= 0; i
< 8; i
++) {
7307 env
->regs
[i
] = env
->xregs
[i
];
7310 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
7311 * Otherwise, we copy x8-x12 into the banked user regs.
7313 if (mode
== ARM_CPU_MODE_FIQ
) {
7314 for (i
= 8; i
< 13; i
++) {
7315 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
7318 for (i
= 8; i
< 13; i
++) {
7319 env
->regs
[i
] = env
->xregs
[i
];
7323 /* Registers r13 & r14 depend on the current mode.
7324 * If we are in a given mode, we copy the corresponding x registers to r13
7325 * and r14. Otherwise, we copy the x register to the banked r13 and r14
7328 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7329 env
->regs
[13] = env
->xregs
[13];
7330 env
->regs
[14] = env
->xregs
[14];
7332 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
7334 /* HYP is an exception in that it does not have its own banked r14 but
7335 * shares the USR r14
7337 if (mode
== ARM_CPU_MODE_HYP
) {
7338 env
->regs
[14] = env
->xregs
[14];
7340 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
7344 if (mode
== ARM_CPU_MODE_HYP
) {
7345 env
->regs
[13] = env
->xregs
[15];
7347 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
7350 if (mode
== ARM_CPU_MODE_IRQ
) {
7351 env
->regs
[14] = env
->xregs
[16];
7352 env
->regs
[13] = env
->xregs
[17];
7354 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
7355 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
7358 if (mode
== ARM_CPU_MODE_SVC
) {
7359 env
->regs
[14] = env
->xregs
[18];
7360 env
->regs
[13] = env
->xregs
[19];
7362 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
7363 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
7366 if (mode
== ARM_CPU_MODE_ABT
) {
7367 env
->regs
[14] = env
->xregs
[20];
7368 env
->regs
[13] = env
->xregs
[21];
7370 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
7371 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
7374 if (mode
== ARM_CPU_MODE_UND
) {
7375 env
->regs
[14] = env
->xregs
[22];
7376 env
->regs
[13] = env
->xregs
[23];
7378 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
7379 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
7382 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7383 * mode, then we can copy to r8-r14. Otherwise, we copy to the
7384 * FIQ bank for r8-r14.
7386 if (mode
== ARM_CPU_MODE_FIQ
) {
7387 for (i
= 24; i
< 31; i
++) {
7388 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
7391 for (i
= 24; i
< 29; i
++) {
7392 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
7394 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
7395 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
7398 env
->regs
[15] = env
->pc
;
7401 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
7403 ARMCPU
*cpu
= ARM_CPU(cs
);
7404 CPUARMState
*env
= &cpu
->env
;
7411 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
7412 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
7414 case EC_BREAKPOINT_SAME_EL
:
7418 case EC_WATCHPOINT_SAME_EL
:
7424 case EC_VECTORCATCH
:
7433 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
7436 /* TODO: Vectored interrupt controller. */
7437 switch (cs
->exception_index
) {
7439 new_mode
= ARM_CPU_MODE_UND
;
7448 new_mode
= ARM_CPU_MODE_SVC
;
7451 /* The PC already points to the next instruction. */
7455 env
->exception
.fsr
= 2;
7456 /* Fall through to prefetch abort. */
7457 case EXCP_PREFETCH_ABORT
:
7458 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
7459 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
7460 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
7461 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
7462 new_mode
= ARM_CPU_MODE_ABT
;
7464 mask
= CPSR_A
| CPSR_I
;
7467 case EXCP_DATA_ABORT
:
7468 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
7469 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
7470 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
7472 (uint32_t)env
->exception
.vaddress
);
7473 new_mode
= ARM_CPU_MODE_ABT
;
7475 mask
= CPSR_A
| CPSR_I
;
7479 new_mode
= ARM_CPU_MODE_IRQ
;
7481 /* Disable IRQ and imprecise data aborts. */
7482 mask
= CPSR_A
| CPSR_I
;
7484 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
7485 /* IRQ routed to monitor mode */
7486 new_mode
= ARM_CPU_MODE_MON
;
7491 new_mode
= ARM_CPU_MODE_FIQ
;
7493 /* Disable FIQ, IRQ and imprecise data aborts. */
7494 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7495 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
7496 /* FIQ routed to monitor mode */
7497 new_mode
= ARM_CPU_MODE_MON
;
7502 new_mode
= ARM_CPU_MODE_IRQ
;
7504 /* Disable IRQ and imprecise data aborts. */
7505 mask
= CPSR_A
| CPSR_I
;
7509 new_mode
= ARM_CPU_MODE_FIQ
;
7511 /* Disable FIQ, IRQ and imprecise data aborts. */
7512 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7516 new_mode
= ARM_CPU_MODE_MON
;
7518 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7522 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7523 return; /* Never happens. Keep compiler happy. */
7526 if (new_mode
== ARM_CPU_MODE_MON
) {
7527 addr
+= env
->cp15
.mvbar
;
7528 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
7529 /* High vectors. When enabled, base address cannot be remapped. */
7532 /* ARM v7 architectures provide a vector base address register to remap
7533 * the interrupt vector table.
7534 * This register is only followed in non-monitor mode, and is banked.
7535 * Note: only bits 31:5 are valid.
7537 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
7540 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
7541 env
->cp15
.scr_el3
&= ~SCR_NS
;
7544 switch_mode (env
, new_mode
);
7545 /* For exceptions taken to AArch32 we must clear the SS bit in both
7546 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
7548 env
->uncached_cpsr
&= ~PSTATE_SS
;
7549 env
->spsr
= cpsr_read(env
);
7550 /* Clear IT bits. */
7551 env
->condexec_bits
= 0;
7552 /* Switch to the new mode, and to the correct instruction set. */
7553 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
7554 /* Set new mode endianness */
7555 env
->uncached_cpsr
&= ~CPSR_E
;
7556 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
7557 env
->uncached_cpsr
|= CPSR_E
;
7560 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
7561 * and we should just guard the thumb mode on V4 */
7562 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
7563 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
7565 env
->regs
[14] = env
->regs
[15] + offset
;
7566 env
->regs
[15] = addr
;
7569 /* Handle exception entry to a target EL which is using AArch64 */
7570 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
7572 ARMCPU
*cpu
= ARM_CPU(cs
);
7573 CPUARMState
*env
= &cpu
->env
;
7574 unsigned int new_el
= env
->exception
.target_el
;
7575 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
7576 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
7578 if (arm_current_el(env
) < new_el
) {
7579 /* Entry vector offset depends on whether the implemented EL
7580 * immediately lower than the target level is using AArch32 or AArch64
7586 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
7589 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
7592 is_aa64
= is_a64(env
);
7595 g_assert_not_reached();
7603 } else if (pstate_read(env
) & PSTATE_SP
) {
7607 switch (cs
->exception_index
) {
7608 case EXCP_PREFETCH_ABORT
:
7609 case EXCP_DATA_ABORT
:
7610 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
7611 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
7612 env
->cp15
.far_el
[new_el
]);
7620 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
7631 qemu_log_mask(CPU_LOG_INT
,
7632 "...handling as semihosting call 0x%" PRIx64
"\n",
7634 env
->xregs
[0] = do_arm_semihosting(env
);
7637 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7641 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
7642 aarch64_save_sp(env
, arm_current_el(env
));
7643 env
->elr_el
[new_el
] = env
->pc
;
7645 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
7646 env
->elr_el
[new_el
] = env
->regs
[15];
7648 aarch64_sync_32_to_64(env
);
7650 env
->condexec_bits
= 0;
7652 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
7653 env
->elr_el
[new_el
]);
7655 pstate_write(env
, PSTATE_DAIF
| new_mode
);
7657 aarch64_restore_sp(env
, new_el
);
7661 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
7662 new_el
, env
->pc
, pstate_read(env
));
7665 static inline bool check_for_semihosting(CPUState
*cs
)
7667 /* Check whether this exception is a semihosting call; if so
7668 * then handle it and return true; otherwise return false.
7670 ARMCPU
*cpu
= ARM_CPU(cs
);
7671 CPUARMState
*env
= &cpu
->env
;
7674 if (cs
->exception_index
== EXCP_SEMIHOST
) {
7675 /* This is always the 64-bit semihosting exception.
7676 * The "is this usermode" and "is semihosting enabled"
7677 * checks have been done at translate time.
7679 qemu_log_mask(CPU_LOG_INT
,
7680 "...handling as semihosting call 0x%" PRIx64
"\n",
7682 env
->xregs
[0] = do_arm_semihosting(env
);
7689 /* Only intercept calls from privileged modes, to provide some
7690 * semblance of security.
7692 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
7693 (!semihosting_enabled() ||
7694 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
7698 switch (cs
->exception_index
) {
7700 /* This is always a semihosting call; the "is this usermode"
7701 * and "is semihosting enabled" checks have been done at
7706 /* Check for semihosting interrupt. */
7708 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
7714 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
7716 if (imm
== 0x123456) {
7722 /* See if this is a semihosting syscall. */
7724 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
7736 qemu_log_mask(CPU_LOG_INT
,
7737 "...handling as semihosting call 0x%x\n",
7739 env
->regs
[0] = do_arm_semihosting(env
);
7744 /* Handle a CPU exception for A and R profile CPUs.
7745 * Do any appropriate logging, handle PSCI calls, and then hand off
7746 * to the AArch64-entry or AArch32-entry function depending on the
7747 * target exception level's register width.
7749 void arm_cpu_do_interrupt(CPUState
*cs
)
7751 ARMCPU
*cpu
= ARM_CPU(cs
);
7752 CPUARMState
*env
= &cpu
->env
;
7753 unsigned int new_el
= env
->exception
.target_el
;
7755 assert(!arm_feature(env
, ARM_FEATURE_M
));
7757 arm_log_exception(cs
->exception_index
);
7758 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
7760 if (qemu_loglevel_mask(CPU_LOG_INT
)
7761 && !excp_is_internal(cs
->exception_index
)) {
7762 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
7763 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
7764 env
->exception
.syndrome
);
7767 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
7768 arm_handle_psci_call(cpu
);
7769 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
7773 /* Semihosting semantics depend on the register width of the
7774 * code that caused the exception, not the target exception level,
7775 * so must be handled here.
7777 if (check_for_semihosting(cs
)) {
7781 assert(!excp_is_internal(cs
->exception_index
));
7782 if (arm_el_is_aa64(env
, new_el
)) {
7783 arm_cpu_do_interrupt_aarch64(cs
);
7785 arm_cpu_do_interrupt_aarch32(cs
);
7788 /* Hooks may change global state so BQL should be held, also the
7789 * BQL needs to be held for any modification of
7790 * cs->interrupt_request.
7792 g_assert(qemu_mutex_iothread_locked());
7794 arm_call_el_change_hook(cpu
);
7796 if (!kvm_enabled()) {
7797 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
7801 /* Return the exception level which controls this address translation regime */
7802 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7805 case ARMMMUIdx_S2NS
:
7806 case ARMMMUIdx_S1E2
:
7808 case ARMMMUIdx_S1E3
:
7810 case ARMMMUIdx_S1SE0
:
7811 return arm_el_is_aa64(env
, 3) ? 1 : 3;
7812 case ARMMMUIdx_S1SE1
:
7813 case ARMMMUIdx_S1NSE0
:
7814 case ARMMMUIdx_S1NSE1
:
7815 case ARMMMUIdx_MPriv
:
7816 case ARMMMUIdx_MNegPri
:
7817 case ARMMMUIdx_MUser
:
7818 case ARMMMUIdx_MSPriv
:
7819 case ARMMMUIdx_MSNegPri
:
7820 case ARMMMUIdx_MSUser
:
7823 g_assert_not_reached();
7827 /* Return the SCTLR value which controls this address translation regime */
7828 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7830 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
7833 /* Return true if the specified stage of address translation is disabled */
7834 static inline bool regime_translation_disabled(CPUARMState
*env
,
7837 if (arm_feature(env
, ARM_FEATURE_M
)) {
7838 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
7839 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
7840 case R_V7M_MPU_CTRL_ENABLE_MASK
:
7841 /* Enabled, but not for HardFault and NMI */
7842 return mmu_idx
== ARMMMUIdx_MNegPri
||
7843 mmu_idx
== ARMMMUIdx_MSNegPri
;
7844 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
7845 /* Enabled for all cases */
7849 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
7850 * we warned about that in armv7m_nvic.c when the guest set it.
7856 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7857 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
7859 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
7862 static inline bool regime_translation_big_endian(CPUARMState
*env
,
7865 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
7868 /* Return the TCR controlling this translation regime */
7869 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7871 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7872 return &env
->cp15
.vtcr_el2
;
7874 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
7877 /* Convert a possible stage1+2 MMU index into the appropriate
7880 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
7882 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
7883 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
7888 /* Returns TBI0 value for current regime el */
7889 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7894 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7895 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7897 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
7899 tcr
= regime_tcr(env
, mmu_idx
);
7900 el
= regime_el(env
, mmu_idx
);
7903 return extract64(tcr
->raw_tcr
, 20, 1);
7905 return extract64(tcr
->raw_tcr
, 37, 1);
7909 /* Returns TBI1 value for current regime el */
7910 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7915 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7916 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7918 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
7920 tcr
= regime_tcr(env
, mmu_idx
);
7921 el
= regime_el(env
, mmu_idx
);
7926 return extract64(tcr
->raw_tcr
, 38, 1);
7930 /* Return the TTBR associated with this translation regime */
7931 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7934 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7935 return env
->cp15
.vttbr_el2
;
7938 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
7940 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
7944 /* Return true if the translation regime is using LPAE format page tables */
7945 static inline bool regime_using_lpae_format(CPUARMState
*env
,
7948 int el
= regime_el(env
, mmu_idx
);
7949 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
7952 if (arm_feature(env
, ARM_FEATURE_LPAE
)
7953 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
7959 /* Returns true if the stage 1 translation regime is using LPAE format page
7960 * tables. Used when raising alignment exceptions, whose FSR changes depending
7961 * on whether the long or short descriptor format is in use. */
7962 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7964 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
7966 return regime_using_lpae_format(env
, mmu_idx
);
7969 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7972 case ARMMMUIdx_S1SE0
:
7973 case ARMMMUIdx_S1NSE0
:
7974 case ARMMMUIdx_MUser
:
7978 case ARMMMUIdx_S12NSE0
:
7979 case ARMMMUIdx_S12NSE1
:
7980 g_assert_not_reached();
7984 /* Translate section/page access permissions to page
7985 * R/W protection flags
7988 * @mmu_idx: MMU index indicating required translation regime
7989 * @ap: The 3-bit access permissions (AP[2:0])
7990 * @domain_prot: The 2-bit domain access permissions
7992 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7993 int ap
, int domain_prot
)
7995 bool is_user
= regime_is_user(env
, mmu_idx
);
7997 if (domain_prot
== 3) {
7998 return PAGE_READ
| PAGE_WRITE
;
8003 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8006 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8008 return is_user
? 0 : PAGE_READ
;
8015 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8020 return PAGE_READ
| PAGE_WRITE
;
8023 return PAGE_READ
| PAGE_WRITE
;
8024 case 4: /* Reserved. */
8027 return is_user
? 0 : PAGE_READ
;
8031 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8036 g_assert_not_reached();
8040 /* Translate section/page access permissions to page
8041 * R/W protection flags.
8043 * @ap: The 2-bit simple AP (AP[2:1])
8044 * @is_user: TRUE if accessing from PL0
8046 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8050 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8052 return PAGE_READ
| PAGE_WRITE
;
8054 return is_user
? 0 : PAGE_READ
;
8058 g_assert_not_reached();
8063 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8065 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8068 /* Translate S2 section/page access permissions to protection flags
8071 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8072 * @xn: XN (execute-never) bit
8074 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8085 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8092 /* Translate section/page access permissions to protection flags
8095 * @mmu_idx: MMU index indicating required translation regime
8096 * @is_aa64: TRUE if AArch64
8097 * @ap: The 2-bit simple AP (AP[2:1])
8098 * @ns: NS (non-secure) bit
8099 * @xn: XN (execute-never) bit
8100 * @pxn: PXN (privileged execute-never) bit
8102 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8103 int ap
, int ns
, int xn
, int pxn
)
8105 bool is_user
= regime_is_user(env
, mmu_idx
);
8106 int prot_rw
, user_rw
;
8110 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8112 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8116 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8119 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8123 /* TODO have_wxn should be replaced with
8124 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8125 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8126 * compatible processors have EL2, which is required for [U]WXN.
8128 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8131 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8135 switch (regime_el(env
, mmu_idx
)) {
8138 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8145 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8146 switch (regime_el(env
, mmu_idx
)) {
8150 xn
= xn
|| !(user_rw
& PAGE_READ
);
8154 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8156 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8157 (uwxn
&& (user_rw
& PAGE_WRITE
));
8167 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8170 return prot_rw
| PAGE_EXEC
;
8173 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8174 uint32_t *table
, uint32_t address
)
8176 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8177 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8179 if (address
& tcr
->mask
) {
8180 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8181 /* Translation table walk disabled for TTBR1 */
8184 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8186 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8187 /* Translation table walk disabled for TTBR0 */
8190 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
8192 *table
|= (address
>> 18) & 0x3ffc;
8196 /* Translate a S1 pagetable walk through S2 if needed. */
8197 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8198 hwaddr addr
, MemTxAttrs txattrs
,
8200 ARMMMUFaultInfo
*fi
)
8202 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
8203 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8204 target_ulong s2size
;
8209 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
8210 &txattrs
, &s2prot
, &s2size
, fsr
, fi
);
8222 /* All loads done in the course of a page table walk go through here.
8223 * TODO: rather than ignoring errors from physical memory reads (which
8224 * are external aborts in ARM terminology) we should propagate this
8225 * error out so that we can turn it into a Data Abort if this walk
8226 * was being done for a CPU load/store or an address translation instruction
8227 * (but not if it was for a debug access).
8229 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8230 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
8231 ARMMMUFaultInfo
*fi
)
8233 ARMCPU
*cpu
= ARM_CPU(cs
);
8234 CPUARMState
*env
= &cpu
->env
;
8235 MemTxAttrs attrs
= {};
8238 attrs
.secure
= is_secure
;
8239 as
= arm_addressspace(cs
, attrs
);
8240 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
8244 if (regime_translation_big_endian(env
, mmu_idx
)) {
8245 return address_space_ldl_be(as
, addr
, attrs
, NULL
);
8247 return address_space_ldl_le(as
, addr
, attrs
, NULL
);
8251 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8252 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
8253 ARMMMUFaultInfo
*fi
)
8255 ARMCPU
*cpu
= ARM_CPU(cs
);
8256 CPUARMState
*env
= &cpu
->env
;
8257 MemTxAttrs attrs
= {};
8260 attrs
.secure
= is_secure
;
8261 as
= arm_addressspace(cs
, attrs
);
8262 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
8266 if (regime_translation_big_endian(env
, mmu_idx
)) {
8267 return address_space_ldq_be(as
, addr
, attrs
, NULL
);
8269 return address_space_ldq_le(as
, addr
, attrs
, NULL
);
8273 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
8274 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8275 hwaddr
*phys_ptr
, int *prot
,
8276 target_ulong
*page_size
, uint32_t *fsr
,
8277 ARMMMUFaultInfo
*fi
)
8279 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8290 /* Pagetable walk. */
8291 /* Lookup l1 descriptor. */
8292 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8293 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8297 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8300 domain
= (desc
>> 5) & 0x0f;
8301 if (regime_el(env
, mmu_idx
) == 1) {
8302 dacr
= env
->cp15
.dacr_ns
;
8304 dacr
= env
->cp15
.dacr_s
;
8306 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8308 /* Section translation fault. */
8312 if (domain_prot
== 0 || domain_prot
== 2) {
8314 code
= 9; /* Section domain fault. */
8316 code
= 11; /* Page domain fault. */
8321 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8322 ap
= (desc
>> 10) & 3;
8324 *page_size
= 1024 * 1024;
8326 /* Lookup l2 entry. */
8328 /* Coarse pagetable. */
8329 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8331 /* Fine pagetable. */
8332 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
8334 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8337 case 0: /* Page translation fault. */
8340 case 1: /* 64k page. */
8341 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8342 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
8343 *page_size
= 0x10000;
8345 case 2: /* 4k page. */
8346 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8347 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
8348 *page_size
= 0x1000;
8350 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
8352 /* ARMv6/XScale extended small page format */
8353 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
8354 || arm_feature(env
, ARM_FEATURE_V6
)) {
8355 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8356 *page_size
= 0x1000;
8358 /* UNPREDICTABLE in ARMv5; we choose to take a
8359 * page translation fault.
8365 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
8368 ap
= (desc
>> 4) & 3;
8371 /* Never happens, but compiler isn't smart enough to tell. */
8376 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
8377 *prot
|= *prot
? PAGE_EXEC
: 0;
8378 if (!(*prot
& (1 << access_type
))) {
8379 /* Access permission fault. */
8382 *phys_ptr
= phys_addr
;
8385 *fsr
= code
| (domain
<< 4);
8389 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
8390 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8391 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
8392 target_ulong
*page_size
, uint32_t *fsr
,
8393 ARMMMUFaultInfo
*fi
)
8395 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8409 /* Pagetable walk. */
8410 /* Lookup l1 descriptor. */
8411 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8412 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8416 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8419 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
8420 /* Section translation fault, or attempt to use the encoding
8421 * which is Reserved on implementations without PXN.
8426 if ((type
== 1) || !(desc
& (1 << 18))) {
8427 /* Page or Section. */
8428 domain
= (desc
>> 5) & 0x0f;
8430 if (regime_el(env
, mmu_idx
) == 1) {
8431 dacr
= env
->cp15
.dacr_ns
;
8433 dacr
= env
->cp15
.dacr_s
;
8435 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8436 if (domain_prot
== 0 || domain_prot
== 2) {
8438 code
= 9; /* Section domain fault. */
8440 code
= 11; /* Page domain fault. */
8445 if (desc
& (1 << 18)) {
8447 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
8448 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
8449 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
8450 *page_size
= 0x1000000;
8453 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8454 *page_size
= 0x100000;
8456 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
8457 xn
= desc
& (1 << 4);
8460 ns
= extract32(desc
, 19, 1);
8462 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
8463 pxn
= (desc
>> 2) & 1;
8465 ns
= extract32(desc
, 3, 1);
8466 /* Lookup l2 entry. */
8467 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8468 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8470 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
8472 case 0: /* Page translation fault. */
8475 case 1: /* 64k page. */
8476 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8477 xn
= desc
& (1 << 15);
8478 *page_size
= 0x10000;
8480 case 2: case 3: /* 4k page. */
8481 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8483 *page_size
= 0x1000;
8486 /* Never happens, but compiler isn't smart enough to tell. */
8491 if (domain_prot
== 3) {
8492 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8494 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
8497 if (xn
&& access_type
== MMU_INST_FETCH
)
8500 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
8501 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
8502 /* The simplified model uses AP[0] as an access control bit. */
8503 if ((ap
& 1) == 0) {
8504 /* Access flag fault. */
8505 code
= (code
== 15) ? 6 : 3;
8508 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
8510 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
8515 if (!(*prot
& (1 << access_type
))) {
8516 /* Access permission fault. */
8521 /* The NS bit will (as required by the architecture) have no effect if
8522 * the CPU doesn't support TZ or this is a non-secure translation
8523 * regime, because the attribute will already be non-secure.
8525 attrs
->secure
= false;
8527 *phys_ptr
= phys_addr
;
8530 *fsr
= code
| (domain
<< 4);
8534 /* Fault type for long-descriptor MMU fault reporting; this corresponds
8535 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
8538 translation_fault
= 1,
8540 permission_fault
= 3,
8544 * check_s2_mmu_setup
8546 * @is_aa64: True if the translation regime is in AArch64 state
8547 * @startlevel: Suggested starting level
8548 * @inputsize: Bitsize of IPAs
8549 * @stride: Page-table stride (See the ARM ARM)
8551 * Returns true if the suggested S2 translation parameters are OK and
8554 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
8555 int inputsize
, int stride
)
8557 const int grainsize
= stride
+ 3;
8560 /* Negative levels are never allowed. */
8565 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
8566 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
8571 CPUARMState
*env
= &cpu
->env
;
8572 unsigned int pamax
= arm_pamax(cpu
);
8575 case 13: /* 64KB Pages. */
8576 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
8580 case 11: /* 16KB Pages. */
8581 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
8585 case 9: /* 4KB Pages. */
8586 if (level
== 0 && pamax
<= 42) {
8591 g_assert_not_reached();
8594 /* Inputsize checks. */
8595 if (inputsize
> pamax
&&
8596 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
8597 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
8601 /* AArch32 only supports 4KB pages. Assert on that. */
8602 assert(stride
== 9);
8611 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
8612 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8613 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
8614 target_ulong
*page_size_ptr
, uint32_t *fsr
,
8615 ARMMMUFaultInfo
*fi
)
8617 ARMCPU
*cpu
= arm_env_get_cpu(env
);
8618 CPUState
*cs
= CPU(cpu
);
8619 /* Read an LPAE long-descriptor translation table. */
8620 MMUFaultType fault_type
= translation_fault
;
8627 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
8628 uint32_t tableattrs
;
8629 target_ulong page_size
;
8635 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8636 int ap
, ns
, xn
, pxn
;
8637 uint32_t el
= regime_el(env
, mmu_idx
);
8638 bool ttbr1_valid
= true;
8639 uint64_t descaddrmask
;
8640 bool aarch64
= arm_el_is_aa64(env
, el
);
8643 * This code does not handle the different format TCR for VTCR_EL2.
8644 * This code also does not support shareability levels.
8645 * Attribute and permission bit handling should also be checked when adding
8646 * support for those page table walks.
8652 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8653 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
8656 if (extract64(address
, 55, 1)) {
8657 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
8659 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
8664 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
8668 ttbr1_valid
= false;
8673 /* There is no TTBR1 for EL2 */
8675 ttbr1_valid
= false;
8679 /* Determine whether this address is in the region controlled by
8680 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
8681 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
8682 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
8685 /* AArch64 translation. */
8686 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
8687 t0sz
= MIN(t0sz
, 39);
8688 t0sz
= MAX(t0sz
, 16);
8689 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8690 /* AArch32 stage 1 translation. */
8691 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
8693 /* AArch32 stage 2 translation. */
8694 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
8695 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
8696 /* Address size is 40-bit for a stage 2 translation,
8697 * and t0sz can be negative (from -8 to 7),
8698 * so we need to adjust it to use the TTBR selecting logic below.
8701 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
8703 /* If the sign-extend bit is not the same as t0sz[3], the result
8704 * is unpredictable. Flag this as a guest error. */
8706 qemu_log_mask(LOG_GUEST_ERROR
,
8707 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
8710 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
8712 t1sz
= MIN(t1sz
, 39);
8713 t1sz
= MAX(t1sz
, 16);
8715 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
8716 /* there is a ttbr0 region and we are in it (high bits all zero) */
8718 } else if (ttbr1_valid
&& t1sz
&&
8719 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
8720 /* there is a ttbr1 region and we are in it (high bits all one) */
8723 /* ttbr0 region is "everything not in the ttbr1 region" */
8725 } else if (!t1sz
&& ttbr1_valid
) {
8726 /* ttbr1 region is "everything not in the ttbr0 region" */
8729 /* in the gap between the two regions, this is a Translation fault */
8730 fault_type
= translation_fault
;
8734 /* Note that QEMU ignores shareability and cacheability attributes,
8735 * so we don't need to do anything with the SH, ORGN, IRGN fields
8736 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
8737 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
8738 * implement any ASID-like capability so we can ignore it (instead
8739 * we will always flush the TLB any time the ASID is changed).
8741 if (ttbr_select
== 0) {
8742 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
8744 epd
= extract32(tcr
->raw_tcr
, 7, 1);
8746 inputsize
= addrsize
- t0sz
;
8748 tg
= extract32(tcr
->raw_tcr
, 14, 2);
8749 if (tg
== 1) { /* 64KB pages */
8752 if (tg
== 2) { /* 16KB pages */
8756 /* We should only be here if TTBR1 is valid */
8757 assert(ttbr1_valid
);
8759 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
8760 epd
= extract32(tcr
->raw_tcr
, 23, 1);
8761 inputsize
= addrsize
- t1sz
;
8763 tg
= extract32(tcr
->raw_tcr
, 30, 2);
8764 if (tg
== 3) { /* 64KB pages */
8767 if (tg
== 1) { /* 16KB pages */
8772 /* Here we should have set up all the parameters for the translation:
8773 * inputsize, ttbr, epd, stride, tbi
8777 /* Translation table walk disabled => Translation fault on TLB miss
8778 * Note: This is always 0 on 64-bit EL2 and EL3.
8783 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8784 /* The starting level depends on the virtual address size (which can
8785 * be up to 48 bits) and the translation granule size. It indicates
8786 * the number of strides (stride bits at a time) needed to
8787 * consume the bits of the input address. In the pseudocode this is:
8788 * level = 4 - RoundUp((inputsize - grainsize) / stride)
8789 * where their 'inputsize' is our 'inputsize', 'grainsize' is
8790 * our 'stride + 3' and 'stride' is our 'stride'.
8791 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
8792 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
8793 * = 4 - (inputsize - 4) / stride;
8795 level
= 4 - (inputsize
- 4) / stride
;
8797 /* For stage 2 translations the starting level is specified by the
8798 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
8800 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
8801 uint32_t startlevel
;
8804 if (!aarch64
|| stride
== 9) {
8805 /* AArch32 or 4KB pages */
8806 startlevel
= 2 - sl0
;
8808 /* 16KB or 64KB pages */
8809 startlevel
= 3 - sl0
;
8812 /* Check that the starting level is valid. */
8813 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
8816 fault_type
= translation_fault
;
8822 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
8823 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
8825 /* Now we can extract the actual base address from the TTBR */
8826 descaddr
= extract64(ttbr
, 0, 48);
8827 descaddr
&= ~indexmask
;
8829 /* The address field in the descriptor goes up to bit 39 for ARMv7
8830 * but up to bit 47 for ARMv8, but we use the descaddrmask
8831 * up to bit 39 for AArch32, because we don't need other bits in that case
8832 * to construct next descriptor address (anyway they should be all zeroes).
8834 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
8835 ~indexmask_grainsize
;
8837 /* Secure accesses start with the page table in secure memory and
8838 * can be downgraded to non-secure at any step. Non-secure accesses
8839 * remain non-secure. We implement this by just ORing in the NSTable/NS
8840 * bits at each step.
8842 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
8844 uint64_t descriptor
;
8847 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
8849 nstable
= extract32(tableattrs
, 4, 1);
8850 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fsr
, fi
);
8855 if (!(descriptor
& 1) ||
8856 (!(descriptor
& 2) && (level
== 3))) {
8857 /* Invalid, or the Reserved level 3 encoding */
8860 descaddr
= descriptor
& descaddrmask
;
8862 if ((descriptor
& 2) && (level
< 3)) {
8863 /* Table entry. The top five bits are attributes which may
8864 * propagate down through lower levels of the table (and
8865 * which are all arranged so that 0 means "no effect", so
8866 * we can gather them up by ORing in the bits at each level).
8868 tableattrs
|= extract64(descriptor
, 59, 5);
8870 indexmask
= indexmask_grainsize
;
8873 /* Block entry at level 1 or 2, or page entry at level 3.
8874 * These are basically the same thing, although the number
8875 * of bits we pull in from the vaddr varies.
8877 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
8878 descaddr
|= (address
& (page_size
- 1));
8879 /* Extract attributes from the descriptor */
8880 attrs
= extract64(descriptor
, 2, 10)
8881 | (extract64(descriptor
, 52, 12) << 10);
8883 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8884 /* Stage 2 table descriptors do not include any attribute fields */
8887 /* Merge in attributes from table descriptors */
8888 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
8889 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
8890 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
8891 * means "force PL1 access only", which means forcing AP[1] to 0.
8893 if (extract32(tableattrs
, 2, 1)) {
8896 attrs
|= nstable
<< 3; /* NS */
8899 /* Here descaddr is the final physical address, and attributes
8902 fault_type
= access_fault
;
8903 if ((attrs
& (1 << 8)) == 0) {
8908 ap
= extract32(attrs
, 4, 2);
8909 xn
= extract32(attrs
, 12, 1);
8911 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8913 *prot
= get_S2prot(env
, ap
, xn
);
8915 ns
= extract32(attrs
, 3, 1);
8916 pxn
= extract32(attrs
, 11, 1);
8917 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
8920 fault_type
= permission_fault
;
8921 if (!(*prot
& (1 << access_type
))) {
8926 /* The NS bit will (as required by the architecture) have no effect if
8927 * the CPU doesn't support TZ or this is a non-secure translation
8928 * regime, because the attribute will already be non-secure.
8930 txattrs
->secure
= false;
8932 *phys_ptr
= descaddr
;
8933 *page_size_ptr
= page_size
;
8937 /* Long-descriptor format IFSR/DFSR value */
8938 *fsr
= (1 << 9) | (fault_type
<< 2) | level
;
8939 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
8940 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
8944 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
8946 int32_t address
, int *prot
)
8948 if (!arm_feature(env
, ARM_FEATURE_M
)) {
8949 *prot
= PAGE_READ
| PAGE_WRITE
;
8951 case 0xF0000000 ... 0xFFFFFFFF:
8952 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
8953 /* hivecs execing is ok */
8957 case 0x00000000 ... 0x7FFFFFFF:
8962 /* Default system address map for M profile cores.
8963 * The architecture specifies which regions are execute-never;
8964 * at the MPU level no other checks are defined.
8967 case 0x00000000 ... 0x1fffffff: /* ROM */
8968 case 0x20000000 ... 0x3fffffff: /* SRAM */
8969 case 0x60000000 ... 0x7fffffff: /* RAM */
8970 case 0x80000000 ... 0x9fffffff: /* RAM */
8971 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8973 case 0x40000000 ... 0x5fffffff: /* Peripheral */
8974 case 0xa0000000 ... 0xbfffffff: /* Device */
8975 case 0xc0000000 ... 0xdfffffff: /* Device */
8976 case 0xe0000000 ... 0xffffffff: /* System */
8977 *prot
= PAGE_READ
| PAGE_WRITE
;
8980 g_assert_not_reached();
8985 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
8986 ARMMMUIdx mmu_idx
, bool is_user
)
8988 /* Return true if we should use the default memory map as a
8989 * "background" region if there are no hits against any MPU regions.
8991 CPUARMState
*env
= &cpu
->env
;
8997 if (arm_feature(env
, ARM_FEATURE_M
)) {
8998 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
8999 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9001 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9005 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9007 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9008 return arm_feature(env
, ARM_FEATURE_M
) &&
9009 extract32(address
, 20, 12) == 0xe00;
9012 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9014 /* True if address is in the M profile system region
9015 * 0xe0000000 - 0xffffffff
9017 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9020 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9021 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9022 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
9024 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9026 bool is_user
= regime_is_user(env
, mmu_idx
);
9028 *phys_ptr
= address
;
9031 if (regime_translation_disabled(env
, mmu_idx
) ||
9032 m_is_ppb_region(env
, address
)) {
9033 /* MPU disabled or M profile PPB access: use default memory map.
9034 * The other case which uses the default memory map in the
9035 * v7M ARM ARM pseudocode is exception vector reads from the vector
9036 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9037 * which always does a direct read using address_space_ldl(), rather
9038 * than going via this function, so we don't need to check that here.
9040 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9041 } else { /* MPU enabled */
9042 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9044 uint32_t base
= env
->pmsav7
.drbar
[n
];
9045 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
9049 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
9054 qemu_log_mask(LOG_GUEST_ERROR
,
9055 "DRSR[%d]: Rsize field cannot be 0\n", n
);
9059 rmask
= (1ull << rsize
) - 1;
9062 qemu_log_mask(LOG_GUEST_ERROR
,
9063 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
9064 "to DRSR region size, mask = 0x%" PRIx32
"\n",
9069 if (address
< base
|| address
> base
+ rmask
) {
9073 /* Region matched */
9075 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
9077 uint32_t srdis_mask
;
9079 rsize
-= 3; /* sub region size (power of 2) */
9080 snd
= ((address
- base
) >> rsize
) & 0x7;
9081 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
9083 srdis_mask
= srdis
? 0x3 : 0x0;
9084 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
9085 /* This will check in groups of 2, 4 and then 8, whether
9086 * the subregion bits are consistent. rsize is incremented
9087 * back up to give the region size, considering consistent
9088 * adjacent subregions as one region. Stop testing if rsize
9089 * is already big enough for an entire QEMU page.
9091 int snd_rounded
= snd
& ~(i
- 1);
9092 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
9093 snd_rounded
+ 8, i
);
9094 if (srdis_mask
^ srdis_multi
) {
9097 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
9101 if (rsize
< TARGET_PAGE_BITS
) {
9102 qemu_log_mask(LOG_UNIMP
,
9103 "DRSR[%d]: No support for MPU (sub)region "
9104 "alignment of %" PRIu32
" bits. Minimum is %d\n",
9105 n
, rsize
, TARGET_PAGE_BITS
);
9114 if (n
== -1) { /* no hits */
9115 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9116 /* background fault */
9120 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9121 } else { /* a MPU hit! */
9122 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
9123 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
9125 if (m_is_system_region(env
, address
)) {
9126 /* System space is always execute never */
9130 if (is_user
) { /* User mode AP bit decoding */
9135 break; /* no access */
9137 *prot
|= PAGE_WRITE
;
9141 *prot
|= PAGE_READ
| PAGE_EXEC
;
9144 qemu_log_mask(LOG_GUEST_ERROR
,
9145 "DRACR[%d]: Bad value for AP bits: 0x%"
9146 PRIx32
"\n", n
, ap
);
9148 } else { /* Priv. mode AP bits decoding */
9151 break; /* no access */
9155 *prot
|= PAGE_WRITE
;
9159 *prot
|= PAGE_READ
| PAGE_EXEC
;
9162 qemu_log_mask(LOG_GUEST_ERROR
,
9163 "DRACR[%d]: Bad value for AP bits: 0x%"
9164 PRIx32
"\n", n
, ap
);
9170 *prot
&= ~PAGE_EXEC
;
9175 *fsr
= 0x00d; /* Permission fault */
9176 return !(*prot
& (1 << access_type
));
9179 static bool v8m_is_sau_exempt(CPUARMState
*env
,
9180 uint32_t address
, MMUAccessType access_type
)
9182 /* The architecture specifies that certain address ranges are
9183 * exempt from v8M SAU/IDAU checks.
9186 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
9187 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
9188 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
9189 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
9190 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
9191 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
9194 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
9195 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9196 V8M_SAttributes
*sattrs
)
9198 /* Look up the security attributes for this address. Compare the
9199 * pseudocode SecurityCheck() function.
9200 * We assume the caller has zero-initialized *sattrs.
9202 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9205 /* TODO: implement IDAU */
9207 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
9208 /* 0xf0000000..0xffffffff is always S for insn fetches */
9212 if (v8m_is_sau_exempt(env
, address
, access_type
)) {
9213 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
9217 switch (env
->sau
.ctrl
& 3) {
9218 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
9220 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
9223 default: /* SAU.ENABLE == 1 */
9224 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
9225 if (env
->sau
.rlar
[r
] & 1) {
9226 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
9227 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
9229 if (base
<= address
&& limit
>= address
) {
9230 if (sattrs
->srvalid
) {
9231 /* If we hit in more than one region then we must report
9232 * as Secure, not NS-Callable, with no valid region
9236 sattrs
->nsc
= false;
9237 sattrs
->sregion
= 0;
9238 sattrs
->srvalid
= false;
9241 if (env
->sau
.rlar
[r
] & 2) {
9246 sattrs
->srvalid
= true;
9247 sattrs
->sregion
= r
;
9253 /* TODO when we support the IDAU then it may override the result here */
9258 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
9259 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9260 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
9261 int *prot
, uint32_t *fsr
)
9263 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9264 bool is_user
= regime_is_user(env
, mmu_idx
);
9265 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
9267 int matchregion
= -1;
9269 V8M_SAttributes sattrs
= {};
9271 *phys_ptr
= address
;
9274 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
9275 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
9276 if (access_type
== MMU_INST_FETCH
) {
9277 /* Instruction fetches always use the MMU bank and the
9278 * transaction attribute determined by the fetch address,
9279 * regardless of CPU state. This is painful for QEMU
9280 * to handle, because it would mean we need to encode
9281 * into the mmu_idx not just the (user, negpri) information
9282 * for the current security state but also that for the
9283 * other security state, which would balloon the number
9284 * of mmu_idx values needed alarmingly.
9285 * Fortunately we can avoid this because it's not actually
9286 * possible to arbitrarily execute code from memory with
9287 * the wrong security attribute: it will always generate
9288 * an exception of some kind or another, apart from the
9289 * special case of an NS CPU executing an SG instruction
9290 * in S&NSC memory. So we always just fail the translation
9291 * here and sort things out in the exception handler
9292 * (including possibly emulating an SG instruction).
9294 if (sattrs
.ns
!= !secure
) {
9295 *fsr
= sattrs
.nsc
? M_FAKE_FSR_NSC_EXEC
: M_FAKE_FSR_SFAULT
;
9299 /* For data accesses we always use the MMU bank indicated
9300 * by the current CPU state, but the security attributes
9301 * might downgrade a secure access to nonsecure.
9304 txattrs
->secure
= false;
9305 } else if (!secure
) {
9306 /* NS access to S memory must fault.
9307 * Architecturally we should first check whether the
9308 * MPU information for this address indicates that we
9309 * are doing an unaligned access to Device memory, which
9310 * should generate a UsageFault instead. QEMU does not
9311 * currently check for that kind of unaligned access though.
9312 * If we added it we would need to do so as a special case
9313 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
9315 *fsr
= M_FAKE_FSR_SFAULT
;
9321 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
9322 * was an exception vector read from the vector table (which is always
9323 * done using the default system address map), because those accesses
9324 * are done in arm_v7m_load_vector(), which always does a direct
9325 * read using address_space_ldl(), rather than going via this function.
9327 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
9329 } else if (m_is_ppb_region(env
, address
)) {
9331 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9334 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9336 /* Note that the base address is bits [31:5] from the register
9337 * with bits [4:0] all zeroes, but the limit address is bits
9338 * [31:5] from the register with bits [4:0] all ones.
9340 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
9341 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
9343 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
9344 /* Region disabled */
9348 if (address
< base
|| address
> limit
) {
9353 /* Multiple regions match -- always a failure (unlike
9354 * PMSAv7 where highest-numbered-region wins)
9356 *fsr
= 0x00d; /* permission fault */
9363 if (base
& ~TARGET_PAGE_MASK
) {
9364 qemu_log_mask(LOG_UNIMP
,
9365 "MPU_RBAR[%d]: No support for MPU region base"
9366 "address of 0x%" PRIx32
". Minimum alignment is "
9368 n
, base
, TARGET_PAGE_BITS
);
9371 if ((limit
+ 1) & ~TARGET_PAGE_MASK
) {
9372 qemu_log_mask(LOG_UNIMP
,
9373 "MPU_RBAR[%d]: No support for MPU region limit"
9374 "address of 0x%" PRIx32
". Minimum alignment is "
9376 n
, limit
, TARGET_PAGE_BITS
);
9383 /* background fault */
9388 if (matchregion
== -1) {
9389 /* hit using the background region */
9390 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9392 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
9393 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
9395 if (m_is_system_region(env
, address
)) {
9396 /* System space is always execute never */
9400 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
9404 /* We don't need to look the attribute up in the MAIR0/MAIR1
9405 * registers because that only tells us about cacheability.
9409 *fsr
= 0x00d; /* Permission fault */
9410 return !(*prot
& (1 << access_type
));
9413 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
9414 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9415 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
9420 bool is_user
= regime_is_user(env
, mmu_idx
);
9422 if (regime_translation_disabled(env
, mmu_idx
)) {
9424 *phys_ptr
= address
;
9425 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9429 *phys_ptr
= address
;
9430 for (n
= 7; n
>= 0; n
--) {
9431 base
= env
->cp15
.c6_region
[n
];
9432 if ((base
& 1) == 0) {
9435 mask
= 1 << ((base
>> 1) & 0x1f);
9436 /* Keep this shift separate from the above to avoid an
9437 (undefined) << 32. */
9438 mask
= (mask
<< 1) - 1;
9439 if (((base
^ address
) & ~mask
) == 0) {
9448 if (access_type
== MMU_INST_FETCH
) {
9449 mask
= env
->cp15
.pmsav5_insn_ap
;
9451 mask
= env
->cp15
.pmsav5_data_ap
;
9453 mask
= (mask
>> (n
* 4)) & 0xf;
9463 *prot
= PAGE_READ
| PAGE_WRITE
;
9468 *prot
|= PAGE_WRITE
;
9472 *prot
= PAGE_READ
| PAGE_WRITE
;
9485 /* Bad permission. */
9493 /* get_phys_addr - get the physical address for this virtual address
9495 * Find the physical address corresponding to the given virtual address,
9496 * by doing a translation table walk on MMU based systems or using the
9497 * MPU state on MPU based systems.
9499 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
9500 * prot and page_size may not be filled in, and the populated fsr value provides
9501 * information on why the translation aborted, in the format of a
9502 * DFSR/IFSR fault register, with the following caveats:
9503 * * we honour the short vs long DFSR format differences.
9504 * * the WnR bit is never set (the caller must do this).
9505 * * for PSMAv5 based systems we don't bother to return a full FSR format
9509 * @address: virtual address to get physical address for
9510 * @access_type: 0 for read, 1 for write, 2 for execute
9511 * @mmu_idx: MMU index indicating required translation regime
9512 * @phys_ptr: set to the physical address corresponding to the virtual address
9513 * @attrs: set to the memory transaction attributes to use
9514 * @prot: set to the permissions for the page containing phys_ptr
9515 * @page_size: set to the size of the page containing phys_ptr
9516 * @fsr: set to the DFSR/IFSR value on failure
9518 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
9519 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9520 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
9521 target_ulong
*page_size
, uint32_t *fsr
,
9522 ARMMMUFaultInfo
*fi
)
9524 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
9525 /* Call ourselves recursively to do the stage 1 and then stage 2
9528 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
9533 ret
= get_phys_addr(env
, address
, access_type
,
9534 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
9535 prot
, page_size
, fsr
, fi
);
9537 /* If S1 fails or S2 is disabled, return early. */
9538 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
9543 /* S1 is done. Now do S2 translation. */
9544 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
9545 phys_ptr
, attrs
, &s2_prot
,
9546 page_size
, fsr
, fi
);
9548 /* Combine the S1 and S2 perms. */
9553 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
9555 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
9559 /* The page table entries may downgrade secure to non-secure, but
9560 * cannot upgrade an non-secure translation regime's attributes
9563 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
9564 attrs
->user
= regime_is_user(env
, mmu_idx
);
9566 /* Fast Context Switch Extension. This doesn't exist at all in v8.
9567 * In v7 and earlier it affects all stage 1 translations.
9569 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
9570 && !arm_feature(env
, ARM_FEATURE_V8
)) {
9571 if (regime_el(env
, mmu_idx
) == 3) {
9572 address
+= env
->cp15
.fcseidr_s
;
9574 address
+= env
->cp15
.fcseidr_ns
;
9578 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9580 *page_size
= TARGET_PAGE_SIZE
;
9582 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9584 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
9585 phys_ptr
, attrs
, prot
, fsr
);
9586 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9588 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
9589 phys_ptr
, prot
, fsr
);
9592 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
9593 phys_ptr
, prot
, fsr
);
9595 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
9596 " mmu_idx %u -> %s (prot %c%c%c)\n",
9597 access_type
== MMU_DATA_LOAD
? "reading" :
9598 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
9599 (uint32_t)address
, mmu_idx
,
9600 ret
? "Miss" : "Hit",
9601 *prot
& PAGE_READ
? 'r' : '-',
9602 *prot
& PAGE_WRITE
? 'w' : '-',
9603 *prot
& PAGE_EXEC
? 'x' : '-');
9608 /* Definitely a real MMU, not an MPU */
9610 if (regime_translation_disabled(env
, mmu_idx
)) {
9612 *phys_ptr
= address
;
9613 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9614 *page_size
= TARGET_PAGE_SIZE
;
9618 if (regime_using_lpae_format(env
, mmu_idx
)) {
9619 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
9620 attrs
, prot
, page_size
, fsr
, fi
);
9621 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
9622 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
9623 attrs
, prot
, page_size
, fsr
, fi
);
9625 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
9626 prot
, page_size
, fsr
, fi
);
9630 /* Walk the page table and (if the mapping exists) add the page
9631 * to the TLB. Return false on success, or true on failure. Populate
9632 * fsr with ARM DFSR/IFSR fault register format value on failure.
9634 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
9635 MMUAccessType access_type
, int mmu_idx
, uint32_t *fsr
,
9636 ARMMMUFaultInfo
*fi
)
9638 ARMCPU
*cpu
= ARM_CPU(cs
);
9639 CPUARMState
*env
= &cpu
->env
;
9641 target_ulong page_size
;
9644 MemTxAttrs attrs
= {};
9646 ret
= get_phys_addr(env
, address
, access_type
,
9647 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
9648 &attrs
, &prot
, &page_size
, fsr
, fi
);
9650 /* Map a single [sub]page. */
9651 phys_addr
&= TARGET_PAGE_MASK
;
9652 address
&= TARGET_PAGE_MASK
;
9653 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
9654 prot
, mmu_idx
, page_size
);
9661 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
9664 ARMCPU
*cpu
= ARM_CPU(cs
);
9665 CPUARMState
*env
= &cpu
->env
;
9667 target_ulong page_size
;
9671 ARMMMUFaultInfo fi
= {};
9672 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
9674 *attrs
= (MemTxAttrs
) {};
9676 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
9677 attrs
, &prot
, &page_size
, &fsr
, &fi
);
9685 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
9688 unsigned el
= arm_current_el(env
);
9690 /* First handle registers which unprivileged can read */
9693 case 0 ... 7: /* xPSR sub-fields */
9695 if ((reg
& 1) && el
) {
9696 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
9699 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
9701 /* EPSR reads as zero */
9702 return xpsr_read(env
) & mask
;
9704 case 20: /* CONTROL */
9705 return env
->v7m
.control
[env
->v7m
.secure
];
9706 case 0x94: /* CONTROL_NS */
9707 /* We have to handle this here because unprivileged Secure code
9708 * can read the NS CONTROL register.
9710 if (!env
->v7m
.secure
) {
9713 return env
->v7m
.control
[M_REG_NS
];
9717 return 0; /* unprivileged reads others as zero */
9720 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
9722 case 0x88: /* MSP_NS */
9723 if (!env
->v7m
.secure
) {
9726 return env
->v7m
.other_ss_msp
;
9727 case 0x89: /* PSP_NS */
9728 if (!env
->v7m
.secure
) {
9731 return env
->v7m
.other_ss_psp
;
9732 case 0x90: /* PRIMASK_NS */
9733 if (!env
->v7m
.secure
) {
9736 return env
->v7m
.primask
[M_REG_NS
];
9737 case 0x91: /* BASEPRI_NS */
9738 if (!env
->v7m
.secure
) {
9741 return env
->v7m
.basepri
[M_REG_NS
];
9742 case 0x93: /* FAULTMASK_NS */
9743 if (!env
->v7m
.secure
) {
9746 return env
->v7m
.faultmask
[M_REG_NS
];
9747 case 0x98: /* SP_NS */
9749 /* This gives the non-secure SP selected based on whether we're
9750 * currently in handler mode or not, using the NS CONTROL.SPSEL.
9752 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
9754 if (!env
->v7m
.secure
) {
9757 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
9758 return env
->v7m
.other_ss_psp
;
9760 return env
->v7m
.other_ss_msp
;
9770 return (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) ?
9771 env
->v7m
.other_sp
: env
->regs
[13];
9773 return (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) ?
9774 env
->regs
[13] : env
->v7m
.other_sp
;
9775 case 16: /* PRIMASK */
9776 return env
->v7m
.primask
[env
->v7m
.secure
];
9777 case 17: /* BASEPRI */
9778 case 18: /* BASEPRI_MAX */
9779 return env
->v7m
.basepri
[env
->v7m
.secure
];
9780 case 19: /* FAULTMASK */
9781 return env
->v7m
.faultmask
[env
->v7m
.secure
];
9783 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
9784 " register %d\n", reg
);
9789 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
9791 /* We're passed bits [11..0] of the instruction; extract
9792 * SYSm and the mask bits.
9793 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
9794 * we choose to treat them as if the mask bits were valid.
9795 * NB that the pseudocode 'mask' variable is bits [11..10],
9796 * whereas ours is [11..8].
9798 uint32_t mask
= extract32(maskreg
, 8, 4);
9799 uint32_t reg
= extract32(maskreg
, 0, 8);
9801 if (arm_current_el(env
) == 0 && reg
> 7) {
9802 /* only xPSR sub-fields may be written by unprivileged */
9806 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
9808 case 0x88: /* MSP_NS */
9809 if (!env
->v7m
.secure
) {
9812 env
->v7m
.other_ss_msp
= val
;
9814 case 0x89: /* PSP_NS */
9815 if (!env
->v7m
.secure
) {
9818 env
->v7m
.other_ss_psp
= val
;
9820 case 0x90: /* PRIMASK_NS */
9821 if (!env
->v7m
.secure
) {
9824 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
9826 case 0x91: /* BASEPRI_NS */
9827 if (!env
->v7m
.secure
) {
9830 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
9832 case 0x93: /* FAULTMASK_NS */
9833 if (!env
->v7m
.secure
) {
9836 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
9838 case 0x98: /* SP_NS */
9840 /* This gives the non-secure SP selected based on whether we're
9841 * currently in handler mode or not, using the NS CONTROL.SPSEL.
9843 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
9845 if (!env
->v7m
.secure
) {
9848 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
9849 env
->v7m
.other_ss_psp
= val
;
9851 env
->v7m
.other_ss_msp
= val
;
9861 case 0 ... 7: /* xPSR sub-fields */
9862 /* only APSR is actually writable */
9864 uint32_t apsrmask
= 0;
9867 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
9869 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
9870 apsrmask
|= XPSR_GE
;
9872 xpsr_write(env
, val
, apsrmask
);
9876 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
9877 env
->v7m
.other_sp
= val
;
9879 env
->regs
[13] = val
;
9883 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
9884 env
->regs
[13] = val
;
9886 env
->v7m
.other_sp
= val
;
9889 case 16: /* PRIMASK */
9890 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
9892 case 17: /* BASEPRI */
9893 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
9895 case 18: /* BASEPRI_MAX */
9897 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
9898 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
9899 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
9902 case 19: /* FAULTMASK */
9903 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
9905 case 20: /* CONTROL */
9906 /* Writing to the SPSEL bit only has an effect if we are in
9907 * thread mode; other bits can be updated by any privileged code.
9908 * write_v7m_control_spsel() deals with updating the SPSEL bit in
9909 * env->v7m.control, so we only need update the others.
9911 if (!arm_v7m_is_handler_mode(env
)) {
9912 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
9914 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
9915 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
9918 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
9919 " register %d\n", reg
);
9926 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
9928 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
9929 * Note that we do not implement the (architecturally mandated)
9930 * alignment fault for attempts to use this on Device memory
9931 * (which matches the usual QEMU behaviour of not implementing either
9932 * alignment faults or any memory attribute handling).
9935 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9936 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
9937 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
9939 #ifndef CONFIG_USER_ONLY
9941 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
9942 * the block size so we might have to do more than one TLB lookup.
9943 * We know that in fact for any v8 CPU the page size is at least 4K
9944 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
9945 * 1K as an artefact of legacy v5 subpage support being present in the
9946 * same QEMU executable.
9948 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
9949 void *hostaddr
[maxidx
];
9951 unsigned mmu_idx
= cpu_mmu_index(env
, false);
9952 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
9954 for (try = 0; try < 2; try++) {
9956 for (i
= 0; i
< maxidx
; i
++) {
9957 hostaddr
[i
] = tlb_vaddr_to_host(env
,
9958 vaddr
+ TARGET_PAGE_SIZE
* i
,
9965 /* If it's all in the TLB it's fair game for just writing to;
9966 * we know we don't need to update dirty status, etc.
9968 for (i
= 0; i
< maxidx
- 1; i
++) {
9969 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
9971 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
9974 /* OK, try a store and see if we can populate the tlb. This
9975 * might cause an exception if the memory isn't writable,
9976 * in which case we will longjmp out of here. We must for
9977 * this purpose use the actual register value passed to us
9978 * so that we get the fault address right.
9980 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
9981 /* Now we can populate the other TLB entries, if any */
9982 for (i
= 0; i
< maxidx
; i
++) {
9983 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
9984 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
9985 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
9990 /* Slow path (probably attempt to do this to an I/O device or
9991 * similar, or clearing of a block of code we have translations
9992 * cached for). Just do a series of byte writes as the architecture
9993 * demands. It's not worth trying to use a cpu_physical_memory_map(),
9994 * memset(), unmap() sequence here because:
9995 * + we'd need to account for the blocksize being larger than a page
9996 * + the direct-RAM access case is almost always going to be dealt
9997 * with in the fastpath code above, so there's no speed benefit
9998 * + we would have to deal with the map returning NULL because the
9999 * bounce buffer was in use
10001 for (i
= 0; i
< blocklen
; i
++) {
10002 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
10006 memset(g2h(vaddr
), 0, blocklen
);
10010 /* Note that signed overflow is undefined in C. The following routines are
10011 careful to use unsigned types where modulo arithmetic is required.
10012 Failure to do so _will_ break on newer gcc. */
10014 /* Signed saturating arithmetic. */
10016 /* Perform 16-bit signed saturating addition. */
10017 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10022 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10031 /* Perform 8-bit signed saturating addition. */
10032 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10037 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10046 /* Perform 16-bit signed saturating subtraction. */
10047 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10052 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10061 /* Perform 8-bit signed saturating subtraction. */
10062 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10067 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10076 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10077 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10078 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10079 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10082 #include "op_addsub.h"
10084 /* Unsigned saturating arithmetic. */
10085 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10094 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10102 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10111 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10119 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10120 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10121 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10122 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10125 #include "op_addsub.h"
10127 /* Signed modulo arithmetic. */
10128 #define SARITH16(a, b, n, op) do { \
10130 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10131 RESULT(sum, n, 16); \
10133 ge |= 3 << (n * 2); \
10136 #define SARITH8(a, b, n, op) do { \
10138 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10139 RESULT(sum, n, 8); \
10145 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10146 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10147 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10148 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10152 #include "op_addsub.h"
10154 /* Unsigned modulo arithmetic. */
10155 #define ADD16(a, b, n) do { \
10157 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10158 RESULT(sum, n, 16); \
10159 if ((sum >> 16) == 1) \
10160 ge |= 3 << (n * 2); \
10163 #define ADD8(a, b, n) do { \
10165 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10166 RESULT(sum, n, 8); \
10167 if ((sum >> 8) == 1) \
10171 #define SUB16(a, b, n) do { \
10173 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10174 RESULT(sum, n, 16); \
10175 if ((sum >> 16) == 0) \
10176 ge |= 3 << (n * 2); \
10179 #define SUB8(a, b, n) do { \
10181 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10182 RESULT(sum, n, 8); \
10183 if ((sum >> 8) == 0) \
10190 #include "op_addsub.h"
10192 /* Halved signed arithmetic. */
10193 #define ADD16(a, b, n) \
10194 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10195 #define SUB16(a, b, n) \
10196 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10197 #define ADD8(a, b, n) \
10198 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10199 #define SUB8(a, b, n) \
10200 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10203 #include "op_addsub.h"
10205 /* Halved unsigned arithmetic. */
10206 #define ADD16(a, b, n) \
10207 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10208 #define SUB16(a, b, n) \
10209 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10210 #define ADD8(a, b, n) \
10211 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10212 #define SUB8(a, b, n) \
10213 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10216 #include "op_addsub.h"
10218 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10226 /* Unsigned sum of absolute byte differences. */
10227 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10230 sum
= do_usad(a
, b
);
10231 sum
+= do_usad(a
>> 8, b
>> 8);
10232 sum
+= do_usad(a
>> 16, b
>>16);
10233 sum
+= do_usad(a
>> 24, b
>> 24);
10237 /* For ARMv6 SEL instruction. */
10238 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10250 mask
|= 0xff000000;
10251 return (a
& mask
) | (b
& ~mask
);
10254 /* VFP support. We follow the convention used for VFP instructions:
10255 Single precision routines have a "s" suffix, double precision a
10258 /* Convert host exception flags to vfp form. */
10259 static inline int vfp_exceptbits_from_host(int host_bits
)
10261 int target_bits
= 0;
10263 if (host_bits
& float_flag_invalid
)
10265 if (host_bits
& float_flag_divbyzero
)
10267 if (host_bits
& float_flag_overflow
)
10269 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
10271 if (host_bits
& float_flag_inexact
)
10272 target_bits
|= 0x10;
10273 if (host_bits
& float_flag_input_denormal
)
10274 target_bits
|= 0x80;
10275 return target_bits
;
10278 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
10283 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
10284 | (env
->vfp
.vec_len
<< 16)
10285 | (env
->vfp
.vec_stride
<< 20);
10286 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
10287 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
10288 fpscr
|= vfp_exceptbits_from_host(i
);
10292 uint32_t vfp_get_fpscr(CPUARMState
*env
)
10294 return HELPER(vfp_get_fpscr
)(env
);
10297 /* Convert vfp exception flags to target form. */
10298 static inline int vfp_exceptbits_to_host(int target_bits
)
10302 if (target_bits
& 1)
10303 host_bits
|= float_flag_invalid
;
10304 if (target_bits
& 2)
10305 host_bits
|= float_flag_divbyzero
;
10306 if (target_bits
& 4)
10307 host_bits
|= float_flag_overflow
;
10308 if (target_bits
& 8)
10309 host_bits
|= float_flag_underflow
;
10310 if (target_bits
& 0x10)
10311 host_bits
|= float_flag_inexact
;
10312 if (target_bits
& 0x80)
10313 host_bits
|= float_flag_input_denormal
;
10317 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
10322 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
10323 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
10324 env
->vfp
.vec_len
= (val
>> 16) & 7;
10325 env
->vfp
.vec_stride
= (val
>> 20) & 3;
10328 if (changed
& (3 << 22)) {
10329 i
= (val
>> 22) & 3;
10331 case FPROUNDING_TIEEVEN
:
10332 i
= float_round_nearest_even
;
10334 case FPROUNDING_POSINF
:
10335 i
= float_round_up
;
10337 case FPROUNDING_NEGINF
:
10338 i
= float_round_down
;
10340 case FPROUNDING_ZERO
:
10341 i
= float_round_to_zero
;
10344 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
10346 if (changed
& (1 << 24)) {
10347 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
10348 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
10350 if (changed
& (1 << 25))
10351 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
10353 i
= vfp_exceptbits_to_host(val
);
10354 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
10355 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
10358 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
10360 HELPER(vfp_set_fpscr
)(env
, val
);
10363 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
10365 #define VFP_BINOP(name) \
10366 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
10368 float_status *fpst = fpstp; \
10369 return float32_ ## name(a, b, fpst); \
10371 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
10373 float_status *fpst = fpstp; \
10374 return float64_ ## name(a, b, fpst); \
10386 float32
VFP_HELPER(neg
, s
)(float32 a
)
10388 return float32_chs(a
);
10391 float64
VFP_HELPER(neg
, d
)(float64 a
)
10393 return float64_chs(a
);
10396 float32
VFP_HELPER(abs
, s
)(float32 a
)
10398 return float32_abs(a
);
10401 float64
VFP_HELPER(abs
, d
)(float64 a
)
10403 return float64_abs(a
);
10406 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
10408 return float32_sqrt(a
, &env
->vfp
.fp_status
);
10411 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
10413 return float64_sqrt(a
, &env
->vfp
.fp_status
);
10416 /* XXX: check quiet/signaling case */
10417 #define DO_VFP_cmp(p, type) \
10418 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
10421 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
10422 case 0: flags = 0x6; break; \
10423 case -1: flags = 0x8; break; \
10424 case 1: flags = 0x2; break; \
10425 default: case 2: flags = 0x3; break; \
10427 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
10428 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
10430 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
10433 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
10434 case 0: flags = 0x6; break; \
10435 case -1: flags = 0x8; break; \
10436 case 1: flags = 0x2; break; \
10437 default: case 2: flags = 0x3; break; \
10439 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
10440 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
10442 DO_VFP_cmp(s
, float32
)
10443 DO_VFP_cmp(d
, float64
)
10446 /* Integer to float and float to integer conversions */
10448 #define CONV_ITOF(name, fsz, sign) \
10449 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
10451 float_status *fpst = fpstp; \
10452 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
10455 #define CONV_FTOI(name, fsz, sign, round) \
10456 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
10458 float_status *fpst = fpstp; \
10459 if (float##fsz##_is_any_nan(x)) { \
10460 float_raise(float_flag_invalid, fpst); \
10463 return float##fsz##_to_##sign##int32##round(x, fpst); \
10466 #define FLOAT_CONVS(name, p, fsz, sign) \
10467 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
10468 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
10469 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
10471 FLOAT_CONVS(si
, s
, 32, )
10472 FLOAT_CONVS(si
, d
, 64, )
10473 FLOAT_CONVS(ui
, s
, 32, u
)
10474 FLOAT_CONVS(ui
, d
, 64, u
)
10480 /* floating point conversion */
10481 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
10483 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
10484 /* ARM requires that S<->D conversion of any kind of NaN generates
10485 * a quiet NaN by forcing the most significant frac bit to 1.
10487 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
10490 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
10492 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
10493 /* ARM requires that S<->D conversion of any kind of NaN generates
10494 * a quiet NaN by forcing the most significant frac bit to 1.
10496 return float32_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
10499 /* VFP3 fixed point conversion. */
10500 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
10501 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
10504 float_status *fpst = fpstp; \
10506 tmp = itype##_to_##float##fsz(x, fpst); \
10507 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
10510 /* Notice that we want only input-denormal exception flags from the
10511 * scalbn operation: the other possible flags (overflow+inexact if
10512 * we overflow to infinity, output-denormal) aren't correct for the
10513 * complete scale-and-convert operation.
10515 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
10516 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
10520 float_status *fpst = fpstp; \
10521 int old_exc_flags = get_float_exception_flags(fpst); \
10523 if (float##fsz##_is_any_nan(x)) { \
10524 float_raise(float_flag_invalid, fpst); \
10527 tmp = float##fsz##_scalbn(x, shift, fpst); \
10528 old_exc_flags |= get_float_exception_flags(fpst) \
10529 & float_flag_input_denormal; \
10530 set_float_exception_flags(old_exc_flags, fpst); \
10531 return float##fsz##_to_##itype##round(tmp, fpst); \
10534 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
10535 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
10536 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
10537 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
10539 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
10540 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
10541 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
10543 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
10544 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
10545 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
10546 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
10547 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
10548 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
10549 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
10550 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
10551 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
10552 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
10553 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
10554 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
10555 #undef VFP_CONV_FIX
10556 #undef VFP_CONV_FIX_FLOAT
10557 #undef VFP_CONV_FLOAT_FIX_ROUND
10559 /* Set the current fp rounding mode and return the old one.
10560 * The argument is a softfloat float_round_ value.
10562 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
10564 float_status
*fp_status
= &env
->vfp
.fp_status
;
10566 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
10567 set_float_rounding_mode(rmode
, fp_status
);
10572 /* Set the current fp rounding mode in the standard fp status and return
10573 * the old one. This is for NEON instructions that need to change the
10574 * rounding mode but wish to use the standard FPSCR values for everything
10575 * else. Always set the rounding mode back to the correct value after
10577 * The argument is a softfloat float_round_ value.
10579 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
10581 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
10583 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
10584 set_float_rounding_mode(rmode
, fp_status
);
10589 /* Half precision conversions. */
10590 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
10592 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
10593 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
10595 return float32_maybe_silence_nan(r
, s
);
10600 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
10602 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
10603 float16 r
= float32_to_float16(a
, ieee
, s
);
10605 r
= float16_maybe_silence_nan(r
, s
);
10607 return float16_val(r
);
10610 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
10612 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
10615 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
10617 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
10620 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
10622 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
10625 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
10627 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
10630 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
10632 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
10633 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
10635 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
10640 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
10642 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
10643 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
10645 r
= float16_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
10647 return float16_val(r
);
10650 #define float32_two make_float32(0x40000000)
10651 #define float32_three make_float32(0x40400000)
10652 #define float32_one_point_five make_float32(0x3fc00000)
10654 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
10656 float_status
*s
= &env
->vfp
.standard_fp_status
;
10657 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
10658 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
10659 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
10660 float_raise(float_flag_input_denormal
, s
);
10662 return float32_two
;
10664 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
10667 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
10669 float_status
*s
= &env
->vfp
.standard_fp_status
;
10671 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
10672 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
10673 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
10674 float_raise(float_flag_input_denormal
, s
);
10676 return float32_one_point_five
;
10678 product
= float32_mul(a
, b
, s
);
10679 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
10682 /* NEON helpers. */
10684 /* Constants 256 and 512 are used in some helpers; we avoid relying on
10685 * int->float conversions at run-time. */
10686 #define float64_256 make_float64(0x4070000000000000LL)
10687 #define float64_512 make_float64(0x4080000000000000LL)
10688 #define float32_maxnorm make_float32(0x7f7fffff)
10689 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
10691 /* Reciprocal functions
10693 * The algorithm that must be used to calculate the estimate
10694 * is specified by the ARM ARM, see FPRecipEstimate()
10697 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
10699 /* These calculations mustn't set any fp exception flags,
10700 * so we use a local copy of the fp_status.
10702 float_status dummy_status
= *real_fp_status
;
10703 float_status
*s
= &dummy_status
;
10704 /* q = (int)(a * 512.0) */
10705 float64 q
= float64_mul(float64_512
, a
, s
);
10706 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
10708 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
10709 q
= int64_to_float64(q_int
, s
);
10710 q
= float64_add(q
, float64_half
, s
);
10711 q
= float64_div(q
, float64_512
, s
);
10712 q
= float64_div(float64_one
, q
, s
);
10714 /* s = (int)(256.0 * r + 0.5) */
10715 q
= float64_mul(q
, float64_256
, s
);
10716 q
= float64_add(q
, float64_half
, s
);
10717 q_int
= float64_to_int64_round_to_zero(q
, s
);
10719 /* return (double)s / 256.0 */
10720 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
10723 /* Common wrapper to call recip_estimate */
10724 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
10726 uint64_t val64
= float64_val(num
);
10727 uint64_t frac
= extract64(val64
, 0, 52);
10728 int64_t exp
= extract64(val64
, 52, 11);
10730 float64 scaled
, estimate
;
10732 /* Generate the scaled number for the estimate function */
10734 if (extract64(frac
, 51, 1) == 0) {
10736 frac
= extract64(frac
, 0, 50) << 2;
10738 frac
= extract64(frac
, 0, 51) << 1;
10742 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
10743 scaled
= make_float64((0x3feULL
<< 52)
10744 | extract64(frac
, 44, 8) << 44);
10746 estimate
= recip_estimate(scaled
, fpst
);
10748 /* Build new result */
10749 val64
= float64_val(estimate
);
10750 sbit
= 0x8000000000000000ULL
& val64
;
10752 frac
= extract64(val64
, 0, 52);
10755 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
10756 } else if (exp
== -1) {
10757 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
10761 return make_float64(sbit
| (exp
<< 52) | frac
);
10764 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
10766 switch (fpst
->float_rounding_mode
) {
10767 case float_round_nearest_even
: /* Round to Nearest */
10769 case float_round_up
: /* Round to +Inf */
10771 case float_round_down
: /* Round to -Inf */
10773 case float_round_to_zero
: /* Round to Zero */
10777 g_assert_not_reached();
10780 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
10782 float_status
*fpst
= fpstp
;
10783 float32 f32
= float32_squash_input_denormal(input
, fpst
);
10784 uint32_t f32_val
= float32_val(f32
);
10785 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
10786 int32_t f32_exp
= extract32(f32_val
, 23, 8);
10787 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
10793 if (float32_is_any_nan(f32
)) {
10795 if (float32_is_signaling_nan(f32
, fpst
)) {
10796 float_raise(float_flag_invalid
, fpst
);
10797 nan
= float32_maybe_silence_nan(f32
, fpst
);
10799 if (fpst
->default_nan_mode
) {
10800 nan
= float32_default_nan(fpst
);
10803 } else if (float32_is_infinity(f32
)) {
10804 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
10805 } else if (float32_is_zero(f32
)) {
10806 float_raise(float_flag_divbyzero
, fpst
);
10807 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
10808 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
10809 /* Abs(value) < 2.0^-128 */
10810 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
10811 if (round_to_inf(fpst
, f32_sbit
)) {
10812 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
10814 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
10816 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
10817 float_raise(float_flag_underflow
, fpst
);
10818 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
10822 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
10823 r64
= call_recip_estimate(f64
, 253, fpst
);
10824 r64_val
= float64_val(r64
);
10825 r64_exp
= extract64(r64_val
, 52, 11);
10826 r64_frac
= extract64(r64_val
, 0, 52);
10828 /* result = sign : result_exp<7:0> : fraction<51:29>; */
10829 return make_float32(f32_sbit
|
10830 (r64_exp
& 0xff) << 23 |
10831 extract64(r64_frac
, 29, 24));
10834 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
10836 float_status
*fpst
= fpstp
;
10837 float64 f64
= float64_squash_input_denormal(input
, fpst
);
10838 uint64_t f64_val
= float64_val(f64
);
10839 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
10840 int64_t f64_exp
= extract64(f64_val
, 52, 11);
10846 /* Deal with any special cases */
10847 if (float64_is_any_nan(f64
)) {
10849 if (float64_is_signaling_nan(f64
, fpst
)) {
10850 float_raise(float_flag_invalid
, fpst
);
10851 nan
= float64_maybe_silence_nan(f64
, fpst
);
10853 if (fpst
->default_nan_mode
) {
10854 nan
= float64_default_nan(fpst
);
10857 } else if (float64_is_infinity(f64
)) {
10858 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
10859 } else if (float64_is_zero(f64
)) {
10860 float_raise(float_flag_divbyzero
, fpst
);
10861 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
10862 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
10863 /* Abs(value) < 2.0^-1024 */
10864 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
10865 if (round_to_inf(fpst
, f64_sbit
)) {
10866 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
10868 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
10870 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
10871 float_raise(float_flag_underflow
, fpst
);
10872 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
10875 r64
= call_recip_estimate(f64
, 2045, fpst
);
10876 r64_val
= float64_val(r64
);
10877 r64_exp
= extract64(r64_val
, 52, 11);
10878 r64_frac
= extract64(r64_val
, 0, 52);
10880 /* result = sign : result_exp<10:0> : fraction<51:0> */
10881 return make_float64(f64_sbit
|
10882 ((r64_exp
& 0x7ff) << 52) |
10886 /* The algorithm that must be used to calculate the estimate
10887 * is specified by the ARM ARM.
10889 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
10891 /* These calculations mustn't set any fp exception flags,
10892 * so we use a local copy of the fp_status.
10894 float_status dummy_status
= *real_fp_status
;
10895 float_status
*s
= &dummy_status
;
10899 if (float64_lt(a
, float64_half
, s
)) {
10900 /* range 0.25 <= a < 0.5 */
10902 /* a in units of 1/512 rounded down */
10903 /* q0 = (int)(a * 512.0); */
10904 q
= float64_mul(float64_512
, a
, s
);
10905 q_int
= float64_to_int64_round_to_zero(q
, s
);
10907 /* reciprocal root r */
10908 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
10909 q
= int64_to_float64(q_int
, s
);
10910 q
= float64_add(q
, float64_half
, s
);
10911 q
= float64_div(q
, float64_512
, s
);
10912 q
= float64_sqrt(q
, s
);
10913 q
= float64_div(float64_one
, q
, s
);
10915 /* range 0.5 <= a < 1.0 */
10917 /* a in units of 1/256 rounded down */
10918 /* q1 = (int)(a * 256.0); */
10919 q
= float64_mul(float64_256
, a
, s
);
10920 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
10922 /* reciprocal root r */
10923 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
10924 q
= int64_to_float64(q_int
, s
);
10925 q
= float64_add(q
, float64_half
, s
);
10926 q
= float64_div(q
, float64_256
, s
);
10927 q
= float64_sqrt(q
, s
);
10928 q
= float64_div(float64_one
, q
, s
);
10930 /* r in units of 1/256 rounded to nearest */
10931 /* s = (int)(256.0 * r + 0.5); */
10933 q
= float64_mul(q
, float64_256
,s
);
10934 q
= float64_add(q
, float64_half
, s
);
10935 q_int
= float64_to_int64_round_to_zero(q
, s
);
10937 /* return (double)s / 256.0;*/
10938 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
10941 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
10943 float_status
*s
= fpstp
;
10944 float32 f32
= float32_squash_input_denormal(input
, s
);
10945 uint32_t val
= float32_val(f32
);
10946 uint32_t f32_sbit
= 0x80000000 & val
;
10947 int32_t f32_exp
= extract32(val
, 23, 8);
10948 uint32_t f32_frac
= extract32(val
, 0, 23);
10954 if (float32_is_any_nan(f32
)) {
10956 if (float32_is_signaling_nan(f32
, s
)) {
10957 float_raise(float_flag_invalid
, s
);
10958 nan
= float32_maybe_silence_nan(f32
, s
);
10960 if (s
->default_nan_mode
) {
10961 nan
= float32_default_nan(s
);
10964 } else if (float32_is_zero(f32
)) {
10965 float_raise(float_flag_divbyzero
, s
);
10966 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
10967 } else if (float32_is_neg(f32
)) {
10968 float_raise(float_flag_invalid
, s
);
10969 return float32_default_nan(s
);
10970 } else if (float32_is_infinity(f32
)) {
10971 return float32_zero
;
10974 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
10975 * preserving the parity of the exponent. */
10977 f64_frac
= ((uint64_t) f32_frac
) << 29;
10978 if (f32_exp
== 0) {
10979 while (extract64(f64_frac
, 51, 1) == 0) {
10980 f64_frac
= f64_frac
<< 1;
10981 f32_exp
= f32_exp
-1;
10983 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
10986 if (extract64(f32_exp
, 0, 1) == 0) {
10987 f64
= make_float64(((uint64_t) f32_sbit
) << 32
10991 f64
= make_float64(((uint64_t) f32_sbit
) << 32
10996 result_exp
= (380 - f32_exp
) / 2;
10998 f64
= recip_sqrt_estimate(f64
, s
);
11000 val64
= float64_val(f64
);
11002 val
= ((result_exp
& 0xff) << 23)
11003 | ((val64
>> 29) & 0x7fffff);
11004 return make_float32(val
);
11007 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
11009 float_status
*s
= fpstp
;
11010 float64 f64
= float64_squash_input_denormal(input
, s
);
11011 uint64_t val
= float64_val(f64
);
11012 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
11013 int64_t f64_exp
= extract64(val
, 52, 11);
11014 uint64_t f64_frac
= extract64(val
, 0, 52);
11015 int64_t result_exp
;
11016 uint64_t result_frac
;
11018 if (float64_is_any_nan(f64
)) {
11020 if (float64_is_signaling_nan(f64
, s
)) {
11021 float_raise(float_flag_invalid
, s
);
11022 nan
= float64_maybe_silence_nan(f64
, s
);
11024 if (s
->default_nan_mode
) {
11025 nan
= float64_default_nan(s
);
11028 } else if (float64_is_zero(f64
)) {
11029 float_raise(float_flag_divbyzero
, s
);
11030 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11031 } else if (float64_is_neg(f64
)) {
11032 float_raise(float_flag_invalid
, s
);
11033 return float64_default_nan(s
);
11034 } else if (float64_is_infinity(f64
)) {
11035 return float64_zero
;
11038 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
11039 * preserving the parity of the exponent. */
11041 if (f64_exp
== 0) {
11042 while (extract64(f64_frac
, 51, 1) == 0) {
11043 f64_frac
= f64_frac
<< 1;
11044 f64_exp
= f64_exp
- 1;
11046 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
11049 if (extract64(f64_exp
, 0, 1) == 0) {
11050 f64
= make_float64(f64_sbit
11054 f64
= make_float64(f64_sbit
11059 result_exp
= (3068 - f64_exp
) / 2;
11061 f64
= recip_sqrt_estimate(f64
, s
);
11063 result_frac
= extract64(float64_val(f64
), 0, 52);
11065 return make_float64(f64_sbit
|
11066 ((result_exp
& 0x7ff) << 52) |
11070 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
11072 float_status
*s
= fpstp
;
11075 if ((a
& 0x80000000) == 0) {
11079 f64
= make_float64((0x3feULL
<< 52)
11080 | ((int64_t)(a
& 0x7fffffff) << 21));
11082 f64
= recip_estimate(f64
, s
);
11084 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
11087 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
11089 float_status
*fpst
= fpstp
;
11092 if ((a
& 0xc0000000) == 0) {
11096 if (a
& 0x80000000) {
11097 f64
= make_float64((0x3feULL
<< 52)
11098 | ((uint64_t)(a
& 0x7fffffff) << 21));
11099 } else { /* bits 31-30 == '01' */
11100 f64
= make_float64((0x3fdULL
<< 52)
11101 | ((uint64_t)(a
& 0x3fffffff) << 22));
11104 f64
= recip_sqrt_estimate(f64
, fpst
);
11106 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
11109 /* VFPv4 fused multiply-accumulate */
11110 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
11112 float_status
*fpst
= fpstp
;
11113 return float32_muladd(a
, b
, c
, 0, fpst
);
11116 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
11118 float_status
*fpst
= fpstp
;
11119 return float64_muladd(a
, b
, c
, 0, fpst
);
11122 /* ARMv8 round to integral */
11123 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
11125 return float32_round_to_int(x
, fp_status
);
11128 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
11130 return float64_round_to_int(x
, fp_status
);
11133 float32
HELPER(rints
)(float32 x
, void *fp_status
)
11135 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
11138 ret
= float32_round_to_int(x
, fp_status
);
11140 /* Suppress any inexact exceptions the conversion produced */
11141 if (!(old_flags
& float_flag_inexact
)) {
11142 new_flags
= get_float_exception_flags(fp_status
);
11143 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
11149 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
11151 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
11154 ret
= float64_round_to_int(x
, fp_status
);
11156 new_flags
= get_float_exception_flags(fp_status
);
11158 /* Suppress any inexact exceptions the conversion produced */
11159 if (!(old_flags
& float_flag_inexact
)) {
11160 new_flags
= get_float_exception_flags(fp_status
);
11161 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
11167 /* Convert ARM rounding mode to softfloat */
11168 int arm_rmode_to_sf(int rmode
)
11171 case FPROUNDING_TIEAWAY
:
11172 rmode
= float_round_ties_away
;
11174 case FPROUNDING_ODD
:
11175 /* FIXME: add support for TIEAWAY and ODD */
11176 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
11178 case FPROUNDING_TIEEVEN
:
11180 rmode
= float_round_nearest_even
;
11182 case FPROUNDING_POSINF
:
11183 rmode
= float_round_up
;
11185 case FPROUNDING_NEGINF
:
11186 rmode
= float_round_down
;
11188 case FPROUNDING_ZERO
:
11189 rmode
= float_round_to_zero
;
11196 * The upper bytes of val (above the number specified by 'bytes') must have
11197 * been zeroed out by the caller.
11199 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11203 stl_le_p(buf
, val
);
11205 /* zlib crc32 converts the accumulator and output to one's complement. */
11206 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11209 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11213 stl_le_p(buf
, val
);
11215 /* Linux crc32c converts the output to one's complement. */
11216 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;