4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/kvm.h"
28 #include "qemu/range.h"
29 #include "qapi/qapi-commands-machine-target.h"
30 #include "qapi/error.h"
31 #include "qemu/guest-random.h"
34 #include "exec/cpu_ldst.h"
37 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
39 #ifndef CONFIG_USER_ONLY
41 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
42 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
43 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
44 target_ulong
*page_size_ptr
,
45 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
48 static void switch_mode(CPUARMState
*env
, int mode
);
50 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
54 /* VFP data registers are always little-endian. */
55 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
57 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
60 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
61 /* Aliases for Q regs. */
64 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
66 stq_le_p(buf
+ 8, q
[1]);
70 switch (reg
- nregs
) {
71 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
72 case 1: stl_p(buf
, vfp_get_fpscr(env
)); return 4;
73 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
78 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
84 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
87 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
90 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
92 q
[1] = ldq_le_p(buf
+ 8);
96 switch (reg
- nregs
) {
97 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
98 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
99 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
104 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
108 /* 128 bit FP register */
110 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
112 stq_le_p(buf
+ 8, q
[1]);
117 stl_p(buf
, vfp_get_fpsr(env
));
121 stl_p(buf
, vfp_get_fpcr(env
));
128 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
132 /* 128 bit FP register */
134 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
135 q
[0] = ldq_le_p(buf
);
136 q
[1] = ldq_le_p(buf
+ 8);
141 vfp_set_fpsr(env
, ldl_p(buf
));
145 vfp_set_fpcr(env
, ldl_p(buf
));
152 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
154 assert(ri
->fieldoffset
);
155 if (cpreg_field_is_64bit(ri
)) {
156 return CPREG_FIELD64(env
, ri
);
158 return CPREG_FIELD32(env
, ri
);
162 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
165 assert(ri
->fieldoffset
);
166 if (cpreg_field_is_64bit(ri
)) {
167 CPREG_FIELD64(env
, ri
) = value
;
169 CPREG_FIELD32(env
, ri
) = value
;
173 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
175 return (char *)env
+ ri
->fieldoffset
;
178 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
180 /* Raw read of a coprocessor register (as needed for migration, etc). */
181 if (ri
->type
& ARM_CP_CONST
) {
182 return ri
->resetvalue
;
183 } else if (ri
->raw_readfn
) {
184 return ri
->raw_readfn(env
, ri
);
185 } else if (ri
->readfn
) {
186 return ri
->readfn(env
, ri
);
188 return raw_read(env
, ri
);
192 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
195 /* Raw write of a coprocessor register (as needed for migration, etc).
196 * Note that constant registers are treated as write-ignored; the
197 * caller should check for success by whether a readback gives the
200 if (ri
->type
& ARM_CP_CONST
) {
202 } else if (ri
->raw_writefn
) {
203 ri
->raw_writefn(env
, ri
, v
);
204 } else if (ri
->writefn
) {
205 ri
->writefn(env
, ri
, v
);
207 raw_write(env
, ri
, v
);
211 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
213 ARMCPU
*cpu
= env_archcpu(env
);
214 const ARMCPRegInfo
*ri
;
217 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
218 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
220 if (cpreg_field_is_64bit(ri
)) {
221 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
223 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
229 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
234 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
236 /* Return true if the regdef would cause an assertion if you called
237 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
238 * program bug for it not to have the NO_RAW flag).
239 * NB that returning false here doesn't necessarily mean that calling
240 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
241 * read/write access functions which are safe for raw use" from "has
242 * read/write access functions which have side effects but has forgotten
243 * to provide raw access functions".
244 * The tests here line up with the conditions in read/write_raw_cp_reg()
245 * and assertions in raw_read()/raw_write().
247 if ((ri
->type
& ARM_CP_CONST
) ||
249 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
255 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
257 /* Write the coprocessor state from cpu->env to the (index,value) list. */
261 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
262 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
263 const ARMCPRegInfo
*ri
;
266 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
271 if (ri
->type
& ARM_CP_NO_RAW
) {
275 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
278 * Only sync if the previous list->cpustate sync succeeded.
279 * Rather than tracking the success/failure state for every
280 * item in the list, we just recheck "does the raw write we must
281 * have made in write_list_to_cpustate() read back OK" here.
283 uint64_t oldval
= cpu
->cpreg_values
[i
];
285 if (oldval
== newval
) {
289 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
290 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
294 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
296 cpu
->cpreg_values
[i
] = newval
;
301 bool write_list_to_cpustate(ARMCPU
*cpu
)
306 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
307 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
308 uint64_t v
= cpu
->cpreg_values
[i
];
309 const ARMCPRegInfo
*ri
;
311 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
316 if (ri
->type
& ARM_CP_NO_RAW
) {
319 /* Write value and confirm it reads back as written
320 * (to catch read-only registers and partially read-only
321 * registers where the incoming migration value doesn't match)
323 write_raw_cp_reg(&cpu
->env
, ri
, v
);
324 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
331 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
333 ARMCPU
*cpu
= opaque
;
335 const ARMCPRegInfo
*ri
;
337 regidx
= *(uint32_t *)key
;
338 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
340 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
341 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
342 /* The value array need not be initialized at this point */
343 cpu
->cpreg_array_len
++;
347 static void count_cpreg(gpointer key
, gpointer opaque
)
349 ARMCPU
*cpu
= opaque
;
351 const ARMCPRegInfo
*ri
;
353 regidx
= *(uint32_t *)key
;
354 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
356 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
357 cpu
->cpreg_array_len
++;
361 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
363 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
364 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
375 void init_cpreg_list(ARMCPU
*cpu
)
377 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
378 * Note that we require cpreg_tuples[] to be sorted by key ID.
383 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
384 keys
= g_list_sort(keys
, cpreg_key_compare
);
386 cpu
->cpreg_array_len
= 0;
388 g_list_foreach(keys
, count_cpreg
, cpu
);
390 arraylen
= cpu
->cpreg_array_len
;
391 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
392 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
393 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
394 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
395 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
396 cpu
->cpreg_array_len
= 0;
398 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
400 assert(cpu
->cpreg_array_len
== arraylen
);
406 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
407 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
409 * access_el3_aa32ns: Used to check AArch32 register views.
410 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
412 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
413 const ARMCPRegInfo
*ri
,
416 bool secure
= arm_is_secure_below_el3(env
);
418 assert(!arm_el_is_aa64(env
, 3));
420 return CP_ACCESS_TRAP_UNCATEGORIZED
;
425 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
426 const ARMCPRegInfo
*ri
,
429 if (!arm_el_is_aa64(env
, 3)) {
430 return access_el3_aa32ns(env
, ri
, isread
);
435 /* Some secure-only AArch32 registers trap to EL3 if used from
436 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
437 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
438 * We assume that the .access field is set to PL1_RW.
440 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
441 const ARMCPRegInfo
*ri
,
444 if (arm_current_el(env
) == 3) {
447 if (arm_is_secure_below_el3(env
)) {
448 return CP_ACCESS_TRAP_EL3
;
450 /* This will be EL1 NS and EL2 NS, which just UNDEF */
451 return CP_ACCESS_TRAP_UNCATEGORIZED
;
454 /* Check for traps to "powerdown debug" registers, which are controlled
457 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 int el
= arm_current_el(env
);
461 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
462 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
463 (arm_hcr_el2_eff(env
) & HCR_TGE
);
465 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
466 return CP_ACCESS_TRAP_EL2
;
468 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
469 return CP_ACCESS_TRAP_EL3
;
474 /* Check for traps to "debug ROM" registers, which are controlled
475 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
477 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
480 int el
= arm_current_el(env
);
481 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
482 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
483 (arm_hcr_el2_eff(env
) & HCR_TGE
);
485 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
486 return CP_ACCESS_TRAP_EL2
;
488 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
489 return CP_ACCESS_TRAP_EL3
;
494 /* Check for traps to general debug registers, which are controlled
495 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
497 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
500 int el
= arm_current_el(env
);
501 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
502 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
503 (arm_hcr_el2_eff(env
) & HCR_TGE
);
505 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
506 return CP_ACCESS_TRAP_EL2
;
508 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
509 return CP_ACCESS_TRAP_EL3
;
514 /* Check for traps to performance monitor registers, which are controlled
515 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
517 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
520 int el
= arm_current_el(env
);
522 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
523 && !arm_is_secure_below_el3(env
)) {
524 return CP_ACCESS_TRAP_EL2
;
526 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
527 return CP_ACCESS_TRAP_EL3
;
532 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
534 ARMCPU
*cpu
= env_archcpu(env
);
536 raw_write(env
, ri
, value
);
537 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
540 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
542 ARMCPU
*cpu
= env_archcpu(env
);
544 if (raw_read(env
, ri
) != value
) {
545 /* Unlike real hardware the qemu TLB uses virtual addresses,
546 * not modified virtual addresses, so this causes a TLB flush.
549 raw_write(env
, ri
, value
);
553 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 ARMCPU
*cpu
= env_archcpu(env
);
558 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
559 && !extended_addresses_enabled(env
)) {
560 /* For VMSA (when not using the LPAE long descriptor page table
561 * format) this register includes the ASID, so do a TLB flush.
562 * For PMSA it is purely a process ID and no action is needed.
566 raw_write(env
, ri
, value
);
569 /* IS variants of TLB operations must affect all cores */
570 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
573 CPUState
*cs
= env_cpu(env
);
575 tlb_flush_all_cpus_synced(cs
);
578 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
581 CPUState
*cs
= env_cpu(env
);
583 tlb_flush_all_cpus_synced(cs
);
586 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
589 CPUState
*cs
= env_cpu(env
);
591 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
594 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= env_cpu(env
);
599 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
603 * Non-IS variants of TLB operations are upgraded to
604 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
605 * force broadcast of these operations.
607 static bool tlb_force_broadcast(CPUARMState
*env
)
609 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
610 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
613 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 /* Invalidate all (TLBIALL) */
617 CPUState
*cs
= env_cpu(env
);
619 if (tlb_force_broadcast(env
)) {
620 tlb_flush_all_cpus_synced(cs
);
626 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
629 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
630 CPUState
*cs
= env_cpu(env
);
632 value
&= TARGET_PAGE_MASK
;
633 if (tlb_force_broadcast(env
)) {
634 tlb_flush_page_all_cpus_synced(cs
, value
);
636 tlb_flush_page(cs
, value
);
640 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
643 /* Invalidate by ASID (TLBIASID) */
644 CPUState
*cs
= env_cpu(env
);
646 if (tlb_force_broadcast(env
)) {
647 tlb_flush_all_cpus_synced(cs
);
653 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
656 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
657 CPUState
*cs
= env_cpu(env
);
659 value
&= TARGET_PAGE_MASK
;
660 if (tlb_force_broadcast(env
)) {
661 tlb_flush_page_all_cpus_synced(cs
, value
);
663 tlb_flush_page(cs
, value
);
667 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
670 CPUState
*cs
= env_cpu(env
);
672 tlb_flush_by_mmuidx(cs
,
674 ARMMMUIdxBit_E10_1_PAN
|
676 ARMMMUIdxBit_Stage2
);
679 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
682 CPUState
*cs
= env_cpu(env
);
684 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
686 ARMMMUIdxBit_E10_1_PAN
|
688 ARMMMUIdxBit_Stage2
);
691 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
694 /* Invalidate by IPA. This has to invalidate any structures that
695 * contain only stage 2 translation information, but does not need
696 * to apply to structures that contain combined stage 1 and stage 2
697 * translation information.
698 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
700 CPUState
*cs
= env_cpu(env
);
703 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
707 pageaddr
= sextract64(value
<< 12, 0, 40);
709 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
712 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
715 CPUState
*cs
= env_cpu(env
);
718 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
722 pageaddr
= sextract64(value
<< 12, 0, 40);
724 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
725 ARMMMUIdxBit_Stage2
);
728 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
731 CPUState
*cs
= env_cpu(env
);
733 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
736 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
739 CPUState
*cs
= env_cpu(env
);
741 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
744 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
747 CPUState
*cs
= env_cpu(env
);
748 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
750 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
753 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
756 CPUState
*cs
= env_cpu(env
);
757 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
759 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
763 static const ARMCPRegInfo cp_reginfo
[] = {
764 /* Define the secure and non-secure FCSE identifier CP registers
765 * separately because there is no secure bank in V8 (no _EL3). This allows
766 * the secure register to be properly reset and migrated. There is also no
767 * v8 EL1 version of the register so the non-secure instance stands alone.
770 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
771 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
772 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
773 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
774 { .name
= "FCSEIDR_S",
775 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
776 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
777 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
778 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
779 /* Define the secure and non-secure context identifier CP registers
780 * separately because there is no secure bank in V8 (no _EL3). This allows
781 * the secure register to be properly reset and migrated. In the
782 * non-secure case, the 32-bit register will have reset and migration
783 * disabled during registration as it is handled by the 64-bit instance.
785 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
786 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
787 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
788 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
789 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
790 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
791 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
792 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
793 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
794 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
798 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
799 /* NB: Some of these registers exist in v8 but with more precise
800 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
802 /* MMU Domain access control / MPU write buffer control */
804 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
805 .access
= PL1_RW
, .resetvalue
= 0,
806 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
807 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
808 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
809 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
810 * For v6 and v5, these mappings are overly broad.
812 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
813 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
814 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
815 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
816 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
817 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
818 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
819 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
820 /* Cache maintenance ops; some of this space may be overridden later. */
821 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
822 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
823 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
827 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
828 /* Not all pre-v6 cores implemented this WFI, so this is slightly
831 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
832 .access
= PL1_W
, .type
= ARM_CP_WFI
},
836 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
837 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
838 * is UNPREDICTABLE; we choose to NOP as most implementations do).
840 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
841 .access
= PL1_W
, .type
= ARM_CP_WFI
},
842 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
843 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
844 * OMAPCP will override this space.
846 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
847 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
849 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
850 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
852 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
853 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
854 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
856 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
857 * implementing it as RAZ means the "debug architecture version" bits
858 * will read as a reserved value, which should cause Linux to not try
859 * to use the debug hardware.
861 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
862 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
863 /* MMU TLB control. Note that the wildcarding means we cover not just
864 * the unified TLB ops but also the dside/iside/inner-shareable variants.
866 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
867 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
868 .type
= ARM_CP_NO_RAW
},
869 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
870 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
871 .type
= ARM_CP_NO_RAW
},
872 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
873 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
874 .type
= ARM_CP_NO_RAW
},
875 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
876 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
877 .type
= ARM_CP_NO_RAW
},
878 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
879 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
880 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
881 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
885 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
890 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
891 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
892 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
893 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
894 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
896 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
897 /* VFP coprocessor: cp10 & cp11 [23:20] */
898 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
900 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
901 /* ASEDIS [31] bit is RAO/WI */
905 /* VFPv3 and upwards with NEON implement 32 double precision
906 * registers (D0-D31).
908 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
909 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
910 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
918 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
919 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
921 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
922 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
923 value
&= ~(0xf << 20);
924 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
927 env
->cp15
.cpacr_el1
= value
;
930 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
933 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
934 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
936 uint64_t value
= env
->cp15
.cpacr_el1
;
938 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
939 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
940 value
&= ~(0xf << 20);
946 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 /* Call cpacr_write() so that we reset with the correct RAO bits set
949 * for our CPU features.
951 cpacr_write(env
, ri
, 0);
954 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
957 if (arm_feature(env
, ARM_FEATURE_V8
)) {
958 /* Check if CPACR accesses are to be trapped to EL2 */
959 if (arm_current_el(env
) == 1 &&
960 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
961 return CP_ACCESS_TRAP_EL2
;
962 /* Check if CPACR accesses are to be trapped to EL3 */
963 } else if (arm_current_el(env
) < 3 &&
964 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
965 return CP_ACCESS_TRAP_EL3
;
972 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
975 /* Check if CPTR accesses are set to trap to EL3 */
976 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
977 return CP_ACCESS_TRAP_EL3
;
983 static const ARMCPRegInfo v6_cp_reginfo
[] = {
984 /* prefetch by MVA in v6, NOP in v7 */
985 { .name
= "MVA_prefetch",
986 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
987 .access
= PL1_W
, .type
= ARM_CP_NOP
},
988 /* We need to break the TB after ISB to execute self-modifying code
989 * correctly and also to take any pending interrupts immediately.
990 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
992 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
993 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
994 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
995 .access
= PL0_W
, .type
= ARM_CP_NOP
},
996 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
997 .access
= PL0_W
, .type
= ARM_CP_NOP
},
998 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1001 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1003 /* Watchpoint Fault Address Register : should actually only be present
1004 * for 1136, 1176, 11MPCore.
1006 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1007 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1008 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1009 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1010 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1011 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1015 /* Definitions for the PMU registers */
1016 #define PMCRN_MASK 0xf800
1017 #define PMCRN_SHIFT 11
1025 #define PMXEVTYPER_P 0x80000000
1026 #define PMXEVTYPER_U 0x40000000
1027 #define PMXEVTYPER_NSK 0x20000000
1028 #define PMXEVTYPER_NSU 0x10000000
1029 #define PMXEVTYPER_NSH 0x08000000
1030 #define PMXEVTYPER_M 0x04000000
1031 #define PMXEVTYPER_MT 0x02000000
1032 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1033 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1034 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1035 PMXEVTYPER_M | PMXEVTYPER_MT | \
1036 PMXEVTYPER_EVTCOUNT)
1038 #define PMCCFILTR 0xf8000000
1039 #define PMCCFILTR_M PMXEVTYPER_M
1040 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1042 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1044 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1047 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1048 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1050 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1053 typedef struct pm_event
{
1054 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1055 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1056 bool (*supported
)(CPUARMState
*);
1058 * Retrieve the current count of the underlying event. The programmed
1059 * counters hold a difference from the return value from this function
1061 uint64_t (*get_count
)(CPUARMState
*);
1063 * Return how many nanoseconds it will take (at a minimum) for count events
1064 * to occur. A negative value indicates the counter will never overflow, or
1065 * that the counter has otherwise arranged for the overflow bit to be set
1066 * and the PMU interrupt to be raised on overflow.
1068 int64_t (*ns_per_count
)(uint64_t);
1071 static bool event_always_supported(CPUARMState
*env
)
1076 static uint64_t swinc_get_count(CPUARMState
*env
)
1079 * SW_INCR events are written directly to the pmevcntr's by writes to
1080 * PMSWINC, so there is no underlying count maintained by the PMU itself
1085 static int64_t swinc_ns_per(uint64_t ignored
)
1091 * Return the underlying cycle count for the PMU cycle counters. If we're in
1092 * usermode, simply return 0.
1094 static uint64_t cycles_get_count(CPUARMState
*env
)
1096 #ifndef CONFIG_USER_ONLY
1097 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1098 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1100 return cpu_get_host_ticks();
1104 #ifndef CONFIG_USER_ONLY
1105 static int64_t cycles_ns_per(uint64_t cycles
)
1107 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1110 static bool instructions_supported(CPUARMState
*env
)
1112 return use_icount
== 1 /* Precise instruction counting */;
1115 static uint64_t instructions_get_count(CPUARMState
*env
)
1117 return (uint64_t)cpu_get_icount_raw();
1120 static int64_t instructions_ns_per(uint64_t icount
)
1122 return cpu_icount_to_ns((int64_t)icount
);
1126 static const pm_event pm_events
[] = {
1127 { .number
= 0x000, /* SW_INCR */
1128 .supported
= event_always_supported
,
1129 .get_count
= swinc_get_count
,
1130 .ns_per_count
= swinc_ns_per
,
1132 #ifndef CONFIG_USER_ONLY
1133 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1134 .supported
= instructions_supported
,
1135 .get_count
= instructions_get_count
,
1136 .ns_per_count
= instructions_ns_per
,
1138 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1139 .supported
= event_always_supported
,
1140 .get_count
= cycles_get_count
,
1141 .ns_per_count
= cycles_ns_per
,
1147 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1148 * events (i.e. the statistical profiling extension), this implementation
1149 * should first be updated to something sparse instead of the current
1150 * supported_event_map[] array.
1152 #define MAX_EVENT_ID 0x11
1153 #define UNSUPPORTED_EVENT UINT16_MAX
1154 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1157 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1158 * of ARM event numbers to indices in our pm_events array.
1160 * Note: Events in the 0x40XX range are not currently supported.
1162 void pmu_init(ARMCPU
*cpu
)
1167 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1170 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1171 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1176 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1177 const pm_event
*cnt
= &pm_events
[i
];
1178 assert(cnt
->number
<= MAX_EVENT_ID
);
1179 /* We do not currently support events in the 0x40xx range */
1180 assert(cnt
->number
<= 0x3f);
1182 if (cnt
->supported(&cpu
->env
)) {
1183 supported_event_map
[cnt
->number
] = i
;
1184 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1185 if (cnt
->number
& 0x20) {
1186 cpu
->pmceid1
|= event_mask
;
1188 cpu
->pmceid0
|= event_mask
;
1195 * Check at runtime whether a PMU event is supported for the current machine
1197 static bool event_supported(uint16_t number
)
1199 if (number
> MAX_EVENT_ID
) {
1202 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1205 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1208 /* Performance monitor registers user accessibility is controlled
1209 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1210 * trapping to EL2 or EL3 for other accesses.
1212 int el
= arm_current_el(env
);
1214 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1215 return CP_ACCESS_TRAP
;
1217 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1218 && !arm_is_secure_below_el3(env
)) {
1219 return CP_ACCESS_TRAP_EL2
;
1221 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1222 return CP_ACCESS_TRAP_EL3
;
1225 return CP_ACCESS_OK
;
1228 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1229 const ARMCPRegInfo
*ri
,
1232 /* ER: event counter read trap control */
1233 if (arm_feature(env
, ARM_FEATURE_V8
)
1234 && arm_current_el(env
) == 0
1235 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1237 return CP_ACCESS_OK
;
1240 return pmreg_access(env
, ri
, isread
);
1243 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1244 const ARMCPRegInfo
*ri
,
1247 /* SW: software increment write trap control */
1248 if (arm_feature(env
, ARM_FEATURE_V8
)
1249 && arm_current_el(env
) == 0
1250 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1252 return CP_ACCESS_OK
;
1255 return pmreg_access(env
, ri
, isread
);
1258 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1259 const ARMCPRegInfo
*ri
,
1262 /* ER: event counter read trap control */
1263 if (arm_feature(env
, ARM_FEATURE_V8
)
1264 && arm_current_el(env
) == 0
1265 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1266 return CP_ACCESS_OK
;
1269 return pmreg_access(env
, ri
, isread
);
1272 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1273 const ARMCPRegInfo
*ri
,
1276 /* CR: cycle counter read trap control */
1277 if (arm_feature(env
, ARM_FEATURE_V8
)
1278 && arm_current_el(env
) == 0
1279 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1281 return CP_ACCESS_OK
;
1284 return pmreg_access(env
, ri
, isread
);
1287 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1288 * the current EL, security state, and register configuration.
1290 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1293 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1294 bool enabled
, prohibited
, filtered
;
1295 bool secure
= arm_is_secure(env
);
1296 int el
= arm_current_el(env
);
1297 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1299 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1303 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1304 (counter
< hpmn
|| counter
== 31)) {
1305 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1307 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1309 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1312 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1313 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1318 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1319 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1322 if (prohibited
&& counter
== 31) {
1323 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1326 if (counter
== 31) {
1327 filter
= env
->cp15
.pmccfiltr_el0
;
1329 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1332 p
= filter
& PMXEVTYPER_P
;
1333 u
= filter
& PMXEVTYPER_U
;
1334 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1335 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1336 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1337 m
= arm_el_is_aa64(env
, 1) &&
1338 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1341 filtered
= secure
? u
: u
!= nsu
;
1342 } else if (el
== 1) {
1343 filtered
= secure
? p
: p
!= nsk
;
1344 } else if (el
== 2) {
1350 if (counter
!= 31) {
1352 * If not checking PMCCNTR, ensure the counter is setup to an event we
1355 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1356 if (!event_supported(event
)) {
1361 return enabled
&& !prohibited
&& !filtered
;
1364 static void pmu_update_irq(CPUARMState
*env
)
1366 ARMCPU
*cpu
= env_archcpu(env
);
1367 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1368 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1372 * Ensure c15_ccnt is the guest-visible count so that operations such as
1373 * enabling/disabling the counter or filtering, modifying the count itself,
1374 * etc. can be done logically. This is essentially a no-op if the counter is
1375 * not enabled at the time of the call.
1377 static void pmccntr_op_start(CPUARMState
*env
)
1379 uint64_t cycles
= cycles_get_count(env
);
1381 if (pmu_counter_enabled(env
, 31)) {
1382 uint64_t eff_cycles
= cycles
;
1383 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1384 /* Increment once every 64 processor clock cycles */
1388 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1390 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1391 1ull << 63 : 1ull << 31;
1392 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1393 env
->cp15
.c9_pmovsr
|= (1 << 31);
1394 pmu_update_irq(env
);
1397 env
->cp15
.c15_ccnt
= new_pmccntr
;
1399 env
->cp15
.c15_ccnt_delta
= cycles
;
1403 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1404 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1407 static void pmccntr_op_finish(CPUARMState
*env
)
1409 if (pmu_counter_enabled(env
, 31)) {
1410 #ifndef CONFIG_USER_ONLY
1411 /* Calculate when the counter will next overflow */
1412 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1413 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1414 remaining_cycles
= (uint32_t)remaining_cycles
;
1416 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1418 if (overflow_in
> 0) {
1419 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1421 ARMCPU
*cpu
= env_archcpu(env
);
1422 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1426 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1427 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1428 /* Increment once every 64 processor clock cycles */
1431 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1435 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1438 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1440 if (event_supported(event
)) {
1441 uint16_t event_idx
= supported_event_map
[event
];
1442 count
= pm_events
[event_idx
].get_count(env
);
1445 if (pmu_counter_enabled(env
, counter
)) {
1446 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1448 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1449 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1450 pmu_update_irq(env
);
1452 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1454 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1457 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1459 if (pmu_counter_enabled(env
, counter
)) {
1460 #ifndef CONFIG_USER_ONLY
1461 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1462 uint16_t event_idx
= supported_event_map
[event
];
1463 uint64_t delta
= UINT32_MAX
-
1464 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1465 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1467 if (overflow_in
> 0) {
1468 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1470 ARMCPU
*cpu
= env_archcpu(env
);
1471 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1475 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1476 env
->cp15
.c14_pmevcntr
[counter
];
1480 void pmu_op_start(CPUARMState
*env
)
1483 pmccntr_op_start(env
);
1484 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1485 pmevcntr_op_start(env
, i
);
1489 void pmu_op_finish(CPUARMState
*env
)
1492 pmccntr_op_finish(env
);
1493 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1494 pmevcntr_op_finish(env
, i
);
1498 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1500 pmu_op_start(&cpu
->env
);
1503 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1505 pmu_op_finish(&cpu
->env
);
1508 void arm_pmu_timer_cb(void *opaque
)
1510 ARMCPU
*cpu
= opaque
;
1513 * Update all the counter values based on the current underlying counts,
1514 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1515 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1516 * counter may expire.
1518 pmu_op_start(&cpu
->env
);
1519 pmu_op_finish(&cpu
->env
);
1522 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1527 if (value
& PMCRC
) {
1528 /* The counter has been reset */
1529 env
->cp15
.c15_ccnt
= 0;
1532 if (value
& PMCRP
) {
1534 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1535 env
->cp15
.c14_pmevcntr
[i
] = 0;
1539 /* only the DP, X, D and E bits are writable */
1540 env
->cp15
.c9_pmcr
&= ~0x39;
1541 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1546 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1550 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1551 /* Increment a counter's count iff: */
1552 if ((value
& (1 << i
)) && /* counter's bit is set */
1553 /* counter is enabled and not filtered */
1554 pmu_counter_enabled(env
, i
) &&
1555 /* counter is SW_INCR */
1556 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1557 pmevcntr_op_start(env
, i
);
1560 * Detect if this write causes an overflow since we can't predict
1561 * PMSWINC overflows like we can for other events
1563 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1565 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1566 env
->cp15
.c9_pmovsr
|= (1 << i
);
1567 pmu_update_irq(env
);
1570 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1572 pmevcntr_op_finish(env
, i
);
1577 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1580 pmccntr_op_start(env
);
1581 ret
= env
->cp15
.c15_ccnt
;
1582 pmccntr_op_finish(env
);
1586 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1589 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1590 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1591 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1594 env
->cp15
.c9_pmselr
= value
& 0x1f;
1597 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1600 pmccntr_op_start(env
);
1601 env
->cp15
.c15_ccnt
= value
;
1602 pmccntr_op_finish(env
);
1605 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1608 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1610 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1613 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1616 pmccntr_op_start(env
);
1617 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1618 pmccntr_op_finish(env
);
1621 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1624 pmccntr_op_start(env
);
1625 /* M is not accessible from AArch32 */
1626 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1627 (value
& PMCCFILTR
);
1628 pmccntr_op_finish(env
);
1631 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1633 /* M is not visible in AArch32 */
1634 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1637 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1640 value
&= pmu_counter_mask(env
);
1641 env
->cp15
.c9_pmcnten
|= value
;
1644 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1647 value
&= pmu_counter_mask(env
);
1648 env
->cp15
.c9_pmcnten
&= ~value
;
1651 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1654 value
&= pmu_counter_mask(env
);
1655 env
->cp15
.c9_pmovsr
&= ~value
;
1656 pmu_update_irq(env
);
1659 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1662 value
&= pmu_counter_mask(env
);
1663 env
->cp15
.c9_pmovsr
|= value
;
1664 pmu_update_irq(env
);
1667 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1668 uint64_t value
, const uint8_t counter
)
1670 if (counter
== 31) {
1671 pmccfiltr_write(env
, ri
, value
);
1672 } else if (counter
< pmu_num_counters(env
)) {
1673 pmevcntr_op_start(env
, counter
);
1676 * If this counter's event type is changing, store the current
1677 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1678 * pmevcntr_op_finish has the correct baseline when it converts back to
1681 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1682 PMXEVTYPER_EVTCOUNT
;
1683 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1684 if (old_event
!= new_event
) {
1686 if (event_supported(new_event
)) {
1687 uint16_t event_idx
= supported_event_map
[new_event
];
1688 count
= pm_events
[event_idx
].get_count(env
);
1690 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1693 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1694 pmevcntr_op_finish(env
, counter
);
1696 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1697 * PMSELR value is equal to or greater than the number of implemented
1698 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1702 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1703 const uint8_t counter
)
1705 if (counter
== 31) {
1706 return env
->cp15
.pmccfiltr_el0
;
1707 } else if (counter
< pmu_num_counters(env
)) {
1708 return env
->cp15
.c14_pmevtyper
[counter
];
1711 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1712 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1718 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1721 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1722 pmevtyper_write(env
, ri
, value
, counter
);
1725 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1729 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1732 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1733 * pmu_op_finish calls when loading saved state for a migration. Because
1734 * we're potentially updating the type of event here, the value written to
1735 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1736 * different counter type. Therefore, we need to set this value to the
1737 * current count for the counter type we're writing so that pmu_op_finish
1738 * has the correct count for its calculation.
1740 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1741 if (event_supported(event
)) {
1742 uint16_t event_idx
= supported_event_map
[event
];
1743 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1744 pm_events
[event_idx
].get_count(env
);
1748 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1750 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1751 return pmevtyper_read(env
, ri
, counter
);
1754 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1757 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1760 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1762 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1765 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1766 uint64_t value
, uint8_t counter
)
1768 if (counter
< pmu_num_counters(env
)) {
1769 pmevcntr_op_start(env
, counter
);
1770 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1771 pmevcntr_op_finish(env
, counter
);
1774 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1775 * are CONSTRAINED UNPREDICTABLE.
1779 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1782 if (counter
< pmu_num_counters(env
)) {
1784 pmevcntr_op_start(env
, counter
);
1785 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1786 pmevcntr_op_finish(env
, counter
);
1789 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1790 * are CONSTRAINED UNPREDICTABLE. */
1795 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1798 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1799 pmevcntr_write(env
, ri
, value
, counter
);
1802 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1804 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1805 return pmevcntr_read(env
, ri
, counter
);
1808 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1812 assert(counter
< pmu_num_counters(env
));
1813 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1814 pmevcntr_write(env
, ri
, value
, counter
);
1817 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1819 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1820 assert(counter
< pmu_num_counters(env
));
1821 return env
->cp15
.c14_pmevcntr
[counter
];
1824 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1827 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1830 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1832 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1835 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1838 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1839 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1841 env
->cp15
.c9_pmuserenr
= value
& 1;
1845 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1848 /* We have no event counters so only the C bit can be changed */
1849 value
&= pmu_counter_mask(env
);
1850 env
->cp15
.c9_pminten
|= value
;
1851 pmu_update_irq(env
);
1854 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1857 value
&= pmu_counter_mask(env
);
1858 env
->cp15
.c9_pminten
&= ~value
;
1859 pmu_update_irq(env
);
1862 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1865 /* Note that even though the AArch64 view of this register has bits
1866 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1867 * architectural requirements for bits which are RES0 only in some
1868 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1869 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1871 raw_write(env
, ri
, value
& ~0x1FULL
);
1874 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1876 /* Begin with base v8.0 state. */
1877 uint32_t valid_mask
= 0x3fff;
1878 ARMCPU
*cpu
= env_archcpu(env
);
1880 if (arm_el_is_aa64(env
, 3)) {
1881 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1882 valid_mask
&= ~SCR_NET
;
1884 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1887 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1888 valid_mask
&= ~SCR_HCE
;
1890 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1891 * supported if EL2 exists. The bit is UNK/SBZP when
1892 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1893 * when EL2 is unavailable.
1894 * On ARMv8, this bit is always available.
1896 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1897 !arm_feature(env
, ARM_FEATURE_V8
)) {
1898 valid_mask
&= ~SCR_SMD
;
1901 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1902 valid_mask
|= SCR_TLOR
;
1904 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1905 valid_mask
|= SCR_API
| SCR_APK
;
1908 /* Clear all-context RES0 bits. */
1909 value
&= valid_mask
;
1910 raw_write(env
, ri
, value
);
1913 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1914 const ARMCPRegInfo
*ri
,
1917 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1918 return CP_ACCESS_TRAP_EL2
;
1921 return CP_ACCESS_OK
;
1924 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1926 ARMCPU
*cpu
= env_archcpu(env
);
1928 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1931 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1932 ri
->secure
& ARM_CP_SECSTATE_S
);
1934 return cpu
->ccsidr
[index
];
1937 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1940 raw_write(env
, ri
, value
& 0xf);
1943 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1945 CPUState
*cs
= env_cpu(env
);
1946 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
1948 bool allow_virt
= (arm_current_el(env
) == 1 &&
1949 (!arm_is_secure_below_el3(env
) ||
1950 (env
->cp15
.scr_el3
& SCR_EEL2
)));
1952 if (allow_virt
&& (hcr_el2
& HCR_IMO
)) {
1953 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1957 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1962 if (allow_virt
&& (hcr_el2
& HCR_FMO
)) {
1963 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1967 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1972 /* External aborts are not possible in QEMU so A bit is always clear */
1976 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1979 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1980 return CP_ACCESS_TRAP_EL2
;
1983 return CP_ACCESS_OK
;
1986 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1989 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1990 return access_aa64_tid1(env
, ri
, isread
);
1993 return CP_ACCESS_OK
;
1996 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1997 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1998 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1999 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2000 /* Performance monitors are implementation defined in v7,
2001 * but with an ARM recommended set of registers, which we
2004 * Performance registers fall into three categories:
2005 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2006 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2007 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2008 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2009 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2011 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2012 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2013 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2014 .writefn
= pmcntenset_write
,
2015 .accessfn
= pmreg_access
,
2016 .raw_writefn
= raw_write
},
2017 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
2018 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2019 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2020 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2021 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2022 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2024 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2025 .accessfn
= pmreg_access
,
2026 .writefn
= pmcntenclr_write
,
2027 .type
= ARM_CP_ALIAS
},
2028 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2029 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2030 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2031 .type
= ARM_CP_ALIAS
,
2032 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2033 .writefn
= pmcntenclr_write
},
2034 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2035 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2036 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2037 .accessfn
= pmreg_access
,
2038 .writefn
= pmovsr_write
,
2039 .raw_writefn
= raw_write
},
2040 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2041 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2042 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2043 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2045 .writefn
= pmovsr_write
,
2046 .raw_writefn
= raw_write
},
2047 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2048 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2049 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2050 .writefn
= pmswinc_write
},
2051 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2052 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2053 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2054 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2055 .writefn
= pmswinc_write
},
2056 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2057 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2058 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2059 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2060 .raw_writefn
= raw_write
},
2061 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2062 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2063 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2064 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2065 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2066 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2067 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2068 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2069 .accessfn
= pmreg_access_ccntr
},
2070 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2071 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2072 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2074 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2075 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2076 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2077 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2078 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2079 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2080 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2082 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2083 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2084 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2085 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2087 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2089 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2090 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2091 .accessfn
= pmreg_access
,
2092 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2093 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2095 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2096 .accessfn
= pmreg_access
,
2097 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2098 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2099 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2100 .accessfn
= pmreg_access_xevcntr
,
2101 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2102 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2103 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2104 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2105 .accessfn
= pmreg_access_xevcntr
,
2106 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2107 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2108 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2109 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2111 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2112 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2113 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2114 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2117 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2118 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2119 .access
= PL1_RW
, .accessfn
= access_tpm
,
2120 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2121 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2123 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2124 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2125 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2126 .access
= PL1_RW
, .accessfn
= access_tpm
,
2128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2129 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2130 .resetvalue
= 0x0 },
2131 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2132 .access
= PL1_RW
, .accessfn
= access_tpm
,
2133 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2134 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2135 .writefn
= pmintenclr_write
, },
2136 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2137 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2138 .access
= PL1_RW
, .accessfn
= access_tpm
,
2139 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2141 .writefn
= pmintenclr_write
},
2142 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2143 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2145 .accessfn
= access_aa64_tid2
,
2146 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2147 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2148 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2150 .accessfn
= access_aa64_tid2
,
2151 .writefn
= csselr_write
, .resetvalue
= 0,
2152 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2153 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2154 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2155 * just RAZ for all cores:
2157 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2158 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2159 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2160 .accessfn
= access_aa64_tid1
,
2162 /* Auxiliary fault status registers: these also are IMPDEF, and we
2163 * choose to RAZ/WI for all cores.
2165 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2166 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2167 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2168 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2169 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2170 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2171 /* MAIR can just read-as-written because we don't implement caches
2172 * and so don't need to care about memory attributes.
2174 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2175 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2176 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2178 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2179 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2180 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2182 /* For non-long-descriptor page tables these are PRRR and NMRR;
2183 * regardless they still act as reads-as-written for QEMU.
2185 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2186 * allows them to assign the correct fieldoffset based on the endianness
2187 * handled in the field definitions.
2189 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2190 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
2191 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2192 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2193 .resetfn
= arm_cp_reset_ignore
},
2194 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2195 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
2196 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2197 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2198 .resetfn
= arm_cp_reset_ignore
},
2199 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2200 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2201 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2202 /* 32 bit ITLB invalidates */
2203 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2204 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2205 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2206 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2207 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2208 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2209 /* 32 bit DTLB invalidates */
2210 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2211 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2212 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2213 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2214 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2215 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2216 /* 32 bit TLB invalidates */
2217 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2218 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2219 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2220 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2221 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2222 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2223 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2224 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2228 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2229 /* 32 bit TLB invalidates, Inner Shareable */
2230 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2231 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
2232 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2233 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2234 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2235 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2236 .writefn
= tlbiasid_is_write
},
2237 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2238 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2239 .writefn
= tlbimvaa_is_write
},
2243 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2244 /* PMOVSSET is not implemented in v7 before v7ve */
2245 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2246 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2247 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2248 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2249 .writefn
= pmovsset_write
,
2250 .raw_writefn
= raw_write
},
2251 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2252 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2253 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2254 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2255 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2256 .writefn
= pmovsset_write
,
2257 .raw_writefn
= raw_write
},
2261 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2268 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2271 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2272 return CP_ACCESS_TRAP
;
2274 return CP_ACCESS_OK
;
2277 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2278 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2279 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2281 .writefn
= teecr_write
},
2282 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2283 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2284 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2288 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2289 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2290 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2292 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2293 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2295 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2296 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2297 .resetfn
= arm_cp_reset_ignore
},
2298 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2299 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2300 .access
= PL0_R
|PL1_W
,
2301 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2303 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2304 .access
= PL0_R
|PL1_W
,
2305 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2306 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2307 .resetfn
= arm_cp_reset_ignore
},
2308 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2309 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2311 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2312 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2314 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2315 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2320 #ifndef CONFIG_USER_ONLY
2322 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2325 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2326 * Writable only at the highest implemented exception level.
2328 int el
= arm_current_el(env
);
2334 hcr
= arm_hcr_el2_eff(env
);
2335 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2336 cntkctl
= env
->cp15
.cnthctl_el2
;
2338 cntkctl
= env
->cp15
.c14_cntkctl
;
2340 if (!extract32(cntkctl
, 0, 2)) {
2341 return CP_ACCESS_TRAP
;
2345 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2346 arm_is_secure_below_el3(env
)) {
2347 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2348 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2356 if (!isread
&& el
< arm_highest_el(env
)) {
2357 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2360 return CP_ACCESS_OK
;
2363 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2366 unsigned int cur_el
= arm_current_el(env
);
2367 bool secure
= arm_is_secure(env
);
2368 uint64_t hcr
= arm_hcr_el2_eff(env
);
2372 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2373 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2374 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2375 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2378 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2379 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2380 return CP_ACCESS_TRAP
;
2383 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2384 if (hcr
& HCR_E2H
) {
2385 if (timeridx
== GTIMER_PHYS
&&
2386 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2387 return CP_ACCESS_TRAP_EL2
;
2390 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2391 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2392 timeridx
== GTIMER_PHYS
&& !secure
&&
2393 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2394 return CP_ACCESS_TRAP_EL2
;
2400 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2401 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2402 timeridx
== GTIMER_PHYS
&& !secure
&&
2404 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2405 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2406 return CP_ACCESS_TRAP_EL2
;
2410 return CP_ACCESS_OK
;
2413 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2416 unsigned int cur_el
= arm_current_el(env
);
2417 bool secure
= arm_is_secure(env
);
2418 uint64_t hcr
= arm_hcr_el2_eff(env
);
2422 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2423 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2424 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2425 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2429 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2430 * EL0 if EL0[PV]TEN is zero.
2432 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2433 return CP_ACCESS_TRAP
;
2438 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2439 timeridx
== GTIMER_PHYS
&& !secure
) {
2440 if (hcr
& HCR_E2H
) {
2441 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2442 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2443 return CP_ACCESS_TRAP_EL2
;
2446 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2447 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2448 return CP_ACCESS_TRAP_EL2
;
2454 return CP_ACCESS_OK
;
2457 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2458 const ARMCPRegInfo
*ri
,
2461 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2464 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2465 const ARMCPRegInfo
*ri
,
2468 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2471 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2474 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2477 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2480 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2483 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2484 const ARMCPRegInfo
*ri
,
2487 /* The AArch64 register view of the secure physical timer is
2488 * always accessible from EL3, and configurably accessible from
2491 switch (arm_current_el(env
)) {
2493 if (!arm_is_secure(env
)) {
2494 return CP_ACCESS_TRAP
;
2496 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2497 return CP_ACCESS_TRAP_EL3
;
2499 return CP_ACCESS_OK
;
2502 return CP_ACCESS_TRAP
;
2504 return CP_ACCESS_OK
;
2506 g_assert_not_reached();
2510 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2512 ARMCPU
*cpu
= env_archcpu(env
);
2514 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2517 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2519 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2522 /* Timer enabled: calculate and set current ISTATUS, irq, and
2523 * reset timer to when ISTATUS next has to change
2525 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2526 cpu
->env
.cp15
.cntvoff_el2
: 0;
2527 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2528 /* Note that this must be unsigned 64 bit arithmetic: */
2529 int istatus
= count
- offset
>= gt
->cval
;
2533 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2535 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2536 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2539 /* Next transition is when count rolls back over to zero */
2540 nexttick
= UINT64_MAX
;
2542 /* Next transition is when we hit cval */
2543 nexttick
= gt
->cval
+ offset
;
2545 /* Note that the desired next expiry time might be beyond the
2546 * signed-64-bit range of a QEMUTimer -- in this case we just
2547 * set the timer for as far in the future as possible. When the
2548 * timer expires we will reset the timer for any remaining period.
2550 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2551 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2553 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2555 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2557 /* Timer disabled: ISTATUS and timer output always clear */
2559 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2560 timer_del(cpu
->gt_timer
[timeridx
]);
2561 trace_arm_gt_recalc_disabled(timeridx
);
2565 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2568 ARMCPU
*cpu
= env_archcpu(env
);
2570 timer_del(cpu
->gt_timer
[timeridx
]);
2573 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2575 return gt_get_countervalue(env
);
2578 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2582 switch (arm_current_el(env
)) {
2584 hcr
= arm_hcr_el2_eff(env
);
2585 if (hcr
& HCR_E2H
) {
2590 hcr
= arm_hcr_el2_eff(env
);
2591 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2597 return env
->cp15
.cntvoff_el2
;
2600 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2602 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2605 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2609 trace_arm_gt_cval_write(timeridx
, value
);
2610 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2611 gt_recalc_timer(env_archcpu(env
), timeridx
);
2614 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2617 uint64_t offset
= 0;
2621 case GTIMER_HYPVIRT
:
2622 offset
= gt_virt_cnt_offset(env
);
2626 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2627 (gt_get_countervalue(env
) - offset
));
2630 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2634 uint64_t offset
= 0;
2638 case GTIMER_HYPVIRT
:
2639 offset
= gt_virt_cnt_offset(env
);
2643 trace_arm_gt_tval_write(timeridx
, value
);
2644 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2645 sextract64(value
, 0, 32);
2646 gt_recalc_timer(env_archcpu(env
), timeridx
);
2649 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2653 ARMCPU
*cpu
= env_archcpu(env
);
2654 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2656 trace_arm_gt_ctl_write(timeridx
, value
);
2657 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2658 if ((oldval
^ value
) & 1) {
2659 /* Enable toggled */
2660 gt_recalc_timer(cpu
, timeridx
);
2661 } else if ((oldval
^ value
) & 2) {
2662 /* IMASK toggled: don't need to recalculate,
2663 * just set the interrupt line based on ISTATUS
2665 int irqstate
= (oldval
& 4) && !(value
& 2);
2667 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2668 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2672 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2674 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2677 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2680 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2683 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2685 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2688 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2691 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2694 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2697 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2700 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2702 switch (arm_mmu_idx(env
)) {
2703 case ARMMMUIdx_E20_0
:
2704 case ARMMMUIdx_E20_2
:
2705 case ARMMMUIdx_E20_2_PAN
:
2712 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2714 switch (arm_mmu_idx(env
)) {
2715 case ARMMMUIdx_E20_0
:
2716 case ARMMMUIdx_E20_2
:
2717 case ARMMMUIdx_E20_2_PAN
:
2718 return GTIMER_HYPVIRT
;
2724 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2725 const ARMCPRegInfo
*ri
)
2727 int timeridx
= gt_phys_redir_timeridx(env
);
2728 return env
->cp15
.c14_timer
[timeridx
].cval
;
2731 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2734 int timeridx
= gt_phys_redir_timeridx(env
);
2735 gt_cval_write(env
, ri
, timeridx
, value
);
2738 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2739 const ARMCPRegInfo
*ri
)
2741 int timeridx
= gt_phys_redir_timeridx(env
);
2742 return gt_tval_read(env
, ri
, timeridx
);
2745 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2748 int timeridx
= gt_phys_redir_timeridx(env
);
2749 gt_tval_write(env
, ri
, timeridx
, value
);
2752 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2753 const ARMCPRegInfo
*ri
)
2755 int timeridx
= gt_phys_redir_timeridx(env
);
2756 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2759 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2762 int timeridx
= gt_phys_redir_timeridx(env
);
2763 gt_ctl_write(env
, ri
, timeridx
, value
);
2766 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2768 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2771 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2774 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2777 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2779 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2782 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2785 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2788 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2791 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2794 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2797 ARMCPU
*cpu
= env_archcpu(env
);
2799 trace_arm_gt_cntvoff_write(value
);
2800 raw_write(env
, ri
, value
);
2801 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2804 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2805 const ARMCPRegInfo
*ri
)
2807 int timeridx
= gt_virt_redir_timeridx(env
);
2808 return env
->cp15
.c14_timer
[timeridx
].cval
;
2811 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2814 int timeridx
= gt_virt_redir_timeridx(env
);
2815 gt_cval_write(env
, ri
, timeridx
, value
);
2818 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2819 const ARMCPRegInfo
*ri
)
2821 int timeridx
= gt_virt_redir_timeridx(env
);
2822 return gt_tval_read(env
, ri
, timeridx
);
2825 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2828 int timeridx
= gt_virt_redir_timeridx(env
);
2829 gt_tval_write(env
, ri
, timeridx
, value
);
2832 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2833 const ARMCPRegInfo
*ri
)
2835 int timeridx
= gt_virt_redir_timeridx(env
);
2836 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2839 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2842 int timeridx
= gt_virt_redir_timeridx(env
);
2843 gt_ctl_write(env
, ri
, timeridx
, value
);
2846 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2848 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2851 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2854 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2857 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2859 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2862 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2865 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2868 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2871 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2874 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2876 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2879 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2882 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2885 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2887 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2890 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2893 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2896 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2899 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2902 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2904 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2907 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2910 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2913 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2915 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2918 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2921 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2924 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2927 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2930 void arm_gt_ptimer_cb(void *opaque
)
2932 ARMCPU
*cpu
= opaque
;
2934 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2937 void arm_gt_vtimer_cb(void *opaque
)
2939 ARMCPU
*cpu
= opaque
;
2941 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2944 void arm_gt_htimer_cb(void *opaque
)
2946 ARMCPU
*cpu
= opaque
;
2948 gt_recalc_timer(cpu
, GTIMER_HYP
);
2951 void arm_gt_stimer_cb(void *opaque
)
2953 ARMCPU
*cpu
= opaque
;
2955 gt_recalc_timer(cpu
, GTIMER_SEC
);
2958 void arm_gt_hvtimer_cb(void *opaque
)
2960 ARMCPU
*cpu
= opaque
;
2962 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
2965 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2967 ARMCPU
*cpu
= env_archcpu(env
);
2969 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
2972 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2973 /* Note that CNTFRQ is purely reads-as-written for the benefit
2974 * of software; writing it doesn't actually change the timer frequency.
2975 * Our reset value matches the fixed frequency we implement the timer at.
2977 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2978 .type
= ARM_CP_ALIAS
,
2979 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2980 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2982 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2983 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2984 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2985 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2986 .resetfn
= arm_gt_cntfrq_reset
,
2988 /* overall control: mostly access permissions */
2989 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2990 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2992 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2995 /* per-timer control */
2996 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2997 .secure
= ARM_CP_SECSTATE_NS
,
2998 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2999 .accessfn
= gt_ptimer_access
,
3000 .fieldoffset
= offsetoflow32(CPUARMState
,
3001 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3002 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3003 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3005 { .name
= "CNTP_CTL_S",
3006 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3007 .secure
= ARM_CP_SECSTATE_S
,
3008 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3009 .accessfn
= gt_ptimer_access
,
3010 .fieldoffset
= offsetoflow32(CPUARMState
,
3011 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3012 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3014 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3015 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3016 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3017 .accessfn
= gt_ptimer_access
,
3018 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3020 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3021 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3023 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3024 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3025 .accessfn
= gt_vtimer_access
,
3026 .fieldoffset
= offsetoflow32(CPUARMState
,
3027 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3028 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3029 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3031 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3032 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3033 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3034 .accessfn
= gt_vtimer_access
,
3035 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3037 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3038 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3040 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3041 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3042 .secure
= ARM_CP_SECSTATE_NS
,
3043 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3044 .accessfn
= gt_ptimer_access
,
3045 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3047 { .name
= "CNTP_TVAL_S",
3048 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3049 .secure
= ARM_CP_SECSTATE_S
,
3050 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3051 .accessfn
= gt_ptimer_access
,
3052 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3054 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3055 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3056 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3057 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3058 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3060 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3061 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3062 .accessfn
= gt_vtimer_access
,
3063 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3065 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3066 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3067 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3068 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3069 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3071 /* The counter itself */
3072 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3073 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3074 .accessfn
= gt_pct_access
,
3075 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3077 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3078 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3079 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3080 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3082 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3083 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3084 .accessfn
= gt_vct_access
,
3085 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3087 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3088 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3089 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3090 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3092 /* Comparison value, indicating when the timer goes off */
3093 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3094 .secure
= ARM_CP_SECSTATE_NS
,
3096 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3097 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3098 .accessfn
= gt_ptimer_access
,
3099 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3100 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3102 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3103 .secure
= ARM_CP_SECSTATE_S
,
3105 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3107 .accessfn
= gt_ptimer_access
,
3108 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3110 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3111 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3114 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3115 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3116 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3117 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3119 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3121 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3122 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3123 .accessfn
= gt_vtimer_access
,
3124 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3125 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3127 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3128 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3131 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3132 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3133 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3134 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3136 /* Secure timer -- this is actually restricted to only EL3
3137 * and configurably Secure-EL1 via the accessfn.
3139 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3140 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3141 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3142 .accessfn
= gt_stimer_access
,
3143 .readfn
= gt_sec_tval_read
,
3144 .writefn
= gt_sec_tval_write
,
3145 .resetfn
= gt_sec_timer_reset
,
3147 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3148 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3149 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3150 .accessfn
= gt_stimer_access
,
3151 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3153 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3155 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3156 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3157 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3158 .accessfn
= gt_stimer_access
,
3159 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3160 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3165 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3168 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3169 return CP_ACCESS_TRAP
;
3171 return CP_ACCESS_OK
;
3176 /* In user-mode most of the generic timer registers are inaccessible
3177 * however modern kernels (4.12+) allow access to cntvct_el0
3180 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3182 ARMCPU
*cpu
= env_archcpu(env
);
3184 /* Currently we have no support for QEMUTimer in linux-user so we
3185 * can't call gt_get_countervalue(env), instead we directly
3186 * call the lower level functions.
3188 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3191 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3192 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3193 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3194 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3196 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3198 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3199 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3200 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3201 .readfn
= gt_virt_cnt_read
,
3208 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3210 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3211 raw_write(env
, ri
, value
);
3212 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3213 raw_write(env
, ri
, value
& 0xfffff6ff);
3215 raw_write(env
, ri
, value
& 0xfffff1ff);
3219 #ifndef CONFIG_USER_ONLY
3220 /* get_phys_addr() isn't present for user-mode-only targets */
3222 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3226 /* The ATS12NSO* operations must trap to EL3 if executed in
3227 * Secure EL1 (which can only happen if EL3 is AArch64).
3228 * They are simply UNDEF if executed from NS EL1.
3229 * They function normally from EL2 or EL3.
3231 if (arm_current_el(env
) == 1) {
3232 if (arm_is_secure_below_el3(env
)) {
3233 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3235 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3238 return CP_ACCESS_OK
;
3241 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3242 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3245 target_ulong page_size
;
3249 bool format64
= false;
3250 MemTxAttrs attrs
= {};
3251 ARMMMUFaultInfo fi
= {};
3252 ARMCacheAttrs cacheattrs
= {};
3254 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3255 &prot
, &page_size
, &fi
, &cacheattrs
);
3259 * Some kinds of translation fault must cause exceptions rather
3260 * than being reported in the PAR.
3262 int current_el
= arm_current_el(env
);
3264 uint32_t syn
, fsr
, fsc
;
3265 bool take_exc
= false;
3267 if (fi
.s1ptw
&& current_el
== 1 && !arm_is_secure(env
)
3268 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3270 * Synchronous stage 2 fault on an access made as part of the
3271 * translation table walk for AT S1E0* or AT S1E1* insn
3272 * executed from NS EL1. If this is a synchronous external abort
3273 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3274 * to EL3. Otherwise the fault is taken as an exception to EL2,
3275 * and HPFAR_EL2 holds the faulting IPA.
3277 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3278 (env
->cp15
.scr_el3
& SCR_EA
)) {
3281 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3285 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3287 * Synchronous external aborts during a translation table walk
3288 * are taken as Data Abort exceptions.
3291 if (current_el
== 3) {
3297 target_el
= exception_target_el(env
);
3303 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3304 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3305 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3306 fsr
= arm_fi_to_lfsc(&fi
);
3307 fsc
= extract32(fsr
, 0, 6);
3309 fsr
= arm_fi_to_sfsc(&fi
);
3313 * Report exception with ESR indicating a fault due to a
3314 * translation table walk for a cache maintenance instruction.
3316 syn
= syn_data_abort_no_iss(current_el
== target_el
,
3317 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3318 env
->exception
.vaddress
= value
;
3319 env
->exception
.fsr
= fsr
;
3320 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3326 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3329 * * TTBCR.EAE determines whether the result is returned using the
3330 * 32-bit or the 64-bit PAR format
3331 * * Instructions executed in Hyp mode always use the 64bit format
3333 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3334 * * The Non-secure TTBCR.EAE bit is set to 1
3335 * * The implementation includes EL2, and the value of HCR.VM is 1
3337 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3339 * ATS1Hx always uses the 64bit format.
3341 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3343 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3344 if (mmu_idx
== ARMMMUIdx_E10_0
||
3345 mmu_idx
== ARMMMUIdx_E10_1
||
3346 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3347 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3349 format64
|= arm_current_el(env
) == 2;
3355 /* Create a 64-bit PAR */
3356 par64
= (1 << 11); /* LPAE bit always set */
3358 par64
|= phys_addr
& ~0xfffULL
;
3359 if (!attrs
.secure
) {
3360 par64
|= (1 << 9); /* NS */
3362 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3363 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3365 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3368 par64
|= (fsr
& 0x3f) << 1; /* FS */
3370 par64
|= (1 << 9); /* S */
3373 par64
|= (1 << 8); /* PTW */
3377 /* fsr is a DFSR/IFSR value for the short descriptor
3378 * translation table format (with WnR always clear).
3379 * Convert it to a 32-bit PAR.
3382 /* We do not set any attribute bits in the PAR */
3383 if (page_size
== (1 << 24)
3384 && arm_feature(env
, ARM_FEATURE_V7
)) {
3385 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3387 par64
= phys_addr
& 0xfffff000;
3389 if (!attrs
.secure
) {
3390 par64
|= (1 << 9); /* NS */
3393 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3395 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3396 ((fsr
& 0xf) << 1) | 1;
3402 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3404 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3407 int el
= arm_current_el(env
);
3408 bool secure
= arm_is_secure_below_el3(env
);
3410 switch (ri
->opc2
& 6) {
3412 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
3415 mmu_idx
= ARMMMUIdx_SE3
;
3418 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3421 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_Stage1_E1
;
3424 g_assert_not_reached();
3428 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3431 mmu_idx
= ARMMMUIdx_SE10_0
;
3434 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3437 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_Stage1_E0
;
3440 g_assert_not_reached();
3444 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3445 mmu_idx
= ARMMMUIdx_E10_1
;
3448 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3449 mmu_idx
= ARMMMUIdx_E10_0
;
3452 g_assert_not_reached();
3455 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3457 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3460 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3463 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3466 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3468 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3471 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3474 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3475 return CP_ACCESS_TRAP
;
3477 return CP_ACCESS_OK
;
3480 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3483 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3485 int secure
= arm_is_secure_below_el3(env
);
3487 switch (ri
->opc2
& 6) {
3490 case 0: /* AT S1E1R, AT S1E1W */
3491 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_Stage1_E1
;
3493 case 4: /* AT S1E2R, AT S1E2W */
3494 mmu_idx
= ARMMMUIdx_E2
;
3496 case 6: /* AT S1E3R, AT S1E3W */
3497 mmu_idx
= ARMMMUIdx_SE3
;
3500 g_assert_not_reached();
3503 case 2: /* AT S1E0R, AT S1E0W */
3504 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_Stage1_E0
;
3506 case 4: /* AT S12E1R, AT S12E1W */
3507 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3509 case 6: /* AT S12E0R, AT S12E0W */
3510 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3513 g_assert_not_reached();
3516 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3520 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3521 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3522 .access
= PL1_RW
, .resetvalue
= 0,
3523 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3524 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3525 .writefn
= par_write
},
3526 #ifndef CONFIG_USER_ONLY
3527 /* This underdecoding is safe because the reginfo is NO_RAW. */
3528 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3529 .access
= PL1_W
, .accessfn
= ats_access
,
3530 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3535 /* Return basic MPU access permission bits. */
3536 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3543 for (i
= 0; i
< 16; i
+= 2) {
3544 ret
|= (val
>> i
) & mask
;
3550 /* Pad basic MPU access permission bits to extended format. */
3551 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3558 for (i
= 0; i
< 16; i
+= 2) {
3559 ret
|= (val
& mask
) << i
;
3565 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3568 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3571 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3573 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3576 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3579 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3582 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3584 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3587 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3589 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3595 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3599 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3602 ARMCPU
*cpu
= env_archcpu(env
);
3603 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3609 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3610 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3614 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3617 ARMCPU
*cpu
= env_archcpu(env
);
3618 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3620 if (value
>= nrgs
) {
3621 qemu_log_mask(LOG_GUEST_ERROR
,
3622 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3623 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3627 raw_write(env
, ri
, value
);
3630 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3631 /* Reset for all these registers is handled in arm_cpu_reset(),
3632 * because the PMSAv7 is also used by M-profile CPUs, which do
3633 * not register cpregs but still need the state to be reset.
3635 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3636 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3637 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3638 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3639 .resetfn
= arm_cp_reset_ignore
},
3640 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3641 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3642 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3643 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3644 .resetfn
= arm_cp_reset_ignore
},
3645 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3646 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3647 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3648 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3649 .resetfn
= arm_cp_reset_ignore
},
3650 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3652 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3653 .writefn
= pmsav7_rgnr_write
,
3654 .resetfn
= arm_cp_reset_ignore
},
3658 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3659 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3660 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3661 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3662 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3663 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3664 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3665 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3666 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3667 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3669 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3671 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3673 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3675 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3677 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3678 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3680 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3681 /* Protection region base and size registers */
3682 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3683 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3684 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3685 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3686 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3687 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3688 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3689 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3690 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3691 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3692 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3693 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3694 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3695 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3696 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3697 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3698 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3699 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3700 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3701 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3702 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3703 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3704 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3705 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3709 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3712 TCR
*tcr
= raw_ptr(env
, ri
);
3713 int maskshift
= extract32(value
, 0, 3);
3715 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3716 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3717 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3718 * using Long-desciptor translation table format */
3719 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3720 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3721 /* In an implementation that includes the Security Extensions
3722 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3723 * Short-descriptor translation table format.
3725 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3731 /* Update the masks corresponding to the TCR bank being written
3732 * Note that we always calculate mask and base_mask, but
3733 * they are only used for short-descriptor tables (ie if EAE is 0);
3734 * for long-descriptor tables the TCR fields are used differently
3735 * and the mask and base_mask values are meaningless.
3737 tcr
->raw_tcr
= value
;
3738 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3739 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3742 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3745 ARMCPU
*cpu
= env_archcpu(env
);
3746 TCR
*tcr
= raw_ptr(env
, ri
);
3748 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3749 /* With LPAE the TTBCR could result in a change of ASID
3750 * via the TTBCR.A1 bit, so do a TLB flush.
3752 tlb_flush(CPU(cpu
));
3754 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3755 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3756 vmsa_ttbcr_raw_write(env
, ri
, value
);
3759 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3761 TCR
*tcr
= raw_ptr(env
, ri
);
3763 /* Reset both the TCR as well as the masks corresponding to the bank of
3764 * the TCR being reset.
3768 tcr
->base_mask
= 0xffffc000u
;
3771 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3774 ARMCPU
*cpu
= env_archcpu(env
);
3775 TCR
*tcr
= raw_ptr(env
, ri
);
3777 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3778 tlb_flush(CPU(cpu
));
3779 tcr
->raw_tcr
= value
;
3782 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3785 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3786 if (cpreg_field_is_64bit(ri
) &&
3787 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3788 ARMCPU
*cpu
= env_archcpu(env
);
3789 tlb_flush(CPU(cpu
));
3791 raw_write(env
, ri
, value
);
3794 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3798 * If we are running with E2&0 regime, then an ASID is active.
3799 * Flush if that might be changing. Note we're not checking
3800 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3801 * holds the active ASID, only checking the field that might.
3803 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3804 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3805 tlb_flush_by_mmuidx(env_cpu(env
),
3806 ARMMMUIdxBit_E20_2
|
3807 ARMMMUIdxBit_E20_2_PAN
|
3808 ARMMMUIdxBit_E20_0
);
3810 raw_write(env
, ri
, value
);
3813 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3816 ARMCPU
*cpu
= env_archcpu(env
);
3817 CPUState
*cs
= CPU(cpu
);
3820 * A change in VMID to the stage2 page table (Stage2) invalidates
3821 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3823 if (raw_read(env
, ri
) != value
) {
3824 tlb_flush_by_mmuidx(cs
,
3825 ARMMMUIdxBit_E10_1
|
3826 ARMMMUIdxBit_E10_1_PAN
|
3827 ARMMMUIdxBit_E10_0
|
3828 ARMMMUIdxBit_Stage2
);
3829 raw_write(env
, ri
, value
);
3833 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3834 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3835 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3836 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3837 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3838 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3839 .access
= PL1_RW
, .resetvalue
= 0,
3840 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3841 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3842 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3843 .access
= PL1_RW
, .resetvalue
= 0,
3844 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3845 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3846 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3847 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3848 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3853 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3854 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3855 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3857 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3858 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3859 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3860 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3861 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3862 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3863 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3864 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3865 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3866 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3867 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3868 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3869 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3870 .access
= PL1_RW
, .writefn
= vmsa_tcr_el12_write
,
3871 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3872 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3873 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3874 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3875 .raw_writefn
= vmsa_ttbcr_raw_write
,
3876 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3877 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3881 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3882 * qemu tlbs nor adjusting cached masks.
3884 static const ARMCPRegInfo ttbcr2_reginfo
= {
3885 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3886 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3887 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3888 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
3891 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3894 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3895 /* The OS_TYPE bit in this register changes the reported CPUID! */
3896 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3897 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3900 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3903 env
->cp15
.c15_threadid
= value
& 0xffff;
3906 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3909 /* Wait-for-interrupt (deprecated) */
3910 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3913 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3916 /* On OMAP there are registers indicating the max/min index of dcache lines
3917 * containing a dirty line; cache flush operations have to reset these.
3919 env
->cp15
.c15_i_max
= 0x000;
3920 env
->cp15
.c15_i_min
= 0xff0;
3923 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3924 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3925 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3926 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3928 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3929 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3930 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3932 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3933 .writefn
= omap_ticonfig_write
},
3934 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3936 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3937 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3938 .access
= PL1_RW
, .resetvalue
= 0xff0,
3939 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3940 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3942 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3943 .writefn
= omap_threadid_write
},
3944 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3945 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3946 .type
= ARM_CP_NO_RAW
,
3947 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3948 /* TODO: Peripheral port remap register:
3949 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3950 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3953 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3954 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3955 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3956 .writefn
= omap_cachemaint_write
},
3957 { .name
= "C9", .cp
= 15, .crn
= 9,
3958 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3959 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3963 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3966 env
->cp15
.c15_cpar
= value
& 0x3fff;
3969 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3970 { .name
= "XSCALE_CPAR",
3971 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3972 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3973 .writefn
= xscale_cpar_write
, },
3974 { .name
= "XSCALE_AUXCR",
3975 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3976 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3978 /* XScale specific cache-lockdown: since we have no cache we NOP these
3979 * and hope the guest does not really rely on cache behaviour.
3981 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3982 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3983 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3984 { .name
= "XSCALE_UNLOCK_ICACHE",
3985 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3986 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3987 { .name
= "XSCALE_DCACHE_LOCK",
3988 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3989 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3990 { .name
= "XSCALE_UNLOCK_DCACHE",
3991 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3992 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3996 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3997 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3998 * implementation of this implementation-defined space.
3999 * Ideally this should eventually disappear in favour of actually
4000 * implementing the correct behaviour for all cores.
4002 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4003 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4005 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4010 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4011 /* Cache status: RAZ because we have no cache so it's always clean */
4012 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4013 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4018 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4019 /* We never have a a block transfer operation in progress */
4020 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4021 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4023 /* The cache ops themselves: these all NOP for QEMU */
4024 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4025 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4026 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4027 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4028 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4029 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4030 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4031 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4032 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4033 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4034 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4035 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4039 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4040 /* The cache test-and-clean instructions always return (1 << 30)
4041 * to indicate that there are no dirty cache lines.
4043 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4044 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4045 .resetvalue
= (1 << 30) },
4046 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4047 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4048 .resetvalue
= (1 << 30) },
4052 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4053 /* Ignore ReadBuffer accesses */
4054 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4055 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4056 .access
= PL1_RW
, .resetvalue
= 0,
4057 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4061 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4063 ARMCPU
*cpu
= env_archcpu(env
);
4064 unsigned int cur_el
= arm_current_el(env
);
4065 bool secure
= arm_is_secure(env
);
4067 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
4068 return env
->cp15
.vpidr_el2
;
4070 return raw_read(env
, ri
);
4073 static uint64_t mpidr_read_val(CPUARMState
*env
)
4075 ARMCPU
*cpu
= env_archcpu(env
);
4076 uint64_t mpidr
= cpu
->mp_affinity
;
4078 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4079 mpidr
|= (1U << 31);
4080 /* Cores which are uniprocessor (non-coherent)
4081 * but still implement the MP extensions set
4082 * bit 30. (For instance, Cortex-R5).
4084 if (cpu
->mp_is_up
) {
4085 mpidr
|= (1u << 30);
4091 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4093 unsigned int cur_el
= arm_current_el(env
);
4094 bool secure
= arm_is_secure(env
);
4096 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
4097 return env
->cp15
.vmpidr_el2
;
4099 return mpidr_read_val(env
);
4102 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4104 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4105 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4106 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
4108 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4109 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4110 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
4112 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4113 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4114 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4115 offsetof(CPUARMState
, cp15
.par_ns
)} },
4116 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4117 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4118 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4119 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4120 .writefn
= vmsa_ttbr_write
, },
4121 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4122 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4123 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4124 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4125 .writefn
= vmsa_ttbr_write
, },
4129 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4131 return vfp_get_fpcr(env
);
4134 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4137 vfp_set_fpcr(env
, value
);
4140 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4142 return vfp_get_fpsr(env
);
4145 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4148 vfp_set_fpsr(env
, value
);
4151 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4154 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4155 return CP_ACCESS_TRAP
;
4157 return CP_ACCESS_OK
;
4160 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4163 env
->daif
= value
& PSTATE_DAIF
;
4166 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4168 return env
->pstate
& PSTATE_PAN
;
4171 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4174 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4177 static const ARMCPRegInfo pan_reginfo
= {
4178 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4179 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4180 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4181 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4184 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
4185 const ARMCPRegInfo
*ri
,
4188 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
4189 * SCTLR_EL1.UCI is set.
4191 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4192 return CP_ACCESS_TRAP
;
4194 return CP_ACCESS_OK
;
4197 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4198 * Page D4-1736 (DDI0487A.b)
4201 static int vae1_tlbmask(CPUARMState
*env
)
4203 /* Since we exclude secure first, we may read HCR_EL2 directly. */
4204 if (arm_is_secure_below_el3(env
)) {
4205 return ARMMMUIdxBit_SE10_1
|
4206 ARMMMUIdxBit_SE10_1_PAN
|
4207 ARMMMUIdxBit_SE10_0
;
4208 } else if ((env
->cp15
.hcr_el2
& (HCR_E2H
| HCR_TGE
))
4209 == (HCR_E2H
| HCR_TGE
)) {
4210 return ARMMMUIdxBit_E20_2
|
4211 ARMMMUIdxBit_E20_2_PAN
|
4214 return ARMMMUIdxBit_E10_1
|
4215 ARMMMUIdxBit_E10_1_PAN
|
4220 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4223 CPUState
*cs
= env_cpu(env
);
4224 int mask
= vae1_tlbmask(env
);
4226 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4229 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4232 CPUState
*cs
= env_cpu(env
);
4233 int mask
= vae1_tlbmask(env
);
4235 if (tlb_force_broadcast(env
)) {
4236 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4238 tlb_flush_by_mmuidx(cs
, mask
);
4242 static int alle1_tlbmask(CPUARMState
*env
)
4245 * Note that the 'ALL' scope must invalidate both stage 1 and
4246 * stage 2 translations, whereas most other scopes only invalidate
4247 * stage 1 translations.
4249 if (arm_is_secure_below_el3(env
)) {
4250 return ARMMMUIdxBit_SE10_1
|
4251 ARMMMUIdxBit_SE10_1_PAN
|
4252 ARMMMUIdxBit_SE10_0
;
4253 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4254 return ARMMMUIdxBit_E10_1
|
4255 ARMMMUIdxBit_E10_1_PAN
|
4256 ARMMMUIdxBit_E10_0
|
4257 ARMMMUIdxBit_Stage2
;
4259 return ARMMMUIdxBit_E10_1
|
4260 ARMMMUIdxBit_E10_1_PAN
|
4265 static int e2_tlbmask(CPUARMState
*env
)
4267 /* TODO: ARMv8.4-SecEL2 */
4268 return ARMMMUIdxBit_E20_0
|
4269 ARMMMUIdxBit_E20_2
|
4270 ARMMMUIdxBit_E20_2_PAN
|
4274 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4277 CPUState
*cs
= env_cpu(env
);
4278 int mask
= alle1_tlbmask(env
);
4280 tlb_flush_by_mmuidx(cs
, mask
);
4283 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4286 CPUState
*cs
= env_cpu(env
);
4287 int mask
= e2_tlbmask(env
);
4289 tlb_flush_by_mmuidx(cs
, mask
);
4292 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4295 ARMCPU
*cpu
= env_archcpu(env
);
4296 CPUState
*cs
= CPU(cpu
);
4298 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4301 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4304 CPUState
*cs
= env_cpu(env
);
4305 int mask
= alle1_tlbmask(env
);
4307 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4310 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4313 CPUState
*cs
= env_cpu(env
);
4314 int mask
= e2_tlbmask(env
);
4316 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4319 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4322 CPUState
*cs
= env_cpu(env
);
4324 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4327 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4330 /* Invalidate by VA, EL2
4331 * Currently handles both VAE2 and VALE2, since we don't support
4332 * flush-last-level-only.
4334 CPUState
*cs
= env_cpu(env
);
4335 int mask
= e2_tlbmask(env
);
4336 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4338 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4341 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4344 /* Invalidate by VA, EL3
4345 * Currently handles both VAE3 and VALE3, since we don't support
4346 * flush-last-level-only.
4348 ARMCPU
*cpu
= env_archcpu(env
);
4349 CPUState
*cs
= CPU(cpu
);
4350 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4352 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4355 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4358 CPUState
*cs
= env_cpu(env
);
4359 int mask
= vae1_tlbmask(env
);
4360 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4362 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4365 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4368 /* Invalidate by VA, EL1&0 (AArch64 version).
4369 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4370 * since we don't support flush-for-specific-ASID-only or
4371 * flush-last-level-only.
4373 CPUState
*cs
= env_cpu(env
);
4374 int mask
= vae1_tlbmask(env
);
4375 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4377 if (tlb_force_broadcast(env
)) {
4378 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4380 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4384 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4387 CPUState
*cs
= env_cpu(env
);
4388 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4390 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4394 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4397 CPUState
*cs
= env_cpu(env
);
4398 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4400 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4404 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4407 /* Invalidate by IPA. This has to invalidate any structures that
4408 * contain only stage 2 translation information, but does not need
4409 * to apply to structures that contain combined stage 1 and stage 2
4410 * translation information.
4411 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
4413 ARMCPU
*cpu
= env_archcpu(env
);
4414 CPUState
*cs
= CPU(cpu
);
4417 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4421 pageaddr
= sextract64(value
<< 12, 0, 48);
4423 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
4426 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4429 CPUState
*cs
= env_cpu(env
);
4432 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4436 pageaddr
= sextract64(value
<< 12, 0, 48);
4438 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4439 ARMMMUIdxBit_Stage2
);
4442 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4445 int cur_el
= arm_current_el(env
);
4448 uint64_t hcr
= arm_hcr_el2_eff(env
);
4451 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4452 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4453 return CP_ACCESS_TRAP_EL2
;
4456 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4457 return CP_ACCESS_TRAP
;
4459 if (hcr
& HCR_TDZ
) {
4460 return CP_ACCESS_TRAP_EL2
;
4463 } else if (hcr
& HCR_TDZ
) {
4464 return CP_ACCESS_TRAP_EL2
;
4467 return CP_ACCESS_OK
;
4470 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4472 ARMCPU
*cpu
= env_archcpu(env
);
4473 int dzp_bit
= 1 << 4;
4475 /* DZP indicates whether DC ZVA access is allowed */
4476 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4479 return cpu
->dcz_blocksize
| dzp_bit
;
4482 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4485 if (!(env
->pstate
& PSTATE_SP
)) {
4486 /* Access to SP_EL0 is undefined if it's being used as
4487 * the stack pointer.
4489 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4491 return CP_ACCESS_OK
;
4494 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4496 return env
->pstate
& PSTATE_SP
;
4499 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4501 update_spsel(env
, val
);
4504 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4507 ARMCPU
*cpu
= env_archcpu(env
);
4509 if (raw_read(env
, ri
) == value
) {
4510 /* Skip the TLB flush if nothing actually changed; Linux likes
4511 * to do a lot of pointless SCTLR writes.
4516 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4517 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4521 raw_write(env
, ri
, value
);
4522 /* ??? Lots of these bits are not implemented. */
4523 /* This may enable/disable the MMU, so do a TLB flush. */
4524 tlb_flush(CPU(cpu
));
4526 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4528 * Normally we would always end the TB on an SCTLR write; see the
4529 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4530 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4531 * of hflags from the translator, so do it here.
4533 arm_rebuild_hflags(env
);
4537 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4540 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4541 return CP_ACCESS_TRAP_FP_EL2
;
4543 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4544 return CP_ACCESS_TRAP_FP_EL3
;
4546 return CP_ACCESS_OK
;
4549 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4552 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4555 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4556 /* Minimal set of EL0-visible registers. This will need to be expanded
4557 * significantly for system emulation of AArch64 CPUs.
4559 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4560 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4561 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4562 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4563 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4564 .type
= ARM_CP_NO_RAW
,
4565 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4566 .fieldoffset
= offsetof(CPUARMState
, daif
),
4567 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4568 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4569 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4570 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4571 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4572 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4573 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4574 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4575 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4576 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4577 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4578 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4579 .readfn
= aa64_dczid_read
},
4580 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4581 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4582 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4583 #ifndef CONFIG_USER_ONLY
4584 /* Avoid overhead of an access check that always passes in user-mode */
4585 .accessfn
= aa64_zva_access
,
4588 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4589 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4590 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4591 /* Cache ops: all NOPs since we don't emulate caches */
4592 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4593 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4594 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4595 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4596 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4597 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4598 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4599 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4600 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4601 .accessfn
= aa64_cacheop_access
},
4602 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4603 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4604 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4605 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4606 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4607 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4608 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4609 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4610 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4611 .accessfn
= aa64_cacheop_access
},
4612 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4613 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4614 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4615 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4616 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4617 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4618 .accessfn
= aa64_cacheop_access
},
4619 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4620 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4621 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4622 .accessfn
= aa64_cacheop_access
},
4623 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4624 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4625 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4626 /* TLBI operations */
4627 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4628 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4629 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4630 .writefn
= tlbi_aa64_vmalle1is_write
},
4631 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4632 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4633 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4634 .writefn
= tlbi_aa64_vae1is_write
},
4635 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4636 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4637 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4638 .writefn
= tlbi_aa64_vmalle1is_write
},
4639 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4640 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4641 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4642 .writefn
= tlbi_aa64_vae1is_write
},
4643 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4644 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4645 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4646 .writefn
= tlbi_aa64_vae1is_write
},
4647 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4648 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4649 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4650 .writefn
= tlbi_aa64_vae1is_write
},
4651 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4652 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4653 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4654 .writefn
= tlbi_aa64_vmalle1_write
},
4655 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4656 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4657 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4658 .writefn
= tlbi_aa64_vae1_write
},
4659 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4660 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4661 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4662 .writefn
= tlbi_aa64_vmalle1_write
},
4663 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4664 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4665 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4666 .writefn
= tlbi_aa64_vae1_write
},
4667 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4668 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4669 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4670 .writefn
= tlbi_aa64_vae1_write
},
4671 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4672 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4673 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4674 .writefn
= tlbi_aa64_vae1_write
},
4675 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4676 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4677 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4678 .writefn
= tlbi_aa64_ipas2e1is_write
},
4679 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4680 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4681 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4682 .writefn
= tlbi_aa64_ipas2e1is_write
},
4683 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4684 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4685 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4686 .writefn
= tlbi_aa64_alle1is_write
},
4687 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4688 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4689 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4690 .writefn
= tlbi_aa64_alle1is_write
},
4691 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4692 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4693 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4694 .writefn
= tlbi_aa64_ipas2e1_write
},
4695 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4696 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4697 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4698 .writefn
= tlbi_aa64_ipas2e1_write
},
4699 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4700 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4701 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4702 .writefn
= tlbi_aa64_alle1_write
},
4703 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4704 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4705 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4706 .writefn
= tlbi_aa64_alle1is_write
},
4707 #ifndef CONFIG_USER_ONLY
4708 /* 64 bit address translation operations */
4709 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4710 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4711 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4712 .writefn
= ats_write64
},
4713 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4714 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4715 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4716 .writefn
= ats_write64
},
4717 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4718 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4719 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4720 .writefn
= ats_write64
},
4721 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4722 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4723 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4724 .writefn
= ats_write64
},
4725 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4726 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4727 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4728 .writefn
= ats_write64
},
4729 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4730 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4731 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4732 .writefn
= ats_write64
},
4733 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4734 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4735 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4736 .writefn
= ats_write64
},
4737 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4738 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4739 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4740 .writefn
= ats_write64
},
4741 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4742 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4743 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4744 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4745 .writefn
= ats_write64
},
4746 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4747 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4748 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4749 .writefn
= ats_write64
},
4750 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4751 .type
= ARM_CP_ALIAS
,
4752 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4753 .access
= PL1_RW
, .resetvalue
= 0,
4754 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4755 .writefn
= par_write
},
4757 /* TLB invalidate last level of translation table walk */
4758 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4759 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
4760 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4761 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
4762 .writefn
= tlbimvaa_is_write
},
4763 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4764 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
4765 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4766 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
4767 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4768 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4769 .writefn
= tlbimva_hyp_write
},
4770 { .name
= "TLBIMVALHIS",
4771 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4772 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4773 .writefn
= tlbimva_hyp_is_write
},
4774 { .name
= "TLBIIPAS2",
4775 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4776 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4777 .writefn
= tlbiipas2_write
},
4778 { .name
= "TLBIIPAS2IS",
4779 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4780 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4781 .writefn
= tlbiipas2_is_write
},
4782 { .name
= "TLBIIPAS2L",
4783 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4784 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4785 .writefn
= tlbiipas2_write
},
4786 { .name
= "TLBIIPAS2LIS",
4787 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4788 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4789 .writefn
= tlbiipas2_is_write
},
4790 /* 32 bit cache operations */
4791 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4792 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4793 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4794 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4795 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4796 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4797 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4798 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4799 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4800 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4801 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4802 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4803 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4804 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4805 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4806 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4807 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4808 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4809 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4810 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4811 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4812 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4813 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4814 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4815 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4816 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4817 /* MMU Domain access control / MPU write buffer control */
4818 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4819 .access
= PL1_RW
, .resetvalue
= 0,
4820 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4821 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4822 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4823 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4824 .type
= ARM_CP_ALIAS
,
4825 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4827 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4828 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4829 .type
= ARM_CP_ALIAS
,
4830 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4832 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4833 /* We rely on the access checks not allowing the guest to write to the
4834 * state field when SPSel indicates that it's being used as the stack
4837 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4838 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4839 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
4840 .type
= ARM_CP_ALIAS
,
4841 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
4842 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
4843 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
4844 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4845 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
4846 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
4847 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
4848 .type
= ARM_CP_NO_RAW
,
4849 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
4850 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
4851 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
4852 .type
= ARM_CP_ALIAS
,
4853 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
4854 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
4855 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
4856 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
4857 .access
= PL2_RW
, .resetvalue
= 0,
4858 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4859 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
4860 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
4861 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
4862 .access
= PL2_RW
, .resetvalue
= 0,
4863 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
4864 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
4865 .type
= ARM_CP_ALIAS
,
4866 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
4868 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
4869 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
4870 .type
= ARM_CP_ALIAS
,
4871 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
4873 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
4874 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
4875 .type
= ARM_CP_ALIAS
,
4876 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
4878 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
4879 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
4880 .type
= ARM_CP_ALIAS
,
4881 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
4883 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
4884 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
4885 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
4887 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
4888 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
4889 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
4890 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4891 .writefn
= sdcr_write
,
4892 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
4896 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4897 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
4898 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4899 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4901 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
4902 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4903 .type
= ARM_CP_NO_RAW
,
4904 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4906 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4907 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4908 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4909 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4910 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4911 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4913 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4914 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4915 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4916 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4917 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4918 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4919 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4921 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4922 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4923 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4924 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4925 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4926 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4928 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4929 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4930 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4932 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4933 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4934 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4936 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4937 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4938 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4940 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4941 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4942 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4943 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4944 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4945 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4946 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4947 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4948 .cp
= 15, .opc1
= 6, .crm
= 2,
4949 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4950 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
4951 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4952 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4953 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4954 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4955 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4956 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4957 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4958 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4959 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4960 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4961 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4962 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4963 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4964 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4966 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4967 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4968 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4969 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4970 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4971 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4972 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4973 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4975 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4976 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4977 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4978 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4979 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4981 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4982 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4983 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4984 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4985 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4986 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4987 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4988 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4989 .access
= PL2_RW
, .accessfn
= access_tda
,
4990 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4991 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4992 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4993 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4994 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4995 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4996 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4997 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4998 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4999 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5000 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5001 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5002 .type
= ARM_CP_CONST
,
5003 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5004 .access
= PL2_RW
, .resetvalue
= 0 },
5008 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5009 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
5010 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5011 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5013 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5017 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5019 ARMCPU
*cpu
= env_archcpu(env
);
5020 /* Begin with bits defined in base ARMv8.0. */
5021 uint64_t valid_mask
= MAKE_64BIT_MASK(0, 34);
5023 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5024 valid_mask
&= ~HCR_HCD
;
5025 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5026 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5027 * However, if we're using the SMC PSCI conduit then QEMU is
5028 * effectively acting like EL3 firmware and so the guest at
5029 * EL2 should retain the ability to prevent EL1 from being
5030 * able to make SMC calls into the ersatz firmware, so in
5031 * that case HCR.TSC should be read/write.
5033 valid_mask
&= ~HCR_TSC
;
5035 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5036 valid_mask
|= HCR_E2H
;
5038 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5039 valid_mask
|= HCR_TLOR
;
5041 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5042 valid_mask
|= HCR_API
| HCR_APK
;
5045 /* Clear RES0 bits. */
5046 value
&= valid_mask
;
5048 /* These bits change the MMU setup:
5049 * HCR_VM enables stage 2 translation
5050 * HCR_PTW forbids certain page-table setups
5051 * HCR_DC Disables stage1 and enables stage2 translation
5053 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
5054 tlb_flush(CPU(cpu
));
5056 env
->cp15
.hcr_el2
= value
;
5059 * Updates to VI and VF require us to update the status of
5060 * virtual interrupts, which are the logical OR of these bits
5061 * and the state of the input lines from the GIC. (This requires
5062 * that we have the iothread lock, which is done by marking the
5063 * reginfo structs as ARM_CP_IO.)
5064 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5065 * possible for it to be taken immediately, because VIRQ and
5066 * VFIQ are masked unless running at EL0 or EL1, and HCR
5067 * can only be written at EL2.
5069 g_assert(qemu_mutex_iothread_locked());
5070 arm_cpu_update_virq(cpu
);
5071 arm_cpu_update_vfiq(cpu
);
5074 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5077 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5078 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5079 hcr_write(env
, NULL
, value
);
5082 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5085 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5086 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5087 hcr_write(env
, NULL
, value
);
5091 * Return the effective value of HCR_EL2.
5092 * Bits that are not included here:
5093 * RW (read from SCR_EL3.RW as needed)
5095 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5097 uint64_t ret
= env
->cp15
.hcr_el2
;
5099 if (arm_is_secure_below_el3(env
)) {
5101 * "This register has no effect if EL2 is not enabled in the
5102 * current Security state". This is ARMv8.4-SecEL2 speak for
5103 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5105 * Prior to that, the language was "In an implementation that
5106 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5107 * as if this field is 0 for all purposes other than a direct
5108 * read or write access of HCR_EL2". With lots of enumeration
5109 * on a per-field basis. In current QEMU, this is condition
5110 * is arm_is_secure_below_el3.
5112 * Since the v8.4 language applies to the entire register, and
5113 * appears to be backward compatible, use that.
5116 } else if (ret
& HCR_TGE
) {
5117 /* These bits are up-to-date as of ARMv8.4. */
5118 if (ret
& HCR_E2H
) {
5119 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5120 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5121 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5122 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
);
5124 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5126 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5127 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5128 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5135 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5139 * For A-profile AArch32 EL3, if NSACR.CP10
5140 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5142 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5143 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5144 value
&= ~(0x3 << 10);
5145 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
5147 env
->cp15
.cptr_el
[2] = value
;
5150 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5153 * For A-profile AArch32 EL3, if NSACR.CP10
5154 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5156 uint64_t value
= env
->cp15
.cptr_el
[2];
5158 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5159 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5165 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5166 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5168 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5169 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5170 .writefn
= hcr_write
},
5171 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5172 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5173 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5174 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5175 .writefn
= hcr_writelow
},
5176 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5177 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5178 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5179 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5180 .type
= ARM_CP_ALIAS
,
5181 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5183 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5184 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5185 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5186 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5187 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5188 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5189 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5190 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5191 .type
= ARM_CP_ALIAS
,
5192 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5194 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5195 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5196 .type
= ARM_CP_ALIAS
,
5197 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5199 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5200 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5201 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5202 .access
= PL2_RW
, .writefn
= vbar_write
,
5203 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5205 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5206 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5207 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5208 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5209 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5210 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5211 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5212 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5213 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5214 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5215 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5216 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5218 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5219 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5220 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5221 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5222 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5223 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5224 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5226 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5227 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5228 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5229 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5231 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5232 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5233 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5235 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5236 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5237 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5239 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5240 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5241 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5242 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5243 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5244 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5245 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5246 .type
= ARM_CP_ALIAS
,
5247 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5248 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5249 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5250 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5252 /* no .writefn needed as this can't cause an ASID change;
5253 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5255 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5256 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5257 .cp
= 15, .opc1
= 6, .crm
= 2,
5258 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5259 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5260 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5261 .writefn
= vttbr_write
},
5262 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5263 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5264 .access
= PL2_RW
, .writefn
= vttbr_write
,
5265 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5266 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5267 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5268 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5269 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5270 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5271 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5272 .access
= PL2_RW
, .resetvalue
= 0,
5273 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5274 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5275 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5276 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5277 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5278 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5279 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5280 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5281 { .name
= "TLBIALLNSNH",
5282 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5283 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5284 .writefn
= tlbiall_nsnh_write
},
5285 { .name
= "TLBIALLNSNHIS",
5286 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5287 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5288 .writefn
= tlbiall_nsnh_is_write
},
5289 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5290 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5291 .writefn
= tlbiall_hyp_write
},
5292 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5293 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5294 .writefn
= tlbiall_hyp_is_write
},
5295 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5296 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5297 .writefn
= tlbimva_hyp_write
},
5298 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5299 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5300 .writefn
= tlbimva_hyp_is_write
},
5301 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5302 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5303 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5304 .writefn
= tlbi_aa64_alle2_write
},
5305 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5306 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5307 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5308 .writefn
= tlbi_aa64_vae2_write
},
5309 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5310 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5311 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5312 .writefn
= tlbi_aa64_vae2_write
},
5313 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5314 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5315 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5316 .writefn
= tlbi_aa64_alle2is_write
},
5317 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5318 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5319 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5320 .writefn
= tlbi_aa64_vae2is_write
},
5321 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5322 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5323 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5324 .writefn
= tlbi_aa64_vae2is_write
},
5325 #ifndef CONFIG_USER_ONLY
5326 /* Unlike the other EL2-related AT operations, these must
5327 * UNDEF from EL3 if EL2 is not implemented, which is why we
5328 * define them here rather than with the rest of the AT ops.
5330 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5331 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5332 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5333 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5334 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5335 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5336 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5337 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5338 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5339 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5340 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5341 * to behave as if SCR.NS was 1.
5343 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5345 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5346 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5348 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5349 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5350 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5351 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5352 * reset values as IMPDEF. We choose to reset to 3 to comply with
5353 * both ARMv7 and ARMv8.
5355 .access
= PL2_RW
, .resetvalue
= 3,
5356 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5357 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5358 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5359 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5360 .writefn
= gt_cntvoff_write
,
5361 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5362 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5363 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5364 .writefn
= gt_cntvoff_write
,
5365 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5366 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5367 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5368 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5369 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5370 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5371 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5372 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5373 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5374 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5375 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5376 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5377 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5378 .resetfn
= gt_hyp_timer_reset
,
5379 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5380 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5382 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5384 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5386 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5388 /* The only field of MDCR_EL2 that has a defined architectural reset value
5389 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5390 * don't implement any PMU event counters, so using zero as a reset
5391 * value for MDCR_EL2 is okay
5393 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5394 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5395 .access
= PL2_RW
, .resetvalue
= 0,
5396 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5397 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5398 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5399 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5400 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5401 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5402 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5404 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5405 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5406 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5408 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5412 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5413 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5414 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5415 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5417 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5418 .writefn
= hcr_writehigh
},
5422 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5425 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5426 * At Secure EL1 it traps to EL3.
5428 if (arm_current_el(env
) == 3) {
5429 return CP_ACCESS_OK
;
5431 if (arm_is_secure_below_el3(env
)) {
5432 return CP_ACCESS_TRAP_EL3
;
5434 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5436 return CP_ACCESS_OK
;
5438 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5441 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5442 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5443 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5444 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5445 .resetvalue
= 0, .writefn
= scr_write
},
5446 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5447 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5448 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5449 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5450 .writefn
= scr_write
},
5451 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5452 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5453 .access
= PL3_RW
, .resetvalue
= 0,
5454 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5456 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5457 .access
= PL3_RW
, .resetvalue
= 0,
5458 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5459 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5460 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5461 .writefn
= vbar_write
, .resetvalue
= 0,
5462 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5463 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5464 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5465 .access
= PL3_RW
, .resetvalue
= 0,
5466 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5467 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5468 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5470 /* no .writefn needed as this can't cause an ASID change;
5471 * we must provide a .raw_writefn and .resetfn because we handle
5472 * reset and migration for the AArch32 TTBCR(S), which might be
5473 * using mask and base_mask.
5475 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5476 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5477 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5478 .type
= ARM_CP_ALIAS
,
5479 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5481 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5482 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5483 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5484 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5485 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5486 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5487 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5488 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5489 .type
= ARM_CP_ALIAS
,
5490 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5492 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5493 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5494 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5495 .access
= PL3_RW
, .writefn
= vbar_write
,
5496 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5498 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5499 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5500 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5501 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5502 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5503 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5504 .access
= PL3_RW
, .resetvalue
= 0,
5505 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5506 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5507 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5508 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5510 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5511 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5512 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5514 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5515 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5516 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5518 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5519 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5520 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5521 .writefn
= tlbi_aa64_alle3is_write
},
5522 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5523 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5524 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5525 .writefn
= tlbi_aa64_vae3is_write
},
5526 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5527 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5528 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5529 .writefn
= tlbi_aa64_vae3is_write
},
5530 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5531 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5532 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5533 .writefn
= tlbi_aa64_alle3_write
},
5534 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5535 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5536 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5537 .writefn
= tlbi_aa64_vae3_write
},
5538 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5539 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5540 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5541 .writefn
= tlbi_aa64_vae3_write
},
5545 #ifndef CONFIG_USER_ONLY
5546 /* Test if system register redirection is to occur in the current state. */
5547 static bool redirect_for_e2h(CPUARMState
*env
)
5549 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5552 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5556 if (redirect_for_e2h(env
)) {
5557 /* Switch to the saved EL2 version of the register. */
5559 readfn
= ri
->readfn
;
5561 readfn
= ri
->orig_readfn
;
5563 if (readfn
== NULL
) {
5566 return readfn(env
, ri
);
5569 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5574 if (redirect_for_e2h(env
)) {
5575 /* Switch to the saved EL2 version of the register. */
5577 writefn
= ri
->writefn
;
5579 writefn
= ri
->orig_writefn
;
5581 if (writefn
== NULL
) {
5582 writefn
= raw_write
;
5584 writefn(env
, ri
, value
);
5587 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5590 uint32_t src_key
, dst_key
, new_key
;
5591 const char *src_name
, *dst_name
, *new_name
;
5592 bool (*feature
)(const ARMISARegisters
*id
);
5595 #define K(op0, op1, crn, crm, op2) \
5596 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5598 static const struct E2HAlias aliases
[] = {
5599 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5600 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5601 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5602 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5603 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5604 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5605 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5606 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5607 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5608 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5609 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5610 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5611 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5612 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5613 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5614 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5615 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5616 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5617 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5618 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5619 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5620 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5621 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5622 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5623 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5624 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5625 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5626 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5627 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5628 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5629 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5630 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5633 * Note that redirection of ZCR is mentioned in the description
5634 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5635 * not in the summary table.
5637 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5638 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5640 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5641 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5647 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5648 const struct E2HAlias
*a
= &aliases
[i
];
5649 ARMCPRegInfo
*src_reg
, *dst_reg
;
5651 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5655 src_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->src_key
);
5656 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->dst_key
);
5657 g_assert(src_reg
!= NULL
);
5658 g_assert(dst_reg
!= NULL
);
5660 /* Cross-compare names to detect typos in the keys. */
5661 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5662 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5664 /* None of the core system registers use opaque; we will. */
5665 g_assert(src_reg
->opaque
== NULL
);
5667 /* Create alias before redirection so we dup the right data. */
5669 ARMCPRegInfo
*new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5670 uint32_t *new_key
= g_memdup(&a
->new_key
, sizeof(uint32_t));
5673 new_reg
->name
= a
->new_name
;
5674 new_reg
->type
|= ARM_CP_ALIAS
;
5675 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5676 new_reg
->access
&= PL2_RW
| PL3_RW
;
5678 ok
= g_hash_table_insert(cpu
->cp_regs
, new_key
, new_reg
);
5682 src_reg
->opaque
= dst_reg
;
5683 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5684 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5685 if (!src_reg
->raw_readfn
) {
5686 src_reg
->raw_readfn
= raw_read
;
5688 if (!src_reg
->raw_writefn
) {
5689 src_reg
->raw_writefn
= raw_write
;
5691 src_reg
->readfn
= el2_e2h_read
;
5692 src_reg
->writefn
= el2_e2h_write
;
5697 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5700 int cur_el
= arm_current_el(env
);
5703 uint64_t hcr
= arm_hcr_el2_eff(env
);
5706 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5707 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5708 return CP_ACCESS_TRAP_EL2
;
5711 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5712 return CP_ACCESS_TRAP
;
5714 if (hcr
& HCR_TID2
) {
5715 return CP_ACCESS_TRAP_EL2
;
5718 } else if (hcr
& HCR_TID2
) {
5719 return CP_ACCESS_TRAP_EL2
;
5723 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5724 return CP_ACCESS_TRAP_EL2
;
5727 return CP_ACCESS_OK
;
5730 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5733 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5734 * read via a bit in OSLSR_EL1.
5738 if (ri
->state
== ARM_CP_STATE_AA32
) {
5739 oslock
= (value
== 0xC5ACCE55);
5744 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5747 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5748 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5749 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5750 * unlike DBGDRAR it is never accessible from EL0.
5751 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5754 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5755 .access
= PL0_R
, .accessfn
= access_tdra
,
5756 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5757 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5758 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5759 .access
= PL1_R
, .accessfn
= access_tdra
,
5760 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5761 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5762 .access
= PL0_R
, .accessfn
= access_tdra
,
5763 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5764 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5765 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5766 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5767 .access
= PL1_RW
, .accessfn
= access_tda
,
5768 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5770 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5771 * We don't implement the configurable EL0 access.
5773 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
5774 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5775 .type
= ARM_CP_ALIAS
,
5776 .access
= PL1_R
, .accessfn
= access_tda
,
5777 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5778 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5779 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5780 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5781 .accessfn
= access_tdosa
,
5782 .writefn
= oslar_write
},
5783 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5784 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5785 .access
= PL1_R
, .resetvalue
= 10,
5786 .accessfn
= access_tdosa
,
5787 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5788 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5789 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5790 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5791 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5792 .type
= ARM_CP_NOP
},
5793 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5794 * implement vector catch debug events yet.
5797 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5798 .access
= PL1_RW
, .accessfn
= access_tda
,
5799 .type
= ARM_CP_NOP
},
5800 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5801 * to save and restore a 32-bit guest's DBGVCR)
5803 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5804 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5805 .access
= PL2_RW
, .accessfn
= access_tda
,
5806 .type
= ARM_CP_NOP
},
5807 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5808 * Channel but Linux may try to access this register. The 32-bit
5809 * alias is DBGDCCINT.
5811 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5812 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5813 .access
= PL1_RW
, .accessfn
= access_tda
,
5814 .type
= ARM_CP_NOP
},
5818 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
5819 /* 64 bit access versions of the (dummy) debug registers */
5820 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
5821 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5822 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
5823 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5827 /* Return the exception level to which exceptions should be taken
5828 * via SVEAccessTrap. If an exception should be routed through
5829 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5830 * take care of raising that exception.
5831 * C.f. the ARM pseudocode function CheckSVEEnabled.
5833 int sve_exception_el(CPUARMState
*env
, int el
)
5835 #ifndef CONFIG_USER_ONLY
5836 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
5838 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
5839 bool disabled
= false;
5841 /* The CPACR.ZEN controls traps to EL1:
5842 * 0, 2 : trap EL0 and EL1 accesses
5843 * 1 : trap only EL0 accesses
5844 * 3 : trap no accesses
5846 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
5848 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
5853 return hcr_el2
& HCR_TGE
? 2 : 1;
5856 /* Check CPACR.FPEN. */
5857 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
5859 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
5867 /* CPTR_EL2. Since TZ and TFP are positive,
5868 * they will be zero when EL2 is not present.
5870 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
5871 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
5874 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
5879 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5880 if (arm_feature(env
, ARM_FEATURE_EL3
)
5881 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
5888 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
5892 end_len
= start_len
&= 0xf;
5893 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
5894 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
5895 assert(end_len
< start_len
);
5901 * Given that SVE is enabled, return the vector length for EL.
5903 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
5905 ARMCPU
*cpu
= env_archcpu(env
);
5906 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
5909 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
5911 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
5912 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
5914 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5915 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
5918 return sve_zcr_get_valid_len(cpu
, zcr_len
);
5921 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5924 int cur_el
= arm_current_el(env
);
5925 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
5928 /* Bits other than [3:0] are RAZ/WI. */
5929 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
5930 raw_write(env
, ri
, value
& 0xf);
5933 * Because we arrived here, we know both FP and SVE are enabled;
5934 * otherwise we would have trapped access to the ZCR_ELn register.
5936 new_len
= sve_zcr_len_for_el(env
, cur_el
);
5937 if (new_len
< old_len
) {
5938 aarch64_sve_narrow_vq(env
, new_len
+ 1);
5942 static const ARMCPRegInfo zcr_el1_reginfo
= {
5943 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
5944 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
5945 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
5946 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
5947 .writefn
= zcr_write
, .raw_writefn
= raw_write
5950 static const ARMCPRegInfo zcr_el2_reginfo
= {
5951 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5952 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5953 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5954 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
5955 .writefn
= zcr_write
, .raw_writefn
= raw_write
5958 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
5959 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5960 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5961 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5962 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
5965 static const ARMCPRegInfo zcr_el3_reginfo
= {
5966 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
5967 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
5968 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
5969 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
5970 .writefn
= zcr_write
, .raw_writefn
= raw_write
5973 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
5975 CPUARMState
*env
= &cpu
->env
;
5977 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
5978 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
5980 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
5982 if (env
->cpu_watchpoint
[n
]) {
5983 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
5984 env
->cpu_watchpoint
[n
] = NULL
;
5987 if (!extract64(wcr
, 0, 1)) {
5988 /* E bit clear : watchpoint disabled */
5992 switch (extract64(wcr
, 3, 2)) {
5994 /* LSC 00 is reserved and must behave as if the wp is disabled */
5997 flags
|= BP_MEM_READ
;
6000 flags
|= BP_MEM_WRITE
;
6003 flags
|= BP_MEM_ACCESS
;
6007 /* Attempts to use both MASK and BAS fields simultaneously are
6008 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6009 * thus generating a watchpoint for every byte in the masked region.
6011 mask
= extract64(wcr
, 24, 4);
6012 if (mask
== 1 || mask
== 2) {
6013 /* Reserved values of MASK; we must act as if the mask value was
6014 * some non-reserved value, or as if the watchpoint were disabled.
6015 * We choose the latter.
6019 /* Watchpoint covers an aligned area up to 2GB in size */
6021 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6022 * whether the watchpoint fires when the unmasked bits match; we opt
6023 * to generate the exceptions.
6027 /* Watchpoint covers bytes defined by the byte address select bits */
6028 int bas
= extract64(wcr
, 5, 8);
6032 /* This must act as if the watchpoint is disabled */
6036 if (extract64(wvr
, 2, 1)) {
6037 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6038 * ignored, and BAS[3:0] define which bytes to watch.
6042 /* The BAS bits are supposed to be programmed to indicate a contiguous
6043 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6044 * we fire for each byte in the word/doubleword addressed by the WVR.
6045 * We choose to ignore any non-zero bits after the first range of 1s.
6047 basstart
= ctz32(bas
);
6048 len
= cto32(bas
>> basstart
);
6052 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6053 &env
->cpu_watchpoint
[n
]);
6056 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6059 CPUARMState
*env
= &cpu
->env
;
6061 /* Completely clear out existing QEMU watchpoints and our array, to
6062 * avoid possible stale entries following migration load.
6064 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6065 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6067 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6068 hw_watchpoint_update(cpu
, i
);
6072 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6075 ARMCPU
*cpu
= env_archcpu(env
);
6078 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6079 * register reads and behaves as if values written are sign extended.
6080 * Bits [1:0] are RES0.
6082 value
= sextract64(value
, 0, 49) & ~3ULL;
6084 raw_write(env
, ri
, value
);
6085 hw_watchpoint_update(cpu
, i
);
6088 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6091 ARMCPU
*cpu
= env_archcpu(env
);
6094 raw_write(env
, ri
, value
);
6095 hw_watchpoint_update(cpu
, i
);
6098 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6100 CPUARMState
*env
= &cpu
->env
;
6101 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6102 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6107 if (env
->cpu_breakpoint
[n
]) {
6108 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6109 env
->cpu_breakpoint
[n
] = NULL
;
6112 if (!extract64(bcr
, 0, 1)) {
6113 /* E bit clear : watchpoint disabled */
6117 bt
= extract64(bcr
, 20, 4);
6120 case 4: /* unlinked address mismatch (reserved if AArch64) */
6121 case 5: /* linked address mismatch (reserved if AArch64) */
6122 qemu_log_mask(LOG_UNIMP
,
6123 "arm: address mismatch breakpoint types not implemented\n");
6125 case 0: /* unlinked address match */
6126 case 1: /* linked address match */
6128 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6129 * we behave as if the register was sign extended. Bits [1:0] are
6130 * RES0. The BAS field is used to allow setting breakpoints on 16
6131 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6132 * a bp will fire if the addresses covered by the bp and the addresses
6133 * covered by the insn overlap but the insn doesn't start at the
6134 * start of the bp address range. We choose to require the insn and
6135 * the bp to have the same address. The constraints on writing to
6136 * BAS enforced in dbgbcr_write mean we have only four cases:
6137 * 0b0000 => no breakpoint
6138 * 0b0011 => breakpoint on addr
6139 * 0b1100 => breakpoint on addr + 2
6140 * 0b1111 => breakpoint on addr
6141 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6143 int bas
= extract64(bcr
, 5, 4);
6144 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
6153 case 2: /* unlinked context ID match */
6154 case 8: /* unlinked VMID match (reserved if no EL2) */
6155 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6156 qemu_log_mask(LOG_UNIMP
,
6157 "arm: unlinked context breakpoint types not implemented\n");
6159 case 9: /* linked VMID match (reserved if no EL2) */
6160 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6161 case 3: /* linked context ID match */
6163 /* We must generate no events for Linked context matches (unless
6164 * they are linked to by some other bp/wp, which is handled in
6165 * updates for the linking bp/wp). We choose to also generate no events
6166 * for reserved values.
6171 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6174 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6177 CPUARMState
*env
= &cpu
->env
;
6179 /* Completely clear out existing QEMU breakpoints and our array, to
6180 * avoid possible stale entries following migration load.
6182 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6183 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6185 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6186 hw_breakpoint_update(cpu
, i
);
6190 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6193 ARMCPU
*cpu
= env_archcpu(env
);
6196 raw_write(env
, ri
, value
);
6197 hw_breakpoint_update(cpu
, i
);
6200 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6203 ARMCPU
*cpu
= env_archcpu(env
);
6206 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6209 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6210 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6212 raw_write(env
, ri
, value
);
6213 hw_breakpoint_update(cpu
, i
);
6216 static void define_debug_regs(ARMCPU
*cpu
)
6218 /* Define v7 and v8 architectural debug registers.
6219 * These are just dummy implementations for now.
6222 int wrps
, brps
, ctx_cmps
;
6223 ARMCPRegInfo dbgdidr
= {
6224 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
6225 .access
= PL0_R
, .accessfn
= access_tda
,
6226 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
6229 /* Note that all these register fields hold "number of Xs minus 1". */
6230 brps
= extract32(cpu
->dbgdidr
, 24, 4);
6231 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
6232 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
6234 assert(ctx_cmps
<= brps
);
6236 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
6237 * of the debug registers such as number of breakpoints;
6238 * check that if they both exist then they agree.
6240 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
6241 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
6242 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
6243 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
6246 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6247 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6249 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6250 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6253 for (i
= 0; i
< brps
+ 1; i
++) {
6254 ARMCPRegInfo dbgregs
[] = {
6255 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
6256 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6257 .access
= PL1_RW
, .accessfn
= access_tda
,
6258 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6259 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6261 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
6262 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6263 .access
= PL1_RW
, .accessfn
= access_tda
,
6264 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6265 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6269 define_arm_cp_regs(cpu
, dbgregs
);
6272 for (i
= 0; i
< wrps
+ 1; i
++) {
6273 ARMCPRegInfo dbgregs
[] = {
6274 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
6275 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6276 .access
= PL1_RW
, .accessfn
= access_tda
,
6277 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6278 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6280 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
6281 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6282 .access
= PL1_RW
, .accessfn
= access_tda
,
6283 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6284 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6288 define_arm_cp_regs(cpu
, dbgregs
);
6292 /* We don't know until after realize whether there's a GICv3
6293 * attached, and that is what registers the gicv3 sysregs.
6294 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6297 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6299 ARMCPU
*cpu
= env_archcpu(env
);
6300 uint64_t pfr1
= cpu
->id_pfr1
;
6302 if (env
->gicv3state
) {
6308 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6310 ARMCPU
*cpu
= env_archcpu(env
);
6311 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6313 if (env
->gicv3state
) {
6319 /* Shared logic between LORID and the rest of the LOR* registers.
6320 * Secure state has already been delt with.
6322 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
6324 int el
= arm_current_el(env
);
6326 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6327 return CP_ACCESS_TRAP_EL2
;
6329 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6330 return CP_ACCESS_TRAP_EL3
;
6332 return CP_ACCESS_OK
;
6335 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6338 if (arm_is_secure_below_el3(env
)) {
6339 /* Access ok in secure mode. */
6340 return CP_ACCESS_OK
;
6342 return access_lor_ns(env
);
6345 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6346 const ARMCPRegInfo
*ri
, bool isread
)
6348 if (arm_is_secure_below_el3(env
)) {
6349 /* Access denied in secure mode. */
6350 return CP_ACCESS_TRAP
;
6352 return access_lor_ns(env
);
6356 * A trivial implementation of ARMv8.1-LOR leaves all of these
6357 * registers fixed at 0, which indicates that there are zero
6358 * supported Limited Ordering regions.
6360 static const ARMCPRegInfo lor_reginfo
[] = {
6361 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6362 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6363 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6364 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6365 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6366 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6367 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6368 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6369 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6370 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6371 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6372 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6373 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6374 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6375 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6376 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6377 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6378 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6379 .access
= PL1_R
, .accessfn
= access_lorid
,
6380 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6384 #ifdef TARGET_AARCH64
6385 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6388 int el
= arm_current_el(env
);
6391 arm_feature(env
, ARM_FEATURE_EL2
) &&
6392 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6393 return CP_ACCESS_TRAP_EL2
;
6396 arm_feature(env
, ARM_FEATURE_EL3
) &&
6397 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6398 return CP_ACCESS_TRAP_EL3
;
6400 return CP_ACCESS_OK
;
6403 static const ARMCPRegInfo pauth_reginfo
[] = {
6404 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6405 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6406 .access
= PL1_RW
, .accessfn
= access_pauth
,
6407 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6408 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6409 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6410 .access
= PL1_RW
, .accessfn
= access_pauth
,
6411 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6412 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6413 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6414 .access
= PL1_RW
, .accessfn
= access_pauth
,
6415 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6416 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6417 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6418 .access
= PL1_RW
, .accessfn
= access_pauth
,
6419 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6420 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6421 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6422 .access
= PL1_RW
, .accessfn
= access_pauth
,
6423 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6424 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6425 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6426 .access
= PL1_RW
, .accessfn
= access_pauth
,
6427 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6428 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6429 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6430 .access
= PL1_RW
, .accessfn
= access_pauth
,
6431 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6432 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6433 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6434 .access
= PL1_RW
, .accessfn
= access_pauth
,
6435 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6436 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6437 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6438 .access
= PL1_RW
, .accessfn
= access_pauth
,
6439 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6440 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6441 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6442 .access
= PL1_RW
, .accessfn
= access_pauth
,
6443 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6447 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6452 /* Success sets NZCV = 0000. */
6453 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
6455 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
6457 * ??? Failed, for unknown reasons in the crypto subsystem.
6458 * The best we can do is log the reason and return the
6459 * timed-out indication to the guest. There is no reason
6460 * we know to expect this failure to be transitory, so the
6461 * guest may well hang retrying the operation.
6463 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
6464 ri
->name
, error_get_pretty(err
));
6467 env
->ZF
= 0; /* NZCF = 0100 */
6473 /* We do not support re-seeding, so the two registers operate the same. */
6474 static const ARMCPRegInfo rndr_reginfo
[] = {
6475 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
6476 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6477 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
6478 .access
= PL0_R
, .readfn
= rndr_readfn
},
6479 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
6480 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6481 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
6482 .access
= PL0_R
, .readfn
= rndr_readfn
},
6486 #ifndef CONFIG_USER_ONLY
6487 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
6490 ARMCPU
*cpu
= env_archcpu(env
);
6491 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6492 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
6493 uint64_t vaddr_in
= (uint64_t) value
;
6494 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
6496 int mem_idx
= cpu_mmu_index(env
, false);
6498 /* This won't be crossing page boundaries */
6499 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
6505 /* RCU lock is already being held */
6506 mr
= memory_region_from_host(haddr
, &offset
);
6509 memory_region_do_writeback(mr
, offset
, dline_size
);
6514 static const ARMCPRegInfo dcpop_reg
[] = {
6515 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
6516 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
6517 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6518 .accessfn
= aa64_cacheop_access
, .writefn
= dccvap_writefn
},
6522 static const ARMCPRegInfo dcpodp_reg
[] = {
6523 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
6524 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
6525 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6526 .accessfn
= aa64_cacheop_access
, .writefn
= dccvap_writefn
},
6529 #endif /*CONFIG_USER_ONLY*/
6533 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6536 int el
= arm_current_el(env
);
6539 uint64_t sctlr
= arm_sctlr(env
, el
);
6540 if (!(sctlr
& SCTLR_EnRCTX
)) {
6541 return CP_ACCESS_TRAP
;
6543 } else if (el
== 1) {
6544 uint64_t hcr
= arm_hcr_el2_eff(env
);
6546 return CP_ACCESS_TRAP_EL2
;
6549 return CP_ACCESS_OK
;
6552 static const ARMCPRegInfo predinv_reginfo
[] = {
6553 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
6554 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
6555 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6556 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
6557 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
6558 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6559 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
6560 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
6561 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6563 * Note the AArch32 opcodes have a different OPC1.
6565 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
6566 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
6567 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6568 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
6569 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
6570 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6571 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
6572 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
6573 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6577 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6580 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
6581 return CP_ACCESS_TRAP_EL2
;
6584 return CP_ACCESS_OK
;
6587 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6590 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6591 return access_aa64_tid3(env
, ri
, isread
);
6594 return CP_ACCESS_OK
;
6597 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6600 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
6601 return CP_ACCESS_TRAP_EL2
;
6604 return CP_ACCESS_OK
;
6607 static const ARMCPRegInfo jazelle_regs
[] = {
6609 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
6610 .access
= PL1_R
, .accessfn
= access_jazelle
,
6611 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6613 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
6614 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6616 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
6617 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6621 static const ARMCPRegInfo vhe_reginfo
[] = {
6622 { .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6623 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
6625 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2]) },
6626 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
6627 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
6628 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
6629 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
6630 #ifndef CONFIG_USER_ONLY
6631 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6632 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
6634 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
6635 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6636 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
6637 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6638 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
6639 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6640 .resetfn
= gt_hv_timer_reset
,
6641 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
6642 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6644 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
6646 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
6647 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
6648 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
6649 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
6650 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6651 .access
= PL2_RW
, .accessfn
= e2h_access
,
6652 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
6653 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
6654 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
6655 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
6656 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6657 .access
= PL2_RW
, .accessfn
= e2h_access
,
6658 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
6659 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
6660 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6661 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
6662 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
6663 .access
= PL2_RW
, .accessfn
= e2h_access
,
6664 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
6665 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6666 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
6667 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
6668 .access
= PL2_RW
, .accessfn
= e2h_access
,
6669 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
6670 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6671 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
6672 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6673 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
6674 .access
= PL2_RW
, .accessfn
= e2h_access
,
6675 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
6676 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
6677 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
6678 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6679 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
6680 .access
= PL2_RW
, .accessfn
= e2h_access
,
6681 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
6686 void register_cp_regs_for_features(ARMCPU
*cpu
)
6688 /* Register all the coprocessor registers based on feature bits */
6689 CPUARMState
*env
= &cpu
->env
;
6690 if (arm_feature(env
, ARM_FEATURE_M
)) {
6691 /* M profile has no coprocessor registers */
6695 define_arm_cp_regs(cpu
, cp_reginfo
);
6696 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
6697 /* Must go early as it is full of wildcards that may be
6698 * overridden by later definitions.
6700 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
6703 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6704 /* The ID registers all have impdef reset values */
6705 ARMCPRegInfo v6_idregs
[] = {
6706 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
6707 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6708 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6709 .accessfn
= access_aa32_tid3
,
6710 .resetvalue
= cpu
->id_pfr0
},
6711 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
6712 * the value of the GIC field until after we define these regs.
6714 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
6715 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
6716 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6717 .accessfn
= access_aa32_tid3
,
6718 .readfn
= id_pfr1_read
,
6719 .writefn
= arm_cp_write_ignore
},
6720 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
6721 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
6722 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6723 .accessfn
= access_aa32_tid3
,
6724 .resetvalue
= cpu
->id_dfr0
},
6725 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
6726 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
6727 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6728 .accessfn
= access_aa32_tid3
,
6729 .resetvalue
= cpu
->id_afr0
},
6730 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
6731 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
6732 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6733 .accessfn
= access_aa32_tid3
,
6734 .resetvalue
= cpu
->id_mmfr0
},
6735 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
6736 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
6737 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6738 .accessfn
= access_aa32_tid3
,
6739 .resetvalue
= cpu
->id_mmfr1
},
6740 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
6741 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
6742 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6743 .accessfn
= access_aa32_tid3
,
6744 .resetvalue
= cpu
->id_mmfr2
},
6745 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
6746 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
6747 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6748 .accessfn
= access_aa32_tid3
,
6749 .resetvalue
= cpu
->id_mmfr3
},
6750 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
6751 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6752 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6753 .accessfn
= access_aa32_tid3
,
6754 .resetvalue
= cpu
->isar
.id_isar0
},
6755 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
6756 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
6757 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6758 .accessfn
= access_aa32_tid3
,
6759 .resetvalue
= cpu
->isar
.id_isar1
},
6760 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
6761 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6762 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6763 .accessfn
= access_aa32_tid3
,
6764 .resetvalue
= cpu
->isar
.id_isar2
},
6765 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
6766 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
6767 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6768 .accessfn
= access_aa32_tid3
,
6769 .resetvalue
= cpu
->isar
.id_isar3
},
6770 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
6771 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
6772 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6773 .accessfn
= access_aa32_tid3
,
6774 .resetvalue
= cpu
->isar
.id_isar4
},
6775 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
6776 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
6777 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6778 .accessfn
= access_aa32_tid3
,
6779 .resetvalue
= cpu
->isar
.id_isar5
},
6780 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
6781 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
6782 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6783 .accessfn
= access_aa32_tid3
,
6784 .resetvalue
= cpu
->id_mmfr4
},
6785 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
6786 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
6787 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6788 .accessfn
= access_aa32_tid3
,
6789 .resetvalue
= cpu
->isar
.id_isar6
},
6792 define_arm_cp_regs(cpu
, v6_idregs
);
6793 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
6795 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
6797 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
6798 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
6800 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
6801 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
6802 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
6804 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
6805 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
6807 if (arm_feature(env
, ARM_FEATURE_V7
)) {
6808 /* v7 performance monitor control register: same implementor
6809 * field as main ID register, and we implement four counters in
6810 * addition to the cycle count register.
6812 unsigned int i
, pmcrn
= 4;
6813 ARMCPRegInfo pmcr
= {
6814 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6816 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6817 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6818 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6819 .raw_writefn
= raw_write
,
6821 ARMCPRegInfo pmcr64
= {
6822 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6823 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6824 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6826 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6827 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
),
6828 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6830 define_one_arm_cp_reg(cpu
, &pmcr
);
6831 define_one_arm_cp_reg(cpu
, &pmcr64
);
6832 for (i
= 0; i
< pmcrn
; i
++) {
6833 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6834 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6835 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6836 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6837 ARMCPRegInfo pmev_regs
[] = {
6838 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6839 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6840 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6841 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6842 .accessfn
= pmreg_access
},
6843 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6844 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6845 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6847 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6848 .raw_readfn
= pmevcntr_rawread
,
6849 .raw_writefn
= pmevcntr_rawwrite
},
6850 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6851 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6852 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6853 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6854 .accessfn
= pmreg_access
},
6855 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6856 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6857 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6859 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6860 .raw_writefn
= pmevtyper_rawwrite
},
6863 define_arm_cp_regs(cpu
, pmev_regs
);
6864 g_free(pmevcntr_name
);
6865 g_free(pmevcntr_el0_name
);
6866 g_free(pmevtyper_name
);
6867 g_free(pmevtyper_el0_name
);
6869 ARMCPRegInfo clidr
= {
6870 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
6871 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
6872 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6873 .accessfn
= access_aa64_tid2
,
6874 .resetvalue
= cpu
->clidr
6876 define_one_arm_cp_reg(cpu
, &clidr
);
6877 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
6878 define_debug_regs(cpu
);
6880 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
6882 if (FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) >= 4 &&
6883 FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf) {
6884 ARMCPRegInfo v81_pmu_regs
[] = {
6885 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6886 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6887 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6888 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6889 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6890 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6891 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6892 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6895 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6897 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6898 /* AArch64 ID registers, which all have impdef reset values.
6899 * Note that within the ID register ranges the unused slots
6900 * must all RAZ, not UNDEF; future architecture versions may
6901 * define new registers here.
6903 ARMCPRegInfo v8_idregs
[] = {
6904 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
6905 * know the right value for the GIC field until after we
6906 * define these regs.
6908 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6909 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
6910 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6911 .accessfn
= access_aa64_tid3
,
6912 .readfn
= id_aa64pfr0_read
,
6913 .writefn
= arm_cp_write_ignore
},
6914 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6915 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
6916 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6917 .accessfn
= access_aa64_tid3
,
6918 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
6919 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6920 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
6921 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6922 .accessfn
= access_aa64_tid3
,
6924 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6925 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
6926 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6927 .accessfn
= access_aa64_tid3
,
6929 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6930 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
6931 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6932 .accessfn
= access_aa64_tid3
,
6933 /* At present, only SVEver == 0 is defined anyway. */
6935 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6936 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
6937 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6938 .accessfn
= access_aa64_tid3
,
6940 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6941 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
6942 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6943 .accessfn
= access_aa64_tid3
,
6945 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6946 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
6947 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6948 .accessfn
= access_aa64_tid3
,
6950 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6951 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
6952 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6953 .accessfn
= access_aa64_tid3
,
6954 .resetvalue
= cpu
->id_aa64dfr0
},
6955 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6956 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
6957 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6958 .accessfn
= access_aa64_tid3
,
6959 .resetvalue
= cpu
->id_aa64dfr1
},
6960 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6961 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
6962 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6963 .accessfn
= access_aa64_tid3
,
6965 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6966 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
6967 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6968 .accessfn
= access_aa64_tid3
,
6970 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6971 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
6972 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6973 .accessfn
= access_aa64_tid3
,
6974 .resetvalue
= cpu
->id_aa64afr0
},
6975 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6976 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
6977 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6978 .accessfn
= access_aa64_tid3
,
6979 .resetvalue
= cpu
->id_aa64afr1
},
6980 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6981 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
6982 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6983 .accessfn
= access_aa64_tid3
,
6985 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6986 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
6987 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6988 .accessfn
= access_aa64_tid3
,
6990 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
6991 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
6992 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6993 .accessfn
= access_aa64_tid3
,
6994 .resetvalue
= cpu
->isar
.id_aa64isar0
},
6995 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
6996 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
6997 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6998 .accessfn
= access_aa64_tid3
,
6999 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7000 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7001 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7002 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7003 .accessfn
= access_aa64_tid3
,
7005 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7006 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7007 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7008 .accessfn
= access_aa64_tid3
,
7010 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7011 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7012 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7013 .accessfn
= access_aa64_tid3
,
7015 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7016 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7017 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7018 .accessfn
= access_aa64_tid3
,
7020 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7021 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7022 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7023 .accessfn
= access_aa64_tid3
,
7025 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7026 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7027 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7028 .accessfn
= access_aa64_tid3
,
7030 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7031 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7032 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7033 .accessfn
= access_aa64_tid3
,
7034 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7035 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7036 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7037 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7038 .accessfn
= access_aa64_tid3
,
7039 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7040 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7041 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7042 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7043 .accessfn
= access_aa64_tid3
,
7045 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7046 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7047 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7048 .accessfn
= access_aa64_tid3
,
7050 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7051 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7052 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7053 .accessfn
= access_aa64_tid3
,
7055 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7056 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7057 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7058 .accessfn
= access_aa64_tid3
,
7060 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7061 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7062 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7063 .accessfn
= access_aa64_tid3
,
7065 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7066 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7067 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7068 .accessfn
= access_aa64_tid3
,
7070 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7071 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7072 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7073 .accessfn
= access_aa64_tid3
,
7074 .resetvalue
= cpu
->isar
.mvfr0
},
7075 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7076 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7077 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7078 .accessfn
= access_aa64_tid3
,
7079 .resetvalue
= cpu
->isar
.mvfr1
},
7080 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7081 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7082 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7083 .accessfn
= access_aa64_tid3
,
7084 .resetvalue
= cpu
->isar
.mvfr2
},
7085 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7086 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7087 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7088 .accessfn
= access_aa64_tid3
,
7090 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7091 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7092 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7093 .accessfn
= access_aa64_tid3
,
7095 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7096 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7097 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7098 .accessfn
= access_aa64_tid3
,
7100 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7101 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7102 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7103 .accessfn
= access_aa64_tid3
,
7105 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7106 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7107 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7108 .accessfn
= access_aa64_tid3
,
7110 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7111 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7112 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7113 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7114 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7115 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7116 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7117 .resetvalue
= cpu
->pmceid0
},
7118 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7119 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7120 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7121 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7122 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7123 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7124 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7125 .resetvalue
= cpu
->pmceid1
},
7128 #ifdef CONFIG_USER_ONLY
7129 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7130 { .name
= "ID_AA64PFR0_EL1",
7131 .exported_bits
= 0x000f000f00ff0000,
7132 .fixed_bits
= 0x0000000000000011 },
7133 { .name
= "ID_AA64PFR1_EL1",
7134 .exported_bits
= 0x00000000000000f0 },
7135 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7137 { .name
= "ID_AA64ZFR0_EL1" },
7138 { .name
= "ID_AA64MMFR0_EL1",
7139 .fixed_bits
= 0x00000000ff000000 },
7140 { .name
= "ID_AA64MMFR1_EL1" },
7141 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7143 { .name
= "ID_AA64DFR0_EL1",
7144 .fixed_bits
= 0x0000000000000006 },
7145 { .name
= "ID_AA64DFR1_EL1" },
7146 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7148 { .name
= "ID_AA64AFR*",
7150 { .name
= "ID_AA64ISAR0_EL1",
7151 .exported_bits
= 0x00fffffff0fffff0 },
7152 { .name
= "ID_AA64ISAR1_EL1",
7153 .exported_bits
= 0x000000f0ffffffff },
7154 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7156 REGUSERINFO_SENTINEL
7158 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7160 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7161 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7162 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7163 ARMCPRegInfo rvbar
= {
7164 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7165 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7166 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
7168 define_one_arm_cp_reg(cpu
, &rvbar
);
7170 define_arm_cp_regs(cpu
, v8_idregs
);
7171 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7173 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7174 uint64_t vmpidr_def
= mpidr_read_val(env
);
7175 ARMCPRegInfo vpidr_regs
[] = {
7176 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7177 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7178 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7179 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
7180 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7181 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7182 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7183 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7184 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7185 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7186 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7187 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7188 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
7189 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7190 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7191 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7193 .resetvalue
= vmpidr_def
,
7194 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7197 define_arm_cp_regs(cpu
, vpidr_regs
);
7198 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7199 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7200 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7202 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7203 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7204 ARMCPRegInfo rvbar
= {
7205 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7206 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7207 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
7209 define_one_arm_cp_reg(cpu
, &rvbar
);
7212 /* If EL2 is missing but higher ELs are enabled, we need to
7213 * register the no_el2 reginfos.
7215 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7216 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7217 * of MIDR_EL1 and MPIDR_EL1.
7219 ARMCPRegInfo vpidr_regs
[] = {
7220 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7221 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7222 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
7223 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
7224 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7225 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7226 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7227 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
7228 .type
= ARM_CP_NO_RAW
,
7229 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
7232 define_arm_cp_regs(cpu
, vpidr_regs
);
7233 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
7234 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7235 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
7239 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7240 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7241 ARMCPRegInfo el3_regs
[] = {
7242 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7243 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7244 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
7245 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7246 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7248 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7249 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7250 .resetvalue
= cpu
->reset_sctlr
},
7254 define_arm_cp_regs(cpu
, el3_regs
);
7256 /* The behaviour of NSACR is sufficiently various that we don't
7257 * try to describe it in a single reginfo:
7258 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7259 * reads as constant 0xc00 from NS EL1 and NS EL2
7260 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7261 * if v7 without EL3, register doesn't exist
7262 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7264 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7265 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7266 ARMCPRegInfo nsacr
= {
7267 .name
= "NSACR", .type
= ARM_CP_CONST
,
7268 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7269 .access
= PL1_RW
, .accessfn
= nsacr_access
,
7272 define_one_arm_cp_reg(cpu
, &nsacr
);
7274 ARMCPRegInfo nsacr
= {
7276 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7277 .access
= PL3_RW
| PL1_R
,
7279 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
7281 define_one_arm_cp_reg(cpu
, &nsacr
);
7284 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7285 ARMCPRegInfo nsacr
= {
7286 .name
= "NSACR", .type
= ARM_CP_CONST
,
7287 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7291 define_one_arm_cp_reg(cpu
, &nsacr
);
7295 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
7296 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7297 /* PMSAv6 not implemented */
7298 assert(arm_feature(env
, ARM_FEATURE_V7
));
7299 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7300 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
7302 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
7305 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7306 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
7307 /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
7308 if (FIELD_EX32(cpu
->id_mmfr4
, ID_MMFR4
, HPDS
) != 0) {
7309 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
7312 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
7313 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
7315 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
7316 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
7318 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
7319 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
7321 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
7322 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
7324 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
7325 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
7327 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
7328 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
7330 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
7331 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
7333 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7334 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
7336 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7337 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
7339 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
7340 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
7342 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
7343 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
7345 if (cpu_isar_feature(jazelle
, cpu
)) {
7346 define_arm_cp_regs(cpu
, jazelle_regs
);
7348 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7349 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7350 * be read-only (ie write causes UNDEF exception).
7353 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
7354 /* Pre-v8 MIDR space.
7355 * Note that the MIDR isn't a simple constant register because
7356 * of the TI925 behaviour where writes to another register can
7357 * cause the MIDR value to change.
7359 * Unimplemented registers in the c15 0 0 0 space default to
7360 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7361 * and friends override accordingly.
7364 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
7365 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
7366 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
7367 .readfn
= midr_read
,
7368 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7369 .type
= ARM_CP_OVERRIDE
},
7370 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7372 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
7373 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7375 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
7376 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7378 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
7379 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7381 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
7382 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7384 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
7385 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7388 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
7389 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7390 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
7391 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
7392 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7393 .readfn
= midr_read
},
7394 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7395 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7396 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7397 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7398 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7399 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
7400 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7401 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7402 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
7404 .accessfn
= access_aa64_tid1
,
7405 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
7408 ARMCPRegInfo id_cp_reginfo
[] = {
7409 /* These are common to v8 and pre-v8 */
7411 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
7412 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
7413 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7414 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
7415 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
7416 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
7417 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7418 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7420 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
7422 .accessfn
= access_aa32_tid1
,
7423 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7426 /* TLBTR is specific to VMSA */
7427 ARMCPRegInfo id_tlbtr_reginfo
= {
7429 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
7431 .accessfn
= access_aa32_tid1
,
7432 .type
= ARM_CP_CONST
, .resetvalue
= 0,
7434 /* MPUIR is specific to PMSA V6+ */
7435 ARMCPRegInfo id_mpuir_reginfo
= {
7437 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7438 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7439 .resetvalue
= cpu
->pmsav7_dregion
<< 8
7441 ARMCPRegInfo crn0_wi_reginfo
= {
7442 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
7443 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
7444 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
7446 #ifdef CONFIG_USER_ONLY
7447 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
7448 { .name
= "MIDR_EL1",
7449 .exported_bits
= 0x00000000ffffffff },
7450 { .name
= "REVIDR_EL1" },
7451 REGUSERINFO_SENTINEL
7453 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
7455 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
7456 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7458 /* Register the blanket "writes ignored" value first to cover the
7459 * whole space. Then update the specific ID registers to allow write
7460 * access, so that they ignore writes rather than causing them to
7463 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
7464 for (r
= id_pre_v8_midr_cp_reginfo
;
7465 r
->type
!= ARM_CP_SENTINEL
; r
++) {
7468 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7471 id_mpuir_reginfo
.access
= PL1_RW
;
7472 id_tlbtr_reginfo
.access
= PL1_RW
;
7474 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7475 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
7477 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
7479 define_arm_cp_regs(cpu
, id_cp_reginfo
);
7480 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
7481 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
7482 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
7483 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
7487 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
7488 ARMCPRegInfo mpidr_cp_reginfo
[] = {
7489 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7490 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
7491 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
7494 #ifdef CONFIG_USER_ONLY
7495 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
7496 { .name
= "MPIDR_EL1",
7497 .fixed_bits
= 0x0000000080000000 },
7498 REGUSERINFO_SENTINEL
7500 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
7502 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
7505 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
7506 ARMCPRegInfo auxcr_reginfo
[] = {
7507 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
7508 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
7509 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
7510 .resetvalue
= cpu
->reset_auxcr
},
7511 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
7512 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
7513 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7515 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7516 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
7517 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
7521 define_arm_cp_regs(cpu
, auxcr_reginfo
);
7522 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7523 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
7524 ARMCPRegInfo hactlr2_reginfo
= {
7525 .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7526 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7527 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7530 define_one_arm_cp_reg(cpu
, &hactlr2_reginfo
);
7534 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
7536 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
7537 * There are two flavours:
7538 * (1) older 32-bit only cores have a simple 32-bit CBAR
7539 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
7540 * 32-bit register visible to AArch32 at a different encoding
7541 * to the "flavour 1" register and with the bits rearranged to
7542 * be able to squash a 64-bit address into the 32-bit view.
7543 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
7544 * in future if we support AArch32-only configs of some of the
7545 * AArch64 cores we might need to add a specific feature flag
7546 * to indicate cores with "flavour 2" CBAR.
7548 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7549 /* 32 bit view is [31:18] 0...0 [43:32]. */
7550 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
7551 | extract64(cpu
->reset_cbar
, 32, 12);
7552 ARMCPRegInfo cbar_reginfo
[] = {
7554 .type
= ARM_CP_CONST
,
7555 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
7556 .access
= PL1_R
, .resetvalue
= cbar32
},
7557 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7558 .type
= ARM_CP_CONST
,
7559 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
7560 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
7563 /* We don't implement a r/w 64 bit CBAR currently */
7564 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
7565 define_arm_cp_regs(cpu
, cbar_reginfo
);
7567 ARMCPRegInfo cbar
= {
7569 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
7570 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
7571 .fieldoffset
= offsetof(CPUARMState
,
7572 cp15
.c15_config_base_address
)
7574 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
7575 cbar
.access
= PL1_R
;
7576 cbar
.fieldoffset
= 0;
7577 cbar
.type
= ARM_CP_CONST
;
7579 define_one_arm_cp_reg(cpu
, &cbar
);
7583 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
7584 ARMCPRegInfo vbar_cp_reginfo
[] = {
7585 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
7586 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
7587 .access
= PL1_RW
, .writefn
= vbar_write
,
7588 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
7589 offsetof(CPUARMState
, cp15
.vbar_ns
) },
7593 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
7596 /* Generic registers whose values depend on the implementation */
7598 ARMCPRegInfo sctlr
= {
7599 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
7600 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
7602 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
7603 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
7604 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
7605 .raw_writefn
= raw_write
,
7607 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7608 /* Normally we would always end the TB on an SCTLR write, but Linux
7609 * arch/arm/mach-pxa/sleep.S expects two instructions following
7610 * an MMU enable to execute from cache. Imitate this behaviour.
7612 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
7614 define_one_arm_cp_reg(cpu
, &sctlr
);
7617 if (cpu_isar_feature(aa64_lor
, cpu
)) {
7618 define_arm_cp_regs(cpu
, lor_reginfo
);
7620 if (cpu_isar_feature(aa64_pan
, cpu
)) {
7621 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
7624 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
7625 define_arm_cp_regs(cpu
, vhe_reginfo
);
7628 if (cpu_isar_feature(aa64_sve
, cpu
)) {
7629 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
7630 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7631 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
7633 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
7635 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7636 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
7640 #ifdef TARGET_AARCH64
7641 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
7642 define_arm_cp_regs(cpu
, pauth_reginfo
);
7644 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
7645 define_arm_cp_regs(cpu
, rndr_reginfo
);
7647 #ifndef CONFIG_USER_ONLY
7648 /* Data Cache clean instructions up to PoP */
7649 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
7650 define_one_arm_cp_reg(cpu
, dcpop_reg
);
7652 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
7653 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
7656 #endif /*CONFIG_USER_ONLY*/
7660 * While all v8.0 cpus support aarch64, QEMU does have configurations
7661 * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
7662 * which will set ID_ISAR6.
7664 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
7665 ? cpu_isar_feature(aa64_predinv
, cpu
)
7666 : cpu_isar_feature(aa32_predinv
, cpu
)) {
7667 define_arm_cp_regs(cpu
, predinv_reginfo
);
7670 #ifndef CONFIG_USER_ONLY
7672 * Register redirections and aliases must be done last,
7673 * after the registers from the other extensions have been defined.
7675 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
7676 define_arm_vh_e2h_redirects_aliases(cpu
);
7681 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
7683 CPUState
*cs
= CPU(cpu
);
7684 CPUARMState
*env
= &cpu
->env
;
7686 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7687 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
7688 aarch64_fpu_gdb_set_reg
,
7689 34, "aarch64-fpu.xml", 0);
7690 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
7691 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7692 51, "arm-neon.xml", 0);
7693 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
7694 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7695 35, "arm-vfp3.xml", 0);
7696 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
7697 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7698 19, "arm-vfp.xml", 0);
7700 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
7701 arm_gen_dynamic_xml(cs
),
7702 "system-registers.xml", 0);
7705 /* Sort alphabetically by type name, except for "any". */
7706 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
7708 ObjectClass
*class_a
= (ObjectClass
*)a
;
7709 ObjectClass
*class_b
= (ObjectClass
*)b
;
7710 const char *name_a
, *name_b
;
7712 name_a
= object_class_get_name(class_a
);
7713 name_b
= object_class_get_name(class_b
);
7714 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
7716 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
7719 return strcmp(name_a
, name_b
);
7723 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
7725 ObjectClass
*oc
= data
;
7726 const char *typename
;
7729 typename
= object_class_get_name(oc
);
7730 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
7731 qemu_printf(" %s\n", name
);
7735 void arm_cpu_list(void)
7739 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7740 list
= g_slist_sort(list
, arm_cpu_list_compare
);
7741 qemu_printf("Available CPUs:\n");
7742 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
7746 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
7748 ObjectClass
*oc
= data
;
7749 CpuDefinitionInfoList
**cpu_list
= user_data
;
7750 CpuDefinitionInfoList
*entry
;
7751 CpuDefinitionInfo
*info
;
7752 const char *typename
;
7754 typename
= object_class_get_name(oc
);
7755 info
= g_malloc0(sizeof(*info
));
7756 info
->name
= g_strndup(typename
,
7757 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
7758 info
->q_typename
= g_strdup(typename
);
7760 entry
= g_malloc0(sizeof(*entry
));
7761 entry
->value
= info
;
7762 entry
->next
= *cpu_list
;
7766 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
7768 CpuDefinitionInfoList
*cpu_list
= NULL
;
7771 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7772 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
7778 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
7779 void *opaque
, int state
, int secstate
,
7780 int crm
, int opc1
, int opc2
,
7783 /* Private utility function for define_one_arm_cp_reg_with_opaque():
7784 * add a single reginfo struct to the hash table.
7786 uint32_t *key
= g_new(uint32_t, 1);
7787 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
7788 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
7789 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
7791 r2
->name
= g_strdup(name
);
7792 /* Reset the secure state to the specific incoming state. This is
7793 * necessary as the register may have been defined with both states.
7795 r2
->secure
= secstate
;
7797 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7798 /* Register is banked (using both entries in array).
7799 * Overwriting fieldoffset as the array is only used to define
7800 * banked registers but later only fieldoffset is used.
7802 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
7805 if (state
== ARM_CP_STATE_AA32
) {
7806 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7807 /* If the register is banked then we don't need to migrate or
7808 * reset the 32-bit instance in certain cases:
7810 * 1) If the register has both 32-bit and 64-bit instances then we
7811 * can count on the 64-bit instance taking care of the
7813 * 2) If ARMv8 is enabled then we can count on a 64-bit version
7814 * taking care of the secure bank. This requires that separate
7815 * 32 and 64-bit definitions are provided.
7817 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
7818 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
7819 r2
->type
|= ARM_CP_ALIAS
;
7821 } else if ((secstate
!= r
->secure
) && !ns
) {
7822 /* The register is not banked so we only want to allow migration of
7823 * the non-secure instance.
7825 r2
->type
|= ARM_CP_ALIAS
;
7828 if (r
->state
== ARM_CP_STATE_BOTH
) {
7829 /* We assume it is a cp15 register if the .cp field is left unset.
7835 #ifdef HOST_WORDS_BIGENDIAN
7836 if (r2
->fieldoffset
) {
7837 r2
->fieldoffset
+= sizeof(uint32_t);
7842 if (state
== ARM_CP_STATE_AA64
) {
7843 /* To allow abbreviation of ARMCPRegInfo
7844 * definitions, we treat cp == 0 as equivalent to
7845 * the value for "standard guest-visible sysreg".
7846 * STATE_BOTH definitions are also always "standard
7847 * sysreg" in their AArch64 view (the .cp value may
7848 * be non-zero for the benefit of the AArch32 view).
7850 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
7851 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
7853 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
7854 r2
->opc0
, opc1
, opc2
);
7856 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
7859 r2
->opaque
= opaque
;
7861 /* reginfo passed to helpers is correct for the actual access,
7862 * and is never ARM_CP_STATE_BOTH:
7865 /* Make sure reginfo passed to helpers for wildcarded regs
7866 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
7871 /* By convention, for wildcarded registers only the first
7872 * entry is used for migration; the others are marked as
7873 * ALIAS so we don't try to transfer the register
7874 * multiple times. Special registers (ie NOP/WFI) are
7875 * never migratable and not even raw-accessible.
7877 if ((r
->type
& ARM_CP_SPECIAL
)) {
7878 r2
->type
|= ARM_CP_NO_RAW
;
7880 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
7881 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
7882 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
7883 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
7886 /* Check that raw accesses are either forbidden or handled. Note that
7887 * we can't assert this earlier because the setup of fieldoffset for
7888 * banked registers has to be done first.
7890 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
7891 assert(!raw_accessors_invalid(r2
));
7894 /* Overriding of an existing definition must be explicitly
7897 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
7898 ARMCPRegInfo
*oldreg
;
7899 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
7900 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
7901 fprintf(stderr
, "Register redefined: cp=%d %d bit "
7902 "crn=%d crm=%d opc1=%d opc2=%d, "
7903 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
7904 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
7905 oldreg
->name
, r2
->name
);
7906 g_assert_not_reached();
7909 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
7913 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
7914 const ARMCPRegInfo
*r
, void *opaque
)
7916 /* Define implementations of coprocessor registers.
7917 * We store these in a hashtable because typically
7918 * there are less than 150 registers in a space which
7919 * is 16*16*16*8*8 = 262144 in size.
7920 * Wildcarding is supported for the crm, opc1 and opc2 fields.
7921 * If a register is defined twice then the second definition is
7922 * used, so this can be used to define some generic registers and
7923 * then override them with implementation specific variations.
7924 * At least one of the original and the second definition should
7925 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
7926 * against accidental use.
7928 * The state field defines whether the register is to be
7929 * visible in the AArch32 or AArch64 execution state. If the
7930 * state is set to ARM_CP_STATE_BOTH then we synthesise a
7931 * reginfo structure for the AArch32 view, which sees the lower
7932 * 32 bits of the 64 bit register.
7934 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
7935 * be wildcarded. AArch64 registers are always considered to be 64
7936 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
7937 * the register, if any.
7939 int crm
, opc1
, opc2
, state
;
7940 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
7941 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
7942 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
7943 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
7944 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
7945 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
7946 /* 64 bit registers have only CRm and Opc1 fields */
7947 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
7948 /* op0 only exists in the AArch64 encodings */
7949 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
7950 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
7951 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
7952 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
7953 * encodes a minimum access level for the register. We roll this
7954 * runtime check into our general permission check code, so check
7955 * here that the reginfo's specified permissions are strict enough
7956 * to encompass the generic architectural permission check.
7958 if (r
->state
!= ARM_CP_STATE_AA32
) {
7962 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
7963 mask
= PL0U_R
| PL1_RW
;
7983 /* min_EL EL1, secure mode only (we don't check the latter) */
7987 /* broken reginfo with out-of-range opc1 */
7991 /* assert our permissions are not too lax (stricter is fine) */
7992 assert((r
->access
& ~mask
) == 0);
7995 /* Check that the register definition has enough info to handle
7996 * reads and writes if they are permitted.
7998 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
7999 if (r
->access
& PL3_R
) {
8000 assert((r
->fieldoffset
||
8001 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8004 if (r
->access
& PL3_W
) {
8005 assert((r
->fieldoffset
||
8006 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8010 /* Bad type field probably means missing sentinel at end of reg list */
8011 assert(cptype_valid(r
->type
));
8012 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8013 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8014 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8015 for (state
= ARM_CP_STATE_AA32
;
8016 state
<= ARM_CP_STATE_AA64
; state
++) {
8017 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8020 if (state
== ARM_CP_STATE_AA32
) {
8021 /* Under AArch32 CP registers can be common
8022 * (same for secure and non-secure world) or banked.
8026 switch (r
->secure
) {
8027 case ARM_CP_SECSTATE_S
:
8028 case ARM_CP_SECSTATE_NS
:
8029 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8030 r
->secure
, crm
, opc1
, opc2
,
8034 name
= g_strdup_printf("%s_S", r
->name
);
8035 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8037 crm
, opc1
, opc2
, name
);
8039 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8041 crm
, opc1
, opc2
, r
->name
);
8045 /* AArch64 registers get mapped to non-secure instance
8047 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8049 crm
, opc1
, opc2
, r
->name
);
8057 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
8058 const ARMCPRegInfo
*regs
, void *opaque
)
8060 /* Define a whole list of registers */
8061 const ARMCPRegInfo
*r
;
8062 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8063 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
8068 * Modify ARMCPRegInfo for access from userspace.
8070 * This is a data driven modification directed by
8071 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8072 * user-space cannot alter any values and dynamic values pertaining to
8073 * execution state are hidden from user space view anyway.
8075 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
8077 const ARMCPRegUserSpaceInfo
*m
;
8080 for (m
= mods
; m
->name
; m
++) {
8081 GPatternSpec
*pat
= NULL
;
8083 pat
= g_pattern_spec_new(m
->name
);
8085 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8086 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8087 r
->type
= ARM_CP_CONST
;
8091 } else if (strcmp(r
->name
, m
->name
) == 0) {
8092 r
->type
= ARM_CP_CONST
;
8094 r
->resetvalue
&= m
->exported_bits
;
8095 r
->resetvalue
|= m
->fixed_bits
;
8100 g_pattern_spec_free(pat
);
8105 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8107 return g_hash_table_lookup(cpregs
, &encoded_cp
);
8110 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8113 /* Helper coprocessor write function for write-ignore registers */
8116 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8118 /* Helper coprocessor write function for read-as-zero registers */
8122 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8124 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8127 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8129 /* Return true if it is not valid for us to switch to
8130 * this CPU mode (ie all the UNPREDICTABLE cases in
8131 * the ARM ARM CPSRWriteByInstr pseudocode).
8134 /* Changes to or from Hyp via MSR and CPS are illegal. */
8135 if (write_type
== CPSRWriteByInstr
&&
8136 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8137 mode
== ARM_CPU_MODE_HYP
)) {
8142 case ARM_CPU_MODE_USR
:
8144 case ARM_CPU_MODE_SYS
:
8145 case ARM_CPU_MODE_SVC
:
8146 case ARM_CPU_MODE_ABT
:
8147 case ARM_CPU_MODE_UND
:
8148 case ARM_CPU_MODE_IRQ
:
8149 case ARM_CPU_MODE_FIQ
:
8150 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8151 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8153 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8154 * and CPS are treated as illegal mode changes.
8156 if (write_type
== CPSRWriteByInstr
&&
8157 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8158 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
8162 case ARM_CPU_MODE_HYP
:
8163 return !arm_feature(env
, ARM_FEATURE_EL2
)
8164 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
8165 case ARM_CPU_MODE_MON
:
8166 return arm_current_el(env
) < 3;
8172 uint32_t cpsr_read(CPUARMState
*env
)
8175 ZF
= (env
->ZF
== 0);
8176 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
8177 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
8178 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
8179 | ((env
->condexec_bits
& 0xfc) << 8)
8180 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
8183 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
8184 CPSRWriteType write_type
)
8186 uint32_t changed_daif
;
8188 if (mask
& CPSR_NZCV
) {
8189 env
->ZF
= (~val
) & CPSR_Z
;
8191 env
->CF
= (val
>> 29) & 1;
8192 env
->VF
= (val
<< 3) & 0x80000000;
8195 env
->QF
= ((val
& CPSR_Q
) != 0);
8197 env
->thumb
= ((val
& CPSR_T
) != 0);
8198 if (mask
& CPSR_IT_0_1
) {
8199 env
->condexec_bits
&= ~3;
8200 env
->condexec_bits
|= (val
>> 25) & 3;
8202 if (mask
& CPSR_IT_2_7
) {
8203 env
->condexec_bits
&= 3;
8204 env
->condexec_bits
|= (val
>> 8) & 0xfc;
8206 if (mask
& CPSR_GE
) {
8207 env
->GE
= (val
>> 16) & 0xf;
8210 /* In a V7 implementation that includes the security extensions but does
8211 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8212 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8213 * bits respectively.
8215 * In a V8 implementation, it is permitted for privileged software to
8216 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8218 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
8219 arm_feature(env
, ARM_FEATURE_EL3
) &&
8220 !arm_feature(env
, ARM_FEATURE_EL2
) &&
8221 !arm_is_secure(env
)) {
8223 changed_daif
= (env
->daif
^ val
) & mask
;
8225 if (changed_daif
& CPSR_A
) {
8226 /* Check to see if we are allowed to change the masking of async
8227 * abort exceptions from a non-secure state.
8229 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
8230 qemu_log_mask(LOG_GUEST_ERROR
,
8231 "Ignoring attempt to switch CPSR_A flag from "
8232 "non-secure world with SCR.AW bit clear\n");
8237 if (changed_daif
& CPSR_F
) {
8238 /* Check to see if we are allowed to change the masking of FIQ
8239 * exceptions from a non-secure state.
8241 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
8242 qemu_log_mask(LOG_GUEST_ERROR
,
8243 "Ignoring attempt to switch CPSR_F flag from "
8244 "non-secure world with SCR.FW bit clear\n");
8248 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8249 * If this bit is set software is not allowed to mask
8250 * FIQs, but is allowed to set CPSR_F to 0.
8252 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
8254 qemu_log_mask(LOG_GUEST_ERROR
,
8255 "Ignoring attempt to enable CPSR_F flag "
8256 "(non-maskable FIQ [NMFI] support enabled)\n");
8262 env
->daif
&= ~(CPSR_AIF
& mask
);
8263 env
->daif
|= val
& CPSR_AIF
& mask
;
8265 if (write_type
!= CPSRWriteRaw
&&
8266 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
8267 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
8268 /* Note that we can only get here in USR mode if this is a
8269 * gdb stub write; for this case we follow the architectural
8270 * behaviour for guest writes in USR mode of ignoring an attempt
8271 * to switch mode. (Those are caught by translate.c for writes
8272 * triggered by guest instructions.)
8275 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
8276 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8277 * v7, and has defined behaviour in v8:
8278 * + leave CPSR.M untouched
8279 * + allow changes to the other CPSR fields
8281 * For user changes via the GDB stub, we don't set PSTATE.IL,
8282 * as this would be unnecessarily harsh for a user error.
8285 if (write_type
!= CPSRWriteByGDBStub
&&
8286 arm_feature(env
, ARM_FEATURE_V8
)) {
8290 qemu_log_mask(LOG_GUEST_ERROR
,
8291 "Illegal AArch32 mode switch attempt from %s to %s\n",
8292 aarch32_mode_name(env
->uncached_cpsr
),
8293 aarch32_mode_name(val
));
8295 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
8296 write_type
== CPSRWriteExceptionReturn
?
8297 "Exception return from AArch32" :
8298 "AArch32 mode switch from",
8299 aarch32_mode_name(env
->uncached_cpsr
),
8300 aarch32_mode_name(val
), env
->regs
[15]);
8301 switch_mode(env
, val
& CPSR_M
);
8304 mask
&= ~CACHED_CPSR_BITS
;
8305 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
8308 /* Sign/zero extend */
8309 uint32_t HELPER(sxtb16
)(uint32_t x
)
8312 res
= (uint16_t)(int8_t)x
;
8313 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
8317 uint32_t HELPER(uxtb16
)(uint32_t x
)
8320 res
= (uint16_t)(uint8_t)x
;
8321 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
8325 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
8329 if (num
== INT_MIN
&& den
== -1)
8334 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
8341 uint32_t HELPER(rbit
)(uint32_t x
)
8346 #ifdef CONFIG_USER_ONLY
8348 static void switch_mode(CPUARMState
*env
, int mode
)
8350 ARMCPU
*cpu
= env_archcpu(env
);
8352 if (mode
!= ARM_CPU_MODE_USR
) {
8353 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
8357 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8358 uint32_t cur_el
, bool secure
)
8363 void aarch64_sync_64_to_32(CPUARMState
*env
)
8365 g_assert_not_reached();
8370 static void switch_mode(CPUARMState
*env
, int mode
)
8375 old_mode
= env
->uncached_cpsr
& CPSR_M
;
8376 if (mode
== old_mode
)
8379 if (old_mode
== ARM_CPU_MODE_FIQ
) {
8380 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8381 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
8382 } else if (mode
== ARM_CPU_MODE_FIQ
) {
8383 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8384 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
8387 i
= bank_number(old_mode
);
8388 env
->banked_r13
[i
] = env
->regs
[13];
8389 env
->banked_spsr
[i
] = env
->spsr
;
8391 i
= bank_number(mode
);
8392 env
->regs
[13] = env
->banked_r13
[i
];
8393 env
->spsr
= env
->banked_spsr
[i
];
8395 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
8396 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
8399 /* Physical Interrupt Target EL Lookup Table
8401 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
8403 * The below multi-dimensional table is used for looking up the target
8404 * exception level given numerous condition criteria. Specifically, the
8405 * target EL is based on SCR and HCR routing controls as well as the
8406 * currently executing EL and secure state.
8409 * target_el_table[2][2][2][2][2][4]
8410 * | | | | | +--- Current EL
8411 * | | | | +------ Non-secure(0)/Secure(1)
8412 * | | | +--------- HCR mask override
8413 * | | +------------ SCR exec state control
8414 * | +--------------- SCR mask override
8415 * +------------------ 32-bit(0)/64-bit(1) EL3
8417 * The table values are as such:
8421 * The ARM ARM target EL table includes entries indicating that an "exception
8422 * is not taken". The two cases where this is applicable are:
8423 * 1) An exception is taken from EL3 but the SCR does not have the exception
8425 * 2) An exception is taken from EL2 but the HCR does not have the exception
8427 * In these two cases, the below table contain a target of EL1. This value is
8428 * returned as it is expected that the consumer of the table data will check
8429 * for "target EL >= current EL" to ensure the exception is not taken.
8433 * BIT IRQ IMO Non-secure Secure
8434 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
8436 static const int8_t target_el_table
[2][2][2][2][2][4] = {
8437 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8438 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
8439 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8440 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
8441 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8442 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
8443 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8444 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
8445 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
8446 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
8447 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
8448 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
8449 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8450 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
8451 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8452 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
8456 * Determine the target EL for physical exceptions
8458 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8459 uint32_t cur_el
, bool secure
)
8461 CPUARMState
*env
= cs
->env_ptr
;
8466 /* Is the highest EL AArch64? */
8467 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
8470 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8471 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
8473 /* Either EL2 is the highest EL (and so the EL2 register width
8474 * is given by is64); or there is no EL2 or EL3, in which case
8475 * the value of 'rw' does not affect the table lookup anyway.
8480 hcr_el2
= arm_hcr_el2_eff(env
);
8483 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
8484 hcr
= hcr_el2
& HCR_IMO
;
8487 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
8488 hcr
= hcr_el2
& HCR_FMO
;
8491 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
8492 hcr
= hcr_el2
& HCR_AMO
;
8497 * For these purposes, TGE and AMO/IMO/FMO both force the
8498 * interrupt to EL2. Fold TGE into the bit extracted above.
8500 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
8502 /* Perform a table-lookup for the target EL given the current state */
8503 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
8505 assert(target_el
> 0);
8510 void arm_log_exception(int idx
)
8512 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
8513 const char *exc
= NULL
;
8514 static const char * const excnames
[] = {
8515 [EXCP_UDEF
] = "Undefined Instruction",
8517 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
8518 [EXCP_DATA_ABORT
] = "Data Abort",
8521 [EXCP_BKPT
] = "Breakpoint",
8522 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
8523 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
8524 [EXCP_HVC
] = "Hypervisor Call",
8525 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
8526 [EXCP_SMC
] = "Secure Monitor Call",
8527 [EXCP_VIRQ
] = "Virtual IRQ",
8528 [EXCP_VFIQ
] = "Virtual FIQ",
8529 [EXCP_SEMIHOST
] = "Semihosting call",
8530 [EXCP_NOCP
] = "v7M NOCP UsageFault",
8531 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
8532 [EXCP_STKOF
] = "v8M STKOF UsageFault",
8533 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
8534 [EXCP_LSERR
] = "v8M LSERR UsageFault",
8535 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
8538 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
8539 exc
= excnames
[idx
];
8544 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
8549 * Function used to synchronize QEMU's AArch64 register set with AArch32
8550 * register set. This is necessary when switching between AArch32 and AArch64
8553 void aarch64_sync_32_to_64(CPUARMState
*env
)
8556 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8558 /* We can blanket copy R[0:7] to X[0:7] */
8559 for (i
= 0; i
< 8; i
++) {
8560 env
->xregs
[i
] = env
->regs
[i
];
8564 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
8565 * Otherwise, they come from the banked user regs.
8567 if (mode
== ARM_CPU_MODE_FIQ
) {
8568 for (i
= 8; i
< 13; i
++) {
8569 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
8572 for (i
= 8; i
< 13; i
++) {
8573 env
->xregs
[i
] = env
->regs
[i
];
8578 * Registers x13-x23 are the various mode SP and FP registers. Registers
8579 * r13 and r14 are only copied if we are in that mode, otherwise we copy
8580 * from the mode banked register.
8582 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8583 env
->xregs
[13] = env
->regs
[13];
8584 env
->xregs
[14] = env
->regs
[14];
8586 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
8587 /* HYP is an exception in that it is copied from r14 */
8588 if (mode
== ARM_CPU_MODE_HYP
) {
8589 env
->xregs
[14] = env
->regs
[14];
8591 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
8595 if (mode
== ARM_CPU_MODE_HYP
) {
8596 env
->xregs
[15] = env
->regs
[13];
8598 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
8601 if (mode
== ARM_CPU_MODE_IRQ
) {
8602 env
->xregs
[16] = env
->regs
[14];
8603 env
->xregs
[17] = env
->regs
[13];
8605 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
8606 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
8609 if (mode
== ARM_CPU_MODE_SVC
) {
8610 env
->xregs
[18] = env
->regs
[14];
8611 env
->xregs
[19] = env
->regs
[13];
8613 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
8614 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
8617 if (mode
== ARM_CPU_MODE_ABT
) {
8618 env
->xregs
[20] = env
->regs
[14];
8619 env
->xregs
[21] = env
->regs
[13];
8621 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
8622 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
8625 if (mode
== ARM_CPU_MODE_UND
) {
8626 env
->xregs
[22] = env
->regs
[14];
8627 env
->xregs
[23] = env
->regs
[13];
8629 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
8630 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
8634 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8635 * mode, then we can copy from r8-r14. Otherwise, we copy from the
8636 * FIQ bank for r8-r14.
8638 if (mode
== ARM_CPU_MODE_FIQ
) {
8639 for (i
= 24; i
< 31; i
++) {
8640 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
8643 for (i
= 24; i
< 29; i
++) {
8644 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
8646 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
8647 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
8650 env
->pc
= env
->regs
[15];
8654 * Function used to synchronize QEMU's AArch32 register set with AArch64
8655 * register set. This is necessary when switching between AArch32 and AArch64
8658 void aarch64_sync_64_to_32(CPUARMState
*env
)
8661 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8663 /* We can blanket copy X[0:7] to R[0:7] */
8664 for (i
= 0; i
< 8; i
++) {
8665 env
->regs
[i
] = env
->xregs
[i
];
8669 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
8670 * Otherwise, we copy x8-x12 into the banked user regs.
8672 if (mode
== ARM_CPU_MODE_FIQ
) {
8673 for (i
= 8; i
< 13; i
++) {
8674 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
8677 for (i
= 8; i
< 13; i
++) {
8678 env
->regs
[i
] = env
->xregs
[i
];
8683 * Registers r13 & r14 depend on the current mode.
8684 * If we are in a given mode, we copy the corresponding x registers to r13
8685 * and r14. Otherwise, we copy the x register to the banked r13 and r14
8688 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8689 env
->regs
[13] = env
->xregs
[13];
8690 env
->regs
[14] = env
->xregs
[14];
8692 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
8695 * HYP is an exception in that it does not have its own banked r14 but
8696 * shares the USR r14
8698 if (mode
== ARM_CPU_MODE_HYP
) {
8699 env
->regs
[14] = env
->xregs
[14];
8701 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
8705 if (mode
== ARM_CPU_MODE_HYP
) {
8706 env
->regs
[13] = env
->xregs
[15];
8708 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
8711 if (mode
== ARM_CPU_MODE_IRQ
) {
8712 env
->regs
[14] = env
->xregs
[16];
8713 env
->regs
[13] = env
->xregs
[17];
8715 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
8716 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
8719 if (mode
== ARM_CPU_MODE_SVC
) {
8720 env
->regs
[14] = env
->xregs
[18];
8721 env
->regs
[13] = env
->xregs
[19];
8723 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
8724 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
8727 if (mode
== ARM_CPU_MODE_ABT
) {
8728 env
->regs
[14] = env
->xregs
[20];
8729 env
->regs
[13] = env
->xregs
[21];
8731 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
8732 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
8735 if (mode
== ARM_CPU_MODE_UND
) {
8736 env
->regs
[14] = env
->xregs
[22];
8737 env
->regs
[13] = env
->xregs
[23];
8739 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
8740 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
8743 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8744 * mode, then we can copy to r8-r14. Otherwise, we copy to the
8745 * FIQ bank for r8-r14.
8747 if (mode
== ARM_CPU_MODE_FIQ
) {
8748 for (i
= 24; i
< 31; i
++) {
8749 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
8752 for (i
= 24; i
< 29; i
++) {
8753 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
8755 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
8756 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
8759 env
->regs
[15] = env
->pc
;
8762 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
8763 uint32_t mask
, uint32_t offset
,
8766 /* Change the CPU state so as to actually take the exception. */
8767 switch_mode(env
, new_mode
);
8769 * For exceptions taken to AArch32 we must clear the SS bit in both
8770 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8772 env
->uncached_cpsr
&= ~PSTATE_SS
;
8773 env
->spsr
= cpsr_read(env
);
8774 /* Clear IT bits. */
8775 env
->condexec_bits
= 0;
8776 /* Switch to the new mode, and to the correct instruction set. */
8777 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8778 /* Set new mode endianness */
8779 env
->uncached_cpsr
&= ~CPSR_E
;
8780 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
8781 env
->uncached_cpsr
|= CPSR_E
;
8783 /* J and IL must always be cleared for exception entry */
8784 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
8787 if (new_mode
== ARM_CPU_MODE_HYP
) {
8788 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
8789 env
->elr_el
[2] = env
->regs
[15];
8792 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8793 * and we should just guard the thumb mode on V4
8795 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8797 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8799 env
->regs
[14] = env
->regs
[15] + offset
;
8801 env
->regs
[15] = newpc
;
8802 arm_rebuild_hflags(env
);
8805 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
8808 * Handle exception entry to Hyp mode; this is sufficiently
8809 * different to entry to other AArch32 modes that we handle it
8812 * The vector table entry used is always the 0x14 Hyp mode entry point,
8813 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8814 * The offset applied to the preferred return address is always zero
8815 * (see DDI0487C.a section G1.12.3).
8816 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8818 uint32_t addr
, mask
;
8819 ARMCPU
*cpu
= ARM_CPU(cs
);
8820 CPUARMState
*env
= &cpu
->env
;
8822 switch (cs
->exception_index
) {
8830 /* Fall through to prefetch abort. */
8831 case EXCP_PREFETCH_ABORT
:
8832 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
8833 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
8834 (uint32_t)env
->exception
.vaddress
);
8837 case EXCP_DATA_ABORT
:
8838 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
8839 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
8840 (uint32_t)env
->exception
.vaddress
);
8856 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8859 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
8860 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8862 * QEMU syndrome values are v8-style. v7 has the IL bit
8863 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
8864 * If this is a v7 CPU, squash the IL bit in those cases.
8866 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
8867 (cs
->exception_index
== EXCP_DATA_ABORT
&&
8868 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
8869 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
8870 env
->exception
.syndrome
&= ~ARM_EL_IL
;
8873 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
8876 if (arm_current_el(env
) != 2 && addr
< 0x14) {
8881 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
8884 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
8887 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
8891 addr
+= env
->cp15
.hvbar
;
8893 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
8896 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
8898 ARMCPU
*cpu
= ARM_CPU(cs
);
8899 CPUARMState
*env
= &cpu
->env
;
8906 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
8907 switch (syn_get_ec(env
->exception
.syndrome
)) {
8909 case EC_BREAKPOINT_SAME_EL
:
8913 case EC_WATCHPOINT_SAME_EL
:
8919 case EC_VECTORCATCH
:
8928 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
8931 if (env
->exception
.target_el
== 2) {
8932 arm_cpu_do_interrupt_aarch32_hyp(cs
);
8936 switch (cs
->exception_index
) {
8938 new_mode
= ARM_CPU_MODE_UND
;
8947 new_mode
= ARM_CPU_MODE_SVC
;
8950 /* The PC already points to the next instruction. */
8954 /* Fall through to prefetch abort. */
8955 case EXCP_PREFETCH_ABORT
:
8956 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
8957 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
8958 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
8959 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
8960 new_mode
= ARM_CPU_MODE_ABT
;
8962 mask
= CPSR_A
| CPSR_I
;
8965 case EXCP_DATA_ABORT
:
8966 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
8967 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
8968 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
8970 (uint32_t)env
->exception
.vaddress
);
8971 new_mode
= ARM_CPU_MODE_ABT
;
8973 mask
= CPSR_A
| CPSR_I
;
8977 new_mode
= ARM_CPU_MODE_IRQ
;
8979 /* Disable IRQ and imprecise data aborts. */
8980 mask
= CPSR_A
| CPSR_I
;
8982 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
8983 /* IRQ routed to monitor mode */
8984 new_mode
= ARM_CPU_MODE_MON
;
8989 new_mode
= ARM_CPU_MODE_FIQ
;
8991 /* Disable FIQ, IRQ and imprecise data aborts. */
8992 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8993 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
8994 /* FIQ routed to monitor mode */
8995 new_mode
= ARM_CPU_MODE_MON
;
9000 new_mode
= ARM_CPU_MODE_IRQ
;
9002 /* Disable IRQ and imprecise data aborts. */
9003 mask
= CPSR_A
| CPSR_I
;
9007 new_mode
= ARM_CPU_MODE_FIQ
;
9009 /* Disable FIQ, IRQ and imprecise data aborts. */
9010 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9014 new_mode
= ARM_CPU_MODE_MON
;
9016 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9020 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9021 return; /* Never happens. Keep compiler happy. */
9024 if (new_mode
== ARM_CPU_MODE_MON
) {
9025 addr
+= env
->cp15
.mvbar
;
9026 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9027 /* High vectors. When enabled, base address cannot be remapped. */
9030 /* ARM v7 architectures provide a vector base address register to remap
9031 * the interrupt vector table.
9032 * This register is only followed in non-monitor mode, and is banked.
9033 * Note: only bits 31:5 are valid.
9035 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9038 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9039 env
->cp15
.scr_el3
&= ~SCR_NS
;
9042 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9045 /* Handle exception entry to a target EL which is using AArch64 */
9046 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9048 ARMCPU
*cpu
= ARM_CPU(cs
);
9049 CPUARMState
*env
= &cpu
->env
;
9050 unsigned int new_el
= env
->exception
.target_el
;
9051 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9052 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9053 unsigned int cur_el
= arm_current_el(env
);
9056 * Note that new_el can never be 0. If cur_el is 0, then
9057 * el0_a64 is is_a64(), else el0_a64 is ignored.
9059 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9061 if (cur_el
< new_el
) {
9062 /* Entry vector offset depends on whether the implemented EL
9063 * immediately lower than the target level is using AArch32 or AArch64
9070 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9073 hcr
= arm_hcr_el2_eff(env
);
9074 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
9075 is_aa64
= (hcr
& HCR_RW
) != 0;
9080 is_aa64
= is_a64(env
);
9083 g_assert_not_reached();
9091 } else if (pstate_read(env
) & PSTATE_SP
) {
9095 switch (cs
->exception_index
) {
9096 case EXCP_PREFETCH_ABORT
:
9097 case EXCP_DATA_ABORT
:
9098 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
9099 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
9100 env
->cp15
.far_el
[new_el
]);
9108 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
9110 * QEMU internal FP/SIMD syndromes from AArch32 include the
9111 * TA and coproc fields which are only exposed if the exception
9112 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9113 * AArch64 format syndrome.
9115 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
9117 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9128 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9132 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
9133 aarch64_save_sp(env
, arm_current_el(env
));
9134 env
->elr_el
[new_el
] = env
->pc
;
9136 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
9137 env
->elr_el
[new_el
] = env
->regs
[15];
9139 aarch64_sync_32_to_64(env
);
9141 env
->condexec_bits
= 0;
9143 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
9144 env
->elr_el
[new_el
]);
9146 pstate_write(env
, PSTATE_DAIF
| new_mode
);
9148 aarch64_restore_sp(env
, new_el
);
9149 helper_rebuild_hflags_a64(env
, new_el
);
9153 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
9154 new_el
, env
->pc
, pstate_read(env
));
9158 * Do semihosting call and set the appropriate return value. All the
9159 * permission and validity checks have been done at translate time.
9161 * We only see semihosting exceptions in TCG only as they are not
9162 * trapped to the hypervisor in KVM.
9165 static void handle_semihosting(CPUState
*cs
)
9167 ARMCPU
*cpu
= ARM_CPU(cs
);
9168 CPUARMState
*env
= &cpu
->env
;
9171 qemu_log_mask(CPU_LOG_INT
,
9172 "...handling as semihosting call 0x%" PRIx64
"\n",
9174 env
->xregs
[0] = do_arm_semihosting(env
);
9177 qemu_log_mask(CPU_LOG_INT
,
9178 "...handling as semihosting call 0x%x\n",
9180 env
->regs
[0] = do_arm_semihosting(env
);
9181 env
->regs
[15] += env
->thumb
? 2 : 4;
9186 /* Handle a CPU exception for A and R profile CPUs.
9187 * Do any appropriate logging, handle PSCI calls, and then hand off
9188 * to the AArch64-entry or AArch32-entry function depending on the
9189 * target exception level's register width.
9191 void arm_cpu_do_interrupt(CPUState
*cs
)
9193 ARMCPU
*cpu
= ARM_CPU(cs
);
9194 CPUARMState
*env
= &cpu
->env
;
9195 unsigned int new_el
= env
->exception
.target_el
;
9197 assert(!arm_feature(env
, ARM_FEATURE_M
));
9199 arm_log_exception(cs
->exception_index
);
9200 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
9202 if (qemu_loglevel_mask(CPU_LOG_INT
)
9203 && !excp_is_internal(cs
->exception_index
)) {
9204 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
9205 syn_get_ec(env
->exception
.syndrome
),
9206 env
->exception
.syndrome
);
9209 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
9210 arm_handle_psci_call(cpu
);
9211 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
9216 * Semihosting semantics depend on the register width of the code
9217 * that caused the exception, not the target exception level, so
9218 * must be handled here.
9221 if (cs
->exception_index
== EXCP_SEMIHOST
) {
9222 handle_semihosting(cs
);
9227 /* Hooks may change global state so BQL should be held, also the
9228 * BQL needs to be held for any modification of
9229 * cs->interrupt_request.
9231 g_assert(qemu_mutex_iothread_locked());
9233 arm_call_pre_el_change_hook(cpu
);
9235 assert(!excp_is_internal(cs
->exception_index
));
9236 if (arm_el_is_aa64(env
, new_el
)) {
9237 arm_cpu_do_interrupt_aarch64(cs
);
9239 arm_cpu_do_interrupt_aarch32(cs
);
9242 arm_call_el_change_hook(cpu
);
9244 if (!kvm_enabled()) {
9245 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
9248 #endif /* !CONFIG_USER_ONLY */
9250 /* Return the exception level which controls this address translation regime */
9251 static uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9254 case ARMMMUIdx_E20_0
:
9255 case ARMMMUIdx_E20_2
:
9256 case ARMMMUIdx_E20_2_PAN
:
9257 case ARMMMUIdx_Stage2
:
9262 case ARMMMUIdx_SE10_0
:
9263 return arm_el_is_aa64(env
, 3) ? 1 : 3;
9264 case ARMMMUIdx_SE10_1
:
9265 case ARMMMUIdx_SE10_1_PAN
:
9266 case ARMMMUIdx_Stage1_E0
:
9267 case ARMMMUIdx_Stage1_E1
:
9268 case ARMMMUIdx_Stage1_E1_PAN
:
9269 case ARMMMUIdx_E10_0
:
9270 case ARMMMUIdx_E10_1
:
9271 case ARMMMUIdx_E10_1_PAN
:
9272 case ARMMMUIdx_MPrivNegPri
:
9273 case ARMMMUIdx_MUserNegPri
:
9274 case ARMMMUIdx_MPriv
:
9275 case ARMMMUIdx_MUser
:
9276 case ARMMMUIdx_MSPrivNegPri
:
9277 case ARMMMUIdx_MSUserNegPri
:
9278 case ARMMMUIdx_MSPriv
:
9279 case ARMMMUIdx_MSUser
:
9282 g_assert_not_reached();
9286 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
9288 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
9290 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
9291 el
= (mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1);
9293 return env
->cp15
.sctlr_el
[el
];
9296 /* Return the SCTLR value which controls this address translation regime */
9297 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9299 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
9302 #ifndef CONFIG_USER_ONLY
9304 /* Return true if the specified stage of address translation is disabled */
9305 static inline bool regime_translation_disabled(CPUARMState
*env
,
9308 if (arm_feature(env
, ARM_FEATURE_M
)) {
9309 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
9310 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
9311 case R_V7M_MPU_CTRL_ENABLE_MASK
:
9312 /* Enabled, but not for HardFault and NMI */
9313 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
9314 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
9315 /* Enabled for all cases */
9319 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9320 * we warned about that in armv7m_nvic.c when the guest set it.
9326 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9327 /* HCR.DC means HCR.VM behaves as 1 */
9328 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
9331 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
9332 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
9333 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
9338 if ((env
->cp15
.hcr_el2
& HCR_DC
) && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
9339 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
9343 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
9346 static inline bool regime_translation_big_endian(CPUARMState
*env
,
9349 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
9352 /* Return the TTBR associated with this translation regime */
9353 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9356 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9357 return env
->cp15
.vttbr_el2
;
9360 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
9362 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
9366 #endif /* !CONFIG_USER_ONLY */
9368 /* Return the TCR controlling this translation regime */
9369 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9371 if (mmu_idx
== ARMMMUIdx_Stage2
) {
9372 return &env
->cp15
.vtcr_el2
;
9374 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
9377 /* Convert a possible stage1+2 MMU index into the appropriate
9380 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
9383 case ARMMMUIdx_E10_0
:
9384 return ARMMMUIdx_Stage1_E0
;
9385 case ARMMMUIdx_E10_1
:
9386 return ARMMMUIdx_Stage1_E1
;
9387 case ARMMMUIdx_E10_1_PAN
:
9388 return ARMMMUIdx_Stage1_E1_PAN
;
9394 /* Return true if the translation regime is using LPAE format page tables */
9395 static inline bool regime_using_lpae_format(CPUARMState
*env
,
9398 int el
= regime_el(env
, mmu_idx
);
9399 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
9402 if (arm_feature(env
, ARM_FEATURE_LPAE
)
9403 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
9409 /* Returns true if the stage 1 translation regime is using LPAE format page
9410 * tables. Used when raising alignment exceptions, whose FSR changes depending
9411 * on whether the long or short descriptor format is in use. */
9412 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9414 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
9416 return regime_using_lpae_format(env
, mmu_idx
);
9419 #ifndef CONFIG_USER_ONLY
9420 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
9423 case ARMMMUIdx_SE10_0
:
9424 case ARMMMUIdx_E20_0
:
9425 case ARMMMUIdx_Stage1_E0
:
9426 case ARMMMUIdx_MUser
:
9427 case ARMMMUIdx_MSUser
:
9428 case ARMMMUIdx_MUserNegPri
:
9429 case ARMMMUIdx_MSUserNegPri
:
9433 case ARMMMUIdx_E10_0
:
9434 case ARMMMUIdx_E10_1
:
9435 case ARMMMUIdx_E10_1_PAN
:
9436 g_assert_not_reached();
9440 /* Translate section/page access permissions to page
9441 * R/W protection flags
9444 * @mmu_idx: MMU index indicating required translation regime
9445 * @ap: The 3-bit access permissions (AP[2:0])
9446 * @domain_prot: The 2-bit domain access permissions
9448 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9449 int ap
, int domain_prot
)
9451 bool is_user
= regime_is_user(env
, mmu_idx
);
9453 if (domain_prot
== 3) {
9454 return PAGE_READ
| PAGE_WRITE
;
9459 if (arm_feature(env
, ARM_FEATURE_V7
)) {
9462 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
9464 return is_user
? 0 : PAGE_READ
;
9471 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9476 return PAGE_READ
| PAGE_WRITE
;
9479 return PAGE_READ
| PAGE_WRITE
;
9480 case 4: /* Reserved. */
9483 return is_user
? 0 : PAGE_READ
;
9487 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
9492 g_assert_not_reached();
9496 /* Translate section/page access permissions to page
9497 * R/W protection flags.
9499 * @ap: The 2-bit simple AP (AP[2:1])
9500 * @is_user: TRUE if accessing from PL0
9502 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
9506 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
9508 return PAGE_READ
| PAGE_WRITE
;
9510 return is_user
? 0 : PAGE_READ
;
9514 g_assert_not_reached();
9519 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
9521 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
9524 /* Translate S2 section/page access permissions to protection flags
9527 * @s2ap: The 2-bit stage2 access permissions (S2AP)
9528 * @xn: XN (execute-never) bit
9530 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
9541 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
9548 /* Translate section/page access permissions to protection flags
9551 * @mmu_idx: MMU index indicating required translation regime
9552 * @is_aa64: TRUE if AArch64
9553 * @ap: The 2-bit simple AP (AP[2:1])
9554 * @ns: NS (non-secure) bit
9555 * @xn: XN (execute-never) bit
9556 * @pxn: PXN (privileged execute-never) bit
9558 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
9559 int ap
, int ns
, int xn
, int pxn
)
9561 bool is_user
= regime_is_user(env
, mmu_idx
);
9562 int prot_rw
, user_rw
;
9566 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
9568 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
9572 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
9575 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
9578 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
9582 /* TODO have_wxn should be replaced with
9583 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
9584 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
9585 * compatible processors have EL2, which is required for [U]WXN.
9587 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
9590 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
9594 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
9595 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
9597 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9598 switch (regime_el(env
, mmu_idx
)) {
9602 xn
= xn
|| !(user_rw
& PAGE_READ
);
9606 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
9608 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
9609 (uwxn
&& (user_rw
& PAGE_WRITE
));
9619 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
9622 return prot_rw
| PAGE_EXEC
;
9625 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9626 uint32_t *table
, uint32_t address
)
9628 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
9629 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9631 if (address
& tcr
->mask
) {
9632 if (tcr
->raw_tcr
& TTBCR_PD1
) {
9633 /* Translation table walk disabled for TTBR1 */
9636 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
9638 if (tcr
->raw_tcr
& TTBCR_PD0
) {
9639 /* Translation table walk disabled for TTBR0 */
9642 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
9644 *table
|= (address
>> 18) & 0x3ffc;
9648 /* Translate a S1 pagetable walk through S2 if needed. */
9649 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9650 hwaddr addr
, MemTxAttrs txattrs
,
9651 ARMMMUFaultInfo
*fi
)
9653 if (arm_mmu_idx_is_stage1_of_2(mmu_idx
) &&
9654 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
9655 target_ulong s2size
;
9659 ARMCacheAttrs cacheattrs
= {};
9660 ARMCacheAttrs
*pcacheattrs
= NULL
;
9662 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
9664 * PTW means we must fault if this S1 walk touches S2 Device
9665 * memory; otherwise we don't care about the attributes and can
9666 * save the S2 translation the effort of computing them.
9668 pcacheattrs
= &cacheattrs
;
9671 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_Stage2
, &s2pa
,
9672 &txattrs
, &s2prot
, &s2size
, fi
, pcacheattrs
);
9674 assert(fi
->type
!= ARMFault_None
);
9680 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
9681 /* Access was to Device memory: generate Permission fault */
9682 fi
->type
= ARMFault_Permission
;
9693 /* All loads done in the course of a page table walk go through here. */
9694 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9695 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9697 ARMCPU
*cpu
= ARM_CPU(cs
);
9698 CPUARMState
*env
= &cpu
->env
;
9699 MemTxAttrs attrs
= {};
9700 MemTxResult result
= MEMTX_OK
;
9704 attrs
.secure
= is_secure
;
9705 as
= arm_addressspace(cs
, attrs
);
9706 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9710 if (regime_translation_big_endian(env
, mmu_idx
)) {
9711 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
9713 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
9715 if (result
== MEMTX_OK
) {
9718 fi
->type
= ARMFault_SyncExternalOnWalk
;
9719 fi
->ea
= arm_extabort_type(result
);
9723 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9724 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9726 ARMCPU
*cpu
= ARM_CPU(cs
);
9727 CPUARMState
*env
= &cpu
->env
;
9728 MemTxAttrs attrs
= {};
9729 MemTxResult result
= MEMTX_OK
;
9733 attrs
.secure
= is_secure
;
9734 as
= arm_addressspace(cs
, attrs
);
9735 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9739 if (regime_translation_big_endian(env
, mmu_idx
)) {
9740 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
9742 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
9744 if (result
== MEMTX_OK
) {
9747 fi
->type
= ARMFault_SyncExternalOnWalk
;
9748 fi
->ea
= arm_extabort_type(result
);
9752 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
9753 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9754 hwaddr
*phys_ptr
, int *prot
,
9755 target_ulong
*page_size
,
9756 ARMMMUFaultInfo
*fi
)
9758 CPUState
*cs
= env_cpu(env
);
9769 /* Pagetable walk. */
9770 /* Lookup l1 descriptor. */
9771 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9772 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9773 fi
->type
= ARMFault_Translation
;
9776 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9778 if (fi
->type
!= ARMFault_None
) {
9782 domain
= (desc
>> 5) & 0x0f;
9783 if (regime_el(env
, mmu_idx
) == 1) {
9784 dacr
= env
->cp15
.dacr_ns
;
9786 dacr
= env
->cp15
.dacr_s
;
9788 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9790 /* Section translation fault. */
9791 fi
->type
= ARMFault_Translation
;
9797 if (domain_prot
== 0 || domain_prot
== 2) {
9798 fi
->type
= ARMFault_Domain
;
9803 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9804 ap
= (desc
>> 10) & 3;
9805 *page_size
= 1024 * 1024;
9807 /* Lookup l2 entry. */
9809 /* Coarse pagetable. */
9810 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9812 /* Fine pagetable. */
9813 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
9815 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9817 if (fi
->type
!= ARMFault_None
) {
9821 case 0: /* Page translation fault. */
9822 fi
->type
= ARMFault_Translation
;
9824 case 1: /* 64k page. */
9825 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9826 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
9827 *page_size
= 0x10000;
9829 case 2: /* 4k page. */
9830 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9831 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
9832 *page_size
= 0x1000;
9834 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
9836 /* ARMv6/XScale extended small page format */
9837 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
9838 || arm_feature(env
, ARM_FEATURE_V6
)) {
9839 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9840 *page_size
= 0x1000;
9842 /* UNPREDICTABLE in ARMv5; we choose to take a
9843 * page translation fault.
9845 fi
->type
= ARMFault_Translation
;
9849 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
9852 ap
= (desc
>> 4) & 3;
9855 /* Never happens, but compiler isn't smart enough to tell. */
9859 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9860 *prot
|= *prot
? PAGE_EXEC
: 0;
9861 if (!(*prot
& (1 << access_type
))) {
9862 /* Access permission fault. */
9863 fi
->type
= ARMFault_Permission
;
9866 *phys_ptr
= phys_addr
;
9869 fi
->domain
= domain
;
9874 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
9875 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9876 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
9877 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
9879 CPUState
*cs
= env_cpu(env
);
9893 /* Pagetable walk. */
9894 /* Lookup l1 descriptor. */
9895 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9896 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9897 fi
->type
= ARMFault_Translation
;
9900 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9902 if (fi
->type
!= ARMFault_None
) {
9906 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
9907 /* Section translation fault, or attempt to use the encoding
9908 * which is Reserved on implementations without PXN.
9910 fi
->type
= ARMFault_Translation
;
9913 if ((type
== 1) || !(desc
& (1 << 18))) {
9914 /* Page or Section. */
9915 domain
= (desc
>> 5) & 0x0f;
9917 if (regime_el(env
, mmu_idx
) == 1) {
9918 dacr
= env
->cp15
.dacr_ns
;
9920 dacr
= env
->cp15
.dacr_s
;
9925 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9926 if (domain_prot
== 0 || domain_prot
== 2) {
9927 /* Section or Page domain fault */
9928 fi
->type
= ARMFault_Domain
;
9932 if (desc
& (1 << 18)) {
9934 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
9935 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
9936 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
9937 *page_size
= 0x1000000;
9940 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9941 *page_size
= 0x100000;
9943 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
9944 xn
= desc
& (1 << 4);
9946 ns
= extract32(desc
, 19, 1);
9948 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
9949 pxn
= (desc
>> 2) & 1;
9951 ns
= extract32(desc
, 3, 1);
9952 /* Lookup l2 entry. */
9953 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9954 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9956 if (fi
->type
!= ARMFault_None
) {
9959 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
9961 case 0: /* Page translation fault. */
9962 fi
->type
= ARMFault_Translation
;
9964 case 1: /* 64k page. */
9965 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9966 xn
= desc
& (1 << 15);
9967 *page_size
= 0x10000;
9969 case 2: case 3: /* 4k page. */
9970 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9972 *page_size
= 0x1000;
9975 /* Never happens, but compiler isn't smart enough to tell. */
9979 if (domain_prot
== 3) {
9980 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9982 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
9985 if (xn
&& access_type
== MMU_INST_FETCH
) {
9986 fi
->type
= ARMFault_Permission
;
9990 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
9991 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
9992 /* The simplified model uses AP[0] as an access control bit. */
9993 if ((ap
& 1) == 0) {
9994 /* Access flag fault. */
9995 fi
->type
= ARMFault_AccessFlag
;
9998 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
10000 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10002 if (*prot
&& !xn
) {
10003 *prot
|= PAGE_EXEC
;
10005 if (!(*prot
& (1 << access_type
))) {
10006 /* Access permission fault. */
10007 fi
->type
= ARMFault_Permission
;
10012 /* The NS bit will (as required by the architecture) have no effect if
10013 * the CPU doesn't support TZ or this is a non-secure translation
10014 * regime, because the attribute will already be non-secure.
10016 attrs
->secure
= false;
10018 *phys_ptr
= phys_addr
;
10021 fi
->domain
= domain
;
10027 * check_s2_mmu_setup
10029 * @is_aa64: True if the translation regime is in AArch64 state
10030 * @startlevel: Suggested starting level
10031 * @inputsize: Bitsize of IPAs
10032 * @stride: Page-table stride (See the ARM ARM)
10034 * Returns true if the suggested S2 translation parameters are OK and
10037 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
10038 int inputsize
, int stride
)
10040 const int grainsize
= stride
+ 3;
10041 int startsizecheck
;
10043 /* Negative levels are never allowed. */
10048 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
10049 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
10054 CPUARMState
*env
= &cpu
->env
;
10055 unsigned int pamax
= arm_pamax(cpu
);
10058 case 13: /* 64KB Pages. */
10059 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
10063 case 11: /* 16KB Pages. */
10064 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
10068 case 9: /* 4KB Pages. */
10069 if (level
== 0 && pamax
<= 42) {
10074 g_assert_not_reached();
10077 /* Inputsize checks. */
10078 if (inputsize
> pamax
&&
10079 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
10080 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10084 /* AArch32 only supports 4KB pages. Assert on that. */
10085 assert(stride
== 9);
10094 /* Translate from the 4-bit stage 2 representation of
10095 * memory attributes (without cache-allocation hints) to
10096 * the 8-bit representation of the stage 1 MAIR registers
10097 * (which includes allocation hints).
10099 * ref: shared/translation/attrs/S2AttrDecode()
10100 * .../S2ConvertAttrsHints()
10102 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
10104 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
10105 uint8_t loattr
= extract32(s2attrs
, 0, 2);
10106 uint8_t hihint
= 0, lohint
= 0;
10108 if (hiattr
!= 0) { /* normal memory */
10109 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
10110 hiattr
= loattr
= 1; /* non-cacheable */
10112 if (hiattr
!= 1) { /* Write-through or write-back */
10113 hihint
= 3; /* RW allocate */
10115 if (loattr
!= 1) { /* Write-through or write-back */
10116 lohint
= 3; /* RW allocate */
10121 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
10123 #endif /* !CONFIG_USER_ONLY */
10125 ARMVAParameters
aa64_va_parameters_both(CPUARMState
*env
, uint64_t va
,
10128 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10129 bool tbi
, tbid
, epd
, hpd
, using16k
, using64k
;
10133 * Bit 55 is always between the two regions, and is canonical for
10134 * determining if address tagging is enabled.
10136 select
= extract64(va
, 55, 1);
10138 if (!regime_has_2_ranges(mmu_idx
)) {
10139 tsz
= extract32(tcr
, 0, 6);
10140 using64k
= extract32(tcr
, 14, 1);
10141 using16k
= extract32(tcr
, 15, 1);
10142 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10144 tbi
= tbid
= hpd
= false;
10146 tbi
= extract32(tcr
, 20, 1);
10147 hpd
= extract32(tcr
, 24, 1);
10148 tbid
= extract32(tcr
, 29, 1);
10151 } else if (!select
) {
10152 tsz
= extract32(tcr
, 0, 6);
10153 epd
= extract32(tcr
, 7, 1);
10154 using64k
= extract32(tcr
, 14, 1);
10155 using16k
= extract32(tcr
, 15, 1);
10156 tbi
= extract64(tcr
, 37, 1);
10157 hpd
= extract64(tcr
, 41, 1);
10158 tbid
= extract64(tcr
, 51, 1);
10160 int tg
= extract32(tcr
, 30, 2);
10161 using16k
= tg
== 1;
10162 using64k
= tg
== 3;
10163 tsz
= extract32(tcr
, 16, 6);
10164 epd
= extract32(tcr
, 23, 1);
10165 tbi
= extract64(tcr
, 38, 1);
10166 hpd
= extract64(tcr
, 42, 1);
10167 tbid
= extract64(tcr
, 52, 1);
10169 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
10170 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
10172 return (ARMVAParameters
) {
10179 .using16k
= using16k
,
10180 .using64k
= using64k
,
10184 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10185 ARMMMUIdx mmu_idx
, bool data
)
10187 ARMVAParameters ret
= aa64_va_parameters_both(env
, va
, mmu_idx
);
10189 /* Present TBI as a composite with TBID. */
10190 ret
.tbi
&= (data
|| !ret
.tbid
);
10194 #ifndef CONFIG_USER_ONLY
10195 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
10198 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10199 uint32_t el
= regime_el(env
, mmu_idx
);
10203 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10205 bool sext
= extract32(tcr
, 4, 1);
10206 bool sign
= extract32(tcr
, 3, 1);
10209 * If the sign-extend bit is not the same as t0sz[3], the result
10210 * is unpredictable. Flag this as a guest error.
10212 if (sign
!= sext
) {
10213 qemu_log_mask(LOG_GUEST_ERROR
,
10214 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10216 tsz
= sextract32(tcr
, 0, 4) + 8;
10220 } else if (el
== 2) {
10222 tsz
= extract32(tcr
, 0, 3);
10224 hpd
= extract64(tcr
, 24, 1);
10227 int t0sz
= extract32(tcr
, 0, 3);
10228 int t1sz
= extract32(tcr
, 16, 3);
10231 select
= va
> (0xffffffffu
>> t0sz
);
10233 /* Note that we will detect errors later. */
10234 select
= va
>= ~(0xffffffffu
>> t1sz
);
10238 epd
= extract32(tcr
, 7, 1);
10239 hpd
= extract64(tcr
, 41, 1);
10242 epd
= extract32(tcr
, 23, 1);
10243 hpd
= extract64(tcr
, 42, 1);
10245 /* For aarch32, hpd0 is not enabled without t2e as well. */
10246 hpd
&= extract32(tcr
, 6, 1);
10249 return (ARMVAParameters
) {
10257 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
10258 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10259 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
10260 target_ulong
*page_size_ptr
,
10261 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10263 ARMCPU
*cpu
= env_archcpu(env
);
10264 CPUState
*cs
= CPU(cpu
);
10265 /* Read an LPAE long-descriptor translation table. */
10266 ARMFaultType fault_type
= ARMFault_Translation
;
10268 ARMVAParameters param
;
10270 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
10271 uint32_t tableattrs
;
10272 target_ulong page_size
;
10275 int addrsize
, inputsize
;
10276 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10277 int ap
, ns
, xn
, pxn
;
10278 uint32_t el
= regime_el(env
, mmu_idx
);
10280 uint64_t descaddrmask
;
10281 bool aarch64
= arm_el_is_aa64(env
, el
);
10282 bool guarded
= false;
10285 * This code does not handle the different format TCR for VTCR_EL2.
10286 * This code also does not support shareability levels.
10287 * Attribute and permission bit handling should also be checked when adding
10288 * support for those page table walks.
10291 param
= aa64_va_parameters(env
, address
, mmu_idx
,
10292 access_type
!= MMU_INST_FETCH
);
10294 ttbr1_valid
= regime_has_2_ranges(mmu_idx
);
10295 addrsize
= 64 - 8 * param
.tbi
;
10296 inputsize
= 64 - param
.tsz
;
10298 param
= aa32_va_parameters(env
, address
, mmu_idx
);
10300 /* There is no TTBR1 for EL2 */
10301 ttbr1_valid
= (el
!= 2);
10302 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
10303 inputsize
= addrsize
- param
.tsz
;
10307 * We determined the region when collecting the parameters, but we
10308 * have not yet validated that the address is valid for the region.
10309 * Extract the top bits and verify that they all match select.
10311 * For aa32, if inputsize == addrsize, then we have selected the
10312 * region by exclusion in aa32_va_parameters and there is no more
10313 * validation to do here.
10315 if (inputsize
< addrsize
) {
10316 target_ulong top_bits
= sextract64(address
, inputsize
,
10317 addrsize
- inputsize
);
10318 if (-top_bits
!= param
.select
|| (param
.select
&& !ttbr1_valid
)) {
10319 /* The gap between the two regions is a Translation fault */
10320 fault_type
= ARMFault_Translation
;
10325 if (param
.using64k
) {
10327 } else if (param
.using16k
) {
10333 /* Note that QEMU ignores shareability and cacheability attributes,
10334 * so we don't need to do anything with the SH, ORGN, IRGN fields
10335 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
10336 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
10337 * implement any ASID-like capability so we can ignore it (instead
10338 * we will always flush the TLB any time the ASID is changed).
10340 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
10342 /* Here we should have set up all the parameters for the translation:
10343 * inputsize, ttbr, epd, stride, tbi
10347 /* Translation table walk disabled => Translation fault on TLB miss
10348 * Note: This is always 0 on 64-bit EL2 and EL3.
10353 if (mmu_idx
!= ARMMMUIdx_Stage2
) {
10354 /* The starting level depends on the virtual address size (which can
10355 * be up to 48 bits) and the translation granule size. It indicates
10356 * the number of strides (stride bits at a time) needed to
10357 * consume the bits of the input address. In the pseudocode this is:
10358 * level = 4 - RoundUp((inputsize - grainsize) / stride)
10359 * where their 'inputsize' is our 'inputsize', 'grainsize' is
10360 * our 'stride + 3' and 'stride' is our 'stride'.
10361 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
10362 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
10363 * = 4 - (inputsize - 4) / stride;
10365 level
= 4 - (inputsize
- 4) / stride
;
10367 /* For stage 2 translations the starting level is specified by the
10368 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
10370 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
10371 uint32_t startlevel
;
10374 if (!aarch64
|| stride
== 9) {
10375 /* AArch32 or 4KB pages */
10376 startlevel
= 2 - sl0
;
10378 /* 16KB or 64KB pages */
10379 startlevel
= 3 - sl0
;
10382 /* Check that the starting level is valid. */
10383 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
10384 inputsize
, stride
);
10386 fault_type
= ARMFault_Translation
;
10389 level
= startlevel
;
10392 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
10393 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
10395 /* Now we can extract the actual base address from the TTBR */
10396 descaddr
= extract64(ttbr
, 0, 48);
10397 descaddr
&= ~indexmask
;
10399 /* The address field in the descriptor goes up to bit 39 for ARMv7
10400 * but up to bit 47 for ARMv8, but we use the descaddrmask
10401 * up to bit 39 for AArch32, because we don't need other bits in that case
10402 * to construct next descriptor address (anyway they should be all zeroes).
10404 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
10405 ~indexmask_grainsize
;
10407 /* Secure accesses start with the page table in secure memory and
10408 * can be downgraded to non-secure at any step. Non-secure accesses
10409 * remain non-secure. We implement this by just ORing in the NSTable/NS
10410 * bits at each step.
10412 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
10414 uint64_t descriptor
;
10417 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
10419 nstable
= extract32(tableattrs
, 4, 1);
10420 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
10421 if (fi
->type
!= ARMFault_None
) {
10425 if (!(descriptor
& 1) ||
10426 (!(descriptor
& 2) && (level
== 3))) {
10427 /* Invalid, or the Reserved level 3 encoding */
10430 descaddr
= descriptor
& descaddrmask
;
10432 if ((descriptor
& 2) && (level
< 3)) {
10433 /* Table entry. The top five bits are attributes which may
10434 * propagate down through lower levels of the table (and
10435 * which are all arranged so that 0 means "no effect", so
10436 * we can gather them up by ORing in the bits at each level).
10438 tableattrs
|= extract64(descriptor
, 59, 5);
10440 indexmask
= indexmask_grainsize
;
10443 /* Block entry at level 1 or 2, or page entry at level 3.
10444 * These are basically the same thing, although the number
10445 * of bits we pull in from the vaddr varies.
10447 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
10448 descaddr
|= (address
& (page_size
- 1));
10449 /* Extract attributes from the descriptor */
10450 attrs
= extract64(descriptor
, 2, 10)
10451 | (extract64(descriptor
, 52, 12) << 10);
10453 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10454 /* Stage 2 table descriptors do not include any attribute fields */
10457 /* Merge in attributes from table descriptors */
10458 attrs
|= nstable
<< 3; /* NS */
10459 guarded
= extract64(descriptor
, 50, 1); /* GP */
10461 /* HPD disables all the table attributes except NSTable. */
10464 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
10465 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
10466 * means "force PL1 access only", which means forcing AP[1] to 0.
10468 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
10469 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
10472 /* Here descaddr is the final physical address, and attributes
10473 * are all in attrs.
10475 fault_type
= ARMFault_AccessFlag
;
10476 if ((attrs
& (1 << 8)) == 0) {
10481 ap
= extract32(attrs
, 4, 2);
10482 xn
= extract32(attrs
, 12, 1);
10484 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10486 *prot
= get_S2prot(env
, ap
, xn
);
10488 ns
= extract32(attrs
, 3, 1);
10489 pxn
= extract32(attrs
, 11, 1);
10490 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
10493 fault_type
= ARMFault_Permission
;
10494 if (!(*prot
& (1 << access_type
))) {
10499 /* The NS bit will (as required by the architecture) have no effect if
10500 * the CPU doesn't support TZ or this is a non-secure translation
10501 * regime, because the attribute will already be non-secure.
10503 txattrs
->secure
= false;
10505 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
10506 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
10507 txattrs
->target_tlb_bit0
= true;
10510 if (cacheattrs
!= NULL
) {
10511 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10512 cacheattrs
->attrs
= convert_stage2_attrs(env
,
10513 extract32(attrs
, 0, 4));
10515 /* Index into MAIR registers for cache attributes */
10516 uint8_t attrindx
= extract32(attrs
, 0, 3);
10517 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
10518 assert(attrindx
<= 7);
10519 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
10521 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
10524 *phys_ptr
= descaddr
;
10525 *page_size_ptr
= page_size
;
10529 fi
->type
= fault_type
;
10531 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
10532 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
);
10536 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
10538 int32_t address
, int *prot
)
10540 if (!arm_feature(env
, ARM_FEATURE_M
)) {
10541 *prot
= PAGE_READ
| PAGE_WRITE
;
10543 case 0xF0000000 ... 0xFFFFFFFF:
10544 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
10545 /* hivecs execing is ok */
10546 *prot
|= PAGE_EXEC
;
10549 case 0x00000000 ... 0x7FFFFFFF:
10550 *prot
|= PAGE_EXEC
;
10554 /* Default system address map for M profile cores.
10555 * The architecture specifies which regions are execute-never;
10556 * at the MPU level no other checks are defined.
10559 case 0x00000000 ... 0x1fffffff: /* ROM */
10560 case 0x20000000 ... 0x3fffffff: /* SRAM */
10561 case 0x60000000 ... 0x7fffffff: /* RAM */
10562 case 0x80000000 ... 0x9fffffff: /* RAM */
10563 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10565 case 0x40000000 ... 0x5fffffff: /* Peripheral */
10566 case 0xa0000000 ... 0xbfffffff: /* Device */
10567 case 0xc0000000 ... 0xdfffffff: /* Device */
10568 case 0xe0000000 ... 0xffffffff: /* System */
10569 *prot
= PAGE_READ
| PAGE_WRITE
;
10572 g_assert_not_reached();
10577 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
10578 ARMMMUIdx mmu_idx
, bool is_user
)
10580 /* Return true if we should use the default memory map as a
10581 * "background" region if there are no hits against any MPU regions.
10583 CPUARMState
*env
= &cpu
->env
;
10589 if (arm_feature(env
, ARM_FEATURE_M
)) {
10590 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
10591 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
10593 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
10597 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
10599 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
10600 return arm_feature(env
, ARM_FEATURE_M
) &&
10601 extract32(address
, 20, 12) == 0xe00;
10604 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
10606 /* True if address is in the M profile system region
10607 * 0xe0000000 - 0xffffffff
10609 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
10612 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
10613 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10614 hwaddr
*phys_ptr
, int *prot
,
10615 target_ulong
*page_size
,
10616 ARMMMUFaultInfo
*fi
)
10618 ARMCPU
*cpu
= env_archcpu(env
);
10620 bool is_user
= regime_is_user(env
, mmu_idx
);
10622 *phys_ptr
= address
;
10623 *page_size
= TARGET_PAGE_SIZE
;
10626 if (regime_translation_disabled(env
, mmu_idx
) ||
10627 m_is_ppb_region(env
, address
)) {
10628 /* MPU disabled or M profile PPB access: use default memory map.
10629 * The other case which uses the default memory map in the
10630 * v7M ARM ARM pseudocode is exception vector reads from the vector
10631 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
10632 * which always does a direct read using address_space_ldl(), rather
10633 * than going via this function, so we don't need to check that here.
10635 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10636 } else { /* MPU enabled */
10637 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10638 /* region search */
10639 uint32_t base
= env
->pmsav7
.drbar
[n
];
10640 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
10642 bool srdis
= false;
10644 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
10649 qemu_log_mask(LOG_GUEST_ERROR
,
10650 "DRSR[%d]: Rsize field cannot be 0\n", n
);
10654 rmask
= (1ull << rsize
) - 1;
10656 if (base
& rmask
) {
10657 qemu_log_mask(LOG_GUEST_ERROR
,
10658 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
10659 "to DRSR region size, mask = 0x%" PRIx32
"\n",
10664 if (address
< base
|| address
> base
+ rmask
) {
10666 * Address not in this region. We must check whether the
10667 * region covers addresses in the same page as our address.
10668 * In that case we must not report a size that covers the
10669 * whole page for a subsequent hit against a different MPU
10670 * region or the background region, because it would result in
10671 * incorrect TLB hits for subsequent accesses to addresses that
10672 * are in this MPU region.
10674 if (ranges_overlap(base
, rmask
,
10675 address
& TARGET_PAGE_MASK
,
10676 TARGET_PAGE_SIZE
)) {
10682 /* Region matched */
10684 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
10686 uint32_t srdis_mask
;
10688 rsize
-= 3; /* sub region size (power of 2) */
10689 snd
= ((address
- base
) >> rsize
) & 0x7;
10690 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
10692 srdis_mask
= srdis
? 0x3 : 0x0;
10693 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
10694 /* This will check in groups of 2, 4 and then 8, whether
10695 * the subregion bits are consistent. rsize is incremented
10696 * back up to give the region size, considering consistent
10697 * adjacent subregions as one region. Stop testing if rsize
10698 * is already big enough for an entire QEMU page.
10700 int snd_rounded
= snd
& ~(i
- 1);
10701 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
10702 snd_rounded
+ 8, i
);
10703 if (srdis_mask
^ srdis_multi
) {
10706 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
10713 if (rsize
< TARGET_PAGE_BITS
) {
10714 *page_size
= 1 << rsize
;
10719 if (n
== -1) { /* no hits */
10720 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10721 /* background fault */
10722 fi
->type
= ARMFault_Background
;
10725 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10726 } else { /* a MPU hit! */
10727 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
10728 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
10730 if (m_is_system_region(env
, address
)) {
10731 /* System space is always execute never */
10735 if (is_user
) { /* User mode AP bit decoding */
10740 break; /* no access */
10742 *prot
|= PAGE_WRITE
;
10746 *prot
|= PAGE_READ
| PAGE_EXEC
;
10749 /* for v7M, same as 6; for R profile a reserved value */
10750 if (arm_feature(env
, ARM_FEATURE_M
)) {
10751 *prot
|= PAGE_READ
| PAGE_EXEC
;
10756 qemu_log_mask(LOG_GUEST_ERROR
,
10757 "DRACR[%d]: Bad value for AP bits: 0x%"
10758 PRIx32
"\n", n
, ap
);
10760 } else { /* Priv. mode AP bits decoding */
10763 break; /* no access */
10767 *prot
|= PAGE_WRITE
;
10771 *prot
|= PAGE_READ
| PAGE_EXEC
;
10774 /* for v7M, same as 6; for R profile a reserved value */
10775 if (arm_feature(env
, ARM_FEATURE_M
)) {
10776 *prot
|= PAGE_READ
| PAGE_EXEC
;
10781 qemu_log_mask(LOG_GUEST_ERROR
,
10782 "DRACR[%d]: Bad value for AP bits: 0x%"
10783 PRIx32
"\n", n
, ap
);
10787 /* execute never */
10789 *prot
&= ~PAGE_EXEC
;
10794 fi
->type
= ARMFault_Permission
;
10796 return !(*prot
& (1 << access_type
));
10799 static bool v8m_is_sau_exempt(CPUARMState
*env
,
10800 uint32_t address
, MMUAccessType access_type
)
10802 /* The architecture specifies that certain address ranges are
10803 * exempt from v8M SAU/IDAU checks.
10806 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
10807 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
10808 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
10809 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
10810 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
10811 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
10814 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
10815 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10816 V8M_SAttributes
*sattrs
)
10818 /* Look up the security attributes for this address. Compare the
10819 * pseudocode SecurityCheck() function.
10820 * We assume the caller has zero-initialized *sattrs.
10822 ARMCPU
*cpu
= env_archcpu(env
);
10824 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
10825 int idau_region
= IREGION_NOTVALID
;
10826 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10827 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10830 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
10831 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
10833 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
10837 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
10838 /* 0xf0000000..0xffffffff is always S for insn fetches */
10842 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
10843 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
10847 if (idau_region
!= IREGION_NOTVALID
) {
10848 sattrs
->irvalid
= true;
10849 sattrs
->iregion
= idau_region
;
10852 switch (env
->sau
.ctrl
& 3) {
10853 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
10855 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
10858 default: /* SAU.ENABLE == 1 */
10859 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
10860 if (env
->sau
.rlar
[r
] & 1) {
10861 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
10862 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
10864 if (base
<= address
&& limit
>= address
) {
10865 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10866 sattrs
->subpage
= true;
10868 if (sattrs
->srvalid
) {
10869 /* If we hit in more than one region then we must report
10870 * as Secure, not NS-Callable, with no valid region
10873 sattrs
->ns
= false;
10874 sattrs
->nsc
= false;
10875 sattrs
->sregion
= 0;
10876 sattrs
->srvalid
= false;
10879 if (env
->sau
.rlar
[r
] & 2) {
10880 sattrs
->nsc
= true;
10884 sattrs
->srvalid
= true;
10885 sattrs
->sregion
= r
;
10889 * Address not in this region. We must check whether the
10890 * region covers addresses in the same page as our address.
10891 * In that case we must not report a size that covers the
10892 * whole page for a subsequent hit against a different MPU
10893 * region or the background region, because it would result
10894 * in incorrect TLB hits for subsequent accesses to
10895 * addresses that are in this MPU region.
10897 if (limit
>= base
&&
10898 ranges_overlap(base
, limit
- base
+ 1,
10900 TARGET_PAGE_SIZE
)) {
10901 sattrs
->subpage
= true;
10910 * The IDAU will override the SAU lookup results if it specifies
10911 * higher security than the SAU does.
10914 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
10915 sattrs
->ns
= false;
10916 sattrs
->nsc
= idau_nsc
;
10921 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
10922 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10923 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10924 int *prot
, bool *is_subpage
,
10925 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
10927 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
10928 * that a full phys-to-virt translation does).
10929 * mregion is (if not NULL) set to the region number which matched,
10930 * or -1 if no region number is returned (MPU off, address did not
10931 * hit a region, address hit in multiple regions).
10932 * We set is_subpage to true if the region hit doesn't cover the
10933 * entire TARGET_PAGE the address is within.
10935 ARMCPU
*cpu
= env_archcpu(env
);
10936 bool is_user
= regime_is_user(env
, mmu_idx
);
10937 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10939 int matchregion
= -1;
10941 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10942 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10944 *is_subpage
= false;
10945 *phys_ptr
= address
;
10951 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
10952 * was an exception vector read from the vector table (which is always
10953 * done using the default system address map), because those accesses
10954 * are done in arm_v7m_load_vector(), which always does a direct
10955 * read using address_space_ldl(), rather than going via this function.
10957 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
10959 } else if (m_is_ppb_region(env
, address
)) {
10962 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10966 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10967 /* region search */
10968 /* Note that the base address is bits [31:5] from the register
10969 * with bits [4:0] all zeroes, but the limit address is bits
10970 * [31:5] from the register with bits [4:0] all ones.
10972 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
10973 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
10975 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
10976 /* Region disabled */
10980 if (address
< base
|| address
> limit
) {
10982 * Address not in this region. We must check whether the
10983 * region covers addresses in the same page as our address.
10984 * In that case we must not report a size that covers the
10985 * whole page for a subsequent hit against a different MPU
10986 * region or the background region, because it would result in
10987 * incorrect TLB hits for subsequent accesses to addresses that
10988 * are in this MPU region.
10990 if (limit
>= base
&&
10991 ranges_overlap(base
, limit
- base
+ 1,
10993 TARGET_PAGE_SIZE
)) {
10994 *is_subpage
= true;
10999 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11000 *is_subpage
= true;
11003 if (matchregion
!= -1) {
11004 /* Multiple regions match -- always a failure (unlike
11005 * PMSAv7 where highest-numbered-region wins)
11007 fi
->type
= ARMFault_Permission
;
11018 /* background fault */
11019 fi
->type
= ARMFault_Background
;
11023 if (matchregion
== -1) {
11024 /* hit using the background region */
11025 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11027 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
11028 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
11030 if (m_is_system_region(env
, address
)) {
11031 /* System space is always execute never */
11035 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
11036 if (*prot
&& !xn
) {
11037 *prot
|= PAGE_EXEC
;
11039 /* We don't need to look the attribute up in the MAIR0/MAIR1
11040 * registers because that only tells us about cacheability.
11043 *mregion
= matchregion
;
11047 fi
->type
= ARMFault_Permission
;
11049 return !(*prot
& (1 << access_type
));
11053 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
11054 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11055 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11056 int *prot
, target_ulong
*page_size
,
11057 ARMMMUFaultInfo
*fi
)
11059 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11060 V8M_SAttributes sattrs
= {};
11062 bool mpu_is_subpage
;
11064 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11065 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
11066 if (access_type
== MMU_INST_FETCH
) {
11067 /* Instruction fetches always use the MMU bank and the
11068 * transaction attribute determined by the fetch address,
11069 * regardless of CPU state. This is painful for QEMU
11070 * to handle, because it would mean we need to encode
11071 * into the mmu_idx not just the (user, negpri) information
11072 * for the current security state but also that for the
11073 * other security state, which would balloon the number
11074 * of mmu_idx values needed alarmingly.
11075 * Fortunately we can avoid this because it's not actually
11076 * possible to arbitrarily execute code from memory with
11077 * the wrong security attribute: it will always generate
11078 * an exception of some kind or another, apart from the
11079 * special case of an NS CPU executing an SG instruction
11080 * in S&NSC memory. So we always just fail the translation
11081 * here and sort things out in the exception handler
11082 * (including possibly emulating an SG instruction).
11084 if (sattrs
.ns
!= !secure
) {
11086 fi
->type
= ARMFault_QEMU_NSCExec
;
11088 fi
->type
= ARMFault_QEMU_SFault
;
11090 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11091 *phys_ptr
= address
;
11096 /* For data accesses we always use the MMU bank indicated
11097 * by the current CPU state, but the security attributes
11098 * might downgrade a secure access to nonsecure.
11101 txattrs
->secure
= false;
11102 } else if (!secure
) {
11103 /* NS access to S memory must fault.
11104 * Architecturally we should first check whether the
11105 * MPU information for this address indicates that we
11106 * are doing an unaligned access to Device memory, which
11107 * should generate a UsageFault instead. QEMU does not
11108 * currently check for that kind of unaligned access though.
11109 * If we added it we would need to do so as a special case
11110 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11112 fi
->type
= ARMFault_QEMU_SFault
;
11113 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11114 *phys_ptr
= address
;
11121 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
11122 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
11123 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
11127 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
11128 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11129 hwaddr
*phys_ptr
, int *prot
,
11130 ARMMMUFaultInfo
*fi
)
11135 bool is_user
= regime_is_user(env
, mmu_idx
);
11137 if (regime_translation_disabled(env
, mmu_idx
)) {
11138 /* MPU disabled. */
11139 *phys_ptr
= address
;
11140 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11144 *phys_ptr
= address
;
11145 for (n
= 7; n
>= 0; n
--) {
11146 base
= env
->cp15
.c6_region
[n
];
11147 if ((base
& 1) == 0) {
11150 mask
= 1 << ((base
>> 1) & 0x1f);
11151 /* Keep this shift separate from the above to avoid an
11152 (undefined) << 32. */
11153 mask
= (mask
<< 1) - 1;
11154 if (((base
^ address
) & ~mask
) == 0) {
11159 fi
->type
= ARMFault_Background
;
11163 if (access_type
== MMU_INST_FETCH
) {
11164 mask
= env
->cp15
.pmsav5_insn_ap
;
11166 mask
= env
->cp15
.pmsav5_data_ap
;
11168 mask
= (mask
>> (n
* 4)) & 0xf;
11171 fi
->type
= ARMFault_Permission
;
11176 fi
->type
= ARMFault_Permission
;
11180 *prot
= PAGE_READ
| PAGE_WRITE
;
11185 *prot
|= PAGE_WRITE
;
11189 *prot
= PAGE_READ
| PAGE_WRITE
;
11193 fi
->type
= ARMFault_Permission
;
11203 /* Bad permission. */
11204 fi
->type
= ARMFault_Permission
;
11208 *prot
|= PAGE_EXEC
;
11212 /* Combine either inner or outer cacheability attributes for normal
11213 * memory, according to table D4-42 and pseudocode procedure
11214 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11216 * NB: only stage 1 includes allocation hints (RW bits), leading to
11219 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
11221 if (s1
== 4 || s2
== 4) {
11222 /* non-cacheable has precedence */
11224 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
11225 /* stage 1 write-through takes precedence */
11227 } else if (extract32(s2
, 2, 2) == 2) {
11228 /* stage 2 write-through takes precedence, but the allocation hint
11229 * is still taken from stage 1
11231 return (2 << 2) | extract32(s1
, 0, 2);
11232 } else { /* write-back */
11237 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11238 * and CombineS1S2Desc()
11240 * @s1: Attributes from stage 1 walk
11241 * @s2: Attributes from stage 2 walk
11243 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
11245 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
11246 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
11249 /* Combine shareability attributes (table D4-43) */
11250 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
11251 /* if either are outer-shareable, the result is outer-shareable */
11252 ret
.shareability
= 2;
11253 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
11254 /* if either are inner-shareable, the result is inner-shareable */
11255 ret
.shareability
= 3;
11257 /* both non-shareable */
11258 ret
.shareability
= 0;
11261 /* Combine memory type and cacheability attributes */
11262 if (s1hi
== 0 || s2hi
== 0) {
11263 /* Device has precedence over normal */
11264 if (s1lo
== 0 || s2lo
== 0) {
11265 /* nGnRnE has precedence over anything */
11267 } else if (s1lo
== 4 || s2lo
== 4) {
11268 /* non-Reordering has precedence over Reordering */
11269 ret
.attrs
= 4; /* nGnRE */
11270 } else if (s1lo
== 8 || s2lo
== 8) {
11271 /* non-Gathering has precedence over Gathering */
11272 ret
.attrs
= 8; /* nGRE */
11274 ret
.attrs
= 0xc; /* GRE */
11277 /* Any location for which the resultant memory type is any
11278 * type of Device memory is always treated as Outer Shareable.
11280 ret
.shareability
= 2;
11281 } else { /* Normal memory */
11282 /* Outer/inner cacheability combine independently */
11283 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
11284 | combine_cacheattr_nibble(s1lo
, s2lo
);
11286 if (ret
.attrs
== 0x44) {
11287 /* Any location for which the resultant memory type is Normal
11288 * Inner Non-cacheable, Outer Non-cacheable is always treated
11289 * as Outer Shareable.
11291 ret
.shareability
= 2;
11299 /* get_phys_addr - get the physical address for this virtual address
11301 * Find the physical address corresponding to the given virtual address,
11302 * by doing a translation table walk on MMU based systems or using the
11303 * MPU state on MPU based systems.
11305 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11306 * prot and page_size may not be filled in, and the populated fsr value provides
11307 * information on why the translation aborted, in the format of a
11308 * DFSR/IFSR fault register, with the following caveats:
11309 * * we honour the short vs long DFSR format differences.
11310 * * the WnR bit is never set (the caller must do this).
11311 * * for PSMAv5 based systems we don't bother to return a full FSR format
11314 * @env: CPUARMState
11315 * @address: virtual address to get physical address for
11316 * @access_type: 0 for read, 1 for write, 2 for execute
11317 * @mmu_idx: MMU index indicating required translation regime
11318 * @phys_ptr: set to the physical address corresponding to the virtual address
11319 * @attrs: set to the memory transaction attributes to use
11320 * @prot: set to the permissions for the page containing phys_ptr
11321 * @page_size: set to the size of the page containing phys_ptr
11322 * @fi: set to fault info if the translation fails
11323 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11325 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
11326 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11327 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
11328 target_ulong
*page_size
,
11329 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11331 if (mmu_idx
== ARMMMUIdx_E10_0
||
11332 mmu_idx
== ARMMMUIdx_E10_1
||
11333 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
11334 /* Call ourselves recursively to do the stage 1 and then stage 2
11337 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
11341 ARMCacheAttrs cacheattrs2
= {};
11343 ret
= get_phys_addr(env
, address
, access_type
,
11344 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
11345 prot
, page_size
, fi
, cacheattrs
);
11347 /* If S1 fails or S2 is disabled, return early. */
11348 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
11353 /* S1 is done. Now do S2 translation. */
11354 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_Stage2
,
11355 phys_ptr
, attrs
, &s2_prot
,
11357 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
11359 /* Combine the S1 and S2 perms. */
11362 /* Combine the S1 and S2 cache attributes, if needed */
11363 if (!ret
&& cacheattrs
!= NULL
) {
11364 if (env
->cp15
.hcr_el2
& HCR_DC
) {
11366 * HCR.DC forces the first stage attributes to
11367 * Normal Non-Shareable,
11368 * Inner Write-Back Read-Allocate Write-Allocate,
11369 * Outer Write-Back Read-Allocate Write-Allocate.
11371 cacheattrs
->attrs
= 0xff;
11372 cacheattrs
->shareability
= 0;
11374 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
11380 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
11382 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
11386 /* The page table entries may downgrade secure to non-secure, but
11387 * cannot upgrade an non-secure translation regime's attributes
11390 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
11391 attrs
->user
= regime_is_user(env
, mmu_idx
);
11393 /* Fast Context Switch Extension. This doesn't exist at all in v8.
11394 * In v7 and earlier it affects all stage 1 translations.
11396 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
11397 && !arm_feature(env
, ARM_FEATURE_V8
)) {
11398 if (regime_el(env
, mmu_idx
) == 3) {
11399 address
+= env
->cp15
.fcseidr_s
;
11401 address
+= env
->cp15
.fcseidr_ns
;
11405 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
11407 *page_size
= TARGET_PAGE_SIZE
;
11409 if (arm_feature(env
, ARM_FEATURE_V8
)) {
11411 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
11412 phys_ptr
, attrs
, prot
, page_size
, fi
);
11413 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
11415 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
11416 phys_ptr
, prot
, page_size
, fi
);
11419 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
11420 phys_ptr
, prot
, fi
);
11422 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
11423 " mmu_idx %u -> %s (prot %c%c%c)\n",
11424 access_type
== MMU_DATA_LOAD
? "reading" :
11425 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
11426 (uint32_t)address
, mmu_idx
,
11427 ret
? "Miss" : "Hit",
11428 *prot
& PAGE_READ
? 'r' : '-',
11429 *prot
& PAGE_WRITE
? 'w' : '-',
11430 *prot
& PAGE_EXEC
? 'x' : '-');
11435 /* Definitely a real MMU, not an MPU */
11437 if (regime_translation_disabled(env
, mmu_idx
)) {
11438 /* MMU disabled. */
11439 *phys_ptr
= address
;
11440 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11441 *page_size
= TARGET_PAGE_SIZE
;
11445 if (regime_using_lpae_format(env
, mmu_idx
)) {
11446 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
11447 phys_ptr
, attrs
, prot
, page_size
,
11449 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
11450 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
11451 phys_ptr
, attrs
, prot
, page_size
, fi
);
11453 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
11454 phys_ptr
, prot
, page_size
, fi
);
11458 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
11461 ARMCPU
*cpu
= ARM_CPU(cs
);
11462 CPUARMState
*env
= &cpu
->env
;
11464 target_ulong page_size
;
11467 ARMMMUFaultInfo fi
= {};
11468 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
11470 *attrs
= (MemTxAttrs
) {};
11472 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
11473 attrs
, &prot
, &page_size
, &fi
, NULL
);
11483 /* Note that signed overflow is undefined in C. The following routines are
11484 careful to use unsigned types where modulo arithmetic is required.
11485 Failure to do so _will_ break on newer gcc. */
11487 /* Signed saturating arithmetic. */
11489 /* Perform 16-bit signed saturating addition. */
11490 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11495 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11504 /* Perform 8-bit signed saturating addition. */
11505 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11510 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11519 /* Perform 16-bit signed saturating subtraction. */
11520 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11525 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11534 /* Perform 8-bit signed saturating subtraction. */
11535 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11540 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11549 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11550 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11551 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11552 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11555 #include "op_addsub.h"
11557 /* Unsigned saturating arithmetic. */
11558 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11567 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11575 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11584 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11592 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11593 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11594 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11595 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11598 #include "op_addsub.h"
11600 /* Signed modulo arithmetic. */
11601 #define SARITH16(a, b, n, op) do { \
11603 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11604 RESULT(sum, n, 16); \
11606 ge |= 3 << (n * 2); \
11609 #define SARITH8(a, b, n, op) do { \
11611 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11612 RESULT(sum, n, 8); \
11618 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11619 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11620 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11621 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11625 #include "op_addsub.h"
11627 /* Unsigned modulo arithmetic. */
11628 #define ADD16(a, b, n) do { \
11630 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11631 RESULT(sum, n, 16); \
11632 if ((sum >> 16) == 1) \
11633 ge |= 3 << (n * 2); \
11636 #define ADD8(a, b, n) do { \
11638 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11639 RESULT(sum, n, 8); \
11640 if ((sum >> 8) == 1) \
11644 #define SUB16(a, b, n) do { \
11646 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11647 RESULT(sum, n, 16); \
11648 if ((sum >> 16) == 0) \
11649 ge |= 3 << (n * 2); \
11652 #define SUB8(a, b, n) do { \
11654 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11655 RESULT(sum, n, 8); \
11656 if ((sum >> 8) == 0) \
11663 #include "op_addsub.h"
11665 /* Halved signed arithmetic. */
11666 #define ADD16(a, b, n) \
11667 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11668 #define SUB16(a, b, n) \
11669 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11670 #define ADD8(a, b, n) \
11671 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11672 #define SUB8(a, b, n) \
11673 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11676 #include "op_addsub.h"
11678 /* Halved unsigned arithmetic. */
11679 #define ADD16(a, b, n) \
11680 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11681 #define SUB16(a, b, n) \
11682 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11683 #define ADD8(a, b, n) \
11684 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11685 #define SUB8(a, b, n) \
11686 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11689 #include "op_addsub.h"
11691 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11699 /* Unsigned sum of absolute byte differences. */
11700 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11703 sum
= do_usad(a
, b
);
11704 sum
+= do_usad(a
>> 8, b
>> 8);
11705 sum
+= do_usad(a
>> 16, b
>>16);
11706 sum
+= do_usad(a
>> 24, b
>> 24);
11710 /* For ARMv6 SEL instruction. */
11711 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11723 mask
|= 0xff000000;
11724 return (a
& mask
) | (b
& ~mask
);
11728 * The upper bytes of val (above the number specified by 'bytes') must have
11729 * been zeroed out by the caller.
11731 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11735 stl_le_p(buf
, val
);
11737 /* zlib crc32 converts the accumulator and output to one's complement. */
11738 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11741 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11745 stl_le_p(buf
, val
);
11747 /* Linux crc32c converts the output to one's complement. */
11748 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11751 /* Return the exception level to which FP-disabled exceptions should
11752 * be taken, or 0 if FP is enabled.
11754 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11756 #ifndef CONFIG_USER_ONLY
11757 /* CPACR and the CPTR registers don't exist before v6, so FP is
11758 * always accessible
11760 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11764 if (arm_feature(env
, ARM_FEATURE_M
)) {
11765 /* CPACR can cause a NOCP UsageFault taken to current security state */
11766 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11770 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11771 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11772 /* FP insns cause a NOCP UsageFault taken to Secure */
11780 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11781 * 0, 2 : trap EL0 and EL1/PL1 accesses
11782 * 1 : trap only EL0 accesses
11783 * 3 : trap no accesses
11784 * This register is ignored if E2H+TGE are both set.
11786 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11787 int fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
11792 if (cur_el
== 0 || cur_el
== 1) {
11793 /* Trap to PL1, which might be EL1 or EL3 */
11794 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
11799 if (cur_el
== 3 && !is_a64(env
)) {
11800 /* Secure PL1 running at EL3 */
11815 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11816 * to control non-secure access to the FPU. It doesn't have any
11817 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11819 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11820 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11821 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11822 /* FP insns act as UNDEF */
11823 return cur_el
== 2 ? 2 : 1;
11827 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
11828 * check because zero bits in the registers mean "don't trap".
11831 /* CPTR_EL2 : present in v7VE or v8 */
11832 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
11833 && !arm_is_secure_below_el3(env
)) {
11834 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
11838 /* CPTR_EL3 : present in v8 */
11839 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
11840 /* Trap all FP ops to EL3 */
11847 /* Return the exception level we're running at if this is our mmu_idx */
11848 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
11850 if (mmu_idx
& ARM_MMU_IDX_M
) {
11851 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
11855 case ARMMMUIdx_E10_0
:
11856 case ARMMMUIdx_E20_0
:
11857 case ARMMMUIdx_SE10_0
:
11859 case ARMMMUIdx_E10_1
:
11860 case ARMMMUIdx_E10_1_PAN
:
11861 case ARMMMUIdx_SE10_1
:
11862 case ARMMMUIdx_SE10_1_PAN
:
11865 case ARMMMUIdx_E20_2
:
11866 case ARMMMUIdx_E20_2_PAN
:
11868 case ARMMMUIdx_SE3
:
11871 g_assert_not_reached();
11876 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11878 g_assert_not_reached();
11882 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11884 if (arm_feature(env
, ARM_FEATURE_M
)) {
11885 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11888 /* See ARM pseudo-function ELIsInHost. */
11891 if (arm_is_secure_below_el3(env
)) {
11892 return ARMMMUIdx_SE10_0
;
11894 if ((env
->cp15
.hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)
11895 && arm_el_is_aa64(env
, 2)) {
11896 return ARMMMUIdx_E20_0
;
11898 return ARMMMUIdx_E10_0
;
11900 if (arm_is_secure_below_el3(env
)) {
11901 if (env
->pstate
& PSTATE_PAN
) {
11902 return ARMMMUIdx_SE10_1_PAN
;
11904 return ARMMMUIdx_SE10_1
;
11906 if (env
->pstate
& PSTATE_PAN
) {
11907 return ARMMMUIdx_E10_1_PAN
;
11909 return ARMMMUIdx_E10_1
;
11911 /* TODO: ARMv8.4-SecEL2 */
11912 /* Note that TGE does not apply at EL2. */
11913 if ((env
->cp15
.hcr_el2
& HCR_E2H
) && arm_el_is_aa64(env
, 2)) {
11914 if (env
->pstate
& PSTATE_PAN
) {
11915 return ARMMMUIdx_E20_2_PAN
;
11917 return ARMMMUIdx_E20_2
;
11919 return ARMMMUIdx_E2
;
11921 return ARMMMUIdx_SE3
;
11923 g_assert_not_reached();
11927 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11929 return arm_mmu_idx_el(env
, arm_current_el(env
));
11932 int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
11934 return arm_to_core_mmu_idx(arm_mmu_idx(env
));
11937 #ifndef CONFIG_USER_ONLY
11938 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
11940 return stage_1_mmu_idx(arm_mmu_idx(env
));
11944 static uint32_t rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11945 ARMMMUIdx mmu_idx
, uint32_t flags
)
11947 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
11948 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
,
11949 arm_to_core_mmu_idx(mmu_idx
));
11951 if (arm_singlestep_active(env
)) {
11952 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
11957 static uint32_t rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11958 ARMMMUIdx mmu_idx
, uint32_t flags
)
11960 bool sctlr_b
= arm_sctlr_b(env
);
11963 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, 1);
11965 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11966 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
11968 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
11970 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11973 static uint32_t rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11976 uint32_t flags
= 0;
11978 if (arm_v7m_is_handler_mode(env
)) {
11979 flags
= FIELD_DP32(flags
, TBFLAG_M32
, HANDLER
, 1);
11983 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11984 * is suppressing them because the requested execution priority
11987 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11988 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11989 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11990 flags
= FIELD_DP32(flags
, TBFLAG_M32
, STACKCHECK
, 1);
11993 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11996 static uint32_t rebuild_hflags_aprofile(CPUARMState
*env
)
12000 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
,
12001 arm_debug_target_el(env
));
12005 static uint32_t rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
12008 uint32_t flags
= rebuild_hflags_aprofile(env
);
12010 if (arm_el_is_aa64(env
, 1)) {
12011 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12014 if (arm_current_el(env
) < 2 && env
->cp15
.hstr_el2
&&
12015 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12016 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HSTR_ACTIVE
, 1);
12019 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12022 static uint32_t rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
12025 uint32_t flags
= rebuild_hflags_aprofile(env
);
12026 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
12027 ARMVAParameters p0
= aa64_va_parameters_both(env
, 0, stage1
);
12031 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
12033 /* Get control bits for tagged addresses. */
12034 if (regime_has_2_ranges(mmu_idx
)) {
12035 ARMVAParameters p1
= aa64_va_parameters_both(env
, -1, stage1
);
12036 tbid
= (p1
.tbi
<< 1) | p0
.tbi
;
12037 tbii
= tbid
& ~((p1
.tbid
<< 1) | p0
.tbid
);
12040 tbii
= tbid
& !p0
.tbid
;
12043 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
12044 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
12046 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
12047 int sve_el
= sve_exception_el(env
, el
);
12051 * If SVE is disabled, but FP is enabled,
12052 * then the effective len is 0.
12054 if (sve_el
!= 0 && fp_el
== 0) {
12057 zcr_len
= sve_zcr_len_for_el(env
, el
);
12059 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
12060 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
12063 sctlr
= regime_sctlr(env
, stage1
);
12065 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
12066 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
12069 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
12071 * In order to save space in flags, we record only whether
12072 * pauth is "inactive", meaning all insns are implemented as
12073 * a nop, or "active" when some action must be performed.
12074 * The decision of which action to take is left to a helper.
12076 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
12077 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
12081 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12082 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12083 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
12084 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
12088 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12089 /* TODO: ARMv8.2-UAO */
12091 case ARMMMUIdx_E10_1
:
12092 case ARMMMUIdx_E10_1_PAN
:
12093 case ARMMMUIdx_SE10_1
:
12094 case ARMMMUIdx_SE10_1_PAN
:
12095 /* TODO: ARMv8.3-NV */
12096 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
12098 case ARMMMUIdx_E20_2
:
12099 case ARMMMUIdx_E20_2_PAN
:
12100 /* TODO: ARMv8.4-SecEL2 */
12102 * Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is
12103 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12105 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
12106 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
12113 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12116 static uint32_t rebuild_hflags_internal(CPUARMState
*env
)
12118 int el
= arm_current_el(env
);
12119 int fp_el
= fp_exception_el(env
, el
);
12120 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12123 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12124 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
12125 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12127 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12131 void arm_rebuild_hflags(CPUARMState
*env
)
12133 env
->hflags
= rebuild_hflags_internal(env
);
12136 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
12138 int fp_el
= fp_exception_el(env
, el
);
12139 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12141 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
12145 * If we have triggered a EL state change we can't rely on the
12146 * translator having passed it too us, we need to recompute.
12148 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
12150 int el
= arm_current_el(env
);
12151 int fp_el
= fp_exception_el(env
, el
);
12152 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12153 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12156 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
12158 int fp_el
= fp_exception_el(env
, el
);
12159 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12161 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
12164 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
12166 int fp_el
= fp_exception_el(env
, el
);
12167 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
12169 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
12172 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
12174 #ifdef CONFIG_DEBUG_TCG
12175 uint32_t env_flags_current
= env
->hflags
;
12176 uint32_t env_flags_rebuilt
= rebuild_hflags_internal(env
);
12178 if (unlikely(env_flags_current
!= env_flags_rebuilt
)) {
12179 fprintf(stderr
, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
12180 env_flags_current
, env_flags_rebuilt
);
12186 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12187 target_ulong
*cs_base
, uint32_t *pflags
)
12189 uint32_t flags
= env
->hflags
;
12190 uint32_t pstate_for_ss
;
12193 assert_hflags_rebuild_correctly(env
);
12195 if (FIELD_EX32(flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
12197 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12198 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
12200 pstate_for_ss
= env
->pstate
;
12202 *pc
= env
->regs
[15];
12204 if (arm_feature(env
, ARM_FEATURE_M
)) {
12205 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12206 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12207 != env
->v7m
.secure
) {
12208 flags
= FIELD_DP32(flags
, TBFLAG_M32
, FPCCR_S_WRONG
, 1);
12211 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12212 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12213 (env
->v7m
.secure
&&
12214 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12216 * ASPEN is set, but FPCA/SFPA indicate that there is no
12217 * active FP context; we must create a new FP context before
12218 * executing any FP insn.
12220 flags
= FIELD_DP32(flags
, TBFLAG_M32
, NEW_FP_CTXT_NEEDED
, 1);
12223 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12224 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12225 flags
= FIELD_DP32(flags
, TBFLAG_M32
, LSPACT
, 1);
12229 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12230 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12232 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12233 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
12234 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12236 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
,
12238 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
,
12239 env
->vfp
.vec_stride
);
12241 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12242 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12246 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, THUMB
, env
->thumb
);
12247 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, CONDEXEC
, env
->condexec_bits
);
12248 pstate_for_ss
= env
->uncached_cpsr
;
12252 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12253 * states defined in the ARM ARM for software singlestep:
12254 * SS_ACTIVE PSTATE.SS State
12255 * 0 x Inactive (the TB flag for SS is always 0)
12256 * 1 0 Active-pending
12257 * 1 1 Active-not-pending
12258 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
12260 if (FIELD_EX32(flags
, TBFLAG_ANY
, SS_ACTIVE
) &&
12261 (pstate_for_ss
& PSTATE_SS
)) {
12262 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
12268 #ifdef TARGET_AARCH64
12270 * The manual says that when SVE is enabled and VQ is widened the
12271 * implementation is allowed to zero the previously inaccessible
12272 * portion of the registers. The corollary to that is that when
12273 * SVE is enabled and VQ is narrowed we are also allowed to zero
12274 * the now inaccessible portion of the registers.
12276 * The intent of this is that no predicate bit beyond VQ is ever set.
12277 * Which means that some operations on predicate registers themselves
12278 * may operate on full uint64_t or even unrolled across the maximum
12279 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12280 * may well be cheaper than conditionals to restrict the operation
12281 * to the relevant portion of a uint16_t[16].
12283 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12288 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12289 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12291 /* Zap the high bits of the zregs. */
12292 for (i
= 0; i
< 32; i
++) {
12293 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12296 /* Zap the high bits of the pregs and ffr. */
12299 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12301 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12302 for (i
= 0; i
< 17; ++i
) {
12303 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12310 * Notice a change in SVE vector size when changing EL.
12312 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12313 int new_el
, bool el0_a64
)
12315 ARMCPU
*cpu
= env_archcpu(env
);
12316 int old_len
, new_len
;
12317 bool old_a64
, new_a64
;
12319 /* Nothing to do if no SVE. */
12320 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12324 /* Nothing to do if FP is disabled in either EL. */
12325 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12330 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12331 * at ELx, or not available because the EL is in AArch32 state, then
12332 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12333 * has an effective value of 0".
12335 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12336 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12337 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12338 * we already have the correct register contents when encountering the
12339 * vq0->vq0 transition between EL0->EL1.
12341 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12342 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
12343 ? sve_zcr_len_for_el(env
, old_el
) : 0);
12344 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12345 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
12346 ? sve_zcr_len_for_el(env
, new_el
) : 0);
12348 /* When changing vector length, clear inaccessible state. */
12349 if (new_len
< old_len
) {
12350 aarch64_sve_narrow_vq(env
, new_len
+ 1);