1 #include "qemu/osdep.h"
5 #include "exec/gdbstub.h"
6 #include "exec/helper-proto.h"
7 #include "qemu/host-utils.h"
8 #include "sysemu/arch_init.h"
9 #include "sysemu/sysemu.h"
10 #include "qemu/bitops.h"
11 #include "qemu/crc32c.h"
12 #include "exec/exec-all.h"
13 #include "exec/cpu_ldst.h"
15 #include <zlib.h> /* For crc32 */
16 #include "exec/semihost.h"
17 #include "sysemu/kvm.h"
18 #include "fpu/softfloat.h"
20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
22 #ifndef CONFIG_USER_ONLY
23 /* Cacheability and shareability attributes for a memory access */
24 typedef struct ARMCacheAttrs
{
25 unsigned int attrs
:8; /* as in the MAIR register encoding */
26 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
29 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
30 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
31 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
32 target_ulong
*page_size
,
33 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
35 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
36 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
37 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
38 target_ulong
*page_size_ptr
,
39 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
41 /* Security attributes for an address, as returned by v8m_security_lookup. */
42 typedef struct V8M_SAttributes
{
51 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
52 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
53 V8M_SAttributes
*sattrs
);
55 /* Definitions for the PMCCNTR and PMCR registers */
61 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
65 /* VFP data registers are always little-endian. */
66 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
68 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
71 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
72 /* Aliases for Q regs. */
75 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
77 stq_le_p(buf
+ 8, q
[1]);
81 switch (reg
- nregs
) {
82 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
83 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
84 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
89 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
93 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
95 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
98 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
101 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
102 q
[0] = ldq_le_p(buf
);
103 q
[1] = ldq_le_p(buf
+ 8);
107 switch (reg
- nregs
) {
108 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
109 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
110 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
115 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
119 /* 128 bit FP register */
121 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
123 stq_le_p(buf
+ 8, q
[1]);
128 stl_p(buf
, vfp_get_fpsr(env
));
132 stl_p(buf
, vfp_get_fpcr(env
));
139 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
143 /* 128 bit FP register */
145 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
146 q
[0] = ldq_le_p(buf
);
147 q
[1] = ldq_le_p(buf
+ 8);
152 vfp_set_fpsr(env
, ldl_p(buf
));
156 vfp_set_fpcr(env
, ldl_p(buf
));
163 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
165 assert(ri
->fieldoffset
);
166 if (cpreg_field_is_64bit(ri
)) {
167 return CPREG_FIELD64(env
, ri
);
169 return CPREG_FIELD32(env
, ri
);
173 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
176 assert(ri
->fieldoffset
);
177 if (cpreg_field_is_64bit(ri
)) {
178 CPREG_FIELD64(env
, ri
) = value
;
180 CPREG_FIELD32(env
, ri
) = value
;
184 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
186 return (char *)env
+ ri
->fieldoffset
;
189 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
191 /* Raw read of a coprocessor register (as needed for migration, etc). */
192 if (ri
->type
& ARM_CP_CONST
) {
193 return ri
->resetvalue
;
194 } else if (ri
->raw_readfn
) {
195 return ri
->raw_readfn(env
, ri
);
196 } else if (ri
->readfn
) {
197 return ri
->readfn(env
, ri
);
199 return raw_read(env
, ri
);
203 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
206 /* Raw write of a coprocessor register (as needed for migration, etc).
207 * Note that constant registers are treated as write-ignored; the
208 * caller should check for success by whether a readback gives the
211 if (ri
->type
& ARM_CP_CONST
) {
213 } else if (ri
->raw_writefn
) {
214 ri
->raw_writefn(env
, ri
, v
);
215 } else if (ri
->writefn
) {
216 ri
->writefn(env
, ri
, v
);
218 raw_write(env
, ri
, v
);
222 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
224 /* Return true if the regdef would cause an assertion if you called
225 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
226 * program bug for it not to have the NO_RAW flag).
227 * NB that returning false here doesn't necessarily mean that calling
228 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
229 * read/write access functions which are safe for raw use" from "has
230 * read/write access functions which have side effects but has forgotten
231 * to provide raw access functions".
232 * The tests here line up with the conditions in read/write_raw_cp_reg()
233 * and assertions in raw_read()/raw_write().
235 if ((ri
->type
& ARM_CP_CONST
) ||
237 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
243 bool write_cpustate_to_list(ARMCPU
*cpu
)
245 /* Write the coprocessor state from cpu->env to the (index,value) list. */
249 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
250 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
251 const ARMCPRegInfo
*ri
;
253 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
258 if (ri
->type
& ARM_CP_NO_RAW
) {
261 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
266 bool write_list_to_cpustate(ARMCPU
*cpu
)
271 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
272 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
273 uint64_t v
= cpu
->cpreg_values
[i
];
274 const ARMCPRegInfo
*ri
;
276 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
281 if (ri
->type
& ARM_CP_NO_RAW
) {
284 /* Write value and confirm it reads back as written
285 * (to catch read-only registers and partially read-only
286 * registers where the incoming migration value doesn't match)
288 write_raw_cp_reg(&cpu
->env
, ri
, v
);
289 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
296 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
298 ARMCPU
*cpu
= opaque
;
300 const ARMCPRegInfo
*ri
;
302 regidx
= *(uint32_t *)key
;
303 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
305 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
306 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
307 /* The value array need not be initialized at this point */
308 cpu
->cpreg_array_len
++;
312 static void count_cpreg(gpointer key
, gpointer opaque
)
314 ARMCPU
*cpu
= opaque
;
316 const ARMCPRegInfo
*ri
;
318 regidx
= *(uint32_t *)key
;
319 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
321 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
322 cpu
->cpreg_array_len
++;
326 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
328 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
329 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
340 void init_cpreg_list(ARMCPU
*cpu
)
342 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
343 * Note that we require cpreg_tuples[] to be sorted by key ID.
348 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
349 keys
= g_list_sort(keys
, cpreg_key_compare
);
351 cpu
->cpreg_array_len
= 0;
353 g_list_foreach(keys
, count_cpreg
, cpu
);
355 arraylen
= cpu
->cpreg_array_len
;
356 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
357 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
358 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
359 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
360 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
361 cpu
->cpreg_array_len
= 0;
363 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
365 assert(cpu
->cpreg_array_len
== arraylen
);
371 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
372 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
374 * access_el3_aa32ns: Used to check AArch32 register views.
375 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
377 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
378 const ARMCPRegInfo
*ri
,
381 bool secure
= arm_is_secure_below_el3(env
);
383 assert(!arm_el_is_aa64(env
, 3));
385 return CP_ACCESS_TRAP_UNCATEGORIZED
;
390 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
391 const ARMCPRegInfo
*ri
,
394 if (!arm_el_is_aa64(env
, 3)) {
395 return access_el3_aa32ns(env
, ri
, isread
);
400 /* Some secure-only AArch32 registers trap to EL3 if used from
401 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
402 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
403 * We assume that the .access field is set to PL1_RW.
405 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
406 const ARMCPRegInfo
*ri
,
409 if (arm_current_el(env
) == 3) {
412 if (arm_is_secure_below_el3(env
)) {
413 return CP_ACCESS_TRAP_EL3
;
415 /* This will be EL1 NS and EL2 NS, which just UNDEF */
416 return CP_ACCESS_TRAP_UNCATEGORIZED
;
419 /* Check for traps to "powerdown debug" registers, which are controlled
422 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
425 int el
= arm_current_el(env
);
427 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDOSA
)
428 && !arm_is_secure_below_el3(env
)) {
429 return CP_ACCESS_TRAP_EL2
;
431 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
432 return CP_ACCESS_TRAP_EL3
;
437 /* Check for traps to "debug ROM" registers, which are controlled
438 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
440 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
443 int el
= arm_current_el(env
);
445 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDRA
)
446 && !arm_is_secure_below_el3(env
)) {
447 return CP_ACCESS_TRAP_EL2
;
449 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
450 return CP_ACCESS_TRAP_EL3
;
455 /* Check for traps to general debug registers, which are controlled
456 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
458 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
461 int el
= arm_current_el(env
);
463 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDA
)
464 && !arm_is_secure_below_el3(env
)) {
465 return CP_ACCESS_TRAP_EL2
;
467 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
468 return CP_ACCESS_TRAP_EL3
;
473 /* Check for traps to performance monitor registers, which are controlled
474 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
476 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
479 int el
= arm_current_el(env
);
481 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
482 && !arm_is_secure_below_el3(env
)) {
483 return CP_ACCESS_TRAP_EL2
;
485 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
486 return CP_ACCESS_TRAP_EL3
;
491 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
493 ARMCPU
*cpu
= arm_env_get_cpu(env
);
495 raw_write(env
, ri
, value
);
496 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
499 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
501 ARMCPU
*cpu
= arm_env_get_cpu(env
);
503 if (raw_read(env
, ri
) != value
) {
504 /* Unlike real hardware the qemu TLB uses virtual addresses,
505 * not modified virtual addresses, so this causes a TLB flush.
508 raw_write(env
, ri
, value
);
512 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 ARMCPU
*cpu
= arm_env_get_cpu(env
);
517 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
518 && !extended_addresses_enabled(env
)) {
519 /* For VMSA (when not using the LPAE long descriptor page table
520 * format) this register includes the ASID, so do a TLB flush.
521 * For PMSA it is purely a process ID and no action is needed.
525 raw_write(env
, ri
, value
);
528 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
531 /* Invalidate all (TLBIALL) */
532 ARMCPU
*cpu
= arm_env_get_cpu(env
);
537 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
540 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
541 ARMCPU
*cpu
= arm_env_get_cpu(env
);
543 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
546 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
549 /* Invalidate by ASID (TLBIASID) */
550 ARMCPU
*cpu
= arm_env_get_cpu(env
);
555 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
558 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
559 ARMCPU
*cpu
= arm_env_get_cpu(env
);
561 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
564 /* IS variants of TLB operations must affect all cores */
565 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= ENV_GET_CPU(env
);
570 tlb_flush_all_cpus_synced(cs
);
573 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 CPUState
*cs
= ENV_GET_CPU(env
);
578 tlb_flush_all_cpus_synced(cs
);
581 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
584 CPUState
*cs
= ENV_GET_CPU(env
);
586 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
589 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
592 CPUState
*cs
= ENV_GET_CPU(env
);
594 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
597 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
600 CPUState
*cs
= ENV_GET_CPU(env
);
602 tlb_flush_by_mmuidx(cs
,
603 ARMMMUIdxBit_S12NSE1
|
604 ARMMMUIdxBit_S12NSE0
|
608 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
611 CPUState
*cs
= ENV_GET_CPU(env
);
613 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
614 ARMMMUIdxBit_S12NSE1
|
615 ARMMMUIdxBit_S12NSE0
|
619 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
622 /* Invalidate by IPA. This has to invalidate any structures that
623 * contain only stage 2 translation information, but does not need
624 * to apply to structures that contain combined stage 1 and stage 2
625 * translation information.
626 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
628 CPUState
*cs
= ENV_GET_CPU(env
);
631 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
635 pageaddr
= sextract64(value
<< 12, 0, 40);
637 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
640 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
643 CPUState
*cs
= ENV_GET_CPU(env
);
646 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
650 pageaddr
= sextract64(value
<< 12, 0, 40);
652 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
656 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
659 CPUState
*cs
= ENV_GET_CPU(env
);
661 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
664 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
667 CPUState
*cs
= ENV_GET_CPU(env
);
669 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
672 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
675 CPUState
*cs
= ENV_GET_CPU(env
);
676 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
678 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
681 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
684 CPUState
*cs
= ENV_GET_CPU(env
);
685 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
687 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
691 static const ARMCPRegInfo cp_reginfo
[] = {
692 /* Define the secure and non-secure FCSE identifier CP registers
693 * separately because there is no secure bank in V8 (no _EL3). This allows
694 * the secure register to be properly reset and migrated. There is also no
695 * v8 EL1 version of the register so the non-secure instance stands alone.
697 { .name
= "FCSEIDR(NS)",
698 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
699 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
700 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
701 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
702 { .name
= "FCSEIDR(S)",
703 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
704 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
705 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
706 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
707 /* Define the secure and non-secure context identifier CP registers
708 * separately because there is no secure bank in V8 (no _EL3). This allows
709 * the secure register to be properly reset and migrated. In the
710 * non-secure case, the 32-bit register will have reset and migration
711 * disabled during registration as it is handled by the 64-bit instance.
713 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
714 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
715 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
716 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
717 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
718 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
719 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
720 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
721 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
722 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
726 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
727 /* NB: Some of these registers exist in v8 but with more precise
728 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
730 /* MMU Domain access control / MPU write buffer control */
732 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
733 .access
= PL1_RW
, .resetvalue
= 0,
734 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
735 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
736 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
737 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
738 * For v6 and v5, these mappings are overly broad.
740 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
741 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
742 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
743 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
744 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
745 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
746 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
747 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
748 /* Cache maintenance ops; some of this space may be overridden later. */
749 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
750 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
751 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
755 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
756 /* Not all pre-v6 cores implemented this WFI, so this is slightly
759 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
760 .access
= PL1_W
, .type
= ARM_CP_WFI
},
764 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
765 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
766 * is UNPREDICTABLE; we choose to NOP as most implementations do).
768 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
769 .access
= PL1_W
, .type
= ARM_CP_WFI
},
770 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
771 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
772 * OMAPCP will override this space.
774 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
775 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
777 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
778 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
780 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
781 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
782 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
784 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
785 * implementing it as RAZ means the "debug architecture version" bits
786 * will read as a reserved value, which should cause Linux to not try
787 * to use the debug hardware.
789 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
790 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
791 /* MMU TLB control. Note that the wildcarding means we cover not just
792 * the unified TLB ops but also the dside/iside/inner-shareable variants.
794 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
795 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
796 .type
= ARM_CP_NO_RAW
},
797 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
798 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
799 .type
= ARM_CP_NO_RAW
},
800 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
801 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
802 .type
= ARM_CP_NO_RAW
},
803 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
804 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
805 .type
= ARM_CP_NO_RAW
},
806 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
807 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
808 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
809 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
813 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
818 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
819 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
820 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
821 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
822 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
824 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
825 /* VFP coprocessor: cp10 & cp11 [23:20] */
826 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
828 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
829 /* ASEDIS [31] bit is RAO/WI */
833 /* VFPv3 and upwards with NEON implement 32 double precision
834 * registers (D0-D31).
836 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
837 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
838 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
844 env
->cp15
.cpacr_el1
= value
;
847 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
850 if (arm_feature(env
, ARM_FEATURE_V8
)) {
851 /* Check if CPACR accesses are to be trapped to EL2 */
852 if (arm_current_el(env
) == 1 &&
853 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
854 return CP_ACCESS_TRAP_EL2
;
855 /* Check if CPACR accesses are to be trapped to EL3 */
856 } else if (arm_current_el(env
) < 3 &&
857 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
858 return CP_ACCESS_TRAP_EL3
;
865 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
868 /* Check if CPTR accesses are set to trap to EL3 */
869 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
870 return CP_ACCESS_TRAP_EL3
;
876 static const ARMCPRegInfo v6_cp_reginfo
[] = {
877 /* prefetch by MVA in v6, NOP in v7 */
878 { .name
= "MVA_prefetch",
879 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
880 .access
= PL1_W
, .type
= ARM_CP_NOP
},
881 /* We need to break the TB after ISB to execute self-modifying code
882 * correctly and also to take any pending interrupts immediately.
883 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
885 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
886 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
887 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
888 .access
= PL0_W
, .type
= ARM_CP_NOP
},
889 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
890 .access
= PL0_W
, .type
= ARM_CP_NOP
},
891 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
893 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
894 offsetof(CPUARMState
, cp15
.ifar_ns
) },
896 /* Watchpoint Fault Address Register : should actually only be present
897 * for 1136, 1176, 11MPCore.
899 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
900 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
901 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
902 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
903 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
904 .resetvalue
= 0, .writefn
= cpacr_write
},
908 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
911 /* Performance monitor registers user accessibility is controlled
912 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
913 * trapping to EL2 or EL3 for other accesses.
915 int el
= arm_current_el(env
);
917 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
918 return CP_ACCESS_TRAP
;
920 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
921 && !arm_is_secure_below_el3(env
)) {
922 return CP_ACCESS_TRAP_EL2
;
924 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
925 return CP_ACCESS_TRAP_EL3
;
931 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
932 const ARMCPRegInfo
*ri
,
935 /* ER: event counter read trap control */
936 if (arm_feature(env
, ARM_FEATURE_V8
)
937 && arm_current_el(env
) == 0
938 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
943 return pmreg_access(env
, ri
, isread
);
946 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
947 const ARMCPRegInfo
*ri
,
950 /* SW: software increment write trap control */
951 if (arm_feature(env
, ARM_FEATURE_V8
)
952 && arm_current_el(env
) == 0
953 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
958 return pmreg_access(env
, ri
, isread
);
961 #ifndef CONFIG_USER_ONLY
963 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
964 const ARMCPRegInfo
*ri
,
967 /* ER: event counter read trap control */
968 if (arm_feature(env
, ARM_FEATURE_V8
)
969 && arm_current_el(env
) == 0
970 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
974 return pmreg_access(env
, ri
, isread
);
977 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
978 const ARMCPRegInfo
*ri
,
981 /* CR: cycle counter read trap control */
982 if (arm_feature(env
, ARM_FEATURE_V8
)
983 && arm_current_el(env
) == 0
984 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
989 return pmreg_access(env
, ri
, isread
);
992 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
994 /* This does not support checking PMCCFILTR_EL0 register */
996 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
1003 void pmccntr_sync(CPUARMState
*env
)
1005 uint64_t temp_ticks
;
1007 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1008 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1010 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1011 /* Increment once every 64 processor clock cycles */
1015 if (arm_ccnt_enabled(env
)) {
1016 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
1020 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1025 if (value
& PMCRC
) {
1026 /* The counter has been reset */
1027 env
->cp15
.c15_ccnt
= 0;
1030 /* only the DP, X, D and E bits are writable */
1031 env
->cp15
.c9_pmcr
&= ~0x39;
1032 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1037 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1039 uint64_t total_ticks
;
1041 if (!arm_ccnt_enabled(env
)) {
1042 /* Counter is disabled, do not change value */
1043 return env
->cp15
.c15_ccnt
;
1046 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1047 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1049 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1050 /* Increment once every 64 processor clock cycles */
1053 return total_ticks
- env
->cp15
.c15_ccnt
;
1056 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1059 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1060 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1061 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1064 env
->cp15
.c9_pmselr
= value
& 0x1f;
1067 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1070 uint64_t total_ticks
;
1072 if (!arm_ccnt_enabled(env
)) {
1073 /* Counter is disabled, set the absolute value */
1074 env
->cp15
.c15_ccnt
= value
;
1078 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1079 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1081 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1082 /* Increment once every 64 processor clock cycles */
1085 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1088 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1091 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1093 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1096 #else /* CONFIG_USER_ONLY */
1098 void pmccntr_sync(CPUARMState
*env
)
1104 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1108 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
1112 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1116 env
->cp15
.c9_pmcnten
|= value
;
1119 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1123 env
->cp15
.c9_pmcnten
&= ~value
;
1126 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1129 env
->cp15
.c9_pmovsr
&= ~value
;
1132 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1135 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1136 * PMSELR value is equal to or greater than the number of implemented
1137 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1139 if (env
->cp15
.c9_pmselr
== 0x1f) {
1140 pmccfiltr_write(env
, ri
, value
);
1144 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1146 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1147 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1149 if (env
->cp15
.c9_pmselr
== 0x1f) {
1150 return env
->cp15
.pmccfiltr_el0
;
1156 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1159 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1160 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1162 env
->cp15
.c9_pmuserenr
= value
& 1;
1166 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1169 /* We have no event counters so only the C bit can be changed */
1171 env
->cp15
.c9_pminten
|= value
;
1174 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1178 env
->cp15
.c9_pminten
&= ~value
;
1181 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1184 /* Note that even though the AArch64 view of this register has bits
1185 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1186 * architectural requirements for bits which are RES0 only in some
1187 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1188 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1190 raw_write(env
, ri
, value
& ~0x1FULL
);
1193 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1195 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1196 * For bits that vary between AArch32/64, code needs to check the
1197 * current execution mode before directly using the feature bit.
1199 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1201 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1202 valid_mask
&= ~SCR_HCE
;
1204 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1205 * supported if EL2 exists. The bit is UNK/SBZP when
1206 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1207 * when EL2 is unavailable.
1208 * On ARMv8, this bit is always available.
1210 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1211 !arm_feature(env
, ARM_FEATURE_V8
)) {
1212 valid_mask
&= ~SCR_SMD
;
1216 /* Clear all-context RES0 bits. */
1217 value
&= valid_mask
;
1218 raw_write(env
, ri
, value
);
1221 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1223 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1225 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1228 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1229 ri
->secure
& ARM_CP_SECSTATE_S
);
1231 return cpu
->ccsidr
[index
];
1234 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1237 raw_write(env
, ri
, value
& 0xf);
1240 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1242 CPUState
*cs
= ENV_GET_CPU(env
);
1245 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1248 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1251 /* External aborts are not possible in QEMU so A bit is always clear */
1255 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1256 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1257 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1258 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1259 /* Performance monitors are implementation defined in v7,
1260 * but with an ARM recommended set of registers, which we
1261 * follow (although we don't actually implement any counters)
1263 * Performance registers fall into three categories:
1264 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1265 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1266 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1267 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1268 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1270 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1271 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1272 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1273 .writefn
= pmcntenset_write
,
1274 .accessfn
= pmreg_access
,
1275 .raw_writefn
= raw_write
},
1276 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1277 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1278 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1279 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1280 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1281 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1283 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1284 .accessfn
= pmreg_access
,
1285 .writefn
= pmcntenclr_write
,
1286 .type
= ARM_CP_ALIAS
},
1287 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1288 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1289 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1290 .type
= ARM_CP_ALIAS
,
1291 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1292 .writefn
= pmcntenclr_write
},
1293 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1294 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1295 .accessfn
= pmreg_access
,
1296 .writefn
= pmovsr_write
,
1297 .raw_writefn
= raw_write
},
1298 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1299 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1300 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1301 .type
= ARM_CP_ALIAS
,
1302 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1303 .writefn
= pmovsr_write
,
1304 .raw_writefn
= raw_write
},
1305 /* Unimplemented so WI. */
1306 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1307 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
, .type
= ARM_CP_NOP
},
1308 #ifndef CONFIG_USER_ONLY
1309 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1310 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1311 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1312 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1313 .raw_writefn
= raw_write
},
1314 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1315 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1316 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1317 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1318 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1319 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1320 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
1321 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1322 .accessfn
= pmreg_access_ccntr
},
1323 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1324 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1325 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1327 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1329 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1330 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1331 .writefn
= pmccfiltr_write
,
1332 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1334 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1336 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1337 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1338 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1339 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1340 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1341 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1342 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1343 /* Unimplemented, RAZ/WI. */
1344 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1345 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1346 .accessfn
= pmreg_access_xevcntr
},
1347 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1348 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1349 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1351 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1352 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1353 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1354 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1355 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1357 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1358 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1359 .access
= PL1_RW
, .accessfn
= access_tpm
,
1360 .type
= ARM_CP_ALIAS
,
1361 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1363 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1364 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1365 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1366 .access
= PL1_RW
, .accessfn
= access_tpm
,
1368 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1369 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1370 .resetvalue
= 0x0 },
1371 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1372 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1373 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1374 .writefn
= pmintenclr_write
, },
1375 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1376 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1377 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1378 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1379 .writefn
= pmintenclr_write
},
1380 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1381 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1382 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1383 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1384 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1385 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1386 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1387 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1388 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1389 * just RAZ for all cores:
1391 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1392 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1393 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1394 /* Auxiliary fault status registers: these also are IMPDEF, and we
1395 * choose to RAZ/WI for all cores.
1397 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1398 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1399 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1400 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1401 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1402 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1403 /* MAIR can just read-as-written because we don't implement caches
1404 * and so don't need to care about memory attributes.
1406 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1407 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1408 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1410 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1411 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1412 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1414 /* For non-long-descriptor page tables these are PRRR and NMRR;
1415 * regardless they still act as reads-as-written for QEMU.
1417 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1418 * allows them to assign the correct fieldoffset based on the endianness
1419 * handled in the field definitions.
1421 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1422 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1423 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1424 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1425 .resetfn
= arm_cp_reset_ignore
},
1426 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1427 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1428 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1429 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1430 .resetfn
= arm_cp_reset_ignore
},
1431 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1432 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1433 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1434 /* 32 bit ITLB invalidates */
1435 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1436 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1437 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1438 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1439 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1440 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1441 /* 32 bit DTLB invalidates */
1442 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1443 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1444 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1445 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1446 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1447 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1448 /* 32 bit TLB invalidates */
1449 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1450 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1451 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1452 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1453 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1454 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1455 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1456 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1460 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1461 /* 32 bit TLB invalidates, Inner Shareable */
1462 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1463 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1464 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1465 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1466 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1467 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1468 .writefn
= tlbiasid_is_write
},
1469 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1470 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1471 .writefn
= tlbimvaa_is_write
},
1475 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1482 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1485 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1486 return CP_ACCESS_TRAP
;
1488 return CP_ACCESS_OK
;
1491 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1492 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1493 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1495 .writefn
= teecr_write
},
1496 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1497 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1498 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1502 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1503 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1504 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1506 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1507 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1509 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1510 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1511 .resetfn
= arm_cp_reset_ignore
},
1512 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1513 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1514 .access
= PL0_R
|PL1_W
,
1515 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1517 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1518 .access
= PL0_R
|PL1_W
,
1519 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1520 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1521 .resetfn
= arm_cp_reset_ignore
},
1522 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1523 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1525 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1526 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1528 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1529 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1534 #ifndef CONFIG_USER_ONLY
1536 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1539 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1540 * Writable only at the highest implemented exception level.
1542 int el
= arm_current_el(env
);
1546 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1547 return CP_ACCESS_TRAP
;
1551 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1552 arm_is_secure_below_el3(env
)) {
1553 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1554 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1562 if (!isread
&& el
< arm_highest_el(env
)) {
1563 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1566 return CP_ACCESS_OK
;
1569 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1572 unsigned int cur_el
= arm_current_el(env
);
1573 bool secure
= arm_is_secure(env
);
1575 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1577 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1578 return CP_ACCESS_TRAP
;
1581 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1582 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1583 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1584 return CP_ACCESS_TRAP_EL2
;
1586 return CP_ACCESS_OK
;
1589 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1592 unsigned int cur_el
= arm_current_el(env
);
1593 bool secure
= arm_is_secure(env
);
1595 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1596 * EL0[PV]TEN is zero.
1599 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1600 return CP_ACCESS_TRAP
;
1603 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1604 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1605 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1606 return CP_ACCESS_TRAP_EL2
;
1608 return CP_ACCESS_OK
;
1611 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1612 const ARMCPRegInfo
*ri
,
1615 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1618 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1619 const ARMCPRegInfo
*ri
,
1622 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1625 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1628 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1631 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1634 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1637 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1638 const ARMCPRegInfo
*ri
,
1641 /* The AArch64 register view of the secure physical timer is
1642 * always accessible from EL3, and configurably accessible from
1645 switch (arm_current_el(env
)) {
1647 if (!arm_is_secure(env
)) {
1648 return CP_ACCESS_TRAP
;
1650 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1651 return CP_ACCESS_TRAP_EL3
;
1653 return CP_ACCESS_OK
;
1656 return CP_ACCESS_TRAP
;
1658 return CP_ACCESS_OK
;
1660 g_assert_not_reached();
1664 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1666 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1669 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1671 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1674 /* Timer enabled: calculate and set current ISTATUS, irq, and
1675 * reset timer to when ISTATUS next has to change
1677 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1678 cpu
->env
.cp15
.cntvoff_el2
: 0;
1679 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1680 /* Note that this must be unsigned 64 bit arithmetic: */
1681 int istatus
= count
- offset
>= gt
->cval
;
1685 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1687 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1688 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1691 /* Next transition is when count rolls back over to zero */
1692 nexttick
= UINT64_MAX
;
1694 /* Next transition is when we hit cval */
1695 nexttick
= gt
->cval
+ offset
;
1697 /* Note that the desired next expiry time might be beyond the
1698 * signed-64-bit range of a QEMUTimer -- in this case we just
1699 * set the timer for as far in the future as possible. When the
1700 * timer expires we will reset the timer for any remaining period.
1702 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1703 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1705 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1706 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1708 /* Timer disabled: ISTATUS and timer output always clear */
1710 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1711 timer_del(cpu
->gt_timer
[timeridx
]);
1712 trace_arm_gt_recalc_disabled(timeridx
);
1716 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1719 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1721 timer_del(cpu
->gt_timer
[timeridx
]);
1724 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1726 return gt_get_countervalue(env
);
1729 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1731 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1734 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1738 trace_arm_gt_cval_write(timeridx
, value
);
1739 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1740 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1743 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1746 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1748 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1749 (gt_get_countervalue(env
) - offset
));
1752 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1756 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1758 trace_arm_gt_tval_write(timeridx
, value
);
1759 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1760 sextract64(value
, 0, 32);
1761 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1764 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1768 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1769 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1771 trace_arm_gt_ctl_write(timeridx
, value
);
1772 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1773 if ((oldval
^ value
) & 1) {
1774 /* Enable toggled */
1775 gt_recalc_timer(cpu
, timeridx
);
1776 } else if ((oldval
^ value
) & 2) {
1777 /* IMASK toggled: don't need to recalculate,
1778 * just set the interrupt line based on ISTATUS
1780 int irqstate
= (oldval
& 4) && !(value
& 2);
1782 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1783 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1787 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1789 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1792 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1795 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1798 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1800 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1803 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1806 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1809 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1812 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1815 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1817 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1820 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1823 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1826 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1828 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1831 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1834 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1837 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1840 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1843 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1846 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1848 trace_arm_gt_cntvoff_write(value
);
1849 raw_write(env
, ri
, value
);
1850 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1853 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1855 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1858 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1861 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1864 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1866 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1869 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1872 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1875 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1878 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1881 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1883 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1886 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1889 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1892 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1894 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1897 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1900 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1903 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1906 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1909 void arm_gt_ptimer_cb(void *opaque
)
1911 ARMCPU
*cpu
= opaque
;
1913 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1916 void arm_gt_vtimer_cb(void *opaque
)
1918 ARMCPU
*cpu
= opaque
;
1920 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1923 void arm_gt_htimer_cb(void *opaque
)
1925 ARMCPU
*cpu
= opaque
;
1927 gt_recalc_timer(cpu
, GTIMER_HYP
);
1930 void arm_gt_stimer_cb(void *opaque
)
1932 ARMCPU
*cpu
= opaque
;
1934 gt_recalc_timer(cpu
, GTIMER_SEC
);
1937 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1938 /* Note that CNTFRQ is purely reads-as-written for the benefit
1939 * of software; writing it doesn't actually change the timer frequency.
1940 * Our reset value matches the fixed frequency we implement the timer at.
1942 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1943 .type
= ARM_CP_ALIAS
,
1944 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1945 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1947 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1948 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1949 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1950 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1951 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1953 /* overall control: mostly access permissions */
1954 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1955 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1957 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1960 /* per-timer control */
1961 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1962 .secure
= ARM_CP_SECSTATE_NS
,
1963 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1964 .accessfn
= gt_ptimer_access
,
1965 .fieldoffset
= offsetoflow32(CPUARMState
,
1966 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1967 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1969 { .name
= "CNTP_CTL(S)",
1970 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1971 .secure
= ARM_CP_SECSTATE_S
,
1972 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1973 .accessfn
= gt_ptimer_access
,
1974 .fieldoffset
= offsetoflow32(CPUARMState
,
1975 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1976 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1978 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1979 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1980 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1981 .accessfn
= gt_ptimer_access
,
1982 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1984 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1986 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1987 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1988 .accessfn
= gt_vtimer_access
,
1989 .fieldoffset
= offsetoflow32(CPUARMState
,
1990 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1991 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1993 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1994 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1995 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1996 .accessfn
= gt_vtimer_access
,
1997 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1999 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2001 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2002 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2003 .secure
= ARM_CP_SECSTATE_NS
,
2004 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2005 .accessfn
= gt_ptimer_access
,
2006 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2008 { .name
= "CNTP_TVAL(S)",
2009 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2010 .secure
= ARM_CP_SECSTATE_S
,
2011 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2012 .accessfn
= gt_ptimer_access
,
2013 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2015 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2016 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2017 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2018 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2019 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2021 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2022 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2023 .accessfn
= gt_vtimer_access
,
2024 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2026 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2027 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2028 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2029 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2030 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2032 /* The counter itself */
2033 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2034 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2035 .accessfn
= gt_pct_access
,
2036 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2038 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2039 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2040 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2041 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2043 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2044 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2045 .accessfn
= gt_vct_access
,
2046 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2048 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2049 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2050 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2051 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2053 /* Comparison value, indicating when the timer goes off */
2054 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2055 .secure
= ARM_CP_SECSTATE_NS
,
2056 .access
= PL1_RW
| PL0_R
,
2057 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2058 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2059 .accessfn
= gt_ptimer_access
,
2060 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2062 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
2063 .secure
= ARM_CP_SECSTATE_S
,
2064 .access
= PL1_RW
| PL0_R
,
2065 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2066 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2067 .accessfn
= gt_ptimer_access
,
2068 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2070 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2071 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2072 .access
= PL1_RW
| PL0_R
,
2074 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2075 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2076 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2078 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2079 .access
= PL1_RW
| PL0_R
,
2080 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2082 .accessfn
= gt_vtimer_access
,
2083 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2085 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2086 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2087 .access
= PL1_RW
| PL0_R
,
2089 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2090 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2091 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2093 /* Secure timer -- this is actually restricted to only EL3
2094 * and configurably Secure-EL1 via the accessfn.
2096 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2097 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2098 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2099 .accessfn
= gt_stimer_access
,
2100 .readfn
= gt_sec_tval_read
,
2101 .writefn
= gt_sec_tval_write
,
2102 .resetfn
= gt_sec_timer_reset
,
2104 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2105 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2106 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2107 .accessfn
= gt_stimer_access
,
2108 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2110 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2112 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2113 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2114 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2115 .accessfn
= gt_stimer_access
,
2116 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2117 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2123 /* In user-mode none of the generic timer registers are accessible,
2124 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
2125 * so instead just don't register any of them.
2127 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2133 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2135 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2136 raw_write(env
, ri
, value
);
2137 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2138 raw_write(env
, ri
, value
& 0xfffff6ff);
2140 raw_write(env
, ri
, value
& 0xfffff1ff);
2144 #ifndef CONFIG_USER_ONLY
2145 /* get_phys_addr() isn't present for user-mode-only targets */
2147 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2151 /* The ATS12NSO* operations must trap to EL3 if executed in
2152 * Secure EL1 (which can only happen if EL3 is AArch64).
2153 * They are simply UNDEF if executed from NS EL1.
2154 * They function normally from EL2 or EL3.
2156 if (arm_current_el(env
) == 1) {
2157 if (arm_is_secure_below_el3(env
)) {
2158 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2160 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2163 return CP_ACCESS_OK
;
2166 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2167 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2170 target_ulong page_size
;
2174 bool format64
= false;
2175 MemTxAttrs attrs
= {};
2176 ARMMMUFaultInfo fi
= {};
2177 ARMCacheAttrs cacheattrs
= {};
2179 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2180 &prot
, &page_size
, &fi
, &cacheattrs
);
2184 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2187 * * TTBCR.EAE determines whether the result is returned using the
2188 * 32-bit or the 64-bit PAR format
2189 * * Instructions executed in Hyp mode always use the 64bit format
2191 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2192 * * The Non-secure TTBCR.EAE bit is set to 1
2193 * * The implementation includes EL2, and the value of HCR.VM is 1
2195 * ATS1Hx always uses the 64bit format (not supported yet).
2197 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
2199 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2200 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
2201 format64
|= env
->cp15
.hcr_el2
& HCR_VM
;
2203 format64
|= arm_current_el(env
) == 2;
2209 /* Create a 64-bit PAR */
2210 par64
= (1 << 11); /* LPAE bit always set */
2212 par64
|= phys_addr
& ~0xfffULL
;
2213 if (!attrs
.secure
) {
2214 par64
|= (1 << 9); /* NS */
2216 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
2217 par64
|= cacheattrs
.shareability
<< 7; /* SH */
2219 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
2222 par64
|= (fsr
& 0x3f) << 1; /* FS */
2223 /* Note that S2WLK and FSTAGE are always zero, because we don't
2224 * implement virtualization and therefore there can't be a stage 2
2229 /* fsr is a DFSR/IFSR value for the short descriptor
2230 * translation table format (with WnR always clear).
2231 * Convert it to a 32-bit PAR.
2234 /* We do not set any attribute bits in the PAR */
2235 if (page_size
== (1 << 24)
2236 && arm_feature(env
, ARM_FEATURE_V7
)) {
2237 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2239 par64
= phys_addr
& 0xfffff000;
2241 if (!attrs
.secure
) {
2242 par64
|= (1 << 9); /* NS */
2245 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
2247 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2248 ((fsr
& 0xf) << 1) | 1;
2254 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2256 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2259 int el
= arm_current_el(env
);
2260 bool secure
= arm_is_secure_below_el3(env
);
2262 switch (ri
->opc2
& 6) {
2264 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2267 mmu_idx
= ARMMMUIdx_S1E3
;
2270 mmu_idx
= ARMMMUIdx_S1NSE1
;
2273 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2276 g_assert_not_reached();
2280 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2283 mmu_idx
= ARMMMUIdx_S1SE0
;
2286 mmu_idx
= ARMMMUIdx_S1NSE0
;
2289 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2292 g_assert_not_reached();
2296 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2297 mmu_idx
= ARMMMUIdx_S12NSE1
;
2300 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2301 mmu_idx
= ARMMMUIdx_S12NSE0
;
2304 g_assert_not_reached();
2307 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2309 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2312 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2315 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2318 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2320 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2323 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2326 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2327 return CP_ACCESS_TRAP
;
2329 return CP_ACCESS_OK
;
2332 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2335 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2337 int secure
= arm_is_secure_below_el3(env
);
2339 switch (ri
->opc2
& 6) {
2342 case 0: /* AT S1E1R, AT S1E1W */
2343 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2345 case 4: /* AT S1E2R, AT S1E2W */
2346 mmu_idx
= ARMMMUIdx_S1E2
;
2348 case 6: /* AT S1E3R, AT S1E3W */
2349 mmu_idx
= ARMMMUIdx_S1E3
;
2352 g_assert_not_reached();
2355 case 2: /* AT S1E0R, AT S1E0W */
2356 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2358 case 4: /* AT S12E1R, AT S12E1W */
2359 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2361 case 6: /* AT S12E0R, AT S12E0W */
2362 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2365 g_assert_not_reached();
2368 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2372 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2373 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2374 .access
= PL1_RW
, .resetvalue
= 0,
2375 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2376 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2377 .writefn
= par_write
},
2378 #ifndef CONFIG_USER_ONLY
2379 /* This underdecoding is safe because the reginfo is NO_RAW. */
2380 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2381 .access
= PL1_W
, .accessfn
= ats_access
,
2382 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2387 /* Return basic MPU access permission bits. */
2388 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2395 for (i
= 0; i
< 16; i
+= 2) {
2396 ret
|= (val
>> i
) & mask
;
2402 /* Pad basic MPU access permission bits to extended format. */
2403 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2410 for (i
= 0; i
< 16; i
+= 2) {
2411 ret
|= (val
& mask
) << i
;
2417 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2420 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2423 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2425 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2428 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2431 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2434 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2436 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2439 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2441 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2447 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2451 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2454 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2455 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2461 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2462 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2466 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2469 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2470 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2472 if (value
>= nrgs
) {
2473 qemu_log_mask(LOG_GUEST_ERROR
,
2474 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2475 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2479 raw_write(env
, ri
, value
);
2482 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2483 /* Reset for all these registers is handled in arm_cpu_reset(),
2484 * because the PMSAv7 is also used by M-profile CPUs, which do
2485 * not register cpregs but still need the state to be reset.
2487 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2488 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2489 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2490 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2491 .resetfn
= arm_cp_reset_ignore
},
2492 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2493 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2494 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2495 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2496 .resetfn
= arm_cp_reset_ignore
},
2497 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2498 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2499 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2500 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2501 .resetfn
= arm_cp_reset_ignore
},
2502 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2504 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
2505 .writefn
= pmsav7_rgnr_write
,
2506 .resetfn
= arm_cp_reset_ignore
},
2510 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2511 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2512 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2513 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2514 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2515 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2516 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2517 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2518 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2519 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2521 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2523 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2525 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2527 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2529 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2530 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2532 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2533 /* Protection region base and size registers */
2534 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2535 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2536 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2537 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2538 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2539 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2540 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2541 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2542 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2543 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2544 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2545 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2546 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2547 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2548 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2549 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2550 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2551 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2552 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2553 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2554 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2555 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2556 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2557 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2561 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2564 TCR
*tcr
= raw_ptr(env
, ri
);
2565 int maskshift
= extract32(value
, 0, 3);
2567 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2568 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2569 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2570 * using Long-desciptor translation table format */
2571 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2572 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2573 /* In an implementation that includes the Security Extensions
2574 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2575 * Short-descriptor translation table format.
2577 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2583 /* Update the masks corresponding to the TCR bank being written
2584 * Note that we always calculate mask and base_mask, but
2585 * they are only used for short-descriptor tables (ie if EAE is 0);
2586 * for long-descriptor tables the TCR fields are used differently
2587 * and the mask and base_mask values are meaningless.
2589 tcr
->raw_tcr
= value
;
2590 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2591 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2594 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2597 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2599 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2600 /* With LPAE the TTBCR could result in a change of ASID
2601 * via the TTBCR.A1 bit, so do a TLB flush.
2603 tlb_flush(CPU(cpu
));
2605 vmsa_ttbcr_raw_write(env
, ri
, value
);
2608 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2610 TCR
*tcr
= raw_ptr(env
, ri
);
2612 /* Reset both the TCR as well as the masks corresponding to the bank of
2613 * the TCR being reset.
2617 tcr
->base_mask
= 0xffffc000u
;
2620 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2623 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2624 TCR
*tcr
= raw_ptr(env
, ri
);
2626 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2627 tlb_flush(CPU(cpu
));
2628 tcr
->raw_tcr
= value
;
2631 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2634 /* 64 bit accesses to the TTBRs can change the ASID and so we
2635 * must flush the TLB.
2637 if (cpreg_field_is_64bit(ri
)) {
2638 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2640 tlb_flush(CPU(cpu
));
2642 raw_write(env
, ri
, value
);
2645 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2648 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2649 CPUState
*cs
= CPU(cpu
);
2651 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2652 if (raw_read(env
, ri
) != value
) {
2653 tlb_flush_by_mmuidx(cs
,
2654 ARMMMUIdxBit_S12NSE1
|
2655 ARMMMUIdxBit_S12NSE0
|
2657 raw_write(env
, ri
, value
);
2661 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2662 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2663 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2664 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2665 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2666 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2667 .access
= PL1_RW
, .resetvalue
= 0,
2668 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2669 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2670 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2671 .access
= PL1_RW
, .resetvalue
= 0,
2672 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2673 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2674 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2675 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2676 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2681 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2682 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2683 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2685 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2686 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2687 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2688 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2689 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2690 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2691 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2692 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2693 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2694 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2695 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2696 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2697 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2698 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2699 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2700 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2701 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2702 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2703 .raw_writefn
= vmsa_ttbcr_raw_write
,
2704 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2705 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2709 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2712 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2713 /* The OS_TYPE bit in this register changes the reported CPUID! */
2714 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2715 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2718 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2721 env
->cp15
.c15_threadid
= value
& 0xffff;
2724 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2727 /* Wait-for-interrupt (deprecated) */
2728 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2731 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2734 /* On OMAP there are registers indicating the max/min index of dcache lines
2735 * containing a dirty line; cache flush operations have to reset these.
2737 env
->cp15
.c15_i_max
= 0x000;
2738 env
->cp15
.c15_i_min
= 0xff0;
2741 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2742 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2743 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2744 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2746 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2747 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2748 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2750 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2751 .writefn
= omap_ticonfig_write
},
2752 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2754 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2755 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2756 .access
= PL1_RW
, .resetvalue
= 0xff0,
2757 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2758 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2760 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2761 .writefn
= omap_threadid_write
},
2762 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2763 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2764 .type
= ARM_CP_NO_RAW
,
2765 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2766 /* TODO: Peripheral port remap register:
2767 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2768 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2771 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2772 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2773 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2774 .writefn
= omap_cachemaint_write
},
2775 { .name
= "C9", .cp
= 15, .crn
= 9,
2776 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2777 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2781 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2784 env
->cp15
.c15_cpar
= value
& 0x3fff;
2787 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2788 { .name
= "XSCALE_CPAR",
2789 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2790 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2791 .writefn
= xscale_cpar_write
, },
2792 { .name
= "XSCALE_AUXCR",
2793 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2794 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2796 /* XScale specific cache-lockdown: since we have no cache we NOP these
2797 * and hope the guest does not really rely on cache behaviour.
2799 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2800 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2801 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2802 { .name
= "XSCALE_UNLOCK_ICACHE",
2803 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2804 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2805 { .name
= "XSCALE_DCACHE_LOCK",
2806 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2807 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2808 { .name
= "XSCALE_UNLOCK_DCACHE",
2809 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2810 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2814 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2815 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2816 * implementation of this implementation-defined space.
2817 * Ideally this should eventually disappear in favour of actually
2818 * implementing the correct behaviour for all cores.
2820 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2821 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2823 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2828 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2829 /* Cache status: RAZ because we have no cache so it's always clean */
2830 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2831 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2836 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2837 /* We never have a a block transfer operation in progress */
2838 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2839 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2841 /* The cache ops themselves: these all NOP for QEMU */
2842 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2843 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2844 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2845 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2846 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2847 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2848 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2849 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2850 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2851 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2852 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2853 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2857 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2858 /* The cache test-and-clean instructions always return (1 << 30)
2859 * to indicate that there are no dirty cache lines.
2861 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2862 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2863 .resetvalue
= (1 << 30) },
2864 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2865 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2866 .resetvalue
= (1 << 30) },
2870 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2871 /* Ignore ReadBuffer accesses */
2872 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2873 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2874 .access
= PL1_RW
, .resetvalue
= 0,
2875 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2879 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2881 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2882 unsigned int cur_el
= arm_current_el(env
);
2883 bool secure
= arm_is_secure(env
);
2885 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2886 return env
->cp15
.vpidr_el2
;
2888 return raw_read(env
, ri
);
2891 static uint64_t mpidr_read_val(CPUARMState
*env
)
2893 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2894 uint64_t mpidr
= cpu
->mp_affinity
;
2896 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2897 mpidr
|= (1U << 31);
2898 /* Cores which are uniprocessor (non-coherent)
2899 * but still implement the MP extensions set
2900 * bit 30. (For instance, Cortex-R5).
2902 if (cpu
->mp_is_up
) {
2903 mpidr
|= (1u << 30);
2909 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2911 unsigned int cur_el
= arm_current_el(env
);
2912 bool secure
= arm_is_secure(env
);
2914 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2915 return env
->cp15
.vmpidr_el2
;
2917 return mpidr_read_val(env
);
2920 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2921 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2922 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2923 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2927 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2929 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2930 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2931 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2933 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2934 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2935 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2937 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2938 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2939 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2940 offsetof(CPUARMState
, cp15
.par_ns
)} },
2941 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2942 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2943 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2944 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2945 .writefn
= vmsa_ttbr_write
, },
2946 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2947 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2948 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2949 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2950 .writefn
= vmsa_ttbr_write
, },
2954 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2956 return vfp_get_fpcr(env
);
2959 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2962 vfp_set_fpcr(env
, value
);
2965 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2967 return vfp_get_fpsr(env
);
2970 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2973 vfp_set_fpsr(env
, value
);
2976 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2979 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2980 return CP_ACCESS_TRAP
;
2982 return CP_ACCESS_OK
;
2985 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2988 env
->daif
= value
& PSTATE_DAIF
;
2991 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2992 const ARMCPRegInfo
*ri
,
2995 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2996 * SCTLR_EL1.UCI is set.
2998 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2999 return CP_ACCESS_TRAP
;
3001 return CP_ACCESS_OK
;
3004 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3005 * Page D4-1736 (DDI0487A.b)
3008 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3011 CPUState
*cs
= ENV_GET_CPU(env
);
3013 if (arm_is_secure_below_el3(env
)) {
3014 tlb_flush_by_mmuidx(cs
,
3015 ARMMMUIdxBit_S1SE1
|
3016 ARMMMUIdxBit_S1SE0
);
3018 tlb_flush_by_mmuidx(cs
,
3019 ARMMMUIdxBit_S12NSE1
|
3020 ARMMMUIdxBit_S12NSE0
);
3024 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3027 CPUState
*cs
= ENV_GET_CPU(env
);
3028 bool sec
= arm_is_secure_below_el3(env
);
3031 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3032 ARMMMUIdxBit_S1SE1
|
3033 ARMMMUIdxBit_S1SE0
);
3035 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3036 ARMMMUIdxBit_S12NSE1
|
3037 ARMMMUIdxBit_S12NSE0
);
3041 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3044 /* Note that the 'ALL' scope must invalidate both stage 1 and
3045 * stage 2 translations, whereas most other scopes only invalidate
3046 * stage 1 translations.
3048 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3049 CPUState
*cs
= CPU(cpu
);
3051 if (arm_is_secure_below_el3(env
)) {
3052 tlb_flush_by_mmuidx(cs
,
3053 ARMMMUIdxBit_S1SE1
|
3054 ARMMMUIdxBit_S1SE0
);
3056 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3057 tlb_flush_by_mmuidx(cs
,
3058 ARMMMUIdxBit_S12NSE1
|
3059 ARMMMUIdxBit_S12NSE0
|
3062 tlb_flush_by_mmuidx(cs
,
3063 ARMMMUIdxBit_S12NSE1
|
3064 ARMMMUIdxBit_S12NSE0
);
3069 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3072 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3073 CPUState
*cs
= CPU(cpu
);
3075 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3078 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3081 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3082 CPUState
*cs
= CPU(cpu
);
3084 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3087 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3090 /* Note that the 'ALL' scope must invalidate both stage 1 and
3091 * stage 2 translations, whereas most other scopes only invalidate
3092 * stage 1 translations.
3094 CPUState
*cs
= ENV_GET_CPU(env
);
3095 bool sec
= arm_is_secure_below_el3(env
);
3096 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3099 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3100 ARMMMUIdxBit_S1SE1
|
3101 ARMMMUIdxBit_S1SE0
);
3102 } else if (has_el2
) {
3103 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3104 ARMMMUIdxBit_S12NSE1
|
3105 ARMMMUIdxBit_S12NSE0
|
3108 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3109 ARMMMUIdxBit_S12NSE1
|
3110 ARMMMUIdxBit_S12NSE0
);
3114 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3117 CPUState
*cs
= ENV_GET_CPU(env
);
3119 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3122 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3125 CPUState
*cs
= ENV_GET_CPU(env
);
3127 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3130 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3133 /* Invalidate by VA, EL1&0 (AArch64 version).
3134 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3135 * since we don't support flush-for-specific-ASID-only or
3136 * flush-last-level-only.
3138 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3139 CPUState
*cs
= CPU(cpu
);
3140 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3142 if (arm_is_secure_below_el3(env
)) {
3143 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3144 ARMMMUIdxBit_S1SE1
|
3145 ARMMMUIdxBit_S1SE0
);
3147 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3148 ARMMMUIdxBit_S12NSE1
|
3149 ARMMMUIdxBit_S12NSE0
);
3153 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3156 /* Invalidate by VA, EL2
3157 * Currently handles both VAE2 and VALE2, since we don't support
3158 * flush-last-level-only.
3160 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3161 CPUState
*cs
= CPU(cpu
);
3162 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3164 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3167 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3170 /* Invalidate by VA, EL3
3171 * Currently handles both VAE3 and VALE3, since we don't support
3172 * flush-last-level-only.
3174 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3175 CPUState
*cs
= CPU(cpu
);
3176 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3178 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3181 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3184 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3185 CPUState
*cs
= CPU(cpu
);
3186 bool sec
= arm_is_secure_below_el3(env
);
3187 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3190 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3191 ARMMMUIdxBit_S1SE1
|
3192 ARMMMUIdxBit_S1SE0
);
3194 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3195 ARMMMUIdxBit_S12NSE1
|
3196 ARMMMUIdxBit_S12NSE0
);
3200 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3203 CPUState
*cs
= ENV_GET_CPU(env
);
3204 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3206 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3210 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3213 CPUState
*cs
= ENV_GET_CPU(env
);
3214 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3216 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3220 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3223 /* Invalidate by IPA. This has to invalidate any structures that
3224 * contain only stage 2 translation information, but does not need
3225 * to apply to structures that contain combined stage 1 and stage 2
3226 * translation information.
3227 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3229 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3230 CPUState
*cs
= CPU(cpu
);
3233 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3237 pageaddr
= sextract64(value
<< 12, 0, 48);
3239 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3242 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3245 CPUState
*cs
= ENV_GET_CPU(env
);
3248 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3252 pageaddr
= sextract64(value
<< 12, 0, 48);
3254 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3258 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3261 /* We don't implement EL2, so the only control on DC ZVA is the
3262 * bit in the SCTLR which can prohibit access for EL0.
3264 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3265 return CP_ACCESS_TRAP
;
3267 return CP_ACCESS_OK
;
3270 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3272 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3273 int dzp_bit
= 1 << 4;
3275 /* DZP indicates whether DC ZVA access is allowed */
3276 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3279 return cpu
->dcz_blocksize
| dzp_bit
;
3282 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3285 if (!(env
->pstate
& PSTATE_SP
)) {
3286 /* Access to SP_EL0 is undefined if it's being used as
3287 * the stack pointer.
3289 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3291 return CP_ACCESS_OK
;
3294 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3296 return env
->pstate
& PSTATE_SP
;
3299 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3301 update_spsel(env
, val
);
3304 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3307 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3309 if (raw_read(env
, ri
) == value
) {
3310 /* Skip the TLB flush if nothing actually changed; Linux likes
3311 * to do a lot of pointless SCTLR writes.
3316 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
3317 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3321 raw_write(env
, ri
, value
);
3322 /* ??? Lots of these bits are not implemented. */
3323 /* This may enable/disable the MMU, so do a TLB flush. */
3324 tlb_flush(CPU(cpu
));
3327 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3330 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3331 return CP_ACCESS_TRAP_FP_EL2
;
3333 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3334 return CP_ACCESS_TRAP_FP_EL3
;
3336 return CP_ACCESS_OK
;
3339 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3342 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3345 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3346 /* Minimal set of EL0-visible registers. This will need to be expanded
3347 * significantly for system emulation of AArch64 CPUs.
3349 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3350 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3351 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3352 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3353 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3354 .type
= ARM_CP_NO_RAW
,
3355 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3356 .fieldoffset
= offsetof(CPUARMState
, daif
),
3357 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3358 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3359 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3360 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
3361 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3362 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3363 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3364 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
3365 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3366 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3367 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3368 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3369 .readfn
= aa64_dczid_read
},
3370 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3371 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3372 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3373 #ifndef CONFIG_USER_ONLY
3374 /* Avoid overhead of an access check that always passes in user-mode */
3375 .accessfn
= aa64_zva_access
,
3378 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3379 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3380 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3381 /* Cache ops: all NOPs since we don't emulate caches */
3382 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3383 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3384 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3385 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3386 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3387 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3388 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3389 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3390 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3391 .accessfn
= aa64_cacheop_access
},
3392 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3393 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3394 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3395 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3396 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3397 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3398 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3399 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3400 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3401 .accessfn
= aa64_cacheop_access
},
3402 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3403 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3404 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3405 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3406 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3407 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3408 .accessfn
= aa64_cacheop_access
},
3409 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3410 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3411 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3412 .accessfn
= aa64_cacheop_access
},
3413 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3414 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3415 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3416 /* TLBI operations */
3417 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3418 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3419 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3420 .writefn
= tlbi_aa64_vmalle1is_write
},
3421 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3422 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3423 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3424 .writefn
= tlbi_aa64_vae1is_write
},
3425 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3426 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3427 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3428 .writefn
= tlbi_aa64_vmalle1is_write
},
3429 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3430 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3431 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3432 .writefn
= tlbi_aa64_vae1is_write
},
3433 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3434 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3435 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3436 .writefn
= tlbi_aa64_vae1is_write
},
3437 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3438 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3439 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3440 .writefn
= tlbi_aa64_vae1is_write
},
3441 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3442 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3443 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3444 .writefn
= tlbi_aa64_vmalle1_write
},
3445 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3446 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3447 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3448 .writefn
= tlbi_aa64_vae1_write
},
3449 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3450 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3451 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3452 .writefn
= tlbi_aa64_vmalle1_write
},
3453 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3454 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3455 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3456 .writefn
= tlbi_aa64_vae1_write
},
3457 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3458 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3459 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3460 .writefn
= tlbi_aa64_vae1_write
},
3461 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3462 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3463 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3464 .writefn
= tlbi_aa64_vae1_write
},
3465 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3466 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3467 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3468 .writefn
= tlbi_aa64_ipas2e1is_write
},
3469 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3470 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3471 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3472 .writefn
= tlbi_aa64_ipas2e1is_write
},
3473 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3474 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3475 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3476 .writefn
= tlbi_aa64_alle1is_write
},
3477 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3478 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3479 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3480 .writefn
= tlbi_aa64_alle1is_write
},
3481 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3482 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3483 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3484 .writefn
= tlbi_aa64_ipas2e1_write
},
3485 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3486 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3487 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3488 .writefn
= tlbi_aa64_ipas2e1_write
},
3489 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3490 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3491 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3492 .writefn
= tlbi_aa64_alle1_write
},
3493 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3494 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3495 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3496 .writefn
= tlbi_aa64_alle1is_write
},
3497 #ifndef CONFIG_USER_ONLY
3498 /* 64 bit address translation operations */
3499 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3500 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3501 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3502 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3503 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3504 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3505 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3506 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3507 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3508 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3509 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3510 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3511 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3512 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3513 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3514 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3515 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3516 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3517 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3518 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3519 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3520 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3521 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3522 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3523 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3524 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3525 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3526 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3527 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3528 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3529 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3530 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3531 .type
= ARM_CP_ALIAS
,
3532 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3533 .access
= PL1_RW
, .resetvalue
= 0,
3534 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3535 .writefn
= par_write
},
3537 /* TLB invalidate last level of translation table walk */
3538 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3539 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3540 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3541 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3542 .writefn
= tlbimvaa_is_write
},
3543 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3544 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3545 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3546 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3547 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3548 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3549 .writefn
= tlbimva_hyp_write
},
3550 { .name
= "TLBIMVALHIS",
3551 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3552 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3553 .writefn
= tlbimva_hyp_is_write
},
3554 { .name
= "TLBIIPAS2",
3555 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3556 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3557 .writefn
= tlbiipas2_write
},
3558 { .name
= "TLBIIPAS2IS",
3559 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3560 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3561 .writefn
= tlbiipas2_is_write
},
3562 { .name
= "TLBIIPAS2L",
3563 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3564 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3565 .writefn
= tlbiipas2_write
},
3566 { .name
= "TLBIIPAS2LIS",
3567 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3568 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3569 .writefn
= tlbiipas2_is_write
},
3570 /* 32 bit cache operations */
3571 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3572 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3573 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3574 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3575 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3576 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3577 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3578 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3579 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3580 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3581 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3582 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3583 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3584 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3585 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3586 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3587 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3588 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3589 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3590 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3591 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3592 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3593 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3594 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3595 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3596 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3597 /* MMU Domain access control / MPU write buffer control */
3598 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3599 .access
= PL1_RW
, .resetvalue
= 0,
3600 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3601 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3602 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3603 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3604 .type
= ARM_CP_ALIAS
,
3605 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3607 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3608 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3609 .type
= ARM_CP_ALIAS
,
3610 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3612 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3613 /* We rely on the access checks not allowing the guest to write to the
3614 * state field when SPSel indicates that it's being used as the stack
3617 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3618 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3619 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3620 .type
= ARM_CP_ALIAS
,
3621 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3622 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3623 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3624 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3625 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3626 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3627 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3628 .type
= ARM_CP_NO_RAW
,
3629 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3630 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3631 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3632 .type
= ARM_CP_ALIAS
,
3633 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3634 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3635 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3636 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3637 .access
= PL2_RW
, .resetvalue
= 0,
3638 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3639 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3640 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3641 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3642 .access
= PL2_RW
, .resetvalue
= 0,
3643 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3644 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3645 .type
= ARM_CP_ALIAS
,
3646 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3648 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3649 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3650 .type
= ARM_CP_ALIAS
,
3651 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3653 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3654 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3655 .type
= ARM_CP_ALIAS
,
3656 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3658 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3659 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3660 .type
= ARM_CP_ALIAS
,
3661 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3663 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3664 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3665 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3667 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3668 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3669 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3670 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3671 .writefn
= sdcr_write
,
3672 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3676 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3677 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3678 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3679 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3681 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3682 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3683 .type
= ARM_CP_NO_RAW
,
3684 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3686 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3687 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3688 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3689 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3690 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3691 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3692 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3694 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3695 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3696 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3697 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3698 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3699 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3701 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3702 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3703 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3705 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3706 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3707 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3709 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3710 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3711 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3713 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3714 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3715 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3716 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3717 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3718 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3719 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3720 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3721 .cp
= 15, .opc1
= 6, .crm
= 2,
3722 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3723 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3724 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3725 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3726 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3727 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3728 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3729 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3730 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3731 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3732 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3733 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3734 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3735 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3736 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3737 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3739 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3740 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3741 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3742 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3743 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3744 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3745 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3746 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3748 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3749 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3750 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3751 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3752 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3754 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3755 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3756 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3757 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3758 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3759 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3760 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3761 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3762 .access
= PL2_RW
, .accessfn
= access_tda
,
3763 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3764 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3765 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3766 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3767 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3768 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3769 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3770 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3774 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3776 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3777 uint64_t valid_mask
= HCR_MASK
;
3779 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3780 valid_mask
&= ~HCR_HCD
;
3781 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
3782 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3783 * However, if we're using the SMC PSCI conduit then QEMU is
3784 * effectively acting like EL3 firmware and so the guest at
3785 * EL2 should retain the ability to prevent EL1 from being
3786 * able to make SMC calls into the ersatz firmware, so in
3787 * that case HCR.TSC should be read/write.
3789 valid_mask
&= ~HCR_TSC
;
3792 /* Clear RES0 bits. */
3793 value
&= valid_mask
;
3795 /* These bits change the MMU setup:
3796 * HCR_VM enables stage 2 translation
3797 * HCR_PTW forbids certain page-table setups
3798 * HCR_DC Disables stage1 and enables stage2 translation
3800 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3801 tlb_flush(CPU(cpu
));
3803 raw_write(env
, ri
, value
);
3806 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3807 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3808 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3809 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3810 .writefn
= hcr_write
},
3811 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3812 .type
= ARM_CP_ALIAS
,
3813 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3815 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3816 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3817 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3818 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3819 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3820 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3821 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3822 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3823 .type
= ARM_CP_ALIAS
,
3824 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3826 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3827 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3828 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3829 .access
= PL2_RW
, .writefn
= vbar_write
,
3830 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3832 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3833 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3834 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3835 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3836 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3837 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3838 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3839 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3840 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3841 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3842 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3844 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3845 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3846 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3847 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3848 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3849 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3850 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3852 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3853 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3854 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3855 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3857 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3858 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3859 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3861 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3862 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3863 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3865 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3866 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3868 /* no .writefn needed as this can't cause an ASID change;
3869 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3871 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3872 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3873 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3874 .type
= ARM_CP_ALIAS
,
3875 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3876 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3877 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3878 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3880 /* no .writefn needed as this can't cause an ASID change;
3881 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3883 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3884 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3885 .cp
= 15, .opc1
= 6, .crm
= 2,
3886 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3887 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3888 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3889 .writefn
= vttbr_write
},
3890 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3891 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3892 .access
= PL2_RW
, .writefn
= vttbr_write
,
3893 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3894 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3895 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3896 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3897 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3898 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3899 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3900 .access
= PL2_RW
, .resetvalue
= 0,
3901 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3902 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3903 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3904 .access
= PL2_RW
, .resetvalue
= 0,
3905 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3906 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3907 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3908 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3909 { .name
= "TLBIALLNSNH",
3910 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3911 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3912 .writefn
= tlbiall_nsnh_write
},
3913 { .name
= "TLBIALLNSNHIS",
3914 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3915 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3916 .writefn
= tlbiall_nsnh_is_write
},
3917 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3918 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3919 .writefn
= tlbiall_hyp_write
},
3920 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3921 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3922 .writefn
= tlbiall_hyp_is_write
},
3923 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3924 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3925 .writefn
= tlbimva_hyp_write
},
3926 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3927 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3928 .writefn
= tlbimva_hyp_is_write
},
3929 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3930 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3931 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3932 .writefn
= tlbi_aa64_alle2_write
},
3933 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3934 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3935 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3936 .writefn
= tlbi_aa64_vae2_write
},
3937 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3938 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3939 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3940 .writefn
= tlbi_aa64_vae2_write
},
3941 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3942 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3943 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3944 .writefn
= tlbi_aa64_alle2is_write
},
3945 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3946 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3947 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3948 .writefn
= tlbi_aa64_vae2is_write
},
3949 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3950 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3951 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3952 .writefn
= tlbi_aa64_vae2is_write
},
3953 #ifndef CONFIG_USER_ONLY
3954 /* Unlike the other EL2-related AT operations, these must
3955 * UNDEF from EL3 if EL2 is not implemented, which is why we
3956 * define them here rather than with the rest of the AT ops.
3958 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3959 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3960 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3961 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3962 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3963 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3964 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3965 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3966 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3967 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3968 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3969 * to behave as if SCR.NS was 1.
3971 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3973 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3974 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3976 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3977 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3978 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3979 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3980 * reset values as IMPDEF. We choose to reset to 3 to comply with
3981 * both ARMv7 and ARMv8.
3983 .access
= PL2_RW
, .resetvalue
= 3,
3984 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3985 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3986 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3987 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3988 .writefn
= gt_cntvoff_write
,
3989 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3990 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3991 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3992 .writefn
= gt_cntvoff_write
,
3993 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3994 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3995 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3996 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3997 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3998 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3999 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4000 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4001 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
4002 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4003 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4004 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4005 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
4006 .resetfn
= gt_hyp_timer_reset
,
4007 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
4008 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4010 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4012 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
4014 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
4016 /* The only field of MDCR_EL2 that has a defined architectural reset value
4017 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4018 * don't impelment any PMU event counters, so using zero as a reset
4019 * value for MDCR_EL2 is okay
4021 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4022 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4023 .access
= PL2_RW
, .resetvalue
= 0,
4024 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
4025 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
4026 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4027 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4028 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4029 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
4030 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4032 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4033 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4034 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4036 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
4040 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4043 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4044 * At Secure EL1 it traps to EL3.
4046 if (arm_current_el(env
) == 3) {
4047 return CP_ACCESS_OK
;
4049 if (arm_is_secure_below_el3(env
)) {
4050 return CP_ACCESS_TRAP_EL3
;
4052 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4054 return CP_ACCESS_OK
;
4056 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4059 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4060 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4061 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4062 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4063 .resetvalue
= 0, .writefn
= scr_write
},
4064 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4065 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4066 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4067 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4068 .writefn
= scr_write
},
4069 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4070 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4071 .access
= PL3_RW
, .resetvalue
= 0,
4072 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4074 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4075 .access
= PL3_RW
, .resetvalue
= 0,
4076 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4077 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4078 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4079 .writefn
= vbar_write
, .resetvalue
= 0,
4080 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4081 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4082 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4083 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4084 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4085 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4086 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4088 /* no .writefn needed as this can't cause an ASID change;
4089 * we must provide a .raw_writefn and .resetfn because we handle
4090 * reset and migration for the AArch32 TTBCR(S), which might be
4091 * using mask and base_mask.
4093 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4094 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4095 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4096 .type
= ARM_CP_ALIAS
,
4097 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4099 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4100 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4101 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4102 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4103 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4104 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4105 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4106 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4107 .type
= ARM_CP_ALIAS
,
4108 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4110 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4111 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4112 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4113 .access
= PL3_RW
, .writefn
= vbar_write
,
4114 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4116 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4117 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4118 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4119 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4120 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4121 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4122 .access
= PL3_RW
, .resetvalue
= 0,
4123 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4124 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4125 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4126 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4128 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4129 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4130 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4132 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4133 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4134 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4136 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4137 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4138 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4139 .writefn
= tlbi_aa64_alle3is_write
},
4140 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4141 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4142 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4143 .writefn
= tlbi_aa64_vae3is_write
},
4144 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4145 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4146 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4147 .writefn
= tlbi_aa64_vae3is_write
},
4148 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4149 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4150 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4151 .writefn
= tlbi_aa64_alle3_write
},
4152 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4153 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4154 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4155 .writefn
= tlbi_aa64_vae3_write
},
4156 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4157 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4158 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4159 .writefn
= tlbi_aa64_vae3_write
},
4163 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4166 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4167 * but the AArch32 CTR has its own reginfo struct)
4169 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4170 return CP_ACCESS_TRAP
;
4172 return CP_ACCESS_OK
;
4175 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4178 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4179 * read via a bit in OSLSR_EL1.
4183 if (ri
->state
== ARM_CP_STATE_AA32
) {
4184 oslock
= (value
== 0xC5ACCE55);
4189 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4192 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4193 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4194 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4195 * unlike DBGDRAR it is never accessible from EL0.
4196 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4199 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4200 .access
= PL0_R
, .accessfn
= access_tdra
,
4201 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4202 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4203 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4204 .access
= PL1_R
, .accessfn
= access_tdra
,
4205 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4206 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4207 .access
= PL0_R
, .accessfn
= access_tdra
,
4208 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4209 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4210 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4211 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4212 .access
= PL1_RW
, .accessfn
= access_tda
,
4213 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4215 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4216 * We don't implement the configurable EL0 access.
4218 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4219 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4220 .type
= ARM_CP_ALIAS
,
4221 .access
= PL1_R
, .accessfn
= access_tda
,
4222 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4223 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4224 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4225 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4226 .accessfn
= access_tdosa
,
4227 .writefn
= oslar_write
},
4228 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4229 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4230 .access
= PL1_R
, .resetvalue
= 10,
4231 .accessfn
= access_tdosa
,
4232 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4233 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4234 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4235 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4236 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4237 .type
= ARM_CP_NOP
},
4238 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4239 * implement vector catch debug events yet.
4242 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4243 .access
= PL1_RW
, .accessfn
= access_tda
,
4244 .type
= ARM_CP_NOP
},
4245 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4246 * to save and restore a 32-bit guest's DBGVCR)
4248 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4249 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4250 .access
= PL2_RW
, .accessfn
= access_tda
,
4251 .type
= ARM_CP_NOP
},
4252 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4253 * Channel but Linux may try to access this register. The 32-bit
4254 * alias is DBGDCCINT.
4256 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4257 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4258 .access
= PL1_RW
, .accessfn
= access_tda
,
4259 .type
= ARM_CP_NOP
},
4263 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4264 /* 64 bit access versions of the (dummy) debug registers */
4265 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4266 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4267 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4268 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4272 /* Return the exception level to which SVE-disabled exceptions should
4273 * be taken, or 0 if SVE is enabled.
4275 static int sve_exception_el(CPUARMState
*env
)
4277 #ifndef CONFIG_USER_ONLY
4278 unsigned current_el
= arm_current_el(env
);
4280 /* The CPACR.ZEN controls traps to EL1:
4281 * 0, 2 : trap EL0 and EL1 accesses
4282 * 1 : trap only EL0 accesses
4283 * 3 : trap no accesses
4285 switch (extract32(env
->cp15
.cpacr_el1
, 16, 2)) {
4287 if (current_el
<= 1) {
4288 /* Trap to PL1, which might be EL1 or EL3 */
4289 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
4296 if (current_el
== 0) {
4304 /* Similarly for CPACR.FPEN, after having checked ZEN. */
4305 switch (extract32(env
->cp15
.cpacr_el1
, 20, 2)) {
4307 if (current_el
<= 1) {
4308 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
4315 if (current_el
== 0) {
4323 /* CPTR_EL2. Check both TZ and TFP. */
4325 && (env
->cp15
.cptr_el
[2] & (CPTR_TFP
| CPTR_TZ
))
4326 && !arm_is_secure_below_el3(env
)) {
4330 /* CPTR_EL3. Check both EZ and TFP. */
4331 if (!(env
->cp15
.cptr_el
[3] & CPTR_EZ
)
4332 || (env
->cp15
.cptr_el
[3] & CPTR_TFP
)) {
4339 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4342 /* Bits other than [3:0] are RAZ/WI. */
4343 raw_write(env
, ri
, value
& 0xf);
4346 static const ARMCPRegInfo zcr_el1_reginfo
= {
4347 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
4348 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
4349 .access
= PL1_RW
, .type
= ARM_CP_SVE
| ARM_CP_FPU
,
4350 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
4351 .writefn
= zcr_write
, .raw_writefn
= raw_write
4354 static const ARMCPRegInfo zcr_el2_reginfo
= {
4355 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
4356 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
4357 .access
= PL2_RW
, .type
= ARM_CP_SVE
| ARM_CP_FPU
,
4358 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
4359 .writefn
= zcr_write
, .raw_writefn
= raw_write
4362 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
4363 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
4364 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
4365 .access
= PL2_RW
, .type
= ARM_CP_SVE
| ARM_CP_FPU
,
4366 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
4369 static const ARMCPRegInfo zcr_el3_reginfo
= {
4370 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
4371 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
4372 .access
= PL3_RW
, .type
= ARM_CP_SVE
| ARM_CP_FPU
,
4373 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
4374 .writefn
= zcr_write
, .raw_writefn
= raw_write
4377 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4379 CPUARMState
*env
= &cpu
->env
;
4381 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4382 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4384 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4386 if (env
->cpu_watchpoint
[n
]) {
4387 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4388 env
->cpu_watchpoint
[n
] = NULL
;
4391 if (!extract64(wcr
, 0, 1)) {
4392 /* E bit clear : watchpoint disabled */
4396 switch (extract64(wcr
, 3, 2)) {
4398 /* LSC 00 is reserved and must behave as if the wp is disabled */
4401 flags
|= BP_MEM_READ
;
4404 flags
|= BP_MEM_WRITE
;
4407 flags
|= BP_MEM_ACCESS
;
4411 /* Attempts to use both MASK and BAS fields simultaneously are
4412 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4413 * thus generating a watchpoint for every byte in the masked region.
4415 mask
= extract64(wcr
, 24, 4);
4416 if (mask
== 1 || mask
== 2) {
4417 /* Reserved values of MASK; we must act as if the mask value was
4418 * some non-reserved value, or as if the watchpoint were disabled.
4419 * We choose the latter.
4423 /* Watchpoint covers an aligned area up to 2GB in size */
4425 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4426 * whether the watchpoint fires when the unmasked bits match; we opt
4427 * to generate the exceptions.
4431 /* Watchpoint covers bytes defined by the byte address select bits */
4432 int bas
= extract64(wcr
, 5, 8);
4436 /* This must act as if the watchpoint is disabled */
4440 if (extract64(wvr
, 2, 1)) {
4441 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4442 * ignored, and BAS[3:0] define which bytes to watch.
4446 /* The BAS bits are supposed to be programmed to indicate a contiguous
4447 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4448 * we fire for each byte in the word/doubleword addressed by the WVR.
4449 * We choose to ignore any non-zero bits after the first range of 1s.
4451 basstart
= ctz32(bas
);
4452 len
= cto32(bas
>> basstart
);
4456 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4457 &env
->cpu_watchpoint
[n
]);
4460 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4463 CPUARMState
*env
= &cpu
->env
;
4465 /* Completely clear out existing QEMU watchpoints and our array, to
4466 * avoid possible stale entries following migration load.
4468 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4469 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4471 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4472 hw_watchpoint_update(cpu
, i
);
4476 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4479 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4482 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4483 * register reads and behaves as if values written are sign extended.
4484 * Bits [1:0] are RES0.
4486 value
= sextract64(value
, 0, 49) & ~3ULL;
4488 raw_write(env
, ri
, value
);
4489 hw_watchpoint_update(cpu
, i
);
4492 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4495 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4498 raw_write(env
, ri
, value
);
4499 hw_watchpoint_update(cpu
, i
);
4502 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4504 CPUARMState
*env
= &cpu
->env
;
4505 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4506 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4511 if (env
->cpu_breakpoint
[n
]) {
4512 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4513 env
->cpu_breakpoint
[n
] = NULL
;
4516 if (!extract64(bcr
, 0, 1)) {
4517 /* E bit clear : watchpoint disabled */
4521 bt
= extract64(bcr
, 20, 4);
4524 case 4: /* unlinked address mismatch (reserved if AArch64) */
4525 case 5: /* linked address mismatch (reserved if AArch64) */
4526 qemu_log_mask(LOG_UNIMP
,
4527 "arm: address mismatch breakpoint types not implemented");
4529 case 0: /* unlinked address match */
4530 case 1: /* linked address match */
4532 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4533 * we behave as if the register was sign extended. Bits [1:0] are
4534 * RES0. The BAS field is used to allow setting breakpoints on 16
4535 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4536 * a bp will fire if the addresses covered by the bp and the addresses
4537 * covered by the insn overlap but the insn doesn't start at the
4538 * start of the bp address range. We choose to require the insn and
4539 * the bp to have the same address. The constraints on writing to
4540 * BAS enforced in dbgbcr_write mean we have only four cases:
4541 * 0b0000 => no breakpoint
4542 * 0b0011 => breakpoint on addr
4543 * 0b1100 => breakpoint on addr + 2
4544 * 0b1111 => breakpoint on addr
4545 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4547 int bas
= extract64(bcr
, 5, 4);
4548 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4557 case 2: /* unlinked context ID match */
4558 case 8: /* unlinked VMID match (reserved if no EL2) */
4559 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4560 qemu_log_mask(LOG_UNIMP
,
4561 "arm: unlinked context breakpoint types not implemented");
4563 case 9: /* linked VMID match (reserved if no EL2) */
4564 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4565 case 3: /* linked context ID match */
4567 /* We must generate no events for Linked context matches (unless
4568 * they are linked to by some other bp/wp, which is handled in
4569 * updates for the linking bp/wp). We choose to also generate no events
4570 * for reserved values.
4575 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4578 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4581 CPUARMState
*env
= &cpu
->env
;
4583 /* Completely clear out existing QEMU breakpoints and our array, to
4584 * avoid possible stale entries following migration load.
4586 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4587 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4589 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4590 hw_breakpoint_update(cpu
, i
);
4594 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4597 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4600 raw_write(env
, ri
, value
);
4601 hw_breakpoint_update(cpu
, i
);
4604 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4607 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4610 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4613 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4614 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4616 raw_write(env
, ri
, value
);
4617 hw_breakpoint_update(cpu
, i
);
4620 static void define_debug_regs(ARMCPU
*cpu
)
4622 /* Define v7 and v8 architectural debug registers.
4623 * These are just dummy implementations for now.
4626 int wrps
, brps
, ctx_cmps
;
4627 ARMCPRegInfo dbgdidr
= {
4628 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4629 .access
= PL0_R
, .accessfn
= access_tda
,
4630 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4633 /* Note that all these register fields hold "number of Xs minus 1". */
4634 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4635 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4636 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4638 assert(ctx_cmps
<= brps
);
4640 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4641 * of the debug registers such as number of breakpoints;
4642 * check that if they both exist then they agree.
4644 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4645 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4646 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4647 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4650 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4651 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4653 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4654 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4657 for (i
= 0; i
< brps
+ 1; i
++) {
4658 ARMCPRegInfo dbgregs
[] = {
4659 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4660 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4661 .access
= PL1_RW
, .accessfn
= access_tda
,
4662 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4663 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4665 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4666 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4667 .access
= PL1_RW
, .accessfn
= access_tda
,
4668 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4669 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4673 define_arm_cp_regs(cpu
, dbgregs
);
4676 for (i
= 0; i
< wrps
+ 1; i
++) {
4677 ARMCPRegInfo dbgregs
[] = {
4678 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4679 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4680 .access
= PL1_RW
, .accessfn
= access_tda
,
4681 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4682 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4684 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4685 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4686 .access
= PL1_RW
, .accessfn
= access_tda
,
4687 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4688 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4692 define_arm_cp_regs(cpu
, dbgregs
);
4696 /* We don't know until after realize whether there's a GICv3
4697 * attached, and that is what registers the gicv3 sysregs.
4698 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
4701 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4703 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4704 uint64_t pfr1
= cpu
->id_pfr1
;
4706 if (env
->gicv3state
) {
4712 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4714 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4715 uint64_t pfr0
= cpu
->id_aa64pfr0
;
4717 if (env
->gicv3state
) {
4723 void register_cp_regs_for_features(ARMCPU
*cpu
)
4725 /* Register all the coprocessor registers based on feature bits */
4726 CPUARMState
*env
= &cpu
->env
;
4727 if (arm_feature(env
, ARM_FEATURE_M
)) {
4728 /* M profile has no coprocessor registers */
4732 define_arm_cp_regs(cpu
, cp_reginfo
);
4733 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4734 /* Must go early as it is full of wildcards that may be
4735 * overridden by later definitions.
4737 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4740 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4741 /* The ID registers all have impdef reset values */
4742 ARMCPRegInfo v6_idregs
[] = {
4743 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4744 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4745 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4746 .resetvalue
= cpu
->id_pfr0
},
4747 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
4748 * the value of the GIC field until after we define these regs.
4750 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4751 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4752 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4753 .readfn
= id_pfr1_read
,
4754 .writefn
= arm_cp_write_ignore
},
4755 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4756 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4757 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4758 .resetvalue
= cpu
->id_dfr0
},
4759 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4760 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4761 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4762 .resetvalue
= cpu
->id_afr0
},
4763 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4764 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4765 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4766 .resetvalue
= cpu
->id_mmfr0
},
4767 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4768 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4769 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4770 .resetvalue
= cpu
->id_mmfr1
},
4771 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4772 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4773 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4774 .resetvalue
= cpu
->id_mmfr2
},
4775 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4776 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4777 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4778 .resetvalue
= cpu
->id_mmfr3
},
4779 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4780 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4781 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4782 .resetvalue
= cpu
->id_isar0
},
4783 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4784 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4785 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4786 .resetvalue
= cpu
->id_isar1
},
4787 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4788 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4789 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4790 .resetvalue
= cpu
->id_isar2
},
4791 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4792 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4793 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4794 .resetvalue
= cpu
->id_isar3
},
4795 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4796 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4797 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4798 .resetvalue
= cpu
->id_isar4
},
4799 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4800 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4801 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4802 .resetvalue
= cpu
->id_isar5
},
4803 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4804 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4805 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4806 .resetvalue
= cpu
->id_mmfr4
},
4807 /* 7 is as yet unallocated and must RAZ */
4808 { .name
= "ID_ISAR7_RESERVED", .state
= ARM_CP_STATE_BOTH
,
4809 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4810 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4814 define_arm_cp_regs(cpu
, v6_idregs
);
4815 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4817 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4819 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4820 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4822 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4823 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
4824 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4826 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4827 /* v7 performance monitor control register: same implementor
4828 * field as main ID register, and we implement only the cycle
4831 #ifndef CONFIG_USER_ONLY
4832 ARMCPRegInfo pmcr
= {
4833 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4835 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4836 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4837 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4838 .raw_writefn
= raw_write
,
4840 ARMCPRegInfo pmcr64
= {
4841 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4842 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4843 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4845 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4846 .resetvalue
= cpu
->midr
& 0xff000000,
4847 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4849 define_one_arm_cp_reg(cpu
, &pmcr
);
4850 define_one_arm_cp_reg(cpu
, &pmcr64
);
4852 ARMCPRegInfo clidr
= {
4853 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4854 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4855 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4857 define_one_arm_cp_reg(cpu
, &clidr
);
4858 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4859 define_debug_regs(cpu
);
4861 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4863 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4864 /* AArch64 ID registers, which all have impdef reset values.
4865 * Note that within the ID register ranges the unused slots
4866 * must all RAZ, not UNDEF; future architecture versions may
4867 * define new registers here.
4869 ARMCPRegInfo v8_idregs
[] = {
4870 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
4871 * know the right value for the GIC field until after we
4872 * define these regs.
4874 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4875 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4876 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4877 .readfn
= id_aa64pfr0_read
,
4878 .writefn
= arm_cp_write_ignore
},
4879 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4880 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4881 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4882 .resetvalue
= cpu
->id_aa64pfr1
},
4883 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4884 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
4885 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4887 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4888 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
4889 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4891 { .name
= "ID_AA64PFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4892 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
4893 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4895 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4896 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
4897 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4899 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4900 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
4901 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4903 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4904 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
4905 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4907 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4908 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4909 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4910 .resetvalue
= cpu
->id_aa64dfr0
},
4911 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4912 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4913 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4914 .resetvalue
= cpu
->id_aa64dfr1
},
4915 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4916 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
4917 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4919 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4920 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
4921 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4923 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4924 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4925 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4926 .resetvalue
= cpu
->id_aa64afr0
},
4927 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4928 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4929 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4930 .resetvalue
= cpu
->id_aa64afr1
},
4931 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4932 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
4933 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4935 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4936 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
4937 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4939 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4940 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4941 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4942 .resetvalue
= cpu
->id_aa64isar0
},
4943 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4944 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4945 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4946 .resetvalue
= cpu
->id_aa64isar1
},
4947 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4948 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
4949 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4951 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4952 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
4953 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4955 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4956 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
4957 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4959 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4960 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
4961 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4963 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4964 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
4965 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4967 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4968 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
4969 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4971 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4972 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4973 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4974 .resetvalue
= cpu
->id_aa64mmfr0
},
4975 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4976 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4977 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4978 .resetvalue
= cpu
->id_aa64mmfr1
},
4979 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4980 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
4981 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4983 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4984 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
4985 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4987 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
4989 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4991 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4992 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
4993 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4995 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4996 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
4997 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4999 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5000 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
5001 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5003 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5004 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
5005 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5006 .resetvalue
= cpu
->mvfr0
},
5007 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5008 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
5009 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5010 .resetvalue
= cpu
->mvfr1
},
5011 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
5012 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
5013 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5014 .resetvalue
= cpu
->mvfr2
},
5015 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5016 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
5017 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5019 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5020 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
5021 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5023 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5024 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
5025 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5027 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5028 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
5029 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5031 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5032 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
5033 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5035 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
5036 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
5037 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5038 .resetvalue
= cpu
->pmceid0
},
5039 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
5040 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
5041 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5042 .resetvalue
= cpu
->pmceid0
},
5043 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
5044 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
5045 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5046 .resetvalue
= cpu
->pmceid1
},
5047 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
5048 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
5049 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5050 .resetvalue
= cpu
->pmceid1
},
5053 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
5054 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
5055 !arm_feature(env
, ARM_FEATURE_EL2
)) {
5056 ARMCPRegInfo rvbar
= {
5057 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5058 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5059 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
5061 define_one_arm_cp_reg(cpu
, &rvbar
);
5063 define_arm_cp_regs(cpu
, v8_idregs
);
5064 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
5066 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
5067 uint64_t vmpidr_def
= mpidr_read_val(env
);
5068 ARMCPRegInfo vpidr_regs
[] = {
5069 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
5070 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5071 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5072 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
5073 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
5074 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
5075 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5076 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
5077 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5078 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
5079 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5080 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5081 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
5082 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
5083 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
5084 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5086 .resetvalue
= vmpidr_def
,
5087 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
5090 define_arm_cp_regs(cpu
, vpidr_regs
);
5091 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
5092 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
5093 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
5094 ARMCPRegInfo rvbar
= {
5095 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
5096 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
5097 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
5099 define_one_arm_cp_reg(cpu
, &rvbar
);
5102 /* If EL2 is missing but higher ELs are enabled, we need to
5103 * register the no_el2 reginfos.
5105 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5106 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
5107 * of MIDR_EL1 and MPIDR_EL1.
5109 ARMCPRegInfo vpidr_regs
[] = {
5110 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5111 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5112 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5113 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
5114 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5115 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5116 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5117 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5118 .type
= ARM_CP_NO_RAW
,
5119 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
5122 define_arm_cp_regs(cpu
, vpidr_regs
);
5123 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
5126 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5127 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
5128 ARMCPRegInfo el3_regs
[] = {
5129 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5130 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
5131 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
5132 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5133 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
5135 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5136 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
5137 .resetvalue
= cpu
->reset_sctlr
},
5141 define_arm_cp_regs(cpu
, el3_regs
);
5143 /* The behaviour of NSACR is sufficiently various that we don't
5144 * try to describe it in a single reginfo:
5145 * if EL3 is 64 bit, then trap to EL3 from S EL1,
5146 * reads as constant 0xc00 from NS EL1 and NS EL2
5147 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
5148 * if v7 without EL3, register doesn't exist
5149 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
5151 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5152 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5153 ARMCPRegInfo nsacr
= {
5154 .name
= "NSACR", .type
= ARM_CP_CONST
,
5155 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5156 .access
= PL1_RW
, .accessfn
= nsacr_access
,
5159 define_one_arm_cp_reg(cpu
, &nsacr
);
5161 ARMCPRegInfo nsacr
= {
5163 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5164 .access
= PL3_RW
| PL1_R
,
5166 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
5168 define_one_arm_cp_reg(cpu
, &nsacr
);
5171 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5172 ARMCPRegInfo nsacr
= {
5173 .name
= "NSACR", .type
= ARM_CP_CONST
,
5174 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5178 define_one_arm_cp_reg(cpu
, &nsacr
);
5182 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
5183 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5184 /* PMSAv6 not implemented */
5185 assert(arm_feature(env
, ARM_FEATURE_V7
));
5186 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5187 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
5189 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
5192 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5193 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
5195 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5196 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
5198 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
5199 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
5201 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
5202 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
5204 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
5205 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
5207 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
5208 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
5210 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
5211 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
5213 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
5214 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
5216 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5217 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
5219 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5220 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
5222 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
5223 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
5225 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
5226 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
5228 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5229 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5230 * be read-only (ie write causes UNDEF exception).
5233 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
5234 /* Pre-v8 MIDR space.
5235 * Note that the MIDR isn't a simple constant register because
5236 * of the TI925 behaviour where writes to another register can
5237 * cause the MIDR value to change.
5239 * Unimplemented registers in the c15 0 0 0 space default to
5240 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5241 * and friends override accordingly.
5244 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
5245 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5246 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5247 .readfn
= midr_read
,
5248 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5249 .type
= ARM_CP_OVERRIDE
},
5250 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5252 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5253 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5255 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5256 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5258 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5259 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5261 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5262 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5264 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5265 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5268 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5269 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5270 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5271 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5272 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5273 .readfn
= midr_read
},
5274 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5275 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5276 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5277 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5278 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5279 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5280 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5281 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5282 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5283 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5286 ARMCPRegInfo id_cp_reginfo
[] = {
5287 /* These are common to v8 and pre-v8 */
5289 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5290 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5291 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5292 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5293 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5294 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5295 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5297 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5298 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5301 /* TLBTR is specific to VMSA */
5302 ARMCPRegInfo id_tlbtr_reginfo
= {
5304 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5305 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5307 /* MPUIR is specific to PMSA V6+ */
5308 ARMCPRegInfo id_mpuir_reginfo
= {
5310 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5311 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5312 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5314 ARMCPRegInfo crn0_wi_reginfo
= {
5315 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5316 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5317 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5319 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5320 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5322 /* Register the blanket "writes ignored" value first to cover the
5323 * whole space. Then update the specific ID registers to allow write
5324 * access, so that they ignore writes rather than causing them to
5327 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5328 for (r
= id_pre_v8_midr_cp_reginfo
;
5329 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5332 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5335 id_tlbtr_reginfo
.access
= PL1_RW
;
5336 id_tlbtr_reginfo
.access
= PL1_RW
;
5338 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5339 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5341 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5343 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5344 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
5345 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5346 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5347 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5351 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5352 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5355 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5356 ARMCPRegInfo auxcr_reginfo
[] = {
5357 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5358 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5359 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5360 .resetvalue
= cpu
->reset_auxcr
},
5361 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5362 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5363 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5365 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5366 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5367 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5371 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5374 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5375 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5376 /* 32 bit view is [31:18] 0...0 [43:32]. */
5377 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5378 | extract64(cpu
->reset_cbar
, 32, 12);
5379 ARMCPRegInfo cbar_reginfo
[] = {
5381 .type
= ARM_CP_CONST
,
5382 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5383 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5384 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5385 .type
= ARM_CP_CONST
,
5386 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5387 .access
= PL1_R
, .resetvalue
= cbar32
},
5390 /* We don't implement a r/w 64 bit CBAR currently */
5391 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5392 define_arm_cp_regs(cpu
, cbar_reginfo
);
5394 ARMCPRegInfo cbar
= {
5396 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5397 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5398 .fieldoffset
= offsetof(CPUARMState
,
5399 cp15
.c15_config_base_address
)
5401 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5402 cbar
.access
= PL1_R
;
5403 cbar
.fieldoffset
= 0;
5404 cbar
.type
= ARM_CP_CONST
;
5406 define_one_arm_cp_reg(cpu
, &cbar
);
5410 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5411 ARMCPRegInfo vbar_cp_reginfo
[] = {
5412 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5413 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5414 .access
= PL1_RW
, .writefn
= vbar_write
,
5415 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5416 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5420 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5423 /* Generic registers whose values depend on the implementation */
5425 ARMCPRegInfo sctlr
= {
5426 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5427 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5429 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5430 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5431 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5432 .raw_writefn
= raw_write
,
5434 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5435 /* Normally we would always end the TB on an SCTLR write, but Linux
5436 * arch/arm/mach-pxa/sleep.S expects two instructions following
5437 * an MMU enable to execute from cache. Imitate this behaviour.
5439 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5441 define_one_arm_cp_reg(cpu
, &sctlr
);
5444 if (arm_feature(env
, ARM_FEATURE_SVE
)) {
5445 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
5446 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
5447 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
5449 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
5451 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5452 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
5457 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5459 CPUState
*cs
= CPU(cpu
);
5460 CPUARMState
*env
= &cpu
->env
;
5462 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5463 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5464 aarch64_fpu_gdb_set_reg
,
5465 34, "aarch64-fpu.xml", 0);
5466 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5467 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5468 51, "arm-neon.xml", 0);
5469 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5470 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5471 35, "arm-vfp3.xml", 0);
5472 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5473 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5474 19, "arm-vfp.xml", 0);
5478 /* Sort alphabetically by type name, except for "any". */
5479 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5481 ObjectClass
*class_a
= (ObjectClass
*)a
;
5482 ObjectClass
*class_b
= (ObjectClass
*)b
;
5483 const char *name_a
, *name_b
;
5485 name_a
= object_class_get_name(class_a
);
5486 name_b
= object_class_get_name(class_b
);
5487 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5489 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5492 return strcmp(name_a
, name_b
);
5496 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5498 ObjectClass
*oc
= data
;
5499 CPUListState
*s
= user_data
;
5500 const char *typename
;
5503 typename
= object_class_get_name(oc
);
5504 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5505 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5510 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5514 .cpu_fprintf
= cpu_fprintf
,
5518 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5519 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5520 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5521 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5524 /* The 'host' CPU type is dynamically registered only if KVM is
5525 * enabled, so we have to special-case it here:
5527 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
5531 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5533 ObjectClass
*oc
= data
;
5534 CpuDefinitionInfoList
**cpu_list
= user_data
;
5535 CpuDefinitionInfoList
*entry
;
5536 CpuDefinitionInfo
*info
;
5537 const char *typename
;
5539 typename
= object_class_get_name(oc
);
5540 info
= g_malloc0(sizeof(*info
));
5541 info
->name
= g_strndup(typename
,
5542 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5543 info
->q_typename
= g_strdup(typename
);
5545 entry
= g_malloc0(sizeof(*entry
));
5546 entry
->value
= info
;
5547 entry
->next
= *cpu_list
;
5551 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5553 CpuDefinitionInfoList
*cpu_list
= NULL
;
5556 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5557 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5563 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5564 void *opaque
, int state
, int secstate
,
5565 int crm
, int opc1
, int opc2
)
5567 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5568 * add a single reginfo struct to the hash table.
5570 uint32_t *key
= g_new(uint32_t, 1);
5571 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5572 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5573 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5575 /* Reset the secure state to the specific incoming state. This is
5576 * necessary as the register may have been defined with both states.
5578 r2
->secure
= secstate
;
5580 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5581 /* Register is banked (using both entries in array).
5582 * Overwriting fieldoffset as the array is only used to define
5583 * banked registers but later only fieldoffset is used.
5585 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5588 if (state
== ARM_CP_STATE_AA32
) {
5589 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5590 /* If the register is banked then we don't need to migrate or
5591 * reset the 32-bit instance in certain cases:
5593 * 1) If the register has both 32-bit and 64-bit instances then we
5594 * can count on the 64-bit instance taking care of the
5596 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5597 * taking care of the secure bank. This requires that separate
5598 * 32 and 64-bit definitions are provided.
5600 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5601 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5602 r2
->type
|= ARM_CP_ALIAS
;
5604 } else if ((secstate
!= r
->secure
) && !ns
) {
5605 /* The register is not banked so we only want to allow migration of
5606 * the non-secure instance.
5608 r2
->type
|= ARM_CP_ALIAS
;
5611 if (r
->state
== ARM_CP_STATE_BOTH
) {
5612 /* We assume it is a cp15 register if the .cp field is left unset.
5618 #ifdef HOST_WORDS_BIGENDIAN
5619 if (r2
->fieldoffset
) {
5620 r2
->fieldoffset
+= sizeof(uint32_t);
5625 if (state
== ARM_CP_STATE_AA64
) {
5626 /* To allow abbreviation of ARMCPRegInfo
5627 * definitions, we treat cp == 0 as equivalent to
5628 * the value for "standard guest-visible sysreg".
5629 * STATE_BOTH definitions are also always "standard
5630 * sysreg" in their AArch64 view (the .cp value may
5631 * be non-zero for the benefit of the AArch32 view).
5633 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5634 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5636 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5637 r2
->opc0
, opc1
, opc2
);
5639 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5642 r2
->opaque
= opaque
;
5644 /* reginfo passed to helpers is correct for the actual access,
5645 * and is never ARM_CP_STATE_BOTH:
5648 /* Make sure reginfo passed to helpers for wildcarded regs
5649 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5654 /* By convention, for wildcarded registers only the first
5655 * entry is used for migration; the others are marked as
5656 * ALIAS so we don't try to transfer the register
5657 * multiple times. Special registers (ie NOP/WFI) are
5658 * never migratable and not even raw-accessible.
5660 if ((r
->type
& ARM_CP_SPECIAL
)) {
5661 r2
->type
|= ARM_CP_NO_RAW
;
5663 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5664 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5665 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5666 r2
->type
|= ARM_CP_ALIAS
;
5669 /* Check that raw accesses are either forbidden or handled. Note that
5670 * we can't assert this earlier because the setup of fieldoffset for
5671 * banked registers has to be done first.
5673 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5674 assert(!raw_accessors_invalid(r2
));
5677 /* Overriding of an existing definition must be explicitly
5680 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5681 ARMCPRegInfo
*oldreg
;
5682 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5683 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5684 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5685 "crn=%d crm=%d opc1=%d opc2=%d, "
5686 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5687 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5688 oldreg
->name
, r2
->name
);
5689 g_assert_not_reached();
5692 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5696 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5697 const ARMCPRegInfo
*r
, void *opaque
)
5699 /* Define implementations of coprocessor registers.
5700 * We store these in a hashtable because typically
5701 * there are less than 150 registers in a space which
5702 * is 16*16*16*8*8 = 262144 in size.
5703 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5704 * If a register is defined twice then the second definition is
5705 * used, so this can be used to define some generic registers and
5706 * then override them with implementation specific variations.
5707 * At least one of the original and the second definition should
5708 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5709 * against accidental use.
5711 * The state field defines whether the register is to be
5712 * visible in the AArch32 or AArch64 execution state. If the
5713 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5714 * reginfo structure for the AArch32 view, which sees the lower
5715 * 32 bits of the 64 bit register.
5717 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5718 * be wildcarded. AArch64 registers are always considered to be 64
5719 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5720 * the register, if any.
5722 int crm
, opc1
, opc2
, state
;
5723 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5724 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5725 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5726 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5727 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5728 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5729 /* 64 bit registers have only CRm and Opc1 fields */
5730 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5731 /* op0 only exists in the AArch64 encodings */
5732 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5733 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5734 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5735 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5736 * encodes a minimum access level for the register. We roll this
5737 * runtime check into our general permission check code, so check
5738 * here that the reginfo's specified permissions are strict enough
5739 * to encompass the generic architectural permission check.
5741 if (r
->state
!= ARM_CP_STATE_AA32
) {
5744 case 0: case 1: case 2:
5757 /* unallocated encoding, so not possible */
5765 /* min_EL EL1, secure mode only (we don't check the latter) */
5769 /* broken reginfo with out-of-range opc1 */
5773 /* assert our permissions are not too lax (stricter is fine) */
5774 assert((r
->access
& ~mask
) == 0);
5777 /* Check that the register definition has enough info to handle
5778 * reads and writes if they are permitted.
5780 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5781 if (r
->access
& PL3_R
) {
5782 assert((r
->fieldoffset
||
5783 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5786 if (r
->access
& PL3_W
) {
5787 assert((r
->fieldoffset
||
5788 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5792 /* Bad type field probably means missing sentinel at end of reg list */
5793 assert(cptype_valid(r
->type
));
5794 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5795 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5796 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5797 for (state
= ARM_CP_STATE_AA32
;
5798 state
<= ARM_CP_STATE_AA64
; state
++) {
5799 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5802 if (state
== ARM_CP_STATE_AA32
) {
5803 /* Under AArch32 CP registers can be common
5804 * (same for secure and non-secure world) or banked.
5806 switch (r
->secure
) {
5807 case ARM_CP_SECSTATE_S
:
5808 case ARM_CP_SECSTATE_NS
:
5809 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5810 r
->secure
, crm
, opc1
, opc2
);
5813 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5816 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5822 /* AArch64 registers get mapped to non-secure instance
5824 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5834 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
5835 const ARMCPRegInfo
*regs
, void *opaque
)
5837 /* Define a whole list of registers */
5838 const ARMCPRegInfo
*r
;
5839 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5840 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
5844 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
5846 return g_hash_table_lookup(cpregs
, &encoded_cp
);
5849 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5852 /* Helper coprocessor write function for write-ignore registers */
5855 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5857 /* Helper coprocessor write function for read-as-zero registers */
5861 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
5863 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5866 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
5868 /* Return true if it is not valid for us to switch to
5869 * this CPU mode (ie all the UNPREDICTABLE cases in
5870 * the ARM ARM CPSRWriteByInstr pseudocode).
5873 /* Changes to or from Hyp via MSR and CPS are illegal. */
5874 if (write_type
== CPSRWriteByInstr
&&
5875 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
5876 mode
== ARM_CPU_MODE_HYP
)) {
5881 case ARM_CPU_MODE_USR
:
5883 case ARM_CPU_MODE_SYS
:
5884 case ARM_CPU_MODE_SVC
:
5885 case ARM_CPU_MODE_ABT
:
5886 case ARM_CPU_MODE_UND
:
5887 case ARM_CPU_MODE_IRQ
:
5888 case ARM_CPU_MODE_FIQ
:
5889 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5890 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5892 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5893 * and CPS are treated as illegal mode changes.
5895 if (write_type
== CPSRWriteByInstr
&&
5896 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
5897 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
5898 !arm_is_secure_below_el3(env
)) {
5902 case ARM_CPU_MODE_HYP
:
5903 return !arm_feature(env
, ARM_FEATURE_EL2
)
5904 || arm_current_el(env
) < 2 || arm_is_secure(env
);
5905 case ARM_CPU_MODE_MON
:
5906 return arm_current_el(env
) < 3;
5912 uint32_t cpsr_read(CPUARMState
*env
)
5915 ZF
= (env
->ZF
== 0);
5916 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
5917 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
5918 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
5919 | ((env
->condexec_bits
& 0xfc) << 8)
5920 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
5923 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
5924 CPSRWriteType write_type
)
5926 uint32_t changed_daif
;
5928 if (mask
& CPSR_NZCV
) {
5929 env
->ZF
= (~val
) & CPSR_Z
;
5931 env
->CF
= (val
>> 29) & 1;
5932 env
->VF
= (val
<< 3) & 0x80000000;
5935 env
->QF
= ((val
& CPSR_Q
) != 0);
5937 env
->thumb
= ((val
& CPSR_T
) != 0);
5938 if (mask
& CPSR_IT_0_1
) {
5939 env
->condexec_bits
&= ~3;
5940 env
->condexec_bits
|= (val
>> 25) & 3;
5942 if (mask
& CPSR_IT_2_7
) {
5943 env
->condexec_bits
&= 3;
5944 env
->condexec_bits
|= (val
>> 8) & 0xfc;
5946 if (mask
& CPSR_GE
) {
5947 env
->GE
= (val
>> 16) & 0xf;
5950 /* In a V7 implementation that includes the security extensions but does
5951 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5952 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5953 * bits respectively.
5955 * In a V8 implementation, it is permitted for privileged software to
5956 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5958 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
5959 arm_feature(env
, ARM_FEATURE_EL3
) &&
5960 !arm_feature(env
, ARM_FEATURE_EL2
) &&
5961 !arm_is_secure(env
)) {
5963 changed_daif
= (env
->daif
^ val
) & mask
;
5965 if (changed_daif
& CPSR_A
) {
5966 /* Check to see if we are allowed to change the masking of async
5967 * abort exceptions from a non-secure state.
5969 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
5970 qemu_log_mask(LOG_GUEST_ERROR
,
5971 "Ignoring attempt to switch CPSR_A flag from "
5972 "non-secure world with SCR.AW bit clear\n");
5977 if (changed_daif
& CPSR_F
) {
5978 /* Check to see if we are allowed to change the masking of FIQ
5979 * exceptions from a non-secure state.
5981 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
5982 qemu_log_mask(LOG_GUEST_ERROR
,
5983 "Ignoring attempt to switch CPSR_F flag from "
5984 "non-secure world with SCR.FW bit clear\n");
5988 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5989 * If this bit is set software is not allowed to mask
5990 * FIQs, but is allowed to set CPSR_F to 0.
5992 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
5994 qemu_log_mask(LOG_GUEST_ERROR
,
5995 "Ignoring attempt to enable CPSR_F flag "
5996 "(non-maskable FIQ [NMFI] support enabled)\n");
6002 env
->daif
&= ~(CPSR_AIF
& mask
);
6003 env
->daif
|= val
& CPSR_AIF
& mask
;
6005 if (write_type
!= CPSRWriteRaw
&&
6006 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
6007 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
6008 /* Note that we can only get here in USR mode if this is a
6009 * gdb stub write; for this case we follow the architectural
6010 * behaviour for guest writes in USR mode of ignoring an attempt
6011 * to switch mode. (Those are caught by translate.c for writes
6012 * triggered by guest instructions.)
6015 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
6016 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
6017 * v7, and has defined behaviour in v8:
6018 * + leave CPSR.M untouched
6019 * + allow changes to the other CPSR fields
6021 * For user changes via the GDB stub, we don't set PSTATE.IL,
6022 * as this would be unnecessarily harsh for a user error.
6025 if (write_type
!= CPSRWriteByGDBStub
&&
6026 arm_feature(env
, ARM_FEATURE_V8
)) {
6031 switch_mode(env
, val
& CPSR_M
);
6034 mask
&= ~CACHED_CPSR_BITS
;
6035 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
6038 /* Sign/zero extend */
6039 uint32_t HELPER(sxtb16
)(uint32_t x
)
6042 res
= (uint16_t)(int8_t)x
;
6043 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
6047 uint32_t HELPER(uxtb16
)(uint32_t x
)
6050 res
= (uint16_t)(uint8_t)x
;
6051 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
6055 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
6059 if (num
== INT_MIN
&& den
== -1)
6064 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
6071 uint32_t HELPER(rbit
)(uint32_t x
)
6076 #if defined(CONFIG_USER_ONLY)
6078 /* These should probably raise undefined insn exceptions. */
6079 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
6081 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6083 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
6086 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
6088 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6090 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
6094 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6096 /* translate.c should never generate calls here in user-only mode */
6097 g_assert_not_reached();
6100 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6102 /* translate.c should never generate calls here in user-only mode */
6103 g_assert_not_reached();
6106 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
6108 /* The TT instructions can be used by unprivileged code, but in
6109 * user-only emulation we don't have the MPU.
6110 * Luckily since we know we are NonSecure unprivileged (and that in
6111 * turn means that the A flag wasn't specified), all the bits in the
6112 * register must be zero:
6113 * IREGION: 0 because IRVALID is 0
6114 * IRVALID: 0 because NS
6116 * NSRW: 0 because NS
6118 * RW: 0 because unpriv and A flag not set
6119 * R: 0 because unpriv and A flag not set
6120 * SRVALID: 0 because NS
6121 * MRVALID: 0 because unpriv and A flag not set
6122 * SREGION: 0 becaus SRVALID is 0
6123 * MREGION: 0 because MRVALID is 0
6128 void switch_mode(CPUARMState
*env
, int mode
)
6130 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6132 if (mode
!= ARM_CPU_MODE_USR
) {
6133 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
6137 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6138 uint32_t cur_el
, bool secure
)
6143 void aarch64_sync_64_to_32(CPUARMState
*env
)
6145 g_assert_not_reached();
6150 void switch_mode(CPUARMState
*env
, int mode
)
6155 old_mode
= env
->uncached_cpsr
& CPSR_M
;
6156 if (mode
== old_mode
)
6159 if (old_mode
== ARM_CPU_MODE_FIQ
) {
6160 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6161 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
6162 } else if (mode
== ARM_CPU_MODE_FIQ
) {
6163 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6164 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
6167 i
= bank_number(old_mode
);
6168 env
->banked_r13
[i
] = env
->regs
[13];
6169 env
->banked_r14
[i
] = env
->regs
[14];
6170 env
->banked_spsr
[i
] = env
->spsr
;
6172 i
= bank_number(mode
);
6173 env
->regs
[13] = env
->banked_r13
[i
];
6174 env
->regs
[14] = env
->banked_r14
[i
];
6175 env
->spsr
= env
->banked_spsr
[i
];
6178 /* Physical Interrupt Target EL Lookup Table
6180 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
6182 * The below multi-dimensional table is used for looking up the target
6183 * exception level given numerous condition criteria. Specifically, the
6184 * target EL is based on SCR and HCR routing controls as well as the
6185 * currently executing EL and secure state.
6188 * target_el_table[2][2][2][2][2][4]
6189 * | | | | | +--- Current EL
6190 * | | | | +------ Non-secure(0)/Secure(1)
6191 * | | | +--------- HCR mask override
6192 * | | +------------ SCR exec state control
6193 * | +--------------- SCR mask override
6194 * +------------------ 32-bit(0)/64-bit(1) EL3
6196 * The table values are as such:
6200 * The ARM ARM target EL table includes entries indicating that an "exception
6201 * is not taken". The two cases where this is applicable are:
6202 * 1) An exception is taken from EL3 but the SCR does not have the exception
6204 * 2) An exception is taken from EL2 but the HCR does not have the exception
6206 * In these two cases, the below table contain a target of EL1. This value is
6207 * returned as it is expected that the consumer of the table data will check
6208 * for "target EL >= current EL" to ensure the exception is not taken.
6212 * BIT IRQ IMO Non-secure Secure
6213 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
6215 static const int8_t target_el_table
[2][2][2][2][2][4] = {
6216 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6217 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
6218 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6219 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
6220 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6221 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
6222 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6223 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
6224 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
6225 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
6226 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
6227 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
6228 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6229 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
6230 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6231 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
6235 * Determine the target EL for physical exceptions
6237 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6238 uint32_t cur_el
, bool secure
)
6240 CPUARMState
*env
= cs
->env_ptr
;
6245 /* Is the highest EL AArch64? */
6246 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
6248 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6249 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
6251 /* Either EL2 is the highest EL (and so the EL2 register width
6252 * is given by is64); or there is no EL2 or EL3, in which case
6253 * the value of 'rw' does not affect the table lookup anyway.
6260 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
6261 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
6264 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
6265 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
6268 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
6269 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
6273 /* If HCR.TGE is set then HCR is treated as being 1 */
6274 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
6276 /* Perform a table-lookup for the target EL given the current state */
6277 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
6279 assert(target_el
> 0);
6284 static bool v7m_stack_write(ARMCPU
*cpu
, uint32_t addr
, uint32_t value
,
6285 ARMMMUIdx mmu_idx
, bool ignfault
)
6287 CPUState
*cs
= CPU(cpu
);
6288 CPUARMState
*env
= &cpu
->env
;
6289 MemTxAttrs attrs
= {};
6291 target_ulong page_size
;
6295 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
6299 if (get_phys_addr(env
, addr
, MMU_DATA_STORE
, mmu_idx
, &physaddr
,
6300 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
6301 /* MPU/SAU lookup failed */
6302 if (fi
.type
== ARMFault_QEMU_SFault
) {
6303 qemu_log_mask(CPU_LOG_INT
,
6304 "...SecureFault with SFSR.AUVIOL during stacking\n");
6305 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
6306 env
->v7m
.sfar
= addr
;
6307 exc
= ARMV7M_EXCP_SECURE
;
6310 qemu_log_mask(CPU_LOG_INT
, "...MemManageFault with CFSR.MSTKERR\n");
6311 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MSTKERR_MASK
;
6312 exc
= ARMV7M_EXCP_MEM
;
6313 exc_secure
= secure
;
6317 address_space_stl_le(arm_addressspace(cs
, attrs
), physaddr
, value
,
6319 if (txres
!= MEMTX_OK
) {
6320 /* BusFault trying to write the data */
6321 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.STKERR\n");
6322 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_STKERR_MASK
;
6323 exc
= ARMV7M_EXCP_BUS
;
6330 /* By pending the exception at this point we are making
6331 * the IMPDEF choice "overridden exceptions pended" (see the
6332 * MergeExcInfo() pseudocode). The other choice would be to not
6333 * pend them now and then make a choice about which to throw away
6334 * later if we have two derived exceptions.
6335 * The only case when we must not pend the exception but instead
6336 * throw it away is if we are doing the push of the callee registers
6337 * and we've already generated a derived exception. Even in this
6338 * case we will still update the fault status registers.
6341 armv7m_nvic_set_pending_derived(env
->nvic
, exc
, exc_secure
);
6346 static bool v7m_stack_read(ARMCPU
*cpu
, uint32_t *dest
, uint32_t addr
,
6349 CPUState
*cs
= CPU(cpu
);
6350 CPUARMState
*env
= &cpu
->env
;
6351 MemTxAttrs attrs
= {};
6353 target_ulong page_size
;
6357 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
6362 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
6363 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
6364 /* MPU/SAU lookup failed */
6365 if (fi
.type
== ARMFault_QEMU_SFault
) {
6366 qemu_log_mask(CPU_LOG_INT
,
6367 "...SecureFault with SFSR.AUVIOL during unstack\n");
6368 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
6369 env
->v7m
.sfar
= addr
;
6370 exc
= ARMV7M_EXCP_SECURE
;
6373 qemu_log_mask(CPU_LOG_INT
,
6374 "...MemManageFault with CFSR.MUNSTKERR\n");
6375 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MUNSTKERR_MASK
;
6376 exc
= ARMV7M_EXCP_MEM
;
6377 exc_secure
= secure
;
6382 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
6384 if (txres
!= MEMTX_OK
) {
6385 /* BusFault trying to read the data */
6386 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.UNSTKERR\n");
6387 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_UNSTKERR_MASK
;
6388 exc
= ARMV7M_EXCP_BUS
;
6397 /* By pending the exception at this point we are making
6398 * the IMPDEF choice "overridden exceptions pended" (see the
6399 * MergeExcInfo() pseudocode). The other choice would be to not
6400 * pend them now and then make a choice about which to throw away
6401 * later if we have two derived exceptions.
6403 armv7m_nvic_set_pending(env
->nvic
, exc
, exc_secure
);
6407 /* Return true if we're using the process stack pointer (not the MSP) */
6408 static bool v7m_using_psp(CPUARMState
*env
)
6410 /* Handler mode always uses the main stack; for thread mode
6411 * the CONTROL.SPSEL bit determines the answer.
6412 * Note that in v7M it is not possible to be in Handler mode with
6413 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
6415 return !arm_v7m_is_handler_mode(env
) &&
6416 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
6419 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6420 * This may change the current stack pointer between Main and Process
6421 * stack pointers if it is done for the CONTROL register for the current
6424 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
6428 bool old_is_psp
= v7m_using_psp(env
);
6430 env
->v7m
.control
[secstate
] =
6431 deposit32(env
->v7m
.control
[secstate
],
6432 R_V7M_CONTROL_SPSEL_SHIFT
,
6433 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6435 if (secstate
== env
->v7m
.secure
) {
6436 bool new_is_psp
= v7m_using_psp(env
);
6439 if (old_is_psp
!= new_is_psp
) {
6440 tmp
= env
->v7m
.other_sp
;
6441 env
->v7m
.other_sp
= env
->regs
[13];
6442 env
->regs
[13] = tmp
;
6447 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6448 * stack pointer between Main and Process stack pointers.
6450 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
6452 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
6455 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
6457 /* Write a new value to v7m.exception, thus transitioning into or out
6458 * of Handler mode; this may result in a change of active stack pointer.
6460 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
6463 env
->v7m
.exception
= new_exc
;
6465 new_is_psp
= v7m_using_psp(env
);
6467 if (old_is_psp
!= new_is_psp
) {
6468 tmp
= env
->v7m
.other_sp
;
6469 env
->v7m
.other_sp
= env
->regs
[13];
6470 env
->regs
[13] = tmp
;
6474 /* Switch M profile security state between NS and S */
6475 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
6477 uint32_t new_ss_msp
, new_ss_psp
;
6479 if (env
->v7m
.secure
== new_secstate
) {
6483 /* All the banked state is accessed by looking at env->v7m.secure
6484 * except for the stack pointer; rearrange the SP appropriately.
6486 new_ss_msp
= env
->v7m
.other_ss_msp
;
6487 new_ss_psp
= env
->v7m
.other_ss_psp
;
6489 if (v7m_using_psp(env
)) {
6490 env
->v7m
.other_ss_psp
= env
->regs
[13];
6491 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
6493 env
->v7m
.other_ss_msp
= env
->regs
[13];
6494 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
6497 env
->v7m
.secure
= new_secstate
;
6499 if (v7m_using_psp(env
)) {
6500 env
->regs
[13] = new_ss_psp
;
6501 env
->v7m
.other_sp
= new_ss_msp
;
6503 env
->regs
[13] = new_ss_msp
;
6504 env
->v7m
.other_sp
= new_ss_psp
;
6508 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6511 * - if the return value is a magic value, do exception return (like BX)
6512 * - otherwise bit 0 of the return value is the target security state
6516 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6517 /* Covers FNC_RETURN and EXC_RETURN magic */
6518 min_magic
= FNC_RETURN_MIN_MAGIC
;
6520 /* EXC_RETURN magic only */
6521 min_magic
= EXC_RETURN_MIN_MAGIC
;
6524 if (dest
>= min_magic
) {
6525 /* This is an exception return magic value; put it where
6526 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6527 * Note that if we ever add gen_ss_advance() singlestep support to
6528 * M profile this should count as an "instruction execution complete"
6529 * event (compare gen_bx_excret_final_code()).
6531 env
->regs
[15] = dest
& ~1;
6532 env
->thumb
= dest
& 1;
6533 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
6537 /* translate.c should have made BXNS UNDEF unless we're secure */
6538 assert(env
->v7m
.secure
);
6540 switch_v7m_security_state(env
, dest
& 1);
6542 env
->regs
[15] = dest
& ~1;
6545 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6547 /* Handle v7M BLXNS:
6548 * - bit 0 of the destination address is the target security state
6551 /* At this point regs[15] is the address just after the BLXNS */
6552 uint32_t nextinst
= env
->regs
[15] | 1;
6553 uint32_t sp
= env
->regs
[13] - 8;
6556 /* translate.c will have made BLXNS UNDEF unless we're secure */
6557 assert(env
->v7m
.secure
);
6560 /* target is Secure, so this is just a normal BLX,
6561 * except that the low bit doesn't indicate Thumb/not.
6563 env
->regs
[14] = nextinst
;
6565 env
->regs
[15] = dest
& ~1;
6569 /* Target is non-secure: first push a stack frame */
6570 if (!QEMU_IS_ALIGNED(sp
, 8)) {
6571 qemu_log_mask(LOG_GUEST_ERROR
,
6572 "BLXNS with misaligned SP is UNPREDICTABLE\n");
6575 saved_psr
= env
->v7m
.exception
;
6576 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
6577 saved_psr
|= XPSR_SFPA
;
6580 /* Note that these stores can throw exceptions on MPU faults */
6581 cpu_stl_data(env
, sp
, nextinst
);
6582 cpu_stl_data(env
, sp
+ 4, saved_psr
);
6585 env
->regs
[14] = 0xfeffffff;
6586 if (arm_v7m_is_handler_mode(env
)) {
6587 /* Write a dummy value to IPSR, to avoid leaking the current secure
6588 * exception number to non-secure code. This is guaranteed not
6589 * to cause write_v7m_exception() to actually change stacks.
6591 write_v7m_exception(env
, 1);
6593 switch_v7m_security_state(env
, 0);
6595 env
->regs
[15] = dest
;
6598 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
6601 /* Return a pointer to the location where we currently store the
6602 * stack pointer for the requested security state and thread mode.
6603 * This pointer will become invalid if the CPU state is updated
6604 * such that the stack pointers are switched around (eg changing
6605 * the SPSEL control bit).
6606 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6607 * Unlike that pseudocode, we require the caller to pass us in the
6608 * SPSEL control bit value; this is because we also use this
6609 * function in handling of pushing of the callee-saves registers
6610 * part of the v8M stack frame (pseudocode PushCalleeStack()),
6611 * and in the tailchain codepath the SPSEL bit comes from the exception
6612 * return magic LR value from the previous exception. The pseudocode
6613 * opencodes the stack-selection in PushCalleeStack(), but we prefer
6614 * to make this utility function generic enough to do the job.
6616 bool want_psp
= threadmode
&& spsel
;
6618 if (secure
== env
->v7m
.secure
) {
6619 if (want_psp
== v7m_using_psp(env
)) {
6620 return &env
->regs
[13];
6622 return &env
->v7m
.other_sp
;
6626 return &env
->v7m
.other_ss_psp
;
6628 return &env
->v7m
.other_ss_msp
;
6633 static bool arm_v7m_load_vector(ARMCPU
*cpu
, int exc
, bool targets_secure
,
6636 CPUState
*cs
= CPU(cpu
);
6637 CPUARMState
*env
= &cpu
->env
;
6639 uint32_t addr
= env
->v7m
.vecbase
[targets_secure
] + exc
* 4;
6640 uint32_t vector_entry
;
6641 MemTxAttrs attrs
= {};
6645 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targets_secure
, true);
6647 /* We don't do a get_phys_addr() here because the rules for vector
6648 * loads are special: they always use the default memory map, and
6649 * the default memory map permits reads from all addresses.
6650 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
6651 * that we want this special case which would always say "yes",
6652 * we just do the SAU lookup here followed by a direct physical load.
6654 attrs
.secure
= targets_secure
;
6657 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6658 V8M_SAttributes sattrs
= {};
6660 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
6662 attrs
.secure
= false;
6663 } else if (!targets_secure
) {
6664 /* NS access to S memory */
6669 vector_entry
= address_space_ldl(arm_addressspace(cs
, attrs
), addr
,
6671 if (result
!= MEMTX_OK
) {
6674 *pvec
= vector_entry
;
6678 /* All vector table fetch fails are reported as HardFault, with
6679 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
6680 * technically the underlying exception is a MemManage or BusFault
6681 * that is escalated to HardFault.) This is a terminal exception,
6682 * so we will either take the HardFault immediately or else enter
6683 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
6685 exc_secure
= targets_secure
||
6686 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
6687 env
->v7m
.hfsr
|= R_V7M_HFSR_VECTTBL_MASK
| R_V7M_HFSR_FORCED_MASK
;
6688 armv7m_nvic_set_pending_derived(env
->nvic
, ARMV7M_EXCP_HARD
, exc_secure
);
6692 static bool v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
6695 /* For v8M, push the callee-saves register part of the stack frame.
6696 * Compare the v8M pseudocode PushCalleeStack().
6697 * In the tailchaining case this may not be the current stack.
6699 CPUARMState
*env
= &cpu
->env
;
6700 uint32_t *frame_sp_p
;
6706 bool mode
= lr
& R_V7M_EXCRET_MODE_MASK
;
6707 bool priv
= !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_NPRIV_MASK
) ||
6710 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, M_REG_S
, priv
);
6711 frame_sp_p
= get_v7m_sp_ptr(env
, M_REG_S
, mode
,
6712 lr
& R_V7M_EXCRET_SPSEL_MASK
);
6714 mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
6715 frame_sp_p
= &env
->regs
[13];
6718 frameptr
= *frame_sp_p
- 0x28;
6720 /* Write as much of the stack frame as we can. A write failure may
6721 * cause us to pend a derived exception.
6724 v7m_stack_write(cpu
, frameptr
, 0xfefa125b, mmu_idx
, ignore_faults
) &&
6725 v7m_stack_write(cpu
, frameptr
+ 0x8, env
->regs
[4], mmu_idx
,
6727 v7m_stack_write(cpu
, frameptr
+ 0xc, env
->regs
[5], mmu_idx
,
6729 v7m_stack_write(cpu
, frameptr
+ 0x10, env
->regs
[6], mmu_idx
,
6731 v7m_stack_write(cpu
, frameptr
+ 0x14, env
->regs
[7], mmu_idx
,
6733 v7m_stack_write(cpu
, frameptr
+ 0x18, env
->regs
[8], mmu_idx
,
6735 v7m_stack_write(cpu
, frameptr
+ 0x1c, env
->regs
[9], mmu_idx
,
6737 v7m_stack_write(cpu
, frameptr
+ 0x20, env
->regs
[10], mmu_idx
,
6739 v7m_stack_write(cpu
, frameptr
+ 0x24, env
->regs
[11], mmu_idx
,
6742 /* Update SP regardless of whether any of the stack accesses failed.
6743 * When we implement v8M stack limit checking then this attempt to
6744 * update SP might also fail and result in a derived exception.
6746 *frame_sp_p
= frameptr
;
6751 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
6752 bool ignore_stackfaults
)
6754 /* Do the "take the exception" parts of exception entry,
6755 * but not the pushing of state to the stack. This is
6756 * similar to the pseudocode ExceptionTaken() function.
6758 CPUARMState
*env
= &cpu
->env
;
6760 bool targets_secure
;
6762 bool push_failed
= false;
6764 armv7m_nvic_get_pending_irq_info(env
->nvic
, &exc
, &targets_secure
);
6766 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6767 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6768 (lr
& R_V7M_EXCRET_S_MASK
)) {
6769 /* The background code (the owner of the registers in the
6770 * exception frame) is Secure. This means it may either already
6771 * have or now needs to push callee-saves registers.
6773 if (targets_secure
) {
6774 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
6775 /* We took an exception from Secure to NonSecure
6776 * (which means the callee-saved registers got stacked)
6777 * and are now tailchaining to a Secure exception.
6778 * Clear DCRS so eventual return from this Secure
6779 * exception unstacks the callee-saved registers.
6781 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
6784 /* We're going to a non-secure exception; push the
6785 * callee-saves registers to the stack now, if they're
6786 * not already saved.
6788 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
6789 !(dotailchain
&& (lr
& R_V7M_EXCRET_ES_MASK
))) {
6790 push_failed
= v7m_push_callee_stack(cpu
, lr
, dotailchain
,
6791 ignore_stackfaults
);
6793 lr
|= R_V7M_EXCRET_DCRS_MASK
;
6797 lr
&= ~R_V7M_EXCRET_ES_MASK
;
6798 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6799 lr
|= R_V7M_EXCRET_ES_MASK
;
6801 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
6802 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
6803 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
6806 /* Clear registers if necessary to prevent non-secure exception
6807 * code being able to see register values from secure code.
6808 * Where register values become architecturally UNKNOWN we leave
6809 * them with their previous values.
6811 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6812 if (!targets_secure
) {
6813 /* Always clear the caller-saved registers (they have been
6814 * pushed to the stack earlier in v7m_push_stack()).
6815 * Clear callee-saved registers if the background code is
6816 * Secure (in which case these regs were saved in
6817 * v7m_push_callee_stack()).
6821 for (i
= 0; i
< 13; i
++) {
6822 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
6823 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
6828 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
6833 if (push_failed
&& !ignore_stackfaults
) {
6834 /* Derived exception on callee-saves register stacking:
6835 * we might now want to take a different exception which
6836 * targets a different security state, so try again from the top.
6838 v7m_exception_taken(cpu
, lr
, true, true);
6842 if (!arm_v7m_load_vector(cpu
, exc
, targets_secure
, &addr
)) {
6843 /* Vector load failed: derived exception */
6844 v7m_exception_taken(cpu
, lr
, true, true);
6848 /* Now we've done everything that might cause a derived exception
6849 * we can go ahead and activate whichever exception we're going to
6850 * take (which might now be the derived exception).
6852 armv7m_nvic_acknowledge_irq(env
->nvic
);
6854 /* Switch to target security state -- must do this before writing SPSEL */
6855 switch_v7m_security_state(env
, targets_secure
);
6856 write_v7m_control_spsel(env
, 0);
6857 arm_clear_exclusive(env
);
6859 env
->condexec_bits
= 0;
6861 env
->regs
[15] = addr
& 0xfffffffe;
6862 env
->thumb
= addr
& 1;
6865 static bool v7m_push_stack(ARMCPU
*cpu
)
6867 /* Do the "set up stack frame" part of exception entry,
6868 * similar to pseudocode PushStack().
6869 * Return true if we generate a derived exception (and so
6870 * should ignore further stack faults trying to process
6871 * that derived exception.)
6874 CPUARMState
*env
= &cpu
->env
;
6875 uint32_t xpsr
= xpsr_read(env
);
6876 uint32_t frameptr
= env
->regs
[13];
6877 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
6879 /* Align stack pointer if the guest wants that */
6880 if ((frameptr
& 4) &&
6881 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
6883 xpsr
|= XPSR_SPREALIGN
;
6888 /* Write as much of the stack frame as we can. If we fail a stack
6889 * write this will result in a derived exception being pended
6890 * (which may be taken in preference to the one we started with
6891 * if it has higher priority).
6894 v7m_stack_write(cpu
, frameptr
, env
->regs
[0], mmu_idx
, false) &&
6895 v7m_stack_write(cpu
, frameptr
+ 4, env
->regs
[1], mmu_idx
, false) &&
6896 v7m_stack_write(cpu
, frameptr
+ 8, env
->regs
[2], mmu_idx
, false) &&
6897 v7m_stack_write(cpu
, frameptr
+ 12, env
->regs
[3], mmu_idx
, false) &&
6898 v7m_stack_write(cpu
, frameptr
+ 16, env
->regs
[12], mmu_idx
, false) &&
6899 v7m_stack_write(cpu
, frameptr
+ 20, env
->regs
[14], mmu_idx
, false) &&
6900 v7m_stack_write(cpu
, frameptr
+ 24, env
->regs
[15], mmu_idx
, false) &&
6901 v7m_stack_write(cpu
, frameptr
+ 28, xpsr
, mmu_idx
, false);
6903 /* Update SP regardless of whether any of the stack accesses failed.
6904 * When we implement v8M stack limit checking then this attempt to
6905 * update SP might also fail and result in a derived exception.
6907 env
->regs
[13] = frameptr
;
6912 static void do_v7m_exception_exit(ARMCPU
*cpu
)
6914 CPUARMState
*env
= &cpu
->env
;
6915 CPUState
*cs
= CPU(cpu
);
6918 bool ufault
= false;
6919 bool sfault
= false;
6920 bool return_to_sp_process
;
6921 bool return_to_handler
;
6922 bool rettobase
= false;
6923 bool exc_secure
= false;
6924 bool return_to_secure
;
6926 /* If we're not in Handler mode then jumps to magic exception-exit
6927 * addresses don't have magic behaviour. However for the v8M
6928 * security extensions the magic secure-function-return has to
6929 * work in thread mode too, so to avoid doing an extra check in
6930 * the generated code we allow exception-exit magic to also cause the
6931 * internal exception and bring us here in thread mode. Correct code
6932 * will never try to do this (the following insn fetch will always
6933 * fault) so we the overhead of having taken an unnecessary exception
6936 if (!arm_v7m_is_handler_mode(env
)) {
6940 /* In the spec pseudocode ExceptionReturn() is called directly
6941 * from BXWritePC() and gets the full target PC value including
6942 * bit zero. In QEMU's implementation we treat it as a normal
6943 * jump-to-register (which is then caught later on), and so split
6944 * the target value up between env->regs[15] and env->thumb in
6945 * gen_bx(). Reconstitute it.
6947 excret
= env
->regs
[15];
6952 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
6953 " previous exception %d\n",
6954 excret
, env
->v7m
.exception
);
6956 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
6957 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
6958 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
6962 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6963 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
6964 * we pick which FAULTMASK to clear.
6966 if (!env
->v7m
.secure
&&
6967 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
6968 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
6970 /* For all other purposes, treat ES as 0 (R_HXSR) */
6971 excret
&= ~R_V7M_EXCRET_ES_MASK
;
6975 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
6976 /* Auto-clear FAULTMASK on return from other than NMI.
6977 * If the security extension is implemented then this only
6978 * happens if the raw execution priority is >= 0; the
6979 * value of the ES bit in the exception return value indicates
6980 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
6982 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6983 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
6984 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
6985 env
->v7m
.faultmask
[exc_secure
] = 0;
6988 env
->v7m
.faultmask
[M_REG_NS
] = 0;
6992 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
6995 /* attempt to exit an exception that isn't active */
6999 /* still an irq active now */
7002 /* we returned to base exception level, no nesting.
7003 * (In the pseudocode this is written using "NestedActivation != 1"
7004 * where we have 'rettobase == false'.)
7009 g_assert_not_reached();
7012 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
7013 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
7014 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
7015 (excret
& R_V7M_EXCRET_S_MASK
);
7017 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7018 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7019 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
7020 * we choose to take the UsageFault.
7022 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
7023 (excret
& R_V7M_EXCRET_ES_MASK
) ||
7024 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
7028 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
7032 /* For v7M we only recognize certain combinations of the low bits */
7033 switch (excret
& 0xf) {
7034 case 1: /* Return to Handler */
7036 case 13: /* Return to Thread using Process stack */
7037 case 9: /* Return to Thread using Main stack */
7038 /* We only need to check NONBASETHRDENA for v7M, because in
7039 * v8M this bit does not exist (it is RES1).
7042 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
7043 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
7053 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
7054 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7055 v7m_exception_taken(cpu
, excret
, true, false);
7056 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
7057 "stackframe: failed EXC_RETURN.ES validity check\n");
7062 /* Bad exception return: instead of popping the exception
7063 * stack, directly take a usage fault on the current stack.
7065 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7066 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7067 v7m_exception_taken(cpu
, excret
, true, false);
7068 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
7069 "stackframe: failed exception return integrity check\n");
7073 /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
7074 * Handler mode (and will be until we write the new XPSR.Interrupt
7075 * field) this does not switch around the current stack pointer.
7077 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
7079 switch_v7m_security_state(env
, return_to_secure
);
7082 /* The stack pointer we should be reading the exception frame from
7083 * depends on bits in the magic exception return type value (and
7084 * for v8M isn't necessarily the stack pointer we will eventually
7085 * end up resuming execution with). Get a pointer to the location
7086 * in the CPU state struct where the SP we need is currently being
7087 * stored; we will use and modify it in place.
7088 * We use this limited C variable scope so we don't accidentally
7089 * use 'frame_sp_p' after we do something that makes it invalid.
7091 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
7094 return_to_sp_process
);
7095 uint32_t frameptr
= *frame_sp_p
;
7099 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, return_to_secure
,
7100 !return_to_handler
);
7102 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
7103 arm_feature(env
, ARM_FEATURE_V8
)) {
7104 qemu_log_mask(LOG_GUEST_ERROR
,
7105 "M profile exception return with non-8-aligned SP "
7106 "for destination state is UNPREDICTABLE\n");
7109 /* Do we need to pop callee-saved registers? */
7110 if (return_to_secure
&&
7111 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
7112 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
7113 uint32_t expected_sig
= 0xfefa125b;
7114 uint32_t actual_sig
= ldl_phys(cs
->as
, frameptr
);
7116 if (expected_sig
!= actual_sig
) {
7117 /* Take a SecureFault on the current stack */
7118 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
7119 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7120 v7m_exception_taken(cpu
, excret
, true, false);
7121 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
7122 "stackframe: failed exception return integrity "
7123 "signature check\n");
7128 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
7129 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
7130 v7m_stack_read(cpu
, &env
->regs
[5], frameptr
+ 0xc, mmu_idx
) &&
7131 v7m_stack_read(cpu
, &env
->regs
[6], frameptr
+ 0x10, mmu_idx
) &&
7132 v7m_stack_read(cpu
, &env
->regs
[7], frameptr
+ 0x14, mmu_idx
) &&
7133 v7m_stack_read(cpu
, &env
->regs
[8], frameptr
+ 0x18, mmu_idx
) &&
7134 v7m_stack_read(cpu
, &env
->regs
[9], frameptr
+ 0x1c, mmu_idx
) &&
7135 v7m_stack_read(cpu
, &env
->regs
[10], frameptr
+ 0x20, mmu_idx
) &&
7136 v7m_stack_read(cpu
, &env
->regs
[11], frameptr
+ 0x24, mmu_idx
);
7143 v7m_stack_read(cpu
, &env
->regs
[0], frameptr
, mmu_idx
) &&
7144 v7m_stack_read(cpu
, &env
->regs
[1], frameptr
+ 0x4, mmu_idx
) &&
7145 v7m_stack_read(cpu
, &env
->regs
[2], frameptr
+ 0x8, mmu_idx
) &&
7146 v7m_stack_read(cpu
, &env
->regs
[3], frameptr
+ 0xc, mmu_idx
) &&
7147 v7m_stack_read(cpu
, &env
->regs
[12], frameptr
+ 0x10, mmu_idx
) &&
7148 v7m_stack_read(cpu
, &env
->regs
[14], frameptr
+ 0x14, mmu_idx
) &&
7149 v7m_stack_read(cpu
, &env
->regs
[15], frameptr
+ 0x18, mmu_idx
) &&
7150 v7m_stack_read(cpu
, &xpsr
, frameptr
+ 0x1c, mmu_idx
);
7153 /* v7m_stack_read() pended a fault, so take it (as a tail
7154 * chained exception on the same stack frame)
7156 v7m_exception_taken(cpu
, excret
, true, false);
7160 /* Returning from an exception with a PC with bit 0 set is defined
7161 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
7162 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
7163 * the lsbit, and there are several RTOSes out there which incorrectly
7164 * assume the r15 in the stack frame should be a Thumb-style "lsbit
7165 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
7166 * complain about the badly behaved guest.
7168 if (env
->regs
[15] & 1) {
7169 env
->regs
[15] &= ~1U;
7170 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7171 qemu_log_mask(LOG_GUEST_ERROR
,
7172 "M profile return from interrupt with misaligned "
7173 "PC is UNPREDICTABLE on v7M\n");
7177 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7178 /* For v8M we have to check whether the xPSR exception field
7179 * matches the EXCRET value for return to handler/thread
7180 * before we commit to changing the SP and xPSR.
7182 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
7183 if (return_to_handler
!= will_be_handler
) {
7184 /* Take an INVPC UsageFault on the current stack.
7185 * By this point we will have switched to the security state
7186 * for the background state, so this UsageFault will target
7189 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7191 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7192 v7m_exception_taken(cpu
, excret
, true, false);
7193 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
7194 "stackframe: failed exception return integrity "
7200 /* Commit to consuming the stack frame */
7202 /* Undo stack alignment (the SPREALIGN bit indicates that the original
7203 * pre-exception SP was not 8-aligned and we added a padding word to
7204 * align it, so we undo this by ORing in the bit that increases it
7205 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
7206 * would work too but a logical OR is how the pseudocode specifies it.)
7208 if (xpsr
& XPSR_SPREALIGN
) {
7211 *frame_sp_p
= frameptr
;
7213 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
7214 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
7216 /* The restored xPSR exception field will be zero if we're
7217 * resuming in Thread mode. If that doesn't match what the
7218 * exception return excret specified then this is a UsageFault.
7219 * v7M requires we make this check here; v8M did it earlier.
7221 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
7222 /* Take an INVPC UsageFault by pushing the stack again;
7223 * we know we're v7M so this is never a Secure UsageFault.
7225 bool ignore_stackfaults
;
7227 assert(!arm_feature(env
, ARM_FEATURE_V8
));
7228 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
7229 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7230 ignore_stackfaults
= v7m_push_stack(cpu
);
7231 v7m_exception_taken(cpu
, excret
, false, ignore_stackfaults
);
7232 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
7233 "failed exception return integrity check\n");
7237 /* Otherwise, we have a successful exception exit. */
7238 arm_clear_exclusive(env
);
7239 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
7242 static bool do_v7m_function_return(ARMCPU
*cpu
)
7244 /* v8M security extensions magic function return.
7246 * (1) throw an exception (longjump)
7247 * (2) return true if we successfully handled the function return
7248 * (3) return false if we failed a consistency check and have
7249 * pended a UsageFault that needs to be taken now
7251 * At this point the magic return value is split between env->regs[15]
7252 * and env->thumb. We don't bother to reconstitute it because we don't
7253 * need it (all values are handled the same way).
7255 CPUARMState
*env
= &cpu
->env
;
7256 uint32_t newpc
, newpsr
, newpsr_exc
;
7258 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
7261 bool threadmode
, spsel
;
7264 uint32_t *frame_sp_p
;
7267 /* Pull the return address and IPSR from the Secure stack */
7268 threadmode
= !arm_v7m_is_handler_mode(env
);
7269 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
7271 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
7272 frameptr
= *frame_sp_p
;
7274 /* These loads may throw an exception (for MPU faults). We want to
7275 * do them as secure, so work out what MMU index that is.
7277 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7278 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
7279 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
7280 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
7282 /* Consistency checks on new IPSR */
7283 newpsr_exc
= newpsr
& XPSR_EXCP
;
7284 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
7285 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
7286 /* Pend the fault and tell our caller to take it */
7287 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7288 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7290 qemu_log_mask(CPU_LOG_INT
,
7291 "...taking INVPC UsageFault: "
7292 "IPSR consistency check failed\n");
7296 *frame_sp_p
= frameptr
+ 8;
7299 /* This invalidates frame_sp_p */
7300 switch_v7m_security_state(env
, true);
7301 env
->v7m
.exception
= newpsr_exc
;
7302 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
7303 if (newpsr
& XPSR_SFPA
) {
7304 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
7306 xpsr_write(env
, 0, XPSR_IT
);
7307 env
->thumb
= newpc
& 1;
7308 env
->regs
[15] = newpc
& ~1;
7310 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
7314 static void arm_log_exception(int idx
)
7316 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
7317 const char *exc
= NULL
;
7318 static const char * const excnames
[] = {
7319 [EXCP_UDEF
] = "Undefined Instruction",
7321 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
7322 [EXCP_DATA_ABORT
] = "Data Abort",
7325 [EXCP_BKPT
] = "Breakpoint",
7326 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
7327 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
7328 [EXCP_HVC
] = "Hypervisor Call",
7329 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
7330 [EXCP_SMC
] = "Secure Monitor Call",
7331 [EXCP_VIRQ
] = "Virtual IRQ",
7332 [EXCP_VFIQ
] = "Virtual FIQ",
7333 [EXCP_SEMIHOST
] = "Semihosting call",
7334 [EXCP_NOCP
] = "v7M NOCP UsageFault",
7335 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
7338 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
7339 exc
= excnames
[idx
];
7344 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
7348 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
7349 uint32_t addr
, uint16_t *insn
)
7351 /* Load a 16-bit portion of a v7M instruction, returning true on success,
7352 * or false on failure (in which case we will have pended the appropriate
7354 * We need to do the instruction fetch's MPU and SAU checks
7355 * like this because there is no MMU index that would allow
7356 * doing the load with a single function call. Instead we must
7357 * first check that the security attributes permit the load
7358 * and that they don't mismatch on the two halves of the instruction,
7359 * and then we do the load as a secure load (ie using the security
7360 * attributes of the address, not the CPU, as architecturally required).
7362 CPUState
*cs
= CPU(cpu
);
7363 CPUARMState
*env
= &cpu
->env
;
7364 V8M_SAttributes sattrs
= {};
7365 MemTxAttrs attrs
= {};
7366 ARMMMUFaultInfo fi
= {};
7368 target_ulong page_size
;
7372 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
7373 if (!sattrs
.nsc
|| sattrs
.ns
) {
7374 /* This must be the second half of the insn, and it straddles a
7375 * region boundary with the second half not being S&NSC.
7377 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7378 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7379 qemu_log_mask(CPU_LOG_INT
,
7380 "...really SecureFault with SFSR.INVEP\n");
7383 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
7384 &physaddr
, &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7385 /* the MPU lookup failed */
7386 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7387 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
7388 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
7391 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
7393 if (txres
!= MEMTX_OK
) {
7394 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7395 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7396 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
7402 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
7404 /* Check whether this attempt to execute code in a Secure & NS-Callable
7405 * memory region is for an SG instruction; if so, then emulate the
7406 * effect of the SG instruction and return true. Otherwise pend
7407 * the correct kind of exception and return false.
7409 CPUARMState
*env
= &cpu
->env
;
7413 /* We should never get here unless get_phys_addr_pmsav8() caused
7414 * an exception for NS executing in S&NSC memory.
7416 assert(!env
->v7m
.secure
);
7417 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7419 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
7420 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7422 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
7430 if (insn
!= 0xe97f) {
7431 /* Not an SG instruction first half (we choose the IMPDEF
7432 * early-SG-check option).
7437 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
7441 if (insn
!= 0xe97f) {
7442 /* Not an SG instruction second half (yes, both halves of the SG
7443 * insn have the same hex value)
7448 /* OK, we have confirmed that we really have an SG instruction.
7449 * We know we're NS in S memory so don't need to repeat those checks.
7451 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
7452 ", executing it\n", env
->regs
[15]);
7453 env
->regs
[14] &= ~1;
7454 switch_v7m_security_state(env
, true);
7455 xpsr_write(env
, 0, XPSR_IT
);
7460 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7461 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7462 qemu_log_mask(CPU_LOG_INT
,
7463 "...really SecureFault with SFSR.INVEP\n");
7467 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
7469 ARMCPU
*cpu
= ARM_CPU(cs
);
7470 CPUARMState
*env
= &cpu
->env
;
7472 bool ignore_stackfaults
;
7474 arm_log_exception(cs
->exception_index
);
7476 /* For exceptions we just mark as pending on the NVIC, and let that
7478 switch (cs
->exception_index
) {
7480 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7481 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
7484 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7485 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
7488 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7489 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
7492 /* The PC already points to the next instruction. */
7493 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
7495 case EXCP_PREFETCH_ABORT
:
7496 case EXCP_DATA_ABORT
:
7497 /* Note that for M profile we don't have a guest facing FSR, but
7498 * the env->exception.fsr will be populated by the code that
7499 * raises the fault, in the A profile short-descriptor format.
7501 switch (env
->exception
.fsr
& 0xf) {
7502 case M_FAKE_FSR_NSC_EXEC
:
7503 /* Exception generated when we try to execute code at an address
7504 * which is marked as Secure & Non-Secure Callable and the CPU
7505 * is in the Non-Secure state. The only instruction which can
7506 * be executed like this is SG (and that only if both halves of
7507 * the SG instruction have the same security attributes.)
7508 * Everything else must generate an INVEP SecureFault, so we
7509 * emulate the SG instruction here.
7511 if (v7m_handle_execute_nsc(cpu
)) {
7515 case M_FAKE_FSR_SFAULT
:
7516 /* Various flavours of SecureFault for attempts to execute or
7517 * access data in the wrong security state.
7519 switch (cs
->exception_index
) {
7520 case EXCP_PREFETCH_ABORT
:
7521 if (env
->v7m
.secure
) {
7522 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
7523 qemu_log_mask(CPU_LOG_INT
,
7524 "...really SecureFault with SFSR.INVTRAN\n");
7526 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7527 qemu_log_mask(CPU_LOG_INT
,
7528 "...really SecureFault with SFSR.INVEP\n");
7531 case EXCP_DATA_ABORT
:
7532 /* This must be an NS access to S memory */
7533 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
7534 qemu_log_mask(CPU_LOG_INT
,
7535 "...really SecureFault with SFSR.AUVIOL\n");
7538 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7540 case 0x8: /* External Abort */
7541 switch (cs
->exception_index
) {
7542 case EXCP_PREFETCH_ABORT
:
7543 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7544 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
7546 case EXCP_DATA_ABORT
:
7547 env
->v7m
.cfsr
[M_REG_NS
] |=
7548 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
7549 env
->v7m
.bfar
= env
->exception
.vaddress
;
7550 qemu_log_mask(CPU_LOG_INT
,
7551 "...with CFSR.PRECISERR and BFAR 0x%x\n",
7555 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7558 /* All other FSR values are either MPU faults or "can't happen
7559 * for M profile" cases.
7561 switch (cs
->exception_index
) {
7562 case EXCP_PREFETCH_ABORT
:
7563 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7564 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
7566 case EXCP_DATA_ABORT
:
7567 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
7568 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
7569 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
7570 qemu_log_mask(CPU_LOG_INT
,
7571 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
7572 env
->v7m
.mmfar
[env
->v7m
.secure
]);
7575 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
7581 if (semihosting_enabled()) {
7583 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
7586 qemu_log_mask(CPU_LOG_INT
,
7587 "...handling as semihosting call 0x%x\n",
7589 env
->regs
[0] = do_arm_semihosting(env
);
7593 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
7597 case EXCP_EXCEPTION_EXIT
:
7598 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
7599 /* Must be v8M security extension function return */
7600 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
7601 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7602 if (do_v7m_function_return(cpu
)) {
7606 do_v7m_exception_exit(cpu
);
7611 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7612 return; /* Never happens. Keep compiler happy. */
7615 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7616 lr
= R_V7M_EXCRET_RES1_MASK
|
7617 R_V7M_EXCRET_DCRS_MASK
|
7618 R_V7M_EXCRET_FTYPE_MASK
;
7619 /* The S bit indicates whether we should return to Secure
7620 * or NonSecure (ie our current state).
7621 * The ES bit indicates whether we're taking this exception
7622 * to Secure or NonSecure (ie our target state). We set it
7623 * later, in v7m_exception_taken().
7624 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
7625 * This corresponds to the ARM ARM pseudocode for v8M setting
7626 * some LR bits in PushStack() and some in ExceptionTaken();
7627 * the distinction matters for the tailchain cases where we
7628 * can take an exception without pushing the stack.
7630 if (env
->v7m
.secure
) {
7631 lr
|= R_V7M_EXCRET_S_MASK
;
7634 lr
= R_V7M_EXCRET_RES1_MASK
|
7635 R_V7M_EXCRET_S_MASK
|
7636 R_V7M_EXCRET_DCRS_MASK
|
7637 R_V7M_EXCRET_FTYPE_MASK
|
7638 R_V7M_EXCRET_ES_MASK
;
7639 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
7640 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
7643 if (!arm_v7m_is_handler_mode(env
)) {
7644 lr
|= R_V7M_EXCRET_MODE_MASK
;
7647 ignore_stackfaults
= v7m_push_stack(cpu
);
7648 v7m_exception_taken(cpu
, lr
, false, ignore_stackfaults
);
7649 qemu_log_mask(CPU_LOG_INT
, "... as %d\n", env
->v7m
.exception
);
7652 /* Function used to synchronize QEMU's AArch64 register set with AArch32
7653 * register set. This is necessary when switching between AArch32 and AArch64
7656 void aarch64_sync_32_to_64(CPUARMState
*env
)
7659 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7661 /* We can blanket copy R[0:7] to X[0:7] */
7662 for (i
= 0; i
< 8; i
++) {
7663 env
->xregs
[i
] = env
->regs
[i
];
7666 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7667 * Otherwise, they come from the banked user regs.
7669 if (mode
== ARM_CPU_MODE_FIQ
) {
7670 for (i
= 8; i
< 13; i
++) {
7671 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7674 for (i
= 8; i
< 13; i
++) {
7675 env
->xregs
[i
] = env
->regs
[i
];
7679 /* Registers x13-x23 are the various mode SP and FP registers. Registers
7680 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7681 * from the mode banked register.
7683 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7684 env
->xregs
[13] = env
->regs
[13];
7685 env
->xregs
[14] = env
->regs
[14];
7687 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7688 /* HYP is an exception in that it is copied from r14 */
7689 if (mode
== ARM_CPU_MODE_HYP
) {
7690 env
->xregs
[14] = env
->regs
[14];
7692 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
7696 if (mode
== ARM_CPU_MODE_HYP
) {
7697 env
->xregs
[15] = env
->regs
[13];
7699 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7702 if (mode
== ARM_CPU_MODE_IRQ
) {
7703 env
->xregs
[16] = env
->regs
[14];
7704 env
->xregs
[17] = env
->regs
[13];
7706 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
7707 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7710 if (mode
== ARM_CPU_MODE_SVC
) {
7711 env
->xregs
[18] = env
->regs
[14];
7712 env
->xregs
[19] = env
->regs
[13];
7714 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
7715 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7718 if (mode
== ARM_CPU_MODE_ABT
) {
7719 env
->xregs
[20] = env
->regs
[14];
7720 env
->xregs
[21] = env
->regs
[13];
7722 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
7723 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
7726 if (mode
== ARM_CPU_MODE_UND
) {
7727 env
->xregs
[22] = env
->regs
[14];
7728 env
->xregs
[23] = env
->regs
[13];
7730 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
7731 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
7734 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7735 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7736 * FIQ bank for r8-r14.
7738 if (mode
== ARM_CPU_MODE_FIQ
) {
7739 for (i
= 24; i
< 31; i
++) {
7740 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
7743 for (i
= 24; i
< 29; i
++) {
7744 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
7746 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
7747 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
7750 env
->pc
= env
->regs
[15];
7753 /* Function used to synchronize QEMU's AArch32 register set with AArch64
7754 * register set. This is necessary when switching between AArch32 and AArch64
7757 void aarch64_sync_64_to_32(CPUARMState
*env
)
7760 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7762 /* We can blanket copy X[0:7] to R[0:7] */
7763 for (i
= 0; i
< 8; i
++) {
7764 env
->regs
[i
] = env
->xregs
[i
];
7767 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
7768 * Otherwise, we copy x8-x12 into the banked user regs.
7770 if (mode
== ARM_CPU_MODE_FIQ
) {
7771 for (i
= 8; i
< 13; i
++) {
7772 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
7775 for (i
= 8; i
< 13; i
++) {
7776 env
->regs
[i
] = env
->xregs
[i
];
7780 /* Registers r13 & r14 depend on the current mode.
7781 * If we are in a given mode, we copy the corresponding x registers to r13
7782 * and r14. Otherwise, we copy the x register to the banked r13 and r14
7785 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7786 env
->regs
[13] = env
->xregs
[13];
7787 env
->regs
[14] = env
->xregs
[14];
7789 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
7791 /* HYP is an exception in that it does not have its own banked r14 but
7792 * shares the USR r14
7794 if (mode
== ARM_CPU_MODE_HYP
) {
7795 env
->regs
[14] = env
->xregs
[14];
7797 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
7801 if (mode
== ARM_CPU_MODE_HYP
) {
7802 env
->regs
[13] = env
->xregs
[15];
7804 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
7807 if (mode
== ARM_CPU_MODE_IRQ
) {
7808 env
->regs
[14] = env
->xregs
[16];
7809 env
->regs
[13] = env
->xregs
[17];
7811 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
7812 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
7815 if (mode
== ARM_CPU_MODE_SVC
) {
7816 env
->regs
[14] = env
->xregs
[18];
7817 env
->regs
[13] = env
->xregs
[19];
7819 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
7820 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
7823 if (mode
== ARM_CPU_MODE_ABT
) {
7824 env
->regs
[14] = env
->xregs
[20];
7825 env
->regs
[13] = env
->xregs
[21];
7827 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
7828 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
7831 if (mode
== ARM_CPU_MODE_UND
) {
7832 env
->regs
[14] = env
->xregs
[22];
7833 env
->regs
[13] = env
->xregs
[23];
7835 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
7836 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
7839 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7840 * mode, then we can copy to r8-r14. Otherwise, we copy to the
7841 * FIQ bank for r8-r14.
7843 if (mode
== ARM_CPU_MODE_FIQ
) {
7844 for (i
= 24; i
< 31; i
++) {
7845 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
7848 for (i
= 24; i
< 29; i
++) {
7849 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
7851 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
7852 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
7855 env
->regs
[15] = env
->pc
;
7858 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
7860 ARMCPU
*cpu
= ARM_CPU(cs
);
7861 CPUARMState
*env
= &cpu
->env
;
7868 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
7869 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
7871 case EC_BREAKPOINT_SAME_EL
:
7875 case EC_WATCHPOINT_SAME_EL
:
7881 case EC_VECTORCATCH
:
7890 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
7893 /* TODO: Vectored interrupt controller. */
7894 switch (cs
->exception_index
) {
7896 new_mode
= ARM_CPU_MODE_UND
;
7905 new_mode
= ARM_CPU_MODE_SVC
;
7908 /* The PC already points to the next instruction. */
7912 env
->exception
.fsr
= 2;
7913 /* Fall through to prefetch abort. */
7914 case EXCP_PREFETCH_ABORT
:
7915 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
7916 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
7917 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
7918 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
7919 new_mode
= ARM_CPU_MODE_ABT
;
7921 mask
= CPSR_A
| CPSR_I
;
7924 case EXCP_DATA_ABORT
:
7925 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
7926 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
7927 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
7929 (uint32_t)env
->exception
.vaddress
);
7930 new_mode
= ARM_CPU_MODE_ABT
;
7932 mask
= CPSR_A
| CPSR_I
;
7936 new_mode
= ARM_CPU_MODE_IRQ
;
7938 /* Disable IRQ and imprecise data aborts. */
7939 mask
= CPSR_A
| CPSR_I
;
7941 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
7942 /* IRQ routed to monitor mode */
7943 new_mode
= ARM_CPU_MODE_MON
;
7948 new_mode
= ARM_CPU_MODE_FIQ
;
7950 /* Disable FIQ, IRQ and imprecise data aborts. */
7951 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7952 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
7953 /* FIQ routed to monitor mode */
7954 new_mode
= ARM_CPU_MODE_MON
;
7959 new_mode
= ARM_CPU_MODE_IRQ
;
7961 /* Disable IRQ and imprecise data aborts. */
7962 mask
= CPSR_A
| CPSR_I
;
7966 new_mode
= ARM_CPU_MODE_FIQ
;
7968 /* Disable FIQ, IRQ and imprecise data aborts. */
7969 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7973 new_mode
= ARM_CPU_MODE_MON
;
7975 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7979 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7980 return; /* Never happens. Keep compiler happy. */
7983 if (new_mode
== ARM_CPU_MODE_MON
) {
7984 addr
+= env
->cp15
.mvbar
;
7985 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
7986 /* High vectors. When enabled, base address cannot be remapped. */
7989 /* ARM v7 architectures provide a vector base address register to remap
7990 * the interrupt vector table.
7991 * This register is only followed in non-monitor mode, and is banked.
7992 * Note: only bits 31:5 are valid.
7994 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
7997 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
7998 env
->cp15
.scr_el3
&= ~SCR_NS
;
8001 switch_mode (env
, new_mode
);
8002 /* For exceptions taken to AArch32 we must clear the SS bit in both
8003 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8005 env
->uncached_cpsr
&= ~PSTATE_SS
;
8006 env
->spsr
= cpsr_read(env
);
8007 /* Clear IT bits. */
8008 env
->condexec_bits
= 0;
8009 /* Switch to the new mode, and to the correct instruction set. */
8010 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8011 /* Set new mode endianness */
8012 env
->uncached_cpsr
&= ~CPSR_E
;
8013 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
8014 env
->uncached_cpsr
|= CPSR_E
;
8017 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
8018 * and we should just guard the thumb mode on V4 */
8019 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8020 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8022 env
->regs
[14] = env
->regs
[15] + offset
;
8023 env
->regs
[15] = addr
;
8026 /* Handle exception entry to a target EL which is using AArch64 */
8027 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
8029 ARMCPU
*cpu
= ARM_CPU(cs
);
8030 CPUARMState
*env
= &cpu
->env
;
8031 unsigned int new_el
= env
->exception
.target_el
;
8032 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
8033 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
8035 if (arm_current_el(env
) < new_el
) {
8036 /* Entry vector offset depends on whether the implemented EL
8037 * immediately lower than the target level is using AArch32 or AArch64
8043 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
8046 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
8049 is_aa64
= is_a64(env
);
8052 g_assert_not_reached();
8060 } else if (pstate_read(env
) & PSTATE_SP
) {
8064 switch (cs
->exception_index
) {
8065 case EXCP_PREFETCH_ABORT
:
8066 case EXCP_DATA_ABORT
:
8067 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
8068 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
8069 env
->cp15
.far_el
[new_el
]);
8077 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
8088 qemu_log_mask(CPU_LOG_INT
,
8089 "...handling as semihosting call 0x%" PRIx64
"\n",
8091 env
->xregs
[0] = do_arm_semihosting(env
);
8094 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8098 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
8099 aarch64_save_sp(env
, arm_current_el(env
));
8100 env
->elr_el
[new_el
] = env
->pc
;
8102 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
8103 env
->elr_el
[new_el
] = env
->regs
[15];
8105 aarch64_sync_32_to_64(env
);
8107 env
->condexec_bits
= 0;
8109 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
8110 env
->elr_el
[new_el
]);
8112 pstate_write(env
, PSTATE_DAIF
| new_mode
);
8114 aarch64_restore_sp(env
, new_el
);
8118 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
8119 new_el
, env
->pc
, pstate_read(env
));
8122 static inline bool check_for_semihosting(CPUState
*cs
)
8124 /* Check whether this exception is a semihosting call; if so
8125 * then handle it and return true; otherwise return false.
8127 ARMCPU
*cpu
= ARM_CPU(cs
);
8128 CPUARMState
*env
= &cpu
->env
;
8131 if (cs
->exception_index
== EXCP_SEMIHOST
) {
8132 /* This is always the 64-bit semihosting exception.
8133 * The "is this usermode" and "is semihosting enabled"
8134 * checks have been done at translate time.
8136 qemu_log_mask(CPU_LOG_INT
,
8137 "...handling as semihosting call 0x%" PRIx64
"\n",
8139 env
->xregs
[0] = do_arm_semihosting(env
);
8146 /* Only intercept calls from privileged modes, to provide some
8147 * semblance of security.
8149 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
8150 (!semihosting_enabled() ||
8151 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
8155 switch (cs
->exception_index
) {
8157 /* This is always a semihosting call; the "is this usermode"
8158 * and "is semihosting enabled" checks have been done at
8163 /* Check for semihosting interrupt. */
8165 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
8171 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
8173 if (imm
== 0x123456) {
8179 /* See if this is a semihosting syscall. */
8181 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
8193 qemu_log_mask(CPU_LOG_INT
,
8194 "...handling as semihosting call 0x%x\n",
8196 env
->regs
[0] = do_arm_semihosting(env
);
8201 /* Handle a CPU exception for A and R profile CPUs.
8202 * Do any appropriate logging, handle PSCI calls, and then hand off
8203 * to the AArch64-entry or AArch32-entry function depending on the
8204 * target exception level's register width.
8206 void arm_cpu_do_interrupt(CPUState
*cs
)
8208 ARMCPU
*cpu
= ARM_CPU(cs
);
8209 CPUARMState
*env
= &cpu
->env
;
8210 unsigned int new_el
= env
->exception
.target_el
;
8212 assert(!arm_feature(env
, ARM_FEATURE_M
));
8214 arm_log_exception(cs
->exception_index
);
8215 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
8217 if (qemu_loglevel_mask(CPU_LOG_INT
)
8218 && !excp_is_internal(cs
->exception_index
)) {
8219 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
8220 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
8221 env
->exception
.syndrome
);
8224 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
8225 arm_handle_psci_call(cpu
);
8226 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
8230 /* Semihosting semantics depend on the register width of the
8231 * code that caused the exception, not the target exception level,
8232 * so must be handled here.
8234 if (check_for_semihosting(cs
)) {
8238 assert(!excp_is_internal(cs
->exception_index
));
8239 if (arm_el_is_aa64(env
, new_el
)) {
8240 arm_cpu_do_interrupt_aarch64(cs
);
8242 arm_cpu_do_interrupt_aarch32(cs
);
8245 /* Hooks may change global state so BQL should be held, also the
8246 * BQL needs to be held for any modification of
8247 * cs->interrupt_request.
8249 g_assert(qemu_mutex_iothread_locked());
8251 arm_call_el_change_hook(cpu
);
8253 if (!kvm_enabled()) {
8254 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
8258 /* Return the exception level which controls this address translation regime */
8259 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8262 case ARMMMUIdx_S2NS
:
8263 case ARMMMUIdx_S1E2
:
8265 case ARMMMUIdx_S1E3
:
8267 case ARMMMUIdx_S1SE0
:
8268 return arm_el_is_aa64(env
, 3) ? 1 : 3;
8269 case ARMMMUIdx_S1SE1
:
8270 case ARMMMUIdx_S1NSE0
:
8271 case ARMMMUIdx_S1NSE1
:
8272 case ARMMMUIdx_MPrivNegPri
:
8273 case ARMMMUIdx_MUserNegPri
:
8274 case ARMMMUIdx_MPriv
:
8275 case ARMMMUIdx_MUser
:
8276 case ARMMMUIdx_MSPrivNegPri
:
8277 case ARMMMUIdx_MSUserNegPri
:
8278 case ARMMMUIdx_MSPriv
:
8279 case ARMMMUIdx_MSUser
:
8282 g_assert_not_reached();
8286 /* Return the SCTLR value which controls this address translation regime */
8287 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8289 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
8292 /* Return true if the specified stage of address translation is disabled */
8293 static inline bool regime_translation_disabled(CPUARMState
*env
,
8296 if (arm_feature(env
, ARM_FEATURE_M
)) {
8297 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
8298 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
8299 case R_V7M_MPU_CTRL_ENABLE_MASK
:
8300 /* Enabled, but not for HardFault and NMI */
8301 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
8302 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
8303 /* Enabled for all cases */
8307 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
8308 * we warned about that in armv7m_nvic.c when the guest set it.
8314 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8315 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
8317 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
8320 static inline bool regime_translation_big_endian(CPUARMState
*env
,
8323 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
8326 /* Return the TCR controlling this translation regime */
8327 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8329 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8330 return &env
->cp15
.vtcr_el2
;
8332 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
8335 /* Convert a possible stage1+2 MMU index into the appropriate
8338 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
8340 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8341 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
8346 /* Returns TBI0 value for current regime el */
8347 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8352 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8353 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8355 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8357 tcr
= regime_tcr(env
, mmu_idx
);
8358 el
= regime_el(env
, mmu_idx
);
8361 return extract64(tcr
->raw_tcr
, 20, 1);
8363 return extract64(tcr
->raw_tcr
, 37, 1);
8367 /* Returns TBI1 value for current regime el */
8368 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8373 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8374 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8376 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8378 tcr
= regime_tcr(env
, mmu_idx
);
8379 el
= regime_el(env
, mmu_idx
);
8384 return extract64(tcr
->raw_tcr
, 38, 1);
8388 /* Return the TTBR associated with this translation regime */
8389 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8392 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8393 return env
->cp15
.vttbr_el2
;
8396 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
8398 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
8402 /* Return true if the translation regime is using LPAE format page tables */
8403 static inline bool regime_using_lpae_format(CPUARMState
*env
,
8406 int el
= regime_el(env
, mmu_idx
);
8407 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
8410 if (arm_feature(env
, ARM_FEATURE_LPAE
)
8411 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
8417 /* Returns true if the stage 1 translation regime is using LPAE format page
8418 * tables. Used when raising alignment exceptions, whose FSR changes depending
8419 * on whether the long or short descriptor format is in use. */
8420 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8422 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8424 return regime_using_lpae_format(env
, mmu_idx
);
8427 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8430 case ARMMMUIdx_S1SE0
:
8431 case ARMMMUIdx_S1NSE0
:
8432 case ARMMMUIdx_MUser
:
8433 case ARMMMUIdx_MSUser
:
8434 case ARMMMUIdx_MUserNegPri
:
8435 case ARMMMUIdx_MSUserNegPri
:
8439 case ARMMMUIdx_S12NSE0
:
8440 case ARMMMUIdx_S12NSE1
:
8441 g_assert_not_reached();
8445 /* Translate section/page access permissions to page
8446 * R/W protection flags
8449 * @mmu_idx: MMU index indicating required translation regime
8450 * @ap: The 3-bit access permissions (AP[2:0])
8451 * @domain_prot: The 2-bit domain access permissions
8453 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8454 int ap
, int domain_prot
)
8456 bool is_user
= regime_is_user(env
, mmu_idx
);
8458 if (domain_prot
== 3) {
8459 return PAGE_READ
| PAGE_WRITE
;
8464 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8467 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8469 return is_user
? 0 : PAGE_READ
;
8476 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8481 return PAGE_READ
| PAGE_WRITE
;
8484 return PAGE_READ
| PAGE_WRITE
;
8485 case 4: /* Reserved. */
8488 return is_user
? 0 : PAGE_READ
;
8492 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8497 g_assert_not_reached();
8501 /* Translate section/page access permissions to page
8502 * R/W protection flags.
8504 * @ap: The 2-bit simple AP (AP[2:1])
8505 * @is_user: TRUE if accessing from PL0
8507 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8511 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8513 return PAGE_READ
| PAGE_WRITE
;
8515 return is_user
? 0 : PAGE_READ
;
8519 g_assert_not_reached();
8524 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8526 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8529 /* Translate S2 section/page access permissions to protection flags
8532 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8533 * @xn: XN (execute-never) bit
8535 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8546 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8553 /* Translate section/page access permissions to protection flags
8556 * @mmu_idx: MMU index indicating required translation regime
8557 * @is_aa64: TRUE if AArch64
8558 * @ap: The 2-bit simple AP (AP[2:1])
8559 * @ns: NS (non-secure) bit
8560 * @xn: XN (execute-never) bit
8561 * @pxn: PXN (privileged execute-never) bit
8563 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8564 int ap
, int ns
, int xn
, int pxn
)
8566 bool is_user
= regime_is_user(env
, mmu_idx
);
8567 int prot_rw
, user_rw
;
8571 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8573 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8577 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8580 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8584 /* TODO have_wxn should be replaced with
8585 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8586 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8587 * compatible processors have EL2, which is required for [U]WXN.
8589 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8592 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8596 switch (regime_el(env
, mmu_idx
)) {
8599 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8606 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8607 switch (regime_el(env
, mmu_idx
)) {
8611 xn
= xn
|| !(user_rw
& PAGE_READ
);
8615 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8617 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8618 (uwxn
&& (user_rw
& PAGE_WRITE
));
8628 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8631 return prot_rw
| PAGE_EXEC
;
8634 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8635 uint32_t *table
, uint32_t address
)
8637 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8638 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8640 if (address
& tcr
->mask
) {
8641 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8642 /* Translation table walk disabled for TTBR1 */
8645 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8647 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8648 /* Translation table walk disabled for TTBR0 */
8651 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
8653 *table
|= (address
>> 18) & 0x3ffc;
8657 /* Translate a S1 pagetable walk through S2 if needed. */
8658 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8659 hwaddr addr
, MemTxAttrs txattrs
,
8660 ARMMMUFaultInfo
*fi
)
8662 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
8663 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8664 target_ulong s2size
;
8669 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
8670 &txattrs
, &s2prot
, &s2size
, fi
, NULL
);
8672 assert(fi
->type
!= ARMFault_None
);
8683 /* All loads done in the course of a page table walk go through here.
8684 * TODO: rather than ignoring errors from physical memory reads (which
8685 * are external aborts in ARM terminology) we should propagate this
8686 * error out so that we can turn it into a Data Abort if this walk
8687 * was being done for a CPU load/store or an address translation instruction
8688 * (but not if it was for a debug access).
8690 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8691 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8693 ARMCPU
*cpu
= ARM_CPU(cs
);
8694 CPUARMState
*env
= &cpu
->env
;
8695 MemTxAttrs attrs
= {};
8696 MemTxResult result
= MEMTX_OK
;
8700 attrs
.secure
= is_secure
;
8701 as
= arm_addressspace(cs
, attrs
);
8702 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8706 if (regime_translation_big_endian(env
, mmu_idx
)) {
8707 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
8709 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
8711 if (result
== MEMTX_OK
) {
8714 fi
->type
= ARMFault_SyncExternalOnWalk
;
8715 fi
->ea
= arm_extabort_type(result
);
8719 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8720 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8722 ARMCPU
*cpu
= ARM_CPU(cs
);
8723 CPUARMState
*env
= &cpu
->env
;
8724 MemTxAttrs attrs
= {};
8725 MemTxResult result
= MEMTX_OK
;
8729 attrs
.secure
= is_secure
;
8730 as
= arm_addressspace(cs
, attrs
);
8731 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8735 if (regime_translation_big_endian(env
, mmu_idx
)) {
8736 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
8738 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
8740 if (result
== MEMTX_OK
) {
8743 fi
->type
= ARMFault_SyncExternalOnWalk
;
8744 fi
->ea
= arm_extabort_type(result
);
8748 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
8749 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8750 hwaddr
*phys_ptr
, int *prot
,
8751 target_ulong
*page_size
,
8752 ARMMMUFaultInfo
*fi
)
8754 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8765 /* Pagetable walk. */
8766 /* Lookup l1 descriptor. */
8767 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8768 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8769 fi
->type
= ARMFault_Translation
;
8772 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8774 if (fi
->type
!= ARMFault_None
) {
8778 domain
= (desc
>> 5) & 0x0f;
8779 if (regime_el(env
, mmu_idx
) == 1) {
8780 dacr
= env
->cp15
.dacr_ns
;
8782 dacr
= env
->cp15
.dacr_s
;
8784 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8786 /* Section translation fault. */
8787 fi
->type
= ARMFault_Translation
;
8793 if (domain_prot
== 0 || domain_prot
== 2) {
8794 fi
->type
= ARMFault_Domain
;
8799 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8800 ap
= (desc
>> 10) & 3;
8801 *page_size
= 1024 * 1024;
8803 /* Lookup l2 entry. */
8805 /* Coarse pagetable. */
8806 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8808 /* Fine pagetable. */
8809 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
8811 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8813 if (fi
->type
!= ARMFault_None
) {
8817 case 0: /* Page translation fault. */
8818 fi
->type
= ARMFault_Translation
;
8820 case 1: /* 64k page. */
8821 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8822 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
8823 *page_size
= 0x10000;
8825 case 2: /* 4k page. */
8826 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8827 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
8828 *page_size
= 0x1000;
8830 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
8832 /* ARMv6/XScale extended small page format */
8833 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
8834 || arm_feature(env
, ARM_FEATURE_V6
)) {
8835 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8836 *page_size
= 0x1000;
8838 /* UNPREDICTABLE in ARMv5; we choose to take a
8839 * page translation fault.
8841 fi
->type
= ARMFault_Translation
;
8845 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
8848 ap
= (desc
>> 4) & 3;
8851 /* Never happens, but compiler isn't smart enough to tell. */
8855 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
8856 *prot
|= *prot
? PAGE_EXEC
: 0;
8857 if (!(*prot
& (1 << access_type
))) {
8858 /* Access permission fault. */
8859 fi
->type
= ARMFault_Permission
;
8862 *phys_ptr
= phys_addr
;
8865 fi
->domain
= domain
;
8870 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
8871 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8872 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
8873 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
8875 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8889 /* Pagetable walk. */
8890 /* Lookup l1 descriptor. */
8891 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8892 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8893 fi
->type
= ARMFault_Translation
;
8896 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8898 if (fi
->type
!= ARMFault_None
) {
8902 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
8903 /* Section translation fault, or attempt to use the encoding
8904 * which is Reserved on implementations without PXN.
8906 fi
->type
= ARMFault_Translation
;
8909 if ((type
== 1) || !(desc
& (1 << 18))) {
8910 /* Page or Section. */
8911 domain
= (desc
>> 5) & 0x0f;
8913 if (regime_el(env
, mmu_idx
) == 1) {
8914 dacr
= env
->cp15
.dacr_ns
;
8916 dacr
= env
->cp15
.dacr_s
;
8921 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8922 if (domain_prot
== 0 || domain_prot
== 2) {
8923 /* Section or Page domain fault */
8924 fi
->type
= ARMFault_Domain
;
8928 if (desc
& (1 << 18)) {
8930 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
8931 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
8932 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
8933 *page_size
= 0x1000000;
8936 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8937 *page_size
= 0x100000;
8939 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
8940 xn
= desc
& (1 << 4);
8942 ns
= extract32(desc
, 19, 1);
8944 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
8945 pxn
= (desc
>> 2) & 1;
8947 ns
= extract32(desc
, 3, 1);
8948 /* Lookup l2 entry. */
8949 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8950 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8952 if (fi
->type
!= ARMFault_None
) {
8955 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
8957 case 0: /* Page translation fault. */
8958 fi
->type
= ARMFault_Translation
;
8960 case 1: /* 64k page. */
8961 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8962 xn
= desc
& (1 << 15);
8963 *page_size
= 0x10000;
8965 case 2: case 3: /* 4k page. */
8966 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8968 *page_size
= 0x1000;
8971 /* Never happens, but compiler isn't smart enough to tell. */
8975 if (domain_prot
== 3) {
8976 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8978 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
8981 if (xn
&& access_type
== MMU_INST_FETCH
) {
8982 fi
->type
= ARMFault_Permission
;
8986 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
8987 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
8988 /* The simplified model uses AP[0] as an access control bit. */
8989 if ((ap
& 1) == 0) {
8990 /* Access flag fault. */
8991 fi
->type
= ARMFault_AccessFlag
;
8994 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
8996 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9001 if (!(*prot
& (1 << access_type
))) {
9002 /* Access permission fault. */
9003 fi
->type
= ARMFault_Permission
;
9008 /* The NS bit will (as required by the architecture) have no effect if
9009 * the CPU doesn't support TZ or this is a non-secure translation
9010 * regime, because the attribute will already be non-secure.
9012 attrs
->secure
= false;
9014 *phys_ptr
= phys_addr
;
9017 fi
->domain
= domain
;
9023 * check_s2_mmu_setup
9025 * @is_aa64: True if the translation regime is in AArch64 state
9026 * @startlevel: Suggested starting level
9027 * @inputsize: Bitsize of IPAs
9028 * @stride: Page-table stride (See the ARM ARM)
9030 * Returns true if the suggested S2 translation parameters are OK and
9033 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
9034 int inputsize
, int stride
)
9036 const int grainsize
= stride
+ 3;
9039 /* Negative levels are never allowed. */
9044 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
9045 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
9050 CPUARMState
*env
= &cpu
->env
;
9051 unsigned int pamax
= arm_pamax(cpu
);
9054 case 13: /* 64KB Pages. */
9055 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
9059 case 11: /* 16KB Pages. */
9060 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
9064 case 9: /* 4KB Pages. */
9065 if (level
== 0 && pamax
<= 42) {
9070 g_assert_not_reached();
9073 /* Inputsize checks. */
9074 if (inputsize
> pamax
&&
9075 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
9076 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
9080 /* AArch32 only supports 4KB pages. Assert on that. */
9081 assert(stride
== 9);
9090 /* Translate from the 4-bit stage 2 representation of
9091 * memory attributes (without cache-allocation hints) to
9092 * the 8-bit representation of the stage 1 MAIR registers
9093 * (which includes allocation hints).
9095 * ref: shared/translation/attrs/S2AttrDecode()
9096 * .../S2ConvertAttrsHints()
9098 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
9100 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
9101 uint8_t loattr
= extract32(s2attrs
, 0, 2);
9102 uint8_t hihint
= 0, lohint
= 0;
9104 if (hiattr
!= 0) { /* normal memory */
9105 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
9106 hiattr
= loattr
= 1; /* non-cacheable */
9108 if (hiattr
!= 1) { /* Write-through or write-back */
9109 hihint
= 3; /* RW allocate */
9111 if (loattr
!= 1) { /* Write-through or write-back */
9112 lohint
= 3; /* RW allocate */
9117 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
9120 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
9121 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9122 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
9123 target_ulong
*page_size_ptr
,
9124 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
9126 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9127 CPUState
*cs
= CPU(cpu
);
9128 /* Read an LPAE long-descriptor translation table. */
9129 ARMFaultType fault_type
= ARMFault_Translation
;
9136 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
9137 uint32_t tableattrs
;
9138 target_ulong page_size
;
9144 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9145 int ap
, ns
, xn
, pxn
;
9146 uint32_t el
= regime_el(env
, mmu_idx
);
9147 bool ttbr1_valid
= true;
9148 uint64_t descaddrmask
;
9149 bool aarch64
= arm_el_is_aa64(env
, el
);
9152 * This code does not handle the different format TCR for VTCR_EL2.
9153 * This code also does not support shareability levels.
9154 * Attribute and permission bit handling should also be checked when adding
9155 * support for those page table walks.
9161 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9162 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
9165 if (extract64(address
, 55, 1)) {
9166 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
9168 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
9173 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9177 ttbr1_valid
= false;
9182 /* There is no TTBR1 for EL2 */
9184 ttbr1_valid
= false;
9188 /* Determine whether this address is in the region controlled by
9189 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
9190 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
9191 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
9194 /* AArch64 translation. */
9195 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
9196 t0sz
= MIN(t0sz
, 39);
9197 t0sz
= MAX(t0sz
, 16);
9198 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9199 /* AArch32 stage 1 translation. */
9200 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
9202 /* AArch32 stage 2 translation. */
9203 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
9204 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
9205 /* Address size is 40-bit for a stage 2 translation,
9206 * and t0sz can be negative (from -8 to 7),
9207 * so we need to adjust it to use the TTBR selecting logic below.
9210 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
9212 /* If the sign-extend bit is not the same as t0sz[3], the result
9213 * is unpredictable. Flag this as a guest error. */
9215 qemu_log_mask(LOG_GUEST_ERROR
,
9216 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
9219 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
9221 t1sz
= MIN(t1sz
, 39);
9222 t1sz
= MAX(t1sz
, 16);
9224 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
9225 /* there is a ttbr0 region and we are in it (high bits all zero) */
9227 } else if (ttbr1_valid
&& t1sz
&&
9228 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
9229 /* there is a ttbr1 region and we are in it (high bits all one) */
9232 /* ttbr0 region is "everything not in the ttbr1 region" */
9234 } else if (!t1sz
&& ttbr1_valid
) {
9235 /* ttbr1 region is "everything not in the ttbr0 region" */
9238 /* in the gap between the two regions, this is a Translation fault */
9239 fault_type
= ARMFault_Translation
;
9243 /* Note that QEMU ignores shareability and cacheability attributes,
9244 * so we don't need to do anything with the SH, ORGN, IRGN fields
9245 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
9246 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
9247 * implement any ASID-like capability so we can ignore it (instead
9248 * we will always flush the TLB any time the ASID is changed).
9250 if (ttbr_select
== 0) {
9251 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
9253 epd
= extract32(tcr
->raw_tcr
, 7, 1);
9255 inputsize
= addrsize
- t0sz
;
9257 tg
= extract32(tcr
->raw_tcr
, 14, 2);
9258 if (tg
== 1) { /* 64KB pages */
9261 if (tg
== 2) { /* 16KB pages */
9265 /* We should only be here if TTBR1 is valid */
9266 assert(ttbr1_valid
);
9268 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
9269 epd
= extract32(tcr
->raw_tcr
, 23, 1);
9270 inputsize
= addrsize
- t1sz
;
9272 tg
= extract32(tcr
->raw_tcr
, 30, 2);
9273 if (tg
== 3) { /* 64KB pages */
9276 if (tg
== 1) { /* 16KB pages */
9281 /* Here we should have set up all the parameters for the translation:
9282 * inputsize, ttbr, epd, stride, tbi
9286 /* Translation table walk disabled => Translation fault on TLB miss
9287 * Note: This is always 0 on 64-bit EL2 and EL3.
9292 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9293 /* The starting level depends on the virtual address size (which can
9294 * be up to 48 bits) and the translation granule size. It indicates
9295 * the number of strides (stride bits at a time) needed to
9296 * consume the bits of the input address. In the pseudocode this is:
9297 * level = 4 - RoundUp((inputsize - grainsize) / stride)
9298 * where their 'inputsize' is our 'inputsize', 'grainsize' is
9299 * our 'stride + 3' and 'stride' is our 'stride'.
9300 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
9301 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
9302 * = 4 - (inputsize - 4) / stride;
9304 level
= 4 - (inputsize
- 4) / stride
;
9306 /* For stage 2 translations the starting level is specified by the
9307 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
9309 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
9310 uint32_t startlevel
;
9313 if (!aarch64
|| stride
== 9) {
9314 /* AArch32 or 4KB pages */
9315 startlevel
= 2 - sl0
;
9317 /* 16KB or 64KB pages */
9318 startlevel
= 3 - sl0
;
9321 /* Check that the starting level is valid. */
9322 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
9325 fault_type
= ARMFault_Translation
;
9331 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
9332 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
9334 /* Now we can extract the actual base address from the TTBR */
9335 descaddr
= extract64(ttbr
, 0, 48);
9336 descaddr
&= ~indexmask
;
9338 /* The address field in the descriptor goes up to bit 39 for ARMv7
9339 * but up to bit 47 for ARMv8, but we use the descaddrmask
9340 * up to bit 39 for AArch32, because we don't need other bits in that case
9341 * to construct next descriptor address (anyway they should be all zeroes).
9343 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
9344 ~indexmask_grainsize
;
9346 /* Secure accesses start with the page table in secure memory and
9347 * can be downgraded to non-secure at any step. Non-secure accesses
9348 * remain non-secure. We implement this by just ORing in the NSTable/NS
9349 * bits at each step.
9351 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
9353 uint64_t descriptor
;
9356 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
9358 nstable
= extract32(tableattrs
, 4, 1);
9359 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
9360 if (fi
->type
!= ARMFault_None
) {
9364 if (!(descriptor
& 1) ||
9365 (!(descriptor
& 2) && (level
== 3))) {
9366 /* Invalid, or the Reserved level 3 encoding */
9369 descaddr
= descriptor
& descaddrmask
;
9371 if ((descriptor
& 2) && (level
< 3)) {
9372 /* Table entry. The top five bits are attributes which may
9373 * propagate down through lower levels of the table (and
9374 * which are all arranged so that 0 means "no effect", so
9375 * we can gather them up by ORing in the bits at each level).
9377 tableattrs
|= extract64(descriptor
, 59, 5);
9379 indexmask
= indexmask_grainsize
;
9382 /* Block entry at level 1 or 2, or page entry at level 3.
9383 * These are basically the same thing, although the number
9384 * of bits we pull in from the vaddr varies.
9386 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
9387 descaddr
|= (address
& (page_size
- 1));
9388 /* Extract attributes from the descriptor */
9389 attrs
= extract64(descriptor
, 2, 10)
9390 | (extract64(descriptor
, 52, 12) << 10);
9392 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9393 /* Stage 2 table descriptors do not include any attribute fields */
9396 /* Merge in attributes from table descriptors */
9397 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
9398 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
9399 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9400 * means "force PL1 access only", which means forcing AP[1] to 0.
9402 if (extract32(tableattrs
, 2, 1)) {
9405 attrs
|= nstable
<< 3; /* NS */
9408 /* Here descaddr is the final physical address, and attributes
9411 fault_type
= ARMFault_AccessFlag
;
9412 if ((attrs
& (1 << 8)) == 0) {
9417 ap
= extract32(attrs
, 4, 2);
9418 xn
= extract32(attrs
, 12, 1);
9420 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9422 *prot
= get_S2prot(env
, ap
, xn
);
9424 ns
= extract32(attrs
, 3, 1);
9425 pxn
= extract32(attrs
, 11, 1);
9426 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
9429 fault_type
= ARMFault_Permission
;
9430 if (!(*prot
& (1 << access_type
))) {
9435 /* The NS bit will (as required by the architecture) have no effect if
9436 * the CPU doesn't support TZ or this is a non-secure translation
9437 * regime, because the attribute will already be non-secure.
9439 txattrs
->secure
= false;
9442 if (cacheattrs
!= NULL
) {
9443 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9444 cacheattrs
->attrs
= convert_stage2_attrs(env
,
9445 extract32(attrs
, 0, 4));
9447 /* Index into MAIR registers for cache attributes */
9448 uint8_t attrindx
= extract32(attrs
, 0, 3);
9449 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
9450 assert(attrindx
<= 7);
9451 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
9453 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
9456 *phys_ptr
= descaddr
;
9457 *page_size_ptr
= page_size
;
9461 fi
->type
= fault_type
;
9463 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9464 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
9468 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
9470 int32_t address
, int *prot
)
9472 if (!arm_feature(env
, ARM_FEATURE_M
)) {
9473 *prot
= PAGE_READ
| PAGE_WRITE
;
9475 case 0xF0000000 ... 0xFFFFFFFF:
9476 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
9477 /* hivecs execing is ok */
9481 case 0x00000000 ... 0x7FFFFFFF:
9486 /* Default system address map for M profile cores.
9487 * The architecture specifies which regions are execute-never;
9488 * at the MPU level no other checks are defined.
9491 case 0x00000000 ... 0x1fffffff: /* ROM */
9492 case 0x20000000 ... 0x3fffffff: /* SRAM */
9493 case 0x60000000 ... 0x7fffffff: /* RAM */
9494 case 0x80000000 ... 0x9fffffff: /* RAM */
9495 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9497 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9498 case 0xa0000000 ... 0xbfffffff: /* Device */
9499 case 0xc0000000 ... 0xdfffffff: /* Device */
9500 case 0xe0000000 ... 0xffffffff: /* System */
9501 *prot
= PAGE_READ
| PAGE_WRITE
;
9504 g_assert_not_reached();
9509 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
9510 ARMMMUIdx mmu_idx
, bool is_user
)
9512 /* Return true if we should use the default memory map as a
9513 * "background" region if there are no hits against any MPU regions.
9515 CPUARMState
*env
= &cpu
->env
;
9521 if (arm_feature(env
, ARM_FEATURE_M
)) {
9522 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
9523 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9525 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9529 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9531 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9532 return arm_feature(env
, ARM_FEATURE_M
) &&
9533 extract32(address
, 20, 12) == 0xe00;
9536 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9538 /* True if address is in the M profile system region
9539 * 0xe0000000 - 0xffffffff
9541 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9544 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9545 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9546 hwaddr
*phys_ptr
, int *prot
,
9547 ARMMMUFaultInfo
*fi
)
9549 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9551 bool is_user
= regime_is_user(env
, mmu_idx
);
9553 *phys_ptr
= address
;
9556 if (regime_translation_disabled(env
, mmu_idx
) ||
9557 m_is_ppb_region(env
, address
)) {
9558 /* MPU disabled or M profile PPB access: use default memory map.
9559 * The other case which uses the default memory map in the
9560 * v7M ARM ARM pseudocode is exception vector reads from the vector
9561 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9562 * which always does a direct read using address_space_ldl(), rather
9563 * than going via this function, so we don't need to check that here.
9565 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9566 } else { /* MPU enabled */
9567 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9569 uint32_t base
= env
->pmsav7
.drbar
[n
];
9570 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
9574 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
9579 qemu_log_mask(LOG_GUEST_ERROR
,
9580 "DRSR[%d]: Rsize field cannot be 0\n", n
);
9584 rmask
= (1ull << rsize
) - 1;
9587 qemu_log_mask(LOG_GUEST_ERROR
,
9588 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
9589 "to DRSR region size, mask = 0x%" PRIx32
"\n",
9594 if (address
< base
|| address
> base
+ rmask
) {
9598 /* Region matched */
9600 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
9602 uint32_t srdis_mask
;
9604 rsize
-= 3; /* sub region size (power of 2) */
9605 snd
= ((address
- base
) >> rsize
) & 0x7;
9606 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
9608 srdis_mask
= srdis
? 0x3 : 0x0;
9609 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
9610 /* This will check in groups of 2, 4 and then 8, whether
9611 * the subregion bits are consistent. rsize is incremented
9612 * back up to give the region size, considering consistent
9613 * adjacent subregions as one region. Stop testing if rsize
9614 * is already big enough for an entire QEMU page.
9616 int snd_rounded
= snd
& ~(i
- 1);
9617 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
9618 snd_rounded
+ 8, i
);
9619 if (srdis_mask
^ srdis_multi
) {
9622 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
9626 if (rsize
< TARGET_PAGE_BITS
) {
9627 qemu_log_mask(LOG_UNIMP
,
9628 "DRSR[%d]: No support for MPU (sub)region "
9629 "alignment of %" PRIu32
" bits. Minimum is %d\n",
9630 n
, rsize
, TARGET_PAGE_BITS
);
9639 if (n
== -1) { /* no hits */
9640 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9641 /* background fault */
9642 fi
->type
= ARMFault_Background
;
9645 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9646 } else { /* a MPU hit! */
9647 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
9648 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
9650 if (m_is_system_region(env
, address
)) {
9651 /* System space is always execute never */
9655 if (is_user
) { /* User mode AP bit decoding */
9660 break; /* no access */
9662 *prot
|= PAGE_WRITE
;
9666 *prot
|= PAGE_READ
| PAGE_EXEC
;
9669 /* for v7M, same as 6; for R profile a reserved value */
9670 if (arm_feature(env
, ARM_FEATURE_M
)) {
9671 *prot
|= PAGE_READ
| PAGE_EXEC
;
9676 qemu_log_mask(LOG_GUEST_ERROR
,
9677 "DRACR[%d]: Bad value for AP bits: 0x%"
9678 PRIx32
"\n", n
, ap
);
9680 } else { /* Priv. mode AP bits decoding */
9683 break; /* no access */
9687 *prot
|= PAGE_WRITE
;
9691 *prot
|= PAGE_READ
| PAGE_EXEC
;
9694 /* for v7M, same as 6; for R profile a reserved value */
9695 if (arm_feature(env
, ARM_FEATURE_M
)) {
9696 *prot
|= PAGE_READ
| PAGE_EXEC
;
9701 qemu_log_mask(LOG_GUEST_ERROR
,
9702 "DRACR[%d]: Bad value for AP bits: 0x%"
9703 PRIx32
"\n", n
, ap
);
9709 *prot
&= ~PAGE_EXEC
;
9714 fi
->type
= ARMFault_Permission
;
9716 return !(*prot
& (1 << access_type
));
9719 static bool v8m_is_sau_exempt(CPUARMState
*env
,
9720 uint32_t address
, MMUAccessType access_type
)
9722 /* The architecture specifies that certain address ranges are
9723 * exempt from v8M SAU/IDAU checks.
9726 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
9727 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
9728 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
9729 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
9730 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
9731 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
9734 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
9735 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9736 V8M_SAttributes
*sattrs
)
9738 /* Look up the security attributes for this address. Compare the
9739 * pseudocode SecurityCheck() function.
9740 * We assume the caller has zero-initialized *sattrs.
9742 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9745 /* TODO: implement IDAU */
9747 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
9748 /* 0xf0000000..0xffffffff is always S for insn fetches */
9752 if (v8m_is_sau_exempt(env
, address
, access_type
)) {
9753 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
9757 switch (env
->sau
.ctrl
& 3) {
9758 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
9760 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
9763 default: /* SAU.ENABLE == 1 */
9764 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
9765 if (env
->sau
.rlar
[r
] & 1) {
9766 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
9767 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
9769 if (base
<= address
&& limit
>= address
) {
9770 if (sattrs
->srvalid
) {
9771 /* If we hit in more than one region then we must report
9772 * as Secure, not NS-Callable, with no valid region
9776 sattrs
->nsc
= false;
9777 sattrs
->sregion
= 0;
9778 sattrs
->srvalid
= false;
9781 if (env
->sau
.rlar
[r
] & 2) {
9786 sattrs
->srvalid
= true;
9787 sattrs
->sregion
= r
;
9793 /* TODO when we support the IDAU then it may override the result here */
9798 static bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
9799 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9800 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
9801 int *prot
, ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
9803 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
9804 * that a full phys-to-virt translation does).
9805 * mregion is (if not NULL) set to the region number which matched,
9806 * or -1 if no region number is returned (MPU off, address did not
9807 * hit a region, address hit in multiple regions).
9809 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9810 bool is_user
= regime_is_user(env
, mmu_idx
);
9811 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
9813 int matchregion
= -1;
9816 *phys_ptr
= address
;
9822 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
9823 * was an exception vector read from the vector table (which is always
9824 * done using the default system address map), because those accesses
9825 * are done in arm_v7m_load_vector(), which always does a direct
9826 * read using address_space_ldl(), rather than going via this function.
9828 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
9830 } else if (m_is_ppb_region(env
, address
)) {
9832 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9835 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9837 /* Note that the base address is bits [31:5] from the register
9838 * with bits [4:0] all zeroes, but the limit address is bits
9839 * [31:5] from the register with bits [4:0] all ones.
9841 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
9842 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
9844 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
9845 /* Region disabled */
9849 if (address
< base
|| address
> limit
) {
9854 /* Multiple regions match -- always a failure (unlike
9855 * PMSAv7 where highest-numbered-region wins)
9857 fi
->type
= ARMFault_Permission
;
9865 if (base
& ~TARGET_PAGE_MASK
) {
9866 qemu_log_mask(LOG_UNIMP
,
9867 "MPU_RBAR[%d]: No support for MPU region base"
9868 "address of 0x%" PRIx32
". Minimum alignment is "
9870 n
, base
, TARGET_PAGE_BITS
);
9873 if ((limit
+ 1) & ~TARGET_PAGE_MASK
) {
9874 qemu_log_mask(LOG_UNIMP
,
9875 "MPU_RBAR[%d]: No support for MPU region limit"
9876 "address of 0x%" PRIx32
". Minimum alignment is "
9878 n
, limit
, TARGET_PAGE_BITS
);
9885 /* background fault */
9886 fi
->type
= ARMFault_Background
;
9890 if (matchregion
== -1) {
9891 /* hit using the background region */
9892 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9894 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
9895 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
9897 if (m_is_system_region(env
, address
)) {
9898 /* System space is always execute never */
9902 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
9906 /* We don't need to look the attribute up in the MAIR0/MAIR1
9907 * registers because that only tells us about cacheability.
9910 *mregion
= matchregion
;
9914 fi
->type
= ARMFault_Permission
;
9916 return !(*prot
& (1 << access_type
));
9920 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
9921 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9922 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
9923 int *prot
, ARMMMUFaultInfo
*fi
)
9925 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
9926 V8M_SAttributes sattrs
= {};
9928 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
9929 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
9930 if (access_type
== MMU_INST_FETCH
) {
9931 /* Instruction fetches always use the MMU bank and the
9932 * transaction attribute determined by the fetch address,
9933 * regardless of CPU state. This is painful for QEMU
9934 * to handle, because it would mean we need to encode
9935 * into the mmu_idx not just the (user, negpri) information
9936 * for the current security state but also that for the
9937 * other security state, which would balloon the number
9938 * of mmu_idx values needed alarmingly.
9939 * Fortunately we can avoid this because it's not actually
9940 * possible to arbitrarily execute code from memory with
9941 * the wrong security attribute: it will always generate
9942 * an exception of some kind or another, apart from the
9943 * special case of an NS CPU executing an SG instruction
9944 * in S&NSC memory. So we always just fail the translation
9945 * here and sort things out in the exception handler
9946 * (including possibly emulating an SG instruction).
9948 if (sattrs
.ns
!= !secure
) {
9950 fi
->type
= ARMFault_QEMU_NSCExec
;
9952 fi
->type
= ARMFault_QEMU_SFault
;
9954 *phys_ptr
= address
;
9959 /* For data accesses we always use the MMU bank indicated
9960 * by the current CPU state, but the security attributes
9961 * might downgrade a secure access to nonsecure.
9964 txattrs
->secure
= false;
9965 } else if (!secure
) {
9966 /* NS access to S memory must fault.
9967 * Architecturally we should first check whether the
9968 * MPU information for this address indicates that we
9969 * are doing an unaligned access to Device memory, which
9970 * should generate a UsageFault instead. QEMU does not
9971 * currently check for that kind of unaligned access though.
9972 * If we added it we would need to do so as a special case
9973 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
9975 fi
->type
= ARMFault_QEMU_SFault
;
9976 *phys_ptr
= address
;
9983 return pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
9984 txattrs
, prot
, fi
, NULL
);
9987 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
9988 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9989 hwaddr
*phys_ptr
, int *prot
,
9990 ARMMMUFaultInfo
*fi
)
9995 bool is_user
= regime_is_user(env
, mmu_idx
);
9997 if (regime_translation_disabled(env
, mmu_idx
)) {
9999 *phys_ptr
= address
;
10000 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10004 *phys_ptr
= address
;
10005 for (n
= 7; n
>= 0; n
--) {
10006 base
= env
->cp15
.c6_region
[n
];
10007 if ((base
& 1) == 0) {
10010 mask
= 1 << ((base
>> 1) & 0x1f);
10011 /* Keep this shift separate from the above to avoid an
10012 (undefined) << 32. */
10013 mask
= (mask
<< 1) - 1;
10014 if (((base
^ address
) & ~mask
) == 0) {
10019 fi
->type
= ARMFault_Background
;
10023 if (access_type
== MMU_INST_FETCH
) {
10024 mask
= env
->cp15
.pmsav5_insn_ap
;
10026 mask
= env
->cp15
.pmsav5_data_ap
;
10028 mask
= (mask
>> (n
* 4)) & 0xf;
10031 fi
->type
= ARMFault_Permission
;
10036 fi
->type
= ARMFault_Permission
;
10040 *prot
= PAGE_READ
| PAGE_WRITE
;
10045 *prot
|= PAGE_WRITE
;
10049 *prot
= PAGE_READ
| PAGE_WRITE
;
10053 fi
->type
= ARMFault_Permission
;
10063 /* Bad permission. */
10064 fi
->type
= ARMFault_Permission
;
10068 *prot
|= PAGE_EXEC
;
10072 /* Combine either inner or outer cacheability attributes for normal
10073 * memory, according to table D4-42 and pseudocode procedure
10074 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
10076 * NB: only stage 1 includes allocation hints (RW bits), leading to
10079 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
10081 if (s1
== 4 || s2
== 4) {
10082 /* non-cacheable has precedence */
10084 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
10085 /* stage 1 write-through takes precedence */
10087 } else if (extract32(s2
, 2, 2) == 2) {
10088 /* stage 2 write-through takes precedence, but the allocation hint
10089 * is still taken from stage 1
10091 return (2 << 2) | extract32(s1
, 0, 2);
10092 } else { /* write-back */
10097 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
10098 * and CombineS1S2Desc()
10100 * @s1: Attributes from stage 1 walk
10101 * @s2: Attributes from stage 2 walk
10103 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
10105 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
10106 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
10109 /* Combine shareability attributes (table D4-43) */
10110 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
10111 /* if either are outer-shareable, the result is outer-shareable */
10112 ret
.shareability
= 2;
10113 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
10114 /* if either are inner-shareable, the result is inner-shareable */
10115 ret
.shareability
= 3;
10117 /* both non-shareable */
10118 ret
.shareability
= 0;
10121 /* Combine memory type and cacheability attributes */
10122 if (s1hi
== 0 || s2hi
== 0) {
10123 /* Device has precedence over normal */
10124 if (s1lo
== 0 || s2lo
== 0) {
10125 /* nGnRnE has precedence over anything */
10127 } else if (s1lo
== 4 || s2lo
== 4) {
10128 /* non-Reordering has precedence over Reordering */
10129 ret
.attrs
= 4; /* nGnRE */
10130 } else if (s1lo
== 8 || s2lo
== 8) {
10131 /* non-Gathering has precedence over Gathering */
10132 ret
.attrs
= 8; /* nGRE */
10134 ret
.attrs
= 0xc; /* GRE */
10137 /* Any location for which the resultant memory type is any
10138 * type of Device memory is always treated as Outer Shareable.
10140 ret
.shareability
= 2;
10141 } else { /* Normal memory */
10142 /* Outer/inner cacheability combine independently */
10143 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
10144 | combine_cacheattr_nibble(s1lo
, s2lo
);
10146 if (ret
.attrs
== 0x44) {
10147 /* Any location for which the resultant memory type is Normal
10148 * Inner Non-cacheable, Outer Non-cacheable is always treated
10149 * as Outer Shareable.
10151 ret
.shareability
= 2;
10159 /* get_phys_addr - get the physical address for this virtual address
10161 * Find the physical address corresponding to the given virtual address,
10162 * by doing a translation table walk on MMU based systems or using the
10163 * MPU state on MPU based systems.
10165 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10166 * prot and page_size may not be filled in, and the populated fsr value provides
10167 * information on why the translation aborted, in the format of a
10168 * DFSR/IFSR fault register, with the following caveats:
10169 * * we honour the short vs long DFSR format differences.
10170 * * the WnR bit is never set (the caller must do this).
10171 * * for PSMAv5 based systems we don't bother to return a full FSR format
10174 * @env: CPUARMState
10175 * @address: virtual address to get physical address for
10176 * @access_type: 0 for read, 1 for write, 2 for execute
10177 * @mmu_idx: MMU index indicating required translation regime
10178 * @phys_ptr: set to the physical address corresponding to the virtual address
10179 * @attrs: set to the memory transaction attributes to use
10180 * @prot: set to the permissions for the page containing phys_ptr
10181 * @page_size: set to the size of the page containing phys_ptr
10182 * @fi: set to fault info if the translation fails
10183 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10185 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
10186 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10187 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10188 target_ulong
*page_size
,
10189 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10191 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
10192 /* Call ourselves recursively to do the stage 1 and then stage 2
10195 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
10199 ARMCacheAttrs cacheattrs2
= {};
10201 ret
= get_phys_addr(env
, address
, access_type
,
10202 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
10203 prot
, page_size
, fi
, cacheattrs
);
10205 /* If S1 fails or S2 is disabled, return early. */
10206 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
10211 /* S1 is done. Now do S2 translation. */
10212 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
10213 phys_ptr
, attrs
, &s2_prot
,
10215 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
10217 /* Combine the S1 and S2 perms. */
10220 /* Combine the S1 and S2 cache attributes, if needed */
10221 if (!ret
&& cacheattrs
!= NULL
) {
10222 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
10228 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
10230 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10234 /* The page table entries may downgrade secure to non-secure, but
10235 * cannot upgrade an non-secure translation regime's attributes
10238 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
10239 attrs
->user
= regime_is_user(env
, mmu_idx
);
10241 /* Fast Context Switch Extension. This doesn't exist at all in v8.
10242 * In v7 and earlier it affects all stage 1 translations.
10244 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
10245 && !arm_feature(env
, ARM_FEATURE_V8
)) {
10246 if (regime_el(env
, mmu_idx
) == 3) {
10247 address
+= env
->cp15
.fcseidr_s
;
10249 address
+= env
->cp15
.fcseidr_ns
;
10253 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
10255 *page_size
= TARGET_PAGE_SIZE
;
10257 if (arm_feature(env
, ARM_FEATURE_V8
)) {
10259 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
10260 phys_ptr
, attrs
, prot
, fi
);
10261 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10263 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
10264 phys_ptr
, prot
, fi
);
10267 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
10268 phys_ptr
, prot
, fi
);
10270 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
10271 " mmu_idx %u -> %s (prot %c%c%c)\n",
10272 access_type
== MMU_DATA_LOAD
? "reading" :
10273 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
10274 (uint32_t)address
, mmu_idx
,
10275 ret
? "Miss" : "Hit",
10276 *prot
& PAGE_READ
? 'r' : '-',
10277 *prot
& PAGE_WRITE
? 'w' : '-',
10278 *prot
& PAGE_EXEC
? 'x' : '-');
10283 /* Definitely a real MMU, not an MPU */
10285 if (regime_translation_disabled(env
, mmu_idx
)) {
10286 /* MMU disabled. */
10287 *phys_ptr
= address
;
10288 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10289 *page_size
= TARGET_PAGE_SIZE
;
10293 if (regime_using_lpae_format(env
, mmu_idx
)) {
10294 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
10295 phys_ptr
, attrs
, prot
, page_size
,
10297 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
10298 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
10299 phys_ptr
, attrs
, prot
, page_size
, fi
);
10301 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
10302 phys_ptr
, prot
, page_size
, fi
);
10306 /* Walk the page table and (if the mapping exists) add the page
10307 * to the TLB. Return false on success, or true on failure. Populate
10308 * fsr with ARM DFSR/IFSR fault register format value on failure.
10310 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
10311 MMUAccessType access_type
, int mmu_idx
,
10312 ARMMMUFaultInfo
*fi
)
10314 ARMCPU
*cpu
= ARM_CPU(cs
);
10315 CPUARMState
*env
= &cpu
->env
;
10317 target_ulong page_size
;
10320 MemTxAttrs attrs
= {};
10322 ret
= get_phys_addr(env
, address
, access_type
,
10323 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
10324 &attrs
, &prot
, &page_size
, fi
, NULL
);
10326 /* Map a single [sub]page. */
10327 phys_addr
&= TARGET_PAGE_MASK
;
10328 address
&= TARGET_PAGE_MASK
;
10329 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
10330 prot
, mmu_idx
, page_size
);
10337 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
10340 ARMCPU
*cpu
= ARM_CPU(cs
);
10341 CPUARMState
*env
= &cpu
->env
;
10343 target_ulong page_size
;
10346 ARMMMUFaultInfo fi
= {};
10347 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
10349 *attrs
= (MemTxAttrs
) {};
10351 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
10352 attrs
, &prot
, &page_size
, &fi
, NULL
);
10360 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
10363 unsigned el
= arm_current_el(env
);
10365 /* First handle registers which unprivileged can read */
10368 case 0 ... 7: /* xPSR sub-fields */
10370 if ((reg
& 1) && el
) {
10371 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
10374 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
10376 /* EPSR reads as zero */
10377 return xpsr_read(env
) & mask
;
10379 case 20: /* CONTROL */
10380 return env
->v7m
.control
[env
->v7m
.secure
];
10381 case 0x94: /* CONTROL_NS */
10382 /* We have to handle this here because unprivileged Secure code
10383 * can read the NS CONTROL register.
10385 if (!env
->v7m
.secure
) {
10388 return env
->v7m
.control
[M_REG_NS
];
10392 return 0; /* unprivileged reads others as zero */
10395 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10397 case 0x88: /* MSP_NS */
10398 if (!env
->v7m
.secure
) {
10401 return env
->v7m
.other_ss_msp
;
10402 case 0x89: /* PSP_NS */
10403 if (!env
->v7m
.secure
) {
10406 return env
->v7m
.other_ss_psp
;
10407 case 0x8a: /* MSPLIM_NS */
10408 if (!env
->v7m
.secure
) {
10411 return env
->v7m
.msplim
[M_REG_NS
];
10412 case 0x8b: /* PSPLIM_NS */
10413 if (!env
->v7m
.secure
) {
10416 return env
->v7m
.psplim
[M_REG_NS
];
10417 case 0x90: /* PRIMASK_NS */
10418 if (!env
->v7m
.secure
) {
10421 return env
->v7m
.primask
[M_REG_NS
];
10422 case 0x91: /* BASEPRI_NS */
10423 if (!env
->v7m
.secure
) {
10426 return env
->v7m
.basepri
[M_REG_NS
];
10427 case 0x93: /* FAULTMASK_NS */
10428 if (!env
->v7m
.secure
) {
10431 return env
->v7m
.faultmask
[M_REG_NS
];
10432 case 0x98: /* SP_NS */
10434 /* This gives the non-secure SP selected based on whether we're
10435 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10437 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10439 if (!env
->v7m
.secure
) {
10442 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10443 return env
->v7m
.other_ss_psp
;
10445 return env
->v7m
.other_ss_msp
;
10455 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
10457 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
10458 case 10: /* MSPLIM */
10459 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10462 return env
->v7m
.msplim
[env
->v7m
.secure
];
10463 case 11: /* PSPLIM */
10464 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10467 return env
->v7m
.psplim
[env
->v7m
.secure
];
10468 case 16: /* PRIMASK */
10469 return env
->v7m
.primask
[env
->v7m
.secure
];
10470 case 17: /* BASEPRI */
10471 case 18: /* BASEPRI_MAX */
10472 return env
->v7m
.basepri
[env
->v7m
.secure
];
10473 case 19: /* FAULTMASK */
10474 return env
->v7m
.faultmask
[env
->v7m
.secure
];
10477 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
10478 " register %d\n", reg
);
10483 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
10485 /* We're passed bits [11..0] of the instruction; extract
10486 * SYSm and the mask bits.
10487 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
10488 * we choose to treat them as if the mask bits were valid.
10489 * NB that the pseudocode 'mask' variable is bits [11..10],
10490 * whereas ours is [11..8].
10492 uint32_t mask
= extract32(maskreg
, 8, 4);
10493 uint32_t reg
= extract32(maskreg
, 0, 8);
10495 if (arm_current_el(env
) == 0 && reg
> 7) {
10496 /* only xPSR sub-fields may be written by unprivileged */
10500 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10502 case 0x88: /* MSP_NS */
10503 if (!env
->v7m
.secure
) {
10506 env
->v7m
.other_ss_msp
= val
;
10508 case 0x89: /* PSP_NS */
10509 if (!env
->v7m
.secure
) {
10512 env
->v7m
.other_ss_psp
= val
;
10514 case 0x8a: /* MSPLIM_NS */
10515 if (!env
->v7m
.secure
) {
10518 env
->v7m
.msplim
[M_REG_NS
] = val
& ~7;
10520 case 0x8b: /* PSPLIM_NS */
10521 if (!env
->v7m
.secure
) {
10524 env
->v7m
.psplim
[M_REG_NS
] = val
& ~7;
10526 case 0x90: /* PRIMASK_NS */
10527 if (!env
->v7m
.secure
) {
10530 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
10532 case 0x91: /* BASEPRI_NS */
10533 if (!env
->v7m
.secure
) {
10536 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
10538 case 0x93: /* FAULTMASK_NS */
10539 if (!env
->v7m
.secure
) {
10542 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
10544 case 0x94: /* CONTROL_NS */
10545 if (!env
->v7m
.secure
) {
10548 write_v7m_control_spsel_for_secstate(env
,
10549 val
& R_V7M_CONTROL_SPSEL_MASK
,
10551 env
->v7m
.control
[M_REG_NS
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
10552 env
->v7m
.control
[M_REG_NS
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
10554 case 0x98: /* SP_NS */
10556 /* This gives the non-secure SP selected based on whether we're
10557 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10559 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10561 if (!env
->v7m
.secure
) {
10564 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10565 env
->v7m
.other_ss_psp
= val
;
10567 env
->v7m
.other_ss_msp
= val
;
10577 case 0 ... 7: /* xPSR sub-fields */
10578 /* only APSR is actually writable */
10580 uint32_t apsrmask
= 0;
10583 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
10585 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
10586 apsrmask
|= XPSR_GE
;
10588 xpsr_write(env
, val
, apsrmask
);
10592 if (v7m_using_psp(env
)) {
10593 env
->v7m
.other_sp
= val
;
10595 env
->regs
[13] = val
;
10599 if (v7m_using_psp(env
)) {
10600 env
->regs
[13] = val
;
10602 env
->v7m
.other_sp
= val
;
10605 case 10: /* MSPLIM */
10606 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10609 env
->v7m
.msplim
[env
->v7m
.secure
] = val
& ~7;
10611 case 11: /* PSPLIM */
10612 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10615 env
->v7m
.psplim
[env
->v7m
.secure
] = val
& ~7;
10617 case 16: /* PRIMASK */
10618 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
10620 case 17: /* BASEPRI */
10621 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
10623 case 18: /* BASEPRI_MAX */
10625 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
10626 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
10627 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
10630 case 19: /* FAULTMASK */
10631 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
10633 case 20: /* CONTROL */
10634 /* Writing to the SPSEL bit only has an effect if we are in
10635 * thread mode; other bits can be updated by any privileged code.
10636 * write_v7m_control_spsel() deals with updating the SPSEL bit in
10637 * env->v7m.control, so we only need update the others.
10638 * For v7M, we must just ignore explicit writes to SPSEL in handler
10639 * mode; for v8M the write is permitted but will have no effect.
10641 if (arm_feature(env
, ARM_FEATURE_V8
) ||
10642 !arm_v7m_is_handler_mode(env
)) {
10643 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
10645 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
10646 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
10650 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
10651 " register %d\n", reg
);
10656 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
10658 /* Implement the TT instruction. op is bits [7:6] of the insn. */
10659 bool forceunpriv
= op
& 1;
10661 V8M_SAttributes sattrs
= {};
10663 bool r
, rw
, nsr
, nsrw
, mrvalid
;
10665 ARMMMUFaultInfo fi
= {};
10666 MemTxAttrs attrs
= {};
10671 bool targetsec
= env
->v7m
.secure
;
10673 /* Work out what the security state and privilege level we're
10674 * interested in is...
10677 targetsec
= !targetsec
;
10681 targetpriv
= false;
10683 targetpriv
= arm_v7m_is_handler_mode(env
) ||
10684 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
10687 /* ...and then figure out which MMU index this is */
10688 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
10690 /* We know that the MPU and SAU don't care about the access type
10691 * for our purposes beyond that we don't want to claim to be
10692 * an insn fetch, so we arbitrarily call this a read.
10695 /* MPU region info only available for privileged or if
10696 * inspecting the other MPU state.
10698 if (arm_current_el(env
) != 0 || alt
) {
10699 /* We can ignore the return value as prot is always set */
10700 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
10701 &phys_addr
, &attrs
, &prot
, &fi
, &mregion
);
10702 if (mregion
== -1) {
10708 r
= prot
& PAGE_READ
;
10709 rw
= prot
& PAGE_WRITE
;
10717 if (env
->v7m
.secure
) {
10718 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
10719 nsr
= sattrs
.ns
&& r
;
10720 nsrw
= sattrs
.ns
&& rw
;
10727 tt_resp
= (sattrs
.iregion
<< 24) |
10728 (sattrs
.irvalid
<< 23) |
10729 ((!sattrs
.ns
) << 22) |
10734 (sattrs
.srvalid
<< 17) |
10736 (sattrs
.sregion
<< 8) |
10744 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
10746 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
10747 * Note that we do not implement the (architecturally mandated)
10748 * alignment fault for attempts to use this on Device memory
10749 * (which matches the usual QEMU behaviour of not implementing either
10750 * alignment faults or any memory attribute handling).
10753 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10754 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
10755 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
10757 #ifndef CONFIG_USER_ONLY
10759 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
10760 * the block size so we might have to do more than one TLB lookup.
10761 * We know that in fact for any v8 CPU the page size is at least 4K
10762 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
10763 * 1K as an artefact of legacy v5 subpage support being present in the
10764 * same QEMU executable.
10766 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
10767 void *hostaddr
[maxidx
];
10769 unsigned mmu_idx
= cpu_mmu_index(env
, false);
10770 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
10772 for (try = 0; try < 2; try++) {
10774 for (i
= 0; i
< maxidx
; i
++) {
10775 hostaddr
[i
] = tlb_vaddr_to_host(env
,
10776 vaddr
+ TARGET_PAGE_SIZE
* i
,
10778 if (!hostaddr
[i
]) {
10783 /* If it's all in the TLB it's fair game for just writing to;
10784 * we know we don't need to update dirty status, etc.
10786 for (i
= 0; i
< maxidx
- 1; i
++) {
10787 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
10789 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
10792 /* OK, try a store and see if we can populate the tlb. This
10793 * might cause an exception if the memory isn't writable,
10794 * in which case we will longjmp out of here. We must for
10795 * this purpose use the actual register value passed to us
10796 * so that we get the fault address right.
10798 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
10799 /* Now we can populate the other TLB entries, if any */
10800 for (i
= 0; i
< maxidx
; i
++) {
10801 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
10802 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
10803 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
10808 /* Slow path (probably attempt to do this to an I/O device or
10809 * similar, or clearing of a block of code we have translations
10810 * cached for). Just do a series of byte writes as the architecture
10811 * demands. It's not worth trying to use a cpu_physical_memory_map(),
10812 * memset(), unmap() sequence here because:
10813 * + we'd need to account for the blocksize being larger than a page
10814 * + the direct-RAM access case is almost always going to be dealt
10815 * with in the fastpath code above, so there's no speed benefit
10816 * + we would have to deal with the map returning NULL because the
10817 * bounce buffer was in use
10819 for (i
= 0; i
< blocklen
; i
++) {
10820 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
10824 memset(g2h(vaddr
), 0, blocklen
);
10828 /* Note that signed overflow is undefined in C. The following routines are
10829 careful to use unsigned types where modulo arithmetic is required.
10830 Failure to do so _will_ break on newer gcc. */
10832 /* Signed saturating arithmetic. */
10834 /* Perform 16-bit signed saturating addition. */
10835 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10840 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10849 /* Perform 8-bit signed saturating addition. */
10850 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10855 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10864 /* Perform 16-bit signed saturating subtraction. */
10865 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10870 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10879 /* Perform 8-bit signed saturating subtraction. */
10880 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10885 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10894 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10895 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10896 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10897 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10900 #include "op_addsub.h"
10902 /* Unsigned saturating arithmetic. */
10903 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10912 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10920 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10929 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10937 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10938 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10939 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10940 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10943 #include "op_addsub.h"
10945 /* Signed modulo arithmetic. */
10946 #define SARITH16(a, b, n, op) do { \
10948 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10949 RESULT(sum, n, 16); \
10951 ge |= 3 << (n * 2); \
10954 #define SARITH8(a, b, n, op) do { \
10956 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10957 RESULT(sum, n, 8); \
10963 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10964 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10965 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10966 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10970 #include "op_addsub.h"
10972 /* Unsigned modulo arithmetic. */
10973 #define ADD16(a, b, n) do { \
10975 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10976 RESULT(sum, n, 16); \
10977 if ((sum >> 16) == 1) \
10978 ge |= 3 << (n * 2); \
10981 #define ADD8(a, b, n) do { \
10983 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10984 RESULT(sum, n, 8); \
10985 if ((sum >> 8) == 1) \
10989 #define SUB16(a, b, n) do { \
10991 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10992 RESULT(sum, n, 16); \
10993 if ((sum >> 16) == 0) \
10994 ge |= 3 << (n * 2); \
10997 #define SUB8(a, b, n) do { \
10999 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11000 RESULT(sum, n, 8); \
11001 if ((sum >> 8) == 0) \
11008 #include "op_addsub.h"
11010 /* Halved signed arithmetic. */
11011 #define ADD16(a, b, n) \
11012 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11013 #define SUB16(a, b, n) \
11014 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11015 #define ADD8(a, b, n) \
11016 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11017 #define SUB8(a, b, n) \
11018 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11021 #include "op_addsub.h"
11023 /* Halved unsigned arithmetic. */
11024 #define ADD16(a, b, n) \
11025 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11026 #define SUB16(a, b, n) \
11027 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11028 #define ADD8(a, b, n) \
11029 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11030 #define SUB8(a, b, n) \
11031 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11034 #include "op_addsub.h"
11036 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11044 /* Unsigned sum of absolute byte differences. */
11045 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11048 sum
= do_usad(a
, b
);
11049 sum
+= do_usad(a
>> 8, b
>> 8);
11050 sum
+= do_usad(a
>> 16, b
>>16);
11051 sum
+= do_usad(a
>> 24, b
>> 24);
11055 /* For ARMv6 SEL instruction. */
11056 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11068 mask
|= 0xff000000;
11069 return (a
& mask
) | (b
& ~mask
);
11072 /* VFP support. We follow the convention used for VFP instructions:
11073 Single precision routines have a "s" suffix, double precision a
11076 /* Convert host exception flags to vfp form. */
11077 static inline int vfp_exceptbits_from_host(int host_bits
)
11079 int target_bits
= 0;
11081 if (host_bits
& float_flag_invalid
)
11083 if (host_bits
& float_flag_divbyzero
)
11085 if (host_bits
& float_flag_overflow
)
11087 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
11089 if (host_bits
& float_flag_inexact
)
11090 target_bits
|= 0x10;
11091 if (host_bits
& float_flag_input_denormal
)
11092 target_bits
|= 0x80;
11093 return target_bits
;
11096 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
11101 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
11102 | (env
->vfp
.vec_len
<< 16)
11103 | (env
->vfp
.vec_stride
<< 20);
11104 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
11105 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
11106 i
|= get_float_exception_flags(&env
->vfp
.fp_status_f16
);
11107 fpscr
|= vfp_exceptbits_from_host(i
);
11111 uint32_t vfp_get_fpscr(CPUARMState
*env
)
11113 return HELPER(vfp_get_fpscr
)(env
);
11116 /* Convert vfp exception flags to target form. */
11117 static inline int vfp_exceptbits_to_host(int target_bits
)
11121 if (target_bits
& 1)
11122 host_bits
|= float_flag_invalid
;
11123 if (target_bits
& 2)
11124 host_bits
|= float_flag_divbyzero
;
11125 if (target_bits
& 4)
11126 host_bits
|= float_flag_overflow
;
11127 if (target_bits
& 8)
11128 host_bits
|= float_flag_underflow
;
11129 if (target_bits
& 0x10)
11130 host_bits
|= float_flag_inexact
;
11131 if (target_bits
& 0x80)
11132 host_bits
|= float_flag_input_denormal
;
11136 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
11141 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
11142 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
11143 env
->vfp
.vec_len
= (val
>> 16) & 7;
11144 env
->vfp
.vec_stride
= (val
>> 20) & 3;
11147 if (changed
& (3 << 22)) {
11148 i
= (val
>> 22) & 3;
11150 case FPROUNDING_TIEEVEN
:
11151 i
= float_round_nearest_even
;
11153 case FPROUNDING_POSINF
:
11154 i
= float_round_up
;
11156 case FPROUNDING_NEGINF
:
11157 i
= float_round_down
;
11159 case FPROUNDING_ZERO
:
11160 i
= float_round_to_zero
;
11163 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
11164 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
11166 if (changed
& FPCR_FZ16
) {
11167 bool ftz_enabled
= val
& FPCR_FZ16
;
11168 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
11169 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
11171 if (changed
& FPCR_FZ
) {
11172 bool ftz_enabled
= val
& FPCR_FZ
;
11173 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
11174 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
11176 if (changed
& FPCR_DN
) {
11177 bool dnan_enabled
= val
& FPCR_DN
;
11178 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
11179 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
11182 /* The exception flags are ORed together when we read fpscr so we
11183 * only need to preserve the current state in one of our
11184 * float_status values.
11186 i
= vfp_exceptbits_to_host(val
);
11187 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
11188 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
11189 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
11192 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
11194 HELPER(vfp_set_fpscr
)(env
, val
);
11197 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
11199 #define VFP_BINOP(name) \
11200 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
11202 float_status *fpst = fpstp; \
11203 return float32_ ## name(a, b, fpst); \
11205 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
11207 float_status *fpst = fpstp; \
11208 return float64_ ## name(a, b, fpst); \
11220 float32
VFP_HELPER(neg
, s
)(float32 a
)
11222 return float32_chs(a
);
11225 float64
VFP_HELPER(neg
, d
)(float64 a
)
11227 return float64_chs(a
);
11230 float32
VFP_HELPER(abs
, s
)(float32 a
)
11232 return float32_abs(a
);
11235 float64
VFP_HELPER(abs
, d
)(float64 a
)
11237 return float64_abs(a
);
11240 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
11242 return float32_sqrt(a
, &env
->vfp
.fp_status
);
11245 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
11247 return float64_sqrt(a
, &env
->vfp
.fp_status
);
11250 /* XXX: check quiet/signaling case */
11251 #define DO_VFP_cmp(p, type) \
11252 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
11255 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
11256 case 0: flags = 0x6; break; \
11257 case -1: flags = 0x8; break; \
11258 case 1: flags = 0x2; break; \
11259 default: case 2: flags = 0x3; break; \
11261 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11262 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11264 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
11267 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
11268 case 0: flags = 0x6; break; \
11269 case -1: flags = 0x8; break; \
11270 case 1: flags = 0x2; break; \
11271 default: case 2: flags = 0x3; break; \
11273 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11274 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11276 DO_VFP_cmp(s
, float32
)
11277 DO_VFP_cmp(d
, float64
)
11280 /* Integer to float and float to integer conversions */
11282 #define CONV_ITOF(name, fsz, sign) \
11283 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
11285 float_status *fpst = fpstp; \
11286 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
11289 #define CONV_FTOI(name, fsz, sign, round) \
11290 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
11292 float_status *fpst = fpstp; \
11293 if (float##fsz##_is_any_nan(x)) { \
11294 float_raise(float_flag_invalid, fpst); \
11297 return float##fsz##_to_##sign##int32##round(x, fpst); \
11300 #define FLOAT_CONVS(name, p, fsz, sign) \
11301 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
11302 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
11303 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
11305 FLOAT_CONVS(si
, h
, 16, )
11306 FLOAT_CONVS(si
, s
, 32, )
11307 FLOAT_CONVS(si
, d
, 64, )
11308 FLOAT_CONVS(ui
, h
, 16, u
)
11309 FLOAT_CONVS(ui
, s
, 32, u
)
11310 FLOAT_CONVS(ui
, d
, 64, u
)
11316 /* floating point conversion */
11317 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
11319 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
11320 /* ARM requires that S<->D conversion of any kind of NaN generates
11321 * a quiet NaN by forcing the most significant frac bit to 1.
11323 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
11326 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
11328 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
11329 /* ARM requires that S<->D conversion of any kind of NaN generates
11330 * a quiet NaN by forcing the most significant frac bit to 1.
11332 return float32_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
11335 /* VFP3 fixed point conversion. */
11336 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11337 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
11340 float_status *fpst = fpstp; \
11342 tmp = itype##_to_##float##fsz(x, fpst); \
11343 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
11346 /* Notice that we want only input-denormal exception flags from the
11347 * scalbn operation: the other possible flags (overflow+inexact if
11348 * we overflow to infinity, output-denormal) aren't correct for the
11349 * complete scale-and-convert operation.
11351 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
11352 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
11356 float_status *fpst = fpstp; \
11357 int old_exc_flags = get_float_exception_flags(fpst); \
11359 if (float##fsz##_is_any_nan(x)) { \
11360 float_raise(float_flag_invalid, fpst); \
11363 tmp = float##fsz##_scalbn(x, shift, fpst); \
11364 old_exc_flags |= get_float_exception_flags(fpst) \
11365 & float_flag_input_denormal; \
11366 set_float_exception_flags(old_exc_flags, fpst); \
11367 return float##fsz##_to_##itype##round(tmp, fpst); \
11370 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
11371 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11372 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
11373 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
11375 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
11376 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11377 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
11379 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
11380 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
11381 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
11382 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
11383 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
11384 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
11385 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
11386 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
11387 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
11388 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
11389 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
11390 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
11391 VFP_CONV_FIX_A64(sl
, h
, 16, 32, int32
)
11392 VFP_CONV_FIX_A64(ul
, h
, 16, 32, uint32
)
11393 #undef VFP_CONV_FIX
11394 #undef VFP_CONV_FIX_FLOAT
11395 #undef VFP_CONV_FLOAT_FIX_ROUND
11397 /* Set the current fp rounding mode and return the old one.
11398 * The argument is a softfloat float_round_ value.
11400 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
11402 float_status
*fp_status
= fpstp
;
11404 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
11405 set_float_rounding_mode(rmode
, fp_status
);
11410 /* Set the current fp rounding mode in the standard fp status and return
11411 * the old one. This is for NEON instructions that need to change the
11412 * rounding mode but wish to use the standard FPSCR values for everything
11413 * else. Always set the rounding mode back to the correct value after
11415 * The argument is a softfloat float_round_ value.
11417 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
11419 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
11421 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
11422 set_float_rounding_mode(rmode
, fp_status
);
11427 /* Half precision conversions. */
11428 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
11430 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11431 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
11433 return float32_maybe_silence_nan(r
, s
);
11438 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
11440 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11441 float16 r
= float32_to_float16(a
, ieee
, s
);
11443 r
= float16_maybe_silence_nan(r
, s
);
11445 return float16_val(r
);
11448 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
11450 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
11453 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
11455 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
11458 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
11460 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
11463 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
11465 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
11468 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
11470 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11471 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
11473 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
11478 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
11480 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11481 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
11483 r
= float16_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
11485 return float16_val(r
);
11488 #define float32_two make_float32(0x40000000)
11489 #define float32_three make_float32(0x40400000)
11490 #define float32_one_point_five make_float32(0x3fc00000)
11492 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11494 float_status
*s
= &env
->vfp
.standard_fp_status
;
11495 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11496 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11497 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11498 float_raise(float_flag_input_denormal
, s
);
11500 return float32_two
;
11502 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
11505 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11507 float_status
*s
= &env
->vfp
.standard_fp_status
;
11509 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11510 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11511 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11512 float_raise(float_flag_input_denormal
, s
);
11514 return float32_one_point_five
;
11516 product
= float32_mul(a
, b
, s
);
11517 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
11520 /* NEON helpers. */
11522 /* Constants 256 and 512 are used in some helpers; we avoid relying on
11523 * int->float conversions at run-time. */
11524 #define float64_256 make_float64(0x4070000000000000LL)
11525 #define float64_512 make_float64(0x4080000000000000LL)
11526 #define float16_maxnorm make_float16(0x7bff)
11527 #define float32_maxnorm make_float32(0x7f7fffff)
11528 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
11530 /* Reciprocal functions
11532 * The algorithm that must be used to calculate the estimate
11533 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
11536 /* See RecipEstimate()
11538 * input is a 9 bit fixed point number
11539 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
11540 * result range 256 .. 511 for a number from 1.0 to 511/256.
11543 static int recip_estimate(int input
)
11546 assert(256 <= input
&& input
< 512);
11547 a
= (input
* 2) + 1;
11550 assert(256 <= r
&& r
< 512);
11555 * Common wrapper to call recip_estimate
11557 * The parameters are exponent and 64 bit fraction (without implicit
11558 * bit) where the binary point is nominally at bit 52. Returns a
11559 * float64 which can then be rounded to the appropriate size by the
11563 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
11565 uint32_t scaled
, estimate
;
11566 uint64_t result_frac
;
11569 /* Handle sub-normals */
11571 if (extract64(frac
, 51, 1) == 0) {
11579 /* scaled = UInt('1':fraction<51:44>) */
11580 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
11581 estimate
= recip_estimate(scaled
);
11583 result_exp
= exp_off
- *exp
;
11584 result_frac
= deposit64(0, 44, 8, estimate
);
11585 if (result_exp
== 0) {
11586 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
11587 } else if (result_exp
== -1) {
11588 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
11594 return result_frac
;
11597 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
11599 switch (fpst
->float_rounding_mode
) {
11600 case float_round_nearest_even
: /* Round to Nearest */
11602 case float_round_up
: /* Round to +Inf */
11604 case float_round_down
: /* Round to -Inf */
11606 case float_round_to_zero
: /* Round to Zero */
11610 g_assert_not_reached();
11613 float16
HELPER(recpe_f16
)(float16 input
, void *fpstp
)
11615 float_status
*fpst
= fpstp
;
11616 float16 f16
= float16_squash_input_denormal(input
, fpst
);
11617 uint32_t f16_val
= float16_val(f16
);
11618 uint32_t f16_sign
= float16_is_neg(f16
);
11619 int f16_exp
= extract32(f16_val
, 10, 5);
11620 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
11623 if (float16_is_any_nan(f16
)) {
11625 if (float16_is_signaling_nan(f16
, fpst
)) {
11626 float_raise(float_flag_invalid
, fpst
);
11627 nan
= float16_maybe_silence_nan(f16
, fpst
);
11629 if (fpst
->default_nan_mode
) {
11630 nan
= float16_default_nan(fpst
);
11633 } else if (float16_is_infinity(f16
)) {
11634 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
11635 } else if (float16_is_zero(f16
)) {
11636 float_raise(float_flag_divbyzero
, fpst
);
11637 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
11638 } else if (float16_abs(f16
) < (1 << 8)) {
11639 /* Abs(value) < 2.0^-16 */
11640 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11641 if (round_to_inf(fpst
, f16_sign
)) {
11642 return float16_set_sign(float16_infinity
, f16_sign
);
11644 return float16_set_sign(float16_maxnorm
, f16_sign
);
11646 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
11647 float_raise(float_flag_underflow
, fpst
);
11648 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
11651 f64_frac
= call_recip_estimate(&f16_exp
, 29,
11652 ((uint64_t) f16_frac
) << (52 - 10));
11654 /* result = sign : result_exp<4:0> : fraction<51:42> */
11655 f16_val
= deposit32(0, 15, 1, f16_sign
);
11656 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
11657 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
11658 return make_float16(f16_val
);
11661 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
11663 float_status
*fpst
= fpstp
;
11664 float32 f32
= float32_squash_input_denormal(input
, fpst
);
11665 uint32_t f32_val
= float32_val(f32
);
11666 bool f32_sign
= float32_is_neg(f32
);
11667 int f32_exp
= extract32(f32_val
, 23, 8);
11668 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
11671 if (float32_is_any_nan(f32
)) {
11673 if (float32_is_signaling_nan(f32
, fpst
)) {
11674 float_raise(float_flag_invalid
, fpst
);
11675 nan
= float32_maybe_silence_nan(f32
, fpst
);
11677 if (fpst
->default_nan_mode
) {
11678 nan
= float32_default_nan(fpst
);
11681 } else if (float32_is_infinity(f32
)) {
11682 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
11683 } else if (float32_is_zero(f32
)) {
11684 float_raise(float_flag_divbyzero
, fpst
);
11685 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
11686 } else if (float32_abs(f32
) < (1ULL << 21)) {
11687 /* Abs(value) < 2.0^-128 */
11688 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11689 if (round_to_inf(fpst
, f32_sign
)) {
11690 return float32_set_sign(float32_infinity
, f32_sign
);
11692 return float32_set_sign(float32_maxnorm
, f32_sign
);
11694 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
11695 float_raise(float_flag_underflow
, fpst
);
11696 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
11699 f64_frac
= call_recip_estimate(&f32_exp
, 253,
11700 ((uint64_t) f32_frac
) << (52 - 23));
11702 /* result = sign : result_exp<7:0> : fraction<51:29> */
11703 f32_val
= deposit32(0, 31, 1, f32_sign
);
11704 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
11705 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
11706 return make_float32(f32_val
);
11709 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
11711 float_status
*fpst
= fpstp
;
11712 float64 f64
= float64_squash_input_denormal(input
, fpst
);
11713 uint64_t f64_val
= float64_val(f64
);
11714 bool f64_sign
= float64_is_neg(f64
);
11715 int f64_exp
= extract64(f64_val
, 52, 11);
11716 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
11718 /* Deal with any special cases */
11719 if (float64_is_any_nan(f64
)) {
11721 if (float64_is_signaling_nan(f64
, fpst
)) {
11722 float_raise(float_flag_invalid
, fpst
);
11723 nan
= float64_maybe_silence_nan(f64
, fpst
);
11725 if (fpst
->default_nan_mode
) {
11726 nan
= float64_default_nan(fpst
);
11729 } else if (float64_is_infinity(f64
)) {
11730 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
11731 } else if (float64_is_zero(f64
)) {
11732 float_raise(float_flag_divbyzero
, fpst
);
11733 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11734 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
11735 /* Abs(value) < 2.0^-1024 */
11736 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11737 if (round_to_inf(fpst
, f64_sign
)) {
11738 return float64_set_sign(float64_infinity
, f64_sign
);
11740 return float64_set_sign(float64_maxnorm
, f64_sign
);
11742 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
11743 float_raise(float_flag_underflow
, fpst
);
11744 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
11747 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
11749 /* result = sign : result_exp<10:0> : fraction<51:0>; */
11750 f64_val
= deposit64(0, 63, 1, f64_sign
);
11751 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
11752 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
11753 return make_float64(f64_val
);
11756 /* The algorithm that must be used to calculate the estimate
11757 * is specified by the ARM ARM.
11760 static int do_recip_sqrt_estimate(int a
)
11764 assert(128 <= a
&& a
< 512);
11772 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
11775 estimate
= (b
+ 1) / 2;
11776 assert(256 <= estimate
&& estimate
< 512);
11782 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
11788 while (extract64(frac
, 51, 1) == 0) {
11792 frac
= extract64(frac
, 0, 51) << 1;
11796 /* scaled = UInt('01':fraction<51:45>) */
11797 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
11799 /* scaled = UInt('1':fraction<51:44>) */
11800 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
11802 estimate
= do_recip_sqrt_estimate(scaled
);
11804 *exp
= (exp_off
- *exp
) / 2;
11805 return extract64(estimate
, 0, 8) << 44;
11808 float16
HELPER(rsqrte_f16
)(float16 input
, void *fpstp
)
11810 float_status
*s
= fpstp
;
11811 float16 f16
= float16_squash_input_denormal(input
, s
);
11812 uint16_t val
= float16_val(f16
);
11813 bool f16_sign
= float16_is_neg(f16
);
11814 int f16_exp
= extract32(val
, 10, 5);
11815 uint16_t f16_frac
= extract32(val
, 0, 10);
11818 if (float16_is_any_nan(f16
)) {
11820 if (float16_is_signaling_nan(f16
, s
)) {
11821 float_raise(float_flag_invalid
, s
);
11822 nan
= float16_maybe_silence_nan(f16
, s
);
11824 if (s
->default_nan_mode
) {
11825 nan
= float16_default_nan(s
);
11828 } else if (float16_is_zero(f16
)) {
11829 float_raise(float_flag_divbyzero
, s
);
11830 return float16_set_sign(float16_infinity
, f16_sign
);
11831 } else if (f16_sign
) {
11832 float_raise(float_flag_invalid
, s
);
11833 return float16_default_nan(s
);
11834 } else if (float16_is_infinity(f16
)) {
11835 return float16_zero
;
11838 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
11839 * preserving the parity of the exponent. */
11841 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
11843 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
11845 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
11846 val
= deposit32(0, 15, 1, f16_sign
);
11847 val
= deposit32(val
, 10, 5, f16_exp
);
11848 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
11849 return make_float16(val
);
11852 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
11854 float_status
*s
= fpstp
;
11855 float32 f32
= float32_squash_input_denormal(input
, s
);
11856 uint32_t val
= float32_val(f32
);
11857 uint32_t f32_sign
= float32_is_neg(f32
);
11858 int f32_exp
= extract32(val
, 23, 8);
11859 uint32_t f32_frac
= extract32(val
, 0, 23);
11862 if (float32_is_any_nan(f32
)) {
11864 if (float32_is_signaling_nan(f32
, s
)) {
11865 float_raise(float_flag_invalid
, s
);
11866 nan
= float32_maybe_silence_nan(f32
, s
);
11868 if (s
->default_nan_mode
) {
11869 nan
= float32_default_nan(s
);
11872 } else if (float32_is_zero(f32
)) {
11873 float_raise(float_flag_divbyzero
, s
);
11874 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
11875 } else if (float32_is_neg(f32
)) {
11876 float_raise(float_flag_invalid
, s
);
11877 return float32_default_nan(s
);
11878 } else if (float32_is_infinity(f32
)) {
11879 return float32_zero
;
11882 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
11883 * preserving the parity of the exponent. */
11885 f64_frac
= ((uint64_t) f32_frac
) << 29;
11887 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
11889 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
11890 val
= deposit32(0, 31, 1, f32_sign
);
11891 val
= deposit32(val
, 23, 8, f32_exp
);
11892 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
11893 return make_float32(val
);
11896 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
11898 float_status
*s
= fpstp
;
11899 float64 f64
= float64_squash_input_denormal(input
, s
);
11900 uint64_t val
= float64_val(f64
);
11901 bool f64_sign
= float64_is_neg(f64
);
11902 int f64_exp
= extract64(val
, 52, 11);
11903 uint64_t f64_frac
= extract64(val
, 0, 52);
11905 if (float64_is_any_nan(f64
)) {
11907 if (float64_is_signaling_nan(f64
, s
)) {
11908 float_raise(float_flag_invalid
, s
);
11909 nan
= float64_maybe_silence_nan(f64
, s
);
11911 if (s
->default_nan_mode
) {
11912 nan
= float64_default_nan(s
);
11915 } else if (float64_is_zero(f64
)) {
11916 float_raise(float_flag_divbyzero
, s
);
11917 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11918 } else if (float64_is_neg(f64
)) {
11919 float_raise(float_flag_invalid
, s
);
11920 return float64_default_nan(s
);
11921 } else if (float64_is_infinity(f64
)) {
11922 return float64_zero
;
11925 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
11927 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
11928 val
= deposit64(0, 61, 1, f64_sign
);
11929 val
= deposit64(val
, 52, 11, f64_exp
);
11930 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
11931 return make_float64(val
);
11934 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
11936 /* float_status *s = fpstp; */
11937 int input
, estimate
;
11939 if ((a
& 0x80000000) == 0) {
11943 input
= extract32(a
, 23, 9);
11944 estimate
= recip_estimate(input
);
11946 return deposit32(0, (32 - 9), 9, estimate
);
11949 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
11953 if ((a
& 0xc0000000) == 0) {
11957 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
11959 return deposit32(0, 23, 9, estimate
);
11962 /* VFPv4 fused multiply-accumulate */
11963 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
11965 float_status
*fpst
= fpstp
;
11966 return float32_muladd(a
, b
, c
, 0, fpst
);
11969 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
11971 float_status
*fpst
= fpstp
;
11972 return float64_muladd(a
, b
, c
, 0, fpst
);
11975 /* ARMv8 round to integral */
11976 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
11978 return float32_round_to_int(x
, fp_status
);
11981 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
11983 return float64_round_to_int(x
, fp_status
);
11986 float32
HELPER(rints
)(float32 x
, void *fp_status
)
11988 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
11991 ret
= float32_round_to_int(x
, fp_status
);
11993 /* Suppress any inexact exceptions the conversion produced */
11994 if (!(old_flags
& float_flag_inexact
)) {
11995 new_flags
= get_float_exception_flags(fp_status
);
11996 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
12002 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
12004 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
12007 ret
= float64_round_to_int(x
, fp_status
);
12009 new_flags
= get_float_exception_flags(fp_status
);
12011 /* Suppress any inexact exceptions the conversion produced */
12012 if (!(old_flags
& float_flag_inexact
)) {
12013 new_flags
= get_float_exception_flags(fp_status
);
12014 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
12020 /* Convert ARM rounding mode to softfloat */
12021 int arm_rmode_to_sf(int rmode
)
12024 case FPROUNDING_TIEAWAY
:
12025 rmode
= float_round_ties_away
;
12027 case FPROUNDING_ODD
:
12028 /* FIXME: add support for TIEAWAY and ODD */
12029 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
12031 case FPROUNDING_TIEEVEN
:
12033 rmode
= float_round_nearest_even
;
12035 case FPROUNDING_POSINF
:
12036 rmode
= float_round_up
;
12038 case FPROUNDING_NEGINF
:
12039 rmode
= float_round_down
;
12041 case FPROUNDING_ZERO
:
12042 rmode
= float_round_to_zero
;
12049 * The upper bytes of val (above the number specified by 'bytes') must have
12050 * been zeroed out by the caller.
12052 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12056 stl_le_p(buf
, val
);
12058 /* zlib crc32 converts the accumulator and output to one's complement. */
12059 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12062 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12066 stl_le_p(buf
, val
);
12068 /* Linux crc32c converts the output to one's complement. */
12069 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12072 /* Return the exception level to which FP-disabled exceptions should
12073 * be taken, or 0 if FP is enabled.
12075 static inline int fp_exception_el(CPUARMState
*env
)
12077 #ifndef CONFIG_USER_ONLY
12079 int cur_el
= arm_current_el(env
);
12081 /* CPACR and the CPTR registers don't exist before v6, so FP is
12082 * always accessible
12084 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12088 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12089 * 0, 2 : trap EL0 and EL1/PL1 accesses
12090 * 1 : trap only EL0 accesses
12091 * 3 : trap no accesses
12093 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
12097 if (cur_el
== 0 || cur_el
== 1) {
12098 /* Trap to PL1, which might be EL1 or EL3 */
12099 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
12104 if (cur_el
== 3 && !is_a64(env
)) {
12105 /* Secure PL1 running at EL3 */
12118 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12119 * check because zero bits in the registers mean "don't trap".
12122 /* CPTR_EL2 : present in v7VE or v8 */
12123 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
12124 && !arm_is_secure_below_el3(env
)) {
12125 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12129 /* CPTR_EL3 : present in v8 */
12130 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
12131 /* Trap all FP ops to EL3 */
12138 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12139 target_ulong
*cs_base
, uint32_t *pflags
)
12141 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
12142 int fp_el
= fp_exception_el(env
);
12146 int sve_el
= sve_exception_el(env
);
12150 flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
12151 /* Get control bits for tagged addresses */
12152 flags
|= (arm_regime_tbi0(env
, mmu_idx
) << ARM_TBFLAG_TBI0_SHIFT
);
12153 flags
|= (arm_regime_tbi1(env
, mmu_idx
) << ARM_TBFLAG_TBI1_SHIFT
);
12154 flags
|= sve_el
<< ARM_TBFLAG_SVEEXC_EL_SHIFT
;
12156 /* If SVE is disabled, but FP is enabled,
12157 then the effective len is 0. */
12158 if (sve_el
!= 0 && fp_el
== 0) {
12161 int current_el
= arm_current_el(env
);
12163 zcr_len
= env
->vfp
.zcr_el
[current_el
<= 1 ? 1 : current_el
];
12165 if (current_el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
12166 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
12168 if (current_el
< 3 && arm_feature(env
, ARM_FEATURE_EL3
)) {
12169 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
12172 flags
|= zcr_len
<< ARM_TBFLAG_ZCR_LEN_SHIFT
;
12174 *pc
= env
->regs
[15];
12175 flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
12176 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
12177 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
12178 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
12179 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
12180 if (!(access_secure_reg(env
))) {
12181 flags
|= ARM_TBFLAG_NS_MASK
;
12183 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
12184 || arm_el_is_aa64(env
, 1)) {
12185 flags
|= ARM_TBFLAG_VFPEN_MASK
;
12187 flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
12188 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
12191 flags
|= (arm_to_core_mmu_idx(mmu_idx
) << ARM_TBFLAG_MMUIDX_SHIFT
);
12193 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12194 * states defined in the ARM ARM for software singlestep:
12195 * SS_ACTIVE PSTATE.SS State
12196 * 0 x Inactive (the TB flag for SS is always 0)
12197 * 1 0 Active-pending
12198 * 1 1 Active-not-pending
12200 if (arm_singlestep_active(env
)) {
12201 flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
12203 if (env
->pstate
& PSTATE_SS
) {
12204 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
12207 if (env
->uncached_cpsr
& PSTATE_SS
) {
12208 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
12212 if (arm_cpu_data_is_big_endian(env
)) {
12213 flags
|= ARM_TBFLAG_BE_DATA_MASK
;
12215 flags
|= fp_el
<< ARM_TBFLAG_FPEXC_EL_SHIFT
;
12217 if (arm_v7m_is_handler_mode(env
)) {
12218 flags
|= ARM_TBFLAG_HANDLER_MASK
;