4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
266 static bool arm_pan_enabled(CPUARMState
*env
)
269 if ((arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
)) == (HCR_NV
| HCR_NV1
)) {
272 return env
->pstate
& PSTATE_PAN
;
274 return env
->uncached_cpsr
& CPSR_PAN
;
279 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
281 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
282 const ARMCPRegInfo
*ri
,
285 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
286 arm_is_secure_below_el3(env
)) {
287 return CP_ACCESS_TRAP_UNCATEGORIZED
;
293 * Some secure-only AArch32 registers trap to EL3 if used from
294 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
295 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
296 * We assume that the .access field is set to PL1_RW.
298 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
299 const ARMCPRegInfo
*ri
,
302 if (arm_current_el(env
) == 3) {
305 if (arm_is_secure_below_el3(env
)) {
306 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
307 return CP_ACCESS_TRAP_EL2
;
309 return CP_ACCESS_TRAP_EL3
;
311 /* This will be EL1 NS and EL2 NS, which just UNDEF */
312 return CP_ACCESS_TRAP_UNCATEGORIZED
;
316 * Check for traps to performance monitor registers, which are controlled
317 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
319 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
322 int el
= arm_current_el(env
);
323 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
325 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
326 return CP_ACCESS_TRAP_EL2
;
328 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
329 return CP_ACCESS_TRAP_EL3
;
334 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
335 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
338 if (arm_current_el(env
) == 1) {
339 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
340 if (arm_hcr_el2_eff(env
) & trap
) {
341 return CP_ACCESS_TRAP_EL2
;
347 /* Check for traps from EL1 due to HCR_EL2.TSW. */
348 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
351 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
352 return CP_ACCESS_TRAP_EL2
;
357 /* Check for traps from EL1 due to HCR_EL2.TACR. */
358 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
361 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
362 return CP_ACCESS_TRAP_EL2
;
367 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
368 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
371 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
372 return CP_ACCESS_TRAP_EL2
;
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
378 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
383 return CP_ACCESS_TRAP_EL2
;
388 #ifdef TARGET_AARCH64
389 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
390 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
393 if (arm_current_el(env
) == 1 &&
394 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
395 return CP_ACCESS_TRAP_EL2
;
401 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
403 ARMCPU
*cpu
= env_archcpu(env
);
405 raw_write(env
, ri
, value
);
406 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
409 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
411 ARMCPU
*cpu
= env_archcpu(env
);
413 if (raw_read(env
, ri
) != value
) {
415 * Unlike real hardware the qemu TLB uses virtual addresses,
416 * not modified virtual addresses, so this causes a TLB flush.
419 raw_write(env
, ri
, value
);
423 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
426 ARMCPU
*cpu
= env_archcpu(env
);
428 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
429 && !extended_addresses_enabled(env
)) {
431 * For VMSA (when not using the LPAE long descriptor page table
432 * format) this register includes the ASID, so do a TLB flush.
433 * For PMSA it is purely a process ID and no action is needed.
437 raw_write(env
, ri
, value
);
440 static int alle1_tlbmask(CPUARMState
*env
)
443 * Note that the 'ALL' scope must invalidate both stage 1 and
444 * stage 2 translations, whereas most other scopes only invalidate
445 * stage 1 translations.
447 return (ARMMMUIdxBit_E10_1
|
448 ARMMMUIdxBit_E10_1_PAN
|
450 ARMMMUIdxBit_Stage2
|
451 ARMMMUIdxBit_Stage2_S
);
455 /* IS variants of TLB operations must affect all cores */
456 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
459 CPUState
*cs
= env_cpu(env
);
461 tlb_flush_all_cpus_synced(cs
);
464 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
467 CPUState
*cs
= env_cpu(env
);
469 tlb_flush_all_cpus_synced(cs
);
472 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 CPUState
*cs
= env_cpu(env
);
477 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
480 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
483 CPUState
*cs
= env_cpu(env
);
485 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
489 * Non-IS variants of TLB operations are upgraded to
490 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
491 * force broadcast of these operations.
493 static bool tlb_force_broadcast(CPUARMState
*env
)
495 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
498 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 /* Invalidate all (TLBIALL) */
502 CPUState
*cs
= env_cpu(env
);
504 if (tlb_force_broadcast(env
)) {
505 tlb_flush_all_cpus_synced(cs
);
511 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
514 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
515 CPUState
*cs
= env_cpu(env
);
517 value
&= TARGET_PAGE_MASK
;
518 if (tlb_force_broadcast(env
)) {
519 tlb_flush_page_all_cpus_synced(cs
, value
);
521 tlb_flush_page(cs
, value
);
525 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate by ASID (TLBIASID) */
529 CPUState
*cs
= env_cpu(env
);
531 if (tlb_force_broadcast(env
)) {
532 tlb_flush_all_cpus_synced(cs
);
538 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
542 CPUState
*cs
= env_cpu(env
);
544 value
&= TARGET_PAGE_MASK
;
545 if (tlb_force_broadcast(env
)) {
546 tlb_flush_page_all_cpus_synced(cs
, value
);
548 tlb_flush_page(cs
, value
);
552 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
555 CPUState
*cs
= env_cpu(env
);
557 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
560 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
563 CPUState
*cs
= env_cpu(env
);
565 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
569 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
572 CPUState
*cs
= env_cpu(env
);
574 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
577 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
580 CPUState
*cs
= env_cpu(env
);
582 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
585 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
588 CPUState
*cs
= env_cpu(env
);
589 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
591 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
594 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= env_cpu(env
);
598 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
600 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
604 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 CPUState
*cs
= env_cpu(env
);
608 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
610 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
613 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 CPUState
*cs
= env_cpu(env
);
617 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
619 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
622 static const ARMCPRegInfo cp_reginfo
[] = {
624 * Define the secure and non-secure FCSE identifier CP registers
625 * separately because there is no secure bank in V8 (no _EL3). This allows
626 * the secure register to be properly reset and migrated. There is also no
627 * v8 EL1 version of the register so the non-secure instance stands alone.
630 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
631 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
633 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
634 { .name
= "FCSEIDR_S",
635 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
636 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
637 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
638 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
640 * Define the secure and non-secure context identifier CP registers
641 * separately because there is no secure bank in V8 (no _EL3). This allows
642 * the secure register to be properly reset and migrated. In the
643 * non-secure case, the 32-bit register will have reset and migration
644 * disabled during registration as it is handled by the 64-bit instance.
646 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
647 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
648 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
649 .fgt
= FGT_CONTEXTIDR_EL1
,
650 .nv2_redirect_offset
= 0x108 | NV2_REDIR_NV1
,
651 .secure
= ARM_CP_SECSTATE_NS
,
652 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
653 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
654 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
655 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
656 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
657 .secure
= ARM_CP_SECSTATE_S
,
658 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
659 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
662 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
664 * NB: Some of these registers exist in v8 but with more precise
665 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
667 /* MMU Domain access control / MPU write buffer control */
669 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
670 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
671 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
672 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
673 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
675 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
676 * For v6 and v5, these mappings are overly broad.
678 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
679 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
680 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
681 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
682 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
683 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
684 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
685 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
686 /* Cache maintenance ops; some of this space may be overridden later. */
687 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
688 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
689 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
692 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
694 * Not all pre-v6 cores implemented this WFI, so this is slightly
697 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
698 .access
= PL1_W
, .type
= ARM_CP_WFI
},
701 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
703 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
704 * is UNPREDICTABLE; we choose to NOP as most implementations do).
706 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
707 .access
= PL1_W
, .type
= ARM_CP_WFI
},
709 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
710 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
711 * OMAPCP will override this space.
713 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
714 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
716 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
717 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
719 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
720 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
721 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
724 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
725 * implementing it as RAZ means the "debug architecture version" bits
726 * will read as a reserved value, which should cause Linux to not try
727 * to use the debug hardware.
729 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
730 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
732 * MMU TLB control. Note that the wildcarding means we cover not just
733 * the unified TLB ops but also the dside/iside/inner-shareable variants.
735 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
736 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
737 .type
= ARM_CP_NO_RAW
},
738 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
739 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
740 .type
= ARM_CP_NO_RAW
},
741 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
742 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
743 .type
= ARM_CP_NO_RAW
},
744 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
745 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
746 .type
= ARM_CP_NO_RAW
},
747 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
748 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
749 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
750 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
753 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
758 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
759 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
761 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
762 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
763 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
765 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
766 /* VFP coprocessor: cp10 & cp11 [23:20] */
767 mask
|= R_CPACR_ASEDIS_MASK
|
768 R_CPACR_D32DIS_MASK
|
772 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
773 /* ASEDIS [31] bit is RAO/WI */
774 value
|= R_CPACR_ASEDIS_MASK
;
778 * VFPv3 and upwards with NEON implement 32 double precision
779 * registers (D0-D31).
781 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
782 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
783 value
|= R_CPACR_D32DIS_MASK
;
790 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
791 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
793 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
794 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
795 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
796 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
799 env
->cp15
.cpacr_el1
= value
;
802 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
805 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
806 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
808 uint64_t value
= env
->cp15
.cpacr_el1
;
810 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
811 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
812 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
818 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
821 * Call cpacr_write() so that we reset with the correct RAO bits set
822 * for our CPU features.
824 cpacr_write(env
, ri
, 0);
827 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
830 if (arm_feature(env
, ARM_FEATURE_V8
)) {
831 /* Check if CPACR accesses are to be trapped to EL2 */
832 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
833 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
834 return CP_ACCESS_TRAP_EL2
;
835 /* Check if CPACR accesses are to be trapped to EL3 */
836 } else if (arm_current_el(env
) < 3 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
845 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
848 /* Check if CPTR accesses are set to trap to EL3 */
849 if (arm_current_el(env
) == 2 &&
850 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
851 return CP_ACCESS_TRAP_EL3
;
857 static const ARMCPRegInfo v6_cp_reginfo
[] = {
858 /* prefetch by MVA in v6, NOP in v7 */
859 { .name
= "MVA_prefetch",
860 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
861 .access
= PL1_W
, .type
= ARM_CP_NOP
},
863 * We need to break the TB after ISB to execute self-modifying code
864 * correctly and also to take any pending interrupts immediately.
865 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
867 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
868 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
869 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
870 .access
= PL0_W
, .type
= ARM_CP_NOP
},
871 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
872 .access
= PL0_W
, .type
= ARM_CP_NOP
},
873 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
874 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
875 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
876 offsetof(CPUARMState
, cp15
.ifar_ns
) },
879 * Watchpoint Fault Address Register : should actually only be present
880 * for 1136, 1176, 11MPCore.
882 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
883 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
884 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
885 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
886 .fgt
= FGT_CPACR_EL1
,
887 .nv2_redirect_offset
= 0x100 | NV2_REDIR_NV1
,
888 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
889 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
892 typedef struct pm_event
{
893 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
894 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
895 bool (*supported
)(CPUARMState
*);
897 * Retrieve the current count of the underlying event. The programmed
898 * counters hold a difference from the return value from this function
900 uint64_t (*get_count
)(CPUARMState
*);
902 * Return how many nanoseconds it will take (at a minimum) for count events
903 * to occur. A negative value indicates the counter will never overflow, or
904 * that the counter has otherwise arranged for the overflow bit to be set
905 * and the PMU interrupt to be raised on overflow.
907 int64_t (*ns_per_count
)(uint64_t);
910 static bool event_always_supported(CPUARMState
*env
)
915 static uint64_t swinc_get_count(CPUARMState
*env
)
918 * SW_INCR events are written directly to the pmevcntr's by writes to
919 * PMSWINC, so there is no underlying count maintained by the PMU itself
924 static int64_t swinc_ns_per(uint64_t ignored
)
930 * Return the underlying cycle count for the PMU cycle counters. If we're in
931 * usermode, simply return 0.
933 static uint64_t cycles_get_count(CPUARMState
*env
)
935 #ifndef CONFIG_USER_ONLY
936 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
937 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
939 return cpu_get_host_ticks();
943 #ifndef CONFIG_USER_ONLY
944 static int64_t cycles_ns_per(uint64_t cycles
)
946 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
949 static bool instructions_supported(CPUARMState
*env
)
951 return icount_enabled() == 1; /* Precise instruction counting */
954 static uint64_t instructions_get_count(CPUARMState
*env
)
956 return (uint64_t)icount_get_raw();
959 static int64_t instructions_ns_per(uint64_t icount
)
961 return icount_to_ns((int64_t)icount
);
965 static bool pmuv3p1_events_supported(CPUARMState
*env
)
967 /* For events which are supported in any v8.1 PMU */
968 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
971 static bool pmuv3p4_events_supported(CPUARMState
*env
)
973 /* For events which are supported in any v8.1 PMU */
974 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
977 static uint64_t zero_event_get_count(CPUARMState
*env
)
979 /* For events which on QEMU never fire, so their count is always zero */
983 static int64_t zero_event_ns_per(uint64_t cycles
)
985 /* An event which never fires can never overflow */
989 static const pm_event pm_events
[] = {
990 { .number
= 0x000, /* SW_INCR */
991 .supported
= event_always_supported
,
992 .get_count
= swinc_get_count
,
993 .ns_per_count
= swinc_ns_per
,
995 #ifndef CONFIG_USER_ONLY
996 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
997 .supported
= instructions_supported
,
998 .get_count
= instructions_get_count
,
999 .ns_per_count
= instructions_ns_per
,
1001 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1002 .supported
= event_always_supported
,
1003 .get_count
= cycles_get_count
,
1004 .ns_per_count
= cycles_ns_per
,
1007 { .number
= 0x023, /* STALL_FRONTEND */
1008 .supported
= pmuv3p1_events_supported
,
1009 .get_count
= zero_event_get_count
,
1010 .ns_per_count
= zero_event_ns_per
,
1012 { .number
= 0x024, /* STALL_BACKEND */
1013 .supported
= pmuv3p1_events_supported
,
1014 .get_count
= zero_event_get_count
,
1015 .ns_per_count
= zero_event_ns_per
,
1017 { .number
= 0x03c, /* STALL */
1018 .supported
= pmuv3p4_events_supported
,
1019 .get_count
= zero_event_get_count
,
1020 .ns_per_count
= zero_event_ns_per
,
1025 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1026 * events (i.e. the statistical profiling extension), this implementation
1027 * should first be updated to something sparse instead of the current
1028 * supported_event_map[] array.
1030 #define MAX_EVENT_ID 0x3c
1031 #define UNSUPPORTED_EVENT UINT16_MAX
1032 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1035 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1036 * of ARM event numbers to indices in our pm_events array.
1038 * Note: Events in the 0x40XX range are not currently supported.
1040 void pmu_init(ARMCPU
*cpu
)
1045 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1048 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1049 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1054 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1055 const pm_event
*cnt
= &pm_events
[i
];
1056 assert(cnt
->number
<= MAX_EVENT_ID
);
1057 /* We do not currently support events in the 0x40xx range */
1058 assert(cnt
->number
<= 0x3f);
1060 if (cnt
->supported(&cpu
->env
)) {
1061 supported_event_map
[cnt
->number
] = i
;
1062 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1063 if (cnt
->number
& 0x20) {
1064 cpu
->pmceid1
|= event_mask
;
1066 cpu
->pmceid0
|= event_mask
;
1073 * Check at runtime whether a PMU event is supported for the current machine
1075 static bool event_supported(uint16_t number
)
1077 if (number
> MAX_EVENT_ID
) {
1080 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1083 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1087 * Performance monitor registers user accessibility is controlled
1088 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1089 * trapping to EL2 or EL3 for other accesses.
1091 int el
= arm_current_el(env
);
1092 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1094 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1095 return CP_ACCESS_TRAP
;
1097 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1098 return CP_ACCESS_TRAP_EL2
;
1100 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1101 return CP_ACCESS_TRAP_EL3
;
1104 return CP_ACCESS_OK
;
1107 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1108 const ARMCPRegInfo
*ri
,
1111 /* ER: event counter read trap control */
1112 if (arm_feature(env
, ARM_FEATURE_V8
)
1113 && arm_current_el(env
) == 0
1114 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1116 return CP_ACCESS_OK
;
1119 return pmreg_access(env
, ri
, isread
);
1122 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1123 const ARMCPRegInfo
*ri
,
1126 /* SW: software increment write trap control */
1127 if (arm_feature(env
, ARM_FEATURE_V8
)
1128 && arm_current_el(env
) == 0
1129 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1131 return CP_ACCESS_OK
;
1134 return pmreg_access(env
, ri
, isread
);
1137 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1138 const ARMCPRegInfo
*ri
,
1141 /* ER: event counter read trap control */
1142 if (arm_feature(env
, ARM_FEATURE_V8
)
1143 && arm_current_el(env
) == 0
1144 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1145 return CP_ACCESS_OK
;
1148 return pmreg_access(env
, ri
, isread
);
1151 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1152 const ARMCPRegInfo
*ri
,
1155 /* CR: cycle counter read trap control */
1156 if (arm_feature(env
, ARM_FEATURE_V8
)
1157 && arm_current_el(env
) == 0
1158 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1160 return CP_ACCESS_OK
;
1163 return pmreg_access(env
, ri
, isread
);
1167 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1168 * We use these to decide whether we need to wrap a write to MDCR_EL2
1169 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1171 #define MDCR_EL2_PMU_ENABLE_BITS \
1172 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1173 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1176 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1177 * the current EL, security state, and register configuration.
1179 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1182 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1183 bool enabled
, prohibited
= false, filtered
;
1184 bool secure
= arm_is_secure(env
);
1185 int el
= arm_current_el(env
);
1186 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1187 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1189 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1193 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1194 (counter
< hpmn
|| counter
== 31)) {
1195 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1197 e
= mdcr_el2
& MDCR_HPME
;
1199 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1201 /* Is event counting prohibited? */
1202 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1203 prohibited
= mdcr_el2
& MDCR_HPMD
;
1206 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1209 if (counter
== 31) {
1211 * The cycle counter defaults to running. PMCR.DP says "disable
1212 * the cycle counter when event counting is prohibited".
1213 * Some MDCR bits disable the cycle counter specifically.
1215 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1216 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1218 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1221 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1226 if (counter
== 31) {
1227 filter
= env
->cp15
.pmccfiltr_el0
;
1229 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1232 p
= filter
& PMXEVTYPER_P
;
1233 u
= filter
& PMXEVTYPER_U
;
1234 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1235 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1236 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1237 m
= arm_el_is_aa64(env
, 1) &&
1238 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1241 filtered
= secure
? u
: u
!= nsu
;
1242 } else if (el
== 1) {
1243 filtered
= secure
? p
: p
!= nsk
;
1244 } else if (el
== 2) {
1250 if (counter
!= 31) {
1252 * If not checking PMCCNTR, ensure the counter is setup to an event we
1255 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1256 if (!event_supported(event
)) {
1261 return enabled
&& !prohibited
&& !filtered
;
1264 static void pmu_update_irq(CPUARMState
*env
)
1266 ARMCPU
*cpu
= env_archcpu(env
);
1267 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1268 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1271 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1274 * Return true if the clock divider is enabled and the cycle counter
1275 * is supposed to tick only once every 64 clock cycles. This is
1276 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1277 * (64-bit) cycle counter PMCR.D has no effect.
1279 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1282 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1284 /* Return true if the specified event counter is configured to be 64 bit */
1286 /* This isn't intended to be used with the cycle counter */
1287 assert(counter
< 31);
1289 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1293 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1295 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1296 * current security state, so we don't use arm_mdcr_el2_eff() here.
1298 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1299 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1301 if (counter
>= hpmn
) {
1305 return env
->cp15
.c9_pmcr
& PMCRLP
;
1309 * Ensure c15_ccnt is the guest-visible count so that operations such as
1310 * enabling/disabling the counter or filtering, modifying the count itself,
1311 * etc. can be done logically. This is essentially a no-op if the counter is
1312 * not enabled at the time of the call.
1314 static void pmccntr_op_start(CPUARMState
*env
)
1316 uint64_t cycles
= cycles_get_count(env
);
1318 if (pmu_counter_enabled(env
, 31)) {
1319 uint64_t eff_cycles
= cycles
;
1320 if (pmccntr_clockdiv_enabled(env
)) {
1324 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1326 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1327 1ull << 63 : 1ull << 31;
1328 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1329 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1330 pmu_update_irq(env
);
1333 env
->cp15
.c15_ccnt
= new_pmccntr
;
1335 env
->cp15
.c15_ccnt_delta
= cycles
;
1339 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1340 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1343 static void pmccntr_op_finish(CPUARMState
*env
)
1345 if (pmu_counter_enabled(env
, 31)) {
1346 #ifndef CONFIG_USER_ONLY
1347 /* Calculate when the counter will next overflow */
1348 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1349 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1350 remaining_cycles
= (uint32_t)remaining_cycles
;
1352 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1354 if (overflow_in
> 0) {
1355 int64_t overflow_at
;
1357 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1358 overflow_in
, &overflow_at
)) {
1359 ARMCPU
*cpu
= env_archcpu(env
);
1360 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1365 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1366 if (pmccntr_clockdiv_enabled(env
)) {
1369 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1373 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1376 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1378 if (event_supported(event
)) {
1379 uint16_t event_idx
= supported_event_map
[event
];
1380 count
= pm_events
[event_idx
].get_count(env
);
1383 if (pmu_counter_enabled(env
, counter
)) {
1384 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1385 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1386 1ULL << 63 : 1ULL << 31;
1388 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1389 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1390 pmu_update_irq(env
);
1392 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1394 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1397 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1399 if (pmu_counter_enabled(env
, counter
)) {
1400 #ifndef CONFIG_USER_ONLY
1401 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1402 uint16_t event_idx
= supported_event_map
[event
];
1403 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1404 int64_t overflow_in
;
1406 if (!pmevcntr_is_64_bit(env
, counter
)) {
1407 delta
= (uint32_t)delta
;
1409 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1411 if (overflow_in
> 0) {
1412 int64_t overflow_at
;
1414 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1415 overflow_in
, &overflow_at
)) {
1416 ARMCPU
*cpu
= env_archcpu(env
);
1417 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1422 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1423 env
->cp15
.c14_pmevcntr
[counter
];
1427 void pmu_op_start(CPUARMState
*env
)
1430 pmccntr_op_start(env
);
1431 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1432 pmevcntr_op_start(env
, i
);
1436 void pmu_op_finish(CPUARMState
*env
)
1439 pmccntr_op_finish(env
);
1440 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1441 pmevcntr_op_finish(env
, i
);
1445 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1447 pmu_op_start(&cpu
->env
);
1450 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1452 pmu_op_finish(&cpu
->env
);
1455 void arm_pmu_timer_cb(void *opaque
)
1457 ARMCPU
*cpu
= opaque
;
1460 * Update all the counter values based on the current underlying counts,
1461 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1462 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1463 * counter may expire.
1465 pmu_op_start(&cpu
->env
);
1466 pmu_op_finish(&cpu
->env
);
1469 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1474 if (value
& PMCRC
) {
1475 /* The counter has been reset */
1476 env
->cp15
.c15_ccnt
= 0;
1479 if (value
& PMCRP
) {
1481 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1482 env
->cp15
.c14_pmevcntr
[i
] = 0;
1486 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1487 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1492 static uint64_t pmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1494 uint64_t pmcr
= env
->cp15
.c9_pmcr
;
1497 * If EL2 is implemented and enabled for the current security state, reads
1498 * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN.
1500 if (arm_current_el(env
) <= 1 && arm_is_el2_enabled(env
)) {
1501 pmcr
&= ~PMCRN_MASK
;
1502 pmcr
|= (env
->cp15
.mdcr_el2
& MDCR_HPMN
) << PMCRN_SHIFT
;
1508 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1512 uint64_t overflow_mask
, new_pmswinc
;
1514 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1515 /* Increment a counter's count iff: */
1516 if ((value
& (1 << i
)) && /* counter's bit is set */
1517 /* counter is enabled and not filtered */
1518 pmu_counter_enabled(env
, i
) &&
1519 /* counter is SW_INCR */
1520 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1521 pmevcntr_op_start(env
, i
);
1524 * Detect if this write causes an overflow since we can't predict
1525 * PMSWINC overflows like we can for other events
1527 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1529 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1530 1ULL << 63 : 1ULL << 31;
1532 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1533 env
->cp15
.c9_pmovsr
|= (1 << i
);
1534 pmu_update_irq(env
);
1537 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1539 pmevcntr_op_finish(env
, i
);
1544 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1547 pmccntr_op_start(env
);
1548 ret
= env
->cp15
.c15_ccnt
;
1549 pmccntr_op_finish(env
);
1553 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1557 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1558 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1559 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1562 env
->cp15
.c9_pmselr
= value
& 0x1f;
1565 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1568 pmccntr_op_start(env
);
1569 env
->cp15
.c15_ccnt
= value
;
1570 pmccntr_op_finish(env
);
1573 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1576 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1578 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1581 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1584 pmccntr_op_start(env
);
1585 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1586 pmccntr_op_finish(env
);
1589 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1592 pmccntr_op_start(env
);
1593 /* M is not accessible from AArch32 */
1594 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1595 (value
& PMCCFILTR
);
1596 pmccntr_op_finish(env
);
1599 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1601 /* M is not visible in AArch32 */
1602 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1605 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1609 value
&= pmu_counter_mask(env
);
1610 env
->cp15
.c9_pmcnten
|= value
;
1614 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1618 value
&= pmu_counter_mask(env
);
1619 env
->cp15
.c9_pmcnten
&= ~value
;
1623 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1626 value
&= pmu_counter_mask(env
);
1627 env
->cp15
.c9_pmovsr
&= ~value
;
1628 pmu_update_irq(env
);
1631 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1634 value
&= pmu_counter_mask(env
);
1635 env
->cp15
.c9_pmovsr
|= value
;
1636 pmu_update_irq(env
);
1639 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1640 uint64_t value
, const uint8_t counter
)
1642 if (counter
== 31) {
1643 pmccfiltr_write(env
, ri
, value
);
1644 } else if (counter
< pmu_num_counters(env
)) {
1645 pmevcntr_op_start(env
, counter
);
1648 * If this counter's event type is changing, store the current
1649 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1650 * pmevcntr_op_finish has the correct baseline when it converts back to
1653 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1654 PMXEVTYPER_EVTCOUNT
;
1655 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1656 if (old_event
!= new_event
) {
1658 if (event_supported(new_event
)) {
1659 uint16_t event_idx
= supported_event_map
[new_event
];
1660 count
= pm_events
[event_idx
].get_count(env
);
1662 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1665 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1666 pmevcntr_op_finish(env
, counter
);
1669 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1670 * PMSELR value is equal to or greater than the number of implemented
1671 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1675 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1676 const uint8_t counter
)
1678 if (counter
== 31) {
1679 return env
->cp15
.pmccfiltr_el0
;
1680 } else if (counter
< pmu_num_counters(env
)) {
1681 return env
->cp15
.c14_pmevtyper
[counter
];
1684 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1685 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1691 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1694 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1695 pmevtyper_write(env
, ri
, value
, counter
);
1698 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1701 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1702 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1705 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1706 * pmu_op_finish calls when loading saved state for a migration. Because
1707 * we're potentially updating the type of event here, the value written to
1708 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1709 * different counter type. Therefore, we need to set this value to the
1710 * current count for the counter type we're writing so that pmu_op_finish
1711 * has the correct count for its calculation.
1713 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1714 if (event_supported(event
)) {
1715 uint16_t event_idx
= supported_event_map
[event
];
1716 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1717 pm_events
[event_idx
].get_count(env
);
1721 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1723 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1724 return pmevtyper_read(env
, ri
, counter
);
1727 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1730 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1733 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1735 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1738 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1739 uint64_t value
, uint8_t counter
)
1741 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1742 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1743 value
&= MAKE_64BIT_MASK(0, 32);
1745 if (counter
< pmu_num_counters(env
)) {
1746 pmevcntr_op_start(env
, counter
);
1747 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1748 pmevcntr_op_finish(env
, counter
);
1751 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1752 * are CONSTRAINED UNPREDICTABLE.
1756 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1759 if (counter
< pmu_num_counters(env
)) {
1761 pmevcntr_op_start(env
, counter
);
1762 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1763 pmevcntr_op_finish(env
, counter
);
1764 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1765 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1766 ret
&= MAKE_64BIT_MASK(0, 32);
1771 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1772 * are CONSTRAINED UNPREDICTABLE.
1778 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1781 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1782 pmevcntr_write(env
, ri
, value
, counter
);
1785 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1787 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1788 return pmevcntr_read(env
, ri
, counter
);
1791 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1794 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1795 assert(counter
< pmu_num_counters(env
));
1796 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1797 pmevcntr_write(env
, ri
, value
, counter
);
1800 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1802 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1803 assert(counter
< pmu_num_counters(env
));
1804 return env
->cp15
.c14_pmevcntr
[counter
];
1807 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1810 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1813 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1815 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1818 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1821 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1822 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1824 env
->cp15
.c9_pmuserenr
= value
& 1;
1828 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1831 /* We have no event counters so only the C bit can be changed */
1832 value
&= pmu_counter_mask(env
);
1833 env
->cp15
.c9_pminten
|= value
;
1834 pmu_update_irq(env
);
1837 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1840 value
&= pmu_counter_mask(env
);
1841 env
->cp15
.c9_pminten
&= ~value
;
1842 pmu_update_irq(env
);
1845 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1849 * Note that even though the AArch64 view of this register has bits
1850 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1851 * architectural requirements for bits which are RES0 only in some
1852 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1853 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1855 raw_write(env
, ri
, value
& ~0x1FULL
);
1858 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1860 /* Begin with base v8.0 state. */
1861 uint64_t valid_mask
= 0x3fff;
1862 ARMCPU
*cpu
= env_archcpu(env
);
1866 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1867 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1868 * Instead, choose the format based on the mode of EL3.
1870 if (arm_el_is_aa64(env
, 3)) {
1871 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1872 valid_mask
&= ~SCR_NET
; /* RES0 */
1874 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1875 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1876 value
|= SCR_RW
; /* RAO/WI */
1878 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1879 valid_mask
|= SCR_TERR
;
1881 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1882 valid_mask
|= SCR_TLOR
;
1884 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1885 valid_mask
|= SCR_API
| SCR_APK
;
1887 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1888 valid_mask
|= SCR_EEL2
;
1889 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1890 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1893 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1894 valid_mask
|= SCR_ATA
;
1896 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1897 valid_mask
|= SCR_ENSCXT
;
1899 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1900 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1902 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1903 valid_mask
|= SCR_ENTP2
;
1905 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1906 valid_mask
|= SCR_HXEN
;
1908 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1909 valid_mask
|= SCR_FGTEN
;
1911 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1912 valid_mask
|= SCR_NSE
| SCR_GPF
;
1915 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1916 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1917 valid_mask
|= SCR_TERR
;
1921 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1922 valid_mask
&= ~SCR_HCE
;
1925 * On ARMv7, SMD (or SCD as it is called in v7) is only
1926 * supported if EL2 exists. The bit is UNK/SBZP when
1927 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1928 * when EL2 is unavailable.
1929 * On ARMv8, this bit is always available.
1931 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1932 !arm_feature(env
, ARM_FEATURE_V8
)) {
1933 valid_mask
&= ~SCR_SMD
;
1937 /* Clear all-context RES0 bits. */
1938 value
&= valid_mask
;
1939 changed
= env
->cp15
.scr_el3
^ value
;
1940 env
->cp15
.scr_el3
= value
;
1943 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1944 * we must invalidate all TLBs below EL3.
1946 if (changed
& (SCR_NS
| SCR_NSE
)) {
1947 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1948 ARMMMUIdxBit_E20_0
|
1949 ARMMMUIdxBit_E10_1
|
1950 ARMMMUIdxBit_E20_2
|
1951 ARMMMUIdxBit_E10_1_PAN
|
1952 ARMMMUIdxBit_E20_2_PAN
|
1957 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1960 * scr_write will set the RES1 bits on an AArch64-only CPU.
1961 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1963 scr_write(env
, ri
, 0);
1966 static CPAccessResult
access_tid4(CPUARMState
*env
,
1967 const ARMCPRegInfo
*ri
,
1970 if (arm_current_el(env
) == 1 &&
1971 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1972 return CP_ACCESS_TRAP_EL2
;
1975 return CP_ACCESS_OK
;
1978 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1980 ARMCPU
*cpu
= env_archcpu(env
);
1983 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1986 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1987 ri
->secure
& ARM_CP_SECSTATE_S
);
1989 return cpu
->ccsidr
[index
];
1992 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1995 raw_write(env
, ri
, value
& 0xf);
1998 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2000 CPUState
*cs
= env_cpu(env
);
2001 bool el1
= arm_current_el(env
) == 1;
2002 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
2005 if (hcr_el2
& HCR_IMO
) {
2006 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2010 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2015 if (hcr_el2
& HCR_FMO
) {
2016 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2020 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2025 if (hcr_el2
& HCR_AMO
) {
2026 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2034 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2037 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2038 return CP_ACCESS_TRAP_EL2
;
2041 return CP_ACCESS_OK
;
2044 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2047 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2048 return access_aa64_tid1(env
, ri
, isread
);
2051 return CP_ACCESS_OK
;
2054 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2055 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2056 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2057 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2059 * Performance monitors are implementation defined in v7,
2060 * but with an ARM recommended set of registers, which we
2063 * Performance registers fall into three categories:
2064 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2065 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2066 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2067 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2068 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2070 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2071 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2072 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2073 .writefn
= pmcntenset_write
,
2074 .accessfn
= pmreg_access
,
2076 .raw_writefn
= raw_write
},
2077 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2078 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2079 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2082 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2083 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2085 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2086 .accessfn
= pmreg_access
,
2088 .writefn
= pmcntenclr_write
,
2089 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2090 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2091 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2092 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2094 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2095 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2096 .writefn
= pmcntenclr_write
},
2097 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2098 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2099 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2100 .accessfn
= pmreg_access
,
2102 .writefn
= pmovsr_write
,
2103 .raw_writefn
= raw_write
},
2104 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2105 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2106 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2108 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2109 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2110 .writefn
= pmovsr_write
,
2111 .raw_writefn
= raw_write
},
2112 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2113 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2114 .fgt
= FGT_PMSWINC_EL0
,
2115 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2116 .writefn
= pmswinc_write
},
2117 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2118 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2119 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2120 .fgt
= FGT_PMSWINC_EL0
,
2121 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2122 .writefn
= pmswinc_write
},
2123 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2124 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2125 .fgt
= FGT_PMSELR_EL0
,
2126 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2127 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2128 .raw_writefn
= raw_write
},
2129 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2130 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2131 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2132 .fgt
= FGT_PMSELR_EL0
,
2133 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2134 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2135 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2136 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2137 .fgt
= FGT_PMCCNTR_EL0
,
2138 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2139 .accessfn
= pmreg_access_ccntr
},
2140 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2141 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2142 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2143 .fgt
= FGT_PMCCNTR_EL0
,
2145 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2146 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2147 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2148 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2149 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2150 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2151 .fgt
= FGT_PMCCFILTR_EL0
,
2152 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2154 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2155 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2156 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2157 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2158 .fgt
= FGT_PMCCFILTR_EL0
,
2160 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2162 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2163 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2164 .accessfn
= pmreg_access
,
2165 .fgt
= FGT_PMEVTYPERN_EL0
,
2166 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2167 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2168 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2169 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2170 .accessfn
= pmreg_access
,
2171 .fgt
= FGT_PMEVTYPERN_EL0
,
2172 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2173 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2174 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2175 .accessfn
= pmreg_access_xevcntr
,
2176 .fgt
= FGT_PMEVCNTRN_EL0
,
2177 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2178 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2179 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2180 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2181 .accessfn
= pmreg_access_xevcntr
,
2182 .fgt
= FGT_PMEVCNTRN_EL0
,
2183 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2184 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2185 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2186 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2188 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2189 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2190 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2191 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2192 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2194 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2195 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2196 .access
= PL1_RW
, .accessfn
= access_tpm
,
2198 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2199 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2201 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2202 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2203 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2204 .access
= PL1_RW
, .accessfn
= access_tpm
,
2207 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2208 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2209 .resetvalue
= 0x0 },
2210 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2211 .access
= PL1_RW
, .accessfn
= access_tpm
,
2213 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2214 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2215 .writefn
= pmintenclr_write
, },
2216 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2217 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2218 .access
= PL1_RW
, .accessfn
= access_tpm
,
2220 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2221 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2222 .writefn
= pmintenclr_write
},
2223 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2224 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2226 .accessfn
= access_tid4
,
2227 .fgt
= FGT_CCSIDR_EL1
,
2228 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2229 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2230 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2232 .accessfn
= access_tid4
,
2233 .fgt
= FGT_CSSELR_EL1
,
2234 .writefn
= csselr_write
, .resetvalue
= 0,
2235 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2236 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2238 * Auxiliary ID register: this actually has an IMPDEF value but for now
2239 * just RAZ for all cores:
2241 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2242 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2243 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2244 .accessfn
= access_aa64_tid1
,
2245 .fgt
= FGT_AIDR_EL1
,
2248 * Auxiliary fault status registers: these also are IMPDEF, and we
2249 * choose to RAZ/WI for all cores.
2251 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2252 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2253 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2254 .fgt
= FGT_AFSR0_EL1
,
2255 .nv2_redirect_offset
= 0x128 | NV2_REDIR_NV1
,
2256 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2257 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2258 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2259 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2260 .fgt
= FGT_AFSR1_EL1
,
2261 .nv2_redirect_offset
= 0x130 | NV2_REDIR_NV1
,
2262 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2264 * MAIR can just read-as-written because we don't implement caches
2265 * and so don't need to care about memory attributes.
2267 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2268 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2269 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2270 .fgt
= FGT_MAIR_EL1
,
2271 .nv2_redirect_offset
= 0x140 | NV2_REDIR_NV1
,
2272 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2274 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2275 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2276 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2279 * For non-long-descriptor page tables these are PRRR and NMRR;
2280 * regardless they still act as reads-as-written for QEMU.
2283 * MAIR0/1 are defined separately from their 64-bit counterpart which
2284 * allows them to assign the correct fieldoffset based on the endianness
2285 * handled in the field definitions.
2287 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2288 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2289 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2290 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2291 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2292 .resetfn
= arm_cp_reset_ignore
},
2293 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2294 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2295 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2296 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2297 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2298 .resetfn
= arm_cp_reset_ignore
},
2299 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2300 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2302 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2303 /* 32 bit ITLB invalidates */
2304 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2305 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2306 .writefn
= tlbiall_write
},
2307 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2308 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2309 .writefn
= tlbimva_write
},
2310 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2311 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2312 .writefn
= tlbiasid_write
},
2313 /* 32 bit DTLB invalidates */
2314 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2315 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2316 .writefn
= tlbiall_write
},
2317 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2318 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2319 .writefn
= tlbimva_write
},
2320 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2321 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2322 .writefn
= tlbiasid_write
},
2323 /* 32 bit TLB invalidates */
2324 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2325 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2326 .writefn
= tlbiall_write
},
2327 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2328 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2329 .writefn
= tlbimva_write
},
2330 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2331 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2332 .writefn
= tlbiasid_write
},
2333 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2334 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2335 .writefn
= tlbimvaa_write
},
2338 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2339 /* 32 bit TLB invalidates, Inner Shareable */
2340 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2341 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2342 .writefn
= tlbiall_is_write
},
2343 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2344 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2345 .writefn
= tlbimva_is_write
},
2346 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2347 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2348 .writefn
= tlbiasid_is_write
},
2349 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2350 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2351 .writefn
= tlbimvaa_is_write
},
2354 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2355 /* PMOVSSET is not implemented in v7 before v7ve */
2356 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2357 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2359 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2360 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2361 .writefn
= pmovsset_write
,
2362 .raw_writefn
= raw_write
},
2363 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2364 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2365 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2367 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2368 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2369 .writefn
= pmovsset_write
,
2370 .raw_writefn
= raw_write
},
2373 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2380 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2384 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2385 * at all, so we don't need to check whether we're v8A.
2387 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2388 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2389 return CP_ACCESS_TRAP_EL2
;
2391 return CP_ACCESS_OK
;
2394 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2397 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2398 return CP_ACCESS_TRAP
;
2400 return teecr_access(env
, ri
, isread
);
2403 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2404 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2405 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2407 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2408 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2409 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2410 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2413 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2414 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2415 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2417 .fgt
= FGT_TPIDR_EL0
,
2418 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2419 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2421 .fgt
= FGT_TPIDR_EL0
,
2422 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2423 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2424 .resetfn
= arm_cp_reset_ignore
},
2425 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2426 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2427 .access
= PL0_R
| PL1_W
,
2428 .fgt
= FGT_TPIDRRO_EL0
,
2429 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2431 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2432 .access
= PL0_R
| PL1_W
,
2433 .fgt
= FGT_TPIDRRO_EL0
,
2434 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2435 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2436 .resetfn
= arm_cp_reset_ignore
},
2437 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2438 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2440 .fgt
= FGT_TPIDR_EL1
,
2441 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2442 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2444 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2445 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2449 #ifndef CONFIG_USER_ONLY
2451 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2455 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2456 * Writable only at the highest implemented exception level.
2458 int el
= arm_current_el(env
);
2464 hcr
= arm_hcr_el2_eff(env
);
2465 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2466 cntkctl
= env
->cp15
.cnthctl_el2
;
2468 cntkctl
= env
->cp15
.c14_cntkctl
;
2470 if (!extract32(cntkctl
, 0, 2)) {
2471 return CP_ACCESS_TRAP
;
2475 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2476 arm_is_secure_below_el3(env
)) {
2477 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2478 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2486 if (!isread
&& el
< arm_highest_el(env
)) {
2487 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2490 return CP_ACCESS_OK
;
2493 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2496 unsigned int cur_el
= arm_current_el(env
);
2497 bool has_el2
= arm_is_el2_enabled(env
);
2498 uint64_t hcr
= arm_hcr_el2_eff(env
);
2502 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2503 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2504 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2505 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2508 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2509 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2510 return CP_ACCESS_TRAP
;
2514 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2515 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2517 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2518 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2519 return CP_ACCESS_TRAP_EL2
;
2523 return CP_ACCESS_OK
;
2526 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2529 unsigned int cur_el
= arm_current_el(env
);
2530 bool has_el2
= arm_is_el2_enabled(env
);
2531 uint64_t hcr
= arm_hcr_el2_eff(env
);
2535 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2536 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2537 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2538 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2542 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2543 * EL0 if EL0[PV]TEN is zero.
2545 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2546 return CP_ACCESS_TRAP
;
2551 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2552 if (hcr
& HCR_E2H
) {
2553 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2554 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2555 return CP_ACCESS_TRAP_EL2
;
2558 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2559 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2560 return CP_ACCESS_TRAP_EL2
;
2566 return CP_ACCESS_OK
;
2569 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2570 const ARMCPRegInfo
*ri
,
2573 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2576 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2577 const ARMCPRegInfo
*ri
,
2580 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2583 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2586 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2589 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2592 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2595 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2596 const ARMCPRegInfo
*ri
,
2600 * The AArch64 register view of the secure physical timer is
2601 * always accessible from EL3, and configurably accessible from
2604 switch (arm_current_el(env
)) {
2606 if (!arm_is_secure(env
)) {
2607 return CP_ACCESS_TRAP
;
2609 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2610 return CP_ACCESS_TRAP_EL3
;
2612 return CP_ACCESS_OK
;
2615 return CP_ACCESS_TRAP
;
2617 return CP_ACCESS_OK
;
2619 g_assert_not_reached();
2623 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2625 ARMCPU
*cpu
= env_archcpu(env
);
2627 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2630 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2632 CPUARMState
*env
= &cpu
->env
;
2633 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2634 ARMSecuritySpace ss
= arm_security_space(env
);
2635 /* ISTATUS && !IMASK */
2636 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2639 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2640 * It is RES0 in Secure and NonSecure state.
2642 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2643 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2644 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2648 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2649 trace_arm_gt_update_irq(timeridx
, irqstate
);
2652 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2655 * Changing security state between Root and Secure/NonSecure, which may
2656 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2657 * mask bits. Update the IRQ state accordingly.
2659 gt_update_irq(cpu
, GTIMER_VIRT
);
2660 gt_update_irq(cpu
, GTIMER_PHYS
);
2663 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2665 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2669 * Timer enabled: calculate and set current ISTATUS, irq, and
2670 * reset timer to when ISTATUS next has to change
2672 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2673 cpu
->env
.cp15
.cntvoff_el2
: 0;
2674 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2675 /* Note that this must be unsigned 64 bit arithmetic: */
2676 int istatus
= count
- offset
>= gt
->cval
;
2679 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2683 * Next transition is when (count - offset) rolls back over to 0.
2684 * If offset > count then this is when count == offset;
2685 * if offset <= count then this is when count == offset + 2^64
2686 * For the latter case we set nexttick to an "as far in future
2687 * as possible" value and let the code below handle it.
2689 if (offset
> count
) {
2692 nexttick
= UINT64_MAX
;
2696 * Next transition is when (count - offset) == cval, i.e.
2697 * when count == (cval + offset).
2698 * If that would overflow, then again we set up the next interrupt
2699 * for "as far in the future as possible" for the code below.
2701 if (uadd64_overflow(gt
->cval
, offset
, &nexttick
)) {
2702 nexttick
= UINT64_MAX
;
2706 * Note that the desired next expiry time might be beyond the
2707 * signed-64-bit range of a QEMUTimer -- in this case we just
2708 * set the timer for as far in the future as possible. When the
2709 * timer expires we will reset the timer for any remaining period.
2711 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2712 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2714 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2716 trace_arm_gt_recalc(timeridx
, nexttick
);
2718 /* Timer disabled: ISTATUS and timer output always clear */
2720 timer_del(cpu
->gt_timer
[timeridx
]);
2721 trace_arm_gt_recalc_disabled(timeridx
);
2723 gt_update_irq(cpu
, timeridx
);
2726 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2729 ARMCPU
*cpu
= env_archcpu(env
);
2731 timer_del(cpu
->gt_timer
[timeridx
]);
2734 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2736 return gt_get_countervalue(env
);
2739 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2743 switch (arm_current_el(env
)) {
2745 hcr
= arm_hcr_el2_eff(env
);
2746 if (hcr
& HCR_E2H
) {
2751 hcr
= arm_hcr_el2_eff(env
);
2752 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2758 return env
->cp15
.cntvoff_el2
;
2761 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2763 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2766 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2770 trace_arm_gt_cval_write(timeridx
, value
);
2771 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2772 gt_recalc_timer(env_archcpu(env
), timeridx
);
2775 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2778 uint64_t offset
= 0;
2782 case GTIMER_HYPVIRT
:
2783 offset
= gt_virt_cnt_offset(env
);
2787 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2788 (gt_get_countervalue(env
) - offset
));
2791 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2795 uint64_t offset
= 0;
2799 case GTIMER_HYPVIRT
:
2800 offset
= gt_virt_cnt_offset(env
);
2804 trace_arm_gt_tval_write(timeridx
, value
);
2805 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2806 sextract64(value
, 0, 32);
2807 gt_recalc_timer(env_archcpu(env
), timeridx
);
2810 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2814 ARMCPU
*cpu
= env_archcpu(env
);
2815 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2817 trace_arm_gt_ctl_write(timeridx
, value
);
2818 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2819 if ((oldval
^ value
) & 1) {
2820 /* Enable toggled */
2821 gt_recalc_timer(cpu
, timeridx
);
2822 } else if ((oldval
^ value
) & 2) {
2824 * IMASK toggled: don't need to recalculate,
2825 * just set the interrupt line based on ISTATUS
2827 trace_arm_gt_imask_toggle(timeridx
);
2828 gt_update_irq(cpu
, timeridx
);
2832 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2834 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2837 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2840 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2843 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2845 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2848 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2851 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2854 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2857 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2860 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2862 switch (arm_mmu_idx(env
)) {
2863 case ARMMMUIdx_E20_0
:
2864 case ARMMMUIdx_E20_2
:
2865 case ARMMMUIdx_E20_2_PAN
:
2872 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2874 switch (arm_mmu_idx(env
)) {
2875 case ARMMMUIdx_E20_0
:
2876 case ARMMMUIdx_E20_2
:
2877 case ARMMMUIdx_E20_2_PAN
:
2878 return GTIMER_HYPVIRT
;
2884 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2885 const ARMCPRegInfo
*ri
)
2887 int timeridx
= gt_phys_redir_timeridx(env
);
2888 return env
->cp15
.c14_timer
[timeridx
].cval
;
2891 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2894 int timeridx
= gt_phys_redir_timeridx(env
);
2895 gt_cval_write(env
, ri
, timeridx
, value
);
2898 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2899 const ARMCPRegInfo
*ri
)
2901 int timeridx
= gt_phys_redir_timeridx(env
);
2902 return gt_tval_read(env
, ri
, timeridx
);
2905 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2908 int timeridx
= gt_phys_redir_timeridx(env
);
2909 gt_tval_write(env
, ri
, timeridx
, value
);
2912 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2913 const ARMCPRegInfo
*ri
)
2915 int timeridx
= gt_phys_redir_timeridx(env
);
2916 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2919 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2922 int timeridx
= gt_phys_redir_timeridx(env
);
2923 gt_ctl_write(env
, ri
, timeridx
, value
);
2926 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2928 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2931 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2934 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2937 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2939 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2942 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2945 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2948 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2951 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2954 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2957 ARMCPU
*cpu
= env_archcpu(env
);
2958 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2960 raw_write(env
, ri
, value
);
2962 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2963 gt_update_irq(cpu
, GTIMER_VIRT
);
2964 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2965 gt_update_irq(cpu
, GTIMER_PHYS
);
2969 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2972 ARMCPU
*cpu
= env_archcpu(env
);
2974 trace_arm_gt_cntvoff_write(value
);
2975 raw_write(env
, ri
, value
);
2976 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2979 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2980 const ARMCPRegInfo
*ri
)
2982 int timeridx
= gt_virt_redir_timeridx(env
);
2983 return env
->cp15
.c14_timer
[timeridx
].cval
;
2986 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2989 int timeridx
= gt_virt_redir_timeridx(env
);
2990 gt_cval_write(env
, ri
, timeridx
, value
);
2993 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2994 const ARMCPRegInfo
*ri
)
2996 int timeridx
= gt_virt_redir_timeridx(env
);
2997 return gt_tval_read(env
, ri
, timeridx
);
3000 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3003 int timeridx
= gt_virt_redir_timeridx(env
);
3004 gt_tval_write(env
, ri
, timeridx
, value
);
3007 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
3008 const ARMCPRegInfo
*ri
)
3010 int timeridx
= gt_virt_redir_timeridx(env
);
3011 return env
->cp15
.c14_timer
[timeridx
].ctl
;
3014 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3017 int timeridx
= gt_virt_redir_timeridx(env
);
3018 gt_ctl_write(env
, ri
, timeridx
, value
);
3021 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3023 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3026 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3029 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3032 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3034 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3037 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3040 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3043 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3046 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3049 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3051 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3054 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3057 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3060 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3062 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3065 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3068 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3071 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3074 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3077 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3079 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3082 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3085 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3088 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3090 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3093 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3096 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3099 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3102 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3105 void arm_gt_ptimer_cb(void *opaque
)
3107 ARMCPU
*cpu
= opaque
;
3109 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3112 void arm_gt_vtimer_cb(void *opaque
)
3114 ARMCPU
*cpu
= opaque
;
3116 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3119 void arm_gt_htimer_cb(void *opaque
)
3121 ARMCPU
*cpu
= opaque
;
3123 gt_recalc_timer(cpu
, GTIMER_HYP
);
3126 void arm_gt_stimer_cb(void *opaque
)
3128 ARMCPU
*cpu
= opaque
;
3130 gt_recalc_timer(cpu
, GTIMER_SEC
);
3133 void arm_gt_hvtimer_cb(void *opaque
)
3135 ARMCPU
*cpu
= opaque
;
3137 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3140 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3142 ARMCPU
*cpu
= env_archcpu(env
);
3144 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3147 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3149 * Note that CNTFRQ is purely reads-as-written for the benefit
3150 * of software; writing it doesn't actually change the timer frequency.
3151 * Our reset value matches the fixed frequency we implement the timer at.
3153 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3154 .type
= ARM_CP_ALIAS
,
3155 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3156 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3158 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3159 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3160 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3161 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3162 .resetfn
= arm_gt_cntfrq_reset
,
3164 /* overall control: mostly access permissions */
3165 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3166 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3168 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3171 /* per-timer control */
3172 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3173 .secure
= ARM_CP_SECSTATE_NS
,
3174 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3175 .accessfn
= gt_ptimer_access
,
3176 .fieldoffset
= offsetoflow32(CPUARMState
,
3177 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3178 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3179 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3181 { .name
= "CNTP_CTL_S",
3182 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3183 .secure
= ARM_CP_SECSTATE_S
,
3184 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3185 .accessfn
= gt_ptimer_access
,
3186 .fieldoffset
= offsetoflow32(CPUARMState
,
3187 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3188 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3190 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3191 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3192 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3193 .accessfn
= gt_ptimer_access
,
3194 .nv2_redirect_offset
= 0x180 | NV2_REDIR_NV1
,
3195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3197 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3198 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3200 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3201 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3202 .accessfn
= gt_vtimer_access
,
3203 .fieldoffset
= offsetoflow32(CPUARMState
,
3204 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3205 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3206 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3208 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3209 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3210 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3211 .accessfn
= gt_vtimer_access
,
3212 .nv2_redirect_offset
= 0x170 | NV2_REDIR_NV1
,
3213 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3215 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3216 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3218 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3219 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3220 .secure
= ARM_CP_SECSTATE_NS
,
3221 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3222 .accessfn
= gt_ptimer_access
,
3223 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3225 { .name
= "CNTP_TVAL_S",
3226 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3227 .secure
= ARM_CP_SECSTATE_S
,
3228 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3229 .accessfn
= gt_ptimer_access
,
3230 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3232 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3233 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3234 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3235 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3236 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3238 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3239 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3240 .accessfn
= gt_vtimer_access
,
3241 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3243 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3244 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3245 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3246 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3247 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3249 /* The counter itself */
3250 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3251 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3252 .accessfn
= gt_pct_access
,
3253 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3255 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3256 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3257 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3258 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3260 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3261 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3262 .accessfn
= gt_vct_access
,
3263 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3265 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3266 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3267 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3268 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3270 /* Comparison value, indicating when the timer goes off */
3271 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3272 .secure
= ARM_CP_SECSTATE_NS
,
3274 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3275 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3276 .accessfn
= gt_ptimer_access
,
3277 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3278 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3280 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3281 .secure
= ARM_CP_SECSTATE_S
,
3283 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3284 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3285 .accessfn
= gt_ptimer_access
,
3286 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3288 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3289 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3292 .nv2_redirect_offset
= 0x178 | NV2_REDIR_NV1
,
3293 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3294 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3295 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3296 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3298 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3300 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3301 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3302 .accessfn
= gt_vtimer_access
,
3303 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3304 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3306 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3307 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3310 .nv2_redirect_offset
= 0x168 | NV2_REDIR_NV1
,
3311 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3312 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3313 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3314 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3317 * Secure timer -- this is actually restricted to only EL3
3318 * and configurably Secure-EL1 via the accessfn.
3320 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3321 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3322 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3323 .accessfn
= gt_stimer_access
,
3324 .readfn
= gt_sec_tval_read
,
3325 .writefn
= gt_sec_tval_write
,
3326 .resetfn
= gt_sec_timer_reset
,
3328 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3329 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3330 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3331 .accessfn
= gt_stimer_access
,
3332 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3334 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3336 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3337 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3338 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3339 .accessfn
= gt_stimer_access
,
3340 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3341 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3345 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3348 if (arm_current_el(env
) == 1) {
3349 /* This must be a FEAT_NV access */
3350 /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
3351 return CP_ACCESS_OK
;
3353 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3354 return CP_ACCESS_TRAP
;
3356 return CP_ACCESS_OK
;
3362 * In user-mode most of the generic timer registers are inaccessible
3363 * however modern kernels (4.12+) allow access to cntvct_el0
3366 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3368 ARMCPU
*cpu
= env_archcpu(env
);
3371 * Currently we have no support for QEMUTimer in linux-user so we
3372 * can't call gt_get_countervalue(env), instead we directly
3373 * call the lower level functions.
3375 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3378 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3379 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3380 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3381 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3382 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3383 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3385 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3386 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3387 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3388 .readfn
= gt_virt_cnt_read
,
3394 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3396 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3397 raw_write(env
, ri
, value
);
3398 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3399 raw_write(env
, ri
, value
& 0xfffff6ff);
3401 raw_write(env
, ri
, value
& 0xfffff1ff);
3405 #ifndef CONFIG_USER_ONLY
3406 /* get_phys_addr() isn't present for user-mode-only targets */
3408 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3413 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3414 * Secure EL1 (which can only happen if EL3 is AArch64).
3415 * They are simply UNDEF if executed from NS EL1.
3416 * They function normally from EL2 or EL3.
3418 if (arm_current_el(env
) == 1) {
3419 if (arm_is_secure_below_el3(env
)) {
3420 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3421 return CP_ACCESS_TRAP_EL2
;
3423 return CP_ACCESS_TRAP_EL3
;
3425 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3428 return CP_ACCESS_OK
;
3432 static int par_el1_shareability(GetPhysAddrResult
*res
)
3435 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3436 * memory -- see pseudocode PAREncodeShareability().
3438 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3439 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3442 return res
->cacheattrs
.shareability
;
3445 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3446 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3447 ARMSecuritySpace ss
)
3451 bool format64
= false;
3452 ARMMMUFaultInfo fi
= {};
3453 GetPhysAddrResult res
= {};
3456 * I_MXTJT: Granule protection checks are not performed on the final address
3457 * of a successful translation.
3459 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3463 * ATS operations only do S1 or S1+S2 translations, so we never
3464 * have to deal with the ARMCacheAttrs format for S2 only.
3466 assert(!res
.cacheattrs
.is_s2_format
);
3470 * Some kinds of translation fault must cause exceptions rather
3471 * than being reported in the PAR.
3473 int current_el
= arm_current_el(env
);
3475 uint32_t syn
, fsr
, fsc
;
3476 bool take_exc
= false;
3478 if (fi
.s1ptw
&& current_el
== 1
3479 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3481 * Synchronous stage 2 fault on an access made as part of the
3482 * translation table walk for AT S1E0* or AT S1E1* insn
3483 * executed from NS EL1. If this is a synchronous external abort
3484 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3485 * to EL3. Otherwise the fault is taken as an exception to EL2,
3486 * and HPFAR_EL2 holds the faulting IPA.
3488 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3489 (env
->cp15
.scr_el3
& SCR_EA
)) {
3492 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3493 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3494 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3499 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3501 * Synchronous external aborts during a translation table walk
3502 * are taken as Data Abort exceptions.
3505 if (current_el
== 3) {
3511 target_el
= exception_target_el(env
);
3517 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3518 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3519 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3520 fsr
= arm_fi_to_lfsc(&fi
);
3521 fsc
= extract32(fsr
, 0, 6);
3523 fsr
= arm_fi_to_sfsc(&fi
);
3527 * Report exception with ESR indicating a fault due to a
3528 * translation table walk for a cache maintenance instruction.
3530 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3531 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3532 env
->exception
.vaddress
= value
;
3533 env
->exception
.fsr
= fsr
;
3534 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3540 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3543 * * TTBCR.EAE determines whether the result is returned using the
3544 * 32-bit or the 64-bit PAR format
3545 * * Instructions executed in Hyp mode always use the 64bit format
3547 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3548 * * The Non-secure TTBCR.EAE bit is set to 1
3549 * * The implementation includes EL2, and the value of HCR.VM is 1
3551 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3553 * ATS1Hx always uses the 64bit format.
3555 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3557 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3558 if (mmu_idx
== ARMMMUIdx_E10_0
||
3559 mmu_idx
== ARMMMUIdx_E10_1
||
3560 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3561 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3563 format64
|= arm_current_el(env
) == 2;
3569 /* Create a 64-bit PAR */
3570 par64
= (1 << 11); /* LPAE bit always set */
3572 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3573 if (!res
.f
.attrs
.secure
) {
3574 par64
|= (1 << 9); /* NS */
3576 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3577 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3579 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3582 par64
|= (fsr
& 0x3f) << 1; /* FS */
3584 par64
|= (1 << 9); /* S */
3587 par64
|= (1 << 8); /* PTW */
3592 * fsr is a DFSR/IFSR value for the short descriptor
3593 * translation table format (with WnR always clear).
3594 * Convert it to a 32-bit PAR.
3597 /* We do not set any attribute bits in the PAR */
3598 if (res
.f
.lg_page_size
== 24
3599 && arm_feature(env
, ARM_FEATURE_V7
)) {
3600 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3602 par64
= res
.f
.phys_addr
& 0xfffff000;
3604 if (!res
.f
.attrs
.secure
) {
3605 par64
|= (1 << 9); /* NS */
3608 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3610 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3611 ((fsr
& 0xf) << 1) | 1;
3616 #endif /* CONFIG_TCG */
3618 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3621 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3624 int el
= arm_current_el(env
);
3625 ARMSecuritySpace ss
= arm_security_space(env
);
3627 switch (ri
->opc2
& 6) {
3629 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3632 mmu_idx
= ARMMMUIdx_E3
;
3635 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3638 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3639 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3641 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3645 g_assert_not_reached();
3649 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3652 mmu_idx
= ARMMMUIdx_E10_0
;
3655 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3656 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3659 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3662 g_assert_not_reached();
3666 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3667 mmu_idx
= ARMMMUIdx_E10_1
;
3668 ss
= ARMSS_NonSecure
;
3671 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3672 mmu_idx
= ARMMMUIdx_E10_0
;
3673 ss
= ARMSS_NonSecure
;
3676 g_assert_not_reached();
3679 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3681 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3683 /* Handled by hardware accelerator. */
3684 g_assert_not_reached();
3685 #endif /* CONFIG_TCG */
3688 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3692 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3695 /* There is no SecureEL2 for AArch32. */
3696 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3699 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3701 /* Handled by hardware accelerator. */
3702 g_assert_not_reached();
3703 #endif /* CONFIG_TCG */
3706 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3710 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3711 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3712 * only happen when executing at EL3 because that combination also causes an
3713 * illegal exception return. We don't need to check FEAT_RME either, because
3714 * scr_write() ensures that the NSE bit is not set otherwise.
3716 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3717 return CP_ACCESS_TRAP
;
3719 return CP_ACCESS_OK
;
3722 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3725 if (arm_current_el(env
) == 3 &&
3726 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3727 return CP_ACCESS_TRAP
;
3729 return at_e012_access(env
, ri
, isread
);
3732 static CPAccessResult
at_s1e01_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3735 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_AT
)) {
3736 return CP_ACCESS_TRAP_EL2
;
3738 return at_e012_access(env
, ri
, isread
);
3741 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3745 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3747 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3748 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3750 switch (ri
->opc2
& 6) {
3753 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3754 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3755 mmu_idx
= regime_e20
?
3756 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3758 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3761 case 4: /* AT S1E2R, AT S1E2W */
3762 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3764 case 6: /* AT S1E3R, AT S1E3W */
3765 mmu_idx
= ARMMMUIdx_E3
;
3768 g_assert_not_reached();
3771 case 2: /* AT S1E0R, AT S1E0W */
3772 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3774 case 4: /* AT S12E1R, AT S12E1W */
3775 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3777 case 6: /* AT S12E0R, AT S12E0W */
3778 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3781 g_assert_not_reached();
3784 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3785 mmu_idx
, arm_security_space(env
));
3787 /* Handled by hardware accelerator. */
3788 g_assert_not_reached();
3789 #endif /* CONFIG_TCG */
3793 /* Return basic MPU access permission bits. */
3794 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3801 for (i
= 0; i
< 16; i
+= 2) {
3802 ret
|= (val
>> i
) & mask
;
3808 /* Pad basic MPU access permission bits to extended format. */
3809 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3816 for (i
= 0; i
< 16; i
+= 2) {
3817 ret
|= (val
& mask
) << i
;
3823 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3826 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3829 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3831 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3834 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3837 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3840 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3842 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3845 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3847 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3853 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3857 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3860 ARMCPU
*cpu
= env_archcpu(env
);
3861 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3867 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3868 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3872 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3875 ARMCPU
*cpu
= env_archcpu(env
);
3876 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3878 if (value
>= nrgs
) {
3879 qemu_log_mask(LOG_GUEST_ERROR
,
3880 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3881 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3885 raw_write(env
, ri
, value
);
3888 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3891 ARMCPU
*cpu
= env_archcpu(env
);
3893 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3894 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3897 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3899 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3902 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3905 ARMCPU
*cpu
= env_archcpu(env
);
3907 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3908 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3911 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3913 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3916 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3919 ARMCPU
*cpu
= env_archcpu(env
);
3922 * Ignore writes that would select not implemented region.
3923 * This is architecturally UNPREDICTABLE.
3925 if (value
>= cpu
->pmsav7_dregion
) {
3929 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3932 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3935 ARMCPU
*cpu
= env_archcpu(env
);
3937 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3938 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3941 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3943 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3946 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3949 ARMCPU
*cpu
= env_archcpu(env
);
3951 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3952 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3955 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3957 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3960 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3965 ARMCPU
*cpu
= env_archcpu(env
);
3967 /* Ignore writes to unimplemented regions */
3968 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3969 value
&= MAKE_64BIT_MASK(0, rmax
);
3971 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3973 /* Register alias is only valid for first 32 indexes */
3974 for (n
= 0; n
< rmax
; ++n
) {
3975 bit
= extract32(value
, n
, 1);
3976 env
->pmsav8
.hprlar
[n
] = deposit32(
3977 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3981 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3984 uint32_t result
= 0x0;
3985 ARMCPU
*cpu
= env_archcpu(env
);
3987 /* Register alias is only valid for first 32 indexes */
3988 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3989 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3990 result
|= (0x1 << n
);
3996 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3999 ARMCPU
*cpu
= env_archcpu(env
);
4002 * Ignore writes that would select not implemented region.
4003 * This is architecturally UNPREDICTABLE.
4005 if (value
>= cpu
->pmsav8r_hdregion
) {
4009 env
->pmsav8
.hprselr
= value
;
4012 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4015 ARMCPU
*cpu
= env_archcpu(env
);
4016 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4017 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4019 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4022 if (index
>= cpu
->pmsav8r_hdregion
) {
4025 if (ri
->opc2
& 0x1) {
4026 env
->pmsav8
.hprlar
[index
] = value
;
4028 env
->pmsav8
.hprbar
[index
] = value
;
4031 if (index
>= cpu
->pmsav7_dregion
) {
4034 if (ri
->opc2
& 0x1) {
4035 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
4037 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
4042 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4044 ARMCPU
*cpu
= env_archcpu(env
);
4045 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4046 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4049 if (index
>= cpu
->pmsav8r_hdregion
) {
4052 if (ri
->opc2
& 0x1) {
4053 return env
->pmsav8
.hprlar
[index
];
4055 return env
->pmsav8
.hprbar
[index
];
4058 if (index
>= cpu
->pmsav7_dregion
) {
4061 if (ri
->opc2
& 0x1) {
4062 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4064 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4069 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4071 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4072 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4073 .accessfn
= access_tvm_trvm
,
4074 .readfn
= prbar_read
, .writefn
= prbar_write
},
4076 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4077 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4078 .accessfn
= access_tvm_trvm
,
4079 .readfn
= prlar_read
, .writefn
= prlar_write
},
4080 { .name
= "PRSELR", .resetvalue
= 0,
4081 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4082 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4083 .writefn
= prselr_write
,
4084 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4085 { .name
= "HPRBAR", .resetvalue
= 0,
4086 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4087 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4088 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4090 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4091 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4092 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4093 { .name
= "HPRSELR", .resetvalue
= 0,
4094 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4096 .writefn
= hprselr_write
,
4097 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4099 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4100 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4101 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4104 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4106 * Reset for all these registers is handled in arm_cpu_reset(),
4107 * because the PMSAv7 is also used by M-profile CPUs, which do
4108 * not register cpregs but still need the state to be reset.
4110 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4111 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4112 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4113 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4114 .resetfn
= arm_cp_reset_ignore
},
4115 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4116 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4117 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4118 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4119 .resetfn
= arm_cp_reset_ignore
},
4120 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4121 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4122 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4123 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4124 .resetfn
= arm_cp_reset_ignore
},
4125 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4127 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4128 .writefn
= pmsav7_rgnr_write
,
4129 .resetfn
= arm_cp_reset_ignore
},
4132 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4133 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4134 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4135 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4136 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4137 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4138 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4139 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4140 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4141 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4143 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4145 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4147 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4149 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4151 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4152 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4154 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4155 /* Protection region base and size registers */
4156 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4157 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4158 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4159 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4160 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4161 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4162 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4163 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4164 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4165 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4166 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4167 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4168 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4169 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4171 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4172 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4173 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4174 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4175 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4176 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4177 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4178 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4179 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4182 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4185 ARMCPU
*cpu
= env_archcpu(env
);
4187 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4188 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4190 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4191 * using Long-descriptor translation table format
4193 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4194 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4196 * In an implementation that includes the Security Extensions
4197 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4198 * Short-descriptor translation table format.
4200 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4206 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4208 * With LPAE the TTBCR could result in a change of ASID
4209 * via the TTBCR.A1 bit, so do a TLB flush.
4211 tlb_flush(CPU(cpu
));
4213 raw_write(env
, ri
, value
);
4216 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4219 ARMCPU
*cpu
= env_archcpu(env
);
4221 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4222 tlb_flush(CPU(cpu
));
4223 raw_write(env
, ri
, value
);
4226 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4229 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4230 if (cpreg_field_is_64bit(ri
) &&
4231 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4232 ARMCPU
*cpu
= env_archcpu(env
);
4233 tlb_flush(CPU(cpu
));
4235 raw_write(env
, ri
, value
);
4238 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4242 * If we are running with E2&0 regime, then an ASID is active.
4243 * Flush if that might be changing. Note we're not checking
4244 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4245 * holds the active ASID, only checking the field that might.
4247 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4248 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4249 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4250 ARMMMUIdxBit_E20_2_PAN
|
4252 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4254 raw_write(env
, ri
, value
);
4257 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4260 ARMCPU
*cpu
= env_archcpu(env
);
4261 CPUState
*cs
= CPU(cpu
);
4264 * A change in VMID to the stage2 page table (Stage2) invalidates
4265 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4267 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4268 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4270 raw_write(env
, ri
, value
);
4273 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4274 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4275 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4276 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4277 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4278 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4279 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4280 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4281 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4282 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4283 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4284 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4285 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4286 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4287 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4288 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4290 .nv2_redirect_offset
= 0x220 | NV2_REDIR_NV1
,
4291 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4295 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4296 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4297 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4298 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4300 .nv2_redirect_offset
= 0x138 | NV2_REDIR_NV1
,
4301 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4302 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4303 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4304 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4305 .fgt
= FGT_TTBR0_EL1
,
4306 .nv2_redirect_offset
= 0x200 | NV2_REDIR_NV1
,
4307 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4308 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4309 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4310 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4311 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4312 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4313 .fgt
= FGT_TTBR1_EL1
,
4314 .nv2_redirect_offset
= 0x210 | NV2_REDIR_NV1
,
4315 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4316 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4317 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4318 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4319 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4320 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4322 .nv2_redirect_offset
= 0x120 | NV2_REDIR_NV1
,
4323 .writefn
= vmsa_tcr_el12_write
,
4324 .raw_writefn
= raw_write
,
4326 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4327 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4328 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4329 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4330 .raw_writefn
= raw_write
,
4331 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4332 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4336 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4337 * qemu tlbs nor adjusting cached masks.
4339 static const ARMCPRegInfo ttbcr2_reginfo
= {
4340 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4341 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4342 .type
= ARM_CP_ALIAS
,
4343 .bank_fieldoffsets
= {
4344 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4345 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4349 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4352 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4353 /* The OS_TYPE bit in this register changes the reported CPUID! */
4354 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4355 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4358 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4361 env
->cp15
.c15_threadid
= value
& 0xffff;
4364 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4367 /* Wait-for-interrupt (deprecated) */
4368 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4371 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4375 * On OMAP there are registers indicating the max/min index of dcache lines
4376 * containing a dirty line; cache flush operations have to reset these.
4378 env
->cp15
.c15_i_max
= 0x000;
4379 env
->cp15
.c15_i_min
= 0xff0;
4382 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4383 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4384 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4385 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4387 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4388 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4389 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4391 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4392 .writefn
= omap_ticonfig_write
},
4393 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4395 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4396 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4397 .access
= PL1_RW
, .resetvalue
= 0xff0,
4398 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4399 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4401 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4402 .writefn
= omap_threadid_write
},
4403 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4404 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4405 .type
= ARM_CP_NO_RAW
,
4406 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4408 * TODO: Peripheral port remap register:
4409 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4410 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4413 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4414 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4415 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4416 .writefn
= omap_cachemaint_write
},
4417 { .name
= "C9", .cp
= 15, .crn
= 9,
4418 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4419 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4422 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4425 env
->cp15
.c15_cpar
= value
& 0x3fff;
4428 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4429 { .name
= "XSCALE_CPAR",
4430 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4431 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4432 .writefn
= xscale_cpar_write
, },
4433 { .name
= "XSCALE_AUXCR",
4434 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4435 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4438 * XScale specific cache-lockdown: since we have no cache we NOP these
4439 * and hope the guest does not really rely on cache behaviour.
4441 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4442 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4443 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4444 { .name
= "XSCALE_UNLOCK_ICACHE",
4445 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4446 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4447 { .name
= "XSCALE_DCACHE_LOCK",
4448 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4449 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4450 { .name
= "XSCALE_UNLOCK_DCACHE",
4451 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4452 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4455 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4457 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4458 * implementation of this implementation-defined space.
4459 * Ideally this should eventually disappear in favour of actually
4460 * implementing the correct behaviour for all cores.
4462 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4463 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4465 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4469 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4470 /* Cache status: RAZ because we have no cache so it's always clean */
4471 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4472 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4476 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4477 /* We never have a block transfer operation in progress */
4478 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4479 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4481 /* The cache ops themselves: these all NOP for QEMU */
4482 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4483 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4484 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4485 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4486 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4487 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4488 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4489 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4490 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4491 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4492 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4493 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4496 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4498 * The cache test-and-clean instructions always return (1 << 30)
4499 * to indicate that there are no dirty cache lines.
4501 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4502 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4503 .resetvalue
= (1 << 30) },
4504 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4505 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4506 .resetvalue
= (1 << 30) },
4509 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4510 /* Ignore ReadBuffer accesses */
4511 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4512 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4513 .access
= PL1_RW
, .resetvalue
= 0,
4514 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4517 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4519 unsigned int cur_el
= arm_current_el(env
);
4521 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4522 return env
->cp15
.vpidr_el2
;
4524 return raw_read(env
, ri
);
4527 static uint64_t mpidr_read_val(CPUARMState
*env
)
4529 ARMCPU
*cpu
= env_archcpu(env
);
4530 uint64_t mpidr
= cpu
->mp_affinity
;
4532 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4533 mpidr
|= (1U << 31);
4535 * Cores which are uniprocessor (non-coherent)
4536 * but still implement the MP extensions set
4537 * bit 30. (For instance, Cortex-R5).
4539 if (cpu
->mp_is_up
) {
4540 mpidr
|= (1u << 30);
4546 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4548 unsigned int cur_el
= arm_current_el(env
);
4550 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4551 return env
->cp15
.vmpidr_el2
;
4553 return mpidr_read_val(env
);
4556 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4558 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4559 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4560 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4561 .fgt
= FGT_AMAIR_EL1
,
4562 .nv2_redirect_offset
= 0x148 | NV2_REDIR_NV1
,
4563 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4564 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4565 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4566 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4567 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4568 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4569 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4570 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4571 offsetof(CPUARMState
, cp15
.par_ns
)} },
4572 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4573 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4574 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4575 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4576 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4577 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4578 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4579 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4580 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4581 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4582 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4583 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4586 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4588 return vfp_get_fpcr(env
);
4591 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4594 vfp_set_fpcr(env
, value
);
4597 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4599 return vfp_get_fpsr(env
);
4602 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4605 vfp_set_fpsr(env
, value
);
4608 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4611 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4612 return CP_ACCESS_TRAP
;
4614 return CP_ACCESS_OK
;
4617 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4620 env
->daif
= value
& PSTATE_DAIF
;
4623 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4625 return env
->pstate
& PSTATE_PAN
;
4628 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4631 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4634 static const ARMCPRegInfo pan_reginfo
= {
4635 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4636 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4637 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4638 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4641 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4643 return env
->pstate
& PSTATE_UAO
;
4646 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4649 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4652 static const ARMCPRegInfo uao_reginfo
= {
4653 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4654 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4655 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4656 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4659 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4661 return env
->pstate
& PSTATE_DIT
;
4664 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4667 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4670 static const ARMCPRegInfo dit_reginfo
= {
4671 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4672 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4673 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4674 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4677 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4679 return env
->pstate
& PSTATE_SSBS
;
4682 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4685 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4688 static const ARMCPRegInfo ssbs_reginfo
= {
4689 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4690 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4691 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4692 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4695 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4696 const ARMCPRegInfo
*ri
,
4699 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4700 switch (arm_current_el(env
)) {
4702 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4703 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4704 return CP_ACCESS_TRAP
;
4708 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4709 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4710 return CP_ACCESS_TRAP_EL2
;
4714 return CP_ACCESS_OK
;
4717 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4719 /* Cache invalidate/clean to Point of Unification... */
4720 switch (arm_current_el(env
)) {
4722 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4723 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4724 return CP_ACCESS_TRAP
;
4728 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4729 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4730 return CP_ACCESS_TRAP_EL2
;
4734 return CP_ACCESS_OK
;
4737 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4740 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4743 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4746 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4750 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4751 * Page D4-1736 (DDI0487A.b)
4754 static int vae1_tlbmask(CPUARMState
*env
)
4756 uint64_t hcr
= arm_hcr_el2_eff(env
);
4759 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4760 mask
= ARMMMUIdxBit_E20_2
|
4761 ARMMMUIdxBit_E20_2_PAN
|
4764 mask
= ARMMMUIdxBit_E10_1
|
4765 ARMMMUIdxBit_E10_1_PAN
|
4771 static int vae2_tlbmask(CPUARMState
*env
)
4773 uint64_t hcr
= arm_hcr_el2_eff(env
);
4776 if (hcr
& HCR_E2H
) {
4777 mask
= ARMMMUIdxBit_E20_2
|
4778 ARMMMUIdxBit_E20_2_PAN
|
4781 mask
= ARMMMUIdxBit_E2
;
4786 /* Return 56 if TBI is enabled, 64 otherwise. */
4787 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4790 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4791 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4792 int select
= extract64(addr
, 55, 1);
4794 return (tbi
>> select
) & 1 ? 56 : 64;
4797 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4799 uint64_t hcr
= arm_hcr_el2_eff(env
);
4802 /* Only the regime of the mmu_idx below is significant. */
4803 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4804 mmu_idx
= ARMMMUIdx_E20_0
;
4806 mmu_idx
= ARMMMUIdx_E10_0
;
4809 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4812 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4814 uint64_t hcr
= arm_hcr_el2_eff(env
);
4818 * Only the regime of the mmu_idx below is significant.
4819 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4822 if (hcr
& HCR_E2H
) {
4823 mmu_idx
= ARMMMUIdx_E20_2
;
4825 mmu_idx
= ARMMMUIdx_E2
;
4828 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4831 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4834 CPUState
*cs
= env_cpu(env
);
4835 int mask
= vae1_tlbmask(env
);
4837 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4840 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4843 CPUState
*cs
= env_cpu(env
);
4844 int mask
= vae1_tlbmask(env
);
4846 if (tlb_force_broadcast(env
)) {
4847 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4849 tlb_flush_by_mmuidx(cs
, mask
);
4853 static int e2_tlbmask(CPUARMState
*env
)
4855 return (ARMMMUIdxBit_E20_0
|
4856 ARMMMUIdxBit_E20_2
|
4857 ARMMMUIdxBit_E20_2_PAN
|
4861 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4864 CPUState
*cs
= env_cpu(env
);
4865 int mask
= alle1_tlbmask(env
);
4867 tlb_flush_by_mmuidx(cs
, mask
);
4870 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4873 CPUState
*cs
= env_cpu(env
);
4874 int mask
= e2_tlbmask(env
);
4876 tlb_flush_by_mmuidx(cs
, mask
);
4879 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4882 ARMCPU
*cpu
= env_archcpu(env
);
4883 CPUState
*cs
= CPU(cpu
);
4885 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4888 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4891 CPUState
*cs
= env_cpu(env
);
4892 int mask
= alle1_tlbmask(env
);
4894 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4897 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4900 CPUState
*cs
= env_cpu(env
);
4901 int mask
= e2_tlbmask(env
);
4903 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4906 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4909 CPUState
*cs
= env_cpu(env
);
4911 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4914 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4918 * Invalidate by VA, EL2
4919 * Currently handles both VAE2 and VALE2, since we don't support
4920 * flush-last-level-only.
4922 CPUState
*cs
= env_cpu(env
);
4923 int mask
= vae2_tlbmask(env
);
4924 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4925 int bits
= vae2_tlbbits(env
, pageaddr
);
4927 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4930 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4934 * Invalidate by VA, EL3
4935 * Currently handles both VAE3 and VALE3, since we don't support
4936 * flush-last-level-only.
4938 ARMCPU
*cpu
= env_archcpu(env
);
4939 CPUState
*cs
= CPU(cpu
);
4940 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4942 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4945 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4948 CPUState
*cs
= env_cpu(env
);
4949 int mask
= vae1_tlbmask(env
);
4950 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4951 int bits
= vae1_tlbbits(env
, pageaddr
);
4953 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4956 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4960 * Invalidate by VA, EL1&0 (AArch64 version).
4961 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4962 * since we don't support flush-for-specific-ASID-only or
4963 * flush-last-level-only.
4965 CPUState
*cs
= env_cpu(env
);
4966 int mask
= vae1_tlbmask(env
);
4967 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4968 int bits
= vae1_tlbbits(env
, pageaddr
);
4970 if (tlb_force_broadcast(env
)) {
4971 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4973 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4977 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4980 CPUState
*cs
= env_cpu(env
);
4981 int mask
= vae2_tlbmask(env
);
4982 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4983 int bits
= vae2_tlbbits(env
, pageaddr
);
4985 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4988 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4991 CPUState
*cs
= env_cpu(env
);
4992 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4993 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4995 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4996 ARMMMUIdxBit_E3
, bits
);
4999 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
5002 * The MSB of value is the NS field, which only applies if SEL2
5003 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
5006 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
5007 && arm_is_secure_below_el3(env
)
5008 ? ARMMMUIdxBit_Stage2_S
5009 : ARMMMUIdxBit_Stage2
);
5012 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5015 CPUState
*cs
= env_cpu(env
);
5016 int mask
= ipas2e1_tlbmask(env
, value
);
5017 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5019 if (tlb_force_broadcast(env
)) {
5020 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5022 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
5026 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5029 CPUState
*cs
= env_cpu(env
);
5030 int mask
= ipas2e1_tlbmask(env
, value
);
5031 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5033 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5036 #ifdef TARGET_AARCH64
5042 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
5045 * Note that the TLBI range TG field encoding differs from both
5046 * TG0 and TG1 encodings.
5060 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5063 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5064 /* Extract one bit to represent the va selector in use. */
5065 uint64_t select
= sextract64(value
, 36, 1);
5066 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5067 TLBIRange ret
= { };
5068 ARMGranuleSize gran
;
5070 page_size_granule
= extract64(value
, 46, 2);
5071 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5073 /* The granule encoded in value must match the granule in use. */
5074 if (gran
!= param
.gran
) {
5075 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5080 page_shift
= arm_granule_bits(gran
);
5081 num
= extract64(value
, 39, 5);
5082 scale
= extract64(value
, 44, 2);
5083 exponent
= (5 * scale
) + 1;
5085 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5088 ret
.base
= sextract64(value
, 0, 37);
5090 ret
.base
= extract64(value
, 0, 37);
5094 * With DS=1, BaseADDR is always shifted 16 so that it is able
5095 * to address all 52 va bits. The input address is perforce
5096 * aligned on a 64k boundary regardless of translation granule.
5100 ret
.base
<<= page_shift
;
5105 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5106 int idxmap
, bool synced
)
5108 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5112 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5113 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5116 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5122 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5123 range
.length
, idxmap
, bits
);
5127 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5128 const ARMCPRegInfo
*ri
,
5132 * Invalidate by VA range, EL1&0.
5133 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5134 * since we don't support flush-for-specific-ASID-only or
5135 * flush-last-level-only.
5138 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5139 tlb_force_broadcast(env
));
5142 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5143 const ARMCPRegInfo
*ri
,
5147 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5148 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5149 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5150 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5151 * shareable specific flushes.
5154 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5157 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5158 const ARMCPRegInfo
*ri
,
5162 * Invalidate by VA range, EL2.
5163 * Currently handles all of RVAE2 and RVALE2,
5164 * since we don't support flush-for-specific-ASID-only or
5165 * flush-last-level-only.
5168 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5169 tlb_force_broadcast(env
));
5174 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5175 const ARMCPRegInfo
*ri
,
5179 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5180 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5181 * since we don't support flush-for-specific-ASID-only,
5182 * flush-last-level-only or inner/outer shareable specific flushes.
5185 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5189 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5190 const ARMCPRegInfo
*ri
,
5194 * Invalidate by VA range, EL3.
5195 * Currently handles all of RVAE3 and RVALE3,
5196 * since we don't support flush-for-specific-ASID-only or
5197 * flush-last-level-only.
5200 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5203 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5204 const ARMCPRegInfo
*ri
,
5208 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5209 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5210 * since we don't support flush-for-specific-ASID-only,
5211 * flush-last-level-only or inner/outer specific flushes.
5214 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5217 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5220 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5221 tlb_force_broadcast(env
));
5224 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5225 const ARMCPRegInfo
*ri
,
5228 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5232 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5235 int cur_el
= arm_current_el(env
);
5238 uint64_t hcr
= arm_hcr_el2_eff(env
);
5241 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5242 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5243 return CP_ACCESS_TRAP_EL2
;
5246 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5247 return CP_ACCESS_TRAP
;
5249 if (hcr
& HCR_TDZ
) {
5250 return CP_ACCESS_TRAP_EL2
;
5253 } else if (hcr
& HCR_TDZ
) {
5254 return CP_ACCESS_TRAP_EL2
;
5257 return CP_ACCESS_OK
;
5260 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5262 ARMCPU
*cpu
= env_archcpu(env
);
5263 int dzp_bit
= 1 << 4;
5265 /* DZP indicates whether DC ZVA access is allowed */
5266 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5269 return cpu
->dcz_blocksize
| dzp_bit
;
5272 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5275 if (!(env
->pstate
& PSTATE_SP
)) {
5277 * Access to SP_EL0 is undefined if it's being used as
5278 * the stack pointer.
5280 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5282 return CP_ACCESS_OK
;
5285 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5287 return env
->pstate
& PSTATE_SP
;
5290 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5292 update_spsel(env
, val
);
5295 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5298 ARMCPU
*cpu
= env_archcpu(env
);
5300 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5301 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5305 /* ??? Lots of these bits are not implemented. */
5307 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5308 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5309 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5311 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5312 SCTLR_ATA0
| SCTLR_ATA
);
5316 if (raw_read(env
, ri
) == value
) {
5318 * Skip the TLB flush if nothing actually changed; Linux likes
5319 * to do a lot of pointless SCTLR writes.
5324 raw_write(env
, ri
, value
);
5326 /* This may enable/disable the MMU, so do a TLB flush. */
5327 tlb_flush(CPU(cpu
));
5329 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5331 * Normally we would always end the TB on an SCTLR write; see the
5332 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5333 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5334 * of hflags from the translator, so do it here.
5336 arm_rebuild_hflags(env
);
5340 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5344 * Some MDCR_EL3 bits affect whether PMU counters are running:
5345 * if we are trying to change any of those then we must
5346 * bracket this update with PMU start/finish calls.
5348 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5353 env
->cp15
.mdcr_el3
= value
;
5359 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5362 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5363 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5366 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5370 * Some MDCR_EL2 bits affect whether PMU counters are running:
5371 * if we are trying to change any of those then we must
5372 * bracket this update with PMU start/finish calls.
5374 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5379 env
->cp15
.mdcr_el2
= value
;
5385 static CPAccessResult
access_nv1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5388 if (arm_current_el(env
) == 1) {
5389 uint64_t hcr_nv
= arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
| HCR_NV2
);
5391 if (hcr_nv
== (HCR_NV
| HCR_NV1
)) {
5392 return CP_ACCESS_TRAP_EL2
;
5395 return CP_ACCESS_OK
;
5398 #ifdef CONFIG_USER_ONLY
5400 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5401 * code to get around W^X restrictions, where one region is writable and the
5402 * other is executable.
5404 * Since the executable region is never written to we cannot detect code
5405 * changes when running in user mode, and rely on the emulated JIT telling us
5406 * that the code has changed by executing this instruction.
5408 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5411 uint64_t icache_line_mask
, start_address
, end_address
;
5414 cpu
= env_archcpu(env
);
5416 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5417 start_address
= value
& ~icache_line_mask
;
5418 end_address
= value
| icache_line_mask
;
5422 tb_invalidate_phys_range(start_address
, end_address
);
5428 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5430 * Minimal set of EL0-visible registers. This will need to be expanded
5431 * significantly for system emulation of AArch64 CPUs.
5433 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5434 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5435 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5436 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5437 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5438 .type
= ARM_CP_NO_RAW
,
5439 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5440 .fieldoffset
= offsetof(CPUARMState
, daif
),
5441 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5442 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5443 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5444 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5445 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5446 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5447 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5448 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5449 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5450 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5451 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5452 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5453 .fgt
= FGT_DCZID_EL0
,
5454 .readfn
= aa64_dczid_read
},
5455 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5456 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5457 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5458 #ifndef CONFIG_USER_ONLY
5459 /* Avoid overhead of an access check that always passes in user-mode */
5460 .accessfn
= aa64_zva_access
,
5464 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5465 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5466 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5468 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5469 * don't emulate caches.
5471 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5472 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5473 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5474 .fgt
= FGT_ICIALLUIS
,
5475 .accessfn
= access_ticab
},
5476 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5477 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5478 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5480 .accessfn
= access_tocu
},
5481 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5482 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5485 .accessfn
= access_tocu
,
5486 #ifdef CONFIG_USER_ONLY
5487 .type
= ARM_CP_NO_RAW
,
5488 .writefn
= ic_ivau_write
5493 /* Cache ops: all NOPs since we don't emulate caches */
5494 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5495 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5496 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5498 .type
= ARM_CP_NOP
},
5499 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5500 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5502 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5503 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5504 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5505 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5507 .accessfn
= aa64_cacheop_poc_access
},
5508 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5509 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5511 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5512 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5513 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5514 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5516 .accessfn
= access_tocu
},
5517 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5518 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5519 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5521 .accessfn
= aa64_cacheop_poc_access
},
5522 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5523 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5525 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5526 /* TLBI operations */
5527 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5528 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5529 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5530 .fgt
= FGT_TLBIVMALLE1IS
,
5531 .writefn
= tlbi_aa64_vmalle1is_write
},
5532 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5533 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5534 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5535 .fgt
= FGT_TLBIVAE1IS
,
5536 .writefn
= tlbi_aa64_vae1is_write
},
5537 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5538 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5539 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5540 .fgt
= FGT_TLBIASIDE1IS
,
5541 .writefn
= tlbi_aa64_vmalle1is_write
},
5542 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5543 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5544 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5545 .fgt
= FGT_TLBIVAAE1IS
,
5546 .writefn
= tlbi_aa64_vae1is_write
},
5547 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5548 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5549 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5550 .fgt
= FGT_TLBIVALE1IS
,
5551 .writefn
= tlbi_aa64_vae1is_write
},
5552 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5553 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5554 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5555 .fgt
= FGT_TLBIVAALE1IS
,
5556 .writefn
= tlbi_aa64_vae1is_write
},
5557 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5558 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5559 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5560 .fgt
= FGT_TLBIVMALLE1
,
5561 .writefn
= tlbi_aa64_vmalle1_write
},
5562 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5563 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5564 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5565 .fgt
= FGT_TLBIVAE1
,
5566 .writefn
= tlbi_aa64_vae1_write
},
5567 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5568 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5569 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5570 .fgt
= FGT_TLBIASIDE1
,
5571 .writefn
= tlbi_aa64_vmalle1_write
},
5572 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5573 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5574 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5575 .fgt
= FGT_TLBIVAAE1
,
5576 .writefn
= tlbi_aa64_vae1_write
},
5577 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5578 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5579 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5580 .fgt
= FGT_TLBIVALE1
,
5581 .writefn
= tlbi_aa64_vae1_write
},
5582 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5583 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5584 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5585 .fgt
= FGT_TLBIVAALE1
,
5586 .writefn
= tlbi_aa64_vae1_write
},
5587 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5588 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5589 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5590 .writefn
= tlbi_aa64_ipas2e1is_write
},
5591 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5592 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5593 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5594 .writefn
= tlbi_aa64_ipas2e1is_write
},
5595 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5596 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5597 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5598 .writefn
= tlbi_aa64_alle1is_write
},
5599 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5600 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5601 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5602 .writefn
= tlbi_aa64_alle1is_write
},
5603 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5604 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5605 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5606 .writefn
= tlbi_aa64_ipas2e1_write
},
5607 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5608 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5609 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5610 .writefn
= tlbi_aa64_ipas2e1_write
},
5611 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5612 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5613 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5614 .writefn
= tlbi_aa64_alle1_write
},
5615 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5616 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5617 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5618 .writefn
= tlbi_aa64_alle1is_write
},
5619 #ifndef CONFIG_USER_ONLY
5620 /* 64 bit address translation operations */
5621 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5622 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5623 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5625 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5626 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5627 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5628 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5630 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5631 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5632 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5633 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5635 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5636 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5637 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5638 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5640 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5641 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5642 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5643 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5644 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5645 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5646 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5647 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5648 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5649 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5650 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5651 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5652 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5653 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5654 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5655 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5656 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5657 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5658 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5659 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5660 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5661 .writefn
= ats_write64
},
5662 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5663 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5664 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5665 .writefn
= ats_write64
},
5666 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5667 .type
= ARM_CP_ALIAS
,
5668 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5669 .access
= PL1_RW
, .resetvalue
= 0,
5671 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5672 .writefn
= par_write
},
5674 /* TLB invalidate last level of translation table walk */
5675 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5676 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5677 .writefn
= tlbimva_is_write
},
5678 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5679 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5680 .writefn
= tlbimvaa_is_write
},
5681 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5682 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5683 .writefn
= tlbimva_write
},
5684 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5685 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5686 .writefn
= tlbimvaa_write
},
5687 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5688 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5689 .writefn
= tlbimva_hyp_write
},
5690 { .name
= "TLBIMVALHIS",
5691 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5692 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5693 .writefn
= tlbimva_hyp_is_write
},
5694 { .name
= "TLBIIPAS2",
5695 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5696 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5697 .writefn
= tlbiipas2_hyp_write
},
5698 { .name
= "TLBIIPAS2IS",
5699 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5700 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5701 .writefn
= tlbiipas2is_hyp_write
},
5702 { .name
= "TLBIIPAS2L",
5703 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5704 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5705 .writefn
= tlbiipas2_hyp_write
},
5706 { .name
= "TLBIIPAS2LIS",
5707 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5708 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5709 .writefn
= tlbiipas2is_hyp_write
},
5710 /* 32 bit cache operations */
5711 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5712 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5713 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5714 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5715 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5716 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5717 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5718 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5719 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5720 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5721 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5722 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5723 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5724 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5725 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5726 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5727 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5728 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5729 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5730 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5731 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5732 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5733 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5734 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5735 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5736 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5737 /* MMU Domain access control / MPU write buffer control */
5738 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5739 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5740 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5741 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5742 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5743 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5744 .type
= ARM_CP_ALIAS
,
5745 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5746 .access
= PL1_RW
, .accessfn
= access_nv1
,
5747 .nv2_redirect_offset
= 0x230 | NV2_REDIR_NV1
,
5748 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5749 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5750 .type
= ARM_CP_ALIAS
,
5751 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5752 .access
= PL1_RW
, .accessfn
= access_nv1
,
5753 .nv2_redirect_offset
= 0x160 | NV2_REDIR_NV1
,
5754 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5756 * We rely on the access checks not allowing the guest to write to the
5757 * state field when SPSel indicates that it's being used as the stack
5760 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5761 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5762 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5763 .type
= ARM_CP_ALIAS
,
5764 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5765 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5766 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5767 .nv2_redirect_offset
= 0x240,
5768 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5769 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5770 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5771 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5772 .type
= ARM_CP_NO_RAW
,
5773 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5774 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5775 .type
= ARM_CP_ALIAS
,
5776 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5778 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5779 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5780 .type
= ARM_CP_ALIAS
,
5781 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5783 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5784 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5785 .type
= ARM_CP_ALIAS
,
5786 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5788 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5789 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5790 .type
= ARM_CP_ALIAS
,
5791 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5793 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5794 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5796 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5799 .writefn
= mdcr_el3_write
,
5800 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5801 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5802 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5803 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5804 .writefn
= sdcr_write
,
5805 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5808 /* These are present only when EL1 supports AArch32 */
5809 static const ARMCPRegInfo v8_aa32_el1_reginfo
[] = {
5810 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5811 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5813 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5814 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5815 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5816 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5817 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5818 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5819 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5820 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5821 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5822 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5823 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5826 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5828 ARMCPU
*cpu
= env_archcpu(env
);
5830 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5831 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5833 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5836 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5837 valid_mask
&= ~HCR_HCD
;
5838 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5840 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5841 * However, if we're using the SMC PSCI conduit then QEMU is
5842 * effectively acting like EL3 firmware and so the guest at
5843 * EL2 should retain the ability to prevent EL1 from being
5844 * able to make SMC calls into the ersatz firmware, so in
5845 * that case HCR.TSC should be read/write.
5847 valid_mask
&= ~HCR_TSC
;
5850 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5851 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5852 valid_mask
|= HCR_E2H
;
5854 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5855 valid_mask
|= HCR_TERR
| HCR_TEA
;
5857 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5858 valid_mask
|= HCR_TLOR
;
5860 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5861 valid_mask
|= HCR_API
| HCR_APK
;
5863 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5864 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5866 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5867 valid_mask
|= HCR_ENSCXT
;
5869 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5870 valid_mask
|= HCR_FWB
;
5872 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5873 valid_mask
|= HCR_GPF
;
5875 if (cpu_isar_feature(aa64_nv
, cpu
)) {
5876 valid_mask
|= HCR_NV
| HCR_NV1
| HCR_AT
;
5878 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
5879 valid_mask
|= HCR_NV2
;
5883 if (cpu_isar_feature(any_evt
, cpu
)) {
5884 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5885 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5886 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5889 /* Clear RES0 bits. */
5890 value
&= valid_mask
;
5893 * These bits change the MMU setup:
5894 * HCR_VM enables stage 2 translation
5895 * HCR_PTW forbids certain page-table setups
5896 * HCR_DC disables stage1 and enables stage2 translation
5897 * HCR_DCT enables tagging on (disabled) stage1 translation
5898 * HCR_FWB changes the interpretation of stage2 descriptor bits
5899 * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
5901 if ((env
->cp15
.hcr_el2
^ value
) &
5902 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
| HCR_NV
| HCR_NV1
)) {
5903 tlb_flush(CPU(cpu
));
5905 env
->cp15
.hcr_el2
= value
;
5908 * Updates to VI and VF require us to update the status of
5909 * virtual interrupts, which are the logical OR of these bits
5910 * and the state of the input lines from the GIC. (This requires
5911 * that we have the BQL, which is done by marking the
5912 * reginfo structs as ARM_CP_IO.)
5913 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5914 * possible for it to be taken immediately, because VIRQ and
5915 * VFIQ are masked unless running at EL0 or EL1, and HCR
5916 * can only be written at EL2.
5918 g_assert(bql_locked());
5919 arm_cpu_update_virq(cpu
);
5920 arm_cpu_update_vfiq(cpu
);
5921 arm_cpu_update_vserr(cpu
);
5924 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5926 do_hcr_write(env
, value
, 0);
5929 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5932 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5933 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5934 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5937 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5940 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5941 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5942 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5946 * Return the effective value of HCR_EL2, at the given security state.
5947 * Bits that are not included here:
5948 * RW (read from SCR_EL3.RW as needed)
5950 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5952 uint64_t ret
= env
->cp15
.hcr_el2
;
5954 assert(space
!= ARMSS_Root
);
5956 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5958 * "This register has no effect if EL2 is not enabled in the
5959 * current Security state". This is ARMv8.4-SecEL2 speak for
5960 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5962 * Prior to that, the language was "In an implementation that
5963 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5964 * as if this field is 0 for all purposes other than a direct
5965 * read or write access of HCR_EL2". With lots of enumeration
5966 * on a per-field basis. In current QEMU, this is condition
5967 * is arm_is_secure_below_el3.
5969 * Since the v8.4 language applies to the entire register, and
5970 * appears to be backward compatible, use that.
5976 * For a cpu that supports both aarch64 and aarch32, we can set bits
5977 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5978 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5980 if (!arm_el_is_aa64(env
, 2)) {
5981 uint64_t aa32_valid
;
5984 * These bits are up-to-date as of ARMv8.6.
5985 * For HCR, it's easiest to list just the 2 bits that are invalid.
5986 * For HCR2, list those that are valid.
5988 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5989 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5990 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5994 if (ret
& HCR_TGE
) {
5995 /* These bits are up-to-date as of ARMv8.6. */
5996 if (ret
& HCR_E2H
) {
5997 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5998 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5999 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
6000 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
6001 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
6002 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
6004 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
6006 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
6007 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
6008 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
6015 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
6017 if (arm_feature(env
, ARM_FEATURE_M
)) {
6020 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
6024 * Corresponds to ARM pseudocode function ELIsInHost().
6026 bool el_is_in_host(CPUARMState
*env
, int el
)
6031 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
6032 * Perform the simplest bit tests first, and validate EL2 afterward.
6035 return false; /* EL1 or EL3 */
6039 * Note that hcr_write() checks isar_feature_aa64_vh(),
6040 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
6042 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
6043 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
6047 /* TGE and/or E2H set: double check those bits are currently legal. */
6048 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
6051 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6054 uint64_t valid_mask
= 0;
6056 /* FEAT_MOPS adds MSCEn and MCE2 */
6057 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6058 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
6061 /* Clear RES0 bits. */
6062 env
->cp15
.hcrx_el2
= value
& valid_mask
;
6065 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6068 if (arm_current_el(env
) == 2
6069 && arm_feature(env
, ARM_FEATURE_EL3
)
6070 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6071 return CP_ACCESS_TRAP_EL3
;
6073 return CP_ACCESS_OK
;
6076 static const ARMCPRegInfo hcrx_el2_reginfo
= {
6077 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
6078 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
6079 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
6080 .nv2_redirect_offset
= 0xa0,
6081 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
6084 /* Return the effective value of HCRX_EL2. */
6085 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
6088 * The bits in this register behave as 0 for all purposes other than
6089 * direct reads of the register if SCR_EL3.HXEn is 0.
6090 * If EL2 is not enabled in the current security state, then the
6091 * bit may behave as if 0, or as if 1, depending on the bit.
6092 * For the moment, we treat the EL2-disabled case as taking
6093 * priority over the HXEn-disabled case. This is true for the only
6094 * bit for a feature which we implement where the answer is different
6095 * for the two cases (MSCEn for FEAT_MOPS).
6096 * This may need to be revisited for future bits.
6098 if (!arm_is_el2_enabled(env
)) {
6100 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6101 /* MSCEn behaves as 1 if EL2 is not enabled */
6106 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6109 return env
->cp15
.hcrx_el2
;
6112 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6116 * For A-profile AArch32 EL3, if NSACR.CP10
6117 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6119 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6120 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6121 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6122 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6124 env
->cp15
.cptr_el
[2] = value
;
6127 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6130 * For A-profile AArch32 EL3, if NSACR.CP10
6131 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6133 uint64_t value
= env
->cp15
.cptr_el
[2];
6135 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6136 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6137 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6142 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6143 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6145 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6146 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6147 .nv2_redirect_offset
= 0x78,
6148 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6149 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6150 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6151 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6152 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6153 .writefn
= hcr_writelow
},
6154 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6155 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6156 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6157 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6158 .type
= ARM_CP_ALIAS
| ARM_CP_NV2_REDIRECT
,
6159 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6161 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6162 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6163 .type
= ARM_CP_NV2_REDIRECT
,
6164 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6165 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6166 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6167 .type
= ARM_CP_NV2_REDIRECT
,
6168 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6169 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6170 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6171 .type
= ARM_CP_ALIAS
,
6172 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6174 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6175 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6176 .type
= ARM_CP_ALIAS
| ARM_CP_NV2_REDIRECT
,
6177 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6179 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6180 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6181 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6182 .access
= PL2_RW
, .writefn
= vbar_write
,
6183 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6185 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6186 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6187 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6188 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6189 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6190 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6191 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6192 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6193 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6194 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6195 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6196 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6198 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6199 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6200 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6201 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6202 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6203 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6204 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6206 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6207 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6208 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6209 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6211 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6212 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6213 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6215 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6216 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6217 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6219 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6220 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6221 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6222 .raw_writefn
= raw_write
,
6223 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6224 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6225 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6226 .type
= ARM_CP_ALIAS
,
6227 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6228 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6229 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6230 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6232 .nv2_redirect_offset
= 0x40,
6233 /* no .writefn needed as this can't cause an ASID change */
6234 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6235 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6236 .cp
= 15, .opc1
= 6, .crm
= 2,
6237 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6238 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6239 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6240 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6241 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6242 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6243 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6244 .nv2_redirect_offset
= 0x20,
6245 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6246 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6247 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6248 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6249 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6250 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6251 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6252 .access
= PL2_RW
, .resetvalue
= 0,
6253 .nv2_redirect_offset
= 0x90,
6254 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6255 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6256 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6257 .access
= PL2_RW
, .resetvalue
= 0,
6258 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6259 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6260 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6261 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6262 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6263 { .name
= "TLBIALLNSNH",
6264 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6265 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6266 .writefn
= tlbiall_nsnh_write
},
6267 { .name
= "TLBIALLNSNHIS",
6268 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6269 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6270 .writefn
= tlbiall_nsnh_is_write
},
6271 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6272 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6273 .writefn
= tlbiall_hyp_write
},
6274 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6275 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6276 .writefn
= tlbiall_hyp_is_write
},
6277 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6278 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6279 .writefn
= tlbimva_hyp_write
},
6280 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6281 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6282 .writefn
= tlbimva_hyp_is_write
},
6283 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6284 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6285 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6286 .writefn
= tlbi_aa64_alle2_write
},
6287 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6288 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6289 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6290 .writefn
= tlbi_aa64_vae2_write
},
6291 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6292 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6293 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6294 .writefn
= tlbi_aa64_vae2_write
},
6295 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6296 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6297 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6298 .writefn
= tlbi_aa64_alle2is_write
},
6299 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6300 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6301 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6302 .writefn
= tlbi_aa64_vae2is_write
},
6303 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6304 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6305 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6306 .writefn
= tlbi_aa64_vae2is_write
},
6307 #ifndef CONFIG_USER_ONLY
6309 * Unlike the other EL2-related AT operations, these must
6310 * UNDEF from EL3 if EL2 is not implemented, which is why we
6311 * define them here rather than with the rest of the AT ops.
6313 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6314 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6315 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6316 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6317 .writefn
= ats_write64
},
6318 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6319 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6320 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6321 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6322 .writefn
= ats_write64
},
6324 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6325 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6326 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6327 * to behave as if SCR.NS was 1.
6329 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6331 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6332 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6334 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6335 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6336 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6338 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6339 * reset values as IMPDEF. We choose to reset to 3 to comply with
6340 * both ARMv7 and ARMv8.
6342 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6343 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6344 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6345 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6346 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6347 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6348 .writefn
= gt_cntvoff_write
,
6349 .nv2_redirect_offset
= 0x60,
6350 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6351 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6352 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6353 .writefn
= gt_cntvoff_write
,
6354 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6355 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6356 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6357 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6358 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6359 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6360 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6361 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6362 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6363 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6364 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6365 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6366 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6367 .resetfn
= gt_hyp_timer_reset
,
6368 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6369 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6371 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6373 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6375 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6377 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6378 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6379 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6380 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6381 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6382 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6384 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6385 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6386 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6388 .nv2_redirect_offset
= 0x80,
6389 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6392 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6393 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6394 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6395 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6397 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6398 .writefn
= hcr_writehigh
},
6401 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6404 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6405 return CP_ACCESS_OK
;
6407 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6410 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6411 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6412 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6413 .access
= PL2_RW
, .accessfn
= sel2_access
,
6414 .nv2_redirect_offset
= 0x30,
6415 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6416 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6417 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6418 .access
= PL2_RW
, .accessfn
= sel2_access
,
6419 .nv2_redirect_offset
= 0x48,
6420 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6423 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6427 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6428 * At Secure EL1 it traps to EL3 or EL2.
6430 if (arm_current_el(env
) == 3) {
6431 return CP_ACCESS_OK
;
6433 if (arm_is_secure_below_el3(env
)) {
6434 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6435 return CP_ACCESS_TRAP_EL2
;
6437 return CP_ACCESS_TRAP_EL3
;
6439 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6441 return CP_ACCESS_OK
;
6443 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6446 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6447 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6448 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6449 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6450 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6451 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6452 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6453 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6454 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6455 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6456 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6457 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6458 .access
= PL3_RW
, .resetvalue
= 0,
6459 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6461 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6462 .access
= PL3_RW
, .resetvalue
= 0,
6463 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6464 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6465 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6466 .writefn
= vbar_write
, .resetvalue
= 0,
6467 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6468 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6469 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6470 .access
= PL3_RW
, .resetvalue
= 0,
6471 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6472 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6473 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6475 /* no .writefn needed as this can't cause an ASID change */
6477 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6478 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6479 .type
= ARM_CP_ALIAS
,
6480 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6482 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6483 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6484 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6485 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6486 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6487 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6488 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6489 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6490 .type
= ARM_CP_ALIAS
,
6491 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6493 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6494 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6495 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6496 .access
= PL3_RW
, .writefn
= vbar_write
,
6497 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6499 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6500 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6501 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6502 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6503 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6504 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6505 .access
= PL3_RW
, .resetvalue
= 0,
6506 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6507 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6508 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6509 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6511 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6512 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6513 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6515 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6516 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6517 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6519 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6520 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6521 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6522 .writefn
= tlbi_aa64_alle3is_write
},
6523 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6524 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6525 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6526 .writefn
= tlbi_aa64_vae3is_write
},
6527 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6528 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6529 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6530 .writefn
= tlbi_aa64_vae3is_write
},
6531 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6532 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6533 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6534 .writefn
= tlbi_aa64_alle3_write
},
6535 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6536 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6537 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6538 .writefn
= tlbi_aa64_vae3_write
},
6539 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6540 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6541 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6542 .writefn
= tlbi_aa64_vae3_write
},
6545 #ifndef CONFIG_USER_ONLY
6546 /* Test if system register redirection is to occur in the current state. */
6547 static bool redirect_for_e2h(CPUARMState
*env
)
6549 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6552 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6556 if (redirect_for_e2h(env
)) {
6557 /* Switch to the saved EL2 version of the register. */
6559 readfn
= ri
->readfn
;
6561 readfn
= ri
->orig_readfn
;
6563 if (readfn
== NULL
) {
6566 return readfn(env
, ri
);
6569 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6574 if (redirect_for_e2h(env
)) {
6575 /* Switch to the saved EL2 version of the register. */
6577 writefn
= ri
->writefn
;
6579 writefn
= ri
->orig_writefn
;
6581 if (writefn
== NULL
) {
6582 writefn
= raw_write
;
6584 writefn(env
, ri
, value
);
6587 static uint64_t el2_e2h_e12_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6589 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6590 return ri
->orig_readfn(env
, ri
->opaque
);
6593 static void el2_e2h_e12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6596 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6597 return ri
->orig_writefn(env
, ri
->opaque
, value
);
6600 static CPAccessResult
el2_e2h_e12_access(CPUARMState
*env
,
6601 const ARMCPRegInfo
*ri
,
6604 if (arm_current_el(env
) == 1) {
6606 * This must be a FEAT_NV access (will either trap or redirect
6607 * to memory). None of the registers with _EL12 aliases want to
6608 * apply their trap controls for this kind of access, so don't
6609 * call the orig_accessfn or do the "UNDEF when E2H is 0" check.
6611 return CP_ACCESS_OK
;
6613 /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
6614 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6615 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6617 if (ri
->orig_accessfn
) {
6618 return ri
->orig_accessfn(env
, ri
->opaque
, isread
);
6620 return CP_ACCESS_OK
;
6623 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6626 uint32_t src_key
, dst_key
, new_key
;
6627 const char *src_name
, *dst_name
, *new_name
;
6628 bool (*feature
)(const ARMISARegisters
*id
);
6631 #define K(op0, op1, crn, crm, op2) \
6632 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6634 static const struct E2HAlias aliases
[] = {
6635 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6636 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6637 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6638 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6639 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6640 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6641 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6642 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6643 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6644 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6645 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6646 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6647 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6648 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6649 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6650 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6651 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6652 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6653 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6654 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6655 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6656 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6657 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6658 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6659 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6660 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6661 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6662 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6663 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6664 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6665 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6666 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6669 * Note that redirection of ZCR is mentioned in the description
6670 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6671 * not in the summary table.
6673 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6674 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6675 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6676 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6678 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6679 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6681 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6682 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6683 isar_feature_aa64_scxtnum
},
6685 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6686 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6692 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6693 const struct E2HAlias
*a
= &aliases
[i
];
6694 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6697 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6701 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6702 (gpointer
)(uintptr_t)a
->src_key
);
6703 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6704 (gpointer
)(uintptr_t)a
->dst_key
);
6705 g_assert(src_reg
!= NULL
);
6706 g_assert(dst_reg
!= NULL
);
6708 /* Cross-compare names to detect typos in the keys. */
6709 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6710 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6712 /* None of the core system registers use opaque; we will. */
6713 g_assert(src_reg
->opaque
== NULL
);
6715 /* Create alias before redirection so we dup the right data. */
6716 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6718 new_reg
->name
= a
->new_name
;
6719 new_reg
->type
|= ARM_CP_ALIAS
;
6720 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6721 new_reg
->access
&= PL2_RW
| PL3_RW
;
6722 /* The new_reg op fields are as per new_key, not the target reg */
6723 new_reg
->crn
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRN_MASK
)
6724 >> CP_REG_ARM64_SYSREG_CRN_SHIFT
;
6725 new_reg
->crm
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRM_MASK
)
6726 >> CP_REG_ARM64_SYSREG_CRM_SHIFT
;
6727 new_reg
->opc0
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP0_MASK
)
6728 >> CP_REG_ARM64_SYSREG_OP0_SHIFT
;
6729 new_reg
->opc1
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP1_MASK
)
6730 >> CP_REG_ARM64_SYSREG_OP1_SHIFT
;
6731 new_reg
->opc2
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP2_MASK
)
6732 >> CP_REG_ARM64_SYSREG_OP2_SHIFT
;
6733 new_reg
->opaque
= src_reg
;
6734 new_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6735 new_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6736 new_reg
->orig_accessfn
= src_reg
->accessfn
;
6737 if (!new_reg
->raw_readfn
) {
6738 new_reg
->raw_readfn
= raw_read
;
6740 if (!new_reg
->raw_writefn
) {
6741 new_reg
->raw_writefn
= raw_write
;
6743 new_reg
->readfn
= el2_e2h_e12_read
;
6744 new_reg
->writefn
= el2_e2h_e12_write
;
6745 new_reg
->accessfn
= el2_e2h_e12_access
;
6748 * If the _EL1 register is redirected to memory by FEAT_NV2,
6749 * then it shares the offset with the _EL12 register,
6750 * and which one is redirected depends on HCR_EL2.NV1.
6752 if (new_reg
->nv2_redirect_offset
) {
6753 assert(new_reg
->nv2_redirect_offset
& NV2_REDIR_NV1
);
6754 new_reg
->nv2_redirect_offset
&= ~NV2_REDIR_NV1
;
6755 new_reg
->nv2_redirect_offset
|= NV2_REDIR_NO_NV1
;
6758 ok
= g_hash_table_insert(cpu
->cp_regs
,
6759 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6762 src_reg
->opaque
= dst_reg
;
6763 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6764 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6765 if (!src_reg
->raw_readfn
) {
6766 src_reg
->raw_readfn
= raw_read
;
6768 if (!src_reg
->raw_writefn
) {
6769 src_reg
->raw_writefn
= raw_write
;
6771 src_reg
->readfn
= el2_e2h_read
;
6772 src_reg
->writefn
= el2_e2h_write
;
6777 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6780 int cur_el
= arm_current_el(env
);
6783 uint64_t hcr
= arm_hcr_el2_eff(env
);
6786 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6787 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6788 return CP_ACCESS_TRAP_EL2
;
6791 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6792 return CP_ACCESS_TRAP
;
6794 if (hcr
& HCR_TID2
) {
6795 return CP_ACCESS_TRAP_EL2
;
6798 } else if (hcr
& HCR_TID2
) {
6799 return CP_ACCESS_TRAP_EL2
;
6803 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6804 return CP_ACCESS_TRAP_EL2
;
6807 return CP_ACCESS_OK
;
6811 * Check for traps to RAS registers, which are controlled
6812 * by HCR_EL2.TERR and SCR_EL3.TERR.
6814 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6817 int el
= arm_current_el(env
);
6819 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6820 return CP_ACCESS_TRAP_EL2
;
6822 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6823 return CP_ACCESS_TRAP_EL3
;
6825 return CP_ACCESS_OK
;
6828 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6830 int el
= arm_current_el(env
);
6832 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6833 return env
->cp15
.vdisr_el2
;
6835 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6836 return 0; /* RAZ/WI */
6838 return env
->cp15
.disr_el1
;
6841 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6843 int el
= arm_current_el(env
);
6845 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6846 env
->cp15
.vdisr_el2
= val
;
6849 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6850 return; /* RAZ/WI */
6852 env
->cp15
.disr_el1
= val
;
6856 * Minimal RAS implementation with no Error Records.
6857 * Which means that all of the Error Record registers:
6865 * ERXPFGCDN_EL1 (RASv1p1)
6866 * ERXPFGCTL_EL1 (RASv1p1)
6867 * ERXPFGF_EL1 (RASv1p1)
6871 * may generate UNDEFINED, which is the effect we get by not
6872 * listing them at all.
6874 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6875 * is higher priority than FGT-to-EL2 so we do not need to list them
6876 * in order to check for an FGT.
6878 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6879 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6880 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6881 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6882 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6883 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6884 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6885 .access
= PL1_R
, .accessfn
= access_terr
,
6886 .fgt
= FGT_ERRIDR_EL1
,
6887 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6888 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6889 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6890 .nv2_redirect_offset
= 0x500,
6891 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6892 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6893 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6894 .nv2_redirect_offset
= 0x508,
6895 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6899 * Return the exception level to which exceptions should be taken
6900 * via SVEAccessTrap. This excludes the check for whether the exception
6901 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6902 * be found by testing 0 < fp_exception_el < sve_exception_el.
6904 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6905 * pseudocode does *not* separate out the FP trap checks, but has them
6906 * all in one function.
6908 int sve_exception_el(CPUARMState
*env
, int el
)
6910 #ifndef CONFIG_USER_ONLY
6911 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6912 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6924 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6925 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6926 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6927 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6929 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6938 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6944 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6945 if (arm_feature(env
, ARM_FEATURE_EL3
)
6946 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6954 * Return the exception level to which exceptions should be taken for SME.
6955 * C.f. the ARM pseudocode function CheckSMEAccess.
6957 int sme_exception_el(CPUARMState
*env
, int el
)
6959 #ifndef CONFIG_USER_ONLY
6960 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6961 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6973 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6974 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6975 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6976 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6978 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6987 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6993 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6994 if (arm_feature(env
, ARM_FEATURE_EL3
)
6995 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7003 * Given that SVE is enabled, return the vector length for EL.
7005 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
7007 ARMCPU
*cpu
= env_archcpu(env
);
7008 uint64_t *cr
= env
->vfp
.zcr_el
;
7009 uint32_t map
= cpu
->sve_vq
.map
;
7010 uint32_t len
= ARM_MAX_VQ
- 1;
7013 cr
= env
->vfp
.smcr_el
;
7014 map
= cpu
->sme_vq
.map
;
7017 if (el
<= 1 && !el_is_in_host(env
, el
)) {
7018 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
7020 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
7021 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
7023 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7024 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
7027 map
&= MAKE_64BIT_MASK(0, len
+ 1);
7029 return 31 - clz32(map
);
7032 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
7034 return ctz32(cpu
->sme_vq
.map
);
7037 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
7039 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
7042 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7045 int cur_el
= arm_current_el(env
);
7046 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7049 /* Bits other than [3:0] are RAZ/WI. */
7050 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
7051 raw_write(env
, ri
, value
& 0xf);
7054 * Because we arrived here, we know both FP and SVE are enabled;
7055 * otherwise we would have trapped access to the ZCR_ELn register.
7057 new_len
= sve_vqm1_for_el(env
, cur_el
);
7058 if (new_len
< old_len
) {
7059 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7063 static const ARMCPRegInfo zcr_reginfo
[] = {
7064 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
7065 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
7066 .nv2_redirect_offset
= 0x1e0 | NV2_REDIR_NV1
,
7067 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
7068 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
7069 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7070 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
7071 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
7072 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
7073 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
7074 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7075 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
7076 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
7077 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
7078 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
7079 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7082 #ifdef TARGET_AARCH64
7083 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7086 int el
= arm_current_el(env
);
7089 uint64_t sctlr
= arm_sctlr(env
, el
);
7090 if (!(sctlr
& SCTLR_EnTP2
)) {
7091 return CP_ACCESS_TRAP
;
7094 /* TODO: FEAT_FGT */
7096 && arm_feature(env
, ARM_FEATURE_EL3
)
7097 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
7098 return CP_ACCESS_TRAP_EL3
;
7100 return CP_ACCESS_OK
;
7103 static CPAccessResult
access_smprimap(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7106 /* If EL1 this is a FEAT_NV access and CPTR_EL3.ESM doesn't apply */
7107 if (arm_current_el(env
) == 2
7108 && arm_feature(env
, ARM_FEATURE_EL3
)
7109 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7110 return CP_ACCESS_TRAP_EL3
;
7112 return CP_ACCESS_OK
;
7115 static CPAccessResult
access_smpri(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7118 if (arm_current_el(env
) < 3
7119 && arm_feature(env
, ARM_FEATURE_EL3
)
7120 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7121 return CP_ACCESS_TRAP_EL3
;
7123 return CP_ACCESS_OK
;
7127 static void arm_reset_sve_state(CPUARMState
*env
)
7129 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
7130 /* Recall that FFR is stored as pregs[16]. */
7131 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
7132 vfp_set_fpcr(env
, 0x0800009f);
7135 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
7137 uint64_t change
= (env
->svcr
^ new) & mask
;
7142 env
->svcr
^= change
;
7144 if (change
& R_SVCR_SM_MASK
) {
7145 arm_reset_sve_state(env
);
7151 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
7152 * on enable: while disabled, the storage is inaccessible and the
7153 * value does not matter. We're not saving the storage in vmstate
7154 * when disabled either.
7156 if (change
& new & R_SVCR_ZA_MASK
) {
7157 memset(env
->zarray
, 0, sizeof(env
->zarray
));
7160 if (tcg_enabled()) {
7161 arm_rebuild_hflags(env
);
7165 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7168 aarch64_set_svcr(env
, value
, -1);
7171 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7174 int cur_el
= arm_current_el(env
);
7175 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7178 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
7179 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
7180 raw_write(env
, ri
, value
);
7183 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7184 * when SVL is widened (old values kept, or zeros). Choose to keep the
7185 * current values for simplicity. But for QEMU internals, we must still
7186 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7187 * above aarch64_sve_narrow_vq.
7189 new_len
= sve_vqm1_for_el(env
, cur_el
);
7190 if (new_len
< old_len
) {
7191 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7195 static const ARMCPRegInfo sme_reginfo
[] = {
7196 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7197 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7198 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7199 .fgt
= FGT_NTPIDR2_EL0
,
7200 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7201 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7202 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7203 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7204 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7205 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7206 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7207 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7208 .nv2_redirect_offset
= 0x1f0 | NV2_REDIR_NV1
,
7209 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7210 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7211 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7212 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7213 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7214 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7215 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7216 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7217 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7218 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7219 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7220 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7221 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7222 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7223 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7224 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7226 * IMPLEMENTOR = 0 (software)
7227 * REVISION = 0 (implementation defined)
7228 * SMPS = 0 (no streaming execution priority in QEMU)
7229 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7231 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7233 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7235 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7236 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7237 .access
= PL1_RW
, .accessfn
= access_smpri
,
7238 .fgt
= FGT_NSMPRI_EL1
,
7239 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7240 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7241 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7242 .nv2_redirect_offset
= 0x1f8,
7243 .access
= PL2_RW
, .accessfn
= access_smprimap
,
7244 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7247 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7250 CPUState
*cs
= env_cpu(env
);
7255 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7258 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7259 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7260 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7261 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7263 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7266 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7268 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7269 env_archcpu(env
)->reset_l0gptsz
);
7272 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7275 CPUState
*cs
= env_cpu(env
);
7277 tlb_flush_all_cpus_synced(cs
);
7280 static const ARMCPRegInfo rme_reginfo
[] = {
7281 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7282 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7283 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7284 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7285 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7286 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7287 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7288 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7289 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7290 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7291 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7292 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7293 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7294 .writefn
= tlbi_aa64_paall_write
},
7295 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7296 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7297 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7298 .writefn
= tlbi_aa64_paallos_write
},
7300 * QEMU does not have a way to invalidate by physical address, thus
7301 * invalidating a range of physical addresses is accomplished by
7302 * flushing all tlb entries in the outer shareable domain,
7303 * just like PAALLOS.
7305 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7306 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7307 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7308 .writefn
= tlbi_aa64_paallos_write
},
7309 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7310 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7311 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7312 .writefn
= tlbi_aa64_paallos_write
},
7313 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7314 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7315 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7318 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7319 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7320 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7321 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7323 #endif /* TARGET_AARCH64 */
7325 static void define_pmu_regs(ARMCPU
*cpu
)
7328 * v7 performance monitor control register: same implementor
7329 * field as main ID register, and we implement four counters in
7330 * addition to the cycle count register.
7332 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7333 ARMCPRegInfo pmcr
= {
7334 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7336 .fgt
= FGT_PMCR_EL0
,
7337 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7338 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7339 .accessfn
= pmreg_access
,
7340 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7341 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7343 ARMCPRegInfo pmcr64
= {
7344 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7345 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7346 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7347 .fgt
= FGT_PMCR_EL0
,
7349 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7350 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7351 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7352 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7355 define_one_arm_cp_reg(cpu
, &pmcr
);
7356 define_one_arm_cp_reg(cpu
, &pmcr64
);
7357 for (i
= 0; i
< pmcrn
; i
++) {
7358 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7359 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7360 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7361 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7362 ARMCPRegInfo pmev_regs
[] = {
7363 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7364 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7365 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7366 .fgt
= FGT_PMEVCNTRN_EL0
,
7367 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7368 .accessfn
= pmreg_access_xevcntr
},
7369 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7370 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7371 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7373 .fgt
= FGT_PMEVCNTRN_EL0
,
7374 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7375 .raw_readfn
= pmevcntr_rawread
,
7376 .raw_writefn
= pmevcntr_rawwrite
},
7377 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7378 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7379 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7380 .fgt
= FGT_PMEVTYPERN_EL0
,
7381 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7382 .accessfn
= pmreg_access
},
7383 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7384 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7385 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7386 .fgt
= FGT_PMEVTYPERN_EL0
,
7388 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7389 .raw_writefn
= pmevtyper_rawwrite
},
7391 define_arm_cp_regs(cpu
, pmev_regs
);
7392 g_free(pmevcntr_name
);
7393 g_free(pmevcntr_el0_name
);
7394 g_free(pmevtyper_name
);
7395 g_free(pmevtyper_el0_name
);
7397 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7398 ARMCPRegInfo v81_pmu_regs
[] = {
7399 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7400 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7401 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7402 .fgt
= FGT_PMCEIDN_EL0
,
7403 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7404 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7405 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7406 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7407 .fgt
= FGT_PMCEIDN_EL0
,
7408 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7410 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7412 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7413 static const ARMCPRegInfo v84_pmmir
= {
7414 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7415 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7416 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7417 .fgt
= FGT_PMMIR_EL1
,
7420 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7424 #ifndef CONFIG_USER_ONLY
7426 * We don't know until after realize whether there's a GICv3
7427 * attached, and that is what registers the gicv3 sysregs.
7428 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7431 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7433 ARMCPU
*cpu
= env_archcpu(env
);
7434 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7436 if (env
->gicv3state
) {
7442 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7444 ARMCPU
*cpu
= env_archcpu(env
);
7445 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7447 if (env
->gicv3state
) {
7455 * Shared logic between LORID and the rest of the LOR* registers.
7456 * Secure state exclusion has already been dealt with.
7458 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7459 const ARMCPRegInfo
*ri
, bool isread
)
7461 int el
= arm_current_el(env
);
7463 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7464 return CP_ACCESS_TRAP_EL2
;
7466 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7467 return CP_ACCESS_TRAP_EL3
;
7469 return CP_ACCESS_OK
;
7472 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7473 const ARMCPRegInfo
*ri
, bool isread
)
7475 if (arm_is_secure_below_el3(env
)) {
7476 /* Access denied in secure mode. */
7477 return CP_ACCESS_TRAP
;
7479 return access_lor_ns(env
, ri
, isread
);
7483 * A trivial implementation of ARMv8.1-LOR leaves all of these
7484 * registers fixed at 0, which indicates that there are zero
7485 * supported Limited Ordering regions.
7487 static const ARMCPRegInfo lor_reginfo
[] = {
7488 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7489 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7490 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7491 .fgt
= FGT_LORSA_EL1
,
7492 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7493 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7494 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7495 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7496 .fgt
= FGT_LOREA_EL1
,
7497 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7498 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7499 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7500 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7501 .fgt
= FGT_LORN_EL1
,
7502 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7503 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7504 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7505 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7506 .fgt
= FGT_LORC_EL1
,
7507 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7508 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7509 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7510 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7511 .fgt
= FGT_LORID_EL1
,
7512 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7515 #ifdef TARGET_AARCH64
7516 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7519 int el
= arm_current_el(env
);
7522 arm_is_el2_enabled(env
) &&
7523 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7524 return CP_ACCESS_TRAP_EL2
;
7527 arm_feature(env
, ARM_FEATURE_EL3
) &&
7528 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7529 return CP_ACCESS_TRAP_EL3
;
7531 return CP_ACCESS_OK
;
7534 static const ARMCPRegInfo pauth_reginfo
[] = {
7535 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7536 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7537 .access
= PL1_RW
, .accessfn
= access_pauth
,
7539 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7540 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7541 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7542 .access
= PL1_RW
, .accessfn
= access_pauth
,
7544 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7545 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7546 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7547 .access
= PL1_RW
, .accessfn
= access_pauth
,
7549 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7550 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7551 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7552 .access
= PL1_RW
, .accessfn
= access_pauth
,
7554 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7555 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7556 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7557 .access
= PL1_RW
, .accessfn
= access_pauth
,
7559 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7560 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7561 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7562 .access
= PL1_RW
, .accessfn
= access_pauth
,
7564 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7565 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7566 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7567 .access
= PL1_RW
, .accessfn
= access_pauth
,
7569 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7570 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7571 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7572 .access
= PL1_RW
, .accessfn
= access_pauth
,
7574 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7575 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7576 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7577 .access
= PL1_RW
, .accessfn
= access_pauth
,
7579 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7580 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7581 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7582 .access
= PL1_RW
, .accessfn
= access_pauth
,
7584 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7587 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7588 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7589 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7590 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7591 .fgt
= FGT_TLBIRVAE1IS
,
7592 .writefn
= tlbi_aa64_rvae1is_write
},
7593 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7594 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7595 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7596 .fgt
= FGT_TLBIRVAAE1IS
,
7597 .writefn
= tlbi_aa64_rvae1is_write
},
7598 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7599 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7600 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7601 .fgt
= FGT_TLBIRVALE1IS
,
7602 .writefn
= tlbi_aa64_rvae1is_write
},
7603 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7604 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7605 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7606 .fgt
= FGT_TLBIRVAALE1IS
,
7607 .writefn
= tlbi_aa64_rvae1is_write
},
7608 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7609 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7610 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7611 .fgt
= FGT_TLBIRVAE1OS
,
7612 .writefn
= tlbi_aa64_rvae1is_write
},
7613 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7614 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7615 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7616 .fgt
= FGT_TLBIRVAAE1OS
,
7617 .writefn
= tlbi_aa64_rvae1is_write
},
7618 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7619 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7620 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7621 .fgt
= FGT_TLBIRVALE1OS
,
7622 .writefn
= tlbi_aa64_rvae1is_write
},
7623 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7624 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7625 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7626 .fgt
= FGT_TLBIRVAALE1OS
,
7627 .writefn
= tlbi_aa64_rvae1is_write
},
7628 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7629 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7630 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7631 .fgt
= FGT_TLBIRVAE1
,
7632 .writefn
= tlbi_aa64_rvae1_write
},
7633 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7634 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7635 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7636 .fgt
= FGT_TLBIRVAAE1
,
7637 .writefn
= tlbi_aa64_rvae1_write
},
7638 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7639 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7640 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7641 .fgt
= FGT_TLBIRVALE1
,
7642 .writefn
= tlbi_aa64_rvae1_write
},
7643 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7644 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7645 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7646 .fgt
= FGT_TLBIRVAALE1
,
7647 .writefn
= tlbi_aa64_rvae1_write
},
7648 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7649 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7650 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7651 .writefn
= tlbi_aa64_ripas2e1is_write
},
7652 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7653 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7654 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7655 .writefn
= tlbi_aa64_ripas2e1is_write
},
7656 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7657 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7658 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7659 .writefn
= tlbi_aa64_rvae2is_write
},
7660 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7661 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7662 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7663 .writefn
= tlbi_aa64_rvae2is_write
},
7664 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7665 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7666 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7667 .writefn
= tlbi_aa64_ripas2e1_write
},
7668 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7669 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7670 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7671 .writefn
= tlbi_aa64_ripas2e1_write
},
7672 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7673 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7674 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7675 .writefn
= tlbi_aa64_rvae2is_write
},
7676 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7677 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7678 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7679 .writefn
= tlbi_aa64_rvae2is_write
},
7680 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7681 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7682 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7683 .writefn
= tlbi_aa64_rvae2_write
},
7684 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7685 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7686 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7687 .writefn
= tlbi_aa64_rvae2_write
},
7688 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7689 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7690 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7691 .writefn
= tlbi_aa64_rvae3is_write
},
7692 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7693 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7694 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7695 .writefn
= tlbi_aa64_rvae3is_write
},
7696 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7697 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7698 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7699 .writefn
= tlbi_aa64_rvae3is_write
},
7700 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7701 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7702 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7703 .writefn
= tlbi_aa64_rvae3is_write
},
7704 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7705 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7706 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7707 .writefn
= tlbi_aa64_rvae3_write
},
7708 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7709 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7710 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7711 .writefn
= tlbi_aa64_rvae3_write
},
7714 static const ARMCPRegInfo tlbios_reginfo
[] = {
7715 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7716 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7717 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7718 .fgt
= FGT_TLBIVMALLE1OS
,
7719 .writefn
= tlbi_aa64_vmalle1is_write
},
7720 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7721 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7722 .fgt
= FGT_TLBIVAE1OS
,
7723 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7724 .writefn
= tlbi_aa64_vae1is_write
},
7725 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7726 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7727 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7728 .fgt
= FGT_TLBIASIDE1OS
,
7729 .writefn
= tlbi_aa64_vmalle1is_write
},
7730 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7731 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7732 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7733 .fgt
= FGT_TLBIVAAE1OS
,
7734 .writefn
= tlbi_aa64_vae1is_write
},
7735 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7736 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7737 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7738 .fgt
= FGT_TLBIVALE1OS
,
7739 .writefn
= tlbi_aa64_vae1is_write
},
7740 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7741 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7742 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7743 .fgt
= FGT_TLBIVAALE1OS
,
7744 .writefn
= tlbi_aa64_vae1is_write
},
7745 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7746 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7747 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7748 .writefn
= tlbi_aa64_alle2is_write
},
7749 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7750 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7751 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7752 .writefn
= tlbi_aa64_vae2is_write
},
7753 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7754 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7755 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7756 .writefn
= tlbi_aa64_alle1is_write
},
7757 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7758 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7759 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7760 .writefn
= tlbi_aa64_vae2is_write
},
7761 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7762 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7763 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7764 .writefn
= tlbi_aa64_alle1is_write
},
7765 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7766 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7767 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7768 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7769 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7770 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7771 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7772 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7773 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7774 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7775 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7776 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7777 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7778 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7779 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7780 .writefn
= tlbi_aa64_alle3is_write
},
7781 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7782 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7783 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7784 .writefn
= tlbi_aa64_vae3is_write
},
7785 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7786 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7787 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7788 .writefn
= tlbi_aa64_vae3is_write
},
7791 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7796 /* Success sets NZCV = 0000. */
7797 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7799 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7801 * ??? Failed, for unknown reasons in the crypto subsystem.
7802 * The best we can do is log the reason and return the
7803 * timed-out indication to the guest. There is no reason
7804 * we know to expect this failure to be transitory, so the
7805 * guest may well hang retrying the operation.
7807 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7808 ri
->name
, error_get_pretty(err
));
7811 env
->ZF
= 0; /* NZCF = 0100 */
7817 /* We do not support re-seeding, so the two registers operate the same. */
7818 static const ARMCPRegInfo rndr_reginfo
[] = {
7819 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7820 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7821 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7822 .access
= PL0_R
, .readfn
= rndr_readfn
},
7823 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7824 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7825 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7826 .access
= PL0_R
, .readfn
= rndr_readfn
},
7829 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7833 ARMCPU
*cpu
= env_archcpu(env
);
7834 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7835 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7836 uint64_t vaddr_in
= (uint64_t) value
;
7837 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7839 int mem_idx
= cpu_mmu_index(env
, false);
7841 /* This won't be crossing page boundaries */
7842 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7844 #ifndef CONFIG_USER_ONLY
7849 /* RCU lock is already being held */
7850 mr
= memory_region_from_host(haddr
, &offset
);
7853 memory_region_writeback(mr
, offset
, dline_size
);
7855 #endif /*CONFIG_USER_ONLY*/
7858 /* Handled by hardware accelerator. */
7859 g_assert_not_reached();
7860 #endif /* CONFIG_TCG */
7863 static const ARMCPRegInfo dcpop_reg
[] = {
7864 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7865 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7866 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7868 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7871 static const ARMCPRegInfo dcpodp_reg
[] = {
7872 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7873 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7874 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7876 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7879 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7882 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7883 return CP_ACCESS_TRAP_EL2
;
7886 return CP_ACCESS_OK
;
7889 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7892 int el
= arm_current_el(env
);
7893 if (el
< 2 && arm_is_el2_enabled(env
)) {
7894 uint64_t hcr
= arm_hcr_el2_eff(env
);
7895 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7896 return CP_ACCESS_TRAP_EL2
;
7900 arm_feature(env
, ARM_FEATURE_EL3
) &&
7901 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7902 return CP_ACCESS_TRAP_EL3
;
7904 return CP_ACCESS_OK
;
7907 static CPAccessResult
access_tfsr_el1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7910 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
7912 if (nv1
!= CP_ACCESS_OK
) {
7915 return access_mte(env
, ri
, isread
);
7918 static CPAccessResult
access_tfsr_el2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7922 * TFSR_EL2: similar to generic access_mte(), but we need to
7923 * account for FEAT_NV. At EL1 this must be a FEAT_NV access;
7924 * if NV2 is enabled then we will redirect this to TFSR_EL1
7925 * after doing the HCR and SCR ATA traps; otherwise this will
7926 * be a trap to EL2 and the HCR/SCR traps do not apply.
7928 int el
= arm_current_el(env
);
7930 if (el
== 1 && (arm_hcr_el2_eff(env
) & HCR_NV2
)) {
7931 return CP_ACCESS_OK
;
7933 if (el
< 2 && arm_is_el2_enabled(env
)) {
7934 uint64_t hcr
= arm_hcr_el2_eff(env
);
7935 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7936 return CP_ACCESS_TRAP_EL2
;
7940 arm_feature(env
, ARM_FEATURE_EL3
) &&
7941 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7942 return CP_ACCESS_TRAP_EL3
;
7944 return CP_ACCESS_OK
;
7947 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7949 return env
->pstate
& PSTATE_TCO
;
7952 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7954 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7957 static const ARMCPRegInfo mte_reginfo
[] = {
7958 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7959 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7960 .access
= PL1_RW
, .accessfn
= access_mte
,
7961 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7962 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7963 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7964 .access
= PL1_RW
, .accessfn
= access_tfsr_el1
,
7965 .nv2_redirect_offset
= 0x190 | NV2_REDIR_NV1
,
7966 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7967 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7968 .type
= ARM_CP_NV2_REDIRECT
,
7969 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7970 .access
= PL2_RW
, .accessfn
= access_tfsr_el2
,
7971 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7972 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7973 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7975 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7976 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7977 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7978 .access
= PL1_RW
, .accessfn
= access_mte
,
7979 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7980 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7981 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7982 .access
= PL1_RW
, .accessfn
= access_mte
,
7983 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7984 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7985 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7986 .type
= ARM_CP_NO_RAW
,
7987 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7988 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7989 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7990 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7992 .accessfn
= aa64_cacheop_poc_access
},
7993 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7994 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7996 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7997 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7998 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7999 .type
= ARM_CP_NOP
, .access
= PL1_W
,
8001 .accessfn
= aa64_cacheop_poc_access
},
8002 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
8003 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
8005 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8006 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
8007 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
8009 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8010 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
8011 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
8013 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8014 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
8015 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
8017 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8018 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
8019 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
8021 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8024 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
8025 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
8026 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
8027 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
8030 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
8031 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
8032 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
8033 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8035 .accessfn
= aa64_cacheop_poc_access
},
8036 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
8037 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
8038 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8040 .accessfn
= aa64_cacheop_poc_access
},
8041 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
8042 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
8043 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8045 .accessfn
= aa64_cacheop_poc_access
},
8046 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
8047 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
8048 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8050 .accessfn
= aa64_cacheop_poc_access
},
8051 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
8052 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
8053 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8055 .accessfn
= aa64_cacheop_poc_access
},
8056 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
8057 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
8058 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8060 .accessfn
= aa64_cacheop_poc_access
},
8061 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
8062 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
8063 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8065 .accessfn
= aa64_cacheop_poc_access
},
8066 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
8067 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
8068 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8070 .accessfn
= aa64_cacheop_poc_access
},
8071 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
8072 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
8073 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
8074 #ifndef CONFIG_USER_ONLY
8075 /* Avoid overhead of an access check that always passes in user-mode */
8076 .accessfn
= aa64_zva_access
,
8080 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
8081 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
8082 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
8083 #ifndef CONFIG_USER_ONLY
8084 /* Avoid overhead of an access check that always passes in user-mode */
8085 .accessfn
= aa64_zva_access
,
8091 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8094 uint64_t hcr
= arm_hcr_el2_eff(env
);
8095 int el
= arm_current_el(env
);
8097 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
8098 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
8099 if (hcr
& HCR_TGE
) {
8100 return CP_ACCESS_TRAP_EL2
;
8102 return CP_ACCESS_TRAP
;
8104 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
8105 return CP_ACCESS_TRAP_EL2
;
8107 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
8108 return CP_ACCESS_TRAP_EL2
;
8111 && arm_feature(env
, ARM_FEATURE_EL3
)
8112 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
8113 return CP_ACCESS_TRAP_EL3
;
8115 return CP_ACCESS_OK
;
8118 static CPAccessResult
access_scxtnum_el1(CPUARMState
*env
,
8119 const ARMCPRegInfo
*ri
,
8122 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
8124 if (nv1
!= CP_ACCESS_OK
) {
8127 return access_scxtnum(env
, ri
, isread
);
8130 static const ARMCPRegInfo scxtnum_reginfo
[] = {
8131 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
8132 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
8133 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
8134 .fgt
= FGT_SCXTNUM_EL0
,
8135 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
8136 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
8137 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
8138 .access
= PL1_RW
, .accessfn
= access_scxtnum_el1
,
8139 .fgt
= FGT_SCXTNUM_EL1
,
8140 .nv2_redirect_offset
= 0x188 | NV2_REDIR_NV1
,
8141 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
8142 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
8143 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
8144 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
8145 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
8146 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
8147 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
8149 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
8152 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8155 if (arm_current_el(env
) == 2 &&
8156 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
8157 return CP_ACCESS_TRAP_EL3
;
8159 return CP_ACCESS_OK
;
8162 static const ARMCPRegInfo fgt_reginfo
[] = {
8163 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8164 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
8165 .nv2_redirect_offset
= 0x1b8,
8166 .access
= PL2_RW
, .accessfn
= access_fgt
,
8167 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
8168 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8169 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
8170 .nv2_redirect_offset
= 0x1c0,
8171 .access
= PL2_RW
, .accessfn
= access_fgt
,
8172 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
8173 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8174 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
8175 .nv2_redirect_offset
= 0x1d0,
8176 .access
= PL2_RW
, .accessfn
= access_fgt
,
8177 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
8178 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8179 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
8180 .nv2_redirect_offset
= 0x1d8,
8181 .access
= PL2_RW
, .accessfn
= access_fgt
,
8182 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
8183 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
8184 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
8185 .nv2_redirect_offset
= 0x1c8,
8186 .access
= PL2_RW
, .accessfn
= access_fgt
,
8187 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
8190 static void vncr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8194 * Clear the RES0 bottom 12 bits; this means at runtime we can guarantee
8195 * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything
8196 * about the RESS bits at the top -- we choose the "generate an EL2
8197 * translation abort on use" CONSTRAINED UNPREDICTABLE option (i.e. let
8198 * the ptw.c code detect the resulting invalid address).
8200 env
->cp15
.vncr_el2
= value
& ~0xfffULL
;
8203 static const ARMCPRegInfo nv2_reginfo
[] = {
8204 { .name
= "VNCR_EL2", .state
= ARM_CP_STATE_AA64
,
8205 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 2, .opc2
= 0,
8207 .writefn
= vncr_write
,
8208 .nv2_redirect_offset
= 0xb0,
8209 .fieldoffset
= offsetof(CPUARMState
, cp15
.vncr_el2
) },
8212 #endif /* TARGET_AARCH64 */
8214 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8217 int el
= arm_current_el(env
);
8220 uint64_t sctlr
= arm_sctlr(env
, el
);
8221 if (!(sctlr
& SCTLR_EnRCTX
)) {
8222 return CP_ACCESS_TRAP
;
8224 } else if (el
== 1) {
8225 uint64_t hcr
= arm_hcr_el2_eff(env
);
8227 return CP_ACCESS_TRAP_EL2
;
8230 return CP_ACCESS_OK
;
8233 static const ARMCPRegInfo predinv_reginfo
[] = {
8234 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
8235 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
8237 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8238 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
8239 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
8241 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8242 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
8243 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
8245 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8247 * Note the AArch32 opcodes have a different OPC1.
8249 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
8250 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
8252 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8253 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
8254 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
8256 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8257 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
8258 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
8260 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8263 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8265 /* Read the high 32 bits of the current CCSIDR */
8266 return extract64(ccsidr_read(env
, ri
), 32, 32);
8269 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
8270 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
8271 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
8273 .accessfn
= access_tid4
,
8274 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8277 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8280 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8281 return CP_ACCESS_TRAP_EL2
;
8284 return CP_ACCESS_OK
;
8287 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8290 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8291 return access_aa64_tid3(env
, ri
, isread
);
8294 return CP_ACCESS_OK
;
8297 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8300 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8301 return CP_ACCESS_TRAP_EL2
;
8304 return CP_ACCESS_OK
;
8307 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8308 const ARMCPRegInfo
*ri
, bool isread
)
8311 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8312 * in v7A, not in v8A.
8314 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8315 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8316 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8317 return CP_ACCESS_TRAP_EL2
;
8319 return CP_ACCESS_OK
;
8322 static const ARMCPRegInfo jazelle_regs
[] = {
8324 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8325 .access
= PL1_R
, .accessfn
= access_jazelle
,
8326 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8328 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8329 .accessfn
= access_joscr_jmcr
,
8330 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8332 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8333 .accessfn
= access_joscr_jmcr
,
8334 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8337 static const ARMCPRegInfo contextidr_el2
= {
8338 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8339 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8341 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8344 static const ARMCPRegInfo vhe_reginfo
[] = {
8345 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8346 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8347 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8348 .raw_writefn
= raw_write
,
8349 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8350 #ifndef CONFIG_USER_ONLY
8351 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8352 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8354 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8355 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8356 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8357 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8358 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8359 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8360 .resetfn
= gt_hv_timer_reset
,
8361 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8362 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8364 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8366 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8367 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8368 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8369 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8370 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8371 .access
= PL2_RW
, .accessfn
= e2h_access
,
8372 .nv2_redirect_offset
= 0x180 | NV2_REDIR_NO_NV1
,
8373 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8374 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8375 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8376 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8377 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8378 .access
= PL2_RW
, .accessfn
= e2h_access
,
8379 .nv2_redirect_offset
= 0x170 | NV2_REDIR_NO_NV1
,
8380 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8381 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8382 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8383 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8384 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8385 .access
= PL2_RW
, .accessfn
= e2h_access
,
8386 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8387 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8388 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8389 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8390 .access
= PL2_RW
, .accessfn
= e2h_access
,
8391 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8392 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8393 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8394 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8395 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8396 .nv2_redirect_offset
= 0x178 | NV2_REDIR_NO_NV1
,
8397 .access
= PL2_RW
, .accessfn
= e2h_access
,
8398 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8399 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8400 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8401 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8402 .nv2_redirect_offset
= 0x168 | NV2_REDIR_NO_NV1
,
8403 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8404 .access
= PL2_RW
, .accessfn
= e2h_access
,
8405 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8409 #ifndef CONFIG_USER_ONLY
8410 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8411 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8412 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8413 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8414 .fgt
= FGT_ATS1E1RP
,
8415 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8416 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8417 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8418 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8419 .fgt
= FGT_ATS1E1WP
,
8420 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8423 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8424 { .name
= "ATS1CPRP",
8425 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8426 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8427 .writefn
= ats_write
},
8428 { .name
= "ATS1CPWP",
8429 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8430 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8431 .writefn
= ats_write
},
8436 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8437 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8438 * is non-zero, which is never for ARMv7, optionally in ARMv8
8439 * and mandatorily for ARMv8.2 and up.
8440 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8441 * implementation is RAZ/WI we can ignore this detail, as we
8444 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8445 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8446 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8447 .access
= PL1_RW
, .accessfn
= access_tacr
,
8448 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8449 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8450 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8451 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8455 void register_cp_regs_for_features(ARMCPU
*cpu
)
8457 /* Register all the coprocessor registers based on feature bits */
8458 CPUARMState
*env
= &cpu
->env
;
8459 if (arm_feature(env
, ARM_FEATURE_M
)) {
8460 /* M profile has no coprocessor registers */
8464 define_arm_cp_regs(cpu
, cp_reginfo
);
8465 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8467 * Must go early as it is full of wildcards that may be
8468 * overridden by later definitions.
8470 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8473 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8474 /* The ID registers all have impdef reset values */
8475 ARMCPRegInfo v6_idregs
[] = {
8476 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8477 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8478 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8479 .accessfn
= access_aa32_tid3
,
8480 .resetvalue
= cpu
->isar
.id_pfr0
},
8482 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8483 * the value of the GIC field until after we define these regs.
8485 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8486 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8487 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8488 .accessfn
= access_aa32_tid3
,
8489 #ifdef CONFIG_USER_ONLY
8490 .type
= ARM_CP_CONST
,
8491 .resetvalue
= cpu
->isar
.id_pfr1
,
8493 .type
= ARM_CP_NO_RAW
,
8494 .accessfn
= access_aa32_tid3
,
8495 .readfn
= id_pfr1_read
,
8496 .writefn
= arm_cp_write_ignore
8499 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8500 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8501 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8502 .accessfn
= access_aa32_tid3
,
8503 .resetvalue
= cpu
->isar
.id_dfr0
},
8504 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8505 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8506 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8507 .accessfn
= access_aa32_tid3
,
8508 .resetvalue
= cpu
->id_afr0
},
8509 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8510 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8511 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8512 .accessfn
= access_aa32_tid3
,
8513 .resetvalue
= cpu
->isar
.id_mmfr0
},
8514 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8515 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8516 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8517 .accessfn
= access_aa32_tid3
,
8518 .resetvalue
= cpu
->isar
.id_mmfr1
},
8519 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8520 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8521 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8522 .accessfn
= access_aa32_tid3
,
8523 .resetvalue
= cpu
->isar
.id_mmfr2
},
8524 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8525 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8526 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8527 .accessfn
= access_aa32_tid3
,
8528 .resetvalue
= cpu
->isar
.id_mmfr3
},
8529 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8530 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8531 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8532 .accessfn
= access_aa32_tid3
,
8533 .resetvalue
= cpu
->isar
.id_isar0
},
8534 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8535 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8536 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8537 .accessfn
= access_aa32_tid3
,
8538 .resetvalue
= cpu
->isar
.id_isar1
},
8539 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8540 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8541 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8542 .accessfn
= access_aa32_tid3
,
8543 .resetvalue
= cpu
->isar
.id_isar2
},
8544 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8545 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8546 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8547 .accessfn
= access_aa32_tid3
,
8548 .resetvalue
= cpu
->isar
.id_isar3
},
8549 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8550 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8551 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8552 .accessfn
= access_aa32_tid3
,
8553 .resetvalue
= cpu
->isar
.id_isar4
},
8554 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8555 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8556 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8557 .accessfn
= access_aa32_tid3
,
8558 .resetvalue
= cpu
->isar
.id_isar5
},
8559 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8560 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8561 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8562 .accessfn
= access_aa32_tid3
,
8563 .resetvalue
= cpu
->isar
.id_mmfr4
},
8564 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8565 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8566 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8567 .accessfn
= access_aa32_tid3
,
8568 .resetvalue
= cpu
->isar
.id_isar6
},
8570 define_arm_cp_regs(cpu
, v6_idregs
);
8571 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8573 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8575 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8576 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8578 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8579 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8580 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8582 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8583 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8585 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8586 ARMCPRegInfo clidr
= {
8587 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8588 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8589 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8590 .accessfn
= access_tid4
,
8591 .fgt
= FGT_CLIDR_EL1
,
8592 .resetvalue
= cpu
->clidr
8594 define_one_arm_cp_reg(cpu
, &clidr
);
8595 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8596 define_debug_regs(cpu
);
8597 define_pmu_regs(cpu
);
8599 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8601 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8603 * v8 ID registers, which all have impdef reset values.
8604 * Note that within the ID register ranges the unused slots
8605 * must all RAZ, not UNDEF; future architecture versions may
8606 * define new registers here.
8607 * ID registers which are AArch64 views of the AArch32 ID registers
8608 * which already existed in v6 and v7 are handled elsewhere,
8612 ARMCPRegInfo v8_idregs
[] = {
8614 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8615 * emulation because we don't know the right value for the
8616 * GIC field until after we define these regs.
8618 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8619 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8621 #ifdef CONFIG_USER_ONLY
8622 .type
= ARM_CP_CONST
,
8623 .resetvalue
= cpu
->isar
.id_aa64pfr0
8625 .type
= ARM_CP_NO_RAW
,
8626 .accessfn
= access_aa64_tid3
,
8627 .readfn
= id_aa64pfr0_read
,
8628 .writefn
= arm_cp_write_ignore
8631 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8632 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8633 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8634 .accessfn
= access_aa64_tid3
,
8635 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8636 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8637 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8638 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8639 .accessfn
= access_aa64_tid3
,
8641 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8642 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8643 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8644 .accessfn
= access_aa64_tid3
,
8646 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8647 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8648 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8649 .accessfn
= access_aa64_tid3
,
8650 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8651 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8652 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8653 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8654 .accessfn
= access_aa64_tid3
,
8655 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8656 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8657 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8658 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8659 .accessfn
= access_aa64_tid3
,
8661 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8662 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8663 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8664 .accessfn
= access_aa64_tid3
,
8666 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8667 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8668 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8669 .accessfn
= access_aa64_tid3
,
8670 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8671 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8672 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8673 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8674 .accessfn
= access_aa64_tid3
,
8675 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8676 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8677 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8678 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8679 .accessfn
= access_aa64_tid3
,
8681 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8682 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8683 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8684 .accessfn
= access_aa64_tid3
,
8686 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8687 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8688 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8689 .accessfn
= access_aa64_tid3
,
8690 .resetvalue
= cpu
->id_aa64afr0
},
8691 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8692 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8693 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8694 .accessfn
= access_aa64_tid3
,
8695 .resetvalue
= cpu
->id_aa64afr1
},
8696 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8697 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8698 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8699 .accessfn
= access_aa64_tid3
,
8701 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8702 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8703 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8704 .accessfn
= access_aa64_tid3
,
8706 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8707 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8708 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8709 .accessfn
= access_aa64_tid3
,
8710 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8711 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8712 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8713 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8714 .accessfn
= access_aa64_tid3
,
8715 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8716 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8717 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8718 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8719 .accessfn
= access_aa64_tid3
,
8720 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8721 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8722 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8723 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8724 .accessfn
= access_aa64_tid3
,
8726 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8727 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8728 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8729 .accessfn
= access_aa64_tid3
,
8731 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8732 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8733 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8734 .accessfn
= access_aa64_tid3
,
8736 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8737 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8738 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8739 .accessfn
= access_aa64_tid3
,
8741 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8742 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8743 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8744 .accessfn
= access_aa64_tid3
,
8746 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8747 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8748 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8749 .accessfn
= access_aa64_tid3
,
8750 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8751 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8752 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8753 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8754 .accessfn
= access_aa64_tid3
,
8755 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8756 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8757 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8758 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8759 .accessfn
= access_aa64_tid3
,
8760 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8761 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8762 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8763 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8764 .accessfn
= access_aa64_tid3
,
8766 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8767 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8768 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8769 .accessfn
= access_aa64_tid3
,
8771 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8772 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8773 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8774 .accessfn
= access_aa64_tid3
,
8776 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8777 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8778 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8779 .accessfn
= access_aa64_tid3
,
8781 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8782 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8783 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8784 .accessfn
= access_aa64_tid3
,
8786 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8787 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8788 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8789 .accessfn
= access_aa64_tid3
,
8790 .resetvalue
= cpu
->isar
.mvfr0
},
8791 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8792 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8793 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8794 .accessfn
= access_aa64_tid3
,
8795 .resetvalue
= cpu
->isar
.mvfr1
},
8796 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8797 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8798 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8799 .accessfn
= access_aa64_tid3
,
8800 .resetvalue
= cpu
->isar
.mvfr2
},
8802 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8803 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8804 * as RAZ, since it is in the "reserved for future ID
8805 * registers, RAZ" part of the AArch32 encoding space.
8807 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8808 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8809 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8810 .accessfn
= access_aa64_tid3
,
8812 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8813 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8814 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8815 .accessfn
= access_aa64_tid3
,
8817 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8818 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8819 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8820 .accessfn
= access_aa64_tid3
,
8823 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8824 * they're also RAZ for AArch64, and in v8 are gradually
8825 * being filled with AArch64-view-of-AArch32-ID-register
8826 * for new ID registers.
8828 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8829 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8830 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8831 .accessfn
= access_aa64_tid3
,
8833 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8834 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8835 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8836 .accessfn
= access_aa64_tid3
,
8837 .resetvalue
= cpu
->isar
.id_pfr2
},
8838 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8839 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8840 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8841 .accessfn
= access_aa64_tid3
,
8842 .resetvalue
= cpu
->isar
.id_dfr1
},
8843 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8844 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8845 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8846 .accessfn
= access_aa64_tid3
,
8847 .resetvalue
= cpu
->isar
.id_mmfr5
},
8848 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8849 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8850 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8851 .accessfn
= access_aa64_tid3
,
8853 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8854 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8855 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8856 .fgt
= FGT_PMCEIDN_EL0
,
8857 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8858 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8859 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8860 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8861 .fgt
= FGT_PMCEIDN_EL0
,
8862 .resetvalue
= cpu
->pmceid0
},
8863 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8864 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8865 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8866 .fgt
= FGT_PMCEIDN_EL0
,
8867 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8868 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8869 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8870 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8871 .fgt
= FGT_PMCEIDN_EL0
,
8872 .resetvalue
= cpu
->pmceid1
},
8874 #ifdef CONFIG_USER_ONLY
8875 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8876 { .name
= "ID_AA64PFR0_EL1",
8877 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8878 R_ID_AA64PFR0_ADVSIMD_MASK
|
8879 R_ID_AA64PFR0_SVE_MASK
|
8880 R_ID_AA64PFR0_DIT_MASK
,
8881 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8882 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8883 { .name
= "ID_AA64PFR1_EL1",
8884 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8885 R_ID_AA64PFR1_SSBS_MASK
|
8886 R_ID_AA64PFR1_MTE_MASK
|
8887 R_ID_AA64PFR1_SME_MASK
},
8888 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8890 { .name
= "ID_AA64ZFR0_EL1",
8891 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8892 R_ID_AA64ZFR0_AES_MASK
|
8893 R_ID_AA64ZFR0_BITPERM_MASK
|
8894 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8895 R_ID_AA64ZFR0_SHA3_MASK
|
8896 R_ID_AA64ZFR0_SM4_MASK
|
8897 R_ID_AA64ZFR0_I8MM_MASK
|
8898 R_ID_AA64ZFR0_F32MM_MASK
|
8899 R_ID_AA64ZFR0_F64MM_MASK
},
8900 { .name
= "ID_AA64SMFR0_EL1",
8901 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8902 R_ID_AA64SMFR0_BI32I32_MASK
|
8903 R_ID_AA64SMFR0_B16F32_MASK
|
8904 R_ID_AA64SMFR0_F16F32_MASK
|
8905 R_ID_AA64SMFR0_I8I32_MASK
|
8906 R_ID_AA64SMFR0_F16F16_MASK
|
8907 R_ID_AA64SMFR0_B16B16_MASK
|
8908 R_ID_AA64SMFR0_I16I32_MASK
|
8909 R_ID_AA64SMFR0_F64F64_MASK
|
8910 R_ID_AA64SMFR0_I16I64_MASK
|
8911 R_ID_AA64SMFR0_SMEVER_MASK
|
8912 R_ID_AA64SMFR0_FA64_MASK
},
8913 { .name
= "ID_AA64MMFR0_EL1",
8914 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8915 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8916 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8917 { .name
= "ID_AA64MMFR1_EL1",
8918 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8919 { .name
= "ID_AA64MMFR2_EL1",
8920 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8921 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8923 { .name
= "ID_AA64DFR0_EL1",
8924 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8925 { .name
= "ID_AA64DFR1_EL1" },
8926 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8928 { .name
= "ID_AA64AFR*",
8930 { .name
= "ID_AA64ISAR0_EL1",
8931 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8932 R_ID_AA64ISAR0_SHA1_MASK
|
8933 R_ID_AA64ISAR0_SHA2_MASK
|
8934 R_ID_AA64ISAR0_CRC32_MASK
|
8935 R_ID_AA64ISAR0_ATOMIC_MASK
|
8936 R_ID_AA64ISAR0_RDM_MASK
|
8937 R_ID_AA64ISAR0_SHA3_MASK
|
8938 R_ID_AA64ISAR0_SM3_MASK
|
8939 R_ID_AA64ISAR0_SM4_MASK
|
8940 R_ID_AA64ISAR0_DP_MASK
|
8941 R_ID_AA64ISAR0_FHM_MASK
|
8942 R_ID_AA64ISAR0_TS_MASK
|
8943 R_ID_AA64ISAR0_RNDR_MASK
},
8944 { .name
= "ID_AA64ISAR1_EL1",
8945 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8946 R_ID_AA64ISAR1_APA_MASK
|
8947 R_ID_AA64ISAR1_API_MASK
|
8948 R_ID_AA64ISAR1_JSCVT_MASK
|
8949 R_ID_AA64ISAR1_FCMA_MASK
|
8950 R_ID_AA64ISAR1_LRCPC_MASK
|
8951 R_ID_AA64ISAR1_GPA_MASK
|
8952 R_ID_AA64ISAR1_GPI_MASK
|
8953 R_ID_AA64ISAR1_FRINTTS_MASK
|
8954 R_ID_AA64ISAR1_SB_MASK
|
8955 R_ID_AA64ISAR1_BF16_MASK
|
8956 R_ID_AA64ISAR1_DGH_MASK
|
8957 R_ID_AA64ISAR1_I8MM_MASK
},
8958 { .name
= "ID_AA64ISAR2_EL1",
8959 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8960 R_ID_AA64ISAR2_RPRES_MASK
|
8961 R_ID_AA64ISAR2_GPA3_MASK
|
8962 R_ID_AA64ISAR2_APA3_MASK
|
8963 R_ID_AA64ISAR2_MOPS_MASK
|
8964 R_ID_AA64ISAR2_BC_MASK
|
8965 R_ID_AA64ISAR2_RPRFM_MASK
|
8966 R_ID_AA64ISAR2_CSSC_MASK
},
8967 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8970 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8973 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8974 * TODO: For RMR, a write with bit 1 set should do something with
8975 * cpu_reset(). In the meantime, "the bit is strictly a request",
8976 * so we are in spec just ignoring writes.
8978 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8979 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8980 ARMCPRegInfo el1_reset_regs
[] = {
8981 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8982 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8984 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8985 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8986 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8987 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8988 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8990 define_arm_cp_regs(cpu
, el1_reset_regs
);
8992 define_arm_cp_regs(cpu
, v8_idregs
);
8993 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8994 if (cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
8995 define_arm_cp_regs(cpu
, v8_aa32_el1_reginfo
);
8998 for (i
= 4; i
< 16; i
++) {
9000 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
9001 * For pre-v8 cores there are RAZ patterns for these in
9002 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
9003 * v8 extends the "must RAZ" part of the ID register space
9004 * to also cover c0, 0, c{8-15}, {0-7}.
9005 * These are STATE_AA32 because in the AArch64 sysreg space
9006 * c4-c7 is where the AArch64 ID registers live (and we've
9007 * already defined those in v8_idregs[]), and c8-c15 are not
9008 * "must RAZ" for AArch64.
9010 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
9011 ARMCPRegInfo v8_aa32_raz_idregs
= {
9013 .state
= ARM_CP_STATE_AA32
,
9014 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
9015 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9016 .accessfn
= access_aa64_tid3
,
9018 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
9023 * Register the base EL2 cpregs.
9024 * Pre v8, these registers are implemented only as part of the
9025 * Virtualization Extensions (EL2 present). Beginning with v8,
9026 * if EL2 is missing but EL3 is enabled, mostly these become
9027 * RES0 from EL3, with some specific exceptions.
9029 if (arm_feature(env
, ARM_FEATURE_EL2
)
9030 || (arm_feature(env
, ARM_FEATURE_EL3
)
9031 && arm_feature(env
, ARM_FEATURE_V8
))) {
9032 uint64_t vmpidr_def
= mpidr_read_val(env
);
9033 ARMCPRegInfo vpidr_regs
[] = {
9034 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
9035 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
9036 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
9037 .resetvalue
= cpu
->midr
,
9038 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
9039 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
9040 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
9041 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
9042 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
9043 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
9044 .nv2_redirect_offset
= 0x88,
9045 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
9046 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
9047 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
9048 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
9049 .resetvalue
= vmpidr_def
,
9050 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
9051 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
9052 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
9053 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
9054 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
9055 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
9056 .nv2_redirect_offset
= 0x50,
9057 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
9060 * The only field of MDCR_EL2 that has a defined architectural reset
9061 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
9063 ARMCPRegInfo mdcr_el2
= {
9064 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
9065 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
9066 .writefn
= mdcr_el2_write
,
9067 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
9068 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
9070 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
9071 define_arm_cp_regs(cpu
, vpidr_regs
);
9072 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
9073 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9074 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
9076 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
9077 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
9080 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
9081 * See commentary near RMR_EL1.
9083 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
9084 static const ARMCPRegInfo el2_reset_regs
[] = {
9085 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
9086 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
9088 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9089 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
9090 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
9092 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9093 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
9094 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
9095 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9097 define_arm_cp_regs(cpu
, el2_reset_regs
);
9101 /* Register the base EL3 cpregs. */
9102 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9103 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
9104 ARMCPRegInfo el3_regs
[] = {
9105 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
9106 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
9108 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
9109 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
9110 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
9111 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9112 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
9113 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
9114 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9115 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
9116 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9117 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
9119 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
9120 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
9121 .resetvalue
= cpu
->reset_sctlr
},
9124 define_arm_cp_regs(cpu
, el3_regs
);
9127 * The behaviour of NSACR is sufficiently various that we don't
9128 * try to describe it in a single reginfo:
9129 * if EL3 is 64 bit, then trap to EL3 from S EL1,
9130 * reads as constant 0xc00 from NS EL1 and NS EL2
9131 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
9132 * if v7 without EL3, register doesn't exist
9133 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
9135 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9136 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9137 static const ARMCPRegInfo nsacr
= {
9138 .name
= "NSACR", .type
= ARM_CP_CONST
,
9139 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9140 .access
= PL1_RW
, .accessfn
= nsacr_access
,
9143 define_one_arm_cp_reg(cpu
, &nsacr
);
9145 static const ARMCPRegInfo nsacr
= {
9147 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9148 .access
= PL3_RW
| PL1_R
,
9150 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
9152 define_one_arm_cp_reg(cpu
, &nsacr
);
9155 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9156 static const ARMCPRegInfo nsacr
= {
9157 .name
= "NSACR", .type
= ARM_CP_CONST
,
9158 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9162 define_one_arm_cp_reg(cpu
, &nsacr
);
9166 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9167 if (arm_feature(env
, ARM_FEATURE_V6
)) {
9168 /* PMSAv6 not implemented */
9169 assert(arm_feature(env
, ARM_FEATURE_V7
));
9170 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9171 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
9173 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
9176 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9177 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
9178 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
9179 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
9180 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
9183 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
9184 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
9186 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
9187 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
9189 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
9190 ARMCPRegInfo vapa_cp_reginfo
[] = {
9191 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
9192 .access
= PL1_RW
, .resetvalue
= 0,
9193 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
9194 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
9195 .writefn
= par_write
},
9196 #ifndef CONFIG_USER_ONLY
9197 /* This underdecoding is safe because the reginfo is NO_RAW. */
9198 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
9199 .access
= PL1_W
, .accessfn
= ats_access
,
9200 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
9205 * When LPAE exists this 32-bit PAR register is an alias of the
9206 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
9208 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9209 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9211 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
9213 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
9214 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
9216 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
9217 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
9219 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
9220 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
9222 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
9223 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
9225 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9226 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
9228 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9229 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
9231 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
9232 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
9234 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9235 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
9237 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
9238 define_arm_cp_regs(cpu
, jazelle_regs
);
9241 * Slightly awkwardly, the OMAP and StrongARM cores need all of
9242 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
9243 * be read-only (ie write causes UNDEF exception).
9246 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
9248 * Pre-v8 MIDR space.
9249 * Note that the MIDR isn't a simple constant register because
9250 * of the TI925 behaviour where writes to another register can
9251 * cause the MIDR value to change.
9253 * Unimplemented registers in the c15 0 0 0 space default to
9254 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
9255 * and friends override accordingly.
9258 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
9259 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
9260 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
9261 .readfn
= midr_read
,
9262 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9263 .type
= ARM_CP_OVERRIDE
},
9264 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
9266 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
9267 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9269 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
9270 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9272 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
9273 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9275 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
9276 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9278 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
9279 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9281 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
9282 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9283 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
9284 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
9285 .fgt
= FGT_MIDR_EL1
,
9286 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9287 .readfn
= midr_read
},
9288 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
9289 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
9290 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
9291 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
9292 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9293 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
9295 .accessfn
= access_aa64_tid1
,
9296 .fgt
= FGT_REVIDR_EL1
,
9297 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9299 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9300 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9301 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9302 .access
= PL1_R
, .resetvalue
= cpu
->midr
9304 ARMCPRegInfo id_cp_reginfo
[] = {
9305 /* These are common to v8 and pre-v8 */
9307 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9308 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9309 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9310 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9311 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9312 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9314 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9315 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9317 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9319 .accessfn
= access_aa32_tid1
,
9320 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9322 /* TLBTR is specific to VMSA */
9323 ARMCPRegInfo id_tlbtr_reginfo
= {
9325 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9327 .accessfn
= access_aa32_tid1
,
9328 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9330 /* MPUIR is specific to PMSA V6+ */
9331 ARMCPRegInfo id_mpuir_reginfo
= {
9333 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9334 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9335 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9337 /* HMPUIR is specific to PMSA V8 */
9338 ARMCPRegInfo id_hmpuir_reginfo
= {
9340 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9341 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9342 .resetvalue
= cpu
->pmsav8r_hdregion
9344 static const ARMCPRegInfo crn0_wi_reginfo
= {
9345 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9346 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9347 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9349 #ifdef CONFIG_USER_ONLY
9350 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9351 { .name
= "MIDR_EL1",
9352 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9353 R_MIDR_EL1_PARTNUM_MASK
|
9354 R_MIDR_EL1_ARCHITECTURE_MASK
|
9355 R_MIDR_EL1_VARIANT_MASK
|
9356 R_MIDR_EL1_IMPLEMENTER_MASK
},
9357 { .name
= "REVIDR_EL1" },
9359 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9361 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9362 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9365 * Register the blanket "writes ignored" value first to cover the
9366 * whole space. Then update the specific ID registers to allow write
9367 * access, so that they ignore writes rather than causing them to
9370 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9371 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9372 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9374 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9375 id_cp_reginfo
[i
].access
= PL1_RW
;
9377 id_mpuir_reginfo
.access
= PL1_RW
;
9378 id_tlbtr_reginfo
.access
= PL1_RW
;
9380 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9381 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9382 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9383 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9386 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9388 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9389 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9390 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9391 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9392 arm_feature(env
, ARM_FEATURE_V8
)) {
9396 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9397 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9398 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9400 /* Register alias is only valid for first 32 indexes */
9401 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9402 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9403 uint8_t opc1
= extract32(i
, 4, 1);
9404 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9406 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9407 ARMCPRegInfo tmp_prbarn_reginfo
= {
9408 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9409 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9410 .access
= PL1_RW
, .resetvalue
= 0,
9411 .accessfn
= access_tvm_trvm
,
9412 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9414 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9417 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9418 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9419 ARMCPRegInfo tmp_prlarn_reginfo
= {
9420 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9421 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9422 .access
= PL1_RW
, .resetvalue
= 0,
9423 .accessfn
= access_tvm_trvm
,
9424 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9426 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9430 /* Register alias is only valid for first 32 indexes */
9431 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9432 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9433 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9434 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9436 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9437 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9439 .type
= ARM_CP_NO_RAW
,
9440 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9441 .access
= PL2_RW
, .resetvalue
= 0,
9442 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9444 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9447 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9448 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9449 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9451 .type
= ARM_CP_NO_RAW
,
9452 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9453 .access
= PL2_RW
, .resetvalue
= 0,
9454 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9456 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9459 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9460 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9464 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9465 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9466 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9467 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9468 .fgt
= FGT_MPIDR_EL1
,
9469 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9471 #ifdef CONFIG_USER_ONLY
9472 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9473 { .name
= "MPIDR_EL1",
9474 .fixed_bits
= 0x0000000080000000 },
9476 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9478 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9481 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9482 ARMCPRegInfo auxcr_reginfo
[] = {
9483 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9484 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9485 .access
= PL1_RW
, .accessfn
= access_tacr
,
9486 .nv2_redirect_offset
= 0x118,
9487 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9488 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9489 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9490 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9492 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9493 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9494 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9497 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9498 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9499 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9503 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9505 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9506 * There are two flavours:
9507 * (1) older 32-bit only cores have a simple 32-bit CBAR
9508 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9509 * 32-bit register visible to AArch32 at a different encoding
9510 * to the "flavour 1" register and with the bits rearranged to
9511 * be able to squash a 64-bit address into the 32-bit view.
9512 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9513 * in future if we support AArch32-only configs of some of the
9514 * AArch64 cores we might need to add a specific feature flag
9515 * to indicate cores with "flavour 2" CBAR.
9517 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9518 /* 32 bit view is [31:18] 0...0 [43:32]. */
9519 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9520 | extract64(cpu
->reset_cbar
, 32, 12);
9521 ARMCPRegInfo cbar_reginfo
[] = {
9523 .type
= ARM_CP_CONST
,
9524 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9525 .access
= PL1_R
, .resetvalue
= cbar32
},
9526 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9527 .type
= ARM_CP_CONST
,
9528 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9529 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9531 /* We don't implement a r/w 64 bit CBAR currently */
9532 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9533 define_arm_cp_regs(cpu
, cbar_reginfo
);
9535 ARMCPRegInfo cbar
= {
9537 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9538 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9539 .fieldoffset
= offsetof(CPUARMState
,
9540 cp15
.c15_config_base_address
)
9542 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9543 cbar
.access
= PL1_R
;
9544 cbar
.fieldoffset
= 0;
9545 cbar
.type
= ARM_CP_CONST
;
9547 define_one_arm_cp_reg(cpu
, &cbar
);
9551 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9552 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9553 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9554 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9555 .access
= PL1_RW
, .writefn
= vbar_write
,
9556 .accessfn
= access_nv1
,
9557 .fgt
= FGT_VBAR_EL1
,
9558 .nv2_redirect_offset
= 0x250 | NV2_REDIR_NV1
,
9559 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9560 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9563 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9566 /* Generic registers whose values depend on the implementation */
9568 ARMCPRegInfo sctlr
= {
9569 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9570 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9571 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9572 .fgt
= FGT_SCTLR_EL1
,
9573 .nv2_redirect_offset
= 0x110 | NV2_REDIR_NV1
,
9574 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9575 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9576 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9577 .raw_writefn
= raw_write
,
9579 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9581 * Normally we would always end the TB on an SCTLR write, but Linux
9582 * arch/arm/mach-pxa/sleep.S expects two instructions following
9583 * an MMU enable to execute from cache. Imitate this behaviour.
9585 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9587 define_one_arm_cp_reg(cpu
, &sctlr
);
9589 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9590 arm_feature(env
, ARM_FEATURE_V8
)) {
9591 ARMCPRegInfo vsctlr
= {
9592 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9593 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9594 .access
= PL2_RW
, .resetvalue
= 0x0,
9595 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9597 define_one_arm_cp_reg(cpu
, &vsctlr
);
9601 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9602 define_arm_cp_regs(cpu
, lor_reginfo
);
9604 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9605 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9607 #ifndef CONFIG_USER_ONLY
9608 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9609 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9611 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9612 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9615 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9616 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9619 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9620 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9622 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9623 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9625 if (cpu_isar_feature(any_ras
, cpu
)) {
9626 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9629 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9630 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9631 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9633 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9634 define_arm_cp_regs(cpu
, vhe_reginfo
);
9637 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9638 define_arm_cp_regs(cpu
, zcr_reginfo
);
9641 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9642 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9645 #ifdef TARGET_AARCH64
9646 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9647 define_arm_cp_regs(cpu
, sme_reginfo
);
9649 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9650 define_arm_cp_regs(cpu
, pauth_reginfo
);
9652 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9653 define_arm_cp_regs(cpu
, rndr_reginfo
);
9655 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9656 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9658 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9659 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9661 /* Data Cache clean instructions up to PoP */
9662 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9663 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9665 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9666 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9671 * If full MTE is enabled, add all of the system registers.
9672 * If only "instructions available at EL0" are enabled,
9673 * then define only a RAZ/WI version of PSTATE.TCO.
9675 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9676 ARMCPRegInfo gmid_reginfo
= {
9677 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9678 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9679 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9680 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9682 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9683 define_arm_cp_regs(cpu
, mte_reginfo
);
9684 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9685 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9686 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9687 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9690 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9691 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9694 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9695 define_arm_cp_regs(cpu
, fgt_reginfo
);
9698 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9699 define_arm_cp_regs(cpu
, rme_reginfo
);
9700 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9701 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9705 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
9706 define_arm_cp_regs(cpu
, nv2_reginfo
);
9710 if (cpu_isar_feature(any_predinv
, cpu
)) {
9711 define_arm_cp_regs(cpu
, predinv_reginfo
);
9714 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9715 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9718 #ifndef CONFIG_USER_ONLY
9720 * Register redirections and aliases must be done last,
9721 * after the registers from the other extensions have been defined.
9723 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9724 define_arm_vh_e2h_redirects_aliases(cpu
);
9730 * Private utility function for define_one_arm_cp_reg_with_opaque():
9731 * add a single reginfo struct to the hash table.
9733 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9734 void *opaque
, CPState state
,
9735 CPSecureState secstate
,
9736 int crm
, int opc1
, int opc2
,
9739 CPUARMState
*env
= &cpu
->env
;
9742 bool is64
= r
->type
& ARM_CP_64BIT
;
9743 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9749 case ARM_CP_STATE_AA32
:
9750 /* We assume it is a cp15 register if the .cp field is left unset. */
9751 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9754 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9756 case ARM_CP_STATE_AA64
:
9758 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9759 * cp == 0 as equivalent to the value for "standard guest-visible
9760 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9761 * in their AArch64 view (the .cp value may be non-zero for the
9762 * benefit of the AArch32 view).
9764 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9765 cp
= CP_REG_ARM64_SYSREG_CP
;
9767 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9770 g_assert_not_reached();
9773 /* Overriding of an existing definition must be explicitly requested. */
9774 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9775 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9777 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9782 * Eliminate registers that are not present because the EL is missing.
9783 * Doing this here makes it easier to put all registers for a given
9784 * feature into the same ARMCPRegInfo array and define them all at once.
9787 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9789 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9790 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9792 int min_el
= ctz32(r
->access
) / 2;
9793 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9794 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9797 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9800 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9802 if ((r
->access
& max_el
) == 0) {
9807 /* Combine cpreg and name into one allocation. */
9808 name_len
= strlen(name
) + 1;
9809 r2
= g_malloc(sizeof(*r2
) + name_len
);
9811 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9814 * Update fields to match the instantiation, overwiting wildcards
9815 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9822 r2
->secure
= secstate
;
9824 r2
->opaque
= opaque
;
9828 /* This should not have been a very special register to begin. */
9829 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9830 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9832 * Set the special function to CONST, retaining the other flags.
9833 * This is important for e.g. ARM_CP_SVE so that we still
9834 * take the SVE trap if CPTR_EL3.EZ == 0.
9836 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9838 * Usually, these registers become RES0, but there are a few
9839 * special cases like VPIDR_EL2 which have a constant non-zero
9840 * value with writes ignored.
9842 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9846 * ARM_CP_CONST has precedence, so removing the callbacks and
9847 * offsets are not strictly necessary, but it is potentially
9848 * less confusing to debug later.
9852 r2
->raw_readfn
= NULL
;
9853 r2
->raw_writefn
= NULL
;
9855 r2
->fieldoffset
= 0;
9856 r2
->bank_fieldoffsets
[0] = 0;
9857 r2
->bank_fieldoffsets
[1] = 0;
9859 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9863 * Register is banked (using both entries in array).
9864 * Overwriting fieldoffset as the array is only used to define
9865 * banked registers but later only fieldoffset is used.
9867 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9869 if (state
== ARM_CP_STATE_AA32
) {
9872 * If the register is banked then we don't need to migrate or
9873 * reset the 32-bit instance in certain cases:
9875 * 1) If the register has both 32-bit and 64-bit instances
9876 * then we can count on the 64-bit instance taking care
9877 * of the non-secure bank.
9878 * 2) If ARMv8 is enabled then we can count on a 64-bit
9879 * version taking care of the secure bank. This requires
9880 * that separate 32 and 64-bit definitions are provided.
9882 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9883 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9884 r2
->type
|= ARM_CP_ALIAS
;
9886 } else if ((secstate
!= r
->secure
) && !ns
) {
9888 * The register is not banked so we only want to allow
9889 * migration of the non-secure instance.
9891 r2
->type
|= ARM_CP_ALIAS
;
9894 if (HOST_BIG_ENDIAN
&&
9895 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9896 r2
->fieldoffset
+= sizeof(uint32_t);
9902 * By convention, for wildcarded registers only the first
9903 * entry is used for migration; the others are marked as
9904 * ALIAS so we don't try to transfer the register
9905 * multiple times. Special registers (ie NOP/WFI) are
9906 * never migratable and not even raw-accessible.
9908 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9909 r2
->type
|= ARM_CP_NO_RAW
;
9911 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9912 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9913 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9914 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9918 * Check that raw accesses are either forbidden or handled. Note that
9919 * we can't assert this earlier because the setup of fieldoffset for
9920 * banked registers has to be done first.
9922 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9923 assert(!raw_accessors_invalid(r2
));
9926 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9930 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9931 const ARMCPRegInfo
*r
, void *opaque
)
9934 * Define implementations of coprocessor registers.
9935 * We store these in a hashtable because typically
9936 * there are less than 150 registers in a space which
9937 * is 16*16*16*8*8 = 262144 in size.
9938 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9939 * If a register is defined twice then the second definition is
9940 * used, so this can be used to define some generic registers and
9941 * then override them with implementation specific variations.
9942 * At least one of the original and the second definition should
9943 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9944 * against accidental use.
9946 * The state field defines whether the register is to be
9947 * visible in the AArch32 or AArch64 execution state. If the
9948 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9949 * reginfo structure for the AArch32 view, which sees the lower
9950 * 32 bits of the 64 bit register.
9952 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9953 * be wildcarded. AArch64 registers are always considered to be 64
9954 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9955 * the register, if any.
9957 int crm
, opc1
, opc2
;
9958 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9959 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9960 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9961 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9962 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9963 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9966 /* 64 bit registers have only CRm and Opc1 fields */
9967 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9968 /* op0 only exists in the AArch64 encodings */
9969 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9970 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9971 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9973 * This API is only for Arm's system coprocessors (14 and 15) or
9974 * (M-profile or v7A-and-earlier only) for implementation defined
9975 * coprocessors in the range 0..7. Our decode assumes this, since
9976 * 8..13 can be used for other insns including VFP and Neon. See
9977 * valid_cp() in translate.c. Assert here that we haven't tried
9978 * to use an invalid coprocessor number.
9981 case ARM_CP_STATE_BOTH
:
9982 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9987 case ARM_CP_STATE_AA32
:
9988 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9989 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9990 assert(r
->cp
>= 14 && r
->cp
<= 15);
9992 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9995 case ARM_CP_STATE_AA64
:
9996 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9999 g_assert_not_reached();
10002 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
10003 * encodes a minimum access level for the register. We roll this
10004 * runtime check into our general permission check code, so check
10005 * here that the reginfo's specified permissions are strict enough
10006 * to encompass the generic architectural permission check.
10008 if (r
->state
!= ARM_CP_STATE_AA32
) {
10009 CPAccessRights mask
;
10012 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
10013 mask
= PL0U_R
| PL1_RW
;
10033 /* min_EL EL1, secure mode only (we don't check the latter) */
10037 /* broken reginfo with out-of-range opc1 */
10038 g_assert_not_reached();
10040 /* assert our permissions are not too lax (stricter is fine) */
10041 assert((r
->access
& ~mask
) == 0);
10045 * Check that the register definition has enough info to handle
10046 * reads and writes if they are permitted.
10048 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
10049 if (r
->access
& PL3_R
) {
10050 assert((r
->fieldoffset
||
10051 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
10054 if (r
->access
& PL3_W
) {
10055 assert((r
->fieldoffset
||
10056 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
10061 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
10062 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
10063 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
10064 for (state
= ARM_CP_STATE_AA32
;
10065 state
<= ARM_CP_STATE_AA64
; state
++) {
10066 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
10069 if (state
== ARM_CP_STATE_AA32
) {
10071 * Under AArch32 CP registers can be common
10072 * (same for secure and non-secure world) or banked.
10076 switch (r
->secure
) {
10077 case ARM_CP_SECSTATE_S
:
10078 case ARM_CP_SECSTATE_NS
:
10079 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10080 r
->secure
, crm
, opc1
, opc2
,
10083 case ARM_CP_SECSTATE_BOTH
:
10084 name
= g_strdup_printf("%s_S", r
->name
);
10085 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10087 crm
, opc1
, opc2
, name
);
10089 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10090 ARM_CP_SECSTATE_NS
,
10091 crm
, opc1
, opc2
, r
->name
);
10094 g_assert_not_reached();
10098 * AArch64 registers get mapped to non-secure instance
10101 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10102 ARM_CP_SECSTATE_NS
,
10103 crm
, opc1
, opc2
, r
->name
);
10111 /* Define a whole list of registers */
10112 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
10113 void *opaque
, size_t len
)
10116 for (i
= 0; i
< len
; ++i
) {
10117 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
10122 * Modify ARMCPRegInfo for access from userspace.
10124 * This is a data driven modification directed by
10125 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
10126 * user-space cannot alter any values and dynamic values pertaining to
10127 * execution state are hidden from user space view anyway.
10129 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
10130 const ARMCPRegUserSpaceInfo
*mods
,
10133 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
10134 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
10135 GPatternSpec
*pat
= NULL
;
10138 pat
= g_pattern_spec_new(m
->name
);
10140 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
10141 ARMCPRegInfo
*r
= regs
+ ri
;
10143 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
10144 r
->type
= ARM_CP_CONST
;
10145 r
->access
= PL0U_R
;
10148 } else if (strcmp(r
->name
, m
->name
) == 0) {
10149 r
->type
= ARM_CP_CONST
;
10150 r
->access
= PL0U_R
;
10151 r
->resetvalue
&= m
->exported_bits
;
10152 r
->resetvalue
|= m
->fixed_bits
;
10157 g_pattern_spec_free(pat
);
10162 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
10164 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
10167 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
10170 /* Helper coprocessor write function for write-ignore registers */
10173 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
10175 /* Helper coprocessor write function for read-as-zero registers */
10179 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
10181 /* Helper coprocessor reset function for do-nothing-on-reset registers */
10184 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
10187 * Return true if it is not valid for us to switch to
10188 * this CPU mode (ie all the UNPREDICTABLE cases in
10189 * the ARM ARM CPSRWriteByInstr pseudocode).
10192 /* Changes to or from Hyp via MSR and CPS are illegal. */
10193 if (write_type
== CPSRWriteByInstr
&&
10194 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
10195 mode
== ARM_CPU_MODE_HYP
)) {
10200 case ARM_CPU_MODE_USR
:
10202 case ARM_CPU_MODE_SYS
:
10203 case ARM_CPU_MODE_SVC
:
10204 case ARM_CPU_MODE_ABT
:
10205 case ARM_CPU_MODE_UND
:
10206 case ARM_CPU_MODE_IRQ
:
10207 case ARM_CPU_MODE_FIQ
:
10209 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
10210 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
10213 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
10214 * and CPS are treated as illegal mode changes.
10216 if (write_type
== CPSRWriteByInstr
&&
10217 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
10218 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
10222 case ARM_CPU_MODE_HYP
:
10223 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
10224 case ARM_CPU_MODE_MON
:
10225 return arm_current_el(env
) < 3;
10231 uint32_t cpsr_read(CPUARMState
*env
)
10234 ZF
= (env
->ZF
== 0);
10235 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
10236 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
10237 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
10238 | ((env
->condexec_bits
& 0xfc) << 8)
10239 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
10242 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
10243 CPSRWriteType write_type
)
10245 uint32_t changed_daif
;
10246 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
10247 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
10249 if (mask
& CPSR_NZCV
) {
10250 env
->ZF
= (~val
) & CPSR_Z
;
10252 env
->CF
= (val
>> 29) & 1;
10253 env
->VF
= (val
<< 3) & 0x80000000;
10255 if (mask
& CPSR_Q
) {
10256 env
->QF
= ((val
& CPSR_Q
) != 0);
10258 if (mask
& CPSR_T
) {
10259 env
->thumb
= ((val
& CPSR_T
) != 0);
10261 if (mask
& CPSR_IT_0_1
) {
10262 env
->condexec_bits
&= ~3;
10263 env
->condexec_bits
|= (val
>> 25) & 3;
10265 if (mask
& CPSR_IT_2_7
) {
10266 env
->condexec_bits
&= 3;
10267 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10269 if (mask
& CPSR_GE
) {
10270 env
->GE
= (val
>> 16) & 0xf;
10274 * In a V7 implementation that includes the security extensions but does
10275 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10276 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10277 * bits respectively.
10279 * In a V8 implementation, it is permitted for privileged software to
10280 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10282 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10283 arm_feature(env
, ARM_FEATURE_EL3
) &&
10284 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10285 !arm_is_secure(env
)) {
10287 changed_daif
= (env
->daif
^ val
) & mask
;
10289 if (changed_daif
& CPSR_A
) {
10291 * Check to see if we are allowed to change the masking of async
10292 * abort exceptions from a non-secure state.
10294 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10295 qemu_log_mask(LOG_GUEST_ERROR
,
10296 "Ignoring attempt to switch CPSR_A flag from "
10297 "non-secure world with SCR.AW bit clear\n");
10302 if (changed_daif
& CPSR_F
) {
10304 * Check to see if we are allowed to change the masking of FIQ
10305 * exceptions from a non-secure state.
10307 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10308 qemu_log_mask(LOG_GUEST_ERROR
,
10309 "Ignoring attempt to switch CPSR_F flag from "
10310 "non-secure world with SCR.FW bit clear\n");
10315 * Check whether non-maskable FIQ (NMFI) support is enabled.
10316 * If this bit is set software is not allowed to mask
10317 * FIQs, but is allowed to set CPSR_F to 0.
10319 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10321 qemu_log_mask(LOG_GUEST_ERROR
,
10322 "Ignoring attempt to enable CPSR_F flag "
10323 "(non-maskable FIQ [NMFI] support enabled)\n");
10329 env
->daif
&= ~(CPSR_AIF
& mask
);
10330 env
->daif
|= val
& CPSR_AIF
& mask
;
10332 if (write_type
!= CPSRWriteRaw
&&
10333 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10334 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10336 * Note that we can only get here in USR mode if this is a
10337 * gdb stub write; for this case we follow the architectural
10338 * behaviour for guest writes in USR mode of ignoring an attempt
10339 * to switch mode. (Those are caught by translate.c for writes
10340 * triggered by guest instructions.)
10343 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10345 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10346 * v7, and has defined behaviour in v8:
10347 * + leave CPSR.M untouched
10348 * + allow changes to the other CPSR fields
10350 * For user changes via the GDB stub, we don't set PSTATE.IL,
10351 * as this would be unnecessarily harsh for a user error.
10354 if (write_type
!= CPSRWriteByGDBStub
&&
10355 arm_feature(env
, ARM_FEATURE_V8
)) {
10359 qemu_log_mask(LOG_GUEST_ERROR
,
10360 "Illegal AArch32 mode switch attempt from %s to %s\n",
10361 aarch32_mode_name(env
->uncached_cpsr
),
10362 aarch32_mode_name(val
));
10364 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10365 write_type
== CPSRWriteExceptionReturn
?
10366 "Exception return from AArch32" :
10367 "AArch32 mode switch from",
10368 aarch32_mode_name(env
->uncached_cpsr
),
10369 aarch32_mode_name(val
), env
->regs
[15]);
10370 switch_mode(env
, val
& CPSR_M
);
10373 mask
&= ~CACHED_CPSR_BITS
;
10374 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10375 if (tcg_enabled() && rebuild_hflags
) {
10376 arm_rebuild_hflags(env
);
10380 #ifdef CONFIG_USER_ONLY
10382 static void switch_mode(CPUARMState
*env
, int mode
)
10384 ARMCPU
*cpu
= env_archcpu(env
);
10386 if (mode
!= ARM_CPU_MODE_USR
) {
10387 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10391 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10392 uint32_t cur_el
, bool secure
)
10397 void aarch64_sync_64_to_32(CPUARMState
*env
)
10399 g_assert_not_reached();
10404 static void switch_mode(CPUARMState
*env
, int mode
)
10409 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10410 if (mode
== old_mode
) {
10414 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10415 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10416 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10417 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10418 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10419 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10422 i
= bank_number(old_mode
);
10423 env
->banked_r13
[i
] = env
->regs
[13];
10424 env
->banked_spsr
[i
] = env
->spsr
;
10426 i
= bank_number(mode
);
10427 env
->regs
[13] = env
->banked_r13
[i
];
10428 env
->spsr
= env
->banked_spsr
[i
];
10430 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10431 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10435 * Physical Interrupt Target EL Lookup Table
10437 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10439 * The below multi-dimensional table is used for looking up the target
10440 * exception level given numerous condition criteria. Specifically, the
10441 * target EL is based on SCR and HCR routing controls as well as the
10442 * currently executing EL and secure state.
10445 * target_el_table[2][2][2][2][2][4]
10446 * | | | | | +--- Current EL
10447 * | | | | +------ Non-secure(0)/Secure(1)
10448 * | | | +--------- HCR mask override
10449 * | | +------------ SCR exec state control
10450 * | +--------------- SCR mask override
10451 * +------------------ 32-bit(0)/64-bit(1) EL3
10453 * The table values are as such:
10455 * -1 = Cannot occur
10457 * The ARM ARM target EL table includes entries indicating that an "exception
10458 * is not taken". The two cases where this is applicable are:
10459 * 1) An exception is taken from EL3 but the SCR does not have the exception
10461 * 2) An exception is taken from EL2 but the HCR does not have the exception
10463 * In these two cases, the below table contain a target of EL1. This value is
10464 * returned as it is expected that the consumer of the table data will check
10465 * for "target EL >= current EL" to ensure the exception is not taken.
10469 * BIT IRQ IMO Non-secure Secure
10470 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10472 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10473 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10474 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10475 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10476 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10477 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10478 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10479 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10480 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10481 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10482 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10483 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10484 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10485 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10486 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10487 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10488 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10492 * Determine the target EL for physical exceptions
10494 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10495 uint32_t cur_el
, bool secure
)
10497 CPUARMState
*env
= cpu_env(cs
);
10502 /* Is the highest EL AArch64? */
10503 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10506 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10507 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10510 * Either EL2 is the highest EL (and so the EL2 register width
10511 * is given by is64); or there is no EL2 or EL3, in which case
10512 * the value of 'rw' does not affect the table lookup anyway.
10517 hcr_el2
= arm_hcr_el2_eff(env
);
10518 switch (excp_idx
) {
10520 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10521 hcr
= hcr_el2
& HCR_IMO
;
10524 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10525 hcr
= hcr_el2
& HCR_FMO
;
10528 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10529 hcr
= hcr_el2
& HCR_AMO
;
10534 * For these purposes, TGE and AMO/IMO/FMO both force the
10535 * interrupt to EL2. Fold TGE into the bit extracted above.
10537 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10539 /* Perform a table-lookup for the target EL given the current state */
10540 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10542 assert(target_el
> 0);
10547 void arm_log_exception(CPUState
*cs
)
10549 int idx
= cs
->exception_index
;
10551 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10552 const char *exc
= NULL
;
10553 static const char * const excnames
[] = {
10554 [EXCP_UDEF
] = "Undefined Instruction",
10555 [EXCP_SWI
] = "SVC",
10556 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10557 [EXCP_DATA_ABORT
] = "Data Abort",
10558 [EXCP_IRQ
] = "IRQ",
10559 [EXCP_FIQ
] = "FIQ",
10560 [EXCP_BKPT
] = "Breakpoint",
10561 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10562 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10563 [EXCP_HVC
] = "Hypervisor Call",
10564 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10565 [EXCP_SMC
] = "Secure Monitor Call",
10566 [EXCP_VIRQ
] = "Virtual IRQ",
10567 [EXCP_VFIQ
] = "Virtual FIQ",
10568 [EXCP_SEMIHOST
] = "Semihosting call",
10569 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10570 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10571 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10572 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10573 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10574 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10575 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10576 [EXCP_VSERR
] = "Virtual SERR",
10577 [EXCP_GPC
] = "Granule Protection Check",
10580 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10581 exc
= excnames
[idx
];
10586 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10587 idx
, exc
, cs
->cpu_index
);
10592 * Function used to synchronize QEMU's AArch64 register set with AArch32
10593 * register set. This is necessary when switching between AArch32 and AArch64
10596 void aarch64_sync_32_to_64(CPUARMState
*env
)
10599 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10601 /* We can blanket copy R[0:7] to X[0:7] */
10602 for (i
= 0; i
< 8; i
++) {
10603 env
->xregs
[i
] = env
->regs
[i
];
10607 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10608 * Otherwise, they come from the banked user regs.
10610 if (mode
== ARM_CPU_MODE_FIQ
) {
10611 for (i
= 8; i
< 13; i
++) {
10612 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10615 for (i
= 8; i
< 13; i
++) {
10616 env
->xregs
[i
] = env
->regs
[i
];
10621 * Registers x13-x23 are the various mode SP and FP registers. Registers
10622 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10623 * from the mode banked register.
10625 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10626 env
->xregs
[13] = env
->regs
[13];
10627 env
->xregs
[14] = env
->regs
[14];
10629 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10630 /* HYP is an exception in that it is copied from r14 */
10631 if (mode
== ARM_CPU_MODE_HYP
) {
10632 env
->xregs
[14] = env
->regs
[14];
10634 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10638 if (mode
== ARM_CPU_MODE_HYP
) {
10639 env
->xregs
[15] = env
->regs
[13];
10641 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10644 if (mode
== ARM_CPU_MODE_IRQ
) {
10645 env
->xregs
[16] = env
->regs
[14];
10646 env
->xregs
[17] = env
->regs
[13];
10648 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10649 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10652 if (mode
== ARM_CPU_MODE_SVC
) {
10653 env
->xregs
[18] = env
->regs
[14];
10654 env
->xregs
[19] = env
->regs
[13];
10656 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10657 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10660 if (mode
== ARM_CPU_MODE_ABT
) {
10661 env
->xregs
[20] = env
->regs
[14];
10662 env
->xregs
[21] = env
->regs
[13];
10664 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10665 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10668 if (mode
== ARM_CPU_MODE_UND
) {
10669 env
->xregs
[22] = env
->regs
[14];
10670 env
->xregs
[23] = env
->regs
[13];
10672 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10673 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10677 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10678 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10679 * FIQ bank for r8-r14.
10681 if (mode
== ARM_CPU_MODE_FIQ
) {
10682 for (i
= 24; i
< 31; i
++) {
10683 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10686 for (i
= 24; i
< 29; i
++) {
10687 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10689 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10690 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10693 env
->pc
= env
->regs
[15];
10697 * Function used to synchronize QEMU's AArch32 register set with AArch64
10698 * register set. This is necessary when switching between AArch32 and AArch64
10701 void aarch64_sync_64_to_32(CPUARMState
*env
)
10704 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10706 /* We can blanket copy X[0:7] to R[0:7] */
10707 for (i
= 0; i
< 8; i
++) {
10708 env
->regs
[i
] = env
->xregs
[i
];
10712 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10713 * Otherwise, we copy x8-x12 into the banked user regs.
10715 if (mode
== ARM_CPU_MODE_FIQ
) {
10716 for (i
= 8; i
< 13; i
++) {
10717 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10720 for (i
= 8; i
< 13; i
++) {
10721 env
->regs
[i
] = env
->xregs
[i
];
10726 * Registers r13 & r14 depend on the current mode.
10727 * If we are in a given mode, we copy the corresponding x registers to r13
10728 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10731 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10732 env
->regs
[13] = env
->xregs
[13];
10733 env
->regs
[14] = env
->xregs
[14];
10735 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10738 * HYP is an exception in that it does not have its own banked r14 but
10739 * shares the USR r14
10741 if (mode
== ARM_CPU_MODE_HYP
) {
10742 env
->regs
[14] = env
->xregs
[14];
10744 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10748 if (mode
== ARM_CPU_MODE_HYP
) {
10749 env
->regs
[13] = env
->xregs
[15];
10751 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10754 if (mode
== ARM_CPU_MODE_IRQ
) {
10755 env
->regs
[14] = env
->xregs
[16];
10756 env
->regs
[13] = env
->xregs
[17];
10758 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10759 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10762 if (mode
== ARM_CPU_MODE_SVC
) {
10763 env
->regs
[14] = env
->xregs
[18];
10764 env
->regs
[13] = env
->xregs
[19];
10766 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10767 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10770 if (mode
== ARM_CPU_MODE_ABT
) {
10771 env
->regs
[14] = env
->xregs
[20];
10772 env
->regs
[13] = env
->xregs
[21];
10774 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10775 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10778 if (mode
== ARM_CPU_MODE_UND
) {
10779 env
->regs
[14] = env
->xregs
[22];
10780 env
->regs
[13] = env
->xregs
[23];
10782 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10783 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10787 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10788 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10789 * FIQ bank for r8-r14.
10791 if (mode
== ARM_CPU_MODE_FIQ
) {
10792 for (i
= 24; i
< 31; i
++) {
10793 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10796 for (i
= 24; i
< 29; i
++) {
10797 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10799 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10800 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10803 env
->regs
[15] = env
->pc
;
10806 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10807 uint32_t mask
, uint32_t offset
,
10812 /* Change the CPU state so as to actually take the exception. */
10813 switch_mode(env
, new_mode
);
10816 * For exceptions taken to AArch32 we must clear the SS bit in both
10817 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10819 env
->pstate
&= ~PSTATE_SS
;
10820 env
->spsr
= cpsr_read(env
);
10821 /* Clear IT bits. */
10822 env
->condexec_bits
= 0;
10823 /* Switch to the new mode, and to the correct instruction set. */
10824 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10826 /* This must be after mode switching. */
10827 new_el
= arm_current_el(env
);
10829 /* Set new mode endianness */
10830 env
->uncached_cpsr
&= ~CPSR_E
;
10831 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10832 env
->uncached_cpsr
|= CPSR_E
;
10834 /* J and IL must always be cleared for exception entry */
10835 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10838 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10839 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10840 env
->uncached_cpsr
|= CPSR_SSBS
;
10842 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10846 if (new_mode
== ARM_CPU_MODE_HYP
) {
10847 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10848 env
->elr_el
[2] = env
->regs
[15];
10850 /* CPSR.PAN is normally preserved preserved unless... */
10851 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10854 if (!arm_is_secure_below_el3(env
)) {
10855 /* ... the target is EL3, from non-secure state. */
10856 env
->uncached_cpsr
&= ~CPSR_PAN
;
10859 /* ... the target is EL3, from secure state ... */
10862 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10863 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10864 env
->uncached_cpsr
|= CPSR_PAN
;
10870 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10871 * and we should just guard the thumb mode on V4
10873 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10875 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10877 env
->regs
[14] = env
->regs
[15] + offset
;
10879 env
->regs
[15] = newpc
;
10881 if (tcg_enabled()) {
10882 arm_rebuild_hflags(env
);
10886 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10889 * Handle exception entry to Hyp mode; this is sufficiently
10890 * different to entry to other AArch32 modes that we handle it
10893 * The vector table entry used is always the 0x14 Hyp mode entry point,
10894 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10895 * The offset applied to the preferred return address is always zero
10896 * (see DDI0487C.a section G1.12.3).
10897 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10899 uint32_t addr
, mask
;
10900 ARMCPU
*cpu
= ARM_CPU(cs
);
10901 CPUARMState
*env
= &cpu
->env
;
10903 switch (cs
->exception_index
) {
10911 /* Fall through to prefetch abort. */
10912 case EXCP_PREFETCH_ABORT
:
10913 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10914 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10915 (uint32_t)env
->exception
.vaddress
);
10918 case EXCP_DATA_ABORT
:
10919 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10920 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10921 (uint32_t)env
->exception
.vaddress
);
10933 case EXCP_HYP_TRAP
:
10937 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10940 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10941 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10943 * QEMU syndrome values are v8-style. v7 has the IL bit
10944 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10945 * If this is a v7 CPU, squash the IL bit in those cases.
10947 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10948 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10949 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10950 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10951 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10954 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10957 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10962 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10965 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10968 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10972 addr
+= env
->cp15
.hvbar
;
10974 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10977 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10979 ARMCPU
*cpu
= ARM_CPU(cs
);
10980 CPUARMState
*env
= &cpu
->env
;
10987 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10988 switch (syn_get_ec(env
->exception
.syndrome
)) {
10989 case EC_BREAKPOINT
:
10990 case EC_BREAKPOINT_SAME_EL
:
10993 case EC_WATCHPOINT
:
10994 case EC_WATCHPOINT_SAME_EL
:
11000 case EC_VECTORCATCH
:
11009 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
11012 if (env
->exception
.target_el
== 2) {
11013 arm_cpu_do_interrupt_aarch32_hyp(cs
);
11017 switch (cs
->exception_index
) {
11019 new_mode
= ARM_CPU_MODE_UND
;
11029 new_mode
= ARM_CPU_MODE_SVC
;
11032 /* The PC already points to the next instruction. */
11036 /* Fall through to prefetch abort. */
11037 case EXCP_PREFETCH_ABORT
:
11038 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
11039 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
11040 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
11041 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
11042 new_mode
= ARM_CPU_MODE_ABT
;
11044 mask
= CPSR_A
| CPSR_I
;
11047 case EXCP_DATA_ABORT
:
11048 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11049 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
11050 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
11051 env
->exception
.fsr
,
11052 (uint32_t)env
->exception
.vaddress
);
11053 new_mode
= ARM_CPU_MODE_ABT
;
11055 mask
= CPSR_A
| CPSR_I
;
11059 new_mode
= ARM_CPU_MODE_IRQ
;
11061 /* Disable IRQ and imprecise data aborts. */
11062 mask
= CPSR_A
| CPSR_I
;
11064 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
11065 /* IRQ routed to monitor mode */
11066 new_mode
= ARM_CPU_MODE_MON
;
11071 new_mode
= ARM_CPU_MODE_FIQ
;
11073 /* Disable FIQ, IRQ and imprecise data aborts. */
11074 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11075 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
11076 /* FIQ routed to monitor mode */
11077 new_mode
= ARM_CPU_MODE_MON
;
11082 new_mode
= ARM_CPU_MODE_IRQ
;
11084 /* Disable IRQ and imprecise data aborts. */
11085 mask
= CPSR_A
| CPSR_I
;
11089 new_mode
= ARM_CPU_MODE_FIQ
;
11091 /* Disable FIQ, IRQ and imprecise data aborts. */
11092 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11098 * Note that this is reported as a data abort, but the DFAR
11099 * has an UNKNOWN value. Construct the SError syndrome from
11100 * AET and ExT fields.
11102 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
11104 if (extended_addresses_enabled(env
)) {
11105 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
11107 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
11109 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
11110 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11111 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
11112 env
->exception
.fsr
);
11114 new_mode
= ARM_CPU_MODE_ABT
;
11116 mask
= CPSR_A
| CPSR_I
;
11121 new_mode
= ARM_CPU_MODE_MON
;
11123 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11127 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11128 return; /* Never happens. Keep compiler happy. */
11131 if (new_mode
== ARM_CPU_MODE_MON
) {
11132 addr
+= env
->cp15
.mvbar
;
11133 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
11134 /* High vectors. When enabled, base address cannot be remapped. */
11135 addr
+= 0xffff0000;
11138 * ARM v7 architectures provide a vector base address register to remap
11139 * the interrupt vector table.
11140 * This register is only followed in non-monitor mode, and is banked.
11141 * Note: only bits 31:5 are valid.
11143 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
11146 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
11147 env
->cp15
.scr_el3
&= ~SCR_NS
;
11150 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
11153 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
11156 * Return the register number of the AArch64 view of the AArch32
11157 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
11158 * be that of the AArch32 mode the exception came from.
11160 int mode
= env
->uncached_cpsr
& CPSR_M
;
11162 switch (aarch32_reg
) {
11164 return aarch32_reg
;
11166 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
11169 case ARM_CPU_MODE_USR
:
11170 case ARM_CPU_MODE_SYS
:
11172 case ARM_CPU_MODE_HYP
:
11174 case ARM_CPU_MODE_IRQ
:
11176 case ARM_CPU_MODE_SVC
:
11178 case ARM_CPU_MODE_ABT
:
11180 case ARM_CPU_MODE_UND
:
11182 case ARM_CPU_MODE_FIQ
:
11185 g_assert_not_reached();
11189 case ARM_CPU_MODE_USR
:
11190 case ARM_CPU_MODE_SYS
:
11191 case ARM_CPU_MODE_HYP
:
11193 case ARM_CPU_MODE_IRQ
:
11195 case ARM_CPU_MODE_SVC
:
11197 case ARM_CPU_MODE_ABT
:
11199 case ARM_CPU_MODE_UND
:
11201 case ARM_CPU_MODE_FIQ
:
11204 g_assert_not_reached();
11209 g_assert_not_reached();
11213 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11215 uint32_t ret
= cpsr_read(env
);
11217 /* Move DIT to the correct location for SPSR_ELx */
11218 if (ret
& CPSR_DIT
) {
11222 /* Merge PSTATE.SS into SPSR_ELx */
11223 ret
|= env
->pstate
& PSTATE_SS
;
11228 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11230 /* Return true if this syndrome value is a synchronous external abort */
11231 switch (syn_get_ec(syndrome
)) {
11233 case EC_INSNABORT_SAME_EL
:
11235 case EC_DATAABORT_SAME_EL
:
11236 /* Look at fault status code for all the synchronous ext abort cases */
11237 switch (syndrome
& 0x3f) {
11253 /* Handle exception entry to a target EL which is using AArch64 */
11254 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11256 ARMCPU
*cpu
= ARM_CPU(cs
);
11257 CPUARMState
*env
= &cpu
->env
;
11258 unsigned int new_el
= env
->exception
.target_el
;
11259 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11260 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11261 unsigned int old_mode
;
11262 unsigned int cur_el
= arm_current_el(env
);
11265 if (tcg_enabled()) {
11267 * Note that new_el can never be 0. If cur_el is 0, then
11268 * el0_a64 is is_a64(), else el0_a64 is ignored.
11270 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11273 if (cur_el
< new_el
) {
11275 * Entry vector offset depends on whether the implemented EL
11276 * immediately lower than the target level is using AArch32 or AArch64
11283 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11286 hcr
= arm_hcr_el2_eff(env
);
11287 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11288 is_aa64
= (hcr
& HCR_RW
) != 0;
11293 is_aa64
= is_a64(env
);
11296 g_assert_not_reached();
11304 } else if (pstate_read(env
) & PSTATE_SP
) {
11308 switch (cs
->exception_index
) {
11310 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11311 env
->cp15
.mfar_el3
);
11313 case EXCP_PREFETCH_ABORT
:
11314 case EXCP_DATA_ABORT
:
11316 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11317 * to be taken to the SError vector entrypoint.
11319 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11320 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11323 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11324 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11325 env
->cp15
.far_el
[new_el
]);
11331 case EXCP_HYP_TRAP
:
11333 switch (syn_get_ec(env
->exception
.syndrome
)) {
11334 case EC_ADVSIMDFPACCESSTRAP
:
11336 * QEMU internal FP/SIMD syndromes from AArch32 include the
11337 * TA and coproc fields which are only exposed if the exception
11338 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11339 * AArch64 format syndrome.
11341 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11343 case EC_CP14RTTRAP
:
11344 case EC_CP15RTTRAP
:
11345 case EC_CP14DTTRAP
:
11347 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11348 * the raw register field from the insn; when taking this to
11349 * AArch64 we must convert it to the AArch64 view of the register
11350 * number. Notice that we read a 4-bit AArch32 register number and
11351 * write back a 5-bit AArch64 one.
11353 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11354 rt
= aarch64_regnum(env
, rt
);
11355 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11358 case EC_CP15RRTTRAP
:
11359 case EC_CP14RRTTRAP
:
11360 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11361 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11362 rt
= aarch64_regnum(env
, rt
);
11363 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11365 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11366 rt
= aarch64_regnum(env
, rt
);
11367 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11371 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11383 /* Construct the SError syndrome from IDS and ISS fields. */
11384 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11385 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11388 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11392 old_mode
= pstate_read(env
);
11393 aarch64_save_sp(env
, arm_current_el(env
));
11394 env
->elr_el
[new_el
] = env
->pc
;
11396 if (cur_el
== 1 && new_el
== 1) {
11397 uint64_t hcr
= arm_hcr_el2_eff(env
);
11398 if ((hcr
& (HCR_NV
| HCR_NV1
| HCR_NV2
)) == HCR_NV
||
11399 (hcr
& (HCR_NV
| HCR_NV2
)) == (HCR_NV
| HCR_NV2
)) {
11401 * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR
11402 * by setting M[3:2] to 0b10.
11403 * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN)
11404 * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM)
11406 old_mode
= deposit32(old_mode
, 2, 2, 2);
11410 old_mode
= cpsr_read_for_spsr_elx(env
);
11411 env
->elr_el
[new_el
] = env
->regs
[15];
11413 aarch64_sync_32_to_64(env
);
11415 env
->condexec_bits
= 0;
11417 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11419 qemu_log_mask(CPU_LOG_INT
, "...with SPSR 0x%x\n", old_mode
);
11420 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11421 env
->elr_el
[new_el
]);
11423 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11424 /* The value of PSTATE.PAN is normally preserved, except when ... */
11425 new_mode
|= old_mode
& PSTATE_PAN
;
11428 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11429 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11430 != (HCR_E2H
| HCR_TGE
)) {
11435 /* ... the target is EL1 ... */
11436 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11437 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11438 new_mode
|= PSTATE_PAN
;
11443 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11444 new_mode
|= PSTATE_TCO
;
11447 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11448 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11449 new_mode
|= PSTATE_SSBS
;
11451 new_mode
&= ~PSTATE_SSBS
;
11455 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11456 env
->aarch64
= true;
11457 aarch64_restore_sp(env
, new_el
);
11459 if (tcg_enabled()) {
11460 helper_rebuild_hflags_a64(env
, new_el
);
11465 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11466 new_el
, env
->pc
, pstate_read(env
));
11470 * Do semihosting call and set the appropriate return value. All the
11471 * permission and validity checks have been done at translate time.
11473 * We only see semihosting exceptions in TCG only as they are not
11474 * trapped to the hypervisor in KVM.
11477 static void tcg_handle_semihosting(CPUState
*cs
)
11479 ARMCPU
*cpu
= ARM_CPU(cs
);
11480 CPUARMState
*env
= &cpu
->env
;
11483 qemu_log_mask(CPU_LOG_INT
,
11484 "...handling as semihosting call 0x%" PRIx64
"\n",
11486 do_common_semihosting(cs
);
11489 qemu_log_mask(CPU_LOG_INT
,
11490 "...handling as semihosting call 0x%x\n",
11492 do_common_semihosting(cs
);
11493 env
->regs
[15] += env
->thumb
? 2 : 4;
11499 * Handle a CPU exception for A and R profile CPUs.
11500 * Do any appropriate logging, handle PSCI calls, and then hand off
11501 * to the AArch64-entry or AArch32-entry function depending on the
11502 * target exception level's register width.
11504 * Note: this is used for both TCG (as the do_interrupt tcg op),
11505 * and KVM to re-inject guest debug exceptions, and to
11506 * inject a Synchronous-External-Abort.
11508 void arm_cpu_do_interrupt(CPUState
*cs
)
11510 ARMCPU
*cpu
= ARM_CPU(cs
);
11511 CPUARMState
*env
= &cpu
->env
;
11512 unsigned int new_el
= env
->exception
.target_el
;
11514 assert(!arm_feature(env
, ARM_FEATURE_M
));
11516 arm_log_exception(cs
);
11517 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11519 if (qemu_loglevel_mask(CPU_LOG_INT
)
11520 && !excp_is_internal(cs
->exception_index
)) {
11521 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11522 syn_get_ec(env
->exception
.syndrome
),
11523 env
->exception
.syndrome
);
11526 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11527 arm_handle_psci_call(cpu
);
11528 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11533 * Semihosting semantics depend on the register width of the code
11534 * that caused the exception, not the target exception level, so
11535 * must be handled here.
11538 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11539 tcg_handle_semihosting(cs
);
11545 * Hooks may change global state so BQL should be held, also the
11546 * BQL needs to be held for any modification of
11547 * cs->interrupt_request.
11549 g_assert(bql_locked());
11551 arm_call_pre_el_change_hook(cpu
);
11553 assert(!excp_is_internal(cs
->exception_index
));
11554 if (arm_el_is_aa64(env
, new_el
)) {
11555 arm_cpu_do_interrupt_aarch64(cs
);
11557 arm_cpu_do_interrupt_aarch32(cs
);
11560 arm_call_el_change_hook(cpu
);
11562 if (!kvm_enabled()) {
11563 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11566 #endif /* !CONFIG_USER_ONLY */
11568 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11570 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11572 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11573 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11575 return env
->cp15
.sctlr_el
[el
];
11578 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11580 if (regime_has_2_ranges(mmu_idx
)) {
11581 return extract64(tcr
, 37, 2);
11582 } else if (regime_is_stage2(mmu_idx
)) {
11583 return 0; /* VTCR_EL2 */
11585 /* Replicate the single TBI bit so we always have 2 bits. */
11586 return extract32(tcr
, 20, 1) * 3;
11590 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11592 if (regime_has_2_ranges(mmu_idx
)) {
11593 return extract64(tcr
, 51, 2);
11594 } else if (regime_is_stage2(mmu_idx
)) {
11595 return 0; /* VTCR_EL2 */
11597 /* Replicate the single TBID bit so we always have 2 bits. */
11598 return extract32(tcr
, 29, 1) * 3;
11602 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11604 if (regime_has_2_ranges(mmu_idx
)) {
11605 return extract64(tcr
, 57, 2);
11607 /* Replicate the single TCMA bit so we always have 2 bits. */
11608 return extract32(tcr
, 30, 1) * 3;
11612 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11622 return GranInvalid
;
11626 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11636 return GranInvalid
;
11640 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11642 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11643 : cpu_isar_feature(aa64_tgran4
, cpu
);
11646 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11648 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11649 : cpu_isar_feature(aa64_tgran16
, cpu
);
11652 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11654 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11655 : cpu_isar_feature(aa64_tgran64
, cpu
);
11658 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11663 if (have4k(cpu
, stage2
)) {
11668 if (have16k(cpu
, stage2
)) {
11673 if (have64k(cpu
, stage2
)) {
11681 * If the guest selects a granule size that isn't implemented,
11682 * the architecture requires that we behave as if it selected one
11683 * that is (with an IMPDEF choice of which one to pick). We choose
11684 * to implement the smallest supported granule size.
11686 if (have4k(cpu
, stage2
)) {
11689 if (have16k(cpu
, stage2
)) {
11692 assert(have64k(cpu
, stage2
));
11696 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11697 ARMMMUIdx mmu_idx
, bool data
,
11700 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11701 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11702 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11703 ARMGranuleSize gran
;
11704 ARMCPU
*cpu
= env_archcpu(env
);
11705 bool stage2
= regime_is_stage2(mmu_idx
);
11707 if (!regime_has_2_ranges(mmu_idx
)) {
11709 tsz
= extract32(tcr
, 0, 6);
11710 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11715 hpd
= extract32(tcr
, 24, 1);
11718 sh
= extract32(tcr
, 12, 2);
11719 ps
= extract32(tcr
, 16, 3);
11720 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11721 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11722 ds
= extract64(tcr
, 32, 1);
11727 * Bit 55 is always between the two regions, and is canonical for
11728 * determining if address tagging is enabled.
11730 select
= extract64(va
, 55, 1);
11732 tsz
= extract32(tcr
, 0, 6);
11733 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11734 epd
= extract32(tcr
, 7, 1);
11735 sh
= extract32(tcr
, 12, 2);
11736 hpd
= extract64(tcr
, 41, 1);
11737 e0pd
= extract64(tcr
, 55, 1);
11739 tsz
= extract32(tcr
, 16, 6);
11740 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11741 epd
= extract32(tcr
, 23, 1);
11742 sh
= extract32(tcr
, 28, 2);
11743 hpd
= extract64(tcr
, 42, 1);
11744 e0pd
= extract64(tcr
, 56, 1);
11746 ps
= extract64(tcr
, 32, 3);
11747 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11748 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11749 ds
= extract64(tcr
, 59, 1);
11751 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11752 regime_is_user(env
, mmu_idx
)) {
11757 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11759 if (cpu_isar_feature(aa64_st
, cpu
)) {
11760 max_tsz
= 48 - (gran
== Gran64K
);
11766 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11767 * adjust the effective value of DS, as documented.
11770 if (gran
== Gran64K
) {
11771 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11776 if (regime_is_stage2(mmu_idx
)) {
11777 if (gran
== Gran16K
) {
11778 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11780 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11783 if (gran
== Gran16K
) {
11784 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11786 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11794 if (stage2
&& el1_is_aa32
) {
11796 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11797 * are loosened: a configured IPA of 40 bits is permitted even if
11798 * the implemented PA is less than that (and so a 40 bit IPA would
11799 * fault for an AArch64 EL1). See R_DTLMN.
11801 min_tsz
= MIN(min_tsz
, 24);
11804 if (tsz
> max_tsz
) {
11807 } else if (tsz
< min_tsz
) {
11814 /* Present TBI as a composite with TBID. */
11815 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11817 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11819 tbi
= (tbi
>> select
) & 1;
11821 return (ARMVAParameters
) {
11829 .tsz_oob
= tsz_oob
,
11838 * Note that signed overflow is undefined in C. The following routines are
11839 * careful to use unsigned types where modulo arithmetic is required.
11840 * Failure to do so _will_ break on newer gcc.
11843 /* Signed saturating arithmetic. */
11845 /* Perform 16-bit signed saturating addition. */
11846 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11851 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11861 /* Perform 8-bit signed saturating addition. */
11862 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11867 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11877 /* Perform 16-bit signed saturating subtraction. */
11878 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11883 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11893 /* Perform 8-bit signed saturating subtraction. */
11894 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11899 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11909 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11910 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11911 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11912 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11915 #include "op_addsub.h"
11917 /* Unsigned saturating arithmetic. */
11918 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11928 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11937 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11947 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11956 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11957 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11958 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11959 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11962 #include "op_addsub.h"
11964 /* Signed modulo arithmetic. */
11965 #define SARITH16(a, b, n, op) do { \
11967 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11968 RESULT(sum, n, 16); \
11970 ge |= 3 << (n * 2); \
11973 #define SARITH8(a, b, n, op) do { \
11975 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11976 RESULT(sum, n, 8); \
11982 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11983 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11984 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11985 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11989 #include "op_addsub.h"
11991 /* Unsigned modulo arithmetic. */
11992 #define ADD16(a, b, n) do { \
11994 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11995 RESULT(sum, n, 16); \
11996 if ((sum >> 16) == 1) \
11997 ge |= 3 << (n * 2); \
12000 #define ADD8(a, b, n) do { \
12002 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12003 RESULT(sum, n, 8); \
12004 if ((sum >> 8) == 1) \
12008 #define SUB16(a, b, n) do { \
12010 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12011 RESULT(sum, n, 16); \
12012 if ((sum >> 16) == 0) \
12013 ge |= 3 << (n * 2); \
12016 #define SUB8(a, b, n) do { \
12018 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12019 RESULT(sum, n, 8); \
12020 if ((sum >> 8) == 0) \
12027 #include "op_addsub.h"
12029 /* Halved signed arithmetic. */
12030 #define ADD16(a, b, n) \
12031 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12032 #define SUB16(a, b, n) \
12033 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12034 #define ADD8(a, b, n) \
12035 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12036 #define SUB8(a, b, n) \
12037 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12040 #include "op_addsub.h"
12042 /* Halved unsigned arithmetic. */
12043 #define ADD16(a, b, n) \
12044 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12045 #define SUB16(a, b, n) \
12046 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12047 #define ADD8(a, b, n) \
12048 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12049 #define SUB8(a, b, n) \
12050 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12053 #include "op_addsub.h"
12055 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
12064 /* Unsigned sum of absolute byte differences. */
12065 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12068 sum
= do_usad(a
, b
);
12069 sum
+= do_usad(a
>> 8, b
>> 8);
12070 sum
+= do_usad(a
>> 16, b
>> 16);
12071 sum
+= do_usad(a
>> 24, b
>> 24);
12075 /* For ARMv6 SEL instruction. */
12076 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12091 mask
|= 0xff000000;
12093 return (a
& mask
) | (b
& ~mask
);
12098 * The upper bytes of val (above the number specified by 'bytes') must have
12099 * been zeroed out by the caller.
12101 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12105 stl_le_p(buf
, val
);
12107 /* zlib crc32 converts the accumulator and output to one's complement. */
12108 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12111 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12115 stl_le_p(buf
, val
);
12117 /* Linux crc32c converts the output to one's complement. */
12118 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12122 * Return the exception level to which FP-disabled exceptions should
12123 * be taken, or 0 if FP is enabled.
12125 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12127 #ifndef CONFIG_USER_ONLY
12131 * CPACR and the CPTR registers don't exist before v6, so FP is
12132 * always accessible
12134 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12138 if (arm_feature(env
, ARM_FEATURE_M
)) {
12139 /* CPACR can cause a NOCP UsageFault taken to current security state */
12140 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12144 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12145 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12146 /* FP insns cause a NOCP UsageFault taken to Secure */
12154 hcr_el2
= arm_hcr_el2_eff(env
);
12157 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12158 * 0, 2 : trap EL0 and EL1/PL1 accesses
12159 * 1 : trap only EL0 accesses
12160 * 3 : trap no accesses
12161 * This register is ignored if E2H+TGE are both set.
12163 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12164 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
12174 /* Trap from Secure PL0 or PL1 to Secure PL1. */
12175 if (!arm_el_is_aa64(env
, 3)
12176 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
12187 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12188 * to control non-secure access to the FPU. It doesn't have any
12189 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12191 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12192 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12193 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12194 /* FP insns act as UNDEF */
12195 return cur_el
== 2 ? 2 : 1;
12200 * CPTR_EL2 is present in v7VE or v8, and changes format
12201 * with HCR_EL2.E2H (regardless of TGE).
12204 if (hcr_el2
& HCR_E2H
) {
12205 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
12207 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
12215 } else if (arm_is_el2_enabled(env
)) {
12216 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
12222 /* CPTR_EL3 : present in v8 */
12223 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
12224 /* Trap all FP ops to EL3 */
12231 /* Return the exception level we're running at if this is our mmu_idx */
12232 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12234 if (mmu_idx
& ARM_MMU_IDX_M
) {
12235 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12239 case ARMMMUIdx_E10_0
:
12240 case ARMMMUIdx_E20_0
:
12242 case ARMMMUIdx_E10_1
:
12243 case ARMMMUIdx_E10_1_PAN
:
12246 case ARMMMUIdx_E20_2
:
12247 case ARMMMUIdx_E20_2_PAN
:
12252 g_assert_not_reached();
12257 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12259 g_assert_not_reached();
12263 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12268 if (arm_feature(env
, ARM_FEATURE_M
)) {
12269 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12272 /* See ARM pseudo-function ELIsInHost. */
12275 hcr
= arm_hcr_el2_eff(env
);
12276 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12277 idx
= ARMMMUIdx_E20_0
;
12279 idx
= ARMMMUIdx_E10_0
;
12283 if (arm_pan_enabled(env
)) {
12284 idx
= ARMMMUIdx_E10_1_PAN
;
12286 idx
= ARMMMUIdx_E10_1
;
12290 /* Note that TGE does not apply at EL2. */
12291 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12292 if (arm_pan_enabled(env
)) {
12293 idx
= ARMMMUIdx_E20_2_PAN
;
12295 idx
= ARMMMUIdx_E20_2
;
12298 idx
= ARMMMUIdx_E2
;
12302 return ARMMMUIdx_E3
;
12304 g_assert_not_reached();
12310 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12312 return arm_mmu_idx_el(env
, arm_current_el(env
));
12315 static bool mve_no_pred(CPUARMState
*env
)
12318 * Return true if there is definitely no predication of MVE
12319 * instructions by VPR or LTPSIZE. (Returning false even if there
12320 * isn't any predication is OK; generated code will just be
12322 * If the CPU does not implement MVE then this TB flag is always 0.
12324 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12325 * logic in gen_update_fp_context() needs to be updated to match.
12327 * We do not include the effect of the ECI bits here -- they are
12328 * tracked in other TB flags. This simplifies the logic for
12329 * "when did we emit code that changes the MVE_NO_PRED TB flag
12330 * and thus need to end the TB?".
12332 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12335 if (env
->v7m
.vpr
) {
12338 if (env
->v7m
.ltpsize
< 4) {
12344 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12345 uint64_t *cs_base
, uint32_t *pflags
)
12347 CPUARMTBFlags flags
;
12349 assert_hflags_rebuild_correctly(env
);
12350 flags
= env
->hflags
;
12352 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12354 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12355 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12358 *pc
= env
->regs
[15];
12360 if (arm_feature(env
, ARM_FEATURE_M
)) {
12361 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12362 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12363 != env
->v7m
.secure
) {
12364 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12367 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12368 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12369 (env
->v7m
.secure
&&
12370 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12372 * ASPEN is set, but FPCA/SFPA indicate that there is no
12373 * active FP context; we must create a new FP context before
12374 * executing any FP insn.
12376 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12379 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12380 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12381 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12384 if (mve_no_pred(env
)) {
12385 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12389 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12390 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12392 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12393 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12395 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12396 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12398 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12399 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12403 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12404 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12408 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12409 * states defined in the ARM ARM for software singlestep:
12410 * SS_ACTIVE PSTATE.SS State
12411 * 0 x Inactive (the TB flag for SS is always 0)
12412 * 1 0 Active-pending
12413 * 1 1 Active-not-pending
12414 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12416 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12417 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12420 *pflags
= flags
.flags
;
12421 *cs_base
= flags
.flags2
;
12424 #ifdef TARGET_AARCH64
12426 * The manual says that when SVE is enabled and VQ is widened the
12427 * implementation is allowed to zero the previously inaccessible
12428 * portion of the registers. The corollary to that is that when
12429 * SVE is enabled and VQ is narrowed we are also allowed to zero
12430 * the now inaccessible portion of the registers.
12432 * The intent of this is that no predicate bit beyond VQ is ever set.
12433 * Which means that some operations on predicate registers themselves
12434 * may operate on full uint64_t or even unrolled across the maximum
12435 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12436 * may well be cheaper than conditionals to restrict the operation
12437 * to the relevant portion of a uint16_t[16].
12439 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12444 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12445 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12447 /* Zap the high bits of the zregs. */
12448 for (i
= 0; i
< 32; i
++) {
12449 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12452 /* Zap the high bits of the pregs and ffr. */
12455 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12457 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12458 for (i
= 0; i
< 17; ++i
) {
12459 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12465 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12470 exc_el
= sme_exception_el(env
, el
);
12472 exc_el
= sve_exception_el(env
, el
);
12475 return 0; /* disabled */
12477 return sve_vqm1_for_el_sm(env
, el
, sm
);
12481 * Notice a change in SVE vector size when changing EL.
12483 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12484 int new_el
, bool el0_a64
)
12486 ARMCPU
*cpu
= env_archcpu(env
);
12487 int old_len
, new_len
;
12488 bool old_a64
, new_a64
, sm
;
12490 /* Nothing to do if no SVE. */
12491 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12495 /* Nothing to do if FP is disabled in either EL. */
12496 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12500 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12501 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12504 * Both AArch64.TakeException and AArch64.ExceptionReturn
12505 * invoke ResetSVEState when taking an exception from, or
12506 * returning to, AArch32 state when PSTATE.SM is enabled.
12508 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12509 if (old_a64
!= new_a64
&& sm
) {
12510 arm_reset_sve_state(env
);
12515 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12516 * at ELx, or not available because the EL is in AArch32 state, then
12517 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12518 * has an effective value of 0".
12520 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12521 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12522 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12523 * we already have the correct register contents when encountering the
12524 * vq0->vq0 transition between EL0->EL1.
12526 old_len
= new_len
= 0;
12528 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12531 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12534 /* When changing vector length, clear inaccessible state. */
12535 if (new_len
< old_len
) {
12536 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12541 #ifndef CONFIG_USER_ONLY
12542 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12544 if (arm_feature(env
, ARM_FEATURE_M
)) {
12545 return arm_secure_to_space(env
->v7m
.secure
);
12549 * If EL3 is not supported then the secure state is implementation
12550 * defined, in which case QEMU defaults to non-secure.
12552 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12553 return ARMSS_NonSecure
;
12556 /* Check for AArch64 EL3 or AArch32 Mon. */
12558 if (extract32(env
->pstate
, 2, 2) == 3) {
12559 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12562 return ARMSS_Secure
;
12566 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12567 return ARMSS_Secure
;
12571 return arm_security_space_below_el3(env
);
12574 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12576 assert(!arm_feature(env
, ARM_FEATURE_M
));
12579 * If EL3 is not supported then the secure state is implementation
12580 * defined, in which case QEMU defaults to non-secure.
12582 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12583 return ARMSS_NonSecure
;
12587 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12588 * Ignoring NSE when !NS retains consistency without having to
12589 * modify other predicates.
12591 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12592 return ARMSS_Secure
;
12593 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12594 return ARMSS_Realm
;
12596 return ARMSS_NonSecure
;
12599 #endif /* !CONFIG_USER_ONLY */