target/arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target/arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 #include "hw/registerfields.h"
  29
  30 /* register banks for CPU modes */
  31 #define BANK_USRSYS 0
  32 #define BANK_SVC    1
  33 #define BANK_ABT    2
  34 #define BANK_UND    3
  35 #define BANK_IRQ    4
  36 #define BANK_FIQ    5
  37 #define BANK_HYP    6
  38 #define BANK_MON    7
  39
  40 static inline bool excp_is_internal(int excp)
  41 {
  42     /* Return true if this exception number represents a QEMU-internal
  43      * exception that will not be passed to the guest.
  44      */
  45     return excp == EXCP_INTERRUPT
  46         || excp == EXCP_HLT
  47         || excp == EXCP_DEBUG
  48         || excp == EXCP_HALTED
  49         || excp == EXCP_EXCEPTION_EXIT
  50         || excp == EXCP_KERNEL_TRAP
  51         || excp == EXCP_SEMIHOST;
  52 }
  53
  54 /* Scale factor for generic timers, ie number of ns per tick.
  55  * This gives a 62.5MHz timer.
  56  */
  57 #define GTIMER_SCALE 16
  58
  59 /* Bit definitions for the v7M CONTROL register */
  60 FIELD(V7M_CONTROL, NPRIV, 0, 1)
  61 FIELD(V7M_CONTROL, SPSEL, 1, 1)
  62 FIELD(V7M_CONTROL, FPCA, 2, 1)
  63 FIELD(V7M_CONTROL, SFPA, 3, 1)
  64
  65 /* Bit definitions for v7M exception return payload */
  66 FIELD(V7M_EXCRET, ES, 0, 1)
  67 FIELD(V7M_EXCRET, RES0, 1, 1)
  68 FIELD(V7M_EXCRET, SPSEL, 2, 1)
  69 FIELD(V7M_EXCRET, MODE, 3, 1)
  70 FIELD(V7M_EXCRET, FTYPE, 4, 1)
  71 FIELD(V7M_EXCRET, DCRS, 5, 1)
  72 FIELD(V7M_EXCRET, S, 6, 1)
  73 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
  74
  75 /* We use a few fake FSR values for internal purposes in M profile.
  76  * M profile cores don't have A/R format FSRs, but currently our
  77  * get_phys_addr() code assumes A/R profile and reports failures via
  78  * an A/R format FSR value. We then translate that into the proper
  79  * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
  80  * Mostly the FSR values we use for this are those defined for v7PMSA,
  81  * since we share some of that codepath. A few kinds of fault are
  82  * only for M profile and have no A/R equivalent, though, so we have
  83  * to pick a value from the reserved range (which we never otherwise
  84  * generate) to use for these.
  85  * These values will never be visible to the guest.
  86  */
  87 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
  88 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
  89
  90 /*
  91  * For AArch64, map a given EL to an index in the banked_spsr array.
  92  * Note that this mapping and the AArch32 mapping defined in bank_number()
  93  * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
  94  * mandated mapping between each other.
  95  */
  96 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
  97 {
  98     static const unsigned int map[4] = {
  99         [1] = BANK_SVC, /* EL1.  */
 100         [2] = BANK_HYP, /* EL2.  */
 101         [3] = BANK_MON, /* EL3.  */
 102     };
 103     assert(el >= 1 && el <= 3);
 104     return map[el];
 105 }
 106
 107 /* Map CPU modes onto saved register banks.  */
 108 static inline int bank_number(int mode)
 109 {
 110     switch (mode) {
 111     case ARM_CPU_MODE_USR:
 112     case ARM_CPU_MODE_SYS:
 113         return BANK_USRSYS;
 114     case ARM_CPU_MODE_SVC:
 115         return BANK_SVC;
 116     case ARM_CPU_MODE_ABT:
 117         return BANK_ABT;
 118     case ARM_CPU_MODE_UND:
 119         return BANK_UND;
 120     case ARM_CPU_MODE_IRQ:
 121         return BANK_IRQ;
 122     case ARM_CPU_MODE_FIQ:
 123         return BANK_FIQ;
 124     case ARM_CPU_MODE_HYP:
 125         return BANK_HYP;
 126     case ARM_CPU_MODE_MON:
 127         return BANK_MON;
 128     }
 129     g_assert_not_reached();
 130 }
 131
 132 void switch_mode(CPUARMState *, int);
 133 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 134 void arm_translate_init(void);
 135
 136 enum arm_fprounding {
 137     FPROUNDING_TIEEVEN,
 138     FPROUNDING_POSINF,
 139     FPROUNDING_NEGINF,
 140     FPROUNDING_ZERO,
 141     FPROUNDING_TIEAWAY,
 142     FPROUNDING_ODD
 143 };
 144
 145 int arm_rmode_to_sf(int rmode);
 146
 147 static inline void aarch64_save_sp(CPUARMState *env, int el)
 148 {
 149     if (env->pstate & PSTATE_SP) {
 150         env->sp_el[el] = env->xregs[31];
 151     } else {
 152         env->sp_el[0] = env->xregs[31];
 153     }
 154 }
 155
 156 static inline void aarch64_restore_sp(CPUARMState *env, int el)
 157 {
 158     if (env->pstate & PSTATE_SP) {
 159         env->xregs[31] = env->sp_el[el];
 160     } else {
 161         env->xregs[31] = env->sp_el[0];
 162     }
 163 }
 164
 165 static inline void update_spsel(CPUARMState *env, uint32_t imm)
 166 {
 167     unsigned int cur_el = arm_current_el(env);
 168     /* Update PSTATE SPSel bit; this requires us to update the
 169      * working stack pointer in xregs[31].
 170      */
 171     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 172         return;
 173     }
 174     aarch64_save_sp(env, cur_el);
 175     env->pstate = deposit32(env->pstate, 0, 1, imm);
 176
 177     /* We rely on illegal updates to SPsel from EL0 to get trapped
 178      * at translation time.
 179      */
 180     assert(cur_el >= 1 && cur_el <= 3);
 181     aarch64_restore_sp(env, cur_el);
 182 }
 183
 184 /*
 185  * arm_pamax
 186  * @cpu: ARMCPU
 187  *
 188  * Returns the implementation defined bit-width of physical addresses.
 189  * The ARMv8 reference manuals refer to this as PAMax().
 190  */
 191 static inline unsigned int arm_pamax(ARMCPU *cpu)
 192 {
 193     static const unsigned int pamax_map[] = {
 194         [0] = 32,
 195         [1] = 36,
 196         [2] = 40,
 197         [3] = 42,
 198         [4] = 44,
 199         [5] = 48,
 200     };
 201     unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
 202
 203     /* id_aa64mmfr0 is a read-only register so values outside of the
 204      * supported mappings can be considered an implementation error.  */
 205     assert(parange < ARRAY_SIZE(pamax_map));
 206     return pamax_map[parange];
 207 }
 208
 209 /* Return true if extended addresses are enabled.
 210  * This is always the case if our translation regime is 64 bit,
 211  * but depends on TTBCR.EAE for 32 bit.
 212  */
 213 static inline bool extended_addresses_enabled(CPUARMState *env)
 214 {
 215     TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
 216     return arm_el_is_aa64(env, 1) ||
 217            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
 218 }
 219
 220 /* Valid Syndrome Register EC field values */
 221 enum arm_exception_class {
 222     EC_UNCATEGORIZED          = 0x00,
 223     EC_WFX_TRAP               = 0x01,
 224     EC_CP15RTTRAP             = 0x03,
 225     EC_CP15RRTTRAP            = 0x04,
 226     EC_CP14RTTRAP             = 0x05,
 227     EC_CP14DTTRAP             = 0x06,
 228     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 229     EC_FPIDTRAP               = 0x08,
 230     EC_CP14RRTTRAP            = 0x0c,
 231     EC_ILLEGALSTATE           = 0x0e,
 232     EC_AA32_SVC               = 0x11,
 233     EC_AA32_HVC               = 0x12,
 234     EC_AA32_SMC               = 0x13,
 235     EC_AA64_SVC               = 0x15,
 236     EC_AA64_HVC               = 0x16,
 237     EC_AA64_SMC               = 0x17,
 238     EC_SYSTEMREGISTERTRAP     = 0x18,
 239     EC_INSNABORT              = 0x20,
 240     EC_INSNABORT_SAME_EL      = 0x21,
 241     EC_PCALIGNMENT            = 0x22,
 242     EC_DATAABORT              = 0x24,
 243     EC_DATAABORT_SAME_EL      = 0x25,
 244     EC_SPALIGNMENT            = 0x26,
 245     EC_AA32_FPTRAP            = 0x28,
 246     EC_AA64_FPTRAP            = 0x2c,
 247     EC_SERROR                 = 0x2f,
 248     EC_BREAKPOINT             = 0x30,
 249     EC_BREAKPOINT_SAME_EL     = 0x31,
 250     EC_SOFTWARESTEP           = 0x32,
 251     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 252     EC_WATCHPOINT             = 0x34,
 253     EC_WATCHPOINT_SAME_EL     = 0x35,
 254     EC_AA32_BKPT              = 0x38,
 255     EC_VECTORCATCH            = 0x3a,
 256     EC_AA64_BKPT              = 0x3c,
 257 };
 258
 259 #define ARM_EL_EC_SHIFT 26
 260 #define ARM_EL_IL_SHIFT 25
 261 #define ARM_EL_ISV_SHIFT 24
 262 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 263 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
 264
 265 /* Utility functions for constructing various kinds of syndrome value.
 266  * Note that in general we follow the AArch64 syndrome values; in a
 267  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 268  * mode differs slightly, so if we ever implemented Hyp mode then the
 269  * syndrome value would need some massaging on exception entry.
 270  * (One example of this is that AArch64 defaults to IL bit set for
 271  * exceptions which don't specifically indicate information about the
 272  * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 273  */
 274 static inline uint32_t syn_uncategorized(void)
 275 {
 276     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 277 }
 278
 279 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 280 {
 281     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 282 }
 283
 284 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
 285 {
 286     return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 287 }
 288
 289 static inline uint32_t syn_aa64_smc(uint32_t imm16)
 290 {
 291     return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 292 }
 293
 294 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
 295 {
 296     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 297         | (is_16bit ? 0 : ARM_EL_IL);
 298 }
 299
 300 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
 301 {
 302     return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 303 }
 304
 305 static inline uint32_t syn_aa32_smc(void)
 306 {
 307     return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 308 }
 309
 310 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 311 {
 312     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 313 }
 314
 315 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
 316 {
 317     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 318         | (is_16bit ? 0 : ARM_EL_IL);
 319 }
 320
 321 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 322                                            int crn, int crm, int rt,
 323                                            int isread)
 324 {
 325     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 326         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 327         | (crm << 1) | isread;
 328 }
 329
 330 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 331                                         int crn, int crm, int rt, int isread,
 332                                         bool is_16bit)
 333 {
 334     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 335         | (is_16bit ? 0 : ARM_EL_IL)
 336         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 337         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 338 }
 339
 340 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 341                                         int crn, int crm, int rt, int isread,
 342                                         bool is_16bit)
 343 {
 344     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 345         | (is_16bit ? 0 : ARM_EL_IL)
 346         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 347         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 348 }
 349
 350 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 351                                          int rt, int rt2, int isread,
 352                                          bool is_16bit)
 353 {
 354     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 355         | (is_16bit ? 0 : ARM_EL_IL)
 356         | (cv << 24) | (cond << 20) | (opc1 << 16)
 357         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 358 }
 359
 360 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 361                                          int rt, int rt2, int isread,
 362                                          bool is_16bit)
 363 {
 364     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 365         | (is_16bit ? 0 : ARM_EL_IL)
 366         | (cv << 24) | (cond << 20) | (opc1 << 16)
 367         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 368 }
 369
 370 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
 371 {
 372     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 373         | (is_16bit ? 0 : ARM_EL_IL)
 374         | (cv << 24) | (cond << 20);
 375 }
 376
 377 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 378 {
 379     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 380         | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
 381 }
 382
 383 static inline uint32_t syn_data_abort_no_iss(int same_el,
 384                                              int ea, int cm, int s1ptw,
 385                                              int wnr, int fsc)
 386 {
 387     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 388            | ARM_EL_IL
 389            | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 390 }
 391
 392 static inline uint32_t syn_data_abort_with_iss(int same_el,
 393                                                int sas, int sse, int srt,
 394                                                int sf, int ar,
 395                                                int ea, int cm, int s1ptw,
 396                                                int wnr, int fsc,
 397                                                bool is_16bit)
 398 {
 399     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 400            | (is_16bit ? 0 : ARM_EL_IL)
 401            | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
 402            | (sf << 15) | (ar << 14)
 403            | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 404 }
 405
 406 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
 407 {
 408     return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 409         | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
 410 }
 411
 412 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
 413 {
 414     return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 415         | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
 416 }
 417
 418 static inline uint32_t syn_breakpoint(int same_el)
 419 {
 420     return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 421         | ARM_EL_IL | 0x22;
 422 }
 423
 424 static inline uint32_t syn_wfx(int cv, int cond, int ti)
 425 {
 426     return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
 427            (cv << 24) | (cond << 20) | ti;
 428 }
 429
 430 /* Update a QEMU watchpoint based on the information the guest has set in the
 431  * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 432  */
 433 void hw_watchpoint_update(ARMCPU *cpu, int n);
 434 /* Update the QEMU watchpoints for every guest watchpoint. This does a
 435  * complete delete-and-reinstate of the QEMU watchpoint list and so is
 436  * suitable for use after migration or on reset.
 437  */
 438 void hw_watchpoint_update_all(ARMCPU *cpu);
 439 /* Update a QEMU breakpoint based on the information the guest has set in the
 440  * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 441  */
 442 void hw_breakpoint_update(ARMCPU *cpu, int n);
 443 /* Update the QEMU breakpoints for every guest breakpoint. This does a
 444  * complete delete-and-reinstate of the QEMU breakpoint list and so is
 445  * suitable for use after migration or on reset.
 446  */
 447 void hw_breakpoint_update_all(ARMCPU *cpu);
 448
 449 /* Callback function for checking if a watchpoint should trigger. */
 450 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 451
 452 /* Adjust addresses (in BE32 mode) before testing against watchpoint
 453  * addresses.
 454  */
 455 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
 456
 457 /* Callback function for when a watchpoint or breakpoint triggers. */
 458 void arm_debug_excp_handler(CPUState *cs);
 459
 460 #ifdef CONFIG_USER_ONLY
 461 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 462 {
 463     return false;
 464 }
 465 #else
 466 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
 467 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
 468 /* Actually handle a PSCI call */
 469 void arm_handle_psci_call(ARMCPU *cpu);
 470 #endif
 471
 472 /**
 473  * arm_clear_exclusive: clear the exclusive monitor
 474  * @env: CPU env
 475  * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
 476  */
 477 static inline void arm_clear_exclusive(CPUARMState *env)
 478 {
 479     env->exclusive_addr = -1;
 480 }
 481
 482 /**
 483  * ARMMMUFaultInfo: Information describing an ARM MMU Fault
 484  * @s2addr: Address that caused a fault at stage 2
 485  * @stage2: True if we faulted at stage 2
 486  * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
 487  * @ea: True if we should set the EA (external abort type) bit in syndrome
 488  */
 489 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 490 struct ARMMMUFaultInfo {
 491     target_ulong s2addr;
 492     bool stage2;
 493     bool s1ptw;
 494     bool ea;
 495 };
 496
 497 /* Do a page table walk and add page to TLB if possible */
 498 bool arm_tlb_fill(CPUState *cpu, vaddr address,
 499                   MMUAccessType access_type, int mmu_idx,
 500                   uint32_t *fsr, ARMMMUFaultInfo *fi);
 501
 502 /* Return true if the stage 1 translation regime is using LPAE format page
 503  * tables */
 504 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
 505
 506 /* Raise a data fault alignment exception for the specified virtual address */
 507 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
 508                                  MMUAccessType access_type,
 509                                  int mmu_idx, uintptr_t retaddr);
 510
 511 /* arm_cpu_do_transaction_failed: handle a memory system error response
 512  * (eg "no device/memory present at address") by raising an external abort
 513  * exception
 514  */
 515 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 516                                    vaddr addr, unsigned size,
 517                                    MMUAccessType access_type,
 518                                    int mmu_idx, MemTxAttrs attrs,
 519                                    MemTxResult response, uintptr_t retaddr);
 520
 521 /* Call the EL change hook if one has been registered */
 522 static inline void arm_call_el_change_hook(ARMCPU *cpu)
 523 {
 524     if (cpu->el_change_hook) {
 525         cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
 526     }
 527 }
 528
 529 /* Return true if this address translation regime is secure */
 530 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
 531 {
 532     switch (mmu_idx) {
 533     case ARMMMUIdx_S12NSE0:
 534     case ARMMMUIdx_S12NSE1:
 535     case ARMMMUIdx_S1NSE0:
 536     case ARMMMUIdx_S1NSE1:
 537     case ARMMMUIdx_S1E2:
 538     case ARMMMUIdx_S2NS:
 539     case ARMMMUIdx_MPriv:
 540     case ARMMMUIdx_MNegPri:
 541     case ARMMMUIdx_MUser:
 542         return false;
 543     case ARMMMUIdx_S1E3:
 544     case ARMMMUIdx_S1SE0:
 545     case ARMMMUIdx_S1SE1:
 546     case ARMMMUIdx_MSPriv:
 547     case ARMMMUIdx_MSNegPri:
 548     case ARMMMUIdx_MSUser:
 549         return true;
 550     default:
 551         g_assert_not_reached();
 552     }
 553 }
 554
 555 #endif