target/arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target/arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 #include "hw/registerfields.h"
  29
  30 /* register banks for CPU modes */
  31 #define BANK_USRSYS 0
  32 #define BANK_SVC    1
  33 #define BANK_ABT    2
  34 #define BANK_UND    3
  35 #define BANK_IRQ    4
  36 #define BANK_FIQ    5
  37 #define BANK_HYP    6
  38 #define BANK_MON    7
  39
  40 static inline bool excp_is_internal(int excp)
  41 {
  42     /* Return true if this exception number represents a QEMU-internal
  43      * exception that will not be passed to the guest.
  44      */
  45     return excp == EXCP_INTERRUPT
  46         || excp == EXCP_HLT
  47         || excp == EXCP_DEBUG
  48         || excp == EXCP_HALTED
  49         || excp == EXCP_EXCEPTION_EXIT
  50         || excp == EXCP_KERNEL_TRAP
  51         || excp == EXCP_SEMIHOST;
  52 }
  53
  54 /* Scale factor for generic timers, ie number of ns per tick.
  55  * This gives a 62.5MHz timer.
  56  */
  57 #define GTIMER_SCALE 16
  58
  59 /* Bit definitions for the v7M CONTROL register */
  60 FIELD(V7M_CONTROL, NPRIV, 0, 1)
  61 FIELD(V7M_CONTROL, SPSEL, 1, 1)
  62 FIELD(V7M_CONTROL, FPCA, 2, 1)
  63 FIELD(V7M_CONTROL, SFPA, 3, 1)
  64
  65 /* Bit definitions for v7M exception return payload */
  66 FIELD(V7M_EXCRET, ES, 0, 1)
  67 FIELD(V7M_EXCRET, RES0, 1, 1)
  68 FIELD(V7M_EXCRET, SPSEL, 2, 1)
  69 FIELD(V7M_EXCRET, MODE, 3, 1)
  70 FIELD(V7M_EXCRET, FTYPE, 4, 1)
  71 FIELD(V7M_EXCRET, DCRS, 5, 1)
  72 FIELD(V7M_EXCRET, S, 6, 1)
  73 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
  74
  75 /* Minimum value which is a magic number for exception return */
  76 #define EXC_RETURN_MIN_MAGIC 0xff000000
  77 /* Minimum number which is a magic number for function or exception return
  78  * when using v8M security extension
  79  */
  80 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
  81
  82 /* We use a few fake FSR values for internal purposes in M profile.
  83  * M profile cores don't have A/R format FSRs, but currently our
  84  * get_phys_addr() code assumes A/R profile and reports failures via
  85  * an A/R format FSR value. We then translate that into the proper
  86  * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
  87  * Mostly the FSR values we use for this are those defined for v7PMSA,
  88  * since we share some of that codepath. A few kinds of fault are
  89  * only for M profile and have no A/R equivalent, though, so we have
  90  * to pick a value from the reserved range (which we never otherwise
  91  * generate) to use for these.
  92  * These values will never be visible to the guest.
  93  */
  94 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
  95 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
  96
  97 /**
  98  * raise_exception: Raise the specified exception.
  99  * Raise a guest exception with the specified value, syndrome register
 100  * and target exception level. This should be called from helper functions,
 101  * and never returns because we will longjump back up to the CPU main loop.
 102  */
 103 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
 104                                    uint32_t syndrome, uint32_t target_el);
 105
 106 /*
 107  * For AArch64, map a given EL to an index in the banked_spsr array.
 108  * Note that this mapping and the AArch32 mapping defined in bank_number()
 109  * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
 110  * mandated mapping between each other.
 111  */
 112 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
 113 {
 114     static const unsigned int map[4] = {
 115         [1] = BANK_SVC, /* EL1.  */
 116         [2] = BANK_HYP, /* EL2.  */
 117         [3] = BANK_MON, /* EL3.  */
 118     };
 119     assert(el >= 1 && el <= 3);
 120     return map[el];
 121 }
 122
 123 /* Map CPU modes onto saved register banks.  */
 124 static inline int bank_number(int mode)
 125 {
 126     switch (mode) {
 127     case ARM_CPU_MODE_USR:
 128     case ARM_CPU_MODE_SYS:
 129         return BANK_USRSYS;
 130     case ARM_CPU_MODE_SVC:
 131         return BANK_SVC;
 132     case ARM_CPU_MODE_ABT:
 133         return BANK_ABT;
 134     case ARM_CPU_MODE_UND:
 135         return BANK_UND;
 136     case ARM_CPU_MODE_IRQ:
 137         return BANK_IRQ;
 138     case ARM_CPU_MODE_FIQ:
 139         return BANK_FIQ;
 140     case ARM_CPU_MODE_HYP:
 141         return BANK_HYP;
 142     case ARM_CPU_MODE_MON:
 143         return BANK_MON;
 144     }
 145     g_assert_not_reached();
 146 }
 147
 148 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 149 void arm_translate_init(void);
 150
 151 enum arm_fprounding {
 152     FPROUNDING_TIEEVEN,
 153     FPROUNDING_POSINF,
 154     FPROUNDING_NEGINF,
 155     FPROUNDING_ZERO,
 156     FPROUNDING_TIEAWAY,
 157     FPROUNDING_ODD
 158 };
 159
 160 int arm_rmode_to_sf(int rmode);
 161
 162 static inline void aarch64_save_sp(CPUARMState *env, int el)
 163 {
 164     if (env->pstate & PSTATE_SP) {
 165         env->sp_el[el] = env->xregs[31];
 166     } else {
 167         env->sp_el[0] = env->xregs[31];
 168     }
 169 }
 170
 171 static inline void aarch64_restore_sp(CPUARMState *env, int el)
 172 {
 173     if (env->pstate & PSTATE_SP) {
 174         env->xregs[31] = env->sp_el[el];
 175     } else {
 176         env->xregs[31] = env->sp_el[0];
 177     }
 178 }
 179
 180 static inline void update_spsel(CPUARMState *env, uint32_t imm)
 181 {
 182     unsigned int cur_el = arm_current_el(env);
 183     /* Update PSTATE SPSel bit; this requires us to update the
 184      * working stack pointer in xregs[31].
 185      */
 186     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 187         return;
 188     }
 189     aarch64_save_sp(env, cur_el);
 190     env->pstate = deposit32(env->pstate, 0, 1, imm);
 191
 192     /* We rely on illegal updates to SPsel from EL0 to get trapped
 193      * at translation time.
 194      */
 195     assert(cur_el >= 1 && cur_el <= 3);
 196     aarch64_restore_sp(env, cur_el);
 197 }
 198
 199 /*
 200  * arm_pamax
 201  * @cpu: ARMCPU
 202  *
 203  * Returns the implementation defined bit-width of physical addresses.
 204  * The ARMv8 reference manuals refer to this as PAMax().
 205  */
 206 static inline unsigned int arm_pamax(ARMCPU *cpu)
 207 {
 208     static const unsigned int pamax_map[] = {
 209         [0] = 32,
 210         [1] = 36,
 211         [2] = 40,
 212         [3] = 42,
 213         [4] = 44,
 214         [5] = 48,
 215     };
 216     unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
 217
 218     /* id_aa64mmfr0 is a read-only register so values outside of the
 219      * supported mappings can be considered an implementation error.  */
 220     assert(parange < ARRAY_SIZE(pamax_map));
 221     return pamax_map[parange];
 222 }
 223
 224 /* Return true if extended addresses are enabled.
 225  * This is always the case if our translation regime is 64 bit,
 226  * but depends on TTBCR.EAE for 32 bit.
 227  */
 228 static inline bool extended_addresses_enabled(CPUARMState *env)
 229 {
 230     TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
 231     return arm_el_is_aa64(env, 1) ||
 232            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
 233 }
 234
 235 /* Valid Syndrome Register EC field values */
 236 enum arm_exception_class {
 237     EC_UNCATEGORIZED          = 0x00,
 238     EC_WFX_TRAP               = 0x01,
 239     EC_CP15RTTRAP             = 0x03,
 240     EC_CP15RRTTRAP            = 0x04,
 241     EC_CP14RTTRAP             = 0x05,
 242     EC_CP14DTTRAP             = 0x06,
 243     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 244     EC_FPIDTRAP               = 0x08,
 245     EC_CP14RRTTRAP            = 0x0c,
 246     EC_ILLEGALSTATE           = 0x0e,
 247     EC_AA32_SVC               = 0x11,
 248     EC_AA32_HVC               = 0x12,
 249     EC_AA32_SMC               = 0x13,
 250     EC_AA64_SVC               = 0x15,
 251     EC_AA64_HVC               = 0x16,
 252     EC_AA64_SMC               = 0x17,
 253     EC_SYSTEMREGISTERTRAP     = 0x18,
 254     EC_SVEACCESSTRAP          = 0x19,
 255     EC_INSNABORT              = 0x20,
 256     EC_INSNABORT_SAME_EL      = 0x21,
 257     EC_PCALIGNMENT            = 0x22,
 258     EC_DATAABORT              = 0x24,
 259     EC_DATAABORT_SAME_EL      = 0x25,
 260     EC_SPALIGNMENT            = 0x26,
 261     EC_AA32_FPTRAP            = 0x28,
 262     EC_AA64_FPTRAP            = 0x2c,
 263     EC_SERROR                 = 0x2f,
 264     EC_BREAKPOINT             = 0x30,
 265     EC_BREAKPOINT_SAME_EL     = 0x31,
 266     EC_SOFTWARESTEP           = 0x32,
 267     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 268     EC_WATCHPOINT             = 0x34,
 269     EC_WATCHPOINT_SAME_EL     = 0x35,
 270     EC_AA32_BKPT              = 0x38,
 271     EC_VECTORCATCH            = 0x3a,
 272     EC_AA64_BKPT              = 0x3c,
 273 };
 274
 275 #define ARM_EL_EC_SHIFT 26
 276 #define ARM_EL_IL_SHIFT 25
 277 #define ARM_EL_ISV_SHIFT 24
 278 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 279 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
 280
 281 static inline uint32_t syn_get_ec(uint32_t syn)
 282 {
 283     return syn >> ARM_EL_EC_SHIFT;
 284 }
 285
 286 /* Utility functions for constructing various kinds of syndrome value.
 287  * Note that in general we follow the AArch64 syndrome values; in a
 288  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 289  * mode differs slightly, and we fix this up when populating HSR in
 290  * arm_cpu_do_interrupt_aarch32_hyp().
 291  * The exception is FP/SIMD access traps -- these report extra information
 292  * when taking an exception to AArch32. For those we include the extra coproc
 293  * and TA fields, and mask them out when taking the exception to AArch64.
 294  */
 295 static inline uint32_t syn_uncategorized(void)
 296 {
 297     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 298 }
 299
 300 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 301 {
 302     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 303 }
 304
 305 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
 306 {
 307     return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 308 }
 309
 310 static inline uint32_t syn_aa64_smc(uint32_t imm16)
 311 {
 312     return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 313 }
 314
 315 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
 316 {
 317     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 318         | (is_16bit ? 0 : ARM_EL_IL);
 319 }
 320
 321 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
 322 {
 323     return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 324 }
 325
 326 static inline uint32_t syn_aa32_smc(void)
 327 {
 328     return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 329 }
 330
 331 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 332 {
 333     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 334 }
 335
 336 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
 337 {
 338     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 339         | (is_16bit ? 0 : ARM_EL_IL);
 340 }
 341
 342 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 343                                            int crn, int crm, int rt,
 344                                            int isread)
 345 {
 346     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 347         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 348         | (crm << 1) | isread;
 349 }
 350
 351 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 352                                         int crn, int crm, int rt, int isread,
 353                                         bool is_16bit)
 354 {
 355     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 356         | (is_16bit ? 0 : ARM_EL_IL)
 357         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 358         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 359 }
 360
 361 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 362                                         int crn, int crm, int rt, int isread,
 363                                         bool is_16bit)
 364 {
 365     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 366         | (is_16bit ? 0 : ARM_EL_IL)
 367         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 368         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 369 }
 370
 371 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 372                                          int rt, int rt2, int isread,
 373                                          bool is_16bit)
 374 {
 375     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 376         | (is_16bit ? 0 : ARM_EL_IL)
 377         | (cv << 24) | (cond << 20) | (opc1 << 16)
 378         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 379 }
 380
 381 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 382                                          int rt, int rt2, int isread,
 383                                          bool is_16bit)
 384 {
 385     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 386         | (is_16bit ? 0 : ARM_EL_IL)
 387         | (cv << 24) | (cond << 20) | (opc1 << 16)
 388         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 389 }
 390
 391 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
 392 {
 393     /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
 394     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 395         | (is_16bit ? 0 : ARM_EL_IL)
 396         | (cv << 24) | (cond << 20) | 0xa;
 397 }
 398
 399 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
 400 {
 401     /* AArch32 SIMD trap: TA == 1 coproc == 0 */
 402     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 403         | (is_16bit ? 0 : ARM_EL_IL)
 404         | (cv << 24) | (cond << 20) | (1 << 5);
 405 }
 406
 407 static inline uint32_t syn_sve_access_trap(void)
 408 {
 409     return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
 410 }
 411
 412 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 413 {
 414     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 415         | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
 416 }
 417
 418 static inline uint32_t syn_data_abort_no_iss(int same_el,
 419                                              int ea, int cm, int s1ptw,
 420                                              int wnr, int fsc)
 421 {
 422     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 423            | ARM_EL_IL
 424            | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 425 }
 426
 427 static inline uint32_t syn_data_abort_with_iss(int same_el,
 428                                                int sas, int sse, int srt,
 429                                                int sf, int ar,
 430                                                int ea, int cm, int s1ptw,
 431                                                int wnr, int fsc,
 432                                                bool is_16bit)
 433 {
 434     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 435            | (is_16bit ? 0 : ARM_EL_IL)
 436            | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
 437            | (sf << 15) | (ar << 14)
 438            | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 439 }
 440
 441 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
 442 {
 443     return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 444         | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
 445 }
 446
 447 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
 448 {
 449     return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 450         | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
 451 }
 452
 453 static inline uint32_t syn_breakpoint(int same_el)
 454 {
 455     return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 456         | ARM_EL_IL | 0x22;
 457 }
 458
 459 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
 460 {
 461     return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
 462            (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
 463            (cv << 24) | (cond << 20) | ti;
 464 }
 465
 466 /* Update a QEMU watchpoint based on the information the guest has set in the
 467  * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 468  */
 469 void hw_watchpoint_update(ARMCPU *cpu, int n);
 470 /* Update the QEMU watchpoints for every guest watchpoint. This does a
 471  * complete delete-and-reinstate of the QEMU watchpoint list and so is
 472  * suitable for use after migration or on reset.
 473  */
 474 void hw_watchpoint_update_all(ARMCPU *cpu);
 475 /* Update a QEMU breakpoint based on the information the guest has set in the
 476  * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 477  */
 478 void hw_breakpoint_update(ARMCPU *cpu, int n);
 479 /* Update the QEMU breakpoints for every guest breakpoint. This does a
 480  * complete delete-and-reinstate of the QEMU breakpoint list and so is
 481  * suitable for use after migration or on reset.
 482  */
 483 void hw_breakpoint_update_all(ARMCPU *cpu);
 484
 485 /* Callback function for checking if a watchpoint should trigger. */
 486 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 487
 488 /* Adjust addresses (in BE32 mode) before testing against watchpoint
 489  * addresses.
 490  */
 491 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
 492
 493 /* Callback function for when a watchpoint or breakpoint triggers. */
 494 void arm_debug_excp_handler(CPUState *cs);
 495
 496 #ifdef CONFIG_USER_ONLY
 497 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 498 {
 499     return false;
 500 }
 501 #else
 502 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
 503 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
 504 /* Actually handle a PSCI call */
 505 void arm_handle_psci_call(ARMCPU *cpu);
 506 #endif
 507
 508 /**
 509  * arm_clear_exclusive: clear the exclusive monitor
 510  * @env: CPU env
 511  * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
 512  */
 513 static inline void arm_clear_exclusive(CPUARMState *env)
 514 {
 515     env->exclusive_addr = -1;
 516 }
 517
 518 /**
 519  * ARMFaultType: type of an ARM MMU fault
 520  * This corresponds to the v8A pseudocode's Fault enumeration,
 521  * with extensions for QEMU internal conditions.
 522  */
 523 typedef enum ARMFaultType {
 524     ARMFault_None,
 525     ARMFault_AccessFlag,
 526     ARMFault_Alignment,
 527     ARMFault_Background,
 528     ARMFault_Domain,
 529     ARMFault_Permission,
 530     ARMFault_Translation,
 531     ARMFault_AddressSize,
 532     ARMFault_SyncExternal,
 533     ARMFault_SyncExternalOnWalk,
 534     ARMFault_SyncParity,
 535     ARMFault_SyncParityOnWalk,
 536     ARMFault_AsyncParity,
 537     ARMFault_AsyncExternal,
 538     ARMFault_Debug,
 539     ARMFault_TLBConflict,
 540     ARMFault_Lockdown,
 541     ARMFault_Exclusive,
 542     ARMFault_ICacheMaint,
 543     ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */
 544     ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
 545 } ARMFaultType;
 546
 547 /**
 548  * ARMMMUFaultInfo: Information describing an ARM MMU Fault
 549  * @type: Type of fault
 550  * @level: Table walk level (for translation, access flag and permission faults)
 551  * @domain: Domain of the fault address (for non-LPAE CPUs only)
 552  * @s2addr: Address that caused a fault at stage 2
 553  * @stage2: True if we faulted at stage 2
 554  * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
 555  * @ea: True if we should set the EA (external abort type) bit in syndrome
 556  */
 557 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 558 struct ARMMMUFaultInfo {
 559     ARMFaultType type;
 560     target_ulong s2addr;
 561     int level;
 562     int domain;
 563     bool stage2;
 564     bool s1ptw;
 565     bool ea;
 566 };
 567
 568 /**
 569  * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
 570  * Compare pseudocode EncodeSDFSC(), though unlike that function
 571  * we set up a whole FSR-format code including domain field and
 572  * putting the high bit of the FSC into bit 10.
 573  */
 574 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi)
 575 {
 576     uint32_t fsc;
 577
 578     switch (fi->type) {
 579     case ARMFault_None:
 580         return 0;
 581     case ARMFault_AccessFlag:
 582         fsc = fi->level == 1 ? 0x3 : 0x6;
 583         break;
 584     case ARMFault_Alignment:
 585         fsc = 0x1;
 586         break;
 587     case ARMFault_Permission:
 588         fsc = fi->level == 1 ? 0xd : 0xf;
 589         break;
 590     case ARMFault_Domain:
 591         fsc = fi->level == 1 ? 0x9 : 0xb;
 592         break;
 593     case ARMFault_Translation:
 594         fsc = fi->level == 1 ? 0x5 : 0x7;
 595         break;
 596     case ARMFault_SyncExternal:
 597         fsc = 0x8 | (fi->ea << 12);
 598         break;
 599     case ARMFault_SyncExternalOnWalk:
 600         fsc = fi->level == 1 ? 0xc : 0xe;
 601         fsc |= (fi->ea << 12);
 602         break;
 603     case ARMFault_SyncParity:
 604         fsc = 0x409;
 605         break;
 606     case ARMFault_SyncParityOnWalk:
 607         fsc = fi->level == 1 ? 0x40c : 0x40e;
 608         break;
 609     case ARMFault_AsyncParity:
 610         fsc = 0x408;
 611         break;
 612     case ARMFault_AsyncExternal:
 613         fsc = 0x406 | (fi->ea << 12);
 614         break;
 615     case ARMFault_Debug:
 616         fsc = 0x2;
 617         break;
 618     case ARMFault_TLBConflict:
 619         fsc = 0x400;
 620         break;
 621     case ARMFault_Lockdown:
 622         fsc = 0x404;
 623         break;
 624     case ARMFault_Exclusive:
 625         fsc = 0x405;
 626         break;
 627     case ARMFault_ICacheMaint:
 628         fsc = 0x4;
 629         break;
 630     case ARMFault_Background:
 631         fsc = 0x0;
 632         break;
 633     case ARMFault_QEMU_NSCExec:
 634         fsc = M_FAKE_FSR_NSC_EXEC;
 635         break;
 636     case ARMFault_QEMU_SFault:
 637         fsc = M_FAKE_FSR_SFAULT;
 638         break;
 639     default:
 640         /* Other faults can't occur in a context that requires a
 641          * short-format status code.
 642          */
 643         g_assert_not_reached();
 644     }
 645
 646     fsc |= (fi->domain << 4);
 647     return fsc;
 648 }
 649
 650 /**
 651  * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
 652  * Compare pseudocode EncodeLDFSC(), though unlike that function
 653  * we fill in also the LPAE bit 9 of a DFSR format.
 654  */
 655 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
 656 {
 657     uint32_t fsc;
 658
 659     switch (fi->type) {
 660     case ARMFault_None:
 661         return 0;
 662     case ARMFault_AddressSize:
 663         fsc = fi->level & 3;
 664         break;
 665     case ARMFault_AccessFlag:
 666         fsc = (fi->level & 3) | (0x2 << 2);
 667         break;
 668     case ARMFault_Permission:
 669         fsc = (fi->level & 3) | (0x3 << 2);
 670         break;
 671     case ARMFault_Translation:
 672         fsc = (fi->level & 3) | (0x1 << 2);
 673         break;
 674     case ARMFault_SyncExternal:
 675         fsc = 0x10 | (fi->ea << 12);
 676         break;
 677     case ARMFault_SyncExternalOnWalk:
 678         fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12);
 679         break;
 680     case ARMFault_SyncParity:
 681         fsc = 0x18;
 682         break;
 683     case ARMFault_SyncParityOnWalk:
 684         fsc = (fi->level & 3) | (0x7 << 2);
 685         break;
 686     case ARMFault_AsyncParity:
 687         fsc = 0x19;
 688         break;
 689     case ARMFault_AsyncExternal:
 690         fsc = 0x11 | (fi->ea << 12);
 691         break;
 692     case ARMFault_Alignment:
 693         fsc = 0x21;
 694         break;
 695     case ARMFault_Debug:
 696         fsc = 0x22;
 697         break;
 698     case ARMFault_TLBConflict:
 699         fsc = 0x30;
 700         break;
 701     case ARMFault_Lockdown:
 702         fsc = 0x34;
 703         break;
 704     case ARMFault_Exclusive:
 705         fsc = 0x35;
 706         break;
 707     default:
 708         /* Other faults can't occur in a context that requires a
 709          * long-format status code.
 710          */
 711         g_assert_not_reached();
 712     }
 713
 714     fsc |= 1 << 9;
 715     return fsc;
 716 }
 717
 718 static inline bool arm_extabort_type(MemTxResult result)
 719 {
 720     /* The EA bit in syndromes and fault status registers is an
 721      * IMPDEF classification of external aborts. ARM implementations
 722      * usually use this to indicate AXI bus Decode error (0) or
 723      * Slave error (1); in QEMU we follow that.
 724      */
 725     return result != MEMTX_DECODE_ERROR;
 726 }
 727
 728 /* Do a page table walk and add page to TLB if possible */
 729 bool arm_tlb_fill(CPUState *cpu, vaddr address,
 730                   MMUAccessType access_type, int mmu_idx,
 731                   ARMMMUFaultInfo *fi);
 732
 733 /* Return true if the stage 1 translation regime is using LPAE format page
 734  * tables */
 735 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
 736
 737 /* Raise a data fault alignment exception for the specified virtual address */
 738 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
 739                                  MMUAccessType access_type,
 740                                  int mmu_idx, uintptr_t retaddr);
 741
 742 /* arm_cpu_do_transaction_failed: handle a memory system error response
 743  * (eg "no device/memory present at address") by raising an external abort
 744  * exception
 745  */
 746 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 747                                    vaddr addr, unsigned size,
 748                                    MMUAccessType access_type,
 749                                    int mmu_idx, MemTxAttrs attrs,
 750                                    MemTxResult response, uintptr_t retaddr);
 751
 752 /* Call any registered EL change hooks */
 753 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
 754 {
 755     ARMELChangeHook *hook, *next;
 756     QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
 757         hook->hook(cpu, hook->opaque);
 758     }
 759 }
 760 static inline void arm_call_el_change_hook(ARMCPU *cpu)
 761 {
 762     ARMELChangeHook *hook, *next;
 763     QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
 764         hook->hook(cpu, hook->opaque);
 765     }
 766 }
 767
 768 /* Return true if this address translation regime is secure */
 769 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
 770 {
 771     switch (mmu_idx) {
 772     case ARMMMUIdx_S12NSE0:
 773     case ARMMMUIdx_S12NSE1:
 774     case ARMMMUIdx_S1NSE0:
 775     case ARMMMUIdx_S1NSE1:
 776     case ARMMMUIdx_S1E2:
 777     case ARMMMUIdx_S2NS:
 778     case ARMMMUIdx_MPrivNegPri:
 779     case ARMMMUIdx_MUserNegPri:
 780     case ARMMMUIdx_MPriv:
 781     case ARMMMUIdx_MUser:
 782         return false;
 783     case ARMMMUIdx_S1E3:
 784     case ARMMMUIdx_S1SE0:
 785     case ARMMMUIdx_S1SE1:
 786     case ARMMMUIdx_MSPrivNegPri:
 787     case ARMMMUIdx_MSUserNegPri:
 788     case ARMMMUIdx_MSPriv:
 789     case ARMMMUIdx_MSUser:
 790         return true;
 791     default:
 792         g_assert_not_reached();
 793     }
 794 }
 795
 796 /* Return the FSR value for a debug exception (watchpoint, hardware
 797  * breakpoint or BKPT insn) targeting the specified exception level.
 798  */
 799 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env)
 800 {
 801     ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
 802     int target_el = arm_debug_target_el(env);
 803     bool using_lpae = false;
 804
 805     if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
 806         using_lpae = true;
 807     } else {
 808         if (arm_feature(env, ARM_FEATURE_LPAE) &&
 809             (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
 810             using_lpae = true;
 811         }
 812     }
 813
 814     if (using_lpae) {
 815         return arm_fi_to_lfsc(&fi);
 816     } else {
 817         return arm_fi_to_sfsc(&fi);
 818     }
 819 }
 820
 821 /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
 822  * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
 823  */
 824 #define MEMOPIDX_SHIFT  8
 825
 826 /**
 827  * v7m_using_psp: Return true if using process stack pointer
 828  * Return true if the CPU is currently using the process stack
 829  * pointer, or false if it is using the main stack pointer.
 830  */
 831 static inline bool v7m_using_psp(CPUARMState *env)
 832 {
 833     /* Handler mode always uses the main stack; for thread mode
 834      * the CONTROL.SPSEL bit determines the answer.
 835      * Note that in v7M it is not possible to be in Handler mode with
 836      * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
 837      */
 838     return !arm_v7m_is_handler_mode(env) &&
 839         env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
 840 }
 841
 842 /**
 843  * v7m_sp_limit: Return SP limit for current CPU state
 844  * Return the SP limit value for the current CPU security state
 845  * and stack pointer.
 846  */
 847 static inline uint32_t v7m_sp_limit(CPUARMState *env)
 848 {
 849     if (v7m_using_psp(env)) {
 850         return env->v7m.psplim[env->v7m.secure];
 851     } else {
 852         return env->v7m.msplim[env->v7m.secure];
 853     }
 854 }
 855
 856 /**
 857  * aarch32_mode_name(): Return name of the AArch32 CPU mode
 858  * @psr: Program Status Register indicating CPU mode
 859  *
 860  * Returns, for debug logging purposes, a printable representation
 861  * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
 862  * the low bits of the specified PSR.
 863  */
 864 static inline const char *aarch32_mode_name(uint32_t psr)
 865 {
 866     static const char cpu_mode_names[16][4] = {
 867         "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
 868         "???", "???", "hyp", "und", "???", "???", "???", "sys"
 869     };
 870
 871     return cpu_mode_names[psr & 0xf];
 872 }
 873
 874 #endif