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1 /*
2 * ARM implementation of KVM hooks
3 *
4 * Copyright Christoffer Dall 2009-2010
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 *
9 */
10
11 #include "qemu/osdep.h"
12 #include <sys/ioctl.h>
13
14 #include <linux/kvm.h>
15
16 #include "qemu-common.h"
17 #include "qemu/timer.h"
18 #include "qemu/error-report.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/kvm.h"
21 #include "kvm_arm.h"
22 #include "cpu.h"
23 #include "internals.h"
24 #include "hw/arm/arm.h"
25 #include "exec/memattrs.h"
26 #include "exec/address-spaces.h"
27 #include "hw/boards.h"
28 #include "qemu/log.h"
29
30 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
31 KVM_CAP_LAST_INFO
32 };
33
34 static bool cap_has_mp_state;
35
36 static ARMHostCPUFeatures arm_host_cpu_features;
37
38 int kvm_arm_vcpu_init(CPUState *cs)
39 {
40 ARMCPU *cpu = ARM_CPU(cs);
41 struct kvm_vcpu_init init;
42
43 init.target = cpu->kvm_target;
44 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features));
45
46 return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
47 }
48
49 bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
50 int *fdarray,
51 struct kvm_vcpu_init *init)
52 {
53 int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
54
55 kvmfd = qemu_open("/dev/kvm", O_RDWR);
56 if (kvmfd < 0) {
57 goto err;
58 }
59 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0);
60 if (vmfd < 0) {
61 goto err;
62 }
63 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
64 if (cpufd < 0) {
65 goto err;
66 }
67
68 if (!init) {
69 /* Caller doesn't want the VCPU to be initialized, so skip it */
70 goto finish;
71 }
72
73 ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
74 if (ret >= 0) {
75 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
76 if (ret < 0) {
77 goto err;
78 }
79 } else if (cpus_to_try) {
80 /* Old kernel which doesn't know about the
81 * PREFERRED_TARGET ioctl: we know it will only support
82 * creating one kind of guest CPU which is its preferred
83 * CPU type.
84 */
85 while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
86 init->target = *cpus_to_try++;
87 memset(init->features, 0, sizeof(init->features));
88 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
89 if (ret >= 0) {
90 break;
91 }
92 }
93 if (ret < 0) {
94 goto err;
95 }
96 } else {
97 /* Treat a NULL cpus_to_try argument the same as an empty
98 * list, which means we will fail the call since this must
99 * be an old kernel which doesn't support PREFERRED_TARGET.
100 */
101 goto err;
102 }
103
104 finish:
105 fdarray[0] = kvmfd;
106 fdarray[1] = vmfd;
107 fdarray[2] = cpufd;
108
109 return true;
110
111 err:
112 if (cpufd >= 0) {
113 close(cpufd);
114 }
115 if (vmfd >= 0) {
116 close(vmfd);
117 }
118 if (kvmfd >= 0) {
119 close(kvmfd);
120 }
121
122 return false;
123 }
124
125 void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
126 {
127 int i;
128
129 for (i = 2; i >= 0; i--) {
130 close(fdarray[i]);
131 }
132 }
133
134 void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
135 {
136 CPUARMState *env = &cpu->env;
137
138 if (!arm_host_cpu_features.dtb_compatible) {
139 if (!kvm_enabled() ||
140 !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) {
141 /* We can't report this error yet, so flag that we need to
142 * in arm_cpu_realizefn().
143 */
144 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
145 cpu->host_cpu_probe_failed = true;
146 return;
147 }
148 }
149
150 cpu->kvm_target = arm_host_cpu_features.target;
151 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
152 env->features = arm_host_cpu_features.features;
153 }
154
155 static void kvm_arm_host_cpu_initfn(Object *obj)
156 {
157 ARMCPU *cpu = ARM_CPU(obj);
158
159 kvm_arm_set_cpu_features_from_host(cpu);
160 }
161
162 static const TypeInfo host_arm_cpu_type_info = {
163 .name = TYPE_ARM_HOST_CPU,
164 #ifdef TARGET_AARCH64
165 .parent = TYPE_AARCH64_CPU,
166 #else
167 .parent = TYPE_ARM_CPU,
168 #endif
169 .instance_init = kvm_arm_host_cpu_initfn,
170 };
171
172 int kvm_arch_init(MachineState *ms, KVMState *s)
173 {
174 /* For ARM interrupt delivery is always asynchronous,
175 * whether we are using an in-kernel VGIC or not.
176 */
177 kvm_async_interrupts_allowed = true;
178
179 /*
180 * PSCI wakes up secondary cores, so we always need to
181 * have vCPUs waiting in kernel space
182 */
183 kvm_halt_in_kernel_allowed = true;
184
185 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
186
187 type_register_static(&host_arm_cpu_type_info);
188
189 return 0;
190 }
191
192 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
193 {
194 return cpu->cpu_index;
195 }
196
197 /* We track all the KVM devices which need their memory addresses
198 * passing to the kernel in a list of these structures.
199 * When board init is complete we run through the list and
200 * tell the kernel the base addresses of the memory regions.
201 * We use a MemoryListener to track mapping and unmapping of
202 * the regions during board creation, so the board models don't
203 * need to do anything special for the KVM case.
204 */
205 typedef struct KVMDevice {
206 struct kvm_arm_device_addr kda;
207 struct kvm_device_attr kdattr;
208 MemoryRegion *mr;
209 QSLIST_ENTRY(KVMDevice) entries;
210 int dev_fd;
211 } KVMDevice;
212
213 static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;
214
215 static void kvm_arm_devlistener_add(MemoryListener *listener,
216 MemoryRegionSection *section)
217 {
218 KVMDevice *kd;
219
220 QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
221 if (section->mr == kd->mr) {
222 kd->kda.addr = section->offset_within_address_space;
223 }
224 }
225 }
226
227 static void kvm_arm_devlistener_del(MemoryListener *listener,
228 MemoryRegionSection *section)
229 {
230 KVMDevice *kd;
231
232 QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
233 if (section->mr == kd->mr) {
234 kd->kda.addr = -1;
235 }
236 }
237 }
238
239 static MemoryListener devlistener = {
240 .region_add = kvm_arm_devlistener_add,
241 .region_del = kvm_arm_devlistener_del,
242 };
243
244 static void kvm_arm_set_device_addr(KVMDevice *kd)
245 {
246 struct kvm_device_attr *attr = &kd->kdattr;
247 int ret;
248
249 /* If the device control API is available and we have a device fd on the
250 * KVMDevice struct, let's use the newer API
251 */
252 if (kd->dev_fd >= 0) {
253 uint64_t addr = kd->kda.addr;
254 attr->addr = (uintptr_t)&addr;
255 ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
256 } else {
257 ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda);
258 }
259
260 if (ret < 0) {
261 fprintf(stderr, "Failed to set device address: %s\n",
262 strerror(-ret));
263 abort();
264 }
265 }
266
267 static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
268 {
269 KVMDevice *kd, *tkd;
270
271 QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
272 if (kd->kda.addr != -1) {
273 kvm_arm_set_device_addr(kd);
274 }
275 memory_region_unref(kd->mr);
276 g_free(kd);
277 }
278 memory_listener_unregister(&devlistener);
279 }
280
281 static Notifier notify = {
282 .notify = kvm_arm_machine_init_done,
283 };
284
285 void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
286 uint64_t attr, int dev_fd)
287 {
288 KVMDevice *kd;
289
290 if (!kvm_irqchip_in_kernel()) {
291 return;
292 }
293
294 if (QSLIST_EMPTY(&kvm_devices_head)) {
295 memory_listener_register(&devlistener, &address_space_memory);
296 qemu_add_machine_init_done_notifier(&notify);
297 }
298 kd = g_new0(KVMDevice, 1);
299 kd->mr = mr;
300 kd->kda.id = devid;
301 kd->kda.addr = -1;
302 kd->kdattr.flags = 0;
303 kd->kdattr.group = group;
304 kd->kdattr.attr = attr;
305 kd->dev_fd = dev_fd;
306 QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
307 memory_region_ref(kd->mr);
308 }
309
310 static int compare_u64(const void *a, const void *b)
311 {
312 if (*(uint64_t *)a > *(uint64_t *)b) {
313 return 1;
314 }
315 if (*(uint64_t *)a < *(uint64_t *)b) {
316 return -1;
317 }
318 return 0;
319 }
320
321 /* Initialize the CPUState's cpreg list according to the kernel's
322 * definition of what CPU registers it knows about (and throw away
323 * the previous TCG-created cpreg list).
324 */
325 int kvm_arm_init_cpreg_list(ARMCPU *cpu)
326 {
327 struct kvm_reg_list rl;
328 struct kvm_reg_list *rlp;
329 int i, ret, arraylen;
330 CPUState *cs = CPU(cpu);
331
332 rl.n = 0;
333 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
334 if (ret != -E2BIG) {
335 return ret;
336 }
337 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
338 rlp->n = rl.n;
339 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
340 if (ret) {
341 goto out;
342 }
343 /* Sort the list we get back from the kernel, since cpreg_tuples
344 * must be in strictly ascending order.
345 */
346 qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
347
348 for (i = 0, arraylen = 0; i < rlp->n; i++) {
349 if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) {
350 continue;
351 }
352 switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
353 case KVM_REG_SIZE_U32:
354 case KVM_REG_SIZE_U64:
355 break;
356 default:
357 fprintf(stderr, "Can't handle size of register in kernel list\n");
358 ret = -EINVAL;
359 goto out;
360 }
361
362 arraylen++;
363 }
364
365 cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
366 cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
367 cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
368 arraylen);
369 cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
370 arraylen);
371 cpu->cpreg_array_len = arraylen;
372 cpu->cpreg_vmstate_array_len = arraylen;
373
374 for (i = 0, arraylen = 0; i < rlp->n; i++) {
375 uint64_t regidx = rlp->reg[i];
376 if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) {
377 continue;
378 }
379 cpu->cpreg_indexes[arraylen] = regidx;
380 arraylen++;
381 }
382 assert(cpu->cpreg_array_len == arraylen);
383
384 if (!write_kvmstate_to_list(cpu)) {
385 /* Shouldn't happen unless kernel is inconsistent about
386 * what registers exist.
387 */
388 fprintf(stderr, "Initial read of kernel register state failed\n");
389 ret = -EINVAL;
390 goto out;
391 }
392
393 out:
394 g_free(rlp);
395 return ret;
396 }
397
398 bool write_kvmstate_to_list(ARMCPU *cpu)
399 {
400 CPUState *cs = CPU(cpu);
401 int i;
402 bool ok = true;
403
404 for (i = 0; i < cpu->cpreg_array_len; i++) {
405 struct kvm_one_reg r;
406 uint64_t regidx = cpu->cpreg_indexes[i];
407 uint32_t v32;
408 int ret;
409
410 r.id = regidx;
411
412 switch (regidx & KVM_REG_SIZE_MASK) {
413 case KVM_REG_SIZE_U32:
414 r.addr = (uintptr_t)&v32;
415 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
416 if (!ret) {
417 cpu->cpreg_values[i] = v32;
418 }
419 break;
420 case KVM_REG_SIZE_U64:
421 r.addr = (uintptr_t)(cpu->cpreg_values + i);
422 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
423 break;
424 default:
425 abort();
426 }
427 if (ret) {
428 ok = false;
429 }
430 }
431 return ok;
432 }
433
434 bool write_list_to_kvmstate(ARMCPU *cpu, int level)
435 {
436 CPUState *cs = CPU(cpu);
437 int i;
438 bool ok = true;
439
440 for (i = 0; i < cpu->cpreg_array_len; i++) {
441 struct kvm_one_reg r;
442 uint64_t regidx = cpu->cpreg_indexes[i];
443 uint32_t v32;
444 int ret;
445
446 if (kvm_arm_cpreg_level(regidx) > level) {
447 continue;
448 }
449
450 r.id = regidx;
451 switch (regidx & KVM_REG_SIZE_MASK) {
452 case KVM_REG_SIZE_U32:
453 v32 = cpu->cpreg_values[i];
454 r.addr = (uintptr_t)&v32;
455 break;
456 case KVM_REG_SIZE_U64:
457 r.addr = (uintptr_t)(cpu->cpreg_values + i);
458 break;
459 default:
460 abort();
461 }
462 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
463 if (ret) {
464 /* We might fail for "unknown register" and also for
465 * "you tried to set a register which is constant with
466 * a different value from what it actually contains".
467 */
468 ok = false;
469 }
470 }
471 return ok;
472 }
473
474 void kvm_arm_reset_vcpu(ARMCPU *cpu)
475 {
476 int ret;
477
478 /* Re-init VCPU so that all registers are set to
479 * their respective reset values.
480 */
481 ret = kvm_arm_vcpu_init(CPU(cpu));
482 if (ret < 0) {
483 fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret));
484 abort();
485 }
486 if (!write_kvmstate_to_list(cpu)) {
487 fprintf(stderr, "write_kvmstate_to_list failed\n");
488 abort();
489 }
490 }
491
492 /*
493 * Update KVM's MP_STATE based on what QEMU thinks it is
494 */
495 int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu)
496 {
497 if (cap_has_mp_state) {
498 struct kvm_mp_state mp_state = {
499 .mp_state = (cpu->power_state == PSCI_OFF) ?
500 KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE
501 };
502 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
503 if (ret) {
504 fprintf(stderr, "%s: failed to set MP_STATE %d/%s\n",
505 __func__, ret, strerror(-ret));
506 return -1;
507 }
508 }
509
510 return 0;
511 }
512
513 /*
514 * Sync the KVM MP_STATE into QEMU
515 */
516 int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
517 {
518 if (cap_has_mp_state) {
519 struct kvm_mp_state mp_state;
520 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
521 if (ret) {
522 fprintf(stderr, "%s: failed to get MP_STATE %d/%s\n",
523 __func__, ret, strerror(-ret));
524 abort();
525 }
526 cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ?
527 PSCI_OFF : PSCI_ON;
528 }
529
530 return 0;
531 }
532
533 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
534 {
535 }
536
537 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
538 {
539 ARMCPU *cpu;
540 uint32_t switched_level;
541
542 if (kvm_irqchip_in_kernel()) {
543 /*
544 * We only need to sync timer states with user-space interrupt
545 * controllers, so return early and save cycles if we don't.
546 */
547 return MEMTXATTRS_UNSPECIFIED;
548 }
549
550 cpu = ARM_CPU(cs);
551
552 /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */
553 if (run->s.regs.device_irq_level != cpu->device_irq_level) {
554 switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level;
555
556 qemu_mutex_lock_iothread();
557
558 if (switched_level & KVM_ARM_DEV_EL1_VTIMER) {
559 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT],
560 !!(run->s.regs.device_irq_level &
561 KVM_ARM_DEV_EL1_VTIMER));
562 switched_level &= ~KVM_ARM_DEV_EL1_VTIMER;
563 }
564
565 if (switched_level & KVM_ARM_DEV_EL1_PTIMER) {
566 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS],
567 !!(run->s.regs.device_irq_level &
568 KVM_ARM_DEV_EL1_PTIMER));
569 switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;
570 }
571
572 if (switched_level & KVM_ARM_DEV_PMU) {
573 qemu_set_irq(cpu->pmu_interrupt,
574 !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU));
575 switched_level &= ~KVM_ARM_DEV_PMU;
576 }
577
578 if (switched_level) {
579 qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",
580 __func__, switched_level);
581 }
582
583 /* We also mark unknown levels as processed to not waste cycles */
584 cpu->device_irq_level = run->s.regs.device_irq_level;
585 qemu_mutex_unlock_iothread();
586 }
587
588 return MEMTXATTRS_UNSPECIFIED;
589 }
590
591
592 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
593 {
594 int ret = 0;
595
596 switch (run->exit_reason) {
597 case KVM_EXIT_DEBUG:
598 if (kvm_arm_handle_debug(cs, &run->debug.arch)) {
599 ret = EXCP_DEBUG;
600 } /* otherwise return to guest */
601 break;
602 default:
603 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
604 __func__, run->exit_reason);
605 break;
606 }
607 return ret;
608 }
609
610 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
611 {
612 return true;
613 }
614
615 int kvm_arch_process_async_events(CPUState *cs)
616 {
617 return 0;
618 }
619
620 /* The #ifdef protections are until 32bit headers are imported and can
621 * be removed once both 32 and 64 bit reach feature parity.
622 */
623 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
624 {
625 #ifdef KVM_GUESTDBG_USE_SW_BP
626 if (kvm_sw_breakpoints_active(cs)) {
627 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
628 }
629 #endif
630 #ifdef KVM_GUESTDBG_USE_HW
631 if (kvm_arm_hw_debug_active(cs)) {
632 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW;
633 kvm_arm_copy_hw_debug_data(&dbg->arch);
634 }
635 #endif
636 }
637
638 void kvm_arch_init_irq_routing(KVMState *s)
639 {
640 }
641
642 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
643 {
644 if (machine_kernel_irqchip_split(ms)) {
645 perror("-machine kernel_irqchip=split is not supported on ARM.");
646 exit(1);
647 }
648
649 /* If we can create the VGIC using the newer device control API, we
650 * let the device do this when it initializes itself, otherwise we
651 * fall back to the old API */
652 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
653 }
654
655 int kvm_arm_vgic_probe(void)
656 {
657 if (kvm_create_device(kvm_state,
658 KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
659 return 3;
660 } else if (kvm_create_device(kvm_state,
661 KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
662 return 2;
663 } else {
664 return 0;
665 }
666 }
667
668 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
669 uint64_t address, uint32_t data, PCIDevice *dev)
670 {
671 return 0;
672 }
673
674 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
675 int vector, PCIDevice *dev)
676 {
677 return 0;
678 }
679
680 int kvm_arch_release_virq_post(int virq)
681 {
682 return 0;
683 }
684
685 int kvm_arch_msi_data_to_gsi(uint32_t data)
686 {
687 return (data - 32) & 0xffff;
688 }