target/arm/kvm64.c

   1 /*
   2  * ARM implementation of KVM hooks, 64 bit specific code
   3  *
   4  * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
   5  * Copyright Alex Bennée 2014, Linaro
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   8  * See the COPYING file in the top-level directory.
   9  *
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include <sys/ioctl.h>
  14 #include <sys/ptrace.h>
  15
  16 #include <linux/elf.h>
  17 #include <linux/kvm.h>
  18
  19 #include "qemu-common.h"
  20 #include "cpu.h"
  21 #include "qemu/timer.h"
  22 #include "qemu/error-report.h"
  23 #include "qemu/host-utils.h"
  24 #include "exec/gdbstub.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/kvm.h"
  27 #include "kvm_arm.h"
  28 #include "internals.h"
  29 #include "hw/arm/arm.h"
  30
  31 static bool have_guest_debug;
  32
  33 /*
  34  * Although the ARM implementation of hardware assisted debugging
  35  * allows for different breakpoints per-core, the current GDB
  36  * interface treats them as a global pool of registers (which seems to
  37  * be the case for x86, ppc and s390). As a result we store one copy
  38  * of registers which is used for all active cores.
  39  *
  40  * Write access is serialised by virtue of the GDB protocol which
  41  * updates things. Read access (i.e. when the values are copied to the
  42  * vCPU) is also gated by GDB's run control.
  43  *
  44  * This is not unreasonable as most of the time debugging kernels you
  45  * never know which core will eventually execute your function.
  46  */
  47
  48 typedef struct {
  49     uint64_t bcr;
  50     uint64_t bvr;
  51 } HWBreakpoint;
  52
  53 /* The watchpoint registers can cover more area than the requested
  54  * watchpoint so we need to store the additional information
  55  * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
  56  * when the watchpoint is hit.
  57  */
  58 typedef struct {
  59     uint64_t wcr;
  60     uint64_t wvr;
  61     CPUWatchpoint details;
  62 } HWWatchpoint;
  63
  64 /* Maximum and current break/watch point counts */
  65 int max_hw_bps, max_hw_wps;
  66 GArray *hw_breakpoints, *hw_watchpoints;
  67
  68 #define cur_hw_wps      (hw_watchpoints->len)
  69 #define cur_hw_bps      (hw_breakpoints->len)
  70 #define get_hw_bp(i)    (&g_array_index(hw_breakpoints, HWBreakpoint, i))
  71 #define get_hw_wp(i)    (&g_array_index(hw_watchpoints, HWWatchpoint, i))
  72
  73 /**
  74  * kvm_arm_init_debug() - check for guest debug capabilities
  75  * @cs: CPUState
  76  *
  77  * kvm_check_extension returns the number of debug registers we have
  78  * or 0 if we have none.
  79  *
  80  */
  81 static void kvm_arm_init_debug(CPUState *cs)
  82 {
  83     have_guest_debug = kvm_check_extension(cs->kvm_state,
  84                                            KVM_CAP_SET_GUEST_DEBUG);
  85
  86     max_hw_wps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_WPS);
  87     hw_watchpoints = g_array_sized_new(true, true,
  88                                        sizeof(HWWatchpoint), max_hw_wps);
  89
  90     max_hw_bps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_BPS);
  91     hw_breakpoints = g_array_sized_new(true, true,
  92                                        sizeof(HWBreakpoint), max_hw_bps);
  93     return;
  94 }
  95
  96 /**
  97  * insert_hw_breakpoint()
  98  * @addr: address of breakpoint
  99  *
 100  * See ARM ARM D2.9.1 for details but here we are only going to create
 101  * simple un-linked breakpoints (i.e. we don't chain breakpoints
 102  * together to match address and context or vmid). The hardware is
 103  * capable of fancier matching but that will require exposing that
 104  * fanciness to GDB's interface
 105  *
 106  * D7.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers
 107  *
 108  *  31  24 23  20 19   16 15 14  13  12   9 8   5 4    3 2   1  0
 109  * +------+------+-------+-----+----+------+-----+------+-----+---+
 110  * | RES0 |  BT  |  LBN  | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
 111  * +------+------+-------+-----+----+------+-----+------+-----+---+
 112  *
 113  * BT: Breakpoint type (0 = unlinked address match)
 114  * LBN: Linked BP number (0 = unused)
 115  * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
 116  * BAS: Byte Address Select (RES1 for AArch64)
 117  * E: Enable bit
 118  */
 119 static int insert_hw_breakpoint(target_ulong addr)
 120 {
 121     HWBreakpoint brk = {
 122         .bcr = 0x1,                             /* BCR E=1, enable */
 123         .bvr = addr
 124     };
 125
 126     if (cur_hw_bps >= max_hw_bps) {
 127         return -ENOBUFS;
 128     }
 129
 130     brk.bcr = deposit32(brk.bcr, 1, 2, 0x3);   /* PMC = 11 */
 131     brk.bcr = deposit32(brk.bcr, 5, 4, 0xf);   /* BAS = RES1 */
 132
 133     g_array_append_val(hw_breakpoints, brk);
 134
 135     return 0;
 136 }
 137
 138 /**
 139  * delete_hw_breakpoint()
 140  * @pc: address of breakpoint
 141  *
 142  * Delete a breakpoint and shuffle any above down
 143  */
 144
 145 static int delete_hw_breakpoint(target_ulong pc)
 146 {
 147     int i;
 148     for (i = 0; i < hw_breakpoints->len; i++) {
 149         HWBreakpoint *brk = get_hw_bp(i);
 150         if (brk->bvr == pc) {
 151             g_array_remove_index(hw_breakpoints, i);
 152             return 0;
 153         }
 154     }
 155     return -ENOENT;
 156 }
 157
 158 /**
 159  * insert_hw_watchpoint()
 160  * @addr: address of watch point
 161  * @len: size of area
 162  * @type: type of watch point
 163  *
 164  * See ARM ARM D2.10. As with the breakpoints we can do some advanced
 165  * stuff if we want to. The watch points can be linked with the break
 166  * points above to make them context aware. However for simplicity
 167  * currently we only deal with simple read/write watch points.
 168  *
 169  * D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
 170  *
 171  *  31  29 28   24 23  21  20  19 16 15 14  13   12  5 4   3 2   1  0
 172  * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
 173  * | RES0 |  MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
 174  * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
 175  *
 176  * MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
 177  * WT: 0 - unlinked, 1 - linked (not currently used)
 178  * LBN: Linked BP number (not currently used)
 179  * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
 180  * BAS: Byte Address Select
 181  * LSC: Load/Store control (01: load, 10: store, 11: both)
 182  * E: Enable
 183  *
 184  * The bottom 2 bits of the value register are masked. Therefore to
 185  * break on any sizes smaller than an unaligned word you need to set
 186  * MASK=0, BAS=bit per byte in question. For larger regions (^2) you
 187  * need to ensure you mask the address as required and set BAS=0xff
 188  */
 189
 190 static int insert_hw_watchpoint(target_ulong addr,
 191                                 target_ulong len, int type)
 192 {
 193     HWWatchpoint wp = {
 194         .wcr = 1, /* E=1, enable */
 195         .wvr = addr & (~0x7ULL),
 196         .details = { .vaddr = addr, .len = len }
 197     };
 198
 199     if (cur_hw_wps >= max_hw_wps) {
 200         return -ENOBUFS;
 201     }
 202
 203     /*
 204      * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
 205      * valid whether EL3 is implemented or not
 206      */
 207     wp.wcr = deposit32(wp.wcr, 1, 2, 3);
 208
 209     switch (type) {
 210     case GDB_WATCHPOINT_READ:
 211         wp.wcr = deposit32(wp.wcr, 3, 2, 1);
 212         wp.details.flags = BP_MEM_READ;
 213         break;
 214     case GDB_WATCHPOINT_WRITE:
 215         wp.wcr = deposit32(wp.wcr, 3, 2, 2);
 216         wp.details.flags = BP_MEM_WRITE;
 217         break;
 218     case GDB_WATCHPOINT_ACCESS:
 219         wp.wcr = deposit32(wp.wcr, 3, 2, 3);
 220         wp.details.flags = BP_MEM_ACCESS;
 221         break;
 222     default:
 223         g_assert_not_reached();
 224         break;
 225     }
 226     if (len <= 8) {
 227         /* we align the address and set the bits in BAS */
 228         int off = addr & 0x7;
 229         int bas = (1 << len) - 1;
 230
 231         wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas);
 232     } else {
 233         /* For ranges above 8 bytes we need to be a power of 2 */
 234         if (is_power_of_2(len)) {
 235             int bits = ctz64(len);
 236
 237             wp.wvr &= ~((1 << bits) - 1);
 238             wp.wcr = deposit32(wp.wcr, 24, 4, bits);
 239             wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
 240         } else {
 241             return -ENOBUFS;
 242         }
 243     }
 244
 245     g_array_append_val(hw_watchpoints, wp);
 246     return 0;
 247 }
 248
 249
 250 static bool check_watchpoint_in_range(int i, target_ulong addr)
 251 {
 252     HWWatchpoint *wp = get_hw_wp(i);
 253     uint64_t addr_top, addr_bottom = wp->wvr;
 254     int bas = extract32(wp->wcr, 5, 8);
 255     int mask = extract32(wp->wcr, 24, 4);
 256
 257     if (mask) {
 258         addr_top = addr_bottom + (1 << mask);
 259     } else {
 260         /* BAS must be contiguous but can offset against the base
 261          * address in DBGWVR */
 262         addr_bottom = addr_bottom + ctz32(bas);
 263         addr_top = addr_bottom + clo32(bas);
 264     }
 265
 266     if (addr >= addr_bottom && addr <= addr_top) {
 267         return true;
 268     }
 269
 270     return false;
 271 }
 272
 273 /**
 274  * delete_hw_watchpoint()
 275  * @addr: address of breakpoint
 276  *
 277  * Delete a breakpoint and shuffle any above down
 278  */
 279
 280 static int delete_hw_watchpoint(target_ulong addr,
 281                                 target_ulong len, int type)
 282 {
 283     int i;
 284     for (i = 0; i < cur_hw_wps; i++) {
 285         if (check_watchpoint_in_range(i, addr)) {
 286             g_array_remove_index(hw_watchpoints, i);
 287             return 0;
 288         }
 289     }
 290     return -ENOENT;
 291 }
 292
 293
 294 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 295                                   target_ulong len, int type)
 296 {
 297     switch (type) {
 298     case GDB_BREAKPOINT_HW:
 299         return insert_hw_breakpoint(addr);
 300         break;
 301     case GDB_WATCHPOINT_READ:
 302     case GDB_WATCHPOINT_WRITE:
 303     case GDB_WATCHPOINT_ACCESS:
 304         return insert_hw_watchpoint(addr, len, type);
 305     default:
 306         return -ENOSYS;
 307     }
 308 }
 309
 310 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 311                                   target_ulong len, int type)
 312 {
 313     switch (type) {
 314     case GDB_BREAKPOINT_HW:
 315         return delete_hw_breakpoint(addr);
 316         break;
 317     case GDB_WATCHPOINT_READ:
 318     case GDB_WATCHPOINT_WRITE:
 319     case GDB_WATCHPOINT_ACCESS:
 320         return delete_hw_watchpoint(addr, len, type);
 321     default:
 322         return -ENOSYS;
 323     }
 324 }
 325
 326
 327 void kvm_arch_remove_all_hw_breakpoints(void)
 328 {
 329     if (cur_hw_wps > 0) {
 330         g_array_remove_range(hw_watchpoints, 0, cur_hw_wps);
 331     }
 332     if (cur_hw_bps > 0) {
 333         g_array_remove_range(hw_breakpoints, 0, cur_hw_bps);
 334     }
 335 }
 336
 337 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 338 {
 339     int i;
 340     memset(ptr, 0, sizeof(struct kvm_guest_debug_arch));
 341
 342     for (i = 0; i < max_hw_wps; i++) {
 343         HWWatchpoint *wp = get_hw_wp(i);
 344         ptr->dbg_wcr[i] = wp->wcr;
 345         ptr->dbg_wvr[i] = wp->wvr;
 346     }
 347     for (i = 0; i < max_hw_bps; i++) {
 348         HWBreakpoint *bp = get_hw_bp(i);
 349         ptr->dbg_bcr[i] = bp->bcr;
 350         ptr->dbg_bvr[i] = bp->bvr;
 351     }
 352 }
 353
 354 bool kvm_arm_hw_debug_active(CPUState *cs)
 355 {
 356     return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
 357 }
 358
 359 static bool find_hw_breakpoint(CPUState *cpu, target_ulong pc)
 360 {
 361     int i;
 362
 363     for (i = 0; i < cur_hw_bps; i++) {
 364         HWBreakpoint *bp = get_hw_bp(i);
 365         if (bp->bvr == pc) {
 366             return true;
 367         }
 368     }
 369     return false;
 370 }
 371
 372 static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
 373 {
 374     int i;
 375
 376     for (i = 0; i < cur_hw_wps; i++) {
 377         if (check_watchpoint_in_range(i, addr)) {
 378             return &get_hw_wp(i)->details;
 379         }
 380     }
 381     return NULL;
 382 }
 383
 384 static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr)
 385 {
 386     int err;
 387
 388     err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
 389     if (err != 0) {
 390         error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err));
 391         return false;
 392     }
 393
 394     err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
 395     if (err != 0) {
 396         error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err));
 397         return false;
 398     }
 399
 400     return true;
 401 }
 402
 403 void kvm_arm_pmu_init(CPUState *cs)
 404 {
 405     struct kvm_device_attr attr = {
 406         .group = KVM_ARM_VCPU_PMU_V3_CTRL,
 407         .attr = KVM_ARM_VCPU_PMU_V3_INIT,
 408     };
 409
 410     if (!ARM_CPU(cs)->has_pmu) {
 411         return;
 412     }
 413     if (!kvm_arm_pmu_set_attr(cs, &attr)) {
 414         error_report("failed to init PMU");
 415         abort();
 416     }
 417 }
 418
 419 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 420 {
 421     struct kvm_device_attr attr = {
 422         .group = KVM_ARM_VCPU_PMU_V3_CTRL,
 423         .addr = (intptr_t)&irq,
 424         .attr = KVM_ARM_VCPU_PMU_V3_IRQ,
 425     };
 426
 427     if (!ARM_CPU(cs)->has_pmu) {
 428         return;
 429     }
 430     if (!kvm_arm_pmu_set_attr(cs, &attr)) {
 431         error_report("failed to set irq for PMU");
 432         abort();
 433     }
 434 }
 435
 436 static inline void set_feature(uint64_t *features, int feature)
 437 {
 438     *features |= 1ULL << feature;
 439 }
 440
 441 static inline void unset_feature(uint64_t *features, int feature)
 442 {
 443     *features &= ~(1ULL << feature);
 444 }
 445
 446 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 447 {
 448     /* Identify the feature bits corresponding to the host CPU, and
 449      * fill out the ARMHostCPUClass fields accordingly. To do this
 450      * we have to create a scratch VM, create a single CPU inside it,
 451      * and then query that CPU for the relevant ID registers.
 452      * For AArch64 we currently don't care about ID registers at
 453      * all; we just want to know the CPU type.
 454      */
 455     int fdarray[3];
 456     uint64_t features = 0;
 457     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
 458      * we know these will only support creating one kind of guest CPU,
 459      * which is its preferred CPU type. Fortunately these old kernels
 460      * support only a very limited number of CPUs.
 461      */
 462     static const uint32_t cpus_to_try[] = {
 463         KVM_ARM_TARGET_AEM_V8,
 464         KVM_ARM_TARGET_FOUNDATION_V8,
 465         KVM_ARM_TARGET_CORTEX_A57,
 466         QEMU_KVM_ARM_TARGET_NONE
 467     };
 468     struct kvm_vcpu_init init;
 469
 470     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
 471         return false;
 472     }
 473
 474     ahcf->target = init.target;
 475     ahcf->dtb_compatible = "arm,arm-v8";
 476
 477     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 478
 479    /* We can assume any KVM supporting CPU is at least a v8
 480      * with VFPv4+Neon; this in turn implies most of the other
 481      * feature bits.
 482      */
 483     set_feature(&features, ARM_FEATURE_V8);
 484     set_feature(&features, ARM_FEATURE_VFP4);
 485     set_feature(&features, ARM_FEATURE_NEON);
 486     set_feature(&features, ARM_FEATURE_AARCH64);
 487     set_feature(&features, ARM_FEATURE_PMU);
 488
 489     ahcf->features = features;
 490
 491     return true;
 492 }
 493
 494 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
 495
 496 int kvm_arch_init_vcpu(CPUState *cs)
 497 {
 498     int ret;
 499     uint64_t mpidr;
 500     ARMCPU *cpu = ARM_CPU(cs);
 501     CPUARMState *env = &cpu->env;
 502
 503     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
 504         !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
 505         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 506         return -EINVAL;
 507     }
 508
 509     /* Determine init features for this CPU */
 510     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 511     if (cpu->start_powered_off) {
 512         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 513     }
 514     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 515         cpu->psci_version = 2;
 516         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 517     }
 518     if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 519         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
 520     }
 521     if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
 522             cpu->has_pmu = false;
 523     }
 524     if (cpu->has_pmu) {
 525         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
 526     } else {
 527         unset_feature(&env->features, ARM_FEATURE_PMU);
 528     }
 529
 530     /* Do KVM_ARM_VCPU_INIT ioctl */
 531     ret = kvm_arm_vcpu_init(cs);
 532     if (ret) {
 533         return ret;
 534     }
 535
 536     /*
 537      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 538      * Currently KVM has its own idea about MPIDR assignment, so we
 539      * override our defaults with what we get from KVM.
 540      */
 541     ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr);
 542     if (ret) {
 543         return ret;
 544     }
 545     cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
 546
 547     kvm_arm_init_debug(cs);
 548
 549     /* Check whether user space can specify guest syndrome value */
 550     kvm_arm_init_serror_injection(cs);
 551
 552     return kvm_arm_init_cpreg_list(cpu);
 553 }
 554
 555 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 556 {
 557     /* Return true if the regidx is a register we should synchronize
 558      * via the cpreg_tuples array (ie is not a core reg we sync by
 559      * hand in kvm_arch_get/put_registers())
 560      */
 561     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 562     case KVM_REG_ARM_CORE:
 563         return false;
 564     default:
 565         return true;
 566     }
 567 }
 568
 569 typedef struct CPRegStateLevel {
 570     uint64_t regidx;
 571     int level;
 572 } CPRegStateLevel;
 573
 574 /* All system registers not listed in the following table are assumed to be
 575  * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 576  * often, you must add it to this table with a state of either
 577  * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 578  */
 579 static const CPRegStateLevel non_runtime_cpregs[] = {
 580     { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 581 };
 582
 583 int kvm_arm_cpreg_level(uint64_t regidx)
 584 {
 585     int i;
 586
 587     for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 588         const CPRegStateLevel *l = &non_runtime_cpregs[i];
 589         if (l->regidx == regidx) {
 590             return l->level;
 591         }
 592     }
 593
 594     return KVM_PUT_RUNTIME_STATE;
 595 }
 596
 597 #define AARCH64_CORE_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
 598                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 599
 600 #define AARCH64_SIMD_CORE_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
 601                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 602
 603 #define AARCH64_SIMD_CTRL_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
 604                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 605
 606 int kvm_arch_put_registers(CPUState *cs, int level)
 607 {
 608     struct kvm_one_reg reg;
 609     uint32_t fpr;
 610     uint64_t val;
 611     int i;
 612     int ret;
 613     unsigned int el;
 614
 615     ARMCPU *cpu = ARM_CPU(cs);
 616     CPUARMState *env = &cpu->env;
 617
 618     /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
 619      * AArch64 registers before pushing them out to 64-bit KVM.
 620      */
 621     if (!is_a64(env)) {
 622         aarch64_sync_32_to_64(env);
 623     }
 624
 625     for (i = 0; i < 31; i++) {
 626         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 627         reg.addr = (uintptr_t) &env->xregs[i];
 628         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 629         if (ret) {
 630             return ret;
 631         }
 632     }
 633
 634     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 635      * QEMU side we keep the current SP in xregs[31] as well.
 636      */
 637     aarch64_save_sp(env, 1);
 638
 639     reg.id = AARCH64_CORE_REG(regs.sp);
 640     reg.addr = (uintptr_t) &env->sp_el[0];
 641     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 642     if (ret) {
 643         return ret;
 644     }
 645
 646     reg.id = AARCH64_CORE_REG(sp_el1);
 647     reg.addr = (uintptr_t) &env->sp_el[1];
 648     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 649     if (ret) {
 650         return ret;
 651     }
 652
 653     /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
 654     if (is_a64(env)) {
 655         val = pstate_read(env);
 656     } else {
 657         val = cpsr_read(env);
 658     }
 659     reg.id = AARCH64_CORE_REG(regs.pstate);
 660     reg.addr = (uintptr_t) &val;
 661     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 662     if (ret) {
 663         return ret;
 664     }
 665
 666     reg.id = AARCH64_CORE_REG(regs.pc);
 667     reg.addr = (uintptr_t) &env->pc;
 668     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 669     if (ret) {
 670         return ret;
 671     }
 672
 673     reg.id = AARCH64_CORE_REG(elr_el1);
 674     reg.addr = (uintptr_t) &env->elr_el[1];
 675     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 676     if (ret) {
 677         return ret;
 678     }
 679
 680     /* Saved Program State Registers
 681      *
 682      * Before we restore from the banked_spsr[] array we need to
 683      * ensure that any modifications to env->spsr are correctly
 684      * reflected in the banks.
 685      */
 686     el = arm_current_el(env);
 687     if (el > 0 && !is_a64(env)) {
 688         i = bank_number(env->uncached_cpsr & CPSR_M);
 689         env->banked_spsr[i] = env->spsr;
 690     }
 691
 692     /* KVM 0-4 map to QEMU banks 1-5 */
 693     for (i = 0; i < KVM_NR_SPSR; i++) {
 694         reg.id = AARCH64_CORE_REG(spsr[i]);
 695         reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
 696         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 697         if (ret) {
 698             return ret;
 699         }
 700     }
 701
 702     /* Advanced SIMD and FP registers. */
 703     for (i = 0; i < 32; i++) {
 704         uint64_t *q = aa64_vfp_qreg(env, i);
 705 #ifdef HOST_WORDS_BIGENDIAN
 706         uint64_t fp_val[2] = { q[1], q[0] };
 707         reg.addr = (uintptr_t)fp_val;
 708 #else
 709         reg.addr = (uintptr_t)q;
 710 #endif
 711         reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
 712         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 713         if (ret) {
 714             return ret;
 715         }
 716     }
 717
 718     reg.addr = (uintptr_t)(&fpr);
 719     fpr = vfp_get_fpsr(env);
 720     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 721     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 722     if (ret) {
 723         return ret;
 724     }
 725
 726     fpr = vfp_get_fpcr(env);
 727     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 728     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 729     if (ret) {
 730         return ret;
 731     }
 732
 733     ret = kvm_put_vcpu_events(cpu);
 734     if (ret) {
 735         return ret;
 736     }
 737
 738     if (!write_list_to_kvmstate(cpu, level)) {
 739         return EINVAL;
 740     }
 741
 742     kvm_arm_sync_mpstate_to_kvm(cpu);
 743
 744     return ret;
 745 }
 746
 747 int kvm_arch_get_registers(CPUState *cs)
 748 {
 749     struct kvm_one_reg reg;
 750     uint64_t val;
 751     uint32_t fpr;
 752     unsigned int el;
 753     int i;
 754     int ret;
 755
 756     ARMCPU *cpu = ARM_CPU(cs);
 757     CPUARMState *env = &cpu->env;
 758
 759     for (i = 0; i < 31; i++) {
 760         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 761         reg.addr = (uintptr_t) &env->xregs[i];
 762         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 763         if (ret) {
 764             return ret;
 765         }
 766     }
 767
 768     reg.id = AARCH64_CORE_REG(regs.sp);
 769     reg.addr = (uintptr_t) &env->sp_el[0];
 770     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 771     if (ret) {
 772         return ret;
 773     }
 774
 775     reg.id = AARCH64_CORE_REG(sp_el1);
 776     reg.addr = (uintptr_t) &env->sp_el[1];
 777     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 778     if (ret) {
 779         return ret;
 780     }
 781
 782     reg.id = AARCH64_CORE_REG(regs.pstate);
 783     reg.addr = (uintptr_t) &val;
 784     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 785     if (ret) {
 786         return ret;
 787     }
 788
 789     env->aarch64 = ((val & PSTATE_nRW) == 0);
 790     if (is_a64(env)) {
 791         pstate_write(env, val);
 792     } else {
 793         cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
 794     }
 795
 796     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 797      * QEMU side we keep the current SP in xregs[31] as well.
 798      */
 799     aarch64_restore_sp(env, 1);
 800
 801     reg.id = AARCH64_CORE_REG(regs.pc);
 802     reg.addr = (uintptr_t) &env->pc;
 803     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 804     if (ret) {
 805         return ret;
 806     }
 807
 808     /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
 809      * incoming AArch64 regs received from 64-bit KVM.
 810      * We must perform this after all of the registers have been acquired from
 811      * the kernel.
 812      */
 813     if (!is_a64(env)) {
 814         aarch64_sync_64_to_32(env);
 815     }
 816
 817     reg.id = AARCH64_CORE_REG(elr_el1);
 818     reg.addr = (uintptr_t) &env->elr_el[1];
 819     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 820     if (ret) {
 821         return ret;
 822     }
 823
 824     /* Fetch the SPSR registers
 825      *
 826      * KVM SPSRs 0-4 map to QEMU banks 1-5
 827      */
 828     for (i = 0; i < KVM_NR_SPSR; i++) {
 829         reg.id = AARCH64_CORE_REG(spsr[i]);
 830         reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
 831         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 832         if (ret) {
 833             return ret;
 834         }
 835     }
 836
 837     el = arm_current_el(env);
 838     if (el > 0 && !is_a64(env)) {
 839         i = bank_number(env->uncached_cpsr & CPSR_M);
 840         env->spsr = env->banked_spsr[i];
 841     }
 842
 843     /* Advanced SIMD and FP registers */
 844     for (i = 0; i < 32; i++) {
 845         uint64_t *q = aa64_vfp_qreg(env, i);
 846         reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
 847         reg.addr = (uintptr_t)q;
 848         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 849         if (ret) {
 850             return ret;
 851         } else {
 852 #ifdef HOST_WORDS_BIGENDIAN
 853             uint64_t t;
 854             t = q[0], q[0] = q[1], q[1] = t;
 855 #endif
 856         }
 857     }
 858
 859     reg.addr = (uintptr_t)(&fpr);
 860     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 861     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 862     if (ret) {
 863         return ret;
 864     }
 865     vfp_set_fpsr(env, fpr);
 866
 867     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 868     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 869     if (ret) {
 870         return ret;
 871     }
 872     vfp_set_fpcr(env, fpr);
 873
 874     ret = kvm_get_vcpu_events(cpu);
 875     if (ret) {
 876         return ret;
 877     }
 878
 879     if (!write_kvmstate_to_list(cpu)) {
 880         return EINVAL;
 881     }
 882     /* Note that it's OK to have registers which aren't in CPUState,
 883      * so we can ignore a failure return here.
 884      */
 885     write_list_to_cpustate(cpu);
 886
 887     kvm_arm_sync_mpstate_to_qemu(cpu);
 888
 889     /* TODO: other registers */
 890     return ret;
 891 }
 892
 893 /* C6.6.29 BRK instruction */
 894 static const uint32_t brk_insn = 0xd4200000;
 895
 896 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 897 {
 898     if (have_guest_debug) {
 899         if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
 900             cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
 901             return -EINVAL;
 902         }
 903         return 0;
 904     } else {
 905         error_report("guest debug not supported on this kernel");
 906         return -EINVAL;
 907     }
 908 }
 909
 910 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 911 {
 912     static uint32_t brk;
 913
 914     if (have_guest_debug) {
 915         if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) ||
 916             brk != brk_insn ||
 917             cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
 918             return -EINVAL;
 919         }
 920         return 0;
 921     } else {
 922         error_report("guest debug not supported on this kernel");
 923         return -EINVAL;
 924     }
 925 }
 926
 927 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
 928  *
 929  * To minimise translating between kernel and user-space the kernel
 930  * ABI just provides user-space with the full exception syndrome
 931  * register value to be decoded in QEMU.
 932  */
 933
 934 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 935 {
 936     int hsr_ec = debug_exit->hsr >> ARM_EL_EC_SHIFT;
 937     ARMCPU *cpu = ARM_CPU(cs);
 938     CPUClass *cc = CPU_GET_CLASS(cs);
 939     CPUARMState *env = &cpu->env;
 940
 941     /* Ensure PC is synchronised */
 942     kvm_cpu_synchronize_state(cs);
 943
 944     switch (hsr_ec) {
 945     case EC_SOFTWARESTEP:
 946         if (cs->singlestep_enabled) {
 947             return true;
 948         } else {
 949             /*
 950              * The kernel should have suppressed the guest's ability to
 951              * single step at this point so something has gone wrong.
 952              */
 953             error_report("%s: guest single-step while debugging unsupported"
 954                          " (%"PRIx64", %"PRIx32")",
 955                          __func__, env->pc, debug_exit->hsr);
 956             return false;
 957         }
 958         break;
 959     case EC_AA64_BKPT:
 960         if (kvm_find_sw_breakpoint(cs, env->pc)) {
 961             return true;
 962         }
 963         break;
 964     case EC_BREAKPOINT:
 965         if (find_hw_breakpoint(cs, env->pc)) {
 966             return true;
 967         }
 968         break;
 969     case EC_WATCHPOINT:
 970     {
 971         CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far);
 972         if (wp) {
 973             cs->watchpoint_hit = wp;
 974             return true;
 975         }
 976         break;
 977     }
 978     default:
 979         error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
 980                      __func__, debug_exit->hsr, env->pc);
 981     }
 982
 983     /* If we are not handling the debug exception it must belong to
 984      * the guest. Let's re-use the existing TCG interrupt code to set
 985      * everything up properly.
 986      */
 987     cs->exception_index = EXCP_BKPT;
 988     env->exception.syndrome = debug_exit->hsr;
 989     env->exception.vaddress = debug_exit->far;
 990     cc->do_interrupt(cs);
 991
 992     return false;
 993 }