target/arm/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "hw/hw.h"
   5 #include "hw/boards.h"
   6 #include "qemu/error-report.h"
   7 #include "sysemu/kvm.h"
   8 #include "kvm_arm.h"
   9 #include "internals.h"
  10 #include "migration/cpu.h"
  11
  12 static bool vfp_needed(void *opaque)
  13 {
  14     ARMCPU *cpu = opaque;
  15     CPUARMState *env = &cpu->env;
  16
  17     return arm_feature(env, ARM_FEATURE_VFP);
  18 }
  19
  20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
  21                      VMStateField *field)
  22 {
  23     ARMCPU *cpu = opaque;
  24     CPUARMState *env = &cpu->env;
  25     uint32_t val = qemu_get_be32(f);
  26
  27     vfp_set_fpscr(env, val);
  28     return 0;
  29 }
  30
  31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size,
  32                      VMStateField *field, QJSON *vmdesc)
  33 {
  34     ARMCPU *cpu = opaque;
  35     CPUARMState *env = &cpu->env;
  36
  37     qemu_put_be32(f, vfp_get_fpscr(env));
  38     return 0;
  39 }
  40
  41 static const VMStateInfo vmstate_fpscr = {
  42     .name = "fpscr",
  43     .get = get_fpscr,
  44     .put = put_fpscr,
  45 };
  46
  47 static const VMStateDescription vmstate_vfp = {
  48     .name = "cpu/vfp",
  49     .version_id = 3,
  50     .minimum_version_id = 3,
  51     .needed = vfp_needed,
  52     .fields = (VMStateField[]) {
  53         /* For compatibility, store Qn out of Zn here.  */
  54         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2),
  55         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2),
  56         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2),
  57         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2),
  58         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2),
  59         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2),
  60         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2),
  61         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2),
  62         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2),
  63         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2),
  64         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2),
  65         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2),
  66         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2),
  67         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2),
  68         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2),
  69         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2),
  70         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2),
  71         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2),
  72         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2),
  73         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2),
  74         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2),
  75         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2),
  76         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2),
  77         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2),
  78         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2),
  79         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2),
  80         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2),
  81         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2),
  82         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2),
  83         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2),
  84         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2),
  85         VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2),
  86
  87         /* The xregs array is a little awkward because element 1 (FPSCR)
  88          * requires a specific accessor, so we have to split it up in
  89          * the vmstate:
  90          */
  91         VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
  92         VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
  93         {
  94             .name = "fpscr",
  95             .version_id = 0,
  96             .size = sizeof(uint32_t),
  97             .info = &vmstate_fpscr,
  98             .flags = VMS_SINGLE,
  99             .offset = 0,
 100         },
 101         VMSTATE_END_OF_LIST()
 102     }
 103 };
 104
 105 static bool iwmmxt_needed(void *opaque)
 106 {
 107     ARMCPU *cpu = opaque;
 108     CPUARMState *env = &cpu->env;
 109
 110     return arm_feature(env, ARM_FEATURE_IWMMXT);
 111 }
 112
 113 static const VMStateDescription vmstate_iwmmxt = {
 114     .name = "cpu/iwmmxt",
 115     .version_id = 1,
 116     .minimum_version_id = 1,
 117     .needed = iwmmxt_needed,
 118     .fields = (VMStateField[]) {
 119         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
 120         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
 121         VMSTATE_END_OF_LIST()
 122     }
 123 };
 124
 125 #ifdef TARGET_AARCH64
 126 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
 127  * and ARMPredicateReg is actively empty.  This triggers errors
 128  * in the expansion of the VMSTATE macros.
 129  */
 130
 131 static bool sve_needed(void *opaque)
 132 {
 133     ARMCPU *cpu = opaque;
 134     CPUARMState *env = &cpu->env;
 135
 136     return arm_feature(env, ARM_FEATURE_SVE);
 137 }
 138
 139 /* The first two words of each Zreg is stored in VFP state.  */
 140 static const VMStateDescription vmstate_zreg_hi_reg = {
 141     .name = "cpu/sve/zreg_hi",
 142     .version_id = 1,
 143     .minimum_version_id = 1,
 144     .fields = (VMStateField[]) {
 145         VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2),
 146         VMSTATE_END_OF_LIST()
 147     }
 148 };
 149
 150 static const VMStateDescription vmstate_preg_reg = {
 151     .name = "cpu/sve/preg",
 152     .version_id = 1,
 153     .minimum_version_id = 1,
 154     .fields = (VMStateField[]) {
 155         VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8),
 156         VMSTATE_END_OF_LIST()
 157     }
 158 };
 159
 160 static const VMStateDescription vmstate_sve = {
 161     .name = "cpu/sve",
 162     .version_id = 1,
 163     .minimum_version_id = 1,
 164     .needed = sve_needed,
 165     .fields = (VMStateField[]) {
 166         VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0,
 167                              vmstate_zreg_hi_reg, ARMVectorReg),
 168         VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0,
 169                              vmstate_preg_reg, ARMPredicateReg),
 170         VMSTATE_END_OF_LIST()
 171     }
 172 };
 173 #endif /* AARCH64 */
 174
 175 static bool m_needed(void *opaque)
 176 {
 177     ARMCPU *cpu = opaque;
 178     CPUARMState *env = &cpu->env;
 179
 180     return arm_feature(env, ARM_FEATURE_M);
 181 }
 182
 183 static const VMStateDescription vmstate_m_faultmask_primask = {
 184     .name = "cpu/m/faultmask-primask",
 185     .version_id = 1,
 186     .minimum_version_id = 1,
 187     .needed = m_needed,
 188     .fields = (VMStateField[]) {
 189         VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU),
 190         VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
 191         VMSTATE_END_OF_LIST()
 192     }
 193 };
 194
 195 /* CSSELR is in a subsection because we didn't implement it previously.
 196  * Migration from an old implementation will leave it at zero, which
 197  * is OK since the only CPUs in the old implementation make the
 198  * register RAZ/WI.
 199  * Since there was no version of QEMU which implemented the CSSELR for
 200  * just non-secure, we transfer both banks here rather than putting
 201  * the secure banked version in the m-security subsection.
 202  */
 203 static bool csselr_vmstate_validate(void *opaque, int version_id)
 204 {
 205     ARMCPU *cpu = opaque;
 206
 207     return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK
 208         && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK;
 209 }
 210
 211 static bool m_csselr_needed(void *opaque)
 212 {
 213     ARMCPU *cpu = opaque;
 214
 215     return !arm_v7m_csselr_razwi(cpu);
 216 }
 217
 218 static const VMStateDescription vmstate_m_csselr = {
 219     .name = "cpu/m/csselr",
 220     .version_id = 1,
 221     .minimum_version_id = 1,
 222     .needed = m_csselr_needed,
 223     .fields = (VMStateField[]) {
 224         VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
 225         VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate),
 226         VMSTATE_END_OF_LIST()
 227     }
 228 };
 229
 230 static const VMStateDescription vmstate_m_scr = {
 231     .name = "cpu/m/scr",
 232     .version_id = 1,
 233     .minimum_version_id = 1,
 234     .needed = m_needed,
 235     .fields = (VMStateField[]) {
 236         VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU),
 237         VMSTATE_END_OF_LIST()
 238     }
 239 };
 240
 241 static const VMStateDescription vmstate_m_other_sp = {
 242     .name = "cpu/m/other-sp",
 243     .version_id = 1,
 244     .minimum_version_id = 1,
 245     .needed = m_needed,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
 248         VMSTATE_END_OF_LIST()
 249     }
 250 };
 251
 252 static bool m_v8m_needed(void *opaque)
 253 {
 254     ARMCPU *cpu = opaque;
 255     CPUARMState *env = &cpu->env;
 256
 257     return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8);
 258 }
 259
 260 static const VMStateDescription vmstate_m_v8m = {
 261     .name = "cpu/m/v8m",
 262     .version_id = 1,
 263     .minimum_version_id = 1,
 264     .needed = m_v8m_needed,
 265     .fields = (VMStateField[]) {
 266         VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
 267         VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
 268         VMSTATE_END_OF_LIST()
 269     }
 270 };
 271
 272 static const VMStateDescription vmstate_m = {
 273     .name = "cpu/m",
 274     .version_id = 4,
 275     .minimum_version_id = 4,
 276     .needed = m_needed,
 277     .fields = (VMStateField[]) {
 278         VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
 279         VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
 280         VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
 281         VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
 282         VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),
 283         VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
 284         VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
 285         VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
 286         VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
 287         VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
 288         VMSTATE_INT32(env.v7m.exception, ARMCPU),
 289         VMSTATE_END_OF_LIST()
 290     },
 291     .subsections = (const VMStateDescription*[]) {
 292         &vmstate_m_faultmask_primask,
 293         &vmstate_m_csselr,
 294         &vmstate_m_scr,
 295         &vmstate_m_other_sp,
 296         &vmstate_m_v8m,
 297         NULL
 298     }
 299 };
 300
 301 static bool thumb2ee_needed(void *opaque)
 302 {
 303     ARMCPU *cpu = opaque;
 304     CPUARMState *env = &cpu->env;
 305
 306     return arm_feature(env, ARM_FEATURE_THUMB2EE);
 307 }
 308
 309 static const VMStateDescription vmstate_thumb2ee = {
 310     .name = "cpu/thumb2ee",
 311     .version_id = 1,
 312     .minimum_version_id = 1,
 313     .needed = thumb2ee_needed,
 314     .fields = (VMStateField[]) {
 315         VMSTATE_UINT32(env.teecr, ARMCPU),
 316         VMSTATE_UINT32(env.teehbr, ARMCPU),
 317         VMSTATE_END_OF_LIST()
 318     }
 319 };
 320
 321 static bool pmsav7_needed(void *opaque)
 322 {
 323     ARMCPU *cpu = opaque;
 324     CPUARMState *env = &cpu->env;
 325
 326     return arm_feature(env, ARM_FEATURE_PMSA) &&
 327            arm_feature(env, ARM_FEATURE_V7) &&
 328            !arm_feature(env, ARM_FEATURE_V8);
 329 }
 330
 331 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
 332 {
 333     ARMCPU *cpu = opaque;
 334
 335     return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion;
 336 }
 337
 338 static const VMStateDescription vmstate_pmsav7 = {
 339     .name = "cpu/pmsav7",
 340     .version_id = 1,
 341     .minimum_version_id = 1,
 342     .needed = pmsav7_needed,
 343     .fields = (VMStateField[]) {
 344         VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
 345                               vmstate_info_uint32, uint32_t),
 346         VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
 347                               vmstate_info_uint32, uint32_t),
 348         VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
 349                               vmstate_info_uint32, uint32_t),
 350         VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
 351         VMSTATE_END_OF_LIST()
 352     }
 353 };
 354
 355 static bool pmsav7_rnr_needed(void *opaque)
 356 {
 357     ARMCPU *cpu = opaque;
 358     CPUARMState *env = &cpu->env;
 359
 360     /* For R profile cores pmsav7.rnr is migrated via the cpreg
 361      * "RGNR" definition in helper.h. For M profile we have to
 362      * migrate it separately.
 363      */
 364     return arm_feature(env, ARM_FEATURE_M);
 365 }
 366
 367 static const VMStateDescription vmstate_pmsav7_rnr = {
 368     .name = "cpu/pmsav7-rnr",
 369     .version_id = 1,
 370     .minimum_version_id = 1,
 371     .needed = pmsav7_rnr_needed,
 372     .fields = (VMStateField[]) {
 373         VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU),
 374         VMSTATE_END_OF_LIST()
 375     }
 376 };
 377
 378 static bool pmsav8_needed(void *opaque)
 379 {
 380     ARMCPU *cpu = opaque;
 381     CPUARMState *env = &cpu->env;
 382
 383     return arm_feature(env, ARM_FEATURE_PMSA) &&
 384         arm_feature(env, ARM_FEATURE_V8);
 385 }
 386
 387 static const VMStateDescription vmstate_pmsav8 = {
 388     .name = "cpu/pmsav8",
 389     .version_id = 1,
 390     .minimum_version_id = 1,
 391     .needed = pmsav8_needed,
 392     .fields = (VMStateField[]) {
 393         VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion,
 394                               0, vmstate_info_uint32, uint32_t),
 395         VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion,
 396                               0, vmstate_info_uint32, uint32_t),
 397         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
 398         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
 399         VMSTATE_END_OF_LIST()
 400     }
 401 };
 402
 403 static bool s_rnr_vmstate_validate(void *opaque, int version_id)
 404 {
 405     ARMCPU *cpu = opaque;
 406
 407     return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion;
 408 }
 409
 410 static bool sau_rnr_vmstate_validate(void *opaque, int version_id)
 411 {
 412     ARMCPU *cpu = opaque;
 413
 414     return cpu->env.sau.rnr < cpu->sau_sregion;
 415 }
 416
 417 static bool m_security_needed(void *opaque)
 418 {
 419     ARMCPU *cpu = opaque;
 420     CPUARMState *env = &cpu->env;
 421
 422     return arm_feature(env, ARM_FEATURE_M_SECURITY);
 423 }
 424
 425 static const VMStateDescription vmstate_m_security = {
 426     .name = "cpu/m-security",
 427     .version_id = 1,
 428     .minimum_version_id = 1,
 429     .needed = m_security_needed,
 430     .fields = (VMStateField[]) {
 431         VMSTATE_UINT32(env.v7m.secure, ARMCPU),
 432         VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU),
 433         VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU),
 434         VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
 435         VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
 436         VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
 437         VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
 438         VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
 439         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
 440         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
 441         VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,
 442                               0, vmstate_info_uint32, uint32_t),
 443         VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,
 444                               0, vmstate_info_uint32, uint32_t),
 445         VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
 446         VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
 447         VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
 448         VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
 449         VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
 450         VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
 451         VMSTATE_UINT32(env.v7m.sfsr, ARMCPU),
 452         VMSTATE_UINT32(env.v7m.sfar, ARMCPU),
 453         VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0,
 454                               vmstate_info_uint32, uint32_t),
 455         VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0,
 456                               vmstate_info_uint32, uint32_t),
 457         VMSTATE_UINT32(env.sau.rnr, ARMCPU),
 458         VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),
 459         VMSTATE_UINT32(env.sau.ctrl, ARMCPU),
 460         VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),
 461         /* AIRCR is not secure-only, but our implementation is R/O if the
 462          * security extension is unimplemented, so we migrate it here.
 463          */
 464         VMSTATE_UINT32(env.v7m.aircr, ARMCPU),
 465         VMSTATE_END_OF_LIST()
 466     }
 467 };
 468
 469 static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
 470                     VMStateField *field)
 471 {
 472     ARMCPU *cpu = opaque;
 473     CPUARMState *env = &cpu->env;
 474     uint32_t val = qemu_get_be32(f);
 475
 476     if (arm_feature(env, ARM_FEATURE_M)) {
 477         if (val & XPSR_EXCP) {
 478             /* This is a CPSR format value from an older QEMU. (We can tell
 479              * because values transferred in XPSR format always have zero
 480              * for the EXCP field, and CPSR format will always have bit 4
 481              * set in CPSR_M.) Rearrange it into XPSR format. The significant
 482              * differences are that the T bit is not in the same place, the
 483              * primask/faultmask info may be in the CPSR I and F bits, and
 484              * we do not want the mode bits.
 485              * We know that this cleanup happened before v8M, so there
 486              * is no complication with banked primask/faultmask.
 487              */
 488             uint32_t newval = val;
 489
 490             assert(!arm_feature(env, ARM_FEATURE_M_SECURITY));
 491
 492             newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);
 493             if (val & CPSR_T) {
 494                 newval |= XPSR_T;
 495             }
 496             /* If the I or F bits are set then this is a migration from
 497              * an old QEMU which still stored the M profile FAULTMASK
 498              * and PRIMASK in env->daif. For a new QEMU, the data is
 499              * transferred using the vmstate_m_faultmask_primask subsection.
 500              */
 501             if (val & CPSR_F) {
 502                 env->v7m.faultmask[M_REG_NS] = 1;
 503             }
 504             if (val & CPSR_I) {
 505                 env->v7m.primask[M_REG_NS] = 1;
 506             }
 507             val = newval;
 508         }
 509         /* Ignore the low bits, they are handled by vmstate_m. */
 510         xpsr_write(env, val, ~XPSR_EXCP);
 511         return 0;
 512     }
 513
 514     env->aarch64 = ((val & PSTATE_nRW) == 0);
 515
 516     if (is_a64(env)) {
 517         pstate_write(env, val);
 518         return 0;
 519     }
 520
 521     cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
 522     return 0;
 523 }
 524
 525 static int put_cpsr(QEMUFile *f, void *opaque, size_t size,
 526                     VMStateField *field, QJSON *vmdesc)
 527 {
 528     ARMCPU *cpu = opaque;
 529     CPUARMState *env = &cpu->env;
 530     uint32_t val;
 531
 532     if (arm_feature(env, ARM_FEATURE_M)) {
 533         /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */
 534         val = xpsr_read(env) & ~XPSR_EXCP;
 535     } else if (is_a64(env)) {
 536         val = pstate_read(env);
 537     } else {
 538         val = cpsr_read(env);
 539     }
 540
 541     qemu_put_be32(f, val);
 542     return 0;
 543 }
 544
 545 static const VMStateInfo vmstate_cpsr = {
 546     .name = "cpsr",
 547     .get = get_cpsr,
 548     .put = put_cpsr,
 549 };
 550
 551 static int get_power(QEMUFile *f, void *opaque, size_t size,
 552                     VMStateField *field)
 553 {
 554     ARMCPU *cpu = opaque;
 555     bool powered_off = qemu_get_byte(f);
 556     cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON;
 557     return 0;
 558 }
 559
 560 static int put_power(QEMUFile *f, void *opaque, size_t size,
 561                     VMStateField *field, QJSON *vmdesc)
 562 {
 563     ARMCPU *cpu = opaque;
 564
 565     /* Migration should never happen while we transition power states */
 566
 567     if (cpu->power_state == PSCI_ON ||
 568         cpu->power_state == PSCI_OFF) {
 569         bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false;
 570         qemu_put_byte(f, powered_off);
 571         return 0;
 572     } else {
 573         return 1;
 574     }
 575 }
 576
 577 static const VMStateInfo vmstate_powered_off = {
 578     .name = "powered_off",
 579     .get = get_power,
 580     .put = put_power,
 581 };
 582
 583 static int cpu_pre_save(void *opaque)
 584 {
 585     ARMCPU *cpu = opaque;
 586
 587     if (kvm_enabled()) {
 588         if (!write_kvmstate_to_list(cpu)) {
 589             /* This should never fail */
 590             abort();
 591         }
 592     } else {
 593         if (!write_cpustate_to_list(cpu)) {
 594             /* This should never fail. */
 595             abort();
 596         }
 597     }
 598
 599     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 600     memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
 601            cpu->cpreg_array_len * sizeof(uint64_t));
 602     memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
 603            cpu->cpreg_array_len * sizeof(uint64_t));
 604
 605     return 0;
 606 }
 607
 608 static int cpu_post_load(void *opaque, int version_id)
 609 {
 610     ARMCPU *cpu = opaque;
 611     int i, v;
 612
 613     /* Update the values list from the incoming migration data.
 614      * Anything in the incoming data which we don't know about is
 615      * a migration failure; anything we know about but the incoming
 616      * data doesn't specify retains its current (reset) value.
 617      * The indexes list remains untouched -- we only inspect the
 618      * incoming migration index list so we can match the values array
 619      * entries with the right slots in our own values array.
 620      */
 621
 622     for (i = 0, v = 0; i < cpu->cpreg_array_len
 623              && v < cpu->cpreg_vmstate_array_len; i++) {
 624         if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
 625             /* register in our list but not incoming : skip it */
 626             continue;
 627         }
 628         if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
 629             /* register in their list but not ours: fail migration */
 630             return -1;
 631         }
 632         /* matching register, copy the value over */
 633         cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
 634         v++;
 635     }
 636
 637     if (kvm_enabled()) {
 638         if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
 639             return -1;
 640         }
 641         /* Note that it's OK for the TCG side not to know about
 642          * every register in the list; KVM is authoritative if
 643          * we're using it.
 644          */
 645         write_list_to_cpustate(cpu);
 646     } else {
 647         if (!write_list_to_cpustate(cpu)) {
 648             return -1;
 649         }
 650     }
 651
 652     hw_breakpoint_update_all(cpu);
 653     hw_watchpoint_update_all(cpu);
 654
 655     return 0;
 656 }
 657
 658 const VMStateDescription vmstate_arm_cpu = {
 659     .name = "cpu",
 660     .version_id = 22,
 661     .minimum_version_id = 22,
 662     .pre_save = cpu_pre_save,
 663     .post_load = cpu_post_load,
 664     .fields = (VMStateField[]) {
 665         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
 666         VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
 667         VMSTATE_UINT64(env.pc, ARMCPU),
 668         {
 669             .name = "cpsr",
 670             .version_id = 0,
 671             .size = sizeof(uint32_t),
 672             .info = &vmstate_cpsr,
 673             .flags = VMS_SINGLE,
 674             .offset = 0,
 675         },
 676         VMSTATE_UINT32(env.spsr, ARMCPU),
 677         VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
 678         VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
 679         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
 680         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
 681         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
 682         VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
 683         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
 684         /* The length-check must come before the arrays to avoid
 685          * incoming data possibly overflowing the array.
 686          */
 687         VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
 688         VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
 689                              cpreg_vmstate_array_len,
 690                              0, vmstate_info_uint64, uint64_t),
 691         VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
 692                              cpreg_vmstate_array_len,
 693                              0, vmstate_info_uint64, uint64_t),
 694         VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
 695         VMSTATE_UINT64(env.exclusive_val, ARMCPU),
 696         VMSTATE_UINT64(env.exclusive_high, ARMCPU),
 697         VMSTATE_UINT64(env.features, ARMCPU),
 698         VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
 699         VMSTATE_UINT32(env.exception.fsr, ARMCPU),
 700         VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
 701         VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
 702         VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
 703         {
 704             .name = "power_state",
 705             .version_id = 0,
 706             .size = sizeof(bool),
 707             .info = &vmstate_powered_off,
 708             .flags = VMS_SINGLE,
 709             .offset = 0,
 710         },
 711         VMSTATE_END_OF_LIST()
 712     },
 713     .subsections = (const VMStateDescription*[]) {
 714         &vmstate_vfp,
 715         &vmstate_iwmmxt,
 716         &vmstate_m,
 717         &vmstate_thumb2ee,
 718         /* pmsav7_rnr must come before pmsav7 so that we have the
 719          * region number before we test it in the VMSTATE_VALIDATE
 720          * in vmstate_pmsav7.
 721          */
 722         &vmstate_pmsav7_rnr,
 723         &vmstate_pmsav7,
 724         &vmstate_pmsav8,
 725         &vmstate_m_security,
 726 #ifdef TARGET_AARCH64
 727         &vmstate_sve,
 728 #endif
 729         NULL
 730     }
 731 };