target/arm/neon-dp.decode

   1 # AArch32 Neon data-processing instruction descriptions
   2 #
   3 #  Copyright (c) 2020 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21 # VFP/Neon register fields; same as vfp.decode
  22 %vm_dp  5:1 0:4
  23 %vn_dp  7:1 16:4
  24 %vd_dp  22:1 12:4
  25
  26 # Encodings for Neon data processing instructions where the T32 encoding
  27 # is a simple transformation of the A32 encoding.
  28 # More specifically, this file covers instructions where the A32 encoding is
  29 #   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
  30 # and the T32 encoding is
  31 #   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
  32 # This file works on the A32 encoding only; calling code for T32 has to
  33 # transform the insn into the A32 version first.
  34
  35 ######################################################################
  36 # 3-reg-same grouping:
  37 # 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
  38 ######################################################################
  39
  40 &3same vm vn vd q size
  41
  42 @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
  43                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
  44
  45 @3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
  46                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
  47
  48 # For FP insns the high bit of 'size' is used as part of opcode decode
  49 @3same_fp        .... ... . . . . size:1 .... .... .... . q:1 . . .... \
  50                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
  51 @3same_fp_q0     .... ... . . . . size:1 .... .... .... . 0 . . .... \
  52                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
  53
  54 VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
  55 VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
  56 VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
  57 VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
  58
  59 VRHADD_S_3s      1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
  60 VRHADD_U_3s      1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
  61
  62 @3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
  63                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
  64
  65 VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
  66 VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
  67 VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
  68 VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
  69 VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
  70 VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
  71 VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
  72 VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
  73
  74 VHSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
  75 VHSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
  76
  77 VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
  78 VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
  79
  80 VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
  81 VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
  82 VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
  83 VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
  84
  85 # The _rev suffix indicates that Vn and Vm are reversed. This is
  86 # the case for shifts. In the Arm ARM these insns are documented
  87 # with the Vm and Vn fields in their usual places, but in the
  88 # assembly the operands are listed "backwards", ie in the order
  89 # Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
  90 # to consider Vm and Vn as being in different fields in the insn,
  91 # which allows us to avoid special-casing shifts in the trans_
  92 # function code. We would otherwise need to manually swap the operands
  93 # over to call Neon helper functions that are shared with AArch64,
  94 # which does not have this odd reversed-operand situation.
  95 @3same_rev       .... ... . . . size:2 .... .... .... . q:1 . . .... \
  96                  &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
  97
  98 VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
  99 VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
 100
 101 # Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
 102 # The _rev suffix indicates that Vn and Vm are reversed (as explained
 103 # by the comment for the @3same_rev format).
 104 @3same_64_rev    .... ... . . . 11 .... .... .... . q:1 . . .... \
 105                  &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
 106
 107 {
 108   VQSHL_S64_3s   1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
 109   VQSHL_S_3s     1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
 110 }
 111 {
 112   VQSHL_U64_3s   1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
 113   VQSHL_U_3s     1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
 114 }
 115 {
 116   VRSHL_S64_3s   1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
 117   VRSHL_S_3s     1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
 118 }
 119 {
 120   VRSHL_U64_3s   1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
 121   VRSHL_U_3s     1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
 122 }
 123 {
 124   VQRSHL_S64_3s  1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
 125   VQRSHL_S_3s    1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
 126 }
 127 {
 128   VQRSHL_U64_3s  1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
 129   VQRSHL_U_3s    1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
 130 }
 131
 132 VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
 133 VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
 134 VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
 135 VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
 136
 137 VABD_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
 138 VABD_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
 139
 140 VABA_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
 141 VABA_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
 142
 143 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 144 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
 145
 146 VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
 147 VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
 148
 149 VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
 150 VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
 151
 152 VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
 153 VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
 154
 155 VPMAX_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
 156 VPMAX_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
 157
 158 VPMIN_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
 159 VPMIN_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
 160
 161 VQDMULH_3s       1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
 162 VQRDMULH_3s      1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
 163
 164 VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
 165
 166 VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
 167
 168 @3same_crypto    .... .... .... .... .... .... .... .... \
 169                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
 170
 171 SHA1C_3s         1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 172 SHA1P_3s         1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 173 SHA1M_3s         1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
 174 SHA1SU0_3s       1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
 175 SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 176 SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 177 SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
 178
 179 VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
 180 VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
 181
 182 VQRDMLSH_3s      1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
 183
 184 VADD_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
 185 VSUB_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
 186 VPADD_fp_3s      1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
 187 VABD_fp_3s       1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
 188 VMLA_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
 189 VMLS_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
 190 VMUL_fp_3s       1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
 191 VCEQ_fp_3s       1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
 192 VCGE_fp_3s       1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
 193 VACGE_fp_3s      1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
 194 VCGT_fp_3s       1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
 195 VACGT_fp_3s      1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
 196 VMAX_fp_3s       1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
 197 VMIN_fp_3s       1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
 198 VPMAX_fp_3s      1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
 199 VPMIN_fp_3s      1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
 200 VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
 201 VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 202 VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
 203 VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 204
 205 ######################################################################
 206 # 2-reg-and-shift grouping:
 207 # 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
 208 ######################################################################
 209 &2reg_shift vm vd q shift size
 210
 211 # Right shifts are encoded as N - shift, where N is the element size in bits.
 212 %neon_rshift_i6  16:6 !function=rsub_64
 213 %neon_rshift_i5  16:5 !function=rsub_32
 214 %neon_rshift_i4  16:4 !function=rsub_16
 215 %neon_rshift_i3  16:3 !function=rsub_8
 216
 217 @2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
 218                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
 219 @2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
 220                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
 221 @2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
 222                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
 223 @2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
 224                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
 225
 226 @2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
 227                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3
 228 @2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
 229                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2
 230 @2reg_shl_h      .... ... . . . 01 shift:4   .... .... 0 q:1 . . .... \
 231                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1
 232 @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
 233                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 234
 235 # Narrowing right shifts: here the Q bit is part of the opcode decode
 236 @2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
 237                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
 238                  shift=%neon_rshift_i5
 239 @2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
 240                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
 241                  shift=%neon_rshift_i4
 242 @2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
 243                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
 244                  shift=%neon_rshift_i3
 245
 246 # Long left shifts: again Q is part of opcode decode
 247 @2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
 248                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
 249 @2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
 250                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
 251 @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
 252                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 253
 254 # We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
 255 @2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
 256                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
 257
 258 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 259 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 260 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
 261 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
 262
 263 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 264 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 265 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
 266 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
 267
 268 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
 269 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
 270 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
 271 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
 272
 273 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
 274 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
 275 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
 276 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
 277
 278 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
 279 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
 280 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
 281 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
 282
 283 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
 284 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
 285 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
 286 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
 287
 288 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
 289 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
 290 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
 291 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
 292
 293 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
 294 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
 295 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
 296 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
 297
 298 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
 299 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
 300 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
 301 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
 302
 303 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 304 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 305 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 306 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 307
 308 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 309 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 310 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 311 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 312
 313 VQSHLU_64_2sh    1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
 314 VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
 315 VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
 316 VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
 317
 318 VQSHL_S_64_2sh   1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 319 VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 320 VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 321 VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 322
 323 VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 324 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 325 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 326 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 327
 328 VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
 329 VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
 330 VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 331
 332 VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 333 VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 334 VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
 335
 336 VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
 337 VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
 338 VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 339
 340 VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 341 VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 342 VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
 343
 344 # VQSHRN with signed input
 345 VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
 346 VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
 347 VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
 348
 349 # VQRSHRN with signed input
 350 VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
 351 VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 352 VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 353
 354 # VQSHRN with unsigned input
 355 VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
 356 VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
 357 VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
 358
 359 # VQRSHRN with unsigned input
 360 VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
 361 VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 362 VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 363
 364 VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 365 VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 366 VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 367
 368 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 369 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 370 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 371
 372 # VCVT fixed<->float conversions
 373 # TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
 374 VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
 375 VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
 376 VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 377 VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 378
 379 ######################################################################
 380 # 1-reg-and-modified-immediate grouping:
 381 # 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
 382 ######################################################################
 383
 384 &1reg_imm        vd q imm cmode op
 385
 386 %asimd_imm_value 24:1 16:3 0:4
 387
 388 @1reg_imm        .... ... . . . ... ... .... .... . q:1 . . .... \
 389                  &1reg_imm imm=%asimd_imm_value vd=%vd_dp
 390
 391 # The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
 392 # not in a way we can conveniently represent in decodetree without
 393 # a lot of repetition:
 394 # VORR: op=0, (cmode & 1) && cmode < 12
 395 # VBIC: op=1, (cmode & 1) && cmode < 12
 396 # VMOV: everything else
 397 # So we have a single decode line and check the cmode/op in the
 398 # trans function.
 399 Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
 400
 401 ######################################################################
 402 # Within the "two registers, or three registers of different lengths"
 403 # grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
 404 # decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
 405 # or they are a size field for the three-reg-different-lengths and
 406 # two-reg-and-scalar insn groups (where size cannot be 0b11). This
 407 # is slightly awkward for decodetree: we handle it with this
 408 # non-exclusive group which contains within it two exclusive groups:
 409 # one for the size=0b11 patterns, and one for the size-not-0b11
 410 # patterns. This allows us to check that none of the insns within
 411 # each subgroup accidentally overlap each other. Note that all the
 412 # trans functions for the size-not-0b11 patterns must check and
 413 # return false for size==3.
 414 ######################################################################
 415 {
 416   [
 417     ##################################################################
 418     # Miscellaneous size=0b11 insns
 419     ##################################################################
 420     VEXT         1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \
 421                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
 422
 423     VTBL         1111 001 1 1 . 11 .... .... 10 len:2 . op:1 . 0 .... \
 424                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
 425
 426     VDUP_scalar  1111 001 1 1 . 11 index:3 1 .... 11 000 q:1 . 0 .... \
 427                  vm=%vm_dp vd=%vd_dp size=0
 428     VDUP_scalar  1111 001 1 1 . 11 index:2 10 .... 11 000 q:1 . 0 .... \
 429                  vm=%vm_dp vd=%vd_dp size=1
 430     VDUP_scalar  1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
 431                  vm=%vm_dp vd=%vd_dp size=2
 432
 433     ##################################################################
 434     # 2-reg-misc grouping:
 435     # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
 436     ##################################################################
 437
 438     &2misc vd vm q size
 439
 440     @2misc       .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
 441                  &2misc vm=%vm_dp vd=%vd_dp
 442     @2misc_q0    .... ... .. . .. size:2 .. .... . .... . . . .... \
 443                  &2misc vm=%vm_dp vd=%vd_dp q=0
 444
 445     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
 446
 447     VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
 448     VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
 449
 450     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
 451     VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
 452
 453     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
 454     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
 455
 456     VMOVN        1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0
 457     # VQMOVUN: unsigned result (source is always signed)
 458     VQMOVUN      1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0
 459     # VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
 460     VQMOVN_S     1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
 461     VQMOVN_U     1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
 462   ]
 463
 464   # Subgroup for size != 0b11
 465   [
 466     ##################################################################
 467     # 3-reg-different-length grouping:
 468     # 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4
 469     ##################################################################
 470
 471     &3diff vm vn vd size
 472
 473     @3diff       .... ... . . . size:2 .... .... .... . . . . .... \
 474                  &3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp
 475
 476     VADDL_S_3d   1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff
 477     VADDL_U_3d   1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff
 478
 479     VADDW_S_3d   1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff
 480     VADDW_U_3d   1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff
 481
 482     VSUBL_S_3d   1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff
 483     VSUBL_U_3d   1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff
 484
 485     VSUBW_S_3d   1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
 486     VSUBW_U_3d   1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
 487
 488     VADDHN_3d    1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
 489     VRADDHN_3d   1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
 490
 491     VABAL_S_3d   1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff
 492     VABAL_U_3d   1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff
 493
 494     VSUBHN_3d    1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
 495     VRSUBHN_3d   1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
 496
 497     VABDL_S_3d   1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff
 498     VABDL_U_3d   1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff
 499
 500     VMLAL_S_3d   1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff
 501     VMLAL_U_3d   1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff
 502
 503     VQDMLAL_3d   1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff
 504
 505     VMLSL_S_3d   1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff
 506     VMLSL_U_3d   1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff
 507
 508     VQDMLSL_3d   1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff
 509
 510     VMULL_S_3d   1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff
 511     VMULL_U_3d   1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff
 512
 513     VQDMULL_3d   1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff
 514
 515     VMULL_P_3d   1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff
 516
 517     ##################################################################
 518     # 2-regs-plus-scalar grouping:
 519     # 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4
 520     ##################################################################
 521     &2scalar vm vn vd size q
 522
 523     @2scalar     .... ... q:1 . . size:2 .... .... .... . . . . .... \
 524                  &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
 525     # For the 'long' ops the Q bit is part of insn decode
 526     @2scalar_q0  .... ... . . . size:2 .... .... .... . . . . .... \
 527                  &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
 528
 529     VMLA_2sc     1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
 530     VMLA_F_2sc   1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
 531
 532     VMLAL_S_2sc  1111 001 0 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
 533     VMLAL_U_2sc  1111 001 1 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
 534
 535     VQDMLAL_2sc  1111 001 0 1 . .. .... .... 0011 . 1 . 0 .... @2scalar_q0
 536
 537     VMLS_2sc     1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
 538     VMLS_F_2sc   1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
 539
 540     VMLSL_S_2sc  1111 001 0 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
 541     VMLSL_U_2sc  1111 001 1 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
 542
 543     VQDMLSL_2sc  1111 001 0 1 . .. .... .... 0111 . 1 . 0 .... @2scalar_q0
 544
 545     VMUL_2sc     1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
 546     VMUL_F_2sc   1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
 547
 548     VMULL_S_2sc  1111 001 0 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
 549     VMULL_U_2sc  1111 001 1 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
 550
 551     VQDMULL_2sc  1111 001 0 1 . .. .... .... 1011 . 1 . 0 .... @2scalar_q0
 552
 553     VQDMULH_2sc  1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar
 554     VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar
 555
 556     VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar
 557     VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar
 558   ]
 559 }