target/arm/neon-dp.decode

   1 # AArch32 Neon data-processing instruction descriptions
   2 #
   3 #  Copyright (c) 2020 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2.1 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21 # VFP/Neon register fields; same as vfp.decode
  22 %vm_dp  5:1 0:4
  23 %vn_dp  7:1 16:4
  24 %vd_dp  22:1 12:4
  25
  26 # Encodings for Neon data processing instructions where the T32 encoding
  27 # is a simple transformation of the A32 encoding.
  28 # More specifically, this file covers instructions where the A32 encoding is
  29 #   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
  30 # and the T32 encoding is
  31 #   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
  32 # This file works on the A32 encoding only; calling code for T32 has to
  33 # transform the insn into the A32 version first.
  34
  35 ######################################################################
  36 # 3-reg-same grouping:
  37 # 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
  38 ######################################################################
  39
  40 &3same vm vn vd q size
  41
  42 @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
  43                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
  44
  45 @3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
  46                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
  47
  48 # For FP insns the high bit of 'size' is used as part of opcode decode,
  49 # and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
  50 # This converts this encoding to the same MO_8/16/32/64 values that the
  51 # integer neon insns use.
  52 %3same_fp_size   20:1 !function=neon_3same_fp_size
  53
  54 @3same_fp        .... ... . . . . . .... .... .... . q:1 . . .... \
  55                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
  56 @3same_fp_q0     .... ... . . . . . .... .... .... . 0 . . .... \
  57                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 size=%3same_fp_size
  58
  59 VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
  60 VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
  61 VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
  62 VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
  63
  64 VRHADD_S_3s      1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
  65 VRHADD_U_3s      1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
  66
  67 @3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
  68                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
  69
  70 VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
  71 VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
  72 VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
  73 VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
  74 VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
  75 VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
  76 VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
  77 VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
  78
  79 VHSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
  80 VHSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
  81
  82 VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
  83 VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
  84
  85 VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
  86 VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
  87 VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
  88 VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
  89
  90 # The _rev suffix indicates that Vn and Vm are reversed. This is
  91 # the case for shifts. In the Arm ARM these insns are documented
  92 # with the Vm and Vn fields in their usual places, but in the
  93 # assembly the operands are listed "backwards", ie in the order
  94 # Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
  95 # to consider Vm and Vn as being in different fields in the insn,
  96 # which allows us to avoid special-casing shifts in the trans_
  97 # function code. We would otherwise need to manually swap the operands
  98 # over to call Neon helper functions that are shared with AArch64,
  99 # which does not have this odd reversed-operand situation.
 100 @3same_rev       .... ... . . . size:2 .... .... .... . q:1 . . .... \
 101                  &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
 102
 103 VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
 104 VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
 105
 106 # Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
 107 # The _rev suffix indicates that Vn and Vm are reversed (as explained
 108 # by the comment for the @3same_rev format).
 109 @3same_64_rev    .... ... . . . 11 .... .... .... . q:1 . . .... \
 110                  &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
 111
 112 {
 113   VQSHL_S64_3s   1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
 114   VQSHL_S_3s     1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
 115 }
 116 {
 117   VQSHL_U64_3s   1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
 118   VQSHL_U_3s     1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
 119 }
 120 {
 121   VRSHL_S64_3s   1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
 122   VRSHL_S_3s     1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
 123 }
 124 {
 125   VRSHL_U64_3s   1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
 126   VRSHL_U_3s     1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
 127 }
 128 {
 129   VQRSHL_S64_3s  1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
 130   VQRSHL_S_3s    1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
 131 }
 132 {
 133   VQRSHL_U64_3s  1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
 134   VQRSHL_U_3s    1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
 135 }
 136
 137 VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
 138 VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
 139 VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
 140 VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
 141
 142 VABD_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
 143 VABD_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
 144
 145 VABA_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
 146 VABA_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
 147
 148 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 149 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
 150
 151 VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
 152 VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
 153
 154 VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
 155 VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
 156
 157 VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
 158 VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
 159
 160 VPMAX_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
 161 VPMAX_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
 162
 163 VPMIN_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
 164 VPMIN_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
 165
 166 VQDMULH_3s       1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
 167 VQRDMULH_3s      1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
 168
 169 VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
 170
 171 VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
 172
 173 @3same_crypto    .... .... .... .... .... .... .... .... \
 174                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
 175
 176 SHA1C_3s         1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 177 SHA1P_3s         1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 178 SHA1M_3s         1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
 179 SHA1SU0_3s       1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
 180 SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 181 SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 182 SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
 183
 184 VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
 185 VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
 186
 187 VQRDMLSH_3s      1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
 188
 189 VADD_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
 190 VSUB_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
 191 VPADD_fp_3s      1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
 192 VABD_fp_3s       1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
 193 VMLA_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
 194 VMLS_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
 195 VMUL_fp_3s       1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
 196 VCEQ_fp_3s       1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
 197 VCGE_fp_3s       1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
 198 VACGE_fp_3s      1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
 199 VCGT_fp_3s       1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
 200 VACGT_fp_3s      1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
 201 VMAX_fp_3s       1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
 202 VMIN_fp_3s       1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
 203 VPMAX_fp_3s      1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
 204 VPMIN_fp_3s      1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
 205 VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
 206 VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 207 VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
 208 VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 209
 210 ######################################################################
 211 # 2-reg-and-shift grouping:
 212 # 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
 213 ######################################################################
 214 &2reg_shift vm vd q shift size
 215
 216 # Right shifts are encoded as N - shift, where N is the element size in bits.
 217 %neon_rshift_i6  16:6 !function=rsub_64
 218 %neon_rshift_i5  16:5 !function=rsub_32
 219 %neon_rshift_i4  16:4 !function=rsub_16
 220 %neon_rshift_i3  16:3 !function=rsub_8
 221
 222 @2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
 223                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
 224 @2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
 225                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
 226 @2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
 227                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
 228 @2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
 229                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
 230
 231 @2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
 232                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3
 233 @2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
 234                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2
 235 @2reg_shl_h      .... ... . . . 01 shift:4   .... .... 0 q:1 . . .... \
 236                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1
 237 @2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
 238                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0
 239
 240 # Narrowing right shifts: here the Q bit is part of the opcode decode
 241 @2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
 242                  &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
 243                  shift=%neon_rshift_i5
 244 @2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
 245                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
 246                  shift=%neon_rshift_i4
 247 @2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
 248                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
 249                  shift=%neon_rshift_i3
 250
 251 # Long left shifts: again Q is part of opcode decode
 252 @2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
 253                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
 254 @2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
 255                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
 256 @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
 257                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 258
 259 @2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
 260                  &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
 261 @2reg_vcvt_f16   .... ... . . . 11 .... .... .... . q:1 . . .... \
 262                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
 263
 264 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 265 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 266 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
 267 VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
 268
 269 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
 270 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
 271 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
 272 VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
 273
 274 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
 275 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
 276 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
 277 VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
 278
 279 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
 280 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
 281 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
 282 VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
 283
 284 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
 285 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
 286 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
 287 VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
 288
 289 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
 290 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
 291 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
 292 VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
 293
 294 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
 295 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
 296 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
 297 VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
 298
 299 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
 300 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
 301 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
 302 VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
 303
 304 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
 305 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
 306 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
 307 VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
 308
 309 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 310 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 311 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 312 VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 313
 314 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
 315 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
 316 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
 317 VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
 318
 319 VQSHLU_64_2sh    1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
 320 VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
 321 VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
 322 VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
 323
 324 VQSHL_S_64_2sh   1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 325 VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 326 VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 327 VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 328
 329 VQSHL_U_64_2sh   1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
 330 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
 331 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
 332 VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
 333
 334 VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
 335 VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
 336 VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 337
 338 VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 339 VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 340 VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
 341
 342 VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
 343 VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
 344 VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
 345
 346 VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
 347 VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
 348 VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
 349
 350 # VQSHRN with signed input
 351 VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
 352 VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
 353 VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
 354
 355 # VQRSHRN with signed input
 356 VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
 357 VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 358 VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 359
 360 # VQSHRN with unsigned input
 361 VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
 362 VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
 363 VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
 364
 365 # VQRSHRN with unsigned input
 366 VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
 367 VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
 368 VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
 369
 370 VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 371 VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 372 VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 373
 374 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
 375 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
 376 VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
 377
 378 # VCVT fixed<->float conversions
 379 VCVT_SH_2sh      1111 001 0 1 . ...... .... 1100 0 . . 1 .... @2reg_vcvt_f16
 380 VCVT_UH_2sh      1111 001 1 1 . ...... .... 1100 0 . . 1 .... @2reg_vcvt_f16
 381 VCVT_HS_2sh      1111 001 0 1 . ...... .... 1101 0 . . 1 .... @2reg_vcvt_f16
 382 VCVT_HU_2sh      1111 001 1 1 . ...... .... 1101 0 . . 1 .... @2reg_vcvt_f16
 383
 384 VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
 385 VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
 386 VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 387 VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
 388
 389 ######################################################################
 390 # 1-reg-and-modified-immediate grouping:
 391 # 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
 392 ######################################################################
 393
 394 &1reg_imm        vd q imm cmode op
 395
 396 %asimd_imm_value 24:1 16:3 0:4
 397
 398 @1reg_imm        .... ... . . . ... ... .... .... . q:1 . . .... \
 399                  &1reg_imm imm=%asimd_imm_value vd=%vd_dp
 400
 401 # The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
 402 # not in a way we can conveniently represent in decodetree without
 403 # a lot of repetition:
 404 # VORR: op=0, (cmode & 1) && cmode < 12
 405 # VBIC: op=1, (cmode & 1) && cmode < 12
 406 # VMOV: everything else
 407 # So we have a single decode line and check the cmode/op in the
 408 # trans function.
 409 Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
 410
 411 ######################################################################
 412 # Within the "two registers, or three registers of different lengths"
 413 # grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
 414 # decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
 415 # or they are a size field for the three-reg-different-lengths and
 416 # two-reg-and-scalar insn groups (where size cannot be 0b11). This
 417 # is slightly awkward for decodetree: we handle it with this
 418 # non-exclusive group which contains within it two exclusive groups:
 419 # one for the size=0b11 patterns, and one for the size-not-0b11
 420 # patterns. This allows us to check that none of the insns within
 421 # each subgroup accidentally overlap each other. Note that all the
 422 # trans functions for the size-not-0b11 patterns must check and
 423 # return false for size==3.
 424 ######################################################################
 425 {
 426   [
 427     ##################################################################
 428     # Miscellaneous size=0b11 insns
 429     ##################################################################
 430     VEXT         1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \
 431                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
 432
 433     VTBL         1111 001 1 1 . 11 .... .... 10 len:2 . op:1 . 0 .... \
 434                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
 435
 436     VDUP_scalar  1111 001 1 1 . 11 index:3 1 .... 11 000 q:1 . 0 .... \
 437                  vm=%vm_dp vd=%vd_dp size=0
 438     VDUP_scalar  1111 001 1 1 . 11 index:2 10 .... 11 000 q:1 . 0 .... \
 439                  vm=%vm_dp vd=%vd_dp size=1
 440     VDUP_scalar  1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
 441                  vm=%vm_dp vd=%vd_dp size=2
 442
 443     ##################################################################
 444     # 2-reg-misc grouping:
 445     # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
 446     ##################################################################
 447
 448     &2misc vd vm q size
 449
 450     @2misc       .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
 451                  &2misc vm=%vm_dp vd=%vd_dp
 452     @2misc_q0    .... ... .. . .. size:2 .. .... . .... . . . .... \
 453                  &2misc vm=%vm_dp vd=%vd_dp q=0
 454     @2misc_q1    .... ... .. . .. size:2 .. .... . .... . . . .... \
 455                  &2misc vm=%vm_dp vd=%vd_dp q=1
 456
 457     VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
 458     VREV32       1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc
 459     VREV16       1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc
 460
 461     VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
 462     VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
 463
 464     AESE         1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1
 465     AESD         1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1
 466     AESMC        1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
 467     AESIMC       1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
 468
 469     VCLS         1111 001 11 . 11 .. 00 .... 0 1000 . . 0 .... @2misc
 470     VCLZ         1111 001 11 . 11 .. 00 .... 0 1001 . . 0 .... @2misc
 471     VCNT         1111 001 11 . 11 .. 00 .... 0 1010 . . 0 .... @2misc
 472
 473     VMVN         1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
 474
 475     VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
 476     VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
 477
 478     VQABS        1111 001 11 . 11 .. 00 .... 0 1110 . . 0 .... @2misc
 479     VQNEG        1111 001 11 . 11 .. 00 .... 0 1111 . . 0 .... @2misc
 480
 481     VCGT0        1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc
 482     VCGE0        1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc
 483     VCEQ0        1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc
 484     VCLE0        1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
 485     VCLT0        1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
 486
 487     SHA1H        1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1
 488
 489     VABS         1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
 490     VNEG         1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
 491
 492     VCGT0_F      1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc
 493     VCGE0_F      1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc
 494     VCEQ0_F      1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc
 495     VCLE0_F      1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc
 496     VCLT0_F      1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc
 497
 498     VABS_F       1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
 499     VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
 500
 501     VSWP         1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
 502     VTRN         1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc
 503     VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
 504     VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
 505
 506     VMOVN        1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0
 507     # VQMOVUN: unsigned result (source is always signed)
 508     VQMOVUN      1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0
 509     # VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
 510     VQMOVN_S     1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
 511     VQMOVN_U     1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
 512
 513     VSHLL        1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
 514
 515     SHA1SU1      1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
 516     SHA256SU0    1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
 517
 518     VRINTN       1111 001 11 . 11 .. 10 .... 0 1000 . . 0 .... @2misc
 519     VRINTX       1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
 520     VRINTA       1111 001 11 . 11 .. 10 .... 0 1010 . . 0 .... @2misc
 521     VRINTZ       1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc
 522
 523     VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
 524
 525     VRINTM       1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc
 526
 527     VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
 528
 529     VRINTP       1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc
 530
 531     VCVTAS       1111 001 11 . 11 .. 11 .... 0 0000 . . 0 .... @2misc
 532     VCVTAU       1111 001 11 . 11 .. 11 .... 0 0001 . . 0 .... @2misc
 533     VCVTNS       1111 001 11 . 11 .. 11 .... 0 0010 . . 0 .... @2misc
 534     VCVTNU       1111 001 11 . 11 .. 11 .... 0 0011 . . 0 .... @2misc
 535     VCVTPS       1111 001 11 . 11 .. 11 .... 0 0100 . . 0 .... @2misc
 536     VCVTPU       1111 001 11 . 11 .. 11 .... 0 0101 . . 0 .... @2misc
 537     VCVTMS       1111 001 11 . 11 .. 11 .... 0 0110 . . 0 .... @2misc
 538     VCVTMU       1111 001 11 . 11 .. 11 .... 0 0111 . . 0 .... @2misc
 539
 540     VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
 541     VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
 542     VRECPE_F     1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
 543     VRSQRTE_F    1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc
 544     VCVT_FS      1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc
 545     VCVT_FU      1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc
 546     VCVT_SF      1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc
 547     VCVT_UF      1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc
 548   ]
 549
 550   # Subgroup for size != 0b11
 551   [
 552     ##################################################################
 553     # 3-reg-different-length grouping:
 554     # 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4
 555     ##################################################################
 556
 557     &3diff vm vn vd size
 558
 559     @3diff       .... ... . . . size:2 .... .... .... . . . . .... \
 560                  &3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp
 561
 562     VADDL_S_3d   1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff
 563     VADDL_U_3d   1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff
 564
 565     VADDW_S_3d   1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff
 566     VADDW_U_3d   1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff
 567
 568     VSUBL_S_3d   1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff
 569     VSUBL_U_3d   1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff
 570
 571     VSUBW_S_3d   1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
 572     VSUBW_U_3d   1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
 573
 574     VADDHN_3d    1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
 575     VRADDHN_3d   1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
 576
 577     VABAL_S_3d   1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff
 578     VABAL_U_3d   1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff
 579
 580     VSUBHN_3d    1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
 581     VRSUBHN_3d   1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
 582
 583     VABDL_S_3d   1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff
 584     VABDL_U_3d   1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff
 585
 586     VMLAL_S_3d   1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff
 587     VMLAL_U_3d   1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff
 588
 589     VQDMLAL_3d   1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff
 590
 591     VMLSL_S_3d   1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff
 592     VMLSL_U_3d   1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff
 593
 594     VQDMLSL_3d   1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff
 595
 596     VMULL_S_3d   1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff
 597     VMULL_U_3d   1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff
 598
 599     VQDMULL_3d   1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff
 600
 601     VMULL_P_3d   1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff
 602
 603     ##################################################################
 604     # 2-regs-plus-scalar grouping:
 605     # 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4
 606     ##################################################################
 607     &2scalar vm vn vd size q
 608
 609     @2scalar     .... ... q:1 . . size:2 .... .... .... . . . . .... \
 610                  &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
 611     # For the 'long' ops the Q bit is part of insn decode
 612     @2scalar_q0  .... ... . . . size:2 .... .... .... . . . . .... \
 613                  &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
 614
 615     VMLA_2sc     1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
 616     VMLA_F_2sc   1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
 617
 618     VMLAL_S_2sc  1111 001 0 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
 619     VMLAL_U_2sc  1111 001 1 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
 620
 621     VQDMLAL_2sc  1111 001 0 1 . .. .... .... 0011 . 1 . 0 .... @2scalar_q0
 622
 623     VMLS_2sc     1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
 624     VMLS_F_2sc   1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
 625
 626     VMLSL_S_2sc  1111 001 0 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
 627     VMLSL_U_2sc  1111 001 1 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
 628
 629     VQDMLSL_2sc  1111 001 0 1 . .. .... .... 0111 . 1 . 0 .... @2scalar_q0
 630
 631     VMUL_2sc     1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
 632     VMUL_F_2sc   1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
 633
 634     VMULL_S_2sc  1111 001 0 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
 635     VMULL_U_2sc  1111 001 1 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
 636
 637     VQDMULL_2sc  1111 001 0 1 . .. .... .... 1011 . 1 . 0 .... @2scalar_q0
 638
 639     VQDMULH_2sc  1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar
 640     VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar
 641
 642     VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar
 643     VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar
 644   ]
 645 }