4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 static CPUState
*do_raise_exception(CPUARMState
*env
, uint32_t excp
,
32 uint32_t syndrome
, uint32_t target_el
)
34 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
36 if (target_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
38 * Redirect NS EL1 exceptions to NS EL2. These are reported with
39 * their original syndrome register value, with the exception of
40 * SIMD/FP access traps, which are reported as uncategorized
41 * (see DDI0478C.a D1.10.4)
44 if (syn_get_ec(syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
45 syndrome
= syn_uncategorized();
49 assert(!excp_is_internal(excp
));
50 cs
->exception_index
= excp
;
51 env
->exception
.syndrome
= syndrome
;
52 env
->exception
.target_el
= target_el
;
57 void raise_exception(CPUARMState
*env
, uint32_t excp
,
58 uint32_t syndrome
, uint32_t target_el
)
60 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
64 void raise_exception_ra(CPUARMState
*env
, uint32_t excp
, uint32_t syndrome
,
65 uint32_t target_el
, uintptr_t ra
)
67 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
68 cpu_loop_exit_restore(cs
, ra
);
71 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
78 for (shift
= 0; shift
< 32; shift
+= 8) {
79 uint32_t index
= (ireg
>> shift
) & 0xff;
80 if (index
< maxindex
) {
81 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
84 val
|= def
& (0xff << shift
);
90 #if !defined(CONFIG_USER_ONLY)
92 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
93 unsigned int target_el
,
94 bool same_el
, bool ea
,
95 bool s1ptw
, bool is_write
,
100 /* ISV is only set for data aborts routed to EL2 and
101 * never for stage-1 page table walks faulting on stage 2.
103 * Furthermore, ISV is only set for certain kinds of load/stores.
104 * If the template syndrome does not have ISV set, we should leave
107 * See ARMv8 specs, D7-1974:
108 * ISS encoding for an exception from a Data Abort, the
111 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
112 syn
= syn_data_abort_no_iss(same_el
,
113 ea
, 0, s1ptw
, is_write
, fsc
);
115 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
116 * syndrome created at translation time.
117 * Now we create the runtime syndrome with the remaining fields.
119 syn
= syn_data_abort_with_iss(same_el
,
121 ea
, 0, s1ptw
, is_write
, fsc
,
123 /* Merge the runtime syndrome with the template syndrome. */
129 static void deliver_fault(ARMCPU
*cpu
, vaddr addr
, MMUAccessType access_type
,
130 int mmu_idx
, ARMMMUFaultInfo
*fi
)
132 CPUARMState
*env
= &cpu
->env
;
135 uint32_t syn
, exc
, fsr
, fsc
;
136 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
138 target_el
= exception_target_el(env
);
141 env
->cp15
.hpfar_el2
= extract64(fi
->s2addr
, 12, 47) << 4;
143 same_el
= (arm_current_el(env
) == target_el
);
145 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
146 arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
147 /* LPAE format fault status register : bottom 6 bits are
148 * status code in the same form as needed for syndrome
150 fsr
= arm_fi_to_lfsc(fi
);
151 fsc
= extract32(fsr
, 0, 6);
153 fsr
= arm_fi_to_sfsc(fi
);
154 /* Short format FSR : this fault will never actually be reported
155 * to an EL that uses a syndrome register. Use a (currently)
156 * reserved FSR code in case the constructed syndrome does leak
157 * into the guest somehow.
162 if (access_type
== MMU_INST_FETCH
) {
163 syn
= syn_insn_abort(same_el
, fi
->ea
, fi
->s1ptw
, fsc
);
164 exc
= EXCP_PREFETCH_ABORT
;
166 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
167 same_el
, fi
->ea
, fi
->s1ptw
,
168 access_type
== MMU_DATA_STORE
,
170 if (access_type
== MMU_DATA_STORE
171 && arm_feature(env
, ARM_FEATURE_V6
)) {
174 exc
= EXCP_DATA_ABORT
;
177 env
->exception
.vaddress
= addr
;
178 env
->exception
.fsr
= fsr
;
179 raise_exception(env
, exc
, syn
, target_el
);
182 /* try to fill the TLB and return an exception if error. If retaddr is
183 * NULL, it means that the function was called in C code (i.e. not
184 * from generated code or from helper.c)
186 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
187 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
190 ARMMMUFaultInfo fi
= {};
192 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fi
);
194 ARMCPU
*cpu
= ARM_CPU(cs
);
196 /* now we have a real cpu fault */
197 cpu_restore_state(cs
, retaddr
, true);
199 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
203 /* Raise a data fault alignment exception for the specified virtual address */
204 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
205 MMUAccessType access_type
,
206 int mmu_idx
, uintptr_t retaddr
)
208 ARMCPU
*cpu
= ARM_CPU(cs
);
209 ARMMMUFaultInfo fi
= {};
211 /* now we have a real cpu fault */
212 cpu_restore_state(cs
, retaddr
, true);
214 fi
.type
= ARMFault_Alignment
;
215 deliver_fault(cpu
, vaddr
, access_type
, mmu_idx
, &fi
);
218 /* arm_cpu_do_transaction_failed: handle a memory system error response
219 * (eg "no device/memory present at address") by raising an external abort
222 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
223 vaddr addr
, unsigned size
,
224 MMUAccessType access_type
,
225 int mmu_idx
, MemTxAttrs attrs
,
226 MemTxResult response
, uintptr_t retaddr
)
228 ARMCPU
*cpu
= ARM_CPU(cs
);
229 ARMMMUFaultInfo fi
= {};
231 /* now we have a real cpu fault */
232 cpu_restore_state(cs
, retaddr
, true);
234 fi
.ea
= arm_extabort_type(response
);
235 fi
.type
= ARMFault_SyncExternal
;
236 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
239 #endif /* !defined(CONFIG_USER_ONLY) */
241 void HELPER(v8m_stackcheck
)(CPUARMState
*env
, uint32_t newvalue
)
244 * Perform the v8M stack limit check for SP updates from translated code,
245 * raising an exception if the limit is breached.
247 if (newvalue
< v7m_sp_limit(env
)) {
248 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
251 * Stack limit exceptions are a rare case, so rather than syncing
252 * PC/condbits before the call, we use cpu_restore_state() to
253 * get them right before raising the exception.
255 cpu_restore_state(cs
, GETPC(), true);
256 raise_exception(env
, EXCP_STKOF
, 0, 1);
260 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
262 uint32_t res
= a
+ b
;
263 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
268 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
270 uint32_t res
= a
+ b
;
271 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
273 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
278 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
280 uint32_t res
= a
- b
;
281 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
283 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
288 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
291 if (val
>= 0x40000000) {
294 } else if (val
<= (int32_t)0xc0000000) {
303 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
305 uint32_t res
= a
+ b
;
313 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
315 uint32_t res
= a
- b
;
323 /* Signed saturation. */
324 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
330 mask
= (1u << shift
) - 1;
334 } else if (top
< -1) {
341 /* Unsigned saturation. */
342 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
346 max
= (1u << shift
) - 1;
350 } else if (val
> max
) {
357 /* Signed saturate. */
358 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
360 return do_ssat(env
, x
, shift
);
363 /* Dual halfword signed saturate. */
364 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
368 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
369 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
373 /* Unsigned saturate. */
374 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
376 return do_usat(env
, x
, shift
);
379 /* Dual halfword unsigned saturate. */
380 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
384 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
385 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
389 void HELPER(setend
)(CPUARMState
*env
)
391 env
->uncached_cpsr
^= CPSR_E
;
394 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
395 * The function returns the target EL (1-3) if the instruction is to be trapped;
396 * otherwise it returns 0 indicating it is not trapped.
398 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
400 int cur_el
= arm_current_el(env
);
403 if (arm_feature(env
, ARM_FEATURE_M
)) {
404 /* M profile cores can never trap WFI/WFE. */
408 /* If we are currently in EL0 then we need to check if SCTLR is set up for
409 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
411 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
414 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
415 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
416 /* Secure EL0 and Secure PL1 is at EL3 */
422 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
427 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
428 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
429 * bits will be zero indicating no trap.
432 mask
= is_wfe
? HCR_TWE
: HCR_TWI
;
433 if (arm_hcr_el2_eff(env
) & mask
) {
438 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
440 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
441 if (env
->cp15
.scr_el3
& mask
) {
449 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
451 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
452 int target_el
= check_wfx_trap(env
, false);
454 if (cpu_has_work(cs
)) {
455 /* Don't bother to go into our "low power state" if
456 * we would just wake up immediately.
463 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
467 cs
->exception_index
= EXCP_HLT
;
472 void HELPER(wfe
)(CPUARMState
*env
)
474 /* This is a hint instruction that is semantically different
475 * from YIELD even though we currently implement it identically.
476 * Don't actually halt the CPU, just yield back to top
477 * level loop. This is not going into a "low power state"
478 * (ie halting until some event occurs), so we never take
479 * a configurable trap to a different exception level.
484 void HELPER(yield
)(CPUARMState
*env
)
486 ARMCPU
*cpu
= arm_env_get_cpu(env
);
487 CPUState
*cs
= CPU(cpu
);
489 /* This is a non-trappable hint instruction that generally indicates
490 * that the guest is currently busy-looping. Yield control back to the
491 * top level loop so that a more deserving VCPU has a chance to run.
493 cs
->exception_index
= EXCP_YIELD
;
497 /* Raise an internal-to-QEMU exception. This is limited to only
498 * those EXCP values which are special cases for QEMU to interrupt
499 * execution and not to be used for exceptions which are passed to
500 * the guest (those must all have syndrome information and thus should
501 * use exception_with_syndrome).
503 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
505 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
507 assert(excp_is_internal(excp
));
508 cs
->exception_index
= excp
;
512 /* Raise an exception with the specified syndrome register value */
513 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
514 uint32_t syndrome
, uint32_t target_el
)
516 raise_exception(env
, excp
, syndrome
, target_el
);
519 /* Raise an EXCP_BKPT with the specified syndrome register value,
520 * targeting the correct exception level for debug exceptions.
522 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
524 /* FSR will only be used if the debug target EL is AArch32. */
525 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
526 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
527 * values to the guest that it shouldn't be able to see at its
528 * exception/security level.
530 env
->exception
.vaddress
= 0;
531 raise_exception(env
, EXCP_BKPT
, syndrome
, arm_debug_target_el(env
));
534 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
536 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
539 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
541 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
544 /* Write the CPSR for a 32-bit exception return */
545 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
547 qemu_mutex_lock_iothread();
548 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
549 qemu_mutex_unlock_iothread();
551 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
553 /* Generated code has already stored the new PC value, but
554 * without masking out its low bits, because which bits need
555 * masking depends on whether we're returning to Thumb or ARM
556 * state. Do the masking now.
558 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
560 qemu_mutex_lock_iothread();
561 arm_call_el_change_hook(arm_env_get_cpu(env
));
562 qemu_mutex_unlock_iothread();
565 /* Access to user mode registers from privileged modes. */
566 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
571 val
= env
->banked_r13
[BANK_USRSYS
];
572 } else if (regno
== 14) {
573 val
= env
->banked_r14
[BANK_USRSYS
];
574 } else if (regno
>= 8
575 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
576 val
= env
->usr_regs
[regno
- 8];
578 val
= env
->regs
[regno
];
583 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
586 env
->banked_r13
[BANK_USRSYS
] = val
;
587 } else if (regno
== 14) {
588 env
->banked_r14
[BANK_USRSYS
] = val
;
589 } else if (regno
>= 8
590 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
591 env
->usr_regs
[regno
- 8] = val
;
593 env
->regs
[regno
] = val
;
597 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
599 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
602 env
->banked_r13
[bank_number(mode
)] = val
;
606 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
608 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
609 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
610 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
612 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
613 exception_target_el(env
));
616 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
617 return env
->regs
[13];
619 return env
->banked_r13
[bank_number(mode
)];
623 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
626 /* Raise an exception if the requested access is one of the UNPREDICTABLE
627 * cases; otherwise return. This broadly corresponds to the pseudocode
628 * BankedRegisterAccessValid() and SPSRAccessValid(),
629 * except that we have already handled some cases at translate time.
631 int curmode
= env
->uncached_cpsr
& CPSR_M
;
634 /* ELR_Hyp: a special case because access from tgtmode is OK */
635 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
641 if (curmode
== tgtmode
) {
645 if (tgtmode
== ARM_CPU_MODE_USR
) {
648 if (curmode
!= ARM_CPU_MODE_FIQ
) {
653 if (curmode
== ARM_CPU_MODE_SYS
) {
658 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
667 if (tgtmode
== ARM_CPU_MODE_HYP
) {
668 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
669 if (curmode
!= ARM_CPU_MODE_MON
) {
677 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
678 exception_target_el(env
));
681 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
684 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
688 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
690 case 17: /* ELR_Hyp */
691 env
->elr_el
[2] = value
;
694 env
->banked_r13
[bank_number(tgtmode
)] = value
;
697 env
->banked_r14
[r14_bank_number(tgtmode
)] = value
;
701 case ARM_CPU_MODE_USR
:
702 env
->usr_regs
[regno
- 8] = value
;
704 case ARM_CPU_MODE_FIQ
:
705 env
->fiq_regs
[regno
- 8] = value
;
708 g_assert_not_reached();
712 g_assert_not_reached();
716 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
718 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
722 return env
->banked_spsr
[bank_number(tgtmode
)];
723 case 17: /* ELR_Hyp */
724 return env
->elr_el
[2];
726 return env
->banked_r13
[bank_number(tgtmode
)];
728 return env
->banked_r14
[r14_bank_number(tgtmode
)];
731 case ARM_CPU_MODE_USR
:
732 return env
->usr_regs
[regno
- 8];
733 case ARM_CPU_MODE_FIQ
:
734 return env
->fiq_regs
[regno
- 8];
736 g_assert_not_reached();
739 g_assert_not_reached();
743 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
746 const ARMCPRegInfo
*ri
= rip
;
749 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
750 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
751 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
758 switch (ri
->accessfn(env
, ri
, isread
)) {
762 target_el
= exception_target_el(env
);
764 case CP_ACCESS_TRAP_EL2
:
765 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
766 * a bug in the access function.
768 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
771 case CP_ACCESS_TRAP_EL3
:
774 case CP_ACCESS_TRAP_UNCATEGORIZED
:
775 target_el
= exception_target_el(env
);
776 syndrome
= syn_uncategorized();
778 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
780 syndrome
= syn_uncategorized();
782 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
784 syndrome
= syn_uncategorized();
786 case CP_ACCESS_TRAP_FP_EL2
:
788 /* Since we are an implementation that takes exceptions on a trapped
789 * conditional insn only if the insn has passed its condition code
790 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
791 * (which is also the required value for AArch64 traps).
793 syndrome
= syn_fp_access_trap(1, 0xe, false);
795 case CP_ACCESS_TRAP_FP_EL3
:
797 syndrome
= syn_fp_access_trap(1, 0xe, false);
800 g_assert_not_reached();
803 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
806 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
808 const ARMCPRegInfo
*ri
= rip
;
810 if (ri
->type
& ARM_CP_IO
) {
811 qemu_mutex_lock_iothread();
812 ri
->writefn(env
, ri
, value
);
813 qemu_mutex_unlock_iothread();
815 ri
->writefn(env
, ri
, value
);
819 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
821 const ARMCPRegInfo
*ri
= rip
;
824 if (ri
->type
& ARM_CP_IO
) {
825 qemu_mutex_lock_iothread();
826 res
= ri
->readfn(env
, ri
);
827 qemu_mutex_unlock_iothread();
829 res
= ri
->readfn(env
, ri
);
835 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
837 const ARMCPRegInfo
*ri
= rip
;
839 if (ri
->type
& ARM_CP_IO
) {
840 qemu_mutex_lock_iothread();
841 ri
->writefn(env
, ri
, value
);
842 qemu_mutex_unlock_iothread();
844 ri
->writefn(env
, ri
, value
);
848 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
850 const ARMCPRegInfo
*ri
= rip
;
853 if (ri
->type
& ARM_CP_IO
) {
854 qemu_mutex_lock_iothread();
855 res
= ri
->readfn(env
, ri
);
856 qemu_mutex_unlock_iothread();
858 res
= ri
->readfn(env
, ri
);
864 void HELPER(pre_hvc
)(CPUARMState
*env
)
866 ARMCPU
*cpu
= arm_env_get_cpu(env
);
867 int cur_el
= arm_current_el(env
);
868 /* FIXME: Use actual secure state. */
872 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
873 /* If PSCI is enabled and this looks like a valid PSCI call then
874 * that overrides the architecturally mandated HVC behaviour.
879 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
880 /* If EL2 doesn't exist, HVC always UNDEFs */
882 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
883 /* EL3.HCE has priority over EL2.HCD. */
884 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
886 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
889 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
890 * For ARMv8/AArch64, HVC is allowed in EL3.
891 * Note that we've already trapped HVC from EL0 at translation
894 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
899 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
900 exception_target_el(env
));
904 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
906 ARMCPU
*cpu
= arm_env_get_cpu(env
);
907 int cur_el
= arm_current_el(env
);
908 bool secure
= arm_is_secure(env
);
909 bool smd_flag
= env
->cp15
.scr_el3
& SCR_SMD
;
912 * SMC behaviour is summarized in the following table.
913 * This helper handles the "Trap to EL2" and "Undef insn" cases.
914 * The "Trap to EL3" and "PSCI call" cases are handled in the exception
917 * -> ARM_FEATURE_EL3 and !SMD
918 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
920 * Conduit SMC, valid call Trap to EL2 PSCI Call
921 * Conduit SMC, inval call Trap to EL2 Trap to EL3
922 * Conduit not SMC Trap to EL2 Trap to EL3
925 * -> ARM_FEATURE_EL3 and SMD
926 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
928 * Conduit SMC, valid call Trap to EL2 PSCI Call
929 * Conduit SMC, inval call Trap to EL2 Undef insn
930 * Conduit not SMC Trap to EL2 Undef insn
933 * -> !ARM_FEATURE_EL3
934 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
936 * Conduit SMC, valid call Trap to EL2 PSCI Call
937 * Conduit SMC, inval call Trap to EL2 Undef insn
938 * Conduit not SMC Undef insn Undef insn
941 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
942 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
943 * extensions, SMD only applies to NS state.
944 * On ARMv7 without the Virtualization extensions, the SMD bit
945 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
946 * so we need not special case this here.
948 bool smd
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd_flag
949 : smd_flag
&& !secure
;
951 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
952 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
953 /* If we have no EL3 then SMC always UNDEFs and can't be
954 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
955 * firmware within QEMU, and we want an EL2 guest to be able
956 * to forbid its EL1 from making PSCI calls into QEMU's
957 * "firmware" via HCR.TSC, so for these purposes treat
958 * PSCI-via-SMC as implying an EL3.
959 * This handles the very last line of the previous table.
961 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
962 exception_target_el(env
));
965 if (cur_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TSC
)) {
966 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
967 * We also want an EL2 guest to be able to forbid its EL1 from
968 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
969 * This handles all the "Trap to EL2" cases of the previous table.
971 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
974 /* Catch the two remaining "Undef insn" cases of the previous table:
975 * - PSCI conduit is SMC but we don't have a valid PCSI call,
976 * - We don't have EL3 or SMD is set.
978 if (!arm_is_psci_call(cpu
, EXCP_SMC
) &&
979 (smd
|| !arm_feature(env
, ARM_FEATURE_EL3
))) {
980 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
981 exception_target_el(env
));
985 /* Return true if the linked breakpoint entry lbn passes its checks */
986 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
988 CPUARMState
*env
= &cpu
->env
;
989 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
990 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
991 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
995 /* Links to unimplemented or non-context aware breakpoints are
996 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
997 * as if linked to an UNKNOWN context-aware breakpoint (in which
998 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
999 * We choose the former.
1001 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1005 bcr
= env
->cp15
.dbgbcr
[lbn
];
1007 if (extract64(bcr
, 0, 1) == 0) {
1008 /* Linked breakpoint disabled : generate no events */
1012 bt
= extract64(bcr
, 20, 4);
1014 /* We match the whole register even if this is AArch32 using the
1015 * short descriptor format (in which case it holds both PROCID and ASID),
1016 * since we don't implement the optional v7 context ID masking.
1018 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1021 case 3: /* linked context ID match */
1022 if (arm_current_el(env
) > 1) {
1023 /* Context matches never fire in EL2 or (AArch64) EL3 */
1026 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1027 case 5: /* linked address mismatch (reserved in AArch64) */
1028 case 9: /* linked VMID match (reserved if no EL2) */
1029 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1031 /* Links to Unlinked context breakpoints must generate no
1032 * events; we choose to do the same for reserved values too.
1040 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1042 CPUARMState
*env
= &cpu
->env
;
1044 int pac
, hmc
, ssc
, wt
, lbn
;
1045 /* Note that for watchpoints the check is against the CPU security
1046 * state, not the S/NS attribute on the offending data access.
1048 bool is_secure
= arm_is_secure(env
);
1049 int access_el
= arm_current_el(env
);
1052 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1054 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1057 cr
= env
->cp15
.dbgwcr
[n
];
1058 if (wp
->hitattrs
.user
) {
1059 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1060 * match watchpoints as if they were accesses done at EL0, even if
1061 * the CPU is at EL1 or higher.
1066 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1068 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1071 cr
= env
->cp15
.dbgbcr
[n
];
1073 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1074 * enabled and that the address and access type match; for breakpoints
1075 * we know the address matched; check the remaining fields, including
1076 * linked breakpoints. We rely on WCR and BCR having the same layout
1077 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1078 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1079 * must act either like some valid combination or as if the watchpoint
1080 * were disabled. We choose the former, and use this together with
1081 * the fact that EL3 must always be Secure and EL2 must always be
1082 * Non-Secure to simplify the code slightly compared to the full
1083 * table in the ARM ARM.
1085 pac
= extract64(cr
, 1, 2);
1086 hmc
= extract64(cr
, 13, 1);
1087 ssc
= extract64(cr
, 14, 2);
1105 switch (access_el
) {
1113 if (extract32(pac
, 0, 1) == 0) {
1118 if (extract32(pac
, 1, 1) == 0) {
1123 g_assert_not_reached();
1126 wt
= extract64(cr
, 20, 1);
1127 lbn
= extract64(cr
, 16, 4);
1129 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1136 static bool check_watchpoints(ARMCPU
*cpu
)
1138 CPUARMState
*env
= &cpu
->env
;
1141 /* If watchpoints are disabled globally or we can't take debug
1142 * exceptions here then watchpoint firings are ignored.
1144 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1145 || !arm_generate_debug_exceptions(env
)) {
1149 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1150 if (bp_wp_matches(cpu
, n
, true)) {
1157 static bool check_breakpoints(ARMCPU
*cpu
)
1159 CPUARMState
*env
= &cpu
->env
;
1162 /* If breakpoints are disabled globally or we can't take debug
1163 * exceptions here then breakpoint firings are ignored.
1165 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1166 || !arm_generate_debug_exceptions(env
)) {
1170 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1171 if (bp_wp_matches(cpu
, n
, false)) {
1178 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1180 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1182 if (check_breakpoints(cpu
)) {
1183 HELPER(exception_internal(env
, EXCP_DEBUG
));
1187 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1189 /* Called by core code when a CPU watchpoint fires; need to check if this
1190 * is also an architectural watchpoint match.
1192 ARMCPU
*cpu
= ARM_CPU(cs
);
1194 return check_watchpoints(cpu
);
1197 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1199 ARMCPU
*cpu
= ARM_CPU(cs
);
1200 CPUARMState
*env
= &cpu
->env
;
1202 /* In BE32 system mode, target memory is stored byteswapped (on a
1203 * little-endian host system), and by the time we reach here (via an
1204 * opcode helper) the addresses of subword accesses have been adjusted
1205 * to account for that, which means that watchpoints will not match.
1206 * Undo the adjustment here.
1208 if (arm_sctlr_b(env
)) {
1211 } else if (len
== 2) {
1219 void arm_debug_excp_handler(CPUState
*cs
)
1221 /* Called by core code when a watchpoint or breakpoint fires;
1222 * need to check which one and raise the appropriate exception.
1224 ARMCPU
*cpu
= ARM_CPU(cs
);
1225 CPUARMState
*env
= &cpu
->env
;
1226 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1229 if (wp_hit
->flags
& BP_CPU
) {
1230 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1231 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1233 cs
->watchpoint_hit
= NULL
;
1235 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1236 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1237 raise_exception(env
, EXCP_DATA_ABORT
,
1238 syn_watchpoint(same_el
, 0, wnr
),
1239 arm_debug_target_el(env
));
1242 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1243 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1245 /* (1) GDB breakpoints should be handled first.
1246 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1247 * since singlestep is also done by generating a debug internal
1250 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1251 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1255 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1256 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
1257 * values to the guest that it shouldn't be able to see at its
1258 * exception/security level.
1260 env
->exception
.vaddress
= 0;
1261 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1262 syn_breakpoint(same_el
),
1263 arm_debug_target_el(env
));
1267 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1268 The only way to do that in TCG is a conditional branch, which clobbers
1269 all our temporaries. For now implement these as helper functions. */
1271 /* Similarly for variable shift instructions. */
1273 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1275 int shift
= i
& 0xff;
1282 } else if (shift
!= 0) {
1283 env
->CF
= (x
>> (32 - shift
)) & 1;
1289 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1291 int shift
= i
& 0xff;
1294 env
->CF
= (x
>> 31) & 1;
1298 } else if (shift
!= 0) {
1299 env
->CF
= (x
>> (shift
- 1)) & 1;
1305 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1307 int shift
= i
& 0xff;
1309 env
->CF
= (x
>> 31) & 1;
1310 return (int32_t)x
>> 31;
1311 } else if (shift
!= 0) {
1312 env
->CF
= (x
>> (shift
- 1)) & 1;
1313 return (int32_t)x
>> shift
;
1318 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1322 shift
= shift1
& 0x1f;
1325 env
->CF
= (x
>> 31) & 1;
1328 env
->CF
= (x
>> (shift
- 1)) & 1;
1329 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));