4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/units.h"
22 #include "qemu/main-loop.h"
24 #include "exec/helper-proto.h"
25 #include "internals.h"
26 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #define SIGNBIT (uint32_t)0x80000000
30 #define SIGNBIT64 ((uint64_t)1 << 63)
32 static CPUState
*do_raise_exception(CPUARMState
*env
, uint32_t excp
,
33 uint32_t syndrome
, uint32_t target_el
)
35 CPUState
*cs
= env_cpu(env
);
37 if (target_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
39 * Redirect NS EL1 exceptions to NS EL2. These are reported with
40 * their original syndrome register value, with the exception of
41 * SIMD/FP access traps, which are reported as uncategorized
42 * (see DDI0478C.a D1.10.4)
45 if (syn_get_ec(syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
46 syndrome
= syn_uncategorized();
50 assert(!excp_is_internal(excp
));
51 cs
->exception_index
= excp
;
52 env
->exception
.syndrome
= syndrome
;
53 env
->exception
.target_el
= target_el
;
58 void raise_exception(CPUARMState
*env
, uint32_t excp
,
59 uint32_t syndrome
, uint32_t target_el
)
61 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
65 void raise_exception_ra(CPUARMState
*env
, uint32_t excp
, uint32_t syndrome
,
66 uint32_t target_el
, uintptr_t ra
)
68 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
69 cpu_loop_exit_restore(cs
, ra
);
72 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
79 for (shift
= 0; shift
< 32; shift
+= 8) {
80 uint32_t index
= (ireg
>> shift
) & 0xff;
81 if (index
< maxindex
) {
82 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
85 val
|= def
& (0xff << shift
);
91 void HELPER(v8m_stackcheck
)(CPUARMState
*env
, uint32_t newvalue
)
94 * Perform the v8M stack limit check for SP updates from translated code,
95 * raising an exception if the limit is breached.
97 if (newvalue
< v7m_sp_limit(env
)) {
98 CPUState
*cs
= env_cpu(env
);
101 * Stack limit exceptions are a rare case, so rather than syncing
102 * PC/condbits before the call, we use cpu_restore_state() to
103 * get them right before raising the exception.
105 cpu_restore_state(cs
, GETPC(), true);
106 raise_exception(env
, EXCP_STKOF
, 0, 1);
110 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
112 uint32_t res
= a
+ b
;
113 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
118 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
120 uint32_t res
= a
+ b
;
121 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
123 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
128 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
130 uint32_t res
= a
- b
;
131 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
133 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
138 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
140 uint32_t res
= a
+ b
;
148 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
150 uint32_t res
= a
- b
;
158 /* Signed saturation. */
159 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
165 mask
= (1u << shift
) - 1;
169 } else if (top
< -1) {
176 /* Unsigned saturation. */
177 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
181 max
= (1u << shift
) - 1;
185 } else if (val
> max
) {
192 /* Signed saturate. */
193 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
195 return do_ssat(env
, x
, shift
);
198 /* Dual halfword signed saturate. */
199 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
203 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
204 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
208 /* Unsigned saturate. */
209 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
211 return do_usat(env
, x
, shift
);
214 /* Dual halfword unsigned saturate. */
215 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
219 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
220 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
224 void HELPER(setend
)(CPUARMState
*env
)
226 env
->uncached_cpsr
^= CPSR_E
;
227 arm_rebuild_hflags(env
);
230 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
231 * The function returns the target EL (1-3) if the instruction is to be trapped;
232 * otherwise it returns 0 indicating it is not trapped.
234 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
236 int cur_el
= arm_current_el(env
);
239 if (arm_feature(env
, ARM_FEATURE_M
)) {
240 /* M profile cores can never trap WFI/WFE. */
244 /* If we are currently in EL0 then we need to check if SCTLR is set up for
245 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
247 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
250 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
251 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
252 /* Secure EL0 and Secure PL1 is at EL3 */
258 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
263 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
264 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
265 * bits will be zero indicating no trap.
268 mask
= is_wfe
? HCR_TWE
: HCR_TWI
;
269 if (arm_hcr_el2_eff(env
) & mask
) {
274 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
276 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
277 if (env
->cp15
.scr_el3
& mask
) {
285 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
287 CPUState
*cs
= env_cpu(env
);
288 int target_el
= check_wfx_trap(env
, false);
290 if (cpu_has_work(cs
)) {
291 /* Don't bother to go into our "low power state" if
292 * we would just wake up immediately.
301 env
->regs
[15] -= insn_len
;
304 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
308 cs
->exception_index
= EXCP_HLT
;
313 void HELPER(wfe
)(CPUARMState
*env
)
315 /* This is a hint instruction that is semantically different
316 * from YIELD even though we currently implement it identically.
317 * Don't actually halt the CPU, just yield back to top
318 * level loop. This is not going into a "low power state"
319 * (ie halting until some event occurs), so we never take
320 * a configurable trap to a different exception level.
325 void HELPER(yield
)(CPUARMState
*env
)
327 CPUState
*cs
= env_cpu(env
);
329 /* This is a non-trappable hint instruction that generally indicates
330 * that the guest is currently busy-looping. Yield control back to the
331 * top level loop so that a more deserving VCPU has a chance to run.
333 cs
->exception_index
= EXCP_YIELD
;
337 /* Raise an internal-to-QEMU exception. This is limited to only
338 * those EXCP values which are special cases for QEMU to interrupt
339 * execution and not to be used for exceptions which are passed to
340 * the guest (those must all have syndrome information and thus should
341 * use exception_with_syndrome).
343 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
345 CPUState
*cs
= env_cpu(env
);
347 assert(excp_is_internal(excp
));
348 cs
->exception_index
= excp
;
352 /* Raise an exception with the specified syndrome register value */
353 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
354 uint32_t syndrome
, uint32_t target_el
)
356 raise_exception(env
, excp
, syndrome
, target_el
);
359 /* Raise an EXCP_BKPT with the specified syndrome register value,
360 * targeting the correct exception level for debug exceptions.
362 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
364 int debug_el
= arm_debug_target_el(env
);
365 int cur_el
= arm_current_el(env
);
367 /* FSR will only be used if the debug target EL is AArch32. */
368 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
369 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
370 * values to the guest that it shouldn't be able to see at its
371 * exception/security level.
373 env
->exception
.vaddress
= 0;
375 * Other kinds of architectural debug exception are ignored if
376 * they target an exception level below the current one (in QEMU
377 * this is checked by arm_generate_debug_exceptions()). Breakpoint
378 * instructions are special because they always generate an exception
379 * to somewhere: if they can't go to the configured debug exception
380 * level they are taken to the current exception level.
382 if (debug_el
< cur_el
) {
385 raise_exception(env
, EXCP_BKPT
, syndrome
, debug_el
);
388 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
391 * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
392 * This is convenient for populating SPSR_ELx, but must be
393 * hidden from aarch32 mode, where it is not visible.
395 * TODO: ARMv8.4-DIT -- need to move SS somewhere else.
397 return cpsr_read(env
) & ~(CPSR_EXEC
| PSTATE_SS
);
400 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
402 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
403 /* TODO: Not all cpsr bits are relevant to hflags. */
404 arm_rebuild_hflags(env
);
407 /* Write the CPSR for a 32-bit exception return */
408 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
412 qemu_mutex_lock_iothread();
413 arm_call_pre_el_change_hook(env_archcpu(env
));
414 qemu_mutex_unlock_iothread();
416 mask
= aarch32_cpsr_valid_mask(env
->features
, &env_archcpu(env
)->isar
);
417 cpsr_write(env
, val
, mask
, CPSRWriteExceptionReturn
);
419 /* Generated code has already stored the new PC value, but
420 * without masking out its low bits, because which bits need
421 * masking depends on whether we're returning to Thumb or ARM
422 * state. Do the masking now.
424 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
425 arm_rebuild_hflags(env
);
427 qemu_mutex_lock_iothread();
428 arm_call_el_change_hook(env_archcpu(env
));
429 qemu_mutex_unlock_iothread();
432 /* Access to user mode registers from privileged modes. */
433 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
438 val
= env
->banked_r13
[BANK_USRSYS
];
439 } else if (regno
== 14) {
440 val
= env
->banked_r14
[BANK_USRSYS
];
441 } else if (regno
>= 8
442 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
443 val
= env
->usr_regs
[regno
- 8];
445 val
= env
->regs
[regno
];
450 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
453 env
->banked_r13
[BANK_USRSYS
] = val
;
454 } else if (regno
== 14) {
455 env
->banked_r14
[BANK_USRSYS
] = val
;
456 } else if (regno
>= 8
457 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
458 env
->usr_regs
[regno
- 8] = val
;
460 env
->regs
[regno
] = val
;
464 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
466 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
469 env
->banked_r13
[bank_number(mode
)] = val
;
473 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
475 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
476 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
477 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
479 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
480 exception_target_el(env
));
483 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
484 return env
->regs
[13];
486 return env
->banked_r13
[bank_number(mode
)];
490 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
493 /* Raise an exception if the requested access is one of the UNPREDICTABLE
494 * cases; otherwise return. This broadly corresponds to the pseudocode
495 * BankedRegisterAccessValid() and SPSRAccessValid(),
496 * except that we have already handled some cases at translate time.
498 int curmode
= env
->uncached_cpsr
& CPSR_M
;
501 /* ELR_Hyp: a special case because access from tgtmode is OK */
502 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
508 if (curmode
== tgtmode
) {
512 if (tgtmode
== ARM_CPU_MODE_USR
) {
515 if (curmode
!= ARM_CPU_MODE_FIQ
) {
520 if (curmode
== ARM_CPU_MODE_SYS
) {
525 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
534 if (tgtmode
== ARM_CPU_MODE_HYP
) {
535 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
536 if (curmode
!= ARM_CPU_MODE_MON
) {
544 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
545 exception_target_el(env
));
548 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
551 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
555 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
557 case 17: /* ELR_Hyp */
558 env
->elr_el
[2] = value
;
561 env
->banked_r13
[bank_number(tgtmode
)] = value
;
564 env
->banked_r14
[r14_bank_number(tgtmode
)] = value
;
568 case ARM_CPU_MODE_USR
:
569 env
->usr_regs
[regno
- 8] = value
;
571 case ARM_CPU_MODE_FIQ
:
572 env
->fiq_regs
[regno
- 8] = value
;
575 g_assert_not_reached();
579 g_assert_not_reached();
583 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
585 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
589 return env
->banked_spsr
[bank_number(tgtmode
)];
590 case 17: /* ELR_Hyp */
591 return env
->elr_el
[2];
593 return env
->banked_r13
[bank_number(tgtmode
)];
595 return env
->banked_r14
[r14_bank_number(tgtmode
)];
598 case ARM_CPU_MODE_USR
:
599 return env
->usr_regs
[regno
- 8];
600 case ARM_CPU_MODE_FIQ
:
601 return env
->fiq_regs
[regno
- 8];
603 g_assert_not_reached();
606 g_assert_not_reached();
610 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
613 const ARMCPRegInfo
*ri
= rip
;
616 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
617 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
618 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
622 * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
623 * to sysregs non accessible at EL0 to have UNDEF-ed already.
625 if (!is_a64(env
) && arm_current_el(env
) < 2 && ri
->cp
== 15 &&
626 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
627 uint32_t mask
= 1 << ri
->crn
;
629 if (ri
->type
& ARM_CP_64BIT
) {
633 /* T4 and T14 are RES0 */
634 mask
&= ~((1 << 4) | (1 << 14));
636 if (env
->cp15
.hstr_el2
& mask
) {
646 switch (ri
->accessfn(env
, ri
, isread
)) {
650 target_el
= exception_target_el(env
);
652 case CP_ACCESS_TRAP_EL2
:
653 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
654 * a bug in the access function.
656 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
659 case CP_ACCESS_TRAP_EL3
:
662 case CP_ACCESS_TRAP_UNCATEGORIZED
:
663 target_el
= exception_target_el(env
);
664 syndrome
= syn_uncategorized();
666 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
668 syndrome
= syn_uncategorized();
670 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
672 syndrome
= syn_uncategorized();
674 case CP_ACCESS_TRAP_FP_EL2
:
676 /* Since we are an implementation that takes exceptions on a trapped
677 * conditional insn only if the insn has passed its condition code
678 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
679 * (which is also the required value for AArch64 traps).
681 syndrome
= syn_fp_access_trap(1, 0xe, false);
683 case CP_ACCESS_TRAP_FP_EL3
:
685 syndrome
= syn_fp_access_trap(1, 0xe, false);
688 g_assert_not_reached();
692 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
695 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
697 const ARMCPRegInfo
*ri
= rip
;
699 if (ri
->type
& ARM_CP_IO
) {
700 qemu_mutex_lock_iothread();
701 ri
->writefn(env
, ri
, value
);
702 qemu_mutex_unlock_iothread();
704 ri
->writefn(env
, ri
, value
);
708 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
710 const ARMCPRegInfo
*ri
= rip
;
713 if (ri
->type
& ARM_CP_IO
) {
714 qemu_mutex_lock_iothread();
715 res
= ri
->readfn(env
, ri
);
716 qemu_mutex_unlock_iothread();
718 res
= ri
->readfn(env
, ri
);
724 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
726 const ARMCPRegInfo
*ri
= rip
;
728 if (ri
->type
& ARM_CP_IO
) {
729 qemu_mutex_lock_iothread();
730 ri
->writefn(env
, ri
, value
);
731 qemu_mutex_unlock_iothread();
733 ri
->writefn(env
, ri
, value
);
737 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
739 const ARMCPRegInfo
*ri
= rip
;
742 if (ri
->type
& ARM_CP_IO
) {
743 qemu_mutex_lock_iothread();
744 res
= ri
->readfn(env
, ri
);
745 qemu_mutex_unlock_iothread();
747 res
= ri
->readfn(env
, ri
);
753 void HELPER(pre_hvc
)(CPUARMState
*env
)
755 ARMCPU
*cpu
= env_archcpu(env
);
756 int cur_el
= arm_current_el(env
);
757 /* FIXME: Use actual secure state. */
761 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
762 /* If PSCI is enabled and this looks like a valid PSCI call then
763 * that overrides the architecturally mandated HVC behaviour.
768 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
769 /* If EL2 doesn't exist, HVC always UNDEFs */
771 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
772 /* EL3.HCE has priority over EL2.HCD. */
773 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
775 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
778 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
779 * For ARMv8/AArch64, HVC is allowed in EL3.
780 * Note that we've already trapped HVC from EL0 at translation
783 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
788 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
789 exception_target_el(env
));
793 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
795 ARMCPU
*cpu
= env_archcpu(env
);
796 int cur_el
= arm_current_el(env
);
797 bool secure
= arm_is_secure(env
);
798 bool smd_flag
= env
->cp15
.scr_el3
& SCR_SMD
;
801 * SMC behaviour is summarized in the following table.
802 * This helper handles the "Trap to EL2" and "Undef insn" cases.
803 * The "Trap to EL3" and "PSCI call" cases are handled in the exception
806 * -> ARM_FEATURE_EL3 and !SMD
807 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
809 * Conduit SMC, valid call Trap to EL2 PSCI Call
810 * Conduit SMC, inval call Trap to EL2 Trap to EL3
811 * Conduit not SMC Trap to EL2 Trap to EL3
814 * -> ARM_FEATURE_EL3 and SMD
815 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
817 * Conduit SMC, valid call Trap to EL2 PSCI Call
818 * Conduit SMC, inval call Trap to EL2 Undef insn
819 * Conduit not SMC Trap to EL2 Undef insn
822 * -> !ARM_FEATURE_EL3
823 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
825 * Conduit SMC, valid call Trap to EL2 PSCI Call
826 * Conduit SMC, inval call Trap to EL2 Undef insn
827 * Conduit not SMC Undef insn Undef insn
830 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
831 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
832 * extensions, SMD only applies to NS state.
833 * On ARMv7 without the Virtualization extensions, the SMD bit
834 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
835 * so we need not special case this here.
837 bool smd
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd_flag
838 : smd_flag
&& !secure
;
840 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
841 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
842 /* If we have no EL3 then SMC always UNDEFs and can't be
843 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
844 * firmware within QEMU, and we want an EL2 guest to be able
845 * to forbid its EL1 from making PSCI calls into QEMU's
846 * "firmware" via HCR.TSC, so for these purposes treat
847 * PSCI-via-SMC as implying an EL3.
848 * This handles the very last line of the previous table.
850 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
851 exception_target_el(env
));
854 if (cur_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TSC
)) {
855 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
856 * We also want an EL2 guest to be able to forbid its EL1 from
857 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
858 * This handles all the "Trap to EL2" cases of the previous table.
860 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
863 /* Catch the two remaining "Undef insn" cases of the previous table:
864 * - PSCI conduit is SMC but we don't have a valid PCSI call,
865 * - We don't have EL3 or SMD is set.
867 if (!arm_is_psci_call(cpu
, EXCP_SMC
) &&
868 (smd
|| !arm_feature(env
, ARM_FEATURE_EL3
))) {
869 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
870 exception_target_el(env
));
874 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
875 The only way to do that in TCG is a conditional branch, which clobbers
876 all our temporaries. For now implement these as helper functions. */
878 /* Similarly for variable shift instructions. */
880 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
882 int shift
= i
& 0xff;
889 } else if (shift
!= 0) {
890 env
->CF
= (x
>> (32 - shift
)) & 1;
896 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
898 int shift
= i
& 0xff;
901 env
->CF
= (x
>> 31) & 1;
905 } else if (shift
!= 0) {
906 env
->CF
= (x
>> (shift
- 1)) & 1;
912 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
914 int shift
= i
& 0xff;
916 env
->CF
= (x
>> 31) & 1;
917 return (int32_t)x
>> 31;
918 } else if (shift
!= 0) {
919 env
->CF
= (x
>> (shift
- 1)) & 1;
920 return (int32_t)x
>> shift
;
925 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
929 shift
= shift1
& 0x1f;
932 env
->CF
= (x
>> 31) & 1;
935 env
->CF
= (x
>> (shift
- 1)) & 1;
936 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));
940 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
943 * Implement DC ZVA, which zeroes a fixed-length block of memory.
944 * Note that we do not implement the (architecturally mandated)
945 * alignment fault for attempts to use this on Device memory
946 * (which matches the usual QEMU behaviour of not implementing either
947 * alignment faults or any memory attribute handling).
950 ARMCPU
*cpu
= env_archcpu(env
);
951 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
952 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
954 #ifndef CONFIG_USER_ONLY
957 * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
958 * the block size so we might have to do more than one TLB lookup.
959 * We know that in fact for any v8 CPU the page size is at least 4K
960 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
961 * 1K as an artefact of legacy v5 subpage support being present in the
962 * same QEMU executable. So in practice the hostaddr[] array has
963 * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
965 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
966 void *hostaddr
[DIV_ROUND_UP(2 * KiB
, 1 << TARGET_PAGE_BITS_MIN
)];
968 unsigned mmu_idx
= cpu_mmu_index(env
, false);
969 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
971 assert(maxidx
<= ARRAY_SIZE(hostaddr
));
973 for (try = 0; try < 2; try++) {
975 for (i
= 0; i
< maxidx
; i
++) {
976 hostaddr
[i
] = tlb_vaddr_to_host(env
,
977 vaddr
+ TARGET_PAGE_SIZE
* i
,
985 * If it's all in the TLB it's fair game for just writing to;
986 * we know we don't need to update dirty status, etc.
988 for (i
= 0; i
< maxidx
- 1; i
++) {
989 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
991 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
995 * OK, try a store and see if we can populate the tlb. This
996 * might cause an exception if the memory isn't writable,
997 * in which case we will longjmp out of here. We must for
998 * this purpose use the actual register value passed to us
999 * so that we get the fault address right.
1001 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
1002 /* Now we can populate the other TLB entries, if any */
1003 for (i
= 0; i
< maxidx
; i
++) {
1004 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
1005 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
1006 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
1012 * Slow path (probably attempt to do this to an I/O device or
1013 * similar, or clearing of a block of code we have translations
1014 * cached for). Just do a series of byte writes as the architecture
1015 * demands. It's not worth trying to use a cpu_physical_memory_map(),
1016 * memset(), unmap() sequence here because:
1017 * + we'd need to account for the blocksize being larger than a page
1018 * + the direct-RAM access case is almost always going to be dealt
1019 * with in the fastpath code above, so there's no speed benefit
1020 * + we would have to deal with the map returning NULL because the
1021 * bounce buffer was in use
1023 for (i
= 0; i
< blocklen
; i
++) {
1024 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
1028 memset(g2h(vaddr
), 0, blocklen
);