2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
15 #include "internals.h"
18 # include "tcg/oversized-guest.h"
21 typedef struct S1Translate
{
34 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
36 MMUAccessType access_type
, bool s1_is_el0
,
37 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
38 __attribute__((nonnull
));
40 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
42 MMUAccessType access_type
,
43 GetPhysAddrResult
*result
,
45 __attribute__((nonnull
));
47 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
48 static const uint8_t pamax_map
[] = {
58 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
59 unsigned int arm_pamax(ARMCPU
*cpu
)
61 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
62 unsigned int parange
=
63 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
66 * id_aa64mmfr0 is a read-only register so values outside of the
67 * supported mappings can be considered an implementation error.
69 assert(parange
< ARRAY_SIZE(pamax_map
));
70 return pamax_map
[parange
];
74 * In machvirt_init, we call arm_pamax on a cpu that is not fully
75 * initialized, so we can't rely on the propagation done in realize.
77 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
78 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
87 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
89 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
93 return ARMMMUIdx_Stage1_E0
;
95 return ARMMMUIdx_Stage1_E1
;
96 case ARMMMUIdx_E10_1_PAN
:
97 return ARMMMUIdx_Stage1_E1_PAN
;
103 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
105 return stage_1_mmu_idx(arm_mmu_idx(env
));
109 * Return where we should do ptw loads from for a stage 2 walk.
110 * This depends on whether the address we are looking up is a
111 * Secure IPA or a NonSecure IPA, which we know from whether this is
112 * Stage2 or Stage2_S.
113 * If this is the Secure EL1&0 regime we need to check the NSW and SW bits.
115 static ARMMMUIdx
ptw_idx_for_stage_2(CPUARMState
*env
, ARMMMUIdx stage2idx
)
120 * We're OK to check the current state of the CPU here because
121 * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes
122 * (2) there's no way to do a lookup that cares about Stage 2 for a
123 * different security state to the current one for AArch64, and AArch32
124 * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do
125 * an NS stage 1+2 lookup while the NS bit is 0.)
127 if (!arm_is_secure_below_el3(env
) || !arm_el_is_aa64(env
, 3)) {
128 return ARMMMUIdx_Phys_NS
;
130 if (stage2idx
== ARMMMUIdx_Stage2_S
) {
131 s2walk_secure
= !(env
->cp15
.vstcr_el2
& VSTCR_SW
);
133 s2walk_secure
= !(env
->cp15
.vtcr_el2
& VTCR_NSW
);
135 return s2walk_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
139 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
141 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
144 /* Return the TTBR associated with this translation regime */
145 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
147 if (mmu_idx
== ARMMMUIdx_Stage2
) {
148 return env
->cp15
.vttbr_el2
;
150 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
151 return env
->cp15
.vsttbr_el2
;
154 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
156 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
160 /* Return true if the specified stage of address translation is disabled */
161 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
166 if (arm_feature(env
, ARM_FEATURE_M
)) {
167 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
168 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
169 case R_V7M_MPU_CTRL_ENABLE_MASK
:
170 /* Enabled, but not for HardFault and NMI */
171 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
172 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
173 /* Enabled for all cases */
178 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
179 * we warned about that in armv7m_nvic.c when the guest set it.
185 hcr_el2
= arm_hcr_el2_eff_secstate(env
, is_secure
);
188 case ARMMMUIdx_Stage2
:
189 case ARMMMUIdx_Stage2_S
:
190 /* HCR.DC means HCR.VM behaves as 1 */
191 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
193 case ARMMMUIdx_E10_0
:
194 case ARMMMUIdx_E10_1
:
195 case ARMMMUIdx_E10_1_PAN
:
196 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
197 if (hcr_el2
& HCR_TGE
) {
202 case ARMMMUIdx_Stage1_E0
:
203 case ARMMMUIdx_Stage1_E1
:
204 case ARMMMUIdx_Stage1_E1_PAN
:
205 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
206 if (hcr_el2
& HCR_DC
) {
211 case ARMMMUIdx_E20_0
:
212 case ARMMMUIdx_E20_2
:
213 case ARMMMUIdx_E20_2_PAN
:
218 case ARMMMUIdx_Phys_NS
:
219 case ARMMMUIdx_Phys_S
:
220 /* No translation for physical address spaces. */
224 g_assert_not_reached();
227 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
230 static bool S2_attrs_are_device(uint64_t hcr
, uint8_t attrs
)
233 * For an S1 page table walk, the stage 1 attributes are always
234 * some form of "this is Normal memory". The combined S1+S2
235 * attributes are therefore only Device if stage 2 specifies Device.
236 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
237 * ie when cacheattrs.attrs bits [3:2] are 0b00.
238 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
239 * when cacheattrs.attrs bit [2] is 0.
242 return (attrs
& 0x4) == 0;
244 return (attrs
& 0xc) == 0;
248 /* Translate a S1 pagetable walk through S2 if needed. */
249 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
250 hwaddr addr
, ARMMMUFaultInfo
*fi
)
252 bool is_secure
= ptw
->in_secure
;
253 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
254 ARMMMUIdx s2_mmu_idx
= ptw
->in_ptw_idx
;
257 ptw
->out_virt
= addr
;
259 if (unlikely(ptw
->in_debug
)) {
261 * From gdbstub, do not use softmmu so that we don't modify the
262 * state of the cpu at all, including softmmu tlb contents.
264 if (regime_is_stage2(s2_mmu_idx
)) {
265 S1Translate s2ptw
= {
266 .in_mmu_idx
= s2_mmu_idx
,
267 .in_ptw_idx
= ptw_idx_for_stage_2(env
, s2_mmu_idx
),
268 .in_secure
= s2_mmu_idx
== ARMMMUIdx_Stage2_S
,
271 GetPhysAddrResult s2
= { };
273 if (get_phys_addr_lpae(env
, &s2ptw
, addr
, MMU_DATA_LOAD
,
277 ptw
->out_phys
= s2
.f
.phys_addr
;
278 pte_attrs
= s2
.cacheattrs
.attrs
;
279 ptw
->out_secure
= s2
.f
.attrs
.secure
;
281 /* Regime is physical. */
282 ptw
->out_phys
= addr
;
284 ptw
->out_secure
= s2_mmu_idx
== ARMMMUIdx_Phys_S
;
286 ptw
->out_host
= NULL
;
290 CPUTLBEntryFull
*full
;
294 flags
= probe_access_full(env
, addr
, 0, MMU_DATA_LOAD
,
295 arm_to_core_mmu_idx(s2_mmu_idx
),
296 true, &ptw
->out_host
, &full
, 0);
299 if (unlikely(flags
& TLB_INVALID_MASK
)) {
302 ptw
->out_phys
= full
->phys_addr
| (addr
& ~TARGET_PAGE_MASK
);
303 ptw
->out_rw
= full
->prot
& PAGE_WRITE
;
304 pte_attrs
= full
->pte_attrs
;
305 ptw
->out_secure
= full
->attrs
.secure
;
307 g_assert_not_reached();
311 if (regime_is_stage2(s2_mmu_idx
)) {
312 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
314 if ((hcr
& HCR_PTW
) && S2_attrs_are_device(hcr
, pte_attrs
)) {
316 * PTW set and S1 walk touched S2 Device memory:
317 * generate Permission fault.
319 fi
->type
= ARMFault_Permission
;
323 fi
->s1ns
= !is_secure
;
328 ptw
->out_be
= regime_translation_big_endian(env
, mmu_idx
);
332 assert(fi
->type
!= ARMFault_None
);
336 fi
->s1ns
= !is_secure
;
340 /* All loads done in the course of a page table walk go through here. */
341 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
,
344 CPUState
*cs
= env_cpu(env
);
345 void *host
= ptw
->out_host
;
349 /* Page tables are in RAM, and we have the host address. */
350 data
= qatomic_read((uint32_t *)host
);
352 data
= be32_to_cpu(data
);
354 data
= le32_to_cpu(data
);
357 /* Page tables are in MMIO. */
358 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
359 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
360 MemTxResult result
= MEMTX_OK
;
363 data
= address_space_ldl_be(as
, ptw
->out_phys
, attrs
, &result
);
365 data
= address_space_ldl_le(as
, ptw
->out_phys
, attrs
, &result
);
367 if (unlikely(result
!= MEMTX_OK
)) {
368 fi
->type
= ARMFault_SyncExternalOnWalk
;
369 fi
->ea
= arm_extabort_type(result
);
376 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
,
379 CPUState
*cs
= env_cpu(env
);
380 void *host
= ptw
->out_host
;
384 /* Page tables are in RAM, and we have the host address. */
385 #ifdef CONFIG_ATOMIC64
386 data
= qatomic_read__nocheck((uint64_t *)host
);
388 data
= be64_to_cpu(data
);
390 data
= le64_to_cpu(data
);
394 data
= ldq_be_p(host
);
396 data
= ldq_le_p(host
);
400 /* Page tables are in MMIO. */
401 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
402 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
403 MemTxResult result
= MEMTX_OK
;
406 data
= address_space_ldq_be(as
, ptw
->out_phys
, attrs
, &result
);
408 data
= address_space_ldq_le(as
, ptw
->out_phys
, attrs
, &result
);
410 if (unlikely(result
!= MEMTX_OK
)) {
411 fi
->type
= ARMFault_SyncExternalOnWalk
;
412 fi
->ea
= arm_extabort_type(result
);
419 static uint64_t arm_casq_ptw(CPUARMState
*env
, uint64_t old_val
,
420 uint64_t new_val
, S1Translate
*ptw
,
423 #ifdef TARGET_AARCH64
425 void *host
= ptw
->out_host
;
427 if (unlikely(!host
)) {
428 fi
->type
= ARMFault_UnsuppAtomicUpdate
;
434 * Raising a stage2 Protection fault for an atomic update to a read-only
435 * page is delayed until it is certain that there is a change to make.
437 if (unlikely(!ptw
->out_rw
)) {
442 flags
= probe_access_flags(env
, ptw
->out_virt
, 0, MMU_DATA_STORE
,
443 arm_to_core_mmu_idx(ptw
->in_ptw_idx
),
447 if (unlikely(flags
& TLB_INVALID_MASK
)) {
448 assert(fi
->type
!= ARMFault_None
);
449 fi
->s2addr
= ptw
->out_virt
;
452 fi
->s1ns
= !ptw
->in_secure
;
456 /* In case CAS mismatches and we loop, remember writability. */
460 #ifdef CONFIG_ATOMIC64
462 old_val
= cpu_to_be64(old_val
);
463 new_val
= cpu_to_be64(new_val
);
464 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
465 cur_val
= be64_to_cpu(cur_val
);
467 old_val
= cpu_to_le64(old_val
);
468 new_val
= cpu_to_le64(new_val
);
469 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
470 cur_val
= le64_to_cpu(cur_val
);
474 * We can't support the full 64-bit atomic cmpxchg on the host.
475 * Because this is only used for FEAT_HAFDBS, which is only for AA64,
476 * we know that TCG_OVERSIZED_GUEST is set, which means that we are
477 * running in round-robin mode and could only race with dma i/o.
479 #if !TCG_OVERSIZED_GUEST
480 # error "Unexpected configuration"
482 bool locked
= qemu_mutex_iothread_locked();
484 qemu_mutex_lock_iothread();
487 cur_val
= ldq_be_p(host
);
488 if (cur_val
== old_val
) {
489 stq_be_p(host
, new_val
);
492 cur_val
= ldq_le_p(host
);
493 if (cur_val
== old_val
) {
494 stq_le_p(host
, new_val
);
498 qemu_mutex_unlock_iothread();
504 /* AArch32 does not have FEAT_HADFS. */
505 g_assert_not_reached();
509 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
510 uint32_t *table
, uint32_t address
)
512 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
513 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
514 int maskshift
= extract32(tcr
, 0, 3);
515 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
518 if (address
& mask
) {
519 if (tcr
& TTBCR_PD1
) {
520 /* Translation table walk disabled for TTBR1 */
523 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
525 if (tcr
& TTBCR_PD0
) {
526 /* Translation table walk disabled for TTBR0 */
529 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
530 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
532 *table
|= (address
>> 18) & 0x3ffc;
537 * Translate section/page access permissions to page R/W protection flags
539 * @mmu_idx: MMU index indicating required translation regime
540 * @ap: The 3-bit access permissions (AP[2:0])
541 * @domain_prot: The 2-bit domain access permissions
542 * @is_user: TRUE if accessing from PL0
544 static int ap_to_rw_prot_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
545 int ap
, int domain_prot
, bool is_user
)
547 if (domain_prot
== 3) {
548 return PAGE_READ
| PAGE_WRITE
;
553 if (arm_feature(env
, ARM_FEATURE_V7
)) {
556 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
558 return is_user
? 0 : PAGE_READ
;
565 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
570 return PAGE_READ
| PAGE_WRITE
;
573 return PAGE_READ
| PAGE_WRITE
;
574 case 4: /* Reserved. */
577 return is_user
? 0 : PAGE_READ
;
581 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
586 g_assert_not_reached();
591 * Translate section/page access permissions to page R/W protection flags
593 * @mmu_idx: MMU index indicating required translation regime
594 * @ap: The 3-bit access permissions (AP[2:0])
595 * @domain_prot: The 2-bit domain access permissions
597 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
598 int ap
, int domain_prot
)
600 return ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
,
601 regime_is_user(env
, mmu_idx
));
605 * Translate section/page access permissions to page R/W protection flags.
606 * @ap: The 2-bit simple AP (AP[2:1])
607 * @is_user: TRUE if accessing from PL0
609 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
613 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
615 return PAGE_READ
| PAGE_WRITE
;
617 return is_user
? 0 : PAGE_READ
;
621 g_assert_not_reached();
625 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
627 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
630 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
631 uint32_t address
, MMUAccessType access_type
,
632 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
644 /* Pagetable walk. */
645 /* Lookup l1 descriptor. */
646 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
647 /* Section translation fault if page walk is disabled by PD0 or PD1 */
648 fi
->type
= ARMFault_Translation
;
651 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
654 desc
= arm_ldl_ptw(env
, ptw
, fi
);
655 if (fi
->type
!= ARMFault_None
) {
659 domain
= (desc
>> 5) & 0x0f;
660 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
661 dacr
= env
->cp15
.dacr_ns
;
663 dacr
= env
->cp15
.dacr_s
;
665 domain_prot
= (dacr
>> (domain
* 2)) & 3;
667 /* Section translation fault. */
668 fi
->type
= ARMFault_Translation
;
674 if (domain_prot
== 0 || domain_prot
== 2) {
675 fi
->type
= ARMFault_Domain
;
680 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
681 ap
= (desc
>> 10) & 3;
682 result
->f
.lg_page_size
= 20; /* 1MB */
684 /* Lookup l2 entry. */
686 /* Coarse pagetable. */
687 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
689 /* Fine pagetable. */
690 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
692 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
695 desc
= arm_ldl_ptw(env
, ptw
, fi
);
696 if (fi
->type
!= ARMFault_None
) {
700 case 0: /* Page translation fault. */
701 fi
->type
= ARMFault_Translation
;
703 case 1: /* 64k page. */
704 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
705 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
706 result
->f
.lg_page_size
= 16;
708 case 2: /* 4k page. */
709 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
710 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
711 result
->f
.lg_page_size
= 12;
713 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
715 /* ARMv6/XScale extended small page format */
716 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
717 || arm_feature(env
, ARM_FEATURE_V6
)) {
718 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
719 result
->f
.lg_page_size
= 12;
722 * UNPREDICTABLE in ARMv5; we choose to take a
723 * page translation fault.
725 fi
->type
= ARMFault_Translation
;
729 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
730 result
->f
.lg_page_size
= 10;
732 ap
= (desc
>> 4) & 3;
735 /* Never happens, but compiler isn't smart enough to tell. */
736 g_assert_not_reached();
739 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
740 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
741 if (!(result
->f
.prot
& (1 << access_type
))) {
742 /* Access permission fault. */
743 fi
->type
= ARMFault_Permission
;
746 result
->f
.phys_addr
= phys_addr
;
754 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
755 uint32_t address
, MMUAccessType access_type
,
756 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
758 ARMCPU
*cpu
= env_archcpu(env
);
759 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
774 /* Pagetable walk. */
775 /* Lookup l1 descriptor. */
776 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
777 /* Section translation fault if page walk is disabled by PD0 or PD1 */
778 fi
->type
= ARMFault_Translation
;
781 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
784 desc
= arm_ldl_ptw(env
, ptw
, fi
);
785 if (fi
->type
!= ARMFault_None
) {
789 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
790 /* Section translation fault, or attempt to use the encoding
791 * which is Reserved on implementations without PXN.
793 fi
->type
= ARMFault_Translation
;
796 if ((type
== 1) || !(desc
& (1 << 18))) {
797 /* Page or Section. */
798 domain
= (desc
>> 5) & 0x0f;
800 if (regime_el(env
, mmu_idx
) == 1) {
801 dacr
= env
->cp15
.dacr_ns
;
803 dacr
= env
->cp15
.dacr_s
;
808 domain_prot
= (dacr
>> (domain
* 2)) & 3;
809 if (domain_prot
== 0 || domain_prot
== 2) {
810 /* Section or Page domain fault */
811 fi
->type
= ARMFault_Domain
;
815 if (desc
& (1 << 18)) {
817 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
818 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
819 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
820 result
->f
.lg_page_size
= 24; /* 16MB */
823 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
824 result
->f
.lg_page_size
= 20; /* 1MB */
826 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
827 xn
= desc
& (1 << 4);
829 ns
= extract32(desc
, 19, 1);
831 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
832 pxn
= (desc
>> 2) & 1;
834 ns
= extract32(desc
, 3, 1);
835 /* Lookup l2 entry. */
836 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
837 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
840 desc
= arm_ldl_ptw(env
, ptw
, fi
);
841 if (fi
->type
!= ARMFault_None
) {
844 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
846 case 0: /* Page translation fault. */
847 fi
->type
= ARMFault_Translation
;
849 case 1: /* 64k page. */
850 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
851 xn
= desc
& (1 << 15);
852 result
->f
.lg_page_size
= 16;
854 case 2: case 3: /* 4k page. */
855 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
857 result
->f
.lg_page_size
= 12;
860 /* Never happens, but compiler isn't smart enough to tell. */
861 g_assert_not_reached();
864 if (domain_prot
== 3) {
865 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
867 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
870 if (xn
&& access_type
== MMU_INST_FETCH
) {
871 fi
->type
= ARMFault_Permission
;
875 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
876 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
877 /* The simplified model uses AP[0] as an access control bit. */
879 /* Access flag fault. */
880 fi
->type
= ARMFault_AccessFlag
;
883 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
884 user_prot
= simple_ap_to_rw_prot_is_user(ap
>> 1, 1);
886 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
887 user_prot
= ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
, 1);
889 if (result
->f
.prot
&& !xn
) {
890 result
->f
.prot
|= PAGE_EXEC
;
892 if (!(result
->f
.prot
& (1 << access_type
))) {
893 /* Access permission fault. */
894 fi
->type
= ARMFault_Permission
;
897 if (regime_is_pan(env
, mmu_idx
) &&
898 !regime_is_user(env
, mmu_idx
) &&
900 access_type
!= MMU_INST_FETCH
) {
901 /* Privileged Access Never fault */
902 fi
->type
= ARMFault_Permission
;
907 /* The NS bit will (as required by the architecture) have no effect if
908 * the CPU doesn't support TZ or this is a non-secure translation
909 * regime, because the attribute will already be non-secure.
911 result
->f
.attrs
.secure
= false;
913 result
->f
.phys_addr
= phys_addr
;
922 * Translate S2 section/page access permissions to protection flags
924 * @s2ap: The 2-bit stage2 access permissions (S2AP)
925 * @xn: XN (execute-never) bits
926 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
928 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
939 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
957 g_assert_not_reached();
960 if (!extract32(xn
, 1, 1)) {
961 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
970 * Translate section/page access permissions to protection flags
972 * @mmu_idx: MMU index indicating required translation regime
973 * @is_aa64: TRUE if AArch64
974 * @ap: The 2-bit simple AP (AP[2:1])
975 * @ns: NS (non-secure) bit
976 * @xn: XN (execute-never) bit
977 * @pxn: PXN (privileged execute-never) bit
979 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
980 int ap
, int ns
, int xn
, int pxn
)
982 ARMCPU
*cpu
= env_archcpu(env
);
983 bool is_user
= regime_is_user(env
, mmu_idx
);
984 int prot_rw
, user_rw
;
988 assert(!regime_is_stage2(mmu_idx
));
990 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
995 * PAN controls can forbid data accesses but don't affect insn fetch.
996 * Plain PAN forbids data accesses if EL0 has data permissions;
997 * PAN3 forbids data accesses if EL0 has either data or exec perms.
998 * Note that for AArch64 the 'user can exec' case is exactly !xn.
999 * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0
1000 * do not affect EPAN.
1002 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
1004 } else if (cpu_isar_feature(aa64_pan3
, cpu
) && is_aa64
&&
1005 regime_is_pan(env
, mmu_idx
) &&
1006 (regime_sctlr(env
, mmu_idx
) & SCTLR_EPAN
) && !xn
) {
1009 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
1013 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
1017 /* TODO have_wxn should be replaced with
1018 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
1019 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
1020 * compatible processors have EL2, which is required for [U]WXN.
1022 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
1025 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
1029 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
1030 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
1032 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1033 switch (regime_el(env
, mmu_idx
)) {
1037 xn
= xn
|| !(user_rw
& PAGE_READ
);
1041 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
1043 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
1044 (uwxn
&& (user_rw
& PAGE_WRITE
));
1054 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
1057 return prot_rw
| PAGE_EXEC
;
1060 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
1063 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1064 uint32_t el
= regime_el(env
, mmu_idx
);
1068 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
1070 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1072 bool sext
= extract32(tcr
, 4, 1);
1073 bool sign
= extract32(tcr
, 3, 1);
1076 * If the sign-extend bit is not the same as t0sz[3], the result
1077 * is unpredictable. Flag this as a guest error.
1080 qemu_log_mask(LOG_GUEST_ERROR
,
1081 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
1083 tsz
= sextract32(tcr
, 0, 4) + 8;
1087 } else if (el
== 2) {
1089 tsz
= extract32(tcr
, 0, 3);
1091 hpd
= extract64(tcr
, 24, 1);
1094 int t0sz
= extract32(tcr
, 0, 3);
1095 int t1sz
= extract32(tcr
, 16, 3);
1098 select
= va
> (0xffffffffu
>> t0sz
);
1100 /* Note that we will detect errors later. */
1101 select
= va
>= ~(0xffffffffu
>> t1sz
);
1105 epd
= extract32(tcr
, 7, 1);
1106 hpd
= extract64(tcr
, 41, 1);
1109 epd
= extract32(tcr
, 23, 1);
1110 hpd
= extract64(tcr
, 42, 1);
1112 /* For aarch32, hpd0 is not enabled without t2e as well. */
1113 hpd
&= extract32(tcr
, 6, 1);
1116 return (ARMVAParameters
) {
1125 * check_s2_mmu_setup
1127 * @is_aa64: True if the translation regime is in AArch64 state
1128 * @tcr: VTCR_EL2 or VSTCR_EL2
1129 * @ds: Effective value of TCR.DS.
1130 * @iasize: Bitsize of IPAs
1131 * @stride: Page-table stride (See the ARM ARM)
1133 * Decode the starting level of the S2 lookup, returning INT_MIN if
1134 * the configuration is invalid.
1136 static int check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, uint64_t tcr
,
1137 bool ds
, int iasize
, int stride
)
1139 int sl0
, sl2
, startlevel
, granulebits
, levels
;
1140 int s1_min_iasize
, s1_max_iasize
;
1142 sl0
= extract32(tcr
, 6, 2);
1145 * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
1146 * so interleave AArch64.S2StartLevel.
1150 /* SL2 is RES0 unless DS=1 & 4KB granule. */
1151 sl2
= extract64(tcr
, 33, 1);
1158 startlevel
= 2 - sl0
;
1161 if (arm_pamax(cpu
) < 44) {
1166 if (!cpu_isar_feature(aa64_st
, cpu
)) {
1177 if (arm_pamax(cpu
) < 42) {
1187 startlevel
= 3 - sl0
;
1192 if (arm_pamax(cpu
) < 44) {
1199 startlevel
= 3 - sl0
;
1202 g_assert_not_reached();
1206 * Things are simpler for AArch32 EL2, with only 4k pages.
1207 * There is no separate S2InvalidSL function, but AArch32.S2Walk
1208 * begins with walkparms.sl0 in {'1x'}.
1210 assert(stride
== 9);
1214 startlevel
= 2 - sl0
;
1217 /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
1218 levels
= 3 - startlevel
;
1219 granulebits
= stride
+ 3;
1221 s1_min_iasize
= levels
* stride
+ granulebits
+ 1;
1222 s1_max_iasize
= s1_min_iasize
+ (stride
- 1) + 4;
1224 if (iasize
>= s1_min_iasize
&& iasize
<= s1_max_iasize
) {
1233 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
1235 * Returns false if the translation was successful. Otherwise, phys_ptr,
1236 * attrs, prot and page_size may not be filled in, and the populated fsr
1237 * value provides information on why the translation aborted, in the format
1238 * of a long-format DFSR/IFSR fault register, with the following caveat:
1239 * the WnR bit is never set (the caller must do this).
1242 * @ptw: Current and next stage parameters for the walk.
1243 * @address: virtual address to get physical address for
1244 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
1245 * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
1246 * (so this is a stage 2 page table walk),
1247 * must be true if this is stage 2 of a stage 1+2
1248 * walk for an EL0 access. If @mmu_idx is anything else,
1249 * @s1_is_el0 is ignored.
1250 * @result: set on translation success,
1251 * @fi: set to fault info if the translation fails
1253 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
1255 MMUAccessType access_type
, bool s1_is_el0
,
1256 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1258 ARMCPU
*cpu
= env_archcpu(env
);
1259 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1260 bool is_secure
= ptw
->in_secure
;
1262 ARMVAParameters param
;
1264 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1265 uint32_t tableattrs
;
1266 target_ulong page_size
;
1269 int addrsize
, inputsize
, outputsize
;
1270 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1271 int ap
, ns
, xn
, pxn
;
1272 uint32_t el
= regime_el(env
, mmu_idx
);
1273 uint64_t descaddrmask
;
1274 bool aarch64
= arm_el_is_aa64(env
, el
);
1275 uint64_t descriptor
, new_descriptor
;
1278 /* TODO: This code does not support shareability levels. */
1282 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1283 access_type
!= MMU_INST_FETCH
,
1284 !arm_el_is_aa64(env
, 1));
1288 * If TxSZ is programmed to a value larger than the maximum,
1289 * or smaller than the effective minimum, it is IMPLEMENTATION
1290 * DEFINED whether we behave as if the field were programmed
1291 * within bounds, or if a level 0 Translation fault is generated.
1293 * With FEAT_LVA, fault on less than minimum becomes required,
1294 * so our choice is to always raise the fault.
1296 if (param
.tsz_oob
) {
1297 goto do_translation_fault
;
1300 addrsize
= 64 - 8 * param
.tbi
;
1301 inputsize
= 64 - param
.tsz
;
1304 * Bound PS by PARANGE to find the effective output address size.
1305 * ID_AA64MMFR0 is a read-only register so values outside of the
1306 * supported mappings can be considered an implementation error.
1308 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1309 ps
= MIN(ps
, param
.ps
);
1310 assert(ps
< ARRAY_SIZE(pamax_map
));
1311 outputsize
= pamax_map
[ps
];
1314 * With LPA2, the effective output address (OA) size is at most 48 bits
1315 * unless TCR.DS == 1
1317 if (!param
.ds
&& param
.gran
!= Gran64K
) {
1318 outputsize
= MIN(outputsize
, 48);
1321 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1323 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1324 inputsize
= addrsize
- param
.tsz
;
1329 * We determined the region when collecting the parameters, but we
1330 * have not yet validated that the address is valid for the region.
1331 * Extract the top bits and verify that they all match select.
1333 * For aa32, if inputsize == addrsize, then we have selected the
1334 * region by exclusion in aa32_va_parameters and there is no more
1335 * validation to do here.
1337 if (inputsize
< addrsize
) {
1338 target_ulong top_bits
= sextract64(address
, inputsize
,
1339 addrsize
- inputsize
);
1340 if (-top_bits
!= param
.select
) {
1341 /* The gap between the two regions is a Translation fault */
1342 goto do_translation_fault
;
1346 stride
= arm_granule_bits(param
.gran
) - 3;
1349 * Note that QEMU ignores shareability and cacheability attributes,
1350 * so we don't need to do anything with the SH, ORGN, IRGN fields
1351 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1352 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1353 * implement any ASID-like capability so we can ignore it (instead
1354 * we will always flush the TLB any time the ASID is changed).
1356 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1359 * Here we should have set up all the parameters for the translation:
1360 * inputsize, ttbr, epd, stride, tbi
1365 * Translation table walk disabled => Translation fault on TLB miss
1366 * Note: This is always 0 on 64-bit EL2 and EL3.
1368 goto do_translation_fault
;
1371 if (!regime_is_stage2(mmu_idx
)) {
1373 * The starting level depends on the virtual address size (which can
1374 * be up to 48 bits) and the translation granule size. It indicates
1375 * the number of strides (stride bits at a time) needed to
1376 * consume the bits of the input address. In the pseudocode this is:
1377 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1378 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1379 * our 'stride + 3' and 'stride' is our 'stride'.
1380 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1381 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1382 * = 4 - (inputsize - 4) / stride;
1384 level
= 4 - (inputsize
- 4) / stride
;
1386 int startlevel
= check_s2_mmu_setup(cpu
, aarch64
, tcr
, param
.ds
,
1388 if (startlevel
== INT_MIN
) {
1390 goto do_translation_fault
;
1395 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1396 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1398 /* Now we can extract the actual base address from the TTBR */
1399 descaddr
= extract64(ttbr
, 0, 48);
1402 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1404 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1405 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1406 * but we've just cleared the bits above 47, so simplify the test.
1408 if (outputsize
> 48) {
1409 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1410 } else if (descaddr
>> outputsize
) {
1412 fi
->type
= ARMFault_AddressSize
;
1417 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1418 * and also to mask out CnP (bit 0) which could validly be non-zero.
1420 descaddr
&= ~indexmask
;
1423 * For AArch32, the address field in the descriptor goes up to bit 39
1424 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1425 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1426 * bits as part of the address, which will be checked via outputsize.
1427 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1428 * the highest bits of a 52-bit output are placed elsewhere.
1431 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1432 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1433 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1435 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1437 descaddrmask
&= ~indexmask_grainsize
;
1440 * Secure stage 1 accesses start with the page table in secure memory and
1441 * can be downgraded to non-secure at any step. Non-secure accesses
1442 * remain non-secure. We implement this by just ORing in the NSTable/NS
1443 * bits at each step.
1444 * Stage 2 never gets this kind of downgrade.
1446 tableattrs
= is_secure
? 0 : (1 << 4);
1449 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1451 nstable
= !regime_is_stage2(mmu_idx
) && extract32(tableattrs
, 4, 1);
1454 * Stage2_S -> Stage2 or Phys_S -> Phys_NS
1455 * Assert that the non-secure idx are even, and relative order.
1457 QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS
& 1) != 0);
1458 QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2
& 1) != 0);
1459 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS
+ 1 != ARMMMUIdx_Phys_S
);
1460 QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2
+ 1 != ARMMMUIdx_Stage2_S
);
1461 ptw
->in_ptw_idx
&= ~1;
1462 ptw
->in_secure
= false;
1464 if (!S1_ptw_translate(env
, ptw
, descaddr
, fi
)) {
1467 descriptor
= arm_ldq_ptw(env
, ptw
, fi
);
1468 if (fi
->type
!= ARMFault_None
) {
1471 new_descriptor
= descriptor
;
1473 restart_atomic_update
:
1474 if (!(descriptor
& 1) || (!(descriptor
& 2) && (level
== 3))) {
1475 /* Invalid, or the Reserved level 3 encoding */
1476 goto do_translation_fault
;
1479 descaddr
= descriptor
& descaddrmask
;
1482 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1483 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1484 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1485 * raise AddressSizeFault.
1487 if (outputsize
> 48) {
1489 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1491 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1493 } else if (descaddr
>> outputsize
) {
1494 fi
->type
= ARMFault_AddressSize
;
1498 if ((descriptor
& 2) && (level
< 3)) {
1500 * Table entry. The top five bits are attributes which may
1501 * propagate down through lower levels of the table (and
1502 * which are all arranged so that 0 means "no effect", so
1503 * we can gather them up by ORing in the bits at each level).
1505 tableattrs
|= extract64(descriptor
, 59, 5);
1507 indexmask
= indexmask_grainsize
;
1512 * Block entry at level 1 or 2, or page entry at level 3.
1513 * These are basically the same thing, although the number
1514 * of bits we pull in from the vaddr varies. Note that although
1515 * descaddrmask masks enough of the low bits of the descriptor
1516 * to give a correct page or table address, the address field
1517 * in a block descriptor is smaller; so we need to explicitly
1518 * clear the lower bits here before ORing in the low vaddr bits.
1520 * Afterward, descaddr is the final physical address.
1522 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1523 descaddr
&= ~(hwaddr
)(page_size
- 1);
1524 descaddr
|= (address
& (page_size
- 1));
1526 if (likely(!ptw
->in_debug
)) {
1529 * If HA is enabled, prepare to update the descriptor below.
1530 * Otherwise, pass the access fault on to software.
1532 if (!(descriptor
& (1 << 10))) {
1534 new_descriptor
|= 1 << 10; /* AF */
1536 fi
->type
= ARMFault_AccessFlag
;
1543 * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
1544 * bit for writeback. The actual write protection test may still be
1545 * overridden by tableattrs, to be merged below.
1548 && extract64(descriptor
, 51, 1) /* DBM */
1549 && access_type
== MMU_DATA_STORE
) {
1550 if (regime_is_stage2(mmu_idx
)) {
1551 new_descriptor
|= 1ull << 7; /* set S2AP[1] */
1553 new_descriptor
&= ~(1ull << 7); /* clear AP[2] */
1559 * Extract attributes from the (modified) descriptor, and apply
1560 * table descriptors. Stage 2 table descriptors do not include
1561 * any attribute fields. HPD disables all the table attributes
1564 attrs
= new_descriptor
& (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
1565 if (!regime_is_stage2(mmu_idx
)) {
1566 attrs
|= nstable
<< 5; /* NS */
1568 attrs
|= extract64(tableattrs
, 0, 2) << 53; /* XN, PXN */
1570 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1571 * means "force PL1 access only", which means forcing AP[1] to 0.
1573 attrs
&= ~(extract64(tableattrs
, 2, 1) << 6); /* !APT[0] => AP[1] */
1574 attrs
|= extract32(tableattrs
, 3, 1) << 7; /* APT[1] => AP[2] */
1578 ap
= extract32(attrs
, 6, 2);
1579 if (regime_is_stage2(mmu_idx
)) {
1580 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1581 xn
= extract64(attrs
, 53, 2);
1582 result
->f
.prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
1584 ns
= extract32(attrs
, 5, 1);
1585 xn
= extract64(attrs
, 54, 1);
1586 pxn
= extract64(attrs
, 53, 1);
1587 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
1590 if (!(result
->f
.prot
& (1 << access_type
))) {
1591 fi
->type
= ARMFault_Permission
;
1595 /* If FEAT_HAFDBS has made changes, update the PTE. */
1596 if (new_descriptor
!= descriptor
) {
1597 new_descriptor
= arm_casq_ptw(env
, descriptor
, new_descriptor
, ptw
, fi
);
1598 if (fi
->type
!= ARMFault_None
) {
1602 * I_YZSVV says that if the in-memory descriptor has changed,
1603 * then we must use the information in that new value
1604 * (which might include a different output address, different
1605 * attributes, or generate a fault).
1606 * Restart the handling of the descriptor value from scratch.
1608 if (new_descriptor
!= descriptor
) {
1609 descriptor
= new_descriptor
;
1610 goto restart_atomic_update
;
1616 * The NS bit will (as required by the architecture) have no effect if
1617 * the CPU doesn't support TZ or this is a non-secure translation
1618 * regime, because the attribute will already be non-secure.
1620 result
->f
.attrs
.secure
= false;
1623 if (regime_is_stage2(mmu_idx
)) {
1624 result
->cacheattrs
.is_s2_format
= true;
1625 result
->cacheattrs
.attrs
= extract32(attrs
, 2, 4);
1627 /* Index into MAIR registers for cache attributes */
1628 uint8_t attrindx
= extract32(attrs
, 2, 3);
1629 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
1630 assert(attrindx
<= 7);
1631 result
->cacheattrs
.is_s2_format
= false;
1632 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
1634 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
1635 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
1636 result
->f
.guarded
= extract64(attrs
, 50, 1); /* GP */
1641 * For FEAT_LPA2 and effective DS, the SH field in the attributes
1642 * was re-purposed for output address bits. The SH attribute in
1643 * that case comes from TCR_ELx, which we extracted earlier.
1646 result
->cacheattrs
.shareability
= param
.sh
;
1648 result
->cacheattrs
.shareability
= extract32(attrs
, 8, 2);
1651 result
->f
.phys_addr
= descaddr
;
1652 result
->f
.lg_page_size
= ctz64(page_size
);
1655 do_translation_fault
:
1656 fi
->type
= ARMFault_Translation
;
1659 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
1660 fi
->stage2
= fi
->s1ptw
|| regime_is_stage2(mmu_idx
);
1661 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1665 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
1666 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1667 bool is_secure
, GetPhysAddrResult
*result
,
1668 ARMMMUFaultInfo
*fi
)
1673 bool is_user
= regime_is_user(env
, mmu_idx
);
1675 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
1677 result
->f
.phys_addr
= address
;
1678 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1682 result
->f
.phys_addr
= address
;
1683 for (n
= 7; n
>= 0; n
--) {
1684 base
= env
->cp15
.c6_region
[n
];
1685 if ((base
& 1) == 0) {
1688 mask
= 1 << ((base
>> 1) & 0x1f);
1689 /* Keep this shift separate from the above to avoid an
1690 (undefined) << 32. */
1691 mask
= (mask
<< 1) - 1;
1692 if (((base
^ address
) & ~mask
) == 0) {
1697 fi
->type
= ARMFault_Background
;
1701 if (access_type
== MMU_INST_FETCH
) {
1702 mask
= env
->cp15
.pmsav5_insn_ap
;
1704 mask
= env
->cp15
.pmsav5_data_ap
;
1706 mask
= (mask
>> (n
* 4)) & 0xf;
1709 fi
->type
= ARMFault_Permission
;
1714 fi
->type
= ARMFault_Permission
;
1718 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1721 result
->f
.prot
= PAGE_READ
;
1723 result
->f
.prot
|= PAGE_WRITE
;
1727 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1731 fi
->type
= ARMFault_Permission
;
1735 result
->f
.prot
= PAGE_READ
;
1738 result
->f
.prot
= PAGE_READ
;
1741 /* Bad permission. */
1742 fi
->type
= ARMFault_Permission
;
1746 result
->f
.prot
|= PAGE_EXEC
;
1750 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1751 int32_t address
, uint8_t *prot
)
1753 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1754 *prot
= PAGE_READ
| PAGE_WRITE
;
1756 case 0xF0000000 ... 0xFFFFFFFF:
1757 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
1758 /* hivecs execing is ok */
1762 case 0x00000000 ... 0x7FFFFFFF:
1767 /* Default system address map for M profile cores.
1768 * The architecture specifies which regions are execute-never;
1769 * at the MPU level no other checks are defined.
1772 case 0x00000000 ... 0x1fffffff: /* ROM */
1773 case 0x20000000 ... 0x3fffffff: /* SRAM */
1774 case 0x60000000 ... 0x7fffffff: /* RAM */
1775 case 0x80000000 ... 0x9fffffff: /* RAM */
1776 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1778 case 0x40000000 ... 0x5fffffff: /* Peripheral */
1779 case 0xa0000000 ... 0xbfffffff: /* Device */
1780 case 0xc0000000 ... 0xdfffffff: /* Device */
1781 case 0xe0000000 ... 0xffffffff: /* System */
1782 *prot
= PAGE_READ
| PAGE_WRITE
;
1785 g_assert_not_reached();
1790 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
1792 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
1793 return arm_feature(env
, ARM_FEATURE_M
) &&
1794 extract32(address
, 20, 12) == 0xe00;
1797 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
1800 * True if address is in the M profile system region
1801 * 0xe0000000 - 0xffffffff
1803 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
1806 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1807 bool is_secure
, bool is_user
)
1810 * Return true if we should use the default memory map as a
1811 * "background" region if there are no hits against any MPU regions.
1813 CPUARMState
*env
= &cpu
->env
;
1819 if (arm_feature(env
, ARM_FEATURE_M
)) {
1820 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
1823 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1827 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
1830 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
1831 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1832 bool secure
, GetPhysAddrResult
*result
,
1833 ARMMMUFaultInfo
*fi
)
1835 ARMCPU
*cpu
= env_archcpu(env
);
1837 bool is_user
= regime_is_user(env
, mmu_idx
);
1839 result
->f
.phys_addr
= address
;
1840 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1843 if (regime_translation_disabled(env
, mmu_idx
, secure
) ||
1844 m_is_ppb_region(env
, address
)) {
1846 * MPU disabled or M profile PPB access: use default memory map.
1847 * The other case which uses the default memory map in the
1848 * v7M ARM ARM pseudocode is exception vector reads from the vector
1849 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
1850 * which always does a direct read using address_space_ldl(), rather
1851 * than going via this function, so we don't need to check that here.
1853 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1854 } else { /* MPU enabled */
1855 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1857 uint32_t base
= env
->pmsav7
.drbar
[n
];
1858 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
1862 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
1867 qemu_log_mask(LOG_GUEST_ERROR
,
1868 "DRSR[%d]: Rsize field cannot be 0\n", n
);
1872 rmask
= (1ull << rsize
) - 1;
1875 qemu_log_mask(LOG_GUEST_ERROR
,
1876 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
1877 "to DRSR region size, mask = 0x%" PRIx32
"\n",
1882 if (address
< base
|| address
> base
+ rmask
) {
1884 * Address not in this region. We must check whether the
1885 * region covers addresses in the same page as our address.
1886 * In that case we must not report a size that covers the
1887 * whole page for a subsequent hit against a different MPU
1888 * region or the background region, because it would result in
1889 * incorrect TLB hits for subsequent accesses to addresses that
1890 * are in this MPU region.
1892 if (ranges_overlap(base
, rmask
,
1893 address
& TARGET_PAGE_MASK
,
1894 TARGET_PAGE_SIZE
)) {
1895 result
->f
.lg_page_size
= 0;
1900 /* Region matched */
1902 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
1904 uint32_t srdis_mask
;
1906 rsize
-= 3; /* sub region size (power of 2) */
1907 snd
= ((address
- base
) >> rsize
) & 0x7;
1908 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
1910 srdis_mask
= srdis
? 0x3 : 0x0;
1911 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
1913 * This will check in groups of 2, 4 and then 8, whether
1914 * the subregion bits are consistent. rsize is incremented
1915 * back up to give the region size, considering consistent
1916 * adjacent subregions as one region. Stop testing if rsize
1917 * is already big enough for an entire QEMU page.
1919 int snd_rounded
= snd
& ~(i
- 1);
1920 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
1921 snd_rounded
+ 8, i
);
1922 if (srdis_mask
^ srdis_multi
) {
1925 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
1932 if (rsize
< TARGET_PAGE_BITS
) {
1933 result
->f
.lg_page_size
= rsize
;
1938 if (n
== -1) { /* no hits */
1939 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1940 /* background fault */
1941 fi
->type
= ARMFault_Background
;
1944 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
1946 } else { /* a MPU hit! */
1947 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
1948 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
1950 if (m_is_system_region(env
, address
)) {
1951 /* System space is always execute never */
1955 if (is_user
) { /* User mode AP bit decoding */
1960 break; /* no access */
1962 result
->f
.prot
|= PAGE_WRITE
;
1966 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1969 /* for v7M, same as 6; for R profile a reserved value */
1970 if (arm_feature(env
, ARM_FEATURE_M
)) {
1971 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1976 qemu_log_mask(LOG_GUEST_ERROR
,
1977 "DRACR[%d]: Bad value for AP bits: 0x%"
1978 PRIx32
"\n", n
, ap
);
1980 } else { /* Priv. mode AP bits decoding */
1983 break; /* no access */
1987 result
->f
.prot
|= PAGE_WRITE
;
1991 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1994 /* for v7M, same as 6; for R profile a reserved value */
1995 if (arm_feature(env
, ARM_FEATURE_M
)) {
1996 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
2001 qemu_log_mask(LOG_GUEST_ERROR
,
2002 "DRACR[%d]: Bad value for AP bits: 0x%"
2003 PRIx32
"\n", n
, ap
);
2009 result
->f
.prot
&= ~PAGE_EXEC
;
2014 fi
->type
= ARMFault_Permission
;
2016 return !(result
->f
.prot
& (1 << access_type
));
2019 static uint32_t *regime_rbar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2022 if (regime_el(env
, mmu_idx
) == 2) {
2023 return env
->pmsav8
.hprbar
;
2025 return env
->pmsav8
.rbar
[secure
];
2029 static uint32_t *regime_rlar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2032 if (regime_el(env
, mmu_idx
) == 2) {
2033 return env
->pmsav8
.hprlar
;
2035 return env
->pmsav8
.rlar
[secure
];
2039 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
2040 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2041 bool secure
, GetPhysAddrResult
*result
,
2042 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
2045 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
2046 * that a full phys-to-virt translation does).
2047 * mregion is (if not NULL) set to the region number which matched,
2048 * or -1 if no region number is returned (MPU off, address did not
2049 * hit a region, address hit in multiple regions).
2050 * If the region hit doesn't cover the entire TARGET_PAGE the address
2051 * is within, then we set the result page_size to 1 to force the
2052 * memory system to use a subpage.
2054 ARMCPU
*cpu
= env_archcpu(env
);
2055 bool is_user
= regime_is_user(env
, mmu_idx
);
2057 int matchregion
= -1;
2059 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2060 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2063 if (regime_el(env
, mmu_idx
) == 2) {
2064 region_counter
= cpu
->pmsav8r_hdregion
;
2066 region_counter
= cpu
->pmsav7_dregion
;
2069 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2070 result
->f
.phys_addr
= address
;
2076 if (mmu_idx
== ARMMMUIdx_Stage2
) {
2081 * Unlike the ARM ARM pseudocode, we don't need to check whether this
2082 * was an exception vector read from the vector table (which is always
2083 * done using the default system address map), because those accesses
2084 * are done in arm_v7m_load_vector(), which always does a direct
2085 * read using address_space_ldl(), rather than going via this function.
2087 if (regime_translation_disabled(env
, mmu_idx
, secure
)) { /* MPU disabled */
2089 } else if (m_is_ppb_region(env
, address
)) {
2092 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
2097 if (arm_feature(env
, ARM_FEATURE_M
)) {
2104 for (n
= region_counter
- 1; n
>= 0; n
--) {
2107 * Note that the base address is bits [31:x] from the register
2108 * with bits [x-1:0] all zeroes, but the limit address is bits
2109 * [31:x] from the register with bits [x:0] all ones. Where x is
2110 * 5 for Cortex-M and 6 for Cortex-R
2112 uint32_t base
= regime_rbar(env
, mmu_idx
, secure
)[n
] & ~bitmask
;
2113 uint32_t limit
= regime_rlar(env
, mmu_idx
, secure
)[n
] | bitmask
;
2115 if (!(regime_rlar(env
, mmu_idx
, secure
)[n
] & 0x1)) {
2116 /* Region disabled */
2120 if (address
< base
|| address
> limit
) {
2122 * Address not in this region. We must check whether the
2123 * region covers addresses in the same page as our address.
2124 * In that case we must not report a size that covers the
2125 * whole page for a subsequent hit against a different MPU
2126 * region or the background region, because it would result in
2127 * incorrect TLB hits for subsequent accesses to addresses that
2128 * are in this MPU region.
2130 if (limit
>= base
&&
2131 ranges_overlap(base
, limit
- base
+ 1,
2133 TARGET_PAGE_SIZE
)) {
2134 result
->f
.lg_page_size
= 0;
2139 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2140 result
->f
.lg_page_size
= 0;
2143 if (matchregion
!= -1) {
2145 * Multiple regions match -- always a failure (unlike
2146 * PMSAv7 where highest-numbered-region wins)
2148 fi
->type
= ARMFault_Permission
;
2149 if (arm_feature(env
, ARM_FEATURE_M
)) {
2161 if (arm_feature(env
, ARM_FEATURE_M
)) {
2162 fi
->type
= ARMFault_Background
;
2164 fi
->type
= ARMFault_Permission
;
2169 if (matchregion
== -1) {
2170 /* hit using the background region */
2171 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2173 uint32_t matched_rbar
= regime_rbar(env
, mmu_idx
, secure
)[matchregion
];
2174 uint32_t matched_rlar
= regime_rlar(env
, mmu_idx
, secure
)[matchregion
];
2175 uint32_t ap
= extract32(matched_rbar
, 1, 2);
2176 uint32_t xn
= extract32(matched_rbar
, 0, 1);
2179 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
2180 pxn
= extract32(matched_rlar
, 4, 1);
2183 if (m_is_system_region(env
, address
)) {
2184 /* System space is always execute never */
2188 if (regime_el(env
, mmu_idx
) == 2) {
2189 result
->f
.prot
= simple_ap_to_rw_prot_is_user(ap
,
2190 mmu_idx
!= ARMMMUIdx_E2
);
2192 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
2195 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2196 uint8_t attrindx
= extract32(matched_rlar
, 1, 3);
2197 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
2198 uint8_t sh
= extract32(matched_rlar
, 3, 2);
2200 if (regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
&&
2201 result
->f
.prot
& PAGE_WRITE
&& mmu_idx
!= ARMMMUIdx_Stage2
) {
2205 if ((regime_el(env
, mmu_idx
) == 1) &&
2206 regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
&& ap
== 0x1) {
2210 result
->cacheattrs
.is_s2_format
= false;
2211 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
2212 result
->cacheattrs
.shareability
= sh
;
2215 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
2216 result
->f
.prot
|= PAGE_EXEC
;
2220 *mregion
= matchregion
;
2224 fi
->type
= ARMFault_Permission
;
2225 if (arm_feature(env
, ARM_FEATURE_M
)) {
2228 return !(result
->f
.prot
& (1 << access_type
));
2231 static bool v8m_is_sau_exempt(CPUARMState
*env
,
2232 uint32_t address
, MMUAccessType access_type
)
2235 * The architecture specifies that certain address ranges are
2236 * exempt from v8M SAU/IDAU checks.
2239 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
2240 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
2241 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
2242 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
2243 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
2244 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
2247 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
2248 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2249 bool is_secure
, V8M_SAttributes
*sattrs
)
2252 * Look up the security attributes for this address. Compare the
2253 * pseudocode SecurityCheck() function.
2254 * We assume the caller has zero-initialized *sattrs.
2256 ARMCPU
*cpu
= env_archcpu(env
);
2258 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
2259 int idau_region
= IREGION_NOTVALID
;
2260 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2261 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2264 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
2265 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
2267 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
2271 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
2272 /* 0xf0000000..0xffffffff is always S for insn fetches */
2276 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
2277 sattrs
->ns
= !is_secure
;
2281 if (idau_region
!= IREGION_NOTVALID
) {
2282 sattrs
->irvalid
= true;
2283 sattrs
->iregion
= idau_region
;
2286 switch (env
->sau
.ctrl
& 3) {
2287 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
2289 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
2292 default: /* SAU.ENABLE == 1 */
2293 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
2294 if (env
->sau
.rlar
[r
] & 1) {
2295 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
2296 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
2298 if (base
<= address
&& limit
>= address
) {
2299 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2300 sattrs
->subpage
= true;
2302 if (sattrs
->srvalid
) {
2304 * If we hit in more than one region then we must report
2305 * as Secure, not NS-Callable, with no valid region
2309 sattrs
->nsc
= false;
2310 sattrs
->sregion
= 0;
2311 sattrs
->srvalid
= false;
2314 if (env
->sau
.rlar
[r
] & 2) {
2319 sattrs
->srvalid
= true;
2320 sattrs
->sregion
= r
;
2324 * Address not in this region. We must check whether the
2325 * region covers addresses in the same page as our address.
2326 * In that case we must not report a size that covers the
2327 * whole page for a subsequent hit against a different MPU
2328 * region or the background region, because it would result
2329 * in incorrect TLB hits for subsequent accesses to
2330 * addresses that are in this MPU region.
2332 if (limit
>= base
&&
2333 ranges_overlap(base
, limit
- base
+ 1,
2335 TARGET_PAGE_SIZE
)) {
2336 sattrs
->subpage
= true;
2345 * The IDAU will override the SAU lookup results if it specifies
2346 * higher security than the SAU does.
2349 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
2351 sattrs
->nsc
= idau_nsc
;
2356 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
2357 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2358 bool secure
, GetPhysAddrResult
*result
,
2359 ARMMMUFaultInfo
*fi
)
2361 V8M_SAttributes sattrs
= {};
2364 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2365 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2367 if (access_type
== MMU_INST_FETCH
) {
2369 * Instruction fetches always use the MMU bank and the
2370 * transaction attribute determined by the fetch address,
2371 * regardless of CPU state. This is painful for QEMU
2372 * to handle, because it would mean we need to encode
2373 * into the mmu_idx not just the (user, negpri) information
2374 * for the current security state but also that for the
2375 * other security state, which would balloon the number
2376 * of mmu_idx values needed alarmingly.
2377 * Fortunately we can avoid this because it's not actually
2378 * possible to arbitrarily execute code from memory with
2379 * the wrong security attribute: it will always generate
2380 * an exception of some kind or another, apart from the
2381 * special case of an NS CPU executing an SG instruction
2382 * in S&NSC memory. So we always just fail the translation
2383 * here and sort things out in the exception handler
2384 * (including possibly emulating an SG instruction).
2386 if (sattrs
.ns
!= !secure
) {
2388 fi
->type
= ARMFault_QEMU_NSCExec
;
2390 fi
->type
= ARMFault_QEMU_SFault
;
2392 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2393 result
->f
.phys_addr
= address
;
2399 * For data accesses we always use the MMU bank indicated
2400 * by the current CPU state, but the security attributes
2401 * might downgrade a secure access to nonsecure.
2404 result
->f
.attrs
.secure
= false;
2405 } else if (!secure
) {
2407 * NS access to S memory must fault.
2408 * Architecturally we should first check whether the
2409 * MPU information for this address indicates that we
2410 * are doing an unaligned access to Device memory, which
2411 * should generate a UsageFault instead. QEMU does not
2412 * currently check for that kind of unaligned access though.
2413 * If we added it we would need to do so as a special case
2414 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2416 fi
->type
= ARMFault_QEMU_SFault
;
2417 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2418 result
->f
.phys_addr
= address
;
2425 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2427 if (sattrs
.subpage
) {
2428 result
->f
.lg_page_size
= 0;
2434 * Translate from the 4-bit stage 2 representation of
2435 * memory attributes (without cache-allocation hints) to
2436 * the 8-bit representation of the stage 1 MAIR registers
2437 * (which includes allocation hints).
2439 * ref: shared/translation/attrs/S2AttrDecode()
2440 * .../S2ConvertAttrsHints()
2442 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2444 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2445 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2446 uint8_t hihint
= 0, lohint
= 0;
2448 if (hiattr
!= 0) { /* normal memory */
2449 if (hcr
& HCR_CD
) { /* cache disabled */
2450 hiattr
= loattr
= 1; /* non-cacheable */
2452 if (hiattr
!= 1) { /* Write-through or write-back */
2453 hihint
= 3; /* RW allocate */
2455 if (loattr
!= 1) { /* Write-through or write-back */
2456 lohint
= 3; /* RW allocate */
2461 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2465 * Combine either inner or outer cacheability attributes for normal
2466 * memory, according to table D4-42 and pseudocode procedure
2467 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2469 * NB: only stage 1 includes allocation hints (RW bits), leading to
2472 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2474 if (s1
== 4 || s2
== 4) {
2475 /* non-cacheable has precedence */
2477 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2478 /* stage 1 write-through takes precedence */
2480 } else if (extract32(s2
, 2, 2) == 2) {
2481 /* stage 2 write-through takes precedence, but the allocation hint
2482 * is still taken from stage 1
2484 return (2 << 2) | extract32(s1
, 0, 2);
2485 } else { /* write-back */
2491 * Combine the memory type and cacheability attributes of
2492 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2493 * combined attributes in MAIR_EL1 format.
2495 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2496 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2498 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2500 if (s2
.is_s2_format
) {
2501 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2503 s2_mair_attrs
= s2
.attrs
;
2506 s1lo
= extract32(s1
.attrs
, 0, 4);
2507 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2508 s1hi
= extract32(s1
.attrs
, 4, 4);
2509 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2511 /* Combine memory type and cacheability attributes */
2512 if (s1hi
== 0 || s2hi
== 0) {
2513 /* Device has precedence over normal */
2514 if (s1lo
== 0 || s2lo
== 0) {
2515 /* nGnRnE has precedence over anything */
2517 } else if (s1lo
== 4 || s2lo
== 4) {
2518 /* non-Reordering has precedence over Reordering */
2519 ret_attrs
= 4; /* nGnRE */
2520 } else if (s1lo
== 8 || s2lo
== 8) {
2521 /* non-Gathering has precedence over Gathering */
2522 ret_attrs
= 8; /* nGRE */
2524 ret_attrs
= 0xc; /* GRE */
2526 } else { /* Normal memory */
2527 /* Outer/inner cacheability combine independently */
2528 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2529 | combine_cacheattr_nibble(s1lo
, s2lo
);
2534 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2537 * Given the 4 bits specifying the outer or inner cacheability
2538 * in MAIR format, return a value specifying Normal Write-Back,
2539 * with the allocation and transient hints taken from the input
2540 * if the input specified some kind of cacheable attribute.
2542 if (attr
== 0 || attr
== 4) {
2544 * 0 == an UNPREDICTABLE encoding
2545 * 4 == Non-cacheable
2546 * Either way, force Write-Back RW allocate non-transient
2550 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2555 * Combine the memory type and cacheability attributes of
2556 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2557 * combined attributes in MAIR_EL1 format.
2559 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2561 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2565 /* Use stage 1 attributes */
2569 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2570 * then we take the allocation hints from it; otherwise it is
2571 * RW allocate, non-transient.
2573 if ((s1
.attrs
& 0xf0) == 0) {
2577 /* Need to check the Inner and Outer nibbles separately */
2578 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2579 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
2581 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
2582 if ((s1
.attrs
& 0xf0) == 0) {
2587 /* Force Device, of subtype specified by S2 */
2588 return s2
.attrs
<< 2;
2591 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
2592 * arbitrarily force Device.
2599 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
2600 * and CombineS1S2Desc()
2603 * @s1: Attributes from stage 1 walk
2604 * @s2: Attributes from stage 2 walk
2606 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
2607 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2610 bool tagged
= false;
2612 assert(!s1
.is_s2_format
);
2613 ret
.is_s2_format
= false;
2614 ret
.guarded
= s1
.guarded
;
2616 if (s1
.attrs
== 0xf0) {
2621 /* Combine shareability attributes (table D4-43) */
2622 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
2623 /* if either are outer-shareable, the result is outer-shareable */
2624 ret
.shareability
= 2;
2625 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
2626 /* if either are inner-shareable, the result is inner-shareable */
2627 ret
.shareability
= 3;
2629 /* both non-shareable */
2630 ret
.shareability
= 0;
2633 /* Combine memory type and cacheability attributes */
2634 if (hcr
& HCR_FWB
) {
2635 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
2637 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
2641 * Any location for which the resultant memory type is any
2642 * type of Device memory is always treated as Outer Shareable.
2643 * Any location for which the resultant memory type is Normal
2644 * Inner Non-cacheable, Outer Non-cacheable is always treated
2645 * as Outer Shareable.
2646 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
2648 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
2649 ret
.shareability
= 2;
2652 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
2653 if (tagged
&& ret
.attrs
== 0xff) {
2661 * MMU disabled. S1 addresses within aa64 translation regimes are
2662 * still checked for bounds -- see AArch64.S1DisabledOutput().
2664 static bool get_phys_addr_disabled(CPUARMState
*env
, target_ulong address
,
2665 MMUAccessType access_type
,
2666 ARMMMUIdx mmu_idx
, bool is_secure
,
2667 GetPhysAddrResult
*result
,
2668 ARMMMUFaultInfo
*fi
)
2670 uint8_t memattr
= 0x00; /* Device nGnRnE */
2671 uint8_t shareability
= 0; /* non-sharable */
2675 case ARMMMUIdx_Stage2
:
2676 case ARMMMUIdx_Stage2_S
:
2677 case ARMMMUIdx_Phys_NS
:
2678 case ARMMMUIdx_Phys_S
:
2682 r_el
= regime_el(env
, mmu_idx
);
2683 if (arm_el_is_aa64(env
, r_el
)) {
2684 int pamax
= arm_pamax(env_archcpu(env
));
2685 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
2688 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
2689 if (access_type
== MMU_INST_FETCH
) {
2690 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
2692 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
2693 addrtop
= (tbi
? 55 : 63);
2695 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
2696 fi
->type
= ARMFault_AddressSize
;
2703 * When TBI is disabled, we've just validated that all of the
2704 * bits above PAMax are zero, so logically we only need to
2705 * clear the top byte for TBI. But it's clearer to follow
2706 * the pseudocode set of addrdesc.paddress.
2708 address
= extract64(address
, 0, 52);
2711 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
2713 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2715 if (hcr
& HCR_DCT
) {
2716 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
2718 memattr
= 0xff; /* Normal, WB, RWA */
2722 if (memattr
== 0 && access_type
== MMU_INST_FETCH
) {
2723 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
2724 memattr
= 0xee; /* Normal, WT, RA, NT */
2726 memattr
= 0x44; /* Normal, NC, No */
2728 shareability
= 2; /* outer sharable */
2730 result
->cacheattrs
.is_s2_format
= false;
2734 result
->f
.phys_addr
= address
;
2735 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2736 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2737 result
->cacheattrs
.shareability
= shareability
;
2738 result
->cacheattrs
.attrs
= memattr
;
2742 static bool get_phys_addr_twostage(CPUARMState
*env
, S1Translate
*ptw
,
2743 target_ulong address
,
2744 MMUAccessType access_type
,
2745 GetPhysAddrResult
*result
,
2746 ARMMMUFaultInfo
*fi
)
2749 int s1_prot
, s1_lgpgsz
;
2750 bool is_secure
= ptw
->in_secure
;
2751 bool ret
, ipa_secure
;
2752 ARMCacheAttrs cacheattrs1
;
2756 ret
= get_phys_addr_with_struct(env
, ptw
, address
, access_type
, result
, fi
);
2758 /* If S1 fails, return early. */
2763 ipa
= result
->f
.phys_addr
;
2764 ipa_secure
= result
->f
.attrs
.secure
;
2766 is_el0
= ptw
->in_mmu_idx
== ARMMMUIdx_Stage1_E0
;
2767 ptw
->in_mmu_idx
= ipa_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2768 ptw
->in_secure
= ipa_secure
;
2769 ptw
->in_ptw_idx
= ptw_idx_for_stage_2(env
, ptw
->in_mmu_idx
);
2772 * S1 is done, now do S2 translation.
2773 * Save the stage1 results so that we may merge prot and cacheattrs later.
2775 s1_prot
= result
->f
.prot
;
2776 s1_lgpgsz
= result
->f
.lg_page_size
;
2777 cacheattrs1
= result
->cacheattrs
;
2778 memset(result
, 0, sizeof(*result
));
2780 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2781 ret
= get_phys_addr_pmsav8(env
, ipa
, access_type
,
2782 ptw
->in_mmu_idx
, is_secure
, result
, fi
);
2784 ret
= get_phys_addr_lpae(env
, ptw
, ipa
, access_type
,
2785 is_el0
, result
, fi
);
2789 /* Combine the S1 and S2 perms. */
2790 result
->f
.prot
&= s1_prot
;
2792 /* If S2 fails, return early. */
2798 * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
2799 * this means "don't put this in the TLB"; in this case, return a
2800 * result with lg_page_size == 0 to achieve that. Otherwise,
2801 * use the maximum of the S1 & S2 page size, so that invalidation
2802 * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
2803 * we know the combined result permissions etc only cover the minimum
2804 * of the S1 and S2 page size, because we know that the common TLB code
2805 * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
2806 * and passing a larger page size value only affects invalidations.)
2808 if (result
->f
.lg_page_size
< TARGET_PAGE_BITS
||
2809 s1_lgpgsz
< TARGET_PAGE_BITS
) {
2810 result
->f
.lg_page_size
= 0;
2811 } else if (result
->f
.lg_page_size
< s1_lgpgsz
) {
2812 result
->f
.lg_page_size
= s1_lgpgsz
;
2815 /* Combine the S1 and S2 cache attributes. */
2816 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2819 * HCR.DC forces the first stage attributes to
2820 * Normal Non-Shareable,
2821 * Inner Write-Back Read-Allocate Write-Allocate,
2822 * Outer Write-Back Read-Allocate Write-Allocate.
2823 * Do not overwrite Tagged within attrs.
2825 if (cacheattrs1
.attrs
!= 0xf0) {
2826 cacheattrs1
.attrs
= 0xff;
2828 cacheattrs1
.shareability
= 0;
2830 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
2831 result
->cacheattrs
);
2834 * Check if IPA translates to secure or non-secure PA space.
2835 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
2837 result
->f
.attrs
.secure
=
2839 && !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
2841 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
))));
2846 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
2847 target_ulong address
,
2848 MMUAccessType access_type
,
2849 GetPhysAddrResult
*result
,
2850 ARMMMUFaultInfo
*fi
)
2852 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2853 bool is_secure
= ptw
->in_secure
;
2854 ARMMMUIdx s1_mmu_idx
;
2857 * The page table entries may downgrade secure to non-secure, but
2858 * cannot upgrade an non-secure translation regime's attributes
2861 result
->f
.attrs
.secure
= is_secure
;
2864 case ARMMMUIdx_Phys_S
:
2865 case ARMMMUIdx_Phys_NS
:
2866 /* Checking Phys early avoids special casing later vs regime_el. */
2867 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2868 is_secure
, result
, fi
);
2870 case ARMMMUIdx_Stage1_E0
:
2871 case ARMMMUIdx_Stage1_E1
:
2872 case ARMMMUIdx_Stage1_E1_PAN
:
2873 /* First stage lookup uses second stage for ptw. */
2874 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2877 case ARMMMUIdx_Stage2
:
2878 case ARMMMUIdx_Stage2_S
:
2880 * Second stage lookup uses physical for ptw; whether this is S or
2881 * NS may depend on the SW/NSW bits if this is a stage 2 lookup for
2882 * the Secure EL2&0 regime.
2884 ptw
->in_ptw_idx
= ptw_idx_for_stage_2(env
, mmu_idx
);
2887 case ARMMMUIdx_E10_0
:
2888 s1_mmu_idx
= ARMMMUIdx_Stage1_E0
;
2890 case ARMMMUIdx_E10_1
:
2891 s1_mmu_idx
= ARMMMUIdx_Stage1_E1
;
2893 case ARMMMUIdx_E10_1_PAN
:
2894 s1_mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
2897 * Call ourselves recursively to do the stage 1 and then stage 2
2898 * translations if mmu_idx is a two-stage regime, and EL2 present.
2899 * Otherwise, a stage1+stage2 translation is just stage 1.
2901 ptw
->in_mmu_idx
= mmu_idx
= s1_mmu_idx
;
2902 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2903 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
, is_secure
)) {
2904 return get_phys_addr_twostage(env
, ptw
, address
, access_type
,
2910 /* Single stage uses physical for ptw. */
2911 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2915 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
2918 * Fast Context Switch Extension. This doesn't exist at all in v8.
2919 * In v7 and earlier it affects all stage 1 translations.
2921 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
2922 && !arm_feature(env
, ARM_FEATURE_V8
)) {
2923 if (regime_el(env
, mmu_idx
) == 3) {
2924 address
+= env
->cp15
.fcseidr_s
;
2926 address
+= env
->cp15
.fcseidr_ns
;
2930 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2932 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2934 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2936 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
2937 is_secure
, result
, fi
);
2938 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2940 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
2941 is_secure
, result
, fi
);
2944 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
2945 is_secure
, result
, fi
);
2947 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
2948 " mmu_idx %u -> %s (prot %c%c%c)\n",
2949 access_type
== MMU_DATA_LOAD
? "reading" :
2950 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
2951 (uint32_t)address
, mmu_idx
,
2952 ret
? "Miss" : "Hit",
2953 result
->f
.prot
& PAGE_READ
? 'r' : '-',
2954 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
2955 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
2960 /* Definitely a real MMU, not an MPU */
2962 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
2963 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2964 is_secure
, result
, fi
);
2967 if (regime_using_lpae_format(env
, mmu_idx
)) {
2968 return get_phys_addr_lpae(env
, ptw
, address
, access_type
, false,
2970 } else if (arm_feature(env
, ARM_FEATURE_V7
) ||
2971 regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
2972 return get_phys_addr_v6(env
, ptw
, address
, access_type
, result
, fi
);
2974 return get_phys_addr_v5(env
, ptw
, address
, access_type
, result
, fi
);
2978 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
2979 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2980 bool is_secure
, GetPhysAddrResult
*result
,
2981 ARMMMUFaultInfo
*fi
)
2984 .in_mmu_idx
= mmu_idx
,
2985 .in_secure
= is_secure
,
2987 return get_phys_addr_with_struct(env
, &ptw
, address
, access_type
,
2991 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
2992 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2993 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
2998 case ARMMMUIdx_E10_0
:
2999 case ARMMMUIdx_E10_1
:
3000 case ARMMMUIdx_E10_1_PAN
:
3001 case ARMMMUIdx_E20_0
:
3002 case ARMMMUIdx_E20_2
:
3003 case ARMMMUIdx_E20_2_PAN
:
3004 case ARMMMUIdx_Stage1_E0
:
3005 case ARMMMUIdx_Stage1_E1
:
3006 case ARMMMUIdx_Stage1_E1_PAN
:
3008 is_secure
= arm_is_secure_below_el3(env
);
3010 case ARMMMUIdx_Stage2
:
3011 case ARMMMUIdx_Phys_NS
:
3012 case ARMMMUIdx_MPrivNegPri
:
3013 case ARMMMUIdx_MUserNegPri
:
3014 case ARMMMUIdx_MPriv
:
3015 case ARMMMUIdx_MUser
:
3019 case ARMMMUIdx_Stage2_S
:
3020 case ARMMMUIdx_Phys_S
:
3021 case ARMMMUIdx_MSPrivNegPri
:
3022 case ARMMMUIdx_MSUserNegPri
:
3023 case ARMMMUIdx_MSPriv
:
3024 case ARMMMUIdx_MSUser
:
3028 g_assert_not_reached();
3030 return get_phys_addr_with_secure(env
, address
, access_type
, mmu_idx
,
3031 is_secure
, result
, fi
);
3034 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
3037 ARMCPU
*cpu
= ARM_CPU(cs
);
3038 CPUARMState
*env
= &cpu
->env
;
3040 .in_mmu_idx
= arm_mmu_idx(env
),
3041 .in_secure
= arm_is_secure(env
),
3044 GetPhysAddrResult res
= {};
3045 ARMMMUFaultInfo fi
= {};
3048 ret
= get_phys_addr_with_struct(env
, &ptw
, addr
, MMU_DATA_LOAD
, &res
, &fi
);
3049 *attrs
= res
.f
.attrs
;
3054 return res
.f
.phys_addr
;