2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
15 #include "internals.h"
19 typedef struct S1Translate
{
32 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
34 MMUAccessType access_type
, bool s1_is_el0
,
35 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
36 __attribute__((nonnull
));
38 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
40 MMUAccessType access_type
,
41 GetPhysAddrResult
*result
,
43 __attribute__((nonnull
));
45 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
46 static const uint8_t pamax_map
[] = {
56 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
57 unsigned int arm_pamax(ARMCPU
*cpu
)
59 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
60 unsigned int parange
=
61 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
64 * id_aa64mmfr0 is a read-only register so values outside of the
65 * supported mappings can be considered an implementation error.
67 assert(parange
< ARRAY_SIZE(pamax_map
));
68 return pamax_map
[parange
];
72 * In machvirt_init, we call arm_pamax on a cpu that is not fully
73 * initialized, so we can't rely on the propagation done in realize.
75 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
76 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
85 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
87 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
91 return ARMMMUIdx_Stage1_E0
;
93 return ARMMMUIdx_Stage1_E1
;
94 case ARMMMUIdx_E10_1_PAN
:
95 return ARMMMUIdx_Stage1_E1_PAN
;
101 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
103 return stage_1_mmu_idx(arm_mmu_idx(env
));
106 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
108 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
111 /* Return the TTBR associated with this translation regime */
112 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
114 if (mmu_idx
== ARMMMUIdx_Stage2
) {
115 return env
->cp15
.vttbr_el2
;
117 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
118 return env
->cp15
.vsttbr_el2
;
121 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
123 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
127 /* Return true if the specified stage of address translation is disabled */
128 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
133 if (arm_feature(env
, ARM_FEATURE_M
)) {
134 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
135 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
136 case R_V7M_MPU_CTRL_ENABLE_MASK
:
137 /* Enabled, but not for HardFault and NMI */
138 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
139 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
140 /* Enabled for all cases */
145 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
146 * we warned about that in armv7m_nvic.c when the guest set it.
152 hcr_el2
= arm_hcr_el2_eff_secstate(env
, is_secure
);
155 case ARMMMUIdx_Stage2
:
156 case ARMMMUIdx_Stage2_S
:
157 /* HCR.DC means HCR.VM behaves as 1 */
158 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
160 case ARMMMUIdx_E10_0
:
161 case ARMMMUIdx_E10_1
:
162 case ARMMMUIdx_E10_1_PAN
:
163 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
164 if (hcr_el2
& HCR_TGE
) {
169 case ARMMMUIdx_Stage1_E0
:
170 case ARMMMUIdx_Stage1_E1
:
171 case ARMMMUIdx_Stage1_E1_PAN
:
172 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
173 if (hcr_el2
& HCR_DC
) {
178 case ARMMMUIdx_E20_0
:
179 case ARMMMUIdx_E20_2
:
180 case ARMMMUIdx_E20_2_PAN
:
185 case ARMMMUIdx_Phys_NS
:
186 case ARMMMUIdx_Phys_S
:
187 /* No translation for physical address spaces. */
191 g_assert_not_reached();
194 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
197 static bool S2_attrs_are_device(uint64_t hcr
, uint8_t attrs
)
200 * For an S1 page table walk, the stage 1 attributes are always
201 * some form of "this is Normal memory". The combined S1+S2
202 * attributes are therefore only Device if stage 2 specifies Device.
203 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
204 * ie when cacheattrs.attrs bits [3:2] are 0b00.
205 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
206 * when cacheattrs.attrs bit [2] is 0.
209 return (attrs
& 0x4) == 0;
211 return (attrs
& 0xc) == 0;
215 /* Translate a S1 pagetable walk through S2 if needed. */
216 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
217 hwaddr addr
, ARMMMUFaultInfo
*fi
)
219 bool is_secure
= ptw
->in_secure
;
220 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
221 ARMMMUIdx s2_mmu_idx
= ptw
->in_ptw_idx
;
225 ptw
->out_virt
= addr
;
227 if (unlikely(ptw
->in_debug
)) {
229 * From gdbstub, do not use softmmu so that we don't modify the
230 * state of the cpu at all, including softmmu tlb contents.
232 if (regime_is_stage2(s2_mmu_idx
)) {
233 S1Translate s2ptw
= {
234 .in_mmu_idx
= s2_mmu_idx
,
235 .in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
,
236 .in_secure
= is_secure
,
239 GetPhysAddrResult s2
= { };
241 if (get_phys_addr_lpae(env
, &s2ptw
, addr
, MMU_DATA_LOAD
,
245 ptw
->out_phys
= s2
.f
.phys_addr
;
246 pte_attrs
= s2
.cacheattrs
.attrs
;
247 pte_secure
= s2
.f
.attrs
.secure
;
249 /* Regime is physical. */
250 ptw
->out_phys
= addr
;
252 pte_secure
= is_secure
;
254 ptw
->out_host
= NULL
;
258 CPUTLBEntryFull
*full
;
262 flags
= probe_access_full(env
, addr
, 0, MMU_DATA_LOAD
,
263 arm_to_core_mmu_idx(s2_mmu_idx
),
264 true, &ptw
->out_host
, &full
, 0);
267 if (unlikely(flags
& TLB_INVALID_MASK
)) {
270 ptw
->out_phys
= full
->phys_addr
| (addr
& ~TARGET_PAGE_MASK
);
271 ptw
->out_rw
= full
->prot
& PAGE_WRITE
;
272 pte_attrs
= full
->pte_attrs
;
273 pte_secure
= full
->attrs
.secure
;
275 g_assert_not_reached();
279 if (regime_is_stage2(s2_mmu_idx
)) {
280 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
282 if ((hcr
& HCR_PTW
) && S2_attrs_are_device(hcr
, pte_attrs
)) {
284 * PTW set and S1 walk touched S2 Device memory:
285 * generate Permission fault.
287 fi
->type
= ARMFault_Permission
;
291 fi
->s1ns
= !is_secure
;
296 /* Check if page table walk is to secure or non-secure PA space. */
297 ptw
->out_secure
= (is_secure
299 ? env
->cp15
.vstcr_el2
& VSTCR_SW
300 : env
->cp15
.vtcr_el2
& VTCR_NSW
));
301 ptw
->out_be
= regime_translation_big_endian(env
, mmu_idx
);
305 assert(fi
->type
!= ARMFault_None
);
309 fi
->s1ns
= !is_secure
;
313 /* All loads done in the course of a page table walk go through here. */
314 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
,
317 CPUState
*cs
= env_cpu(env
);
318 void *host
= ptw
->out_host
;
322 /* Page tables are in RAM, and we have the host address. */
323 data
= qatomic_read((uint32_t *)host
);
325 data
= be32_to_cpu(data
);
327 data
= le32_to_cpu(data
);
330 /* Page tables are in MMIO. */
331 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
332 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
333 MemTxResult result
= MEMTX_OK
;
336 data
= address_space_ldl_be(as
, ptw
->out_phys
, attrs
, &result
);
338 data
= address_space_ldl_le(as
, ptw
->out_phys
, attrs
, &result
);
340 if (unlikely(result
!= MEMTX_OK
)) {
341 fi
->type
= ARMFault_SyncExternalOnWalk
;
342 fi
->ea
= arm_extabort_type(result
);
349 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
,
352 CPUState
*cs
= env_cpu(env
);
353 void *host
= ptw
->out_host
;
357 /* Page tables are in RAM, and we have the host address. */
358 #ifdef CONFIG_ATOMIC64
359 data
= qatomic_read__nocheck((uint64_t *)host
);
361 data
= be64_to_cpu(data
);
363 data
= le64_to_cpu(data
);
367 data
= ldq_be_p(host
);
369 data
= ldq_le_p(host
);
373 /* Page tables are in MMIO. */
374 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
375 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
376 MemTxResult result
= MEMTX_OK
;
379 data
= address_space_ldq_be(as
, ptw
->out_phys
, attrs
, &result
);
381 data
= address_space_ldq_le(as
, ptw
->out_phys
, attrs
, &result
);
383 if (unlikely(result
!= MEMTX_OK
)) {
384 fi
->type
= ARMFault_SyncExternalOnWalk
;
385 fi
->ea
= arm_extabort_type(result
);
392 static uint64_t arm_casq_ptw(CPUARMState
*env
, uint64_t old_val
,
393 uint64_t new_val
, S1Translate
*ptw
,
397 void *host
= ptw
->out_host
;
399 if (unlikely(!host
)) {
400 fi
->type
= ARMFault_UnsuppAtomicUpdate
;
406 * Raising a stage2 Protection fault for an atomic update to a read-only
407 * page is delayed until it is certain that there is a change to make.
409 if (unlikely(!ptw
->out_rw
)) {
414 flags
= probe_access_flags(env
, ptw
->out_virt
, 0, MMU_DATA_STORE
,
415 arm_to_core_mmu_idx(ptw
->in_ptw_idx
),
419 if (unlikely(flags
& TLB_INVALID_MASK
)) {
420 assert(fi
->type
!= ARMFault_None
);
421 fi
->s2addr
= ptw
->out_virt
;
424 fi
->s1ns
= !ptw
->in_secure
;
428 /* In case CAS mismatches and we loop, remember writability. */
432 #ifdef CONFIG_ATOMIC64
434 old_val
= cpu_to_be64(old_val
);
435 new_val
= cpu_to_be64(new_val
);
436 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
437 cur_val
= be64_to_cpu(cur_val
);
439 old_val
= cpu_to_le64(old_val
);
440 new_val
= cpu_to_le64(new_val
);
441 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
442 cur_val
= le64_to_cpu(cur_val
);
446 * We can't support the full 64-bit atomic cmpxchg on the host.
447 * Because this is only used for FEAT_HAFDBS, which is only for AA64,
448 * we know that TCG_OVERSIZED_GUEST is set, which means that we are
449 * running in round-robin mode and could only race with dma i/o.
451 #ifndef TCG_OVERSIZED_GUEST
452 # error "Unexpected configuration"
454 bool locked
= qemu_mutex_iothread_locked();
456 qemu_mutex_lock_iothread();
459 cur_val
= ldq_be_p(host
);
460 if (cur_val
== old_val
) {
461 stq_be_p(host
, new_val
);
464 cur_val
= ldq_le_p(host
);
465 if (cur_val
== old_val
) {
466 stq_le_p(host
, new_val
);
470 qemu_mutex_unlock_iothread();
477 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
478 uint32_t *table
, uint32_t address
)
480 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
481 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
482 int maskshift
= extract32(tcr
, 0, 3);
483 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
486 if (address
& mask
) {
487 if (tcr
& TTBCR_PD1
) {
488 /* Translation table walk disabled for TTBR1 */
491 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
493 if (tcr
& TTBCR_PD0
) {
494 /* Translation table walk disabled for TTBR0 */
497 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
498 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
500 *table
|= (address
>> 18) & 0x3ffc;
505 * Translate section/page access permissions to page R/W protection flags
507 * @mmu_idx: MMU index indicating required translation regime
508 * @ap: The 3-bit access permissions (AP[2:0])
509 * @domain_prot: The 2-bit domain access permissions
510 * @is_user: TRUE if accessing from PL0
512 static int ap_to_rw_prot_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
513 int ap
, int domain_prot
, bool is_user
)
515 if (domain_prot
== 3) {
516 return PAGE_READ
| PAGE_WRITE
;
521 if (arm_feature(env
, ARM_FEATURE_V7
)) {
524 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
526 return is_user
? 0 : PAGE_READ
;
533 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
538 return PAGE_READ
| PAGE_WRITE
;
541 return PAGE_READ
| PAGE_WRITE
;
542 case 4: /* Reserved. */
545 return is_user
? 0 : PAGE_READ
;
549 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
554 g_assert_not_reached();
559 * Translate section/page access permissions to page R/W protection flags
561 * @mmu_idx: MMU index indicating required translation regime
562 * @ap: The 3-bit access permissions (AP[2:0])
563 * @domain_prot: The 2-bit domain access permissions
565 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
566 int ap
, int domain_prot
)
568 return ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
,
569 regime_is_user(env
, mmu_idx
));
573 * Translate section/page access permissions to page R/W protection flags.
574 * @ap: The 2-bit simple AP (AP[2:1])
575 * @is_user: TRUE if accessing from PL0
577 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
581 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
583 return PAGE_READ
| PAGE_WRITE
;
585 return is_user
? 0 : PAGE_READ
;
589 g_assert_not_reached();
593 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
595 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
598 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
599 uint32_t address
, MMUAccessType access_type
,
600 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
612 /* Pagetable walk. */
613 /* Lookup l1 descriptor. */
614 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
615 /* Section translation fault if page walk is disabled by PD0 or PD1 */
616 fi
->type
= ARMFault_Translation
;
619 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
622 desc
= arm_ldl_ptw(env
, ptw
, fi
);
623 if (fi
->type
!= ARMFault_None
) {
627 domain
= (desc
>> 5) & 0x0f;
628 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
629 dacr
= env
->cp15
.dacr_ns
;
631 dacr
= env
->cp15
.dacr_s
;
633 domain_prot
= (dacr
>> (domain
* 2)) & 3;
635 /* Section translation fault. */
636 fi
->type
= ARMFault_Translation
;
642 if (domain_prot
== 0 || domain_prot
== 2) {
643 fi
->type
= ARMFault_Domain
;
648 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
649 ap
= (desc
>> 10) & 3;
650 result
->f
.lg_page_size
= 20; /* 1MB */
652 /* Lookup l2 entry. */
654 /* Coarse pagetable. */
655 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
657 /* Fine pagetable. */
658 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
660 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
663 desc
= arm_ldl_ptw(env
, ptw
, fi
);
664 if (fi
->type
!= ARMFault_None
) {
668 case 0: /* Page translation fault. */
669 fi
->type
= ARMFault_Translation
;
671 case 1: /* 64k page. */
672 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
673 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
674 result
->f
.lg_page_size
= 16;
676 case 2: /* 4k page. */
677 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
678 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
679 result
->f
.lg_page_size
= 12;
681 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
683 /* ARMv6/XScale extended small page format */
684 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
685 || arm_feature(env
, ARM_FEATURE_V6
)) {
686 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
687 result
->f
.lg_page_size
= 12;
690 * UNPREDICTABLE in ARMv5; we choose to take a
691 * page translation fault.
693 fi
->type
= ARMFault_Translation
;
697 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
698 result
->f
.lg_page_size
= 10;
700 ap
= (desc
>> 4) & 3;
703 /* Never happens, but compiler isn't smart enough to tell. */
704 g_assert_not_reached();
707 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
708 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
709 if (!(result
->f
.prot
& (1 << access_type
))) {
710 /* Access permission fault. */
711 fi
->type
= ARMFault_Permission
;
714 result
->f
.phys_addr
= phys_addr
;
722 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
723 uint32_t address
, MMUAccessType access_type
,
724 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
726 ARMCPU
*cpu
= env_archcpu(env
);
727 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
742 /* Pagetable walk. */
743 /* Lookup l1 descriptor. */
744 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
745 /* Section translation fault if page walk is disabled by PD0 or PD1 */
746 fi
->type
= ARMFault_Translation
;
749 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
752 desc
= arm_ldl_ptw(env
, ptw
, fi
);
753 if (fi
->type
!= ARMFault_None
) {
757 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
758 /* Section translation fault, or attempt to use the encoding
759 * which is Reserved on implementations without PXN.
761 fi
->type
= ARMFault_Translation
;
764 if ((type
== 1) || !(desc
& (1 << 18))) {
765 /* Page or Section. */
766 domain
= (desc
>> 5) & 0x0f;
768 if (regime_el(env
, mmu_idx
) == 1) {
769 dacr
= env
->cp15
.dacr_ns
;
771 dacr
= env
->cp15
.dacr_s
;
776 domain_prot
= (dacr
>> (domain
* 2)) & 3;
777 if (domain_prot
== 0 || domain_prot
== 2) {
778 /* Section or Page domain fault */
779 fi
->type
= ARMFault_Domain
;
783 if (desc
& (1 << 18)) {
785 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
786 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
787 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
788 result
->f
.lg_page_size
= 24; /* 16MB */
791 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
792 result
->f
.lg_page_size
= 20; /* 1MB */
794 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
795 xn
= desc
& (1 << 4);
797 ns
= extract32(desc
, 19, 1);
799 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
800 pxn
= (desc
>> 2) & 1;
802 ns
= extract32(desc
, 3, 1);
803 /* Lookup l2 entry. */
804 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
805 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
808 desc
= arm_ldl_ptw(env
, ptw
, fi
);
809 if (fi
->type
!= ARMFault_None
) {
812 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
814 case 0: /* Page translation fault. */
815 fi
->type
= ARMFault_Translation
;
817 case 1: /* 64k page. */
818 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
819 xn
= desc
& (1 << 15);
820 result
->f
.lg_page_size
= 16;
822 case 2: case 3: /* 4k page. */
823 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
825 result
->f
.lg_page_size
= 12;
828 /* Never happens, but compiler isn't smart enough to tell. */
829 g_assert_not_reached();
832 if (domain_prot
== 3) {
833 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
835 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
838 if (xn
&& access_type
== MMU_INST_FETCH
) {
839 fi
->type
= ARMFault_Permission
;
843 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
844 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
845 /* The simplified model uses AP[0] as an access control bit. */
847 /* Access flag fault. */
848 fi
->type
= ARMFault_AccessFlag
;
851 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
852 user_prot
= simple_ap_to_rw_prot_is_user(ap
>> 1, 1);
854 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
855 user_prot
= ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
, 1);
857 if (result
->f
.prot
&& !xn
) {
858 result
->f
.prot
|= PAGE_EXEC
;
860 if (!(result
->f
.prot
& (1 << access_type
))) {
861 /* Access permission fault. */
862 fi
->type
= ARMFault_Permission
;
865 if (regime_is_pan(env
, mmu_idx
) &&
866 !regime_is_user(env
, mmu_idx
) &&
868 access_type
!= MMU_INST_FETCH
) {
869 /* Privileged Access Never fault */
870 fi
->type
= ARMFault_Permission
;
875 /* The NS bit will (as required by the architecture) have no effect if
876 * the CPU doesn't support TZ or this is a non-secure translation
877 * regime, because the attribute will already be non-secure.
879 result
->f
.attrs
.secure
= false;
881 result
->f
.phys_addr
= phys_addr
;
890 * Translate S2 section/page access permissions to protection flags
892 * @s2ap: The 2-bit stage2 access permissions (S2AP)
893 * @xn: XN (execute-never) bits
894 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
896 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
907 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
925 g_assert_not_reached();
928 if (!extract32(xn
, 1, 1)) {
929 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
938 * Translate section/page access permissions to protection flags
940 * @mmu_idx: MMU index indicating required translation regime
941 * @is_aa64: TRUE if AArch64
942 * @ap: The 2-bit simple AP (AP[2:1])
943 * @ns: NS (non-secure) bit
944 * @xn: XN (execute-never) bit
945 * @pxn: PXN (privileged execute-never) bit
947 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
948 int ap
, int ns
, int xn
, int pxn
)
950 bool is_user
= regime_is_user(env
, mmu_idx
);
951 int prot_rw
, user_rw
;
955 assert(!regime_is_stage2(mmu_idx
));
957 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
961 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
962 /* PAN forbids data accesses but doesn't affect insn fetch */
965 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
969 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
973 /* TODO have_wxn should be replaced with
974 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
975 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
976 * compatible processors have EL2, which is required for [U]WXN.
978 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
981 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
985 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
986 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
988 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
989 switch (regime_el(env
, mmu_idx
)) {
993 xn
= xn
|| !(user_rw
& PAGE_READ
);
997 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
999 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
1000 (uwxn
&& (user_rw
& PAGE_WRITE
));
1010 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
1013 return prot_rw
| PAGE_EXEC
;
1016 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
1019 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1020 uint32_t el
= regime_el(env
, mmu_idx
);
1024 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
1026 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1028 bool sext
= extract32(tcr
, 4, 1);
1029 bool sign
= extract32(tcr
, 3, 1);
1032 * If the sign-extend bit is not the same as t0sz[3], the result
1033 * is unpredictable. Flag this as a guest error.
1036 qemu_log_mask(LOG_GUEST_ERROR
,
1037 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
1039 tsz
= sextract32(tcr
, 0, 4) + 8;
1043 } else if (el
== 2) {
1045 tsz
= extract32(tcr
, 0, 3);
1047 hpd
= extract64(tcr
, 24, 1);
1050 int t0sz
= extract32(tcr
, 0, 3);
1051 int t1sz
= extract32(tcr
, 16, 3);
1054 select
= va
> (0xffffffffu
>> t0sz
);
1056 /* Note that we will detect errors later. */
1057 select
= va
>= ~(0xffffffffu
>> t1sz
);
1061 epd
= extract32(tcr
, 7, 1);
1062 hpd
= extract64(tcr
, 41, 1);
1065 epd
= extract32(tcr
, 23, 1);
1066 hpd
= extract64(tcr
, 42, 1);
1068 /* For aarch32, hpd0 is not enabled without t2e as well. */
1069 hpd
&= extract32(tcr
, 6, 1);
1072 return (ARMVAParameters
) {
1081 * check_s2_mmu_setup
1083 * @is_aa64: True if the translation regime is in AArch64 state
1084 * @startlevel: Suggested starting level
1085 * @inputsize: Bitsize of IPAs
1086 * @stride: Page-table stride (See the ARM ARM)
1088 * Returns true if the suggested S2 translation parameters are OK and
1091 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
1092 int inputsize
, int stride
, int outputsize
)
1094 const int grainsize
= stride
+ 3;
1098 * Negative levels are usually not allowed...
1099 * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
1100 * begins with level -1. Note that previous feature tests will have
1101 * eliminated this combination if it is not enabled.
1103 if (level
< (inputsize
== 52 && stride
== 9 ? -1 : 0)) {
1107 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
1108 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
1114 case 13: /* 64KB Pages. */
1115 if (level
== 0 || (level
== 1 && outputsize
<= 42)) {
1119 case 11: /* 16KB Pages. */
1120 if (level
== 0 || (level
== 1 && outputsize
<= 40)) {
1124 case 9: /* 4KB Pages. */
1125 if (level
== 0 && outputsize
<= 42) {
1130 g_assert_not_reached();
1133 /* Inputsize checks. */
1134 if (inputsize
> outputsize
&&
1135 (arm_el_is_aa64(&cpu
->env
, 1) || inputsize
> 40)) {
1136 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
1140 /* AArch32 only supports 4KB pages. Assert on that. */
1141 assert(stride
== 9);
1151 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
1153 * Returns false if the translation was successful. Otherwise, phys_ptr,
1154 * attrs, prot and page_size may not be filled in, and the populated fsr
1155 * value provides information on why the translation aborted, in the format
1156 * of a long-format DFSR/IFSR fault register, with the following caveat:
1157 * the WnR bit is never set (the caller must do this).
1160 * @ptw: Current and next stage parameters for the walk.
1161 * @address: virtual address to get physical address for
1162 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
1163 * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
1164 * (so this is a stage 2 page table walk),
1165 * must be true if this is stage 2 of a stage 1+2
1166 * walk for an EL0 access. If @mmu_idx is anything else,
1167 * @s1_is_el0 is ignored.
1168 * @result: set on translation success,
1169 * @fi: set to fault info if the translation fails
1171 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
1173 MMUAccessType access_type
, bool s1_is_el0
,
1174 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1176 ARMCPU
*cpu
= env_archcpu(env
);
1177 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1178 bool is_secure
= ptw
->in_secure
;
1180 ARMVAParameters param
;
1182 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1183 uint32_t tableattrs
;
1184 target_ulong page_size
;
1187 int addrsize
, inputsize
, outputsize
;
1188 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1189 int ap
, ns
, xn
, pxn
;
1190 uint32_t el
= regime_el(env
, mmu_idx
);
1191 uint64_t descaddrmask
;
1192 bool aarch64
= arm_el_is_aa64(env
, el
);
1193 uint64_t descriptor
, new_descriptor
;
1196 /* TODO: This code does not support shareability levels. */
1200 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1201 access_type
!= MMU_INST_FETCH
);
1205 * If TxSZ is programmed to a value larger than the maximum,
1206 * or smaller than the effective minimum, it is IMPLEMENTATION
1207 * DEFINED whether we behave as if the field were programmed
1208 * within bounds, or if a level 0 Translation fault is generated.
1210 * With FEAT_LVA, fault on less than minimum becomes required,
1211 * so our choice is to always raise the fault.
1213 if (param
.tsz_oob
) {
1214 goto do_translation_fault
;
1217 addrsize
= 64 - 8 * param
.tbi
;
1218 inputsize
= 64 - param
.tsz
;
1221 * Bound PS by PARANGE to find the effective output address size.
1222 * ID_AA64MMFR0 is a read-only register so values outside of the
1223 * supported mappings can be considered an implementation error.
1225 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1226 ps
= MIN(ps
, param
.ps
);
1227 assert(ps
< ARRAY_SIZE(pamax_map
));
1228 outputsize
= pamax_map
[ps
];
1231 * With LPA2, the effective output address (OA) size is at most 48 bits
1232 * unless TCR.DS == 1
1234 if (!param
.ds
&& param
.gran
!= Gran64K
) {
1235 outputsize
= MIN(outputsize
, 48);
1238 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1240 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1241 inputsize
= addrsize
- param
.tsz
;
1246 * We determined the region when collecting the parameters, but we
1247 * have not yet validated that the address is valid for the region.
1248 * Extract the top bits and verify that they all match select.
1250 * For aa32, if inputsize == addrsize, then we have selected the
1251 * region by exclusion in aa32_va_parameters and there is no more
1252 * validation to do here.
1254 if (inputsize
< addrsize
) {
1255 target_ulong top_bits
= sextract64(address
, inputsize
,
1256 addrsize
- inputsize
);
1257 if (-top_bits
!= param
.select
) {
1258 /* The gap between the two regions is a Translation fault */
1259 goto do_translation_fault
;
1263 stride
= arm_granule_bits(param
.gran
) - 3;
1266 * Note that QEMU ignores shareability and cacheability attributes,
1267 * so we don't need to do anything with the SH, ORGN, IRGN fields
1268 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1269 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1270 * implement any ASID-like capability so we can ignore it (instead
1271 * we will always flush the TLB any time the ASID is changed).
1273 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1276 * Here we should have set up all the parameters for the translation:
1277 * inputsize, ttbr, epd, stride, tbi
1282 * Translation table walk disabled => Translation fault on TLB miss
1283 * Note: This is always 0 on 64-bit EL2 and EL3.
1285 goto do_translation_fault
;
1288 if (!regime_is_stage2(mmu_idx
)) {
1290 * The starting level depends on the virtual address size (which can
1291 * be up to 48 bits) and the translation granule size. It indicates
1292 * the number of strides (stride bits at a time) needed to
1293 * consume the bits of the input address. In the pseudocode this is:
1294 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1295 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1296 * our 'stride + 3' and 'stride' is our 'stride'.
1297 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1298 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1299 * = 4 - (inputsize - 4) / stride;
1301 level
= 4 - (inputsize
- 4) / stride
;
1304 * For stage 2 translations the starting level is specified by the
1305 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
1307 uint32_t sl0
= extract32(tcr
, 6, 2);
1308 uint32_t sl2
= extract64(tcr
, 33, 1);
1312 /* SL2 is RES0 unless DS=1 & 4kb granule. */
1313 if (param
.ds
&& stride
== 9 && sl2
) {
1316 goto do_translation_fault
;
1319 } else if (!aarch64
|| stride
== 9) {
1320 /* AArch32 or 4KB pages */
1321 startlevel
= 2 - sl0
;
1323 if (cpu_isar_feature(aa64_st
, cpu
)) {
1327 /* 16KB or 64KB pages */
1328 startlevel
= 3 - sl0
;
1331 /* Check that the starting level is valid. */
1332 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
1333 inputsize
, stride
, outputsize
);
1335 goto do_translation_fault
;
1340 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1341 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1343 /* Now we can extract the actual base address from the TTBR */
1344 descaddr
= extract64(ttbr
, 0, 48);
1347 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1349 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1350 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1351 * but we've just cleared the bits above 47, so simplify the test.
1353 if (outputsize
> 48) {
1354 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1355 } else if (descaddr
>> outputsize
) {
1357 fi
->type
= ARMFault_AddressSize
;
1362 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1363 * and also to mask out CnP (bit 0) which could validly be non-zero.
1365 descaddr
&= ~indexmask
;
1368 * For AArch32, the address field in the descriptor goes up to bit 39
1369 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1370 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1371 * bits as part of the address, which will be checked via outputsize.
1372 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1373 * the highest bits of a 52-bit output are placed elsewhere.
1376 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1377 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1378 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1380 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1382 descaddrmask
&= ~indexmask_grainsize
;
1385 * Secure accesses start with the page table in secure memory and
1386 * can be downgraded to non-secure at any step. Non-secure accesses
1387 * remain non-secure. We implement this by just ORing in the NSTable/NS
1388 * bits at each step.
1390 tableattrs
= is_secure
? 0 : (1 << 4);
1393 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1395 nstable
= extract32(tableattrs
, 4, 1);
1398 * Stage2_S -> Stage2 or Phys_S -> Phys_NS
1399 * Assert that the non-secure idx are even, and relative order.
1401 QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS
& 1) != 0);
1402 QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2
& 1) != 0);
1403 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS
+ 1 != ARMMMUIdx_Phys_S
);
1404 QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2
+ 1 != ARMMMUIdx_Stage2_S
);
1405 ptw
->in_ptw_idx
&= ~1;
1406 ptw
->in_secure
= false;
1408 if (!S1_ptw_translate(env
, ptw
, descaddr
, fi
)) {
1411 descriptor
= arm_ldq_ptw(env
, ptw
, fi
);
1412 if (fi
->type
!= ARMFault_None
) {
1415 new_descriptor
= descriptor
;
1417 restart_atomic_update
:
1418 if (!(descriptor
& 1) || (!(descriptor
& 2) && (level
== 3))) {
1419 /* Invalid, or the Reserved level 3 encoding */
1420 goto do_translation_fault
;
1423 descaddr
= descriptor
& descaddrmask
;
1426 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1427 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1428 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1429 * raise AddressSizeFault.
1431 if (outputsize
> 48) {
1433 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1435 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1437 } else if (descaddr
>> outputsize
) {
1438 fi
->type
= ARMFault_AddressSize
;
1442 if ((descriptor
& 2) && (level
< 3)) {
1444 * Table entry. The top five bits are attributes which may
1445 * propagate down through lower levels of the table (and
1446 * which are all arranged so that 0 means "no effect", so
1447 * we can gather them up by ORing in the bits at each level).
1449 tableattrs
|= extract64(descriptor
, 59, 5);
1451 indexmask
= indexmask_grainsize
;
1456 * Block entry at level 1 or 2, or page entry at level 3.
1457 * These are basically the same thing, although the number
1458 * of bits we pull in from the vaddr varies. Note that although
1459 * descaddrmask masks enough of the low bits of the descriptor
1460 * to give a correct page or table address, the address field
1461 * in a block descriptor is smaller; so we need to explicitly
1462 * clear the lower bits here before ORing in the low vaddr bits.
1464 * Afterward, descaddr is the final physical address.
1466 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1467 descaddr
&= ~(hwaddr
)(page_size
- 1);
1468 descaddr
|= (address
& (page_size
- 1));
1470 if (likely(!ptw
->in_debug
)) {
1473 * If HA is enabled, prepare to update the descriptor below.
1474 * Otherwise, pass the access fault on to software.
1476 if (!(descriptor
& (1 << 10))) {
1478 new_descriptor
|= 1 << 10; /* AF */
1480 fi
->type
= ARMFault_AccessFlag
;
1487 * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
1488 * bit for writeback. The actual write protection test may still be
1489 * overridden by tableattrs, to be merged below.
1492 && extract64(descriptor
, 51, 1) /* DBM */
1493 && access_type
== MMU_DATA_STORE
) {
1494 if (regime_is_stage2(mmu_idx
)) {
1495 new_descriptor
|= 1ull << 7; /* set S2AP[1] */
1497 new_descriptor
&= ~(1ull << 7); /* clear AP[2] */
1503 * Extract attributes from the (modified) descriptor, and apply
1504 * table descriptors. Stage 2 table descriptors do not include
1505 * any attribute fields. HPD disables all the table attributes
1508 attrs
= new_descriptor
& (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
1509 if (!regime_is_stage2(mmu_idx
)) {
1510 attrs
|= nstable
<< 5; /* NS */
1512 attrs
|= extract64(tableattrs
, 0, 2) << 53; /* XN, PXN */
1514 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1515 * means "force PL1 access only", which means forcing AP[1] to 0.
1517 attrs
&= ~(extract64(tableattrs
, 2, 1) << 6); /* !APT[0] => AP[1] */
1518 attrs
|= extract32(tableattrs
, 3, 1) << 7; /* APT[1] => AP[2] */
1522 ap
= extract32(attrs
, 6, 2);
1523 if (regime_is_stage2(mmu_idx
)) {
1524 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1525 xn
= extract64(attrs
, 53, 2);
1526 result
->f
.prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
1528 ns
= extract32(attrs
, 5, 1);
1529 xn
= extract64(attrs
, 54, 1);
1530 pxn
= extract64(attrs
, 53, 1);
1531 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
1534 if (!(result
->f
.prot
& (1 << access_type
))) {
1535 fi
->type
= ARMFault_Permission
;
1539 /* If FEAT_HAFDBS has made changes, update the PTE. */
1540 if (new_descriptor
!= descriptor
) {
1541 new_descriptor
= arm_casq_ptw(env
, descriptor
, new_descriptor
, ptw
, fi
);
1542 if (fi
->type
!= ARMFault_None
) {
1546 * I_YZSVV says that if the in-memory descriptor has changed,
1547 * then we must use the information in that new value
1548 * (which might include a different output address, different
1549 * attributes, or generate a fault).
1550 * Restart the handling of the descriptor value from scratch.
1552 if (new_descriptor
!= descriptor
) {
1553 descriptor
= new_descriptor
;
1554 goto restart_atomic_update
;
1560 * The NS bit will (as required by the architecture) have no effect if
1561 * the CPU doesn't support TZ or this is a non-secure translation
1562 * regime, because the attribute will already be non-secure.
1564 result
->f
.attrs
.secure
= false;
1567 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
1568 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
1569 result
->f
.guarded
= extract64(attrs
, 50, 1); /* GP */
1572 if (regime_is_stage2(mmu_idx
)) {
1573 result
->cacheattrs
.is_s2_format
= true;
1574 result
->cacheattrs
.attrs
= extract32(attrs
, 2, 4);
1576 /* Index into MAIR registers for cache attributes */
1577 uint8_t attrindx
= extract32(attrs
, 2, 3);
1578 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
1579 assert(attrindx
<= 7);
1580 result
->cacheattrs
.is_s2_format
= false;
1581 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
1585 * For FEAT_LPA2 and effective DS, the SH field in the attributes
1586 * was re-purposed for output address bits. The SH attribute in
1587 * that case comes from TCR_ELx, which we extracted earlier.
1590 result
->cacheattrs
.shareability
= param
.sh
;
1592 result
->cacheattrs
.shareability
= extract32(attrs
, 8, 2);
1595 result
->f
.phys_addr
= descaddr
;
1596 result
->f
.lg_page_size
= ctz64(page_size
);
1599 do_translation_fault
:
1600 fi
->type
= ARMFault_Translation
;
1603 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
1604 fi
->stage2
= fi
->s1ptw
|| regime_is_stage2(mmu_idx
);
1605 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1609 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
1610 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1611 bool is_secure
, GetPhysAddrResult
*result
,
1612 ARMMMUFaultInfo
*fi
)
1617 bool is_user
= regime_is_user(env
, mmu_idx
);
1619 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
1621 result
->f
.phys_addr
= address
;
1622 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1626 result
->f
.phys_addr
= address
;
1627 for (n
= 7; n
>= 0; n
--) {
1628 base
= env
->cp15
.c6_region
[n
];
1629 if ((base
& 1) == 0) {
1632 mask
= 1 << ((base
>> 1) & 0x1f);
1633 /* Keep this shift separate from the above to avoid an
1634 (undefined) << 32. */
1635 mask
= (mask
<< 1) - 1;
1636 if (((base
^ address
) & ~mask
) == 0) {
1641 fi
->type
= ARMFault_Background
;
1645 if (access_type
== MMU_INST_FETCH
) {
1646 mask
= env
->cp15
.pmsav5_insn_ap
;
1648 mask
= env
->cp15
.pmsav5_data_ap
;
1650 mask
= (mask
>> (n
* 4)) & 0xf;
1653 fi
->type
= ARMFault_Permission
;
1658 fi
->type
= ARMFault_Permission
;
1662 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1665 result
->f
.prot
= PAGE_READ
;
1667 result
->f
.prot
|= PAGE_WRITE
;
1671 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1675 fi
->type
= ARMFault_Permission
;
1679 result
->f
.prot
= PAGE_READ
;
1682 result
->f
.prot
= PAGE_READ
;
1685 /* Bad permission. */
1686 fi
->type
= ARMFault_Permission
;
1690 result
->f
.prot
|= PAGE_EXEC
;
1694 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1695 int32_t address
, uint8_t *prot
)
1697 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1698 *prot
= PAGE_READ
| PAGE_WRITE
;
1700 case 0xF0000000 ... 0xFFFFFFFF:
1701 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
1702 /* hivecs execing is ok */
1706 case 0x00000000 ... 0x7FFFFFFF:
1711 /* Default system address map for M profile cores.
1712 * The architecture specifies which regions are execute-never;
1713 * at the MPU level no other checks are defined.
1716 case 0x00000000 ... 0x1fffffff: /* ROM */
1717 case 0x20000000 ... 0x3fffffff: /* SRAM */
1718 case 0x60000000 ... 0x7fffffff: /* RAM */
1719 case 0x80000000 ... 0x9fffffff: /* RAM */
1720 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1722 case 0x40000000 ... 0x5fffffff: /* Peripheral */
1723 case 0xa0000000 ... 0xbfffffff: /* Device */
1724 case 0xc0000000 ... 0xdfffffff: /* Device */
1725 case 0xe0000000 ... 0xffffffff: /* System */
1726 *prot
= PAGE_READ
| PAGE_WRITE
;
1729 g_assert_not_reached();
1734 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
1736 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
1737 return arm_feature(env
, ARM_FEATURE_M
) &&
1738 extract32(address
, 20, 12) == 0xe00;
1741 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
1744 * True if address is in the M profile system region
1745 * 0xe0000000 - 0xffffffff
1747 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
1750 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1751 bool is_secure
, bool is_user
)
1754 * Return true if we should use the default memory map as a
1755 * "background" region if there are no hits against any MPU regions.
1757 CPUARMState
*env
= &cpu
->env
;
1763 if (arm_feature(env
, ARM_FEATURE_M
)) {
1764 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
1767 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1771 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
1774 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
1775 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1776 bool secure
, GetPhysAddrResult
*result
,
1777 ARMMMUFaultInfo
*fi
)
1779 ARMCPU
*cpu
= env_archcpu(env
);
1781 bool is_user
= regime_is_user(env
, mmu_idx
);
1783 result
->f
.phys_addr
= address
;
1784 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1787 if (regime_translation_disabled(env
, mmu_idx
, secure
) ||
1788 m_is_ppb_region(env
, address
)) {
1790 * MPU disabled or M profile PPB access: use default memory map.
1791 * The other case which uses the default memory map in the
1792 * v7M ARM ARM pseudocode is exception vector reads from the vector
1793 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
1794 * which always does a direct read using address_space_ldl(), rather
1795 * than going via this function, so we don't need to check that here.
1797 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1798 } else { /* MPU enabled */
1799 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1801 uint32_t base
= env
->pmsav7
.drbar
[n
];
1802 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
1806 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
1811 qemu_log_mask(LOG_GUEST_ERROR
,
1812 "DRSR[%d]: Rsize field cannot be 0\n", n
);
1816 rmask
= (1ull << rsize
) - 1;
1819 qemu_log_mask(LOG_GUEST_ERROR
,
1820 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
1821 "to DRSR region size, mask = 0x%" PRIx32
"\n",
1826 if (address
< base
|| address
> base
+ rmask
) {
1828 * Address not in this region. We must check whether the
1829 * region covers addresses in the same page as our address.
1830 * In that case we must not report a size that covers the
1831 * whole page for a subsequent hit against a different MPU
1832 * region or the background region, because it would result in
1833 * incorrect TLB hits for subsequent accesses to addresses that
1834 * are in this MPU region.
1836 if (ranges_overlap(base
, rmask
,
1837 address
& TARGET_PAGE_MASK
,
1838 TARGET_PAGE_SIZE
)) {
1839 result
->f
.lg_page_size
= 0;
1844 /* Region matched */
1846 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
1848 uint32_t srdis_mask
;
1850 rsize
-= 3; /* sub region size (power of 2) */
1851 snd
= ((address
- base
) >> rsize
) & 0x7;
1852 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
1854 srdis_mask
= srdis
? 0x3 : 0x0;
1855 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
1857 * This will check in groups of 2, 4 and then 8, whether
1858 * the subregion bits are consistent. rsize is incremented
1859 * back up to give the region size, considering consistent
1860 * adjacent subregions as one region. Stop testing if rsize
1861 * is already big enough for an entire QEMU page.
1863 int snd_rounded
= snd
& ~(i
- 1);
1864 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
1865 snd_rounded
+ 8, i
);
1866 if (srdis_mask
^ srdis_multi
) {
1869 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
1876 if (rsize
< TARGET_PAGE_BITS
) {
1877 result
->f
.lg_page_size
= rsize
;
1882 if (n
== -1) { /* no hits */
1883 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1884 /* background fault */
1885 fi
->type
= ARMFault_Background
;
1888 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
1890 } else { /* a MPU hit! */
1891 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
1892 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
1894 if (m_is_system_region(env
, address
)) {
1895 /* System space is always execute never */
1899 if (is_user
) { /* User mode AP bit decoding */
1904 break; /* no access */
1906 result
->f
.prot
|= PAGE_WRITE
;
1910 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1913 /* for v7M, same as 6; for R profile a reserved value */
1914 if (arm_feature(env
, ARM_FEATURE_M
)) {
1915 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1920 qemu_log_mask(LOG_GUEST_ERROR
,
1921 "DRACR[%d]: Bad value for AP bits: 0x%"
1922 PRIx32
"\n", n
, ap
);
1924 } else { /* Priv. mode AP bits decoding */
1927 break; /* no access */
1931 result
->f
.prot
|= PAGE_WRITE
;
1935 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1938 /* for v7M, same as 6; for R profile a reserved value */
1939 if (arm_feature(env
, ARM_FEATURE_M
)) {
1940 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1945 qemu_log_mask(LOG_GUEST_ERROR
,
1946 "DRACR[%d]: Bad value for AP bits: 0x%"
1947 PRIx32
"\n", n
, ap
);
1953 result
->f
.prot
&= ~PAGE_EXEC
;
1958 fi
->type
= ARMFault_Permission
;
1960 return !(result
->f
.prot
& (1 << access_type
));
1963 static uint32_t *regime_rbar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1966 if (regime_el(env
, mmu_idx
) == 2) {
1967 return env
->pmsav8
.hprbar
;
1969 return env
->pmsav8
.rbar
[secure
];
1973 static uint32_t *regime_rlar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1976 if (regime_el(env
, mmu_idx
) == 2) {
1977 return env
->pmsav8
.hprlar
;
1979 return env
->pmsav8
.rlar
[secure
];
1983 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
1984 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1985 bool secure
, GetPhysAddrResult
*result
,
1986 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
1989 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
1990 * that a full phys-to-virt translation does).
1991 * mregion is (if not NULL) set to the region number which matched,
1992 * or -1 if no region number is returned (MPU off, address did not
1993 * hit a region, address hit in multiple regions).
1994 * If the region hit doesn't cover the entire TARGET_PAGE the address
1995 * is within, then we set the result page_size to 1 to force the
1996 * memory system to use a subpage.
1998 ARMCPU
*cpu
= env_archcpu(env
);
1999 bool is_user
= regime_is_user(env
, mmu_idx
);
2001 int matchregion
= -1;
2003 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2004 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2007 if (regime_el(env
, mmu_idx
) == 2) {
2008 region_counter
= cpu
->pmsav8r_hdregion
;
2010 region_counter
= cpu
->pmsav7_dregion
;
2013 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2014 result
->f
.phys_addr
= address
;
2020 if (mmu_idx
== ARMMMUIdx_Stage2
) {
2025 * Unlike the ARM ARM pseudocode, we don't need to check whether this
2026 * was an exception vector read from the vector table (which is always
2027 * done using the default system address map), because those accesses
2028 * are done in arm_v7m_load_vector(), which always does a direct
2029 * read using address_space_ldl(), rather than going via this function.
2031 if (regime_translation_disabled(env
, mmu_idx
, secure
)) { /* MPU disabled */
2033 } else if (m_is_ppb_region(env
, address
)) {
2036 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
2041 if (arm_feature(env
, ARM_FEATURE_M
)) {
2048 for (n
= region_counter
- 1; n
>= 0; n
--) {
2051 * Note that the base address is bits [31:x] from the register
2052 * with bits [x-1:0] all zeroes, but the limit address is bits
2053 * [31:x] from the register with bits [x:0] all ones. Where x is
2054 * 5 for Cortex-M and 6 for Cortex-R
2056 uint32_t base
= regime_rbar(env
, mmu_idx
, secure
)[n
] & ~bitmask
;
2057 uint32_t limit
= regime_rlar(env
, mmu_idx
, secure
)[n
] | bitmask
;
2059 if (!(regime_rlar(env
, mmu_idx
, secure
)[n
] & 0x1)) {
2060 /* Region disabled */
2064 if (address
< base
|| address
> limit
) {
2066 * Address not in this region. We must check whether the
2067 * region covers addresses in the same page as our address.
2068 * In that case we must not report a size that covers the
2069 * whole page for a subsequent hit against a different MPU
2070 * region or the background region, because it would result in
2071 * incorrect TLB hits for subsequent accesses to addresses that
2072 * are in this MPU region.
2074 if (limit
>= base
&&
2075 ranges_overlap(base
, limit
- base
+ 1,
2077 TARGET_PAGE_SIZE
)) {
2078 result
->f
.lg_page_size
= 0;
2083 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2084 result
->f
.lg_page_size
= 0;
2087 if (matchregion
!= -1) {
2089 * Multiple regions match -- always a failure (unlike
2090 * PMSAv7 where highest-numbered-region wins)
2092 fi
->type
= ARMFault_Permission
;
2093 if (arm_feature(env
, ARM_FEATURE_M
)) {
2105 if (arm_feature(env
, ARM_FEATURE_M
)) {
2106 fi
->type
= ARMFault_Background
;
2108 fi
->type
= ARMFault_Permission
;
2113 if (matchregion
== -1) {
2114 /* hit using the background region */
2115 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2117 uint32_t matched_rbar
= regime_rbar(env
, mmu_idx
, secure
)[matchregion
];
2118 uint32_t matched_rlar
= regime_rlar(env
, mmu_idx
, secure
)[matchregion
];
2119 uint32_t ap
= extract32(matched_rbar
, 1, 2);
2120 uint32_t xn
= extract32(matched_rbar
, 0, 1);
2123 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
2124 pxn
= extract32(matched_rlar
, 4, 1);
2127 if (m_is_system_region(env
, address
)) {
2128 /* System space is always execute never */
2132 if (regime_el(env
, mmu_idx
) == 2) {
2133 result
->f
.prot
= simple_ap_to_rw_prot_is_user(ap
,
2134 mmu_idx
!= ARMMMUIdx_E2
);
2136 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
2139 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2140 uint8_t attrindx
= extract32(matched_rlar
, 1, 3);
2141 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
2142 uint8_t sh
= extract32(matched_rlar
, 3, 2);
2144 if (regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
&&
2145 result
->f
.prot
& PAGE_WRITE
&& mmu_idx
!= ARMMMUIdx_Stage2
) {
2149 if ((regime_el(env
, mmu_idx
) == 1) &&
2150 regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
&& ap
== 0x1) {
2154 result
->cacheattrs
.is_s2_format
= false;
2155 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
2156 result
->cacheattrs
.shareability
= sh
;
2159 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
2160 result
->f
.prot
|= PAGE_EXEC
;
2164 *mregion
= matchregion
;
2168 fi
->type
= ARMFault_Permission
;
2169 if (arm_feature(env
, ARM_FEATURE_M
)) {
2172 return !(result
->f
.prot
& (1 << access_type
));
2175 static bool v8m_is_sau_exempt(CPUARMState
*env
,
2176 uint32_t address
, MMUAccessType access_type
)
2179 * The architecture specifies that certain address ranges are
2180 * exempt from v8M SAU/IDAU checks.
2183 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
2184 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
2185 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
2186 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
2187 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
2188 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
2191 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
2192 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2193 bool is_secure
, V8M_SAttributes
*sattrs
)
2196 * Look up the security attributes for this address. Compare the
2197 * pseudocode SecurityCheck() function.
2198 * We assume the caller has zero-initialized *sattrs.
2200 ARMCPU
*cpu
= env_archcpu(env
);
2202 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
2203 int idau_region
= IREGION_NOTVALID
;
2204 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2205 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2208 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
2209 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
2211 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
2215 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
2216 /* 0xf0000000..0xffffffff is always S for insn fetches */
2220 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
2221 sattrs
->ns
= !is_secure
;
2225 if (idau_region
!= IREGION_NOTVALID
) {
2226 sattrs
->irvalid
= true;
2227 sattrs
->iregion
= idau_region
;
2230 switch (env
->sau
.ctrl
& 3) {
2231 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
2233 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
2236 default: /* SAU.ENABLE == 1 */
2237 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
2238 if (env
->sau
.rlar
[r
] & 1) {
2239 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
2240 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
2242 if (base
<= address
&& limit
>= address
) {
2243 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2244 sattrs
->subpage
= true;
2246 if (sattrs
->srvalid
) {
2248 * If we hit in more than one region then we must report
2249 * as Secure, not NS-Callable, with no valid region
2253 sattrs
->nsc
= false;
2254 sattrs
->sregion
= 0;
2255 sattrs
->srvalid
= false;
2258 if (env
->sau
.rlar
[r
] & 2) {
2263 sattrs
->srvalid
= true;
2264 sattrs
->sregion
= r
;
2268 * Address not in this region. We must check whether the
2269 * region covers addresses in the same page as our address.
2270 * In that case we must not report a size that covers the
2271 * whole page for a subsequent hit against a different MPU
2272 * region or the background region, because it would result
2273 * in incorrect TLB hits for subsequent accesses to
2274 * addresses that are in this MPU region.
2276 if (limit
>= base
&&
2277 ranges_overlap(base
, limit
- base
+ 1,
2279 TARGET_PAGE_SIZE
)) {
2280 sattrs
->subpage
= true;
2289 * The IDAU will override the SAU lookup results if it specifies
2290 * higher security than the SAU does.
2293 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
2295 sattrs
->nsc
= idau_nsc
;
2300 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
2301 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2302 bool secure
, GetPhysAddrResult
*result
,
2303 ARMMMUFaultInfo
*fi
)
2305 V8M_SAttributes sattrs
= {};
2308 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2309 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2311 if (access_type
== MMU_INST_FETCH
) {
2313 * Instruction fetches always use the MMU bank and the
2314 * transaction attribute determined by the fetch address,
2315 * regardless of CPU state. This is painful for QEMU
2316 * to handle, because it would mean we need to encode
2317 * into the mmu_idx not just the (user, negpri) information
2318 * for the current security state but also that for the
2319 * other security state, which would balloon the number
2320 * of mmu_idx values needed alarmingly.
2321 * Fortunately we can avoid this because it's not actually
2322 * possible to arbitrarily execute code from memory with
2323 * the wrong security attribute: it will always generate
2324 * an exception of some kind or another, apart from the
2325 * special case of an NS CPU executing an SG instruction
2326 * in S&NSC memory. So we always just fail the translation
2327 * here and sort things out in the exception handler
2328 * (including possibly emulating an SG instruction).
2330 if (sattrs
.ns
!= !secure
) {
2332 fi
->type
= ARMFault_QEMU_NSCExec
;
2334 fi
->type
= ARMFault_QEMU_SFault
;
2336 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2337 result
->f
.phys_addr
= address
;
2343 * For data accesses we always use the MMU bank indicated
2344 * by the current CPU state, but the security attributes
2345 * might downgrade a secure access to nonsecure.
2348 result
->f
.attrs
.secure
= false;
2349 } else if (!secure
) {
2351 * NS access to S memory must fault.
2352 * Architecturally we should first check whether the
2353 * MPU information for this address indicates that we
2354 * are doing an unaligned access to Device memory, which
2355 * should generate a UsageFault instead. QEMU does not
2356 * currently check for that kind of unaligned access though.
2357 * If we added it we would need to do so as a special case
2358 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2360 fi
->type
= ARMFault_QEMU_SFault
;
2361 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2362 result
->f
.phys_addr
= address
;
2369 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2371 if (sattrs
.subpage
) {
2372 result
->f
.lg_page_size
= 0;
2378 * Translate from the 4-bit stage 2 representation of
2379 * memory attributes (without cache-allocation hints) to
2380 * the 8-bit representation of the stage 1 MAIR registers
2381 * (which includes allocation hints).
2383 * ref: shared/translation/attrs/S2AttrDecode()
2384 * .../S2ConvertAttrsHints()
2386 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2388 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2389 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2390 uint8_t hihint
= 0, lohint
= 0;
2392 if (hiattr
!= 0) { /* normal memory */
2393 if (hcr
& HCR_CD
) { /* cache disabled */
2394 hiattr
= loattr
= 1; /* non-cacheable */
2396 if (hiattr
!= 1) { /* Write-through or write-back */
2397 hihint
= 3; /* RW allocate */
2399 if (loattr
!= 1) { /* Write-through or write-back */
2400 lohint
= 3; /* RW allocate */
2405 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2409 * Combine either inner or outer cacheability attributes for normal
2410 * memory, according to table D4-42 and pseudocode procedure
2411 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2413 * NB: only stage 1 includes allocation hints (RW bits), leading to
2416 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2418 if (s1
== 4 || s2
== 4) {
2419 /* non-cacheable has precedence */
2421 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2422 /* stage 1 write-through takes precedence */
2424 } else if (extract32(s2
, 2, 2) == 2) {
2425 /* stage 2 write-through takes precedence, but the allocation hint
2426 * is still taken from stage 1
2428 return (2 << 2) | extract32(s1
, 0, 2);
2429 } else { /* write-back */
2435 * Combine the memory type and cacheability attributes of
2436 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2437 * combined attributes in MAIR_EL1 format.
2439 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2440 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2442 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2444 if (s2
.is_s2_format
) {
2445 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2447 s2_mair_attrs
= s2
.attrs
;
2450 s1lo
= extract32(s1
.attrs
, 0, 4);
2451 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2452 s1hi
= extract32(s1
.attrs
, 4, 4);
2453 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2455 /* Combine memory type and cacheability attributes */
2456 if (s1hi
== 0 || s2hi
== 0) {
2457 /* Device has precedence over normal */
2458 if (s1lo
== 0 || s2lo
== 0) {
2459 /* nGnRnE has precedence over anything */
2461 } else if (s1lo
== 4 || s2lo
== 4) {
2462 /* non-Reordering has precedence over Reordering */
2463 ret_attrs
= 4; /* nGnRE */
2464 } else if (s1lo
== 8 || s2lo
== 8) {
2465 /* non-Gathering has precedence over Gathering */
2466 ret_attrs
= 8; /* nGRE */
2468 ret_attrs
= 0xc; /* GRE */
2470 } else { /* Normal memory */
2471 /* Outer/inner cacheability combine independently */
2472 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2473 | combine_cacheattr_nibble(s1lo
, s2lo
);
2478 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2481 * Given the 4 bits specifying the outer or inner cacheability
2482 * in MAIR format, return a value specifying Normal Write-Back,
2483 * with the allocation and transient hints taken from the input
2484 * if the input specified some kind of cacheable attribute.
2486 if (attr
== 0 || attr
== 4) {
2488 * 0 == an UNPREDICTABLE encoding
2489 * 4 == Non-cacheable
2490 * Either way, force Write-Back RW allocate non-transient
2494 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2499 * Combine the memory type and cacheability attributes of
2500 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2501 * combined attributes in MAIR_EL1 format.
2503 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2505 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2509 /* Use stage 1 attributes */
2513 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2514 * then we take the allocation hints from it; otherwise it is
2515 * RW allocate, non-transient.
2517 if ((s1
.attrs
& 0xf0) == 0) {
2521 /* Need to check the Inner and Outer nibbles separately */
2522 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2523 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
2525 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
2526 if ((s1
.attrs
& 0xf0) == 0) {
2531 /* Force Device, of subtype specified by S2 */
2532 return s2
.attrs
<< 2;
2535 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
2536 * arbitrarily force Device.
2543 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
2544 * and CombineS1S2Desc()
2547 * @s1: Attributes from stage 1 walk
2548 * @s2: Attributes from stage 2 walk
2550 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
2551 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2554 bool tagged
= false;
2556 assert(!s1
.is_s2_format
);
2557 ret
.is_s2_format
= false;
2559 if (s1
.attrs
== 0xf0) {
2564 /* Combine shareability attributes (table D4-43) */
2565 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
2566 /* if either are outer-shareable, the result is outer-shareable */
2567 ret
.shareability
= 2;
2568 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
2569 /* if either are inner-shareable, the result is inner-shareable */
2570 ret
.shareability
= 3;
2572 /* both non-shareable */
2573 ret
.shareability
= 0;
2576 /* Combine memory type and cacheability attributes */
2577 if (hcr
& HCR_FWB
) {
2578 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
2580 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
2584 * Any location for which the resultant memory type is any
2585 * type of Device memory is always treated as Outer Shareable.
2586 * Any location for which the resultant memory type is Normal
2587 * Inner Non-cacheable, Outer Non-cacheable is always treated
2588 * as Outer Shareable.
2589 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
2591 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
2592 ret
.shareability
= 2;
2595 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
2596 if (tagged
&& ret
.attrs
== 0xff) {
2604 * MMU disabled. S1 addresses within aa64 translation regimes are
2605 * still checked for bounds -- see AArch64.S1DisabledOutput().
2607 static bool get_phys_addr_disabled(CPUARMState
*env
, target_ulong address
,
2608 MMUAccessType access_type
,
2609 ARMMMUIdx mmu_idx
, bool is_secure
,
2610 GetPhysAddrResult
*result
,
2611 ARMMMUFaultInfo
*fi
)
2613 uint8_t memattr
= 0x00; /* Device nGnRnE */
2614 uint8_t shareability
= 0; /* non-sharable */
2618 case ARMMMUIdx_Stage2
:
2619 case ARMMMUIdx_Stage2_S
:
2620 case ARMMMUIdx_Phys_NS
:
2621 case ARMMMUIdx_Phys_S
:
2625 r_el
= regime_el(env
, mmu_idx
);
2626 if (arm_el_is_aa64(env
, r_el
)) {
2627 int pamax
= arm_pamax(env_archcpu(env
));
2628 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
2631 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
2632 if (access_type
== MMU_INST_FETCH
) {
2633 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
2635 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
2636 addrtop
= (tbi
? 55 : 63);
2638 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
2639 fi
->type
= ARMFault_AddressSize
;
2646 * When TBI is disabled, we've just validated that all of the
2647 * bits above PAMax are zero, so logically we only need to
2648 * clear the top byte for TBI. But it's clearer to follow
2649 * the pseudocode set of addrdesc.paddress.
2651 address
= extract64(address
, 0, 52);
2654 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
2656 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2658 if (hcr
& HCR_DCT
) {
2659 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
2661 memattr
= 0xff; /* Normal, WB, RWA */
2665 if (memattr
== 0 && access_type
== MMU_INST_FETCH
) {
2666 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
2667 memattr
= 0xee; /* Normal, WT, RA, NT */
2669 memattr
= 0x44; /* Normal, NC, No */
2671 shareability
= 2; /* outer sharable */
2673 result
->cacheattrs
.is_s2_format
= false;
2677 result
->f
.phys_addr
= address
;
2678 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2679 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2680 result
->cacheattrs
.shareability
= shareability
;
2681 result
->cacheattrs
.attrs
= memattr
;
2685 static bool get_phys_addr_twostage(CPUARMState
*env
, S1Translate
*ptw
,
2686 target_ulong address
,
2687 MMUAccessType access_type
,
2688 GetPhysAddrResult
*result
,
2689 ARMMMUFaultInfo
*fi
)
2692 int s1_prot
, s1_lgpgsz
;
2693 bool is_secure
= ptw
->in_secure
;
2694 bool ret
, ipa_secure
, s2walk_secure
;
2695 ARMCacheAttrs cacheattrs1
;
2699 ret
= get_phys_addr_with_struct(env
, ptw
, address
, access_type
, result
, fi
);
2701 /* If S1 fails, return early. */
2706 ipa
= result
->f
.phys_addr
;
2707 ipa_secure
= result
->f
.attrs
.secure
;
2709 /* Select TCR based on the NS bit from the S1 walk. */
2710 s2walk_secure
= !(ipa_secure
2711 ? env
->cp15
.vstcr_el2
& VSTCR_SW
2712 : env
->cp15
.vtcr_el2
& VTCR_NSW
);
2714 assert(!ipa_secure
);
2715 s2walk_secure
= false;
2718 is_el0
= ptw
->in_mmu_idx
== ARMMMUIdx_Stage1_E0
;
2719 ptw
->in_mmu_idx
= s2walk_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2720 ptw
->in_ptw_idx
= s2walk_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2721 ptw
->in_secure
= s2walk_secure
;
2724 * S1 is done, now do S2 translation.
2725 * Save the stage1 results so that we may merge prot and cacheattrs later.
2727 s1_prot
= result
->f
.prot
;
2728 s1_lgpgsz
= result
->f
.lg_page_size
;
2729 cacheattrs1
= result
->cacheattrs
;
2730 memset(result
, 0, sizeof(*result
));
2732 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2733 ret
= get_phys_addr_pmsav8(env
, ipa
, access_type
,
2734 ptw
->in_mmu_idx
, is_secure
, result
, fi
);
2736 ret
= get_phys_addr_lpae(env
, ptw
, ipa
, access_type
,
2737 is_el0
, result
, fi
);
2741 /* Combine the S1 and S2 perms. */
2742 result
->f
.prot
&= s1_prot
;
2744 /* If S2 fails, return early. */
2750 * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
2751 * this means "don't put this in the TLB"; in this case, return a
2752 * result with lg_page_size == 0 to achieve that. Otherwise,
2753 * use the maximum of the S1 & S2 page size, so that invalidation
2754 * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
2755 * we know the combined result permissions etc only cover the minimum
2756 * of the S1 and S2 page size, because we know that the common TLB code
2757 * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
2758 * and passing a larger page size value only affects invalidations.)
2760 if (result
->f
.lg_page_size
< TARGET_PAGE_BITS
||
2761 s1_lgpgsz
< TARGET_PAGE_BITS
) {
2762 result
->f
.lg_page_size
= 0;
2763 } else if (result
->f
.lg_page_size
< s1_lgpgsz
) {
2764 result
->f
.lg_page_size
= s1_lgpgsz
;
2767 /* Combine the S1 and S2 cache attributes. */
2768 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2771 * HCR.DC forces the first stage attributes to
2772 * Normal Non-Shareable,
2773 * Inner Write-Back Read-Allocate Write-Allocate,
2774 * Outer Write-Back Read-Allocate Write-Allocate.
2775 * Do not overwrite Tagged within attrs.
2777 if (cacheattrs1
.attrs
!= 0xf0) {
2778 cacheattrs1
.attrs
= 0xff;
2780 cacheattrs1
.shareability
= 0;
2782 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
2783 result
->cacheattrs
);
2786 * Check if IPA translates to secure or non-secure PA space.
2787 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
2789 result
->f
.attrs
.secure
=
2791 && !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
2793 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
))));
2798 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
2799 target_ulong address
,
2800 MMUAccessType access_type
,
2801 GetPhysAddrResult
*result
,
2802 ARMMMUFaultInfo
*fi
)
2804 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2805 bool is_secure
= ptw
->in_secure
;
2806 ARMMMUIdx s1_mmu_idx
;
2809 * The page table entries may downgrade secure to non-secure, but
2810 * cannot upgrade an non-secure translation regime's attributes
2813 result
->f
.attrs
.secure
= is_secure
;
2816 case ARMMMUIdx_Phys_S
:
2817 case ARMMMUIdx_Phys_NS
:
2818 /* Checking Phys early avoids special casing later vs regime_el. */
2819 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2820 is_secure
, result
, fi
);
2822 case ARMMMUIdx_Stage1_E0
:
2823 case ARMMMUIdx_Stage1_E1
:
2824 case ARMMMUIdx_Stage1_E1_PAN
:
2825 /* First stage lookup uses second stage for ptw. */
2826 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2829 case ARMMMUIdx_E10_0
:
2830 s1_mmu_idx
= ARMMMUIdx_Stage1_E0
;
2832 case ARMMMUIdx_E10_1
:
2833 s1_mmu_idx
= ARMMMUIdx_Stage1_E1
;
2835 case ARMMMUIdx_E10_1_PAN
:
2836 s1_mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
2839 * Call ourselves recursively to do the stage 1 and then stage 2
2840 * translations if mmu_idx is a two-stage regime, and EL2 present.
2841 * Otherwise, a stage1+stage2 translation is just stage 1.
2843 ptw
->in_mmu_idx
= mmu_idx
= s1_mmu_idx
;
2844 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2845 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
, is_secure
)) {
2846 return get_phys_addr_twostage(env
, ptw
, address
, access_type
,
2852 /* Single stage and second stage uses physical for ptw. */
2853 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2857 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
2860 * Fast Context Switch Extension. This doesn't exist at all in v8.
2861 * In v7 and earlier it affects all stage 1 translations.
2863 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
2864 && !arm_feature(env
, ARM_FEATURE_V8
)) {
2865 if (regime_el(env
, mmu_idx
) == 3) {
2866 address
+= env
->cp15
.fcseidr_s
;
2868 address
+= env
->cp15
.fcseidr_ns
;
2872 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2874 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2876 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2878 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
2879 is_secure
, result
, fi
);
2880 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2882 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
2883 is_secure
, result
, fi
);
2886 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
2887 is_secure
, result
, fi
);
2889 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
2890 " mmu_idx %u -> %s (prot %c%c%c)\n",
2891 access_type
== MMU_DATA_LOAD
? "reading" :
2892 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
2893 (uint32_t)address
, mmu_idx
,
2894 ret
? "Miss" : "Hit",
2895 result
->f
.prot
& PAGE_READ
? 'r' : '-',
2896 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
2897 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
2902 /* Definitely a real MMU, not an MPU */
2904 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
2905 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2906 is_secure
, result
, fi
);
2909 if (regime_using_lpae_format(env
, mmu_idx
)) {
2910 return get_phys_addr_lpae(env
, ptw
, address
, access_type
, false,
2912 } else if (arm_feature(env
, ARM_FEATURE_V7
) ||
2913 regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
2914 return get_phys_addr_v6(env
, ptw
, address
, access_type
, result
, fi
);
2916 return get_phys_addr_v5(env
, ptw
, address
, access_type
, result
, fi
);
2920 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
2921 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2922 bool is_secure
, GetPhysAddrResult
*result
,
2923 ARMMMUFaultInfo
*fi
)
2926 .in_mmu_idx
= mmu_idx
,
2927 .in_secure
= is_secure
,
2929 return get_phys_addr_with_struct(env
, &ptw
, address
, access_type
,
2933 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
2934 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2935 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
2940 case ARMMMUIdx_E10_0
:
2941 case ARMMMUIdx_E10_1
:
2942 case ARMMMUIdx_E10_1_PAN
:
2943 case ARMMMUIdx_E20_0
:
2944 case ARMMMUIdx_E20_2
:
2945 case ARMMMUIdx_E20_2_PAN
:
2946 case ARMMMUIdx_Stage1_E0
:
2947 case ARMMMUIdx_Stage1_E1
:
2948 case ARMMMUIdx_Stage1_E1_PAN
:
2950 is_secure
= arm_is_secure_below_el3(env
);
2952 case ARMMMUIdx_Stage2
:
2953 case ARMMMUIdx_Phys_NS
:
2954 case ARMMMUIdx_MPrivNegPri
:
2955 case ARMMMUIdx_MUserNegPri
:
2956 case ARMMMUIdx_MPriv
:
2957 case ARMMMUIdx_MUser
:
2961 case ARMMMUIdx_Stage2_S
:
2962 case ARMMMUIdx_Phys_S
:
2963 case ARMMMUIdx_MSPrivNegPri
:
2964 case ARMMMUIdx_MSUserNegPri
:
2965 case ARMMMUIdx_MSPriv
:
2966 case ARMMMUIdx_MSUser
:
2970 g_assert_not_reached();
2972 return get_phys_addr_with_secure(env
, address
, access_type
, mmu_idx
,
2973 is_secure
, result
, fi
);
2976 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
2979 ARMCPU
*cpu
= ARM_CPU(cs
);
2980 CPUARMState
*env
= &cpu
->env
;
2982 .in_mmu_idx
= arm_mmu_idx(env
),
2983 .in_secure
= arm_is_secure(env
),
2986 GetPhysAddrResult res
= {};
2987 ARMMMUFaultInfo fi
= {};
2990 ret
= get_phys_addr_with_struct(env
, &ptw
, addr
, MMU_DATA_LOAD
, &res
, &fi
);
2991 *attrs
= res
.f
.attrs
;
2996 return res
.f
.phys_addr
;