2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
15 #include "internals.h"
19 typedef struct S1Translate
{
32 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
34 MMUAccessType access_type
, bool s1_is_el0
,
35 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
36 __attribute__((nonnull
));
38 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
40 MMUAccessType access_type
,
41 GetPhysAddrResult
*result
,
43 __attribute__((nonnull
));
45 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
46 static const uint8_t pamax_map
[] = {
56 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
57 unsigned int arm_pamax(ARMCPU
*cpu
)
59 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
60 unsigned int parange
=
61 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
64 * id_aa64mmfr0 is a read-only register so values outside of the
65 * supported mappings can be considered an implementation error.
67 assert(parange
< ARRAY_SIZE(pamax_map
));
68 return pamax_map
[parange
];
72 * In machvirt_init, we call arm_pamax on a cpu that is not fully
73 * initialized, so we can't rely on the propagation done in realize.
75 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
76 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
85 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
87 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
91 return ARMMMUIdx_Stage1_E0
;
93 return ARMMMUIdx_Stage1_E1
;
94 case ARMMMUIdx_E10_1_PAN
:
95 return ARMMMUIdx_Stage1_E1_PAN
;
101 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
103 return stage_1_mmu_idx(arm_mmu_idx(env
));
107 * Return where we should do ptw loads from for a stage 2 walk.
108 * This depends on whether the address we are looking up is a
109 * Secure IPA or a NonSecure IPA, which we know from whether this is
110 * Stage2 or Stage2_S.
111 * If this is the Secure EL1&0 regime we need to check the NSW and SW bits.
113 static ARMMMUIdx
ptw_idx_for_stage_2(CPUARMState
*env
, ARMMMUIdx stage2idx
)
118 * We're OK to check the current state of the CPU here because
119 * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes
120 * (2) there's no way to do a lookup that cares about Stage 2 for a
121 * different security state to the current one for AArch64, and AArch32
122 * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do
123 * an NS stage 1+2 lookup while the NS bit is 0.)
125 if (!arm_is_secure_below_el3(env
) || !arm_el_is_aa64(env
, 3)) {
126 return ARMMMUIdx_Phys_NS
;
128 if (stage2idx
== ARMMMUIdx_Stage2_S
) {
129 s2walk_secure
= !(env
->cp15
.vstcr_el2
& VSTCR_SW
);
131 s2walk_secure
= !(env
->cp15
.vtcr_el2
& VTCR_NSW
);
133 return s2walk_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
137 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
139 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
142 /* Return the TTBR associated with this translation regime */
143 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
145 if (mmu_idx
== ARMMMUIdx_Stage2
) {
146 return env
->cp15
.vttbr_el2
;
148 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
149 return env
->cp15
.vsttbr_el2
;
152 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
154 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
158 /* Return true if the specified stage of address translation is disabled */
159 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
164 if (arm_feature(env
, ARM_FEATURE_M
)) {
165 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
166 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
167 case R_V7M_MPU_CTRL_ENABLE_MASK
:
168 /* Enabled, but not for HardFault and NMI */
169 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
170 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
171 /* Enabled for all cases */
176 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
177 * we warned about that in armv7m_nvic.c when the guest set it.
183 hcr_el2
= arm_hcr_el2_eff_secstate(env
, is_secure
);
186 case ARMMMUIdx_Stage2
:
187 case ARMMMUIdx_Stage2_S
:
188 /* HCR.DC means HCR.VM behaves as 1 */
189 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
191 case ARMMMUIdx_E10_0
:
192 case ARMMMUIdx_E10_1
:
193 case ARMMMUIdx_E10_1_PAN
:
194 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
195 if (hcr_el2
& HCR_TGE
) {
200 case ARMMMUIdx_Stage1_E0
:
201 case ARMMMUIdx_Stage1_E1
:
202 case ARMMMUIdx_Stage1_E1_PAN
:
203 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
204 if (hcr_el2
& HCR_DC
) {
209 case ARMMMUIdx_E20_0
:
210 case ARMMMUIdx_E20_2
:
211 case ARMMMUIdx_E20_2_PAN
:
216 case ARMMMUIdx_Phys_NS
:
217 case ARMMMUIdx_Phys_S
:
218 /* No translation for physical address spaces. */
222 g_assert_not_reached();
225 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
228 static bool S2_attrs_are_device(uint64_t hcr
, uint8_t attrs
)
231 * For an S1 page table walk, the stage 1 attributes are always
232 * some form of "this is Normal memory". The combined S1+S2
233 * attributes are therefore only Device if stage 2 specifies Device.
234 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
235 * ie when cacheattrs.attrs bits [3:2] are 0b00.
236 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
237 * when cacheattrs.attrs bit [2] is 0.
240 return (attrs
& 0x4) == 0;
242 return (attrs
& 0xc) == 0;
246 /* Translate a S1 pagetable walk through S2 if needed. */
247 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
248 hwaddr addr
, ARMMMUFaultInfo
*fi
)
250 bool is_secure
= ptw
->in_secure
;
251 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
252 ARMMMUIdx s2_mmu_idx
= ptw
->in_ptw_idx
;
255 ptw
->out_virt
= addr
;
257 if (unlikely(ptw
->in_debug
)) {
259 * From gdbstub, do not use softmmu so that we don't modify the
260 * state of the cpu at all, including softmmu tlb contents.
262 if (regime_is_stage2(s2_mmu_idx
)) {
263 S1Translate s2ptw
= {
264 .in_mmu_idx
= s2_mmu_idx
,
265 .in_ptw_idx
= ptw_idx_for_stage_2(env
, s2_mmu_idx
),
266 .in_secure
= s2_mmu_idx
== ARMMMUIdx_Stage2_S
,
269 GetPhysAddrResult s2
= { };
271 if (get_phys_addr_lpae(env
, &s2ptw
, addr
, MMU_DATA_LOAD
,
275 ptw
->out_phys
= s2
.f
.phys_addr
;
276 pte_attrs
= s2
.cacheattrs
.attrs
;
277 ptw
->out_secure
= s2
.f
.attrs
.secure
;
279 /* Regime is physical. */
280 ptw
->out_phys
= addr
;
282 ptw
->out_secure
= s2_mmu_idx
== ARMMMUIdx_Phys_S
;
284 ptw
->out_host
= NULL
;
288 CPUTLBEntryFull
*full
;
292 flags
= probe_access_full(env
, addr
, 0, MMU_DATA_LOAD
,
293 arm_to_core_mmu_idx(s2_mmu_idx
),
294 true, &ptw
->out_host
, &full
, 0);
297 if (unlikely(flags
& TLB_INVALID_MASK
)) {
300 ptw
->out_phys
= full
->phys_addr
| (addr
& ~TARGET_PAGE_MASK
);
301 ptw
->out_rw
= full
->prot
& PAGE_WRITE
;
302 pte_attrs
= full
->pte_attrs
;
303 ptw
->out_secure
= full
->attrs
.secure
;
305 g_assert_not_reached();
309 if (regime_is_stage2(s2_mmu_idx
)) {
310 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
312 if ((hcr
& HCR_PTW
) && S2_attrs_are_device(hcr
, pte_attrs
)) {
314 * PTW set and S1 walk touched S2 Device memory:
315 * generate Permission fault.
317 fi
->type
= ARMFault_Permission
;
321 fi
->s1ns
= !is_secure
;
326 ptw
->out_be
= regime_translation_big_endian(env
, mmu_idx
);
330 assert(fi
->type
!= ARMFault_None
);
334 fi
->s1ns
= !is_secure
;
338 /* All loads done in the course of a page table walk go through here. */
339 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
,
342 CPUState
*cs
= env_cpu(env
);
343 void *host
= ptw
->out_host
;
347 /* Page tables are in RAM, and we have the host address. */
348 data
= qatomic_read((uint32_t *)host
);
350 data
= be32_to_cpu(data
);
352 data
= le32_to_cpu(data
);
355 /* Page tables are in MMIO. */
356 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
357 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
358 MemTxResult result
= MEMTX_OK
;
361 data
= address_space_ldl_be(as
, ptw
->out_phys
, attrs
, &result
);
363 data
= address_space_ldl_le(as
, ptw
->out_phys
, attrs
, &result
);
365 if (unlikely(result
!= MEMTX_OK
)) {
366 fi
->type
= ARMFault_SyncExternalOnWalk
;
367 fi
->ea
= arm_extabort_type(result
);
374 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
,
377 CPUState
*cs
= env_cpu(env
);
378 void *host
= ptw
->out_host
;
382 /* Page tables are in RAM, and we have the host address. */
383 #ifdef CONFIG_ATOMIC64
384 data
= qatomic_read__nocheck((uint64_t *)host
);
386 data
= be64_to_cpu(data
);
388 data
= le64_to_cpu(data
);
392 data
= ldq_be_p(host
);
394 data
= ldq_le_p(host
);
398 /* Page tables are in MMIO. */
399 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
400 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
401 MemTxResult result
= MEMTX_OK
;
404 data
= address_space_ldq_be(as
, ptw
->out_phys
, attrs
, &result
);
406 data
= address_space_ldq_le(as
, ptw
->out_phys
, attrs
, &result
);
408 if (unlikely(result
!= MEMTX_OK
)) {
409 fi
->type
= ARMFault_SyncExternalOnWalk
;
410 fi
->ea
= arm_extabort_type(result
);
417 static uint64_t arm_casq_ptw(CPUARMState
*env
, uint64_t old_val
,
418 uint64_t new_val
, S1Translate
*ptw
,
422 void *host
= ptw
->out_host
;
424 if (unlikely(!host
)) {
425 fi
->type
= ARMFault_UnsuppAtomicUpdate
;
431 * Raising a stage2 Protection fault for an atomic update to a read-only
432 * page is delayed until it is certain that there is a change to make.
434 if (unlikely(!ptw
->out_rw
)) {
439 flags
= probe_access_flags(env
, ptw
->out_virt
, 0, MMU_DATA_STORE
,
440 arm_to_core_mmu_idx(ptw
->in_ptw_idx
),
444 if (unlikely(flags
& TLB_INVALID_MASK
)) {
445 assert(fi
->type
!= ARMFault_None
);
446 fi
->s2addr
= ptw
->out_virt
;
449 fi
->s1ns
= !ptw
->in_secure
;
453 /* In case CAS mismatches and we loop, remember writability. */
457 #ifdef CONFIG_ATOMIC64
459 old_val
= cpu_to_be64(old_val
);
460 new_val
= cpu_to_be64(new_val
);
461 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
462 cur_val
= be64_to_cpu(cur_val
);
464 old_val
= cpu_to_le64(old_val
);
465 new_val
= cpu_to_le64(new_val
);
466 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
467 cur_val
= le64_to_cpu(cur_val
);
471 * We can't support the full 64-bit atomic cmpxchg on the host.
472 * Because this is only used for FEAT_HAFDBS, which is only for AA64,
473 * we know that TCG_OVERSIZED_GUEST is set, which means that we are
474 * running in round-robin mode and could only race with dma i/o.
476 #ifndef TCG_OVERSIZED_GUEST
477 # error "Unexpected configuration"
479 bool locked
= qemu_mutex_iothread_locked();
481 qemu_mutex_lock_iothread();
484 cur_val
= ldq_be_p(host
);
485 if (cur_val
== old_val
) {
486 stq_be_p(host
, new_val
);
489 cur_val
= ldq_le_p(host
);
490 if (cur_val
== old_val
) {
491 stq_le_p(host
, new_val
);
495 qemu_mutex_unlock_iothread();
502 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
503 uint32_t *table
, uint32_t address
)
505 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
506 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
507 int maskshift
= extract32(tcr
, 0, 3);
508 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
511 if (address
& mask
) {
512 if (tcr
& TTBCR_PD1
) {
513 /* Translation table walk disabled for TTBR1 */
516 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
518 if (tcr
& TTBCR_PD0
) {
519 /* Translation table walk disabled for TTBR0 */
522 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
523 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
525 *table
|= (address
>> 18) & 0x3ffc;
530 * Translate section/page access permissions to page R/W protection flags
532 * @mmu_idx: MMU index indicating required translation regime
533 * @ap: The 3-bit access permissions (AP[2:0])
534 * @domain_prot: The 2-bit domain access permissions
535 * @is_user: TRUE if accessing from PL0
537 static int ap_to_rw_prot_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
538 int ap
, int domain_prot
, bool is_user
)
540 if (domain_prot
== 3) {
541 return PAGE_READ
| PAGE_WRITE
;
546 if (arm_feature(env
, ARM_FEATURE_V7
)) {
549 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
551 return is_user
? 0 : PAGE_READ
;
558 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
563 return PAGE_READ
| PAGE_WRITE
;
566 return PAGE_READ
| PAGE_WRITE
;
567 case 4: /* Reserved. */
570 return is_user
? 0 : PAGE_READ
;
574 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
579 g_assert_not_reached();
584 * Translate section/page access permissions to page R/W protection flags
586 * @mmu_idx: MMU index indicating required translation regime
587 * @ap: The 3-bit access permissions (AP[2:0])
588 * @domain_prot: The 2-bit domain access permissions
590 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
591 int ap
, int domain_prot
)
593 return ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
,
594 regime_is_user(env
, mmu_idx
));
598 * Translate section/page access permissions to page R/W protection flags.
599 * @ap: The 2-bit simple AP (AP[2:1])
600 * @is_user: TRUE if accessing from PL0
602 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
606 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
608 return PAGE_READ
| PAGE_WRITE
;
610 return is_user
? 0 : PAGE_READ
;
614 g_assert_not_reached();
618 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
620 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
623 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
624 uint32_t address
, MMUAccessType access_type
,
625 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
637 /* Pagetable walk. */
638 /* Lookup l1 descriptor. */
639 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
640 /* Section translation fault if page walk is disabled by PD0 or PD1 */
641 fi
->type
= ARMFault_Translation
;
644 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
647 desc
= arm_ldl_ptw(env
, ptw
, fi
);
648 if (fi
->type
!= ARMFault_None
) {
652 domain
= (desc
>> 5) & 0x0f;
653 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
654 dacr
= env
->cp15
.dacr_ns
;
656 dacr
= env
->cp15
.dacr_s
;
658 domain_prot
= (dacr
>> (domain
* 2)) & 3;
660 /* Section translation fault. */
661 fi
->type
= ARMFault_Translation
;
667 if (domain_prot
== 0 || domain_prot
== 2) {
668 fi
->type
= ARMFault_Domain
;
673 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
674 ap
= (desc
>> 10) & 3;
675 result
->f
.lg_page_size
= 20; /* 1MB */
677 /* Lookup l2 entry. */
679 /* Coarse pagetable. */
680 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
682 /* Fine pagetable. */
683 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
685 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
688 desc
= arm_ldl_ptw(env
, ptw
, fi
);
689 if (fi
->type
!= ARMFault_None
) {
693 case 0: /* Page translation fault. */
694 fi
->type
= ARMFault_Translation
;
696 case 1: /* 64k page. */
697 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
698 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
699 result
->f
.lg_page_size
= 16;
701 case 2: /* 4k page. */
702 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
703 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
704 result
->f
.lg_page_size
= 12;
706 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
708 /* ARMv6/XScale extended small page format */
709 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
710 || arm_feature(env
, ARM_FEATURE_V6
)) {
711 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
712 result
->f
.lg_page_size
= 12;
715 * UNPREDICTABLE in ARMv5; we choose to take a
716 * page translation fault.
718 fi
->type
= ARMFault_Translation
;
722 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
723 result
->f
.lg_page_size
= 10;
725 ap
= (desc
>> 4) & 3;
728 /* Never happens, but compiler isn't smart enough to tell. */
729 g_assert_not_reached();
732 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
733 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
734 if (!(result
->f
.prot
& (1 << access_type
))) {
735 /* Access permission fault. */
736 fi
->type
= ARMFault_Permission
;
739 result
->f
.phys_addr
= phys_addr
;
747 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
748 uint32_t address
, MMUAccessType access_type
,
749 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
751 ARMCPU
*cpu
= env_archcpu(env
);
752 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
767 /* Pagetable walk. */
768 /* Lookup l1 descriptor. */
769 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
770 /* Section translation fault if page walk is disabled by PD0 or PD1 */
771 fi
->type
= ARMFault_Translation
;
774 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
777 desc
= arm_ldl_ptw(env
, ptw
, fi
);
778 if (fi
->type
!= ARMFault_None
) {
782 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
783 /* Section translation fault, or attempt to use the encoding
784 * which is Reserved on implementations without PXN.
786 fi
->type
= ARMFault_Translation
;
789 if ((type
== 1) || !(desc
& (1 << 18))) {
790 /* Page or Section. */
791 domain
= (desc
>> 5) & 0x0f;
793 if (regime_el(env
, mmu_idx
) == 1) {
794 dacr
= env
->cp15
.dacr_ns
;
796 dacr
= env
->cp15
.dacr_s
;
801 domain_prot
= (dacr
>> (domain
* 2)) & 3;
802 if (domain_prot
== 0 || domain_prot
== 2) {
803 /* Section or Page domain fault */
804 fi
->type
= ARMFault_Domain
;
808 if (desc
& (1 << 18)) {
810 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
811 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
812 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
813 result
->f
.lg_page_size
= 24; /* 16MB */
816 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
817 result
->f
.lg_page_size
= 20; /* 1MB */
819 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
820 xn
= desc
& (1 << 4);
822 ns
= extract32(desc
, 19, 1);
824 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
825 pxn
= (desc
>> 2) & 1;
827 ns
= extract32(desc
, 3, 1);
828 /* Lookup l2 entry. */
829 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
830 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
833 desc
= arm_ldl_ptw(env
, ptw
, fi
);
834 if (fi
->type
!= ARMFault_None
) {
837 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
839 case 0: /* Page translation fault. */
840 fi
->type
= ARMFault_Translation
;
842 case 1: /* 64k page. */
843 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
844 xn
= desc
& (1 << 15);
845 result
->f
.lg_page_size
= 16;
847 case 2: case 3: /* 4k page. */
848 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
850 result
->f
.lg_page_size
= 12;
853 /* Never happens, but compiler isn't smart enough to tell. */
854 g_assert_not_reached();
857 if (domain_prot
== 3) {
858 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
860 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
863 if (xn
&& access_type
== MMU_INST_FETCH
) {
864 fi
->type
= ARMFault_Permission
;
868 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
869 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
870 /* The simplified model uses AP[0] as an access control bit. */
872 /* Access flag fault. */
873 fi
->type
= ARMFault_AccessFlag
;
876 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
877 user_prot
= simple_ap_to_rw_prot_is_user(ap
>> 1, 1);
879 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
880 user_prot
= ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
, 1);
882 if (result
->f
.prot
&& !xn
) {
883 result
->f
.prot
|= PAGE_EXEC
;
885 if (!(result
->f
.prot
& (1 << access_type
))) {
886 /* Access permission fault. */
887 fi
->type
= ARMFault_Permission
;
890 if (regime_is_pan(env
, mmu_idx
) &&
891 !regime_is_user(env
, mmu_idx
) &&
893 access_type
!= MMU_INST_FETCH
) {
894 /* Privileged Access Never fault */
895 fi
->type
= ARMFault_Permission
;
900 /* The NS bit will (as required by the architecture) have no effect if
901 * the CPU doesn't support TZ or this is a non-secure translation
902 * regime, because the attribute will already be non-secure.
904 result
->f
.attrs
.secure
= false;
906 result
->f
.phys_addr
= phys_addr
;
915 * Translate S2 section/page access permissions to protection flags
917 * @s2ap: The 2-bit stage2 access permissions (S2AP)
918 * @xn: XN (execute-never) bits
919 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
921 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
932 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
950 g_assert_not_reached();
953 if (!extract32(xn
, 1, 1)) {
954 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
963 * Translate section/page access permissions to protection flags
965 * @mmu_idx: MMU index indicating required translation regime
966 * @is_aa64: TRUE if AArch64
967 * @ap: The 2-bit simple AP (AP[2:1])
968 * @ns: NS (non-secure) bit
969 * @xn: XN (execute-never) bit
970 * @pxn: PXN (privileged execute-never) bit
972 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
973 int ap
, int ns
, int xn
, int pxn
)
975 ARMCPU
*cpu
= env_archcpu(env
);
976 bool is_user
= regime_is_user(env
, mmu_idx
);
977 int prot_rw
, user_rw
;
981 assert(!regime_is_stage2(mmu_idx
));
983 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
988 * PAN controls can forbid data accesses but don't affect insn fetch.
989 * Plain PAN forbids data accesses if EL0 has data permissions;
990 * PAN3 forbids data accesses if EL0 has either data or exec perms.
991 * Note that for AArch64 the 'user can exec' case is exactly !xn.
992 * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0
993 * do not affect EPAN.
995 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
997 } else if (cpu_isar_feature(aa64_pan3
, cpu
) && is_aa64
&&
998 regime_is_pan(env
, mmu_idx
) &&
999 (regime_sctlr(env
, mmu_idx
) & SCTLR_EPAN
) && !xn
) {
1002 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
1006 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
1010 /* TODO have_wxn should be replaced with
1011 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
1012 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
1013 * compatible processors have EL2, which is required for [U]WXN.
1015 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
1018 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
1022 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
1023 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
1025 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1026 switch (regime_el(env
, mmu_idx
)) {
1030 xn
= xn
|| !(user_rw
& PAGE_READ
);
1034 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
1036 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
1037 (uwxn
&& (user_rw
& PAGE_WRITE
));
1047 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
1050 return prot_rw
| PAGE_EXEC
;
1053 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
1056 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1057 uint32_t el
= regime_el(env
, mmu_idx
);
1061 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
1063 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1065 bool sext
= extract32(tcr
, 4, 1);
1066 bool sign
= extract32(tcr
, 3, 1);
1069 * If the sign-extend bit is not the same as t0sz[3], the result
1070 * is unpredictable. Flag this as a guest error.
1073 qemu_log_mask(LOG_GUEST_ERROR
,
1074 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
1076 tsz
= sextract32(tcr
, 0, 4) + 8;
1080 } else if (el
== 2) {
1082 tsz
= extract32(tcr
, 0, 3);
1084 hpd
= extract64(tcr
, 24, 1);
1087 int t0sz
= extract32(tcr
, 0, 3);
1088 int t1sz
= extract32(tcr
, 16, 3);
1091 select
= va
> (0xffffffffu
>> t0sz
);
1093 /* Note that we will detect errors later. */
1094 select
= va
>= ~(0xffffffffu
>> t1sz
);
1098 epd
= extract32(tcr
, 7, 1);
1099 hpd
= extract64(tcr
, 41, 1);
1102 epd
= extract32(tcr
, 23, 1);
1103 hpd
= extract64(tcr
, 42, 1);
1105 /* For aarch32, hpd0 is not enabled without t2e as well. */
1106 hpd
&= extract32(tcr
, 6, 1);
1109 return (ARMVAParameters
) {
1118 * check_s2_mmu_setup
1120 * @is_aa64: True if the translation regime is in AArch64 state
1121 * @tcr: VTCR_EL2 or VSTCR_EL2
1122 * @ds: Effective value of TCR.DS.
1123 * @iasize: Bitsize of IPAs
1124 * @stride: Page-table stride (See the ARM ARM)
1126 * Decode the starting level of the S2 lookup, returning INT_MIN if
1127 * the configuration is invalid.
1129 static int check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, uint64_t tcr
,
1130 bool ds
, int iasize
, int stride
)
1132 int sl0
, sl2
, startlevel
, granulebits
, levels
;
1133 int s1_min_iasize
, s1_max_iasize
;
1135 sl0
= extract32(tcr
, 6, 2);
1138 * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
1139 * so interleave AArch64.S2StartLevel.
1143 /* SL2 is RES0 unless DS=1 & 4KB granule. */
1144 sl2
= extract64(tcr
, 33, 1);
1151 startlevel
= 2 - sl0
;
1154 if (arm_pamax(cpu
) < 44) {
1159 if (!cpu_isar_feature(aa64_st
, cpu
)) {
1170 if (arm_pamax(cpu
) < 42) {
1180 startlevel
= 3 - sl0
;
1185 if (arm_pamax(cpu
) < 44) {
1192 startlevel
= 3 - sl0
;
1195 g_assert_not_reached();
1199 * Things are simpler for AArch32 EL2, with only 4k pages.
1200 * There is no separate S2InvalidSL function, but AArch32.S2Walk
1201 * begins with walkparms.sl0 in {'1x'}.
1203 assert(stride
== 9);
1207 startlevel
= 2 - sl0
;
1210 /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
1211 levels
= 3 - startlevel
;
1212 granulebits
= stride
+ 3;
1214 s1_min_iasize
= levels
* stride
+ granulebits
+ 1;
1215 s1_max_iasize
= s1_min_iasize
+ (stride
- 1) + 4;
1217 if (iasize
>= s1_min_iasize
&& iasize
<= s1_max_iasize
) {
1226 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
1228 * Returns false if the translation was successful. Otherwise, phys_ptr,
1229 * attrs, prot and page_size may not be filled in, and the populated fsr
1230 * value provides information on why the translation aborted, in the format
1231 * of a long-format DFSR/IFSR fault register, with the following caveat:
1232 * the WnR bit is never set (the caller must do this).
1235 * @ptw: Current and next stage parameters for the walk.
1236 * @address: virtual address to get physical address for
1237 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
1238 * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
1239 * (so this is a stage 2 page table walk),
1240 * must be true if this is stage 2 of a stage 1+2
1241 * walk for an EL0 access. If @mmu_idx is anything else,
1242 * @s1_is_el0 is ignored.
1243 * @result: set on translation success,
1244 * @fi: set to fault info if the translation fails
1246 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
1248 MMUAccessType access_type
, bool s1_is_el0
,
1249 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1251 ARMCPU
*cpu
= env_archcpu(env
);
1252 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1253 bool is_secure
= ptw
->in_secure
;
1255 ARMVAParameters param
;
1257 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1258 uint32_t tableattrs
;
1259 target_ulong page_size
;
1262 int addrsize
, inputsize
, outputsize
;
1263 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1264 int ap
, ns
, xn
, pxn
;
1265 uint32_t el
= regime_el(env
, mmu_idx
);
1266 uint64_t descaddrmask
;
1267 bool aarch64
= arm_el_is_aa64(env
, el
);
1268 uint64_t descriptor
, new_descriptor
;
1271 /* TODO: This code does not support shareability levels. */
1275 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1276 access_type
!= MMU_INST_FETCH
,
1277 !arm_el_is_aa64(env
, 1));
1281 * If TxSZ is programmed to a value larger than the maximum,
1282 * or smaller than the effective minimum, it is IMPLEMENTATION
1283 * DEFINED whether we behave as if the field were programmed
1284 * within bounds, or if a level 0 Translation fault is generated.
1286 * With FEAT_LVA, fault on less than minimum becomes required,
1287 * so our choice is to always raise the fault.
1289 if (param
.tsz_oob
) {
1290 goto do_translation_fault
;
1293 addrsize
= 64 - 8 * param
.tbi
;
1294 inputsize
= 64 - param
.tsz
;
1297 * Bound PS by PARANGE to find the effective output address size.
1298 * ID_AA64MMFR0 is a read-only register so values outside of the
1299 * supported mappings can be considered an implementation error.
1301 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1302 ps
= MIN(ps
, param
.ps
);
1303 assert(ps
< ARRAY_SIZE(pamax_map
));
1304 outputsize
= pamax_map
[ps
];
1307 * With LPA2, the effective output address (OA) size is at most 48 bits
1308 * unless TCR.DS == 1
1310 if (!param
.ds
&& param
.gran
!= Gran64K
) {
1311 outputsize
= MIN(outputsize
, 48);
1314 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1316 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1317 inputsize
= addrsize
- param
.tsz
;
1322 * We determined the region when collecting the parameters, but we
1323 * have not yet validated that the address is valid for the region.
1324 * Extract the top bits and verify that they all match select.
1326 * For aa32, if inputsize == addrsize, then we have selected the
1327 * region by exclusion in aa32_va_parameters and there is no more
1328 * validation to do here.
1330 if (inputsize
< addrsize
) {
1331 target_ulong top_bits
= sextract64(address
, inputsize
,
1332 addrsize
- inputsize
);
1333 if (-top_bits
!= param
.select
) {
1334 /* The gap between the two regions is a Translation fault */
1335 goto do_translation_fault
;
1339 stride
= arm_granule_bits(param
.gran
) - 3;
1342 * Note that QEMU ignores shareability and cacheability attributes,
1343 * so we don't need to do anything with the SH, ORGN, IRGN fields
1344 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1345 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1346 * implement any ASID-like capability so we can ignore it (instead
1347 * we will always flush the TLB any time the ASID is changed).
1349 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1352 * Here we should have set up all the parameters for the translation:
1353 * inputsize, ttbr, epd, stride, tbi
1358 * Translation table walk disabled => Translation fault on TLB miss
1359 * Note: This is always 0 on 64-bit EL2 and EL3.
1361 goto do_translation_fault
;
1364 if (!regime_is_stage2(mmu_idx
)) {
1366 * The starting level depends on the virtual address size (which can
1367 * be up to 48 bits) and the translation granule size. It indicates
1368 * the number of strides (stride bits at a time) needed to
1369 * consume the bits of the input address. In the pseudocode this is:
1370 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1371 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1372 * our 'stride + 3' and 'stride' is our 'stride'.
1373 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1374 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1375 * = 4 - (inputsize - 4) / stride;
1377 level
= 4 - (inputsize
- 4) / stride
;
1379 int startlevel
= check_s2_mmu_setup(cpu
, aarch64
, tcr
, param
.ds
,
1381 if (startlevel
== INT_MIN
) {
1383 goto do_translation_fault
;
1388 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1389 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1391 /* Now we can extract the actual base address from the TTBR */
1392 descaddr
= extract64(ttbr
, 0, 48);
1395 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1397 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1398 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1399 * but we've just cleared the bits above 47, so simplify the test.
1401 if (outputsize
> 48) {
1402 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1403 } else if (descaddr
>> outputsize
) {
1405 fi
->type
= ARMFault_AddressSize
;
1410 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1411 * and also to mask out CnP (bit 0) which could validly be non-zero.
1413 descaddr
&= ~indexmask
;
1416 * For AArch32, the address field in the descriptor goes up to bit 39
1417 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1418 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1419 * bits as part of the address, which will be checked via outputsize.
1420 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1421 * the highest bits of a 52-bit output are placed elsewhere.
1424 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1425 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1426 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1428 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1430 descaddrmask
&= ~indexmask_grainsize
;
1433 * Secure stage 1 accesses start with the page table in secure memory and
1434 * can be downgraded to non-secure at any step. Non-secure accesses
1435 * remain non-secure. We implement this by just ORing in the NSTable/NS
1436 * bits at each step.
1437 * Stage 2 never gets this kind of downgrade.
1439 tableattrs
= is_secure
? 0 : (1 << 4);
1442 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1444 nstable
= !regime_is_stage2(mmu_idx
) && extract32(tableattrs
, 4, 1);
1447 * Stage2_S -> Stage2 or Phys_S -> Phys_NS
1448 * Assert that the non-secure idx are even, and relative order.
1450 QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS
& 1) != 0);
1451 QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2
& 1) != 0);
1452 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS
+ 1 != ARMMMUIdx_Phys_S
);
1453 QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2
+ 1 != ARMMMUIdx_Stage2_S
);
1454 ptw
->in_ptw_idx
&= ~1;
1455 ptw
->in_secure
= false;
1457 if (!S1_ptw_translate(env
, ptw
, descaddr
, fi
)) {
1460 descriptor
= arm_ldq_ptw(env
, ptw
, fi
);
1461 if (fi
->type
!= ARMFault_None
) {
1464 new_descriptor
= descriptor
;
1466 restart_atomic_update
:
1467 if (!(descriptor
& 1) || (!(descriptor
& 2) && (level
== 3))) {
1468 /* Invalid, or the Reserved level 3 encoding */
1469 goto do_translation_fault
;
1472 descaddr
= descriptor
& descaddrmask
;
1475 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1476 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1477 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1478 * raise AddressSizeFault.
1480 if (outputsize
> 48) {
1482 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1484 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1486 } else if (descaddr
>> outputsize
) {
1487 fi
->type
= ARMFault_AddressSize
;
1491 if ((descriptor
& 2) && (level
< 3)) {
1493 * Table entry. The top five bits are attributes which may
1494 * propagate down through lower levels of the table (and
1495 * which are all arranged so that 0 means "no effect", so
1496 * we can gather them up by ORing in the bits at each level).
1498 tableattrs
|= extract64(descriptor
, 59, 5);
1500 indexmask
= indexmask_grainsize
;
1505 * Block entry at level 1 or 2, or page entry at level 3.
1506 * These are basically the same thing, although the number
1507 * of bits we pull in from the vaddr varies. Note that although
1508 * descaddrmask masks enough of the low bits of the descriptor
1509 * to give a correct page or table address, the address field
1510 * in a block descriptor is smaller; so we need to explicitly
1511 * clear the lower bits here before ORing in the low vaddr bits.
1513 * Afterward, descaddr is the final physical address.
1515 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1516 descaddr
&= ~(hwaddr
)(page_size
- 1);
1517 descaddr
|= (address
& (page_size
- 1));
1519 if (likely(!ptw
->in_debug
)) {
1522 * If HA is enabled, prepare to update the descriptor below.
1523 * Otherwise, pass the access fault on to software.
1525 if (!(descriptor
& (1 << 10))) {
1527 new_descriptor
|= 1 << 10; /* AF */
1529 fi
->type
= ARMFault_AccessFlag
;
1536 * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
1537 * bit for writeback. The actual write protection test may still be
1538 * overridden by tableattrs, to be merged below.
1541 && extract64(descriptor
, 51, 1) /* DBM */
1542 && access_type
== MMU_DATA_STORE
) {
1543 if (regime_is_stage2(mmu_idx
)) {
1544 new_descriptor
|= 1ull << 7; /* set S2AP[1] */
1546 new_descriptor
&= ~(1ull << 7); /* clear AP[2] */
1552 * Extract attributes from the (modified) descriptor, and apply
1553 * table descriptors. Stage 2 table descriptors do not include
1554 * any attribute fields. HPD disables all the table attributes
1557 attrs
= new_descriptor
& (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
1558 if (!regime_is_stage2(mmu_idx
)) {
1559 attrs
|= nstable
<< 5; /* NS */
1561 attrs
|= extract64(tableattrs
, 0, 2) << 53; /* XN, PXN */
1563 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1564 * means "force PL1 access only", which means forcing AP[1] to 0.
1566 attrs
&= ~(extract64(tableattrs
, 2, 1) << 6); /* !APT[0] => AP[1] */
1567 attrs
|= extract32(tableattrs
, 3, 1) << 7; /* APT[1] => AP[2] */
1571 ap
= extract32(attrs
, 6, 2);
1572 if (regime_is_stage2(mmu_idx
)) {
1573 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1574 xn
= extract64(attrs
, 53, 2);
1575 result
->f
.prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
1577 ns
= extract32(attrs
, 5, 1);
1578 xn
= extract64(attrs
, 54, 1);
1579 pxn
= extract64(attrs
, 53, 1);
1580 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
1583 if (!(result
->f
.prot
& (1 << access_type
))) {
1584 fi
->type
= ARMFault_Permission
;
1588 /* If FEAT_HAFDBS has made changes, update the PTE. */
1589 if (new_descriptor
!= descriptor
) {
1590 new_descriptor
= arm_casq_ptw(env
, descriptor
, new_descriptor
, ptw
, fi
);
1591 if (fi
->type
!= ARMFault_None
) {
1595 * I_YZSVV says that if the in-memory descriptor has changed,
1596 * then we must use the information in that new value
1597 * (which might include a different output address, different
1598 * attributes, or generate a fault).
1599 * Restart the handling of the descriptor value from scratch.
1601 if (new_descriptor
!= descriptor
) {
1602 descriptor
= new_descriptor
;
1603 goto restart_atomic_update
;
1609 * The NS bit will (as required by the architecture) have no effect if
1610 * the CPU doesn't support TZ or this is a non-secure translation
1611 * regime, because the attribute will already be non-secure.
1613 result
->f
.attrs
.secure
= false;
1616 if (regime_is_stage2(mmu_idx
)) {
1617 result
->cacheattrs
.is_s2_format
= true;
1618 result
->cacheattrs
.attrs
= extract32(attrs
, 2, 4);
1620 /* Index into MAIR registers for cache attributes */
1621 uint8_t attrindx
= extract32(attrs
, 2, 3);
1622 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
1623 assert(attrindx
<= 7);
1624 result
->cacheattrs
.is_s2_format
= false;
1625 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
1627 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
1628 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
1629 result
->f
.guarded
= extract64(attrs
, 50, 1); /* GP */
1634 * For FEAT_LPA2 and effective DS, the SH field in the attributes
1635 * was re-purposed for output address bits. The SH attribute in
1636 * that case comes from TCR_ELx, which we extracted earlier.
1639 result
->cacheattrs
.shareability
= param
.sh
;
1641 result
->cacheattrs
.shareability
= extract32(attrs
, 8, 2);
1644 result
->f
.phys_addr
= descaddr
;
1645 result
->f
.lg_page_size
= ctz64(page_size
);
1648 do_translation_fault
:
1649 fi
->type
= ARMFault_Translation
;
1652 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
1653 fi
->stage2
= fi
->s1ptw
|| regime_is_stage2(mmu_idx
);
1654 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1658 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
1659 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1660 bool is_secure
, GetPhysAddrResult
*result
,
1661 ARMMMUFaultInfo
*fi
)
1666 bool is_user
= regime_is_user(env
, mmu_idx
);
1668 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
1670 result
->f
.phys_addr
= address
;
1671 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1675 result
->f
.phys_addr
= address
;
1676 for (n
= 7; n
>= 0; n
--) {
1677 base
= env
->cp15
.c6_region
[n
];
1678 if ((base
& 1) == 0) {
1681 mask
= 1 << ((base
>> 1) & 0x1f);
1682 /* Keep this shift separate from the above to avoid an
1683 (undefined) << 32. */
1684 mask
= (mask
<< 1) - 1;
1685 if (((base
^ address
) & ~mask
) == 0) {
1690 fi
->type
= ARMFault_Background
;
1694 if (access_type
== MMU_INST_FETCH
) {
1695 mask
= env
->cp15
.pmsav5_insn_ap
;
1697 mask
= env
->cp15
.pmsav5_data_ap
;
1699 mask
= (mask
>> (n
* 4)) & 0xf;
1702 fi
->type
= ARMFault_Permission
;
1707 fi
->type
= ARMFault_Permission
;
1711 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1714 result
->f
.prot
= PAGE_READ
;
1716 result
->f
.prot
|= PAGE_WRITE
;
1720 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1724 fi
->type
= ARMFault_Permission
;
1728 result
->f
.prot
= PAGE_READ
;
1731 result
->f
.prot
= PAGE_READ
;
1734 /* Bad permission. */
1735 fi
->type
= ARMFault_Permission
;
1739 result
->f
.prot
|= PAGE_EXEC
;
1743 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1744 int32_t address
, uint8_t *prot
)
1746 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1747 *prot
= PAGE_READ
| PAGE_WRITE
;
1749 case 0xF0000000 ... 0xFFFFFFFF:
1750 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
1751 /* hivecs execing is ok */
1755 case 0x00000000 ... 0x7FFFFFFF:
1760 /* Default system address map for M profile cores.
1761 * The architecture specifies which regions are execute-never;
1762 * at the MPU level no other checks are defined.
1765 case 0x00000000 ... 0x1fffffff: /* ROM */
1766 case 0x20000000 ... 0x3fffffff: /* SRAM */
1767 case 0x60000000 ... 0x7fffffff: /* RAM */
1768 case 0x80000000 ... 0x9fffffff: /* RAM */
1769 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1771 case 0x40000000 ... 0x5fffffff: /* Peripheral */
1772 case 0xa0000000 ... 0xbfffffff: /* Device */
1773 case 0xc0000000 ... 0xdfffffff: /* Device */
1774 case 0xe0000000 ... 0xffffffff: /* System */
1775 *prot
= PAGE_READ
| PAGE_WRITE
;
1778 g_assert_not_reached();
1783 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
1785 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
1786 return arm_feature(env
, ARM_FEATURE_M
) &&
1787 extract32(address
, 20, 12) == 0xe00;
1790 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
1793 * True if address is in the M profile system region
1794 * 0xe0000000 - 0xffffffff
1796 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
1799 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1800 bool is_secure
, bool is_user
)
1803 * Return true if we should use the default memory map as a
1804 * "background" region if there are no hits against any MPU regions.
1806 CPUARMState
*env
= &cpu
->env
;
1812 if (arm_feature(env
, ARM_FEATURE_M
)) {
1813 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
1816 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1820 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
1823 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
1824 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1825 bool secure
, GetPhysAddrResult
*result
,
1826 ARMMMUFaultInfo
*fi
)
1828 ARMCPU
*cpu
= env_archcpu(env
);
1830 bool is_user
= regime_is_user(env
, mmu_idx
);
1832 result
->f
.phys_addr
= address
;
1833 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1836 if (regime_translation_disabled(env
, mmu_idx
, secure
) ||
1837 m_is_ppb_region(env
, address
)) {
1839 * MPU disabled or M profile PPB access: use default memory map.
1840 * The other case which uses the default memory map in the
1841 * v7M ARM ARM pseudocode is exception vector reads from the vector
1842 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
1843 * which always does a direct read using address_space_ldl(), rather
1844 * than going via this function, so we don't need to check that here.
1846 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1847 } else { /* MPU enabled */
1848 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1850 uint32_t base
= env
->pmsav7
.drbar
[n
];
1851 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
1855 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
1860 qemu_log_mask(LOG_GUEST_ERROR
,
1861 "DRSR[%d]: Rsize field cannot be 0\n", n
);
1865 rmask
= (1ull << rsize
) - 1;
1868 qemu_log_mask(LOG_GUEST_ERROR
,
1869 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
1870 "to DRSR region size, mask = 0x%" PRIx32
"\n",
1875 if (address
< base
|| address
> base
+ rmask
) {
1877 * Address not in this region. We must check whether the
1878 * region covers addresses in the same page as our address.
1879 * In that case we must not report a size that covers the
1880 * whole page for a subsequent hit against a different MPU
1881 * region or the background region, because it would result in
1882 * incorrect TLB hits for subsequent accesses to addresses that
1883 * are in this MPU region.
1885 if (ranges_overlap(base
, rmask
,
1886 address
& TARGET_PAGE_MASK
,
1887 TARGET_PAGE_SIZE
)) {
1888 result
->f
.lg_page_size
= 0;
1893 /* Region matched */
1895 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
1897 uint32_t srdis_mask
;
1899 rsize
-= 3; /* sub region size (power of 2) */
1900 snd
= ((address
- base
) >> rsize
) & 0x7;
1901 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
1903 srdis_mask
= srdis
? 0x3 : 0x0;
1904 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
1906 * This will check in groups of 2, 4 and then 8, whether
1907 * the subregion bits are consistent. rsize is incremented
1908 * back up to give the region size, considering consistent
1909 * adjacent subregions as one region. Stop testing if rsize
1910 * is already big enough for an entire QEMU page.
1912 int snd_rounded
= snd
& ~(i
- 1);
1913 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
1914 snd_rounded
+ 8, i
);
1915 if (srdis_mask
^ srdis_multi
) {
1918 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
1925 if (rsize
< TARGET_PAGE_BITS
) {
1926 result
->f
.lg_page_size
= rsize
;
1931 if (n
== -1) { /* no hits */
1932 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1933 /* background fault */
1934 fi
->type
= ARMFault_Background
;
1937 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
1939 } else { /* a MPU hit! */
1940 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
1941 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
1943 if (m_is_system_region(env
, address
)) {
1944 /* System space is always execute never */
1948 if (is_user
) { /* User mode AP bit decoding */
1953 break; /* no access */
1955 result
->f
.prot
|= PAGE_WRITE
;
1959 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1962 /* for v7M, same as 6; for R profile a reserved value */
1963 if (arm_feature(env
, ARM_FEATURE_M
)) {
1964 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1969 qemu_log_mask(LOG_GUEST_ERROR
,
1970 "DRACR[%d]: Bad value for AP bits: 0x%"
1971 PRIx32
"\n", n
, ap
);
1973 } else { /* Priv. mode AP bits decoding */
1976 break; /* no access */
1980 result
->f
.prot
|= PAGE_WRITE
;
1984 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1987 /* for v7M, same as 6; for R profile a reserved value */
1988 if (arm_feature(env
, ARM_FEATURE_M
)) {
1989 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1994 qemu_log_mask(LOG_GUEST_ERROR
,
1995 "DRACR[%d]: Bad value for AP bits: 0x%"
1996 PRIx32
"\n", n
, ap
);
2002 result
->f
.prot
&= ~PAGE_EXEC
;
2007 fi
->type
= ARMFault_Permission
;
2009 return !(result
->f
.prot
& (1 << access_type
));
2012 static uint32_t *regime_rbar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2015 if (regime_el(env
, mmu_idx
) == 2) {
2016 return env
->pmsav8
.hprbar
;
2018 return env
->pmsav8
.rbar
[secure
];
2022 static uint32_t *regime_rlar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
2025 if (regime_el(env
, mmu_idx
) == 2) {
2026 return env
->pmsav8
.hprlar
;
2028 return env
->pmsav8
.rlar
[secure
];
2032 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
2033 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2034 bool secure
, GetPhysAddrResult
*result
,
2035 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
2038 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
2039 * that a full phys-to-virt translation does).
2040 * mregion is (if not NULL) set to the region number which matched,
2041 * or -1 if no region number is returned (MPU off, address did not
2042 * hit a region, address hit in multiple regions).
2043 * If the region hit doesn't cover the entire TARGET_PAGE the address
2044 * is within, then we set the result page_size to 1 to force the
2045 * memory system to use a subpage.
2047 ARMCPU
*cpu
= env_archcpu(env
);
2048 bool is_user
= regime_is_user(env
, mmu_idx
);
2050 int matchregion
= -1;
2052 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2053 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2056 if (regime_el(env
, mmu_idx
) == 2) {
2057 region_counter
= cpu
->pmsav8r_hdregion
;
2059 region_counter
= cpu
->pmsav7_dregion
;
2062 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2063 result
->f
.phys_addr
= address
;
2069 if (mmu_idx
== ARMMMUIdx_Stage2
) {
2074 * Unlike the ARM ARM pseudocode, we don't need to check whether this
2075 * was an exception vector read from the vector table (which is always
2076 * done using the default system address map), because those accesses
2077 * are done in arm_v7m_load_vector(), which always does a direct
2078 * read using address_space_ldl(), rather than going via this function.
2080 if (regime_translation_disabled(env
, mmu_idx
, secure
)) { /* MPU disabled */
2082 } else if (m_is_ppb_region(env
, address
)) {
2085 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
2090 if (arm_feature(env
, ARM_FEATURE_M
)) {
2097 for (n
= region_counter
- 1; n
>= 0; n
--) {
2100 * Note that the base address is bits [31:x] from the register
2101 * with bits [x-1:0] all zeroes, but the limit address is bits
2102 * [31:x] from the register with bits [x:0] all ones. Where x is
2103 * 5 for Cortex-M and 6 for Cortex-R
2105 uint32_t base
= regime_rbar(env
, mmu_idx
, secure
)[n
] & ~bitmask
;
2106 uint32_t limit
= regime_rlar(env
, mmu_idx
, secure
)[n
] | bitmask
;
2108 if (!(regime_rlar(env
, mmu_idx
, secure
)[n
] & 0x1)) {
2109 /* Region disabled */
2113 if (address
< base
|| address
> limit
) {
2115 * Address not in this region. We must check whether the
2116 * region covers addresses in the same page as our address.
2117 * In that case we must not report a size that covers the
2118 * whole page for a subsequent hit against a different MPU
2119 * region or the background region, because it would result in
2120 * incorrect TLB hits for subsequent accesses to addresses that
2121 * are in this MPU region.
2123 if (limit
>= base
&&
2124 ranges_overlap(base
, limit
- base
+ 1,
2126 TARGET_PAGE_SIZE
)) {
2127 result
->f
.lg_page_size
= 0;
2132 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2133 result
->f
.lg_page_size
= 0;
2136 if (matchregion
!= -1) {
2138 * Multiple regions match -- always a failure (unlike
2139 * PMSAv7 where highest-numbered-region wins)
2141 fi
->type
= ARMFault_Permission
;
2142 if (arm_feature(env
, ARM_FEATURE_M
)) {
2154 if (arm_feature(env
, ARM_FEATURE_M
)) {
2155 fi
->type
= ARMFault_Background
;
2157 fi
->type
= ARMFault_Permission
;
2162 if (matchregion
== -1) {
2163 /* hit using the background region */
2164 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2166 uint32_t matched_rbar
= regime_rbar(env
, mmu_idx
, secure
)[matchregion
];
2167 uint32_t matched_rlar
= regime_rlar(env
, mmu_idx
, secure
)[matchregion
];
2168 uint32_t ap
= extract32(matched_rbar
, 1, 2);
2169 uint32_t xn
= extract32(matched_rbar
, 0, 1);
2172 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
2173 pxn
= extract32(matched_rlar
, 4, 1);
2176 if (m_is_system_region(env
, address
)) {
2177 /* System space is always execute never */
2181 if (regime_el(env
, mmu_idx
) == 2) {
2182 result
->f
.prot
= simple_ap_to_rw_prot_is_user(ap
,
2183 mmu_idx
!= ARMMMUIdx_E2
);
2185 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
2188 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2189 uint8_t attrindx
= extract32(matched_rlar
, 1, 3);
2190 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
2191 uint8_t sh
= extract32(matched_rlar
, 3, 2);
2193 if (regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
&&
2194 result
->f
.prot
& PAGE_WRITE
&& mmu_idx
!= ARMMMUIdx_Stage2
) {
2198 if ((regime_el(env
, mmu_idx
) == 1) &&
2199 regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
&& ap
== 0x1) {
2203 result
->cacheattrs
.is_s2_format
= false;
2204 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
2205 result
->cacheattrs
.shareability
= sh
;
2208 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
2209 result
->f
.prot
|= PAGE_EXEC
;
2213 *mregion
= matchregion
;
2217 fi
->type
= ARMFault_Permission
;
2218 if (arm_feature(env
, ARM_FEATURE_M
)) {
2221 return !(result
->f
.prot
& (1 << access_type
));
2224 static bool v8m_is_sau_exempt(CPUARMState
*env
,
2225 uint32_t address
, MMUAccessType access_type
)
2228 * The architecture specifies that certain address ranges are
2229 * exempt from v8M SAU/IDAU checks.
2232 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
2233 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
2234 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
2235 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
2236 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
2237 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
2240 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
2241 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2242 bool is_secure
, V8M_SAttributes
*sattrs
)
2245 * Look up the security attributes for this address. Compare the
2246 * pseudocode SecurityCheck() function.
2247 * We assume the caller has zero-initialized *sattrs.
2249 ARMCPU
*cpu
= env_archcpu(env
);
2251 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
2252 int idau_region
= IREGION_NOTVALID
;
2253 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2254 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2257 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
2258 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
2260 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
2264 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
2265 /* 0xf0000000..0xffffffff is always S for insn fetches */
2269 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
2270 sattrs
->ns
= !is_secure
;
2274 if (idau_region
!= IREGION_NOTVALID
) {
2275 sattrs
->irvalid
= true;
2276 sattrs
->iregion
= idau_region
;
2279 switch (env
->sau
.ctrl
& 3) {
2280 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
2282 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
2285 default: /* SAU.ENABLE == 1 */
2286 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
2287 if (env
->sau
.rlar
[r
] & 1) {
2288 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
2289 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
2291 if (base
<= address
&& limit
>= address
) {
2292 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2293 sattrs
->subpage
= true;
2295 if (sattrs
->srvalid
) {
2297 * If we hit in more than one region then we must report
2298 * as Secure, not NS-Callable, with no valid region
2302 sattrs
->nsc
= false;
2303 sattrs
->sregion
= 0;
2304 sattrs
->srvalid
= false;
2307 if (env
->sau
.rlar
[r
] & 2) {
2312 sattrs
->srvalid
= true;
2313 sattrs
->sregion
= r
;
2317 * Address not in this region. We must check whether the
2318 * region covers addresses in the same page as our address.
2319 * In that case we must not report a size that covers the
2320 * whole page for a subsequent hit against a different MPU
2321 * region or the background region, because it would result
2322 * in incorrect TLB hits for subsequent accesses to
2323 * addresses that are in this MPU region.
2325 if (limit
>= base
&&
2326 ranges_overlap(base
, limit
- base
+ 1,
2328 TARGET_PAGE_SIZE
)) {
2329 sattrs
->subpage
= true;
2338 * The IDAU will override the SAU lookup results if it specifies
2339 * higher security than the SAU does.
2342 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
2344 sattrs
->nsc
= idau_nsc
;
2349 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
2350 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2351 bool secure
, GetPhysAddrResult
*result
,
2352 ARMMMUFaultInfo
*fi
)
2354 V8M_SAttributes sattrs
= {};
2357 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2358 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2360 if (access_type
== MMU_INST_FETCH
) {
2362 * Instruction fetches always use the MMU bank and the
2363 * transaction attribute determined by the fetch address,
2364 * regardless of CPU state. This is painful for QEMU
2365 * to handle, because it would mean we need to encode
2366 * into the mmu_idx not just the (user, negpri) information
2367 * for the current security state but also that for the
2368 * other security state, which would balloon the number
2369 * of mmu_idx values needed alarmingly.
2370 * Fortunately we can avoid this because it's not actually
2371 * possible to arbitrarily execute code from memory with
2372 * the wrong security attribute: it will always generate
2373 * an exception of some kind or another, apart from the
2374 * special case of an NS CPU executing an SG instruction
2375 * in S&NSC memory. So we always just fail the translation
2376 * here and sort things out in the exception handler
2377 * (including possibly emulating an SG instruction).
2379 if (sattrs
.ns
!= !secure
) {
2381 fi
->type
= ARMFault_QEMU_NSCExec
;
2383 fi
->type
= ARMFault_QEMU_SFault
;
2385 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2386 result
->f
.phys_addr
= address
;
2392 * For data accesses we always use the MMU bank indicated
2393 * by the current CPU state, but the security attributes
2394 * might downgrade a secure access to nonsecure.
2397 result
->f
.attrs
.secure
= false;
2398 } else if (!secure
) {
2400 * NS access to S memory must fault.
2401 * Architecturally we should first check whether the
2402 * MPU information for this address indicates that we
2403 * are doing an unaligned access to Device memory, which
2404 * should generate a UsageFault instead. QEMU does not
2405 * currently check for that kind of unaligned access though.
2406 * If we added it we would need to do so as a special case
2407 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2409 fi
->type
= ARMFault_QEMU_SFault
;
2410 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2411 result
->f
.phys_addr
= address
;
2418 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2420 if (sattrs
.subpage
) {
2421 result
->f
.lg_page_size
= 0;
2427 * Translate from the 4-bit stage 2 representation of
2428 * memory attributes (without cache-allocation hints) to
2429 * the 8-bit representation of the stage 1 MAIR registers
2430 * (which includes allocation hints).
2432 * ref: shared/translation/attrs/S2AttrDecode()
2433 * .../S2ConvertAttrsHints()
2435 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2437 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2438 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2439 uint8_t hihint
= 0, lohint
= 0;
2441 if (hiattr
!= 0) { /* normal memory */
2442 if (hcr
& HCR_CD
) { /* cache disabled */
2443 hiattr
= loattr
= 1; /* non-cacheable */
2445 if (hiattr
!= 1) { /* Write-through or write-back */
2446 hihint
= 3; /* RW allocate */
2448 if (loattr
!= 1) { /* Write-through or write-back */
2449 lohint
= 3; /* RW allocate */
2454 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2458 * Combine either inner or outer cacheability attributes for normal
2459 * memory, according to table D4-42 and pseudocode procedure
2460 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2462 * NB: only stage 1 includes allocation hints (RW bits), leading to
2465 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2467 if (s1
== 4 || s2
== 4) {
2468 /* non-cacheable has precedence */
2470 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2471 /* stage 1 write-through takes precedence */
2473 } else if (extract32(s2
, 2, 2) == 2) {
2474 /* stage 2 write-through takes precedence, but the allocation hint
2475 * is still taken from stage 1
2477 return (2 << 2) | extract32(s1
, 0, 2);
2478 } else { /* write-back */
2484 * Combine the memory type and cacheability attributes of
2485 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2486 * combined attributes in MAIR_EL1 format.
2488 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2489 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2491 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2493 if (s2
.is_s2_format
) {
2494 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2496 s2_mair_attrs
= s2
.attrs
;
2499 s1lo
= extract32(s1
.attrs
, 0, 4);
2500 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2501 s1hi
= extract32(s1
.attrs
, 4, 4);
2502 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2504 /* Combine memory type and cacheability attributes */
2505 if (s1hi
== 0 || s2hi
== 0) {
2506 /* Device has precedence over normal */
2507 if (s1lo
== 0 || s2lo
== 0) {
2508 /* nGnRnE has precedence over anything */
2510 } else if (s1lo
== 4 || s2lo
== 4) {
2511 /* non-Reordering has precedence over Reordering */
2512 ret_attrs
= 4; /* nGnRE */
2513 } else if (s1lo
== 8 || s2lo
== 8) {
2514 /* non-Gathering has precedence over Gathering */
2515 ret_attrs
= 8; /* nGRE */
2517 ret_attrs
= 0xc; /* GRE */
2519 } else { /* Normal memory */
2520 /* Outer/inner cacheability combine independently */
2521 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2522 | combine_cacheattr_nibble(s1lo
, s2lo
);
2527 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2530 * Given the 4 bits specifying the outer or inner cacheability
2531 * in MAIR format, return a value specifying Normal Write-Back,
2532 * with the allocation and transient hints taken from the input
2533 * if the input specified some kind of cacheable attribute.
2535 if (attr
== 0 || attr
== 4) {
2537 * 0 == an UNPREDICTABLE encoding
2538 * 4 == Non-cacheable
2539 * Either way, force Write-Back RW allocate non-transient
2543 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2548 * Combine the memory type and cacheability attributes of
2549 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2550 * combined attributes in MAIR_EL1 format.
2552 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2554 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2558 /* Use stage 1 attributes */
2562 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2563 * then we take the allocation hints from it; otherwise it is
2564 * RW allocate, non-transient.
2566 if ((s1
.attrs
& 0xf0) == 0) {
2570 /* Need to check the Inner and Outer nibbles separately */
2571 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2572 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
2574 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
2575 if ((s1
.attrs
& 0xf0) == 0) {
2580 /* Force Device, of subtype specified by S2 */
2581 return s2
.attrs
<< 2;
2584 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
2585 * arbitrarily force Device.
2592 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
2593 * and CombineS1S2Desc()
2596 * @s1: Attributes from stage 1 walk
2597 * @s2: Attributes from stage 2 walk
2599 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
2600 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2603 bool tagged
= false;
2605 assert(!s1
.is_s2_format
);
2606 ret
.is_s2_format
= false;
2607 ret
.guarded
= s1
.guarded
;
2609 if (s1
.attrs
== 0xf0) {
2614 /* Combine shareability attributes (table D4-43) */
2615 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
2616 /* if either are outer-shareable, the result is outer-shareable */
2617 ret
.shareability
= 2;
2618 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
2619 /* if either are inner-shareable, the result is inner-shareable */
2620 ret
.shareability
= 3;
2622 /* both non-shareable */
2623 ret
.shareability
= 0;
2626 /* Combine memory type and cacheability attributes */
2627 if (hcr
& HCR_FWB
) {
2628 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
2630 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
2634 * Any location for which the resultant memory type is any
2635 * type of Device memory is always treated as Outer Shareable.
2636 * Any location for which the resultant memory type is Normal
2637 * Inner Non-cacheable, Outer Non-cacheable is always treated
2638 * as Outer Shareable.
2639 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
2641 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
2642 ret
.shareability
= 2;
2645 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
2646 if (tagged
&& ret
.attrs
== 0xff) {
2654 * MMU disabled. S1 addresses within aa64 translation regimes are
2655 * still checked for bounds -- see AArch64.S1DisabledOutput().
2657 static bool get_phys_addr_disabled(CPUARMState
*env
, target_ulong address
,
2658 MMUAccessType access_type
,
2659 ARMMMUIdx mmu_idx
, bool is_secure
,
2660 GetPhysAddrResult
*result
,
2661 ARMMMUFaultInfo
*fi
)
2663 uint8_t memattr
= 0x00; /* Device nGnRnE */
2664 uint8_t shareability
= 0; /* non-sharable */
2668 case ARMMMUIdx_Stage2
:
2669 case ARMMMUIdx_Stage2_S
:
2670 case ARMMMUIdx_Phys_NS
:
2671 case ARMMMUIdx_Phys_S
:
2675 r_el
= regime_el(env
, mmu_idx
);
2676 if (arm_el_is_aa64(env
, r_el
)) {
2677 int pamax
= arm_pamax(env_archcpu(env
));
2678 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
2681 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
2682 if (access_type
== MMU_INST_FETCH
) {
2683 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
2685 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
2686 addrtop
= (tbi
? 55 : 63);
2688 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
2689 fi
->type
= ARMFault_AddressSize
;
2696 * When TBI is disabled, we've just validated that all of the
2697 * bits above PAMax are zero, so logically we only need to
2698 * clear the top byte for TBI. But it's clearer to follow
2699 * the pseudocode set of addrdesc.paddress.
2701 address
= extract64(address
, 0, 52);
2704 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
2706 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2708 if (hcr
& HCR_DCT
) {
2709 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
2711 memattr
= 0xff; /* Normal, WB, RWA */
2715 if (memattr
== 0 && access_type
== MMU_INST_FETCH
) {
2716 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
2717 memattr
= 0xee; /* Normal, WT, RA, NT */
2719 memattr
= 0x44; /* Normal, NC, No */
2721 shareability
= 2; /* outer sharable */
2723 result
->cacheattrs
.is_s2_format
= false;
2727 result
->f
.phys_addr
= address
;
2728 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2729 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2730 result
->cacheattrs
.shareability
= shareability
;
2731 result
->cacheattrs
.attrs
= memattr
;
2735 static bool get_phys_addr_twostage(CPUARMState
*env
, S1Translate
*ptw
,
2736 target_ulong address
,
2737 MMUAccessType access_type
,
2738 GetPhysAddrResult
*result
,
2739 ARMMMUFaultInfo
*fi
)
2742 int s1_prot
, s1_lgpgsz
;
2743 bool is_secure
= ptw
->in_secure
;
2744 bool ret
, ipa_secure
;
2745 ARMCacheAttrs cacheattrs1
;
2749 ret
= get_phys_addr_with_struct(env
, ptw
, address
, access_type
, result
, fi
);
2751 /* If S1 fails, return early. */
2756 ipa
= result
->f
.phys_addr
;
2757 ipa_secure
= result
->f
.attrs
.secure
;
2759 is_el0
= ptw
->in_mmu_idx
== ARMMMUIdx_Stage1_E0
;
2760 ptw
->in_mmu_idx
= ipa_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2761 ptw
->in_secure
= ipa_secure
;
2762 ptw
->in_ptw_idx
= ptw_idx_for_stage_2(env
, ptw
->in_mmu_idx
);
2765 * S1 is done, now do S2 translation.
2766 * Save the stage1 results so that we may merge prot and cacheattrs later.
2768 s1_prot
= result
->f
.prot
;
2769 s1_lgpgsz
= result
->f
.lg_page_size
;
2770 cacheattrs1
= result
->cacheattrs
;
2771 memset(result
, 0, sizeof(*result
));
2773 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2774 ret
= get_phys_addr_pmsav8(env
, ipa
, access_type
,
2775 ptw
->in_mmu_idx
, is_secure
, result
, fi
);
2777 ret
= get_phys_addr_lpae(env
, ptw
, ipa
, access_type
,
2778 is_el0
, result
, fi
);
2782 /* Combine the S1 and S2 perms. */
2783 result
->f
.prot
&= s1_prot
;
2785 /* If S2 fails, return early. */
2791 * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
2792 * this means "don't put this in the TLB"; in this case, return a
2793 * result with lg_page_size == 0 to achieve that. Otherwise,
2794 * use the maximum of the S1 & S2 page size, so that invalidation
2795 * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
2796 * we know the combined result permissions etc only cover the minimum
2797 * of the S1 and S2 page size, because we know that the common TLB code
2798 * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
2799 * and passing a larger page size value only affects invalidations.)
2801 if (result
->f
.lg_page_size
< TARGET_PAGE_BITS
||
2802 s1_lgpgsz
< TARGET_PAGE_BITS
) {
2803 result
->f
.lg_page_size
= 0;
2804 } else if (result
->f
.lg_page_size
< s1_lgpgsz
) {
2805 result
->f
.lg_page_size
= s1_lgpgsz
;
2808 /* Combine the S1 and S2 cache attributes. */
2809 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2812 * HCR.DC forces the first stage attributes to
2813 * Normal Non-Shareable,
2814 * Inner Write-Back Read-Allocate Write-Allocate,
2815 * Outer Write-Back Read-Allocate Write-Allocate.
2816 * Do not overwrite Tagged within attrs.
2818 if (cacheattrs1
.attrs
!= 0xf0) {
2819 cacheattrs1
.attrs
= 0xff;
2821 cacheattrs1
.shareability
= 0;
2823 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
2824 result
->cacheattrs
);
2827 * Check if IPA translates to secure or non-secure PA space.
2828 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
2830 result
->f
.attrs
.secure
=
2832 && !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
2834 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
))));
2839 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
2840 target_ulong address
,
2841 MMUAccessType access_type
,
2842 GetPhysAddrResult
*result
,
2843 ARMMMUFaultInfo
*fi
)
2845 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2846 bool is_secure
= ptw
->in_secure
;
2847 ARMMMUIdx s1_mmu_idx
;
2850 * The page table entries may downgrade secure to non-secure, but
2851 * cannot upgrade an non-secure translation regime's attributes
2854 result
->f
.attrs
.secure
= is_secure
;
2857 case ARMMMUIdx_Phys_S
:
2858 case ARMMMUIdx_Phys_NS
:
2859 /* Checking Phys early avoids special casing later vs regime_el. */
2860 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2861 is_secure
, result
, fi
);
2863 case ARMMMUIdx_Stage1_E0
:
2864 case ARMMMUIdx_Stage1_E1
:
2865 case ARMMMUIdx_Stage1_E1_PAN
:
2866 /* First stage lookup uses second stage for ptw. */
2867 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2870 case ARMMMUIdx_Stage2
:
2871 case ARMMMUIdx_Stage2_S
:
2873 * Second stage lookup uses physical for ptw; whether this is S or
2874 * NS may depend on the SW/NSW bits if this is a stage 2 lookup for
2875 * the Secure EL2&0 regime.
2877 ptw
->in_ptw_idx
= ptw_idx_for_stage_2(env
, mmu_idx
);
2880 case ARMMMUIdx_E10_0
:
2881 s1_mmu_idx
= ARMMMUIdx_Stage1_E0
;
2883 case ARMMMUIdx_E10_1
:
2884 s1_mmu_idx
= ARMMMUIdx_Stage1_E1
;
2886 case ARMMMUIdx_E10_1_PAN
:
2887 s1_mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
2890 * Call ourselves recursively to do the stage 1 and then stage 2
2891 * translations if mmu_idx is a two-stage regime, and EL2 present.
2892 * Otherwise, a stage1+stage2 translation is just stage 1.
2894 ptw
->in_mmu_idx
= mmu_idx
= s1_mmu_idx
;
2895 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2896 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
, is_secure
)) {
2897 return get_phys_addr_twostage(env
, ptw
, address
, access_type
,
2903 /* Single stage uses physical for ptw. */
2904 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2908 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
2911 * Fast Context Switch Extension. This doesn't exist at all in v8.
2912 * In v7 and earlier it affects all stage 1 translations.
2914 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
2915 && !arm_feature(env
, ARM_FEATURE_V8
)) {
2916 if (regime_el(env
, mmu_idx
) == 3) {
2917 address
+= env
->cp15
.fcseidr_s
;
2919 address
+= env
->cp15
.fcseidr_ns
;
2923 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2925 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2927 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2929 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
2930 is_secure
, result
, fi
);
2931 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2933 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
2934 is_secure
, result
, fi
);
2937 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
2938 is_secure
, result
, fi
);
2940 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
2941 " mmu_idx %u -> %s (prot %c%c%c)\n",
2942 access_type
== MMU_DATA_LOAD
? "reading" :
2943 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
2944 (uint32_t)address
, mmu_idx
,
2945 ret
? "Miss" : "Hit",
2946 result
->f
.prot
& PAGE_READ
? 'r' : '-',
2947 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
2948 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
2953 /* Definitely a real MMU, not an MPU */
2955 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
2956 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2957 is_secure
, result
, fi
);
2960 if (regime_using_lpae_format(env
, mmu_idx
)) {
2961 return get_phys_addr_lpae(env
, ptw
, address
, access_type
, false,
2963 } else if (arm_feature(env
, ARM_FEATURE_V7
) ||
2964 regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
2965 return get_phys_addr_v6(env
, ptw
, address
, access_type
, result
, fi
);
2967 return get_phys_addr_v5(env
, ptw
, address
, access_type
, result
, fi
);
2971 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
2972 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2973 bool is_secure
, GetPhysAddrResult
*result
,
2974 ARMMMUFaultInfo
*fi
)
2977 .in_mmu_idx
= mmu_idx
,
2978 .in_secure
= is_secure
,
2980 return get_phys_addr_with_struct(env
, &ptw
, address
, access_type
,
2984 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
2985 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2986 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
2991 case ARMMMUIdx_E10_0
:
2992 case ARMMMUIdx_E10_1
:
2993 case ARMMMUIdx_E10_1_PAN
:
2994 case ARMMMUIdx_E20_0
:
2995 case ARMMMUIdx_E20_2
:
2996 case ARMMMUIdx_E20_2_PAN
:
2997 case ARMMMUIdx_Stage1_E0
:
2998 case ARMMMUIdx_Stage1_E1
:
2999 case ARMMMUIdx_Stage1_E1_PAN
:
3001 is_secure
= arm_is_secure_below_el3(env
);
3003 case ARMMMUIdx_Stage2
:
3004 case ARMMMUIdx_Phys_NS
:
3005 case ARMMMUIdx_MPrivNegPri
:
3006 case ARMMMUIdx_MUserNegPri
:
3007 case ARMMMUIdx_MPriv
:
3008 case ARMMMUIdx_MUser
:
3012 case ARMMMUIdx_Stage2_S
:
3013 case ARMMMUIdx_Phys_S
:
3014 case ARMMMUIdx_MSPrivNegPri
:
3015 case ARMMMUIdx_MSUserNegPri
:
3016 case ARMMMUIdx_MSPriv
:
3017 case ARMMMUIdx_MSUser
:
3021 g_assert_not_reached();
3023 return get_phys_addr_with_secure(env
, address
, access_type
, mmu_idx
,
3024 is_secure
, result
, fi
);
3027 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
3030 ARMCPU
*cpu
= ARM_CPU(cs
);
3031 CPUARMState
*env
= &cpu
->env
;
3033 .in_mmu_idx
= arm_mmu_idx(env
),
3034 .in_secure
= arm_is_secure(env
),
3037 GetPhysAddrResult res
= {};
3038 ARMMMUFaultInfo fi
= {};
3041 ret
= get_phys_addr_with_struct(env
, &ptw
, addr
, MMU_DATA_LOAD
, &res
, &fi
);
3042 *attrs
= res
.f
.attrs
;
3047 return res
.f
.phys_addr
;