1 # AArch64 SVE instruction descriptions
3 # Copyright (c) 2017 Linaro, Ltd
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
10 # This library is distributed in the hope that it will be useful,
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13 # Lesser General Public License for more details.
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 # This file is processed by scripts/decodetree.py
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
29 %imm9_16_10 16:s6 10:3
31 %dtype_23_13 23:2 13:2
33 # A combination of tsz:imm3 -- extract esize.
34 %tszimm_esz 22:2 5:5 !function=tszimm_esz
35 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
36 %tszimm_shr 22:2 5:5 !function=tszimm_shr
37 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
38 %tszimm_shl 22:2 5:5 !function=tszimm_shl
40 # Similarly for the tszh/tszl pair at 22/16 for zzi
41 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
42 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
43 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
45 # Signed 8-bit immediate, optionally shifted left by 8.
46 %sh8_i8s 5:9 !function=expand_imm_sh8s
47 # Unsigned 8-bit immediate, optionally shifted left by 8.
48 %sh8_i8u 5:9 !function=expand_imm_sh8u
50 # Unsigned load of msz into esz=2, represented as a dtype.
51 %msz_dtype 23:2 !function=msz_dtype
53 # Either a copy of rd (at bit 0), or a different source
54 # as propagated via the MOVPRFX instruction.
57 ###########################################################################
58 # Named attribute sets. These are used to make nice(er) names
59 # when creating helpers common to those for the individual
60 # instruction patterns.
66 &rri_esz rd rn imm esz
71 &rprr_esz rd pg rn rm esz
72 &rprrr_esz rd pg rn rm ra esz
73 &rpri_esz rd pg rn imm esz
75 &incdec_cnt rd pat esz imm d u
76 &incdec2_cnt rd rn pat esz imm d u
77 &incdec_pred rd pg esz d u
78 &incdec2_pred rd rn pg esz d u
79 &rprr_load rd pg rn rm dtype nreg
80 &rpri_load rd pg rn imm dtype nreg
81 &rprr_store rd pg rn rm msz esz nreg
82 &rpri_store rd pg rn imm msz esz nreg
83 &rprr_gather_load rd pg rn rm esz msz u ff xs scale
84 &rpri_gather_load rd pg rn imm esz msz u ff
85 &rprr_scatter_store rd pg rn rm esz msz xs scale
86 &rpri_scatter_store rd pg rn imm esz msz
88 ###########################################################################
89 # Named instruction formats. These are generally used to
90 # reduce the amount of duplication between instruction patterns.
92 # Two operand with unused vector element size
93 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
96 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
97 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
99 # Two operand with governing predicate, flags setting
100 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
102 # Three operand with unused vector element size
103 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
105 # Three predicate operand, with governing predicate, flag setting
106 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
108 # Three operand, vector element size
109 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
110 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
111 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
112 &rrr_esz rn=%reg_movprfx
113 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
114 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
115 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
116 &rri_esz rn=%reg_movprfx
117 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
118 &rri_esz rn=%reg_movprfx
120 # Three operand with "memory" size, aka immediate left shift
121 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
123 # Two register operand, with governing predicate, vector element size
124 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
125 &rprr_esz rn=%reg_movprfx
126 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
127 &rprr_esz rm=%reg_movprfx
128 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
129 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
131 # Three register operand, with governing predicate, vector element size
132 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
133 &rprrr_esz ra=%reg_movprfx
134 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
135 &rprrr_esz rn=%reg_movprfx
136 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
137 &rprrr_esz rn=%reg_movprfx
139 # One register operand, with governing predicate, vector element size
140 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
141 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
143 # One register operand, with governing predicate, no vector element size
144 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
146 # Two register operands with a 6-bit signed immediate.
147 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
149 # Two register operand, one immediate operand, with predicate,
150 # element size encoded as TSZHL. User must fill in imm.
151 @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
152 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
154 # Similarly without predicate.
155 @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
156 &rri_esz esz=%tszimm16_esz
158 # Two register operand, one immediate operand, with 4-bit predicate.
159 # User must fill in imm.
160 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
161 &rpri_esz rn=%reg_movprfx
163 # Two register operand, one one-bit floating-point operand.
164 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
165 &rpri_esz rn=%reg_movprfx
167 # Two register operand, one encoded bitmask.
168 @rdn_dbm ........ .. .... dbm:13 rd:5 \
169 &rr_dbm rn=%reg_movprfx
171 # Predicate output, vector and immediate input,
172 # controlling predicate, element size.
173 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
174 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
176 # Basic Load/Store with 9-bit immediate offset
177 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
179 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
182 # One register, pattern, and uint4+1.
183 # User must fill in U and D.
184 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
185 &incdec_cnt imm=%imm4_16_p1
186 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
187 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
189 # One register, predicate.
190 # User must fill in U and D.
191 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
192 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
193 &incdec2_pred rn=%reg_movprfx
195 # Loads; user must fill in NREG.
196 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
197 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
199 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
200 &rprr_load dtype=%msz_dtype
201 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
202 &rpri_load dtype=%msz_dtype
205 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
206 &rprr_gather_load xs=2
207 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
209 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
211 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
213 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
214 &rprr_gather_load xs=2
215 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
216 &rprr_gather_load xs=2
217 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
220 # Stores; user must fill in ESZ, MSZ, NREG as needed.
221 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
222 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
223 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
225 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
227 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
230 ###########################################################################
231 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
233 ### SVE Integer Arithmetic - Binary Predicated Group
235 # SVE bitwise logical vector operations (predicated)
236 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
237 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
238 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
239 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
241 # SVE integer add/subtract vectors (predicated)
242 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
243 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
244 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
246 # SVE integer min/max/difference (predicated)
247 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
248 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
249 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
250 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
251 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
252 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
254 # SVE integer multiply/divide (predicated)
255 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
256 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
257 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
258 # Note that divide requires size >= 2; below 2 is unallocated.
259 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
260 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
261 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
262 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
264 ### SVE Integer Reduction Group
266 # SVE bitwise logical reduction (predicated)
267 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
268 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
269 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
271 # SVE integer add reduction (predicated)
272 # Note that saddv requires size != 3.
273 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
274 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
276 # SVE integer min/max reduction (predicated)
277 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
278 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
279 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
280 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
282 ### SVE Shift by Immediate - Predicated Group
284 # SVE bitwise shift by immediate (predicated)
285 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
286 @rdn_pg_tszimm imm=%tszimm_shr
287 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
288 @rdn_pg_tszimm imm=%tszimm_shr
289 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
290 @rdn_pg_tszimm imm=%tszimm_shl
291 ASRD 00000100 .. 000 100 100 ... .. ... ..... \
292 @rdn_pg_tszimm imm=%tszimm_shr
294 # SVE bitwise shift by vector (predicated)
295 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
296 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
297 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
298 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
299 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
300 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
302 # SVE bitwise shift by wide elements (predicated)
303 # Note these require size != 3.
304 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
305 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
306 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
308 ### SVE Integer Arithmetic - Unary Predicated Group
310 # SVE unary bit operations (predicated)
311 # Note esz != 0 for FABS and FNEG.
312 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
313 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
314 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
315 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
316 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
317 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
318 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
320 # SVE integer unary operations (predicated)
321 # Note esz > original size for extensions.
322 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
323 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
324 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
325 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
326 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
327 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
328 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
329 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
331 ### SVE Floating Point Compare - Vectors Group
333 # SVE floating-point compare vectors
334 FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
335 FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
336 FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
337 FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
338 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
339 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
340 FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
342 ### SVE Integer Multiply-Add Group
344 # SVE integer multiply-add writing addend (predicated)
345 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
346 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
348 # SVE integer multiply-add writing multiplicand (predicated)
349 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
350 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
352 ### SVE Integer Arithmetic - Unpredicated Group
354 # SVE integer add/subtract vectors (unpredicated)
355 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
356 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
357 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
358 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
359 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
360 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
362 ### SVE Logical - Unpredicated Group
364 # SVE bitwise logical operations (unpredicated)
365 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
366 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
367 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
368 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
370 ### SVE Index Generation Group
372 # SVE index generation (immediate start, immediate increment)
373 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
375 # SVE index generation (immediate start, register increment)
376 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
378 # SVE index generation (register start, immediate increment)
379 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
381 # SVE index generation (register start, register increment)
382 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
384 ### SVE Stack Allocation Group
386 # SVE stack frame adjustment
387 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
388 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
390 # SVE stack frame size
391 RDVL 00000100 101 11111 01010 imm:s6 rd:5
393 ### SVE Bitwise Shift - Unpredicated Group
395 # SVE bitwise shift by immediate (unpredicated)
396 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
397 @rd_rn_tszimm imm=%tszimm16_shr
398 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
399 @rd_rn_tszimm imm=%tszimm16_shr
400 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
401 @rd_rn_tszimm imm=%tszimm16_shl
403 # SVE bitwise shift by wide elements (unpredicated)
405 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
406 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
407 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
409 ### SVE Compute Vector Address Group
411 # SVE vector address generation
412 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
413 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
414 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
415 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
417 ### SVE Integer Misc - Unpredicated Group
419 # SVE floating-point exponential accelerator
421 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
423 # SVE floating-point trig select coefficient
425 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
427 ### SVE Element Count Group
430 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
432 # SVE inc/dec register by element count
433 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
435 # SVE saturating inc/dec register by element count
436 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
437 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
439 # SVE inc/dec vector by element count
440 # Note this requires esz != 0.
441 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
443 # SVE saturating inc/dec vector by element count
444 # Note these require esz != 0.
445 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
447 ### SVE Bitwise Immediate Group
449 # SVE bitwise logical with immediate (unpredicated)
450 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
451 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
452 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
454 # SVE broadcast bitmask immediate
455 DUPM 00000101 11 0000 dbm:13 rd:5
457 ### SVE Integer Wide Immediate - Predicated Group
459 # SVE copy floating-point immediate (predicated)
460 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
462 # SVE copy integer immediate (predicated)
463 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
464 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
466 ### SVE Permute - Extract Group
468 # SVE extract vector (immediate offset)
469 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
470 &rrri rn=%reg_movprfx imm=%imm8_16_10
472 ### SVE Permute - Unpredicated Group
474 # SVE broadcast general register
475 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
477 # SVE broadcast indexed element
478 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
481 # SVE insert SIMD&FP scalar register
482 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
484 # SVE insert general register
485 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
487 # SVE reverse vector elements
488 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
490 # SVE vector table lookup
491 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
493 # SVE unpack vector elements
494 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
496 ### SVE Permute - Predicates Group
498 # SVE permute predicate elements
499 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
500 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
501 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
502 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
503 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
504 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
506 # SVE reverse predicate elements
507 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
509 # SVE unpack predicate elements
510 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
511 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
513 ### SVE Permute - Interleaving Group
515 # SVE permute vector elements
516 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
517 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
518 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
519 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
520 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
521 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
523 ### SVE Permute - Predicated Group
525 # SVE compress active elements
527 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
529 # SVE conditionally broadcast element to vector
530 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
531 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
533 # SVE conditionally copy element to SIMD&FP scalar
534 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
535 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
537 # SVE conditionally copy element to general register
538 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
539 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
541 # SVE copy element to SIMD&FP scalar register
542 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
543 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
545 # SVE copy element to general register
546 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
547 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
549 # SVE copy element from SIMD&FP scalar register
550 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
552 # SVE copy element from general register to vector (predicated)
553 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
555 # SVE reverse within elements
556 # Note esz >= operation size
557 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
558 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
559 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
560 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
562 # SVE vector splice (predicated)
563 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
565 ### SVE Select Vectors Group
567 # SVE select vector elements (predicated)
568 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
570 ### SVE Integer Compare - Vectors Group
572 # SVE integer compare_vectors
573 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
574 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
575 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
576 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
577 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
578 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
580 # SVE integer compare with wide elements
581 # Note these require esz != 3.
582 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
583 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
584 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
585 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
586 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
587 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
588 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
589 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
590 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
591 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
593 ### SVE Integer Compare - Unsigned Immediate Group
595 # SVE integer compare with unsigned immediate
596 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
597 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
598 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
599 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
601 ### SVE Integer Compare - Signed Immediate Group
603 # SVE integer compare with signed immediate
604 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
605 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
606 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
607 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
608 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
609 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
611 ### SVE Predicate Logical Operations Group
613 # SVE predicate logical operations
614 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
615 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
616 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
617 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
618 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
619 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
620 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
621 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
623 ### SVE Predicate Misc Group
626 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
628 # SVE predicate initialize
629 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
632 SETFFR 00100101 0010 1100 1001 0000 0000 0000
634 # SVE zero predicate register
635 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
637 # SVE predicate read from FFR (predicated)
638 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
640 # SVE predicate read from FFR (unpredicated)
641 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
643 # SVE FFR write from predicate (WRFFR)
644 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
646 # SVE predicate first active
647 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
649 # SVE predicate next active
650 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
652 ### SVE Partition Break Group
654 # SVE propagate break from previous partition
655 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
656 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
658 # SVE partition break condition
659 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
660 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
661 BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
662 BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
664 # SVE propagate break to next partition
665 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
667 ### SVE Predicate Count Group
669 # SVE predicate count
670 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
672 # SVE inc/dec register by predicate count
673 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
675 # SVE inc/dec vector by predicate count
676 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
678 # SVE saturating inc/dec register by predicate count
679 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
680 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
682 # SVE saturating inc/dec vector by predicate count
683 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
685 ### SVE Integer Compare - Scalars Group
687 # SVE conditionally terminate scalars
688 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
690 # SVE integer compare scalar count and limit
691 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
693 ### SVE Integer Wide Immediate - Unpredicated Group
695 # SVE broadcast floating-point immediate (unpredicated)
696 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
698 # SVE broadcast integer immediate (unpredicated)
699 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
701 # SVE integer add/subtract immediate (unpredicated)
702 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
703 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
704 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
705 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
706 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
707 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
708 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
710 # SVE integer min/max immediate (unpredicated)
711 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
712 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
713 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
714 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
716 # SVE integer multiply immediate (unpredicated)
717 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
719 ### SVE FP Accumulating Reduction Group
721 # SVE floating-point serial reduction (predicated)
722 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
724 ### SVE Floating Point Arithmetic - Unpredicated Group
726 # SVE floating-point arithmetic (unpredicated)
727 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
728 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
729 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
730 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
731 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
732 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
734 ### SVE FP Arithmetic Predicated Group
736 # SVE floating-point arithmetic (predicated)
737 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
738 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
739 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
740 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
741 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
742 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
743 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
744 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
745 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
746 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
747 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
748 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
749 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
751 # SVE floating-point arithmetic with immediate (predicated)
752 FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
753 FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
754 FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
755 FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
756 FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
757 FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
758 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
759 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
761 ### SVE FP Multiply-Add Group
763 # SVE floating-point multiply-accumulate writing addend
764 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
765 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
766 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
767 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
769 # SVE floating-point multiply-accumulate writing multiplicand
770 # Alter the operand extraction order and reuse the helpers from above.
771 # FMAD, FMSB, FNMAD, FNMS
772 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
773 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
774 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
775 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
777 ### SVE FP Unary Operations Predicated Group
779 # SVE integer convert to floating-point
780 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
781 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
782 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
783 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
784 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
785 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
786 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
788 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
789 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
790 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
791 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
792 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
793 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
794 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
796 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
798 # SVE load predicate register
799 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
801 # SVE load vector register
802 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
804 # SVE load and broadcast element
805 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
806 &rpri_load dtype=%dtype_23_13 nreg=0
808 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
809 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
810 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
811 @rprr_g_load_xs_u esz=2 msz=0 scale=0
812 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
813 @rprr_g_load_xs_u_sc esz=2 msz=1
814 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
815 @rprr_g_load_xs_sc esz=2 msz=2 u=1
817 # SVE 32-bit gather load (vector plus immediate)
818 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
821 ### SVE Memory Contiguous Load Group
823 # SVE contiguous load (scalar plus scalar)
824 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
826 # SVE contiguous first-fault load (scalar plus scalar)
827 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
829 # SVE contiguous load (scalar plus immediate)
830 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
832 # SVE contiguous non-fault load (scalar plus immediate)
833 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
835 # SVE contiguous non-temporal load (scalar plus scalar)
836 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
837 # SVE load multiple structures (scalar plus scalar)
838 # LD2B, LD2H, LD2W, LD2D; etc.
839 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
841 # SVE contiguous non-temporal load (scalar plus immediate)
842 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
843 # SVE load multiple structures (scalar plus immediate)
844 # LD2B, LD2H, LD2W, LD2D; etc.
845 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
847 # SVE load and broadcast quadword (scalar plus scalar)
848 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
849 @rprr_load_msz nreg=0
851 # SVE load and broadcast quadword (scalar plus immediate)
852 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
853 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
854 @rpri_load_msz nreg=0
856 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
857 PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
859 # SVE 32-bit gather prefetch (vector plus immediate)
860 PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
862 # SVE contiguous prefetch (scalar plus immediate)
863 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
865 # SVE contiguous prefetch (scalar plus scalar)
866 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
868 ### SVE Memory 64-bit Gather Group
870 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
871 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
872 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
873 @rprr_g_load_xs_u esz=3 msz=0 scale=0
874 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
875 @rprr_g_load_xs_u_sc esz=3 msz=1
876 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
877 @rprr_g_load_xs_u_sc esz=3 msz=2
878 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
879 @rprr_g_load_xs_sc esz=3 msz=3 u=1
881 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
882 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
883 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
884 @rprr_g_load_u esz=3 msz=0 scale=0
885 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
886 @rprr_g_load_u_sc esz=3 msz=1
887 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
888 @rprr_g_load_u_sc esz=3 msz=2
889 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
890 @rprr_g_load_sc esz=3 msz=3 u=1
892 # SVE 64-bit gather load (vector plus immediate)
893 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
896 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
897 PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
899 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
900 PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
902 # SVE 64-bit gather prefetch (vector plus immediate)
903 PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
905 ### SVE Memory Store Group
907 # SVE store predicate register
908 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
910 # SVE store vector register
911 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
913 # SVE contiguous store (scalar plus immediate)
914 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
915 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
916 @rpri_store_msz nreg=0
918 # SVE contiguous store (scalar plus scalar)
919 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
920 # Enumerate msz lest we conflict with STR_zri.
921 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
922 @rprr_store_esz_n0 msz=0
923 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
924 @rprr_store_esz_n0 msz=1
925 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
926 @rprr_store_esz_n0 msz=2
927 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
928 @rprr_store msz=3 esz=3 nreg=0
930 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
931 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
932 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
933 @rpri_store_msz esz=%size_23
935 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
936 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
937 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
938 @rprr_store esz=%size_23
940 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
941 # Require msz > 0 && msz <= esz.
942 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
943 @rprr_scatter_store xs=0 esz=2 scale=1
944 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
945 @rprr_scatter_store xs=1 esz=2 scale=1
947 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
948 # Require msz <= esz.
949 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
950 @rprr_scatter_store xs=0 esz=2 scale=0
951 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
952 @rprr_scatter_store xs=1 esz=2 scale=0
954 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
956 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
957 @rprr_scatter_store xs=2 esz=3 scale=1
959 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
960 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
961 @rprr_scatter_store xs=2 esz=3 scale=0
963 # SVE 64-bit scatter store (vector plus immediate)
964 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
965 @rpri_scatter_store esz=3
967 # SVE 32-bit scatter store (vector plus immediate)
968 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
969 @rpri_scatter_store esz=2
971 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
973 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
974 @rprr_scatter_store xs=0 esz=3 scale=1
975 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
976 @rprr_scatter_store xs=1 esz=3 scale=1
978 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
979 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
980 @rprr_scatter_store xs=0 esz=3 scale=0
981 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
982 @rprr_scatter_store xs=1 esz=3 scale=0
projects / mirror_qemu.git / blob