target/arm/t16.decode

   1 # Thumb1 instructions
   2 #
   3 #  Copyright (c) 2019 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21
  22 &s_rrr_shi       !extern s rd rn rm shim shty
  23 &s_rrr_shr       !extern s rn rd rm rs shty
  24 &s_rri_rot       !extern s rn rd imm rot
  25 &s_rrrr          !extern s rd rn rm ra
  26 &rrr_rot         !extern rd rn rm rot
  27 &ri              !extern rd imm
  28 &r               !extern rm
  29 &ldst_rr         !extern p w u rn rt rm shimm shtype
  30 &ldst_ri         !extern p w u rn rt imm
  31 &ldst_block      !extern rn i b u w list
  32 &setend          !extern E
  33 &cps             !extern mode imod M A I F
  34
  35 # Set S if the instruction is outside of an IT block.
  36 %s               !function=t16_setflags
  37
  38 # Data-processing (two low registers)
  39
  40 %reg_0           0:3
  41
  42 @lll_noshr       ...... .... rm:3 rd:3 \
  43                  &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
  44 @xll_noshr       ...... .... rm:3 rn:3 \
  45                  &s_rrr_shi s=1 rd=0 shim=0 shty=0
  46 @lxl_shr         ...... .... rs:3 rd:3 \
  47                  &s_rrr_shr %s rm=%reg_0 rn=0
  48
  49 AND_rrri         010000 0000 ... ...            @lll_noshr
  50 EOR_rrri         010000 0001 ... ...            @lll_noshr
  51 MOV_rxrr         010000 0010 ... ...            @lxl_shr shty=0  # LSL
  52 MOV_rxrr         010000 0011 ... ...            @lxl_shr shty=1  # LSR
  53 MOV_rxrr         010000 0100 ... ...            @lxl_shr shty=2  # ASR
  54 ADC_rrri         010000 0101 ... ...            @lll_noshr
  55 SBC_rrri         010000 0110 ... ...            @lll_noshr
  56 MOV_rxrr         010000 0111 ... ...            @lxl_shr shty=3  # ROR
  57 TST_xrri         010000 1000 ... ...            @xll_noshr
  58 RSB_rri          010000 1001 rn:3 rd:3          &s_rri_rot %s imm=0 rot=0
  59 CMP_xrri         010000 1010 ... ...            @xll_noshr
  60 CMN_xrri         010000 1011 ... ...            @xll_noshr
  61 ORR_rrri         010000 1100 ... ...            @lll_noshr
  62 MUL              010000 1101 rn:3 rd:3          &s_rrrr %s rm=%reg_0 ra=0
  63 BIC_rrri         010000 1110 ... ...            @lll_noshr
  64 MVN_rxri         010000 1111 ... ...            @lll_noshr
  65
  66 # Load/store (register offset)
  67
  68 @ldst_rr         ....... rm:3 rn:3 rt:3 \
  69                  &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
  70
  71 STR_rr           0101 000 ... ... ...           @ldst_rr
  72 STRH_rr          0101 001 ... ... ...           @ldst_rr
  73 STRB_rr          0101 010 ... ... ...           @ldst_rr
  74 LDRSB_rr         0101 011 ... ... ...           @ldst_rr
  75 LDR_rr           0101 100 ... ... ...           @ldst_rr
  76 LDRH_rr          0101 101 ... ... ...           @ldst_rr
  77 LDRB_rr          0101 110 ... ... ...           @ldst_rr
  78 LDRSH_rr         0101 111 ... ... ...           @ldst_rr
  79
  80 # Load/store word/byte (immediate offset)
  81
  82 %imm5_6x4       6:5 !function=times_4
  83
  84 @ldst_ri_1      ..... imm:5 rn:3 rt:3 \
  85                 &ldst_ri p=1 w=0 u=1
  86 @ldst_ri_4      ..... ..... rn:3 rt:3 \
  87                 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
  88
  89 STR_ri          01100 ..... ... ...             @ldst_ri_4
  90 LDR_ri          01101 ..... ... ...             @ldst_ri_4
  91 STRB_ri         01110 ..... ... ...             @ldst_ri_1
  92 LDRB_ri         01111 ..... ... ...             @ldst_ri_1
  93
  94 # Load/store halfword (immediate offset)
  95
  96 %imm5_6x2       6:5 !function=times_2
  97 @ldst_ri_2      ..... ..... rn:3 rt:3 \
  98                 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
  99
 100 STRH_ri         10000 ..... ... ...             @ldst_ri_2
 101 LDRH_ri         10001 ..... ... ...             @ldst_ri_2
 102
 103 # Load/store (SP-relative)
 104
 105 %imm8_0x4       0:8 !function=times_4
 106 @ldst_spec_i    ..... rt:3 ........ \
 107                 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
 108
 109 STR_ri          10010 ... ........              @ldst_spec_i rn=13
 110 LDR_ri          10011 ... ........              @ldst_spec_i rn=13
 111
 112 # Add PC/SP (immediate)
 113
 114 ADR             10100 rd:3 ........             imm=%imm8_0x4
 115 ADD_rri         10101 rd:3 ........ \
 116                 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4  # SP
 117
 118 # Load/store multiple
 119
 120 @ldstm          ..... rn:3 list:8               &ldst_block i=1 b=0 u=0 w=1
 121
 122 STM             11000 ... ........              @ldstm
 123 LDM_t16         11001 ... ........              @ldstm
 124
 125 # Add/subtract (three low registers)
 126
 127 @addsub_3       ....... rm:3 rn:3 rd:3 \
 128                 &s_rrr_shi %s shim=0 shty=0
 129
 130 ADD_rrri        0001100 ... ... ...             @addsub_3
 131 SUB_rrri        0001101 ... ... ...             @addsub_3
 132
 133 # Add/subtract (two low registers and immediate)
 134
 135 @addsub_2i      ....... imm:3 rn:3 rd:3 \
 136                 &s_rri_rot %s rot=0
 137
 138 ADD_rri         0001 110 ... ... ...            @addsub_2i
 139 SUB_rri         0001 111 ... ... ...            @addsub_2i
 140
 141 # Add, subtract, compare, move (one low register and immediate)
 142
 143 %reg_8          8:3
 144 @arith_1i       ..... rd:3 imm:8 \
 145                 &s_rri_rot rot=0 rn=%reg_8
 146
 147 MOV_rxi         00100 ... ........              @arith_1i %s
 148 CMP_xri         00101 ... ........              @arith_1i s=1
 149 ADD_rri         00110 ... ........              @arith_1i %s
 150 SUB_rri         00111 ... ........              @arith_1i %s
 151
 152 # Add, compare, move (two high registers)
 153
 154 %reg_0_7        7:1 0:3
 155 @addsub_2h      .... .... . rm:4 ... \
 156                 &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
 157
 158 ADD_rrri        0100 0100 . .... ...            @addsub_2h s=0
 159 CMP_xrri        0100 0101 . .... ...            @addsub_2h s=1
 160 MOV_rxri        0100 0110 . .... ...            @addsub_2h s=0
 161
 162 # Adjust SP (immediate)
 163
 164 %imm7_0x4       0:7 !function=times_4
 165 @addsub_sp_i    .... .... . ....... \
 166                 &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
 167
 168 ADD_rri         1011 0000 0 .......             @addsub_sp_i
 169 SUB_rri         1011 0000 1 .......             @addsub_sp_i
 170
 171 # Branch and exchange
 172
 173 @branchr        .... .... . rm:4 ...            &r
 174
 175 BX              0100 0111 0 .... 000            @branchr
 176 BLX_r           0100 0111 1 .... 000            @branchr
 177 BXNS            0100 0111 0 .... 100            @branchr
 178 BLXNS           0100 0111 1 .... 100            @branchr
 179
 180 # Extend
 181
 182 @extend         .... .... .. rm:3 rd:3          &rrr_rot rn=15 rot=0
 183
 184 SXTAH           1011 0010 00 ... ...            @extend
 185 SXTAB           1011 0010 01 ... ...            @extend
 186 UXTAH           1011 0010 10 ... ...            @extend
 187 UXTAB           1011 0010 11 ... ...            @extend
 188
 189 # Change processor state
 190
 191 %imod           4:1 !function=plus_2
 192
 193 SETEND          1011 0110 010 1 E:1 000         &setend
 194 {
 195   CPS           1011 0110 011 . 0 A:1 I:1 F:1   &cps mode=0 M=0 %imod
 196   CPS_v7m       1011 0110 011 im:1 00 I:1 F:1
 197 }