target/arm/t16.decode

   1 # Thumb1 instructions
   2 #
   3 #  Copyright (c) 2019 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21
  22 &s_rrr_shi       !extern s rd rn rm shim shty
  23 &s_rrr_shr       !extern s rn rd rm rs shty
  24 &s_rri_rot       !extern s rn rd imm rot
  25 &s_rrrr          !extern s rd rn rm ra
  26 &ri              !extern rd imm
  27 &ldst_rr         !extern p w u rn rt rm shimm shtype
  28 &ldst_ri         !extern p w u rn rt imm
  29 &ldst_block      !extern rn i b u w list
  30
  31 # Set S if the instruction is outside of an IT block.
  32 %s               !function=t16_setflags
  33
  34 # Data-processing (two low registers)
  35
  36 %reg_0           0:3
  37
  38 @lll_noshr       ...... .... rm:3 rd:3 \
  39                  &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
  40 @xll_noshr       ...... .... rm:3 rn:3 \
  41                  &s_rrr_shi s=1 rd=0 shim=0 shty=0
  42 @lxl_shr         ...... .... rs:3 rd:3 \
  43                  &s_rrr_shr %s rm=%reg_0 rn=0
  44
  45 AND_rrri         010000 0000 ... ...            @lll_noshr
  46 EOR_rrri         010000 0001 ... ...            @lll_noshr
  47 MOV_rxrr         010000 0010 ... ...            @lxl_shr shty=0  # LSL
  48 MOV_rxrr         010000 0011 ... ...            @lxl_shr shty=1  # LSR
  49 MOV_rxrr         010000 0100 ... ...            @lxl_shr shty=2  # ASR
  50 ADC_rrri         010000 0101 ... ...            @lll_noshr
  51 SBC_rrri         010000 0110 ... ...            @lll_noshr
  52 MOV_rxrr         010000 0111 ... ...            @lxl_shr shty=3  # ROR
  53 TST_xrri         010000 1000 ... ...            @xll_noshr
  54 RSB_rri          010000 1001 rn:3 rd:3          &s_rri_rot %s imm=0 rot=0
  55 CMP_xrri         010000 1010 ... ...            @xll_noshr
  56 CMN_xrri         010000 1011 ... ...            @xll_noshr
  57 ORR_rrri         010000 1100 ... ...            @lll_noshr
  58 MUL              010000 1101 rn:3 rd:3          &s_rrrr %s rm=%reg_0 ra=0
  59 BIC_rrri         010000 1110 ... ...            @lll_noshr
  60 MVN_rxri         010000 1111 ... ...            @lll_noshr
  61
  62 # Load/store (register offset)
  63
  64 @ldst_rr         ....... rm:3 rn:3 rt:3 \
  65                  &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
  66
  67 STR_rr           0101 000 ... ... ...           @ldst_rr
  68 STRH_rr          0101 001 ... ... ...           @ldst_rr
  69 STRB_rr          0101 010 ... ... ...           @ldst_rr
  70 LDRSB_rr         0101 011 ... ... ...           @ldst_rr
  71 LDR_rr           0101 100 ... ... ...           @ldst_rr
  72 LDRH_rr          0101 101 ... ... ...           @ldst_rr
  73 LDRB_rr          0101 110 ... ... ...           @ldst_rr
  74 LDRSH_rr         0101 111 ... ... ...           @ldst_rr
  75
  76 # Load/store word/byte (immediate offset)
  77
  78 %imm5_6x4       6:5 !function=times_4
  79
  80 @ldst_ri_1      ..... imm:5 rn:3 rt:3 \
  81                 &ldst_ri p=1 w=0 u=1
  82 @ldst_ri_4      ..... ..... rn:3 rt:3 \
  83                 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
  84
  85 STR_ri          01100 ..... ... ...             @ldst_ri_4
  86 LDR_ri          01101 ..... ... ...             @ldst_ri_4
  87 STRB_ri         01110 ..... ... ...             @ldst_ri_1
  88 LDRB_ri         01111 ..... ... ...             @ldst_ri_1
  89
  90 # Load/store halfword (immediate offset)
  91
  92 %imm5_6x2       6:5 !function=times_2
  93 @ldst_ri_2      ..... ..... rn:3 rt:3 \
  94                 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
  95
  96 STRH_ri         10000 ..... ... ...             @ldst_ri_2
  97 LDRH_ri         10001 ..... ... ...             @ldst_ri_2
  98
  99 # Load/store (SP-relative)
 100
 101 %imm8_0x4       0:8 !function=times_4
 102 @ldst_spec_i    ..... rt:3 ........ \
 103                 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
 104
 105 STR_ri          10010 ... ........              @ldst_spec_i rn=13
 106 LDR_ri          10011 ... ........              @ldst_spec_i rn=13
 107
 108 # Add PC/SP (immediate)
 109
 110 ADR             10100 rd:3 ........             imm=%imm8_0x4
 111 ADD_rri         10101 rd:3 ........ \
 112                 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4  # SP
 113
 114 # Load/store multiple
 115
 116 @ldstm          ..... rn:3 list:8               &ldst_block i=1 b=0 u=0 w=1
 117
 118 STM             11000 ... ........              @ldstm
 119 LDM_t16         11001 ... ........              @ldstm
 120
 121 # Add/subtract (three low registers)
 122
 123 @addsub_3       ....... rm:3 rn:3 rd:3 \
 124                 &s_rrr_shi %s shim=0 shty=0
 125
 126 ADD_rrri        0001100 ... ... ...             @addsub_3
 127 SUB_rrri        0001101 ... ... ...             @addsub_3
 128
 129 # Add/subtract (two low registers and immediate)
 130
 131 @addsub_2i      ....... imm:3 rn:3 rd:3 \
 132                 &s_rri_rot %s rot=0
 133
 134 ADD_rri         0001 110 ... ... ...            @addsub_2i
 135 SUB_rri         0001 111 ... ... ...            @addsub_2i
 136
 137 # Add, subtract, compare, move (one low register and immediate)
 138
 139 %reg_8          8:3
 140 @arith_1i       ..... rd:3 imm:8 \
 141                 &s_rri_rot rot=0 rn=%reg_8
 142
 143 MOV_rxi         00100 ... ........              @arith_1i %s
 144 CMP_xri         00101 ... ........              @arith_1i s=1
 145 ADD_rri         00110 ... ........              @arith_1i %s
 146 SUB_rri         00111 ... ........              @arith_1i %s