target/arm/t16.decode

   1 # Thumb1 instructions
   2 #
   3 #  Copyright (c) 2019 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21
  22 &s_rrr_shi       !extern s rd rn rm shim shty
  23 &s_rrr_shr       !extern s rn rd rm rs shty
  24 &s_rri_rot       !extern s rn rd imm rot
  25 &s_rrrr          !extern s rd rn rm ra
  26 &ri              !extern rd imm
  27 &ldst_rr         !extern p w u rn rt rm shimm shtype
  28 &ldst_ri         !extern p w u rn rt imm
  29
  30 # Set S if the instruction is outside of an IT block.
  31 %s               !function=t16_setflags
  32
  33 # Data-processing (two low registers)
  34
  35 %reg_0           0:3
  36
  37 @lll_noshr       ...... .... rm:3 rd:3 \
  38                  &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
  39 @xll_noshr       ...... .... rm:3 rn:3 \
  40                  &s_rrr_shi s=1 rd=0 shim=0 shty=0
  41 @lxl_shr         ...... .... rs:3 rd:3 \
  42                  &s_rrr_shr %s rm=%reg_0 rn=0
  43
  44 AND_rrri         010000 0000 ... ...            @lll_noshr
  45 EOR_rrri         010000 0001 ... ...            @lll_noshr
  46 MOV_rxrr         010000 0010 ... ...            @lxl_shr shty=0  # LSL
  47 MOV_rxrr         010000 0011 ... ...            @lxl_shr shty=1  # LSR
  48 MOV_rxrr         010000 0100 ... ...            @lxl_shr shty=2  # ASR
  49 ADC_rrri         010000 0101 ... ...            @lll_noshr
  50 SBC_rrri         010000 0110 ... ...            @lll_noshr
  51 MOV_rxrr         010000 0111 ... ...            @lxl_shr shty=3  # ROR
  52 TST_xrri         010000 1000 ... ...            @xll_noshr
  53 RSB_rri          010000 1001 rn:3 rd:3          &s_rri_rot %s imm=0 rot=0
  54 CMP_xrri         010000 1010 ... ...            @xll_noshr
  55 CMN_xrri         010000 1011 ... ...            @xll_noshr
  56 ORR_rrri         010000 1100 ... ...            @lll_noshr
  57 MUL              010000 1101 rn:3 rd:3          &s_rrrr %s rm=%reg_0 ra=0
  58 BIC_rrri         010000 1110 ... ...            @lll_noshr
  59 MVN_rxri         010000 1111 ... ...            @lll_noshr
  60
  61 # Load/store (register offset)
  62
  63 @ldst_rr         ....... rm:3 rn:3 rt:3 \
  64                  &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
  65
  66 STR_rr           0101 000 ... ... ...           @ldst_rr
  67 STRH_rr          0101 001 ... ... ...           @ldst_rr
  68 STRB_rr          0101 010 ... ... ...           @ldst_rr
  69 LDRSB_rr         0101 011 ... ... ...           @ldst_rr
  70 LDR_rr           0101 100 ... ... ...           @ldst_rr
  71 LDRH_rr          0101 101 ... ... ...           @ldst_rr
  72 LDRB_rr          0101 110 ... ... ...           @ldst_rr
  73 LDRSH_rr         0101 111 ... ... ...           @ldst_rr
  74
  75 # Load/store word/byte (immediate offset)
  76
  77 %imm5_6x4       6:5 !function=times_4
  78
  79 @ldst_ri_1      ..... imm:5 rn:3 rt:3 \
  80                 &ldst_ri p=1 w=0 u=1
  81 @ldst_ri_4      ..... ..... rn:3 rt:3 \
  82                 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
  83
  84 STR_ri          01100 ..... ... ...             @ldst_ri_4
  85 LDR_ri          01101 ..... ... ...             @ldst_ri_4
  86 STRB_ri         01110 ..... ... ...             @ldst_ri_1
  87 LDRB_ri         01111 ..... ... ...             @ldst_ri_1
  88
  89 # Load/store halfword (immediate offset)
  90
  91 %imm5_6x2       6:5 !function=times_2
  92 @ldst_ri_2      ..... ..... rn:3 rt:3 \
  93                 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
  94
  95 STRH_ri         10000 ..... ... ...             @ldst_ri_2
  96 LDRH_ri         10001 ..... ... ...             @ldst_ri_2
  97
  98 # Load/store (SP-relative)
  99
 100 %imm8_0x4       0:8 !function=times_4
 101 @ldst_spec_i    ..... rt:3 ........ \
 102                 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
 103
 104 STR_ri          10010 ... ........              @ldst_spec_i rn=13
 105 LDR_ri          10011 ... ........              @ldst_spec_i rn=13
 106
 107 # Add PC/SP (immediate)
 108
 109 ADR             10100 rd:3 ........             imm=%imm8_0x4
 110 ADD_rri         10101 rd:3 ........ \
 111                 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4  # SP