4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
30 #include "semihosting/semihost.h"
31 #include "exec/gen-icount.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
36 #include "translate-a64.h"
37 #include "qemu/atomic128.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
45 static const char *regnames
[] = {
46 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
47 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
48 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
49 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
53 A64_SHIFT_TYPE_LSL
= 0,
54 A64_SHIFT_TYPE_LSR
= 1,
55 A64_SHIFT_TYPE_ASR
= 2,
56 A64_SHIFT_TYPE_ROR
= 3
59 /* Table based decoder typedefs - used when the relevant bits for decode
60 * are too awkwardly scattered across the instruction (eg SIMD).
62 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
64 typedef struct AArch64DecodeTable
{
67 AArch64DecodeFn
*disas_fn
;
70 /* initialize TCG globals. */
71 void a64_translate_init(void)
75 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
76 offsetof(CPUARMState
, pc
),
78 for (i
= 0; i
< 32; i
++) {
79 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
80 offsetof(CPUARMState
, xregs
[i
]),
84 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
85 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
89 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
91 static int get_a64_user_mem_index(DisasContext
*s
)
94 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
95 * which is the usual mmu_idx for this cpu state.
97 ARMMMUIdx useridx
= s
->mmu_idx
;
101 * We have pre-computed the condition for AccType_UNPRIV.
102 * Therefore we should never get here with a mmu_idx for
103 * which we do not know the corresponding user mmu_idx.
106 case ARMMMUIdx_E10_1
:
107 case ARMMMUIdx_E10_1_PAN
:
108 useridx
= ARMMMUIdx_E10_0
;
110 case ARMMMUIdx_E20_2
:
111 case ARMMMUIdx_E20_2_PAN
:
112 useridx
= ARMMMUIdx_E20_0
;
115 g_assert_not_reached();
118 return arm_to_core_mmu_idx(useridx
);
121 static void set_btype_raw(int val
)
123 tcg_gen_st_i32(tcg_constant_i32(val
), cpu_env
,
124 offsetof(CPUARMState
, btype
));
127 static void set_btype(DisasContext
*s
, int val
)
129 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
130 tcg_debug_assert(val
>= 1 && val
<= 3);
135 static void reset_btype(DisasContext
*s
)
143 static void gen_pc_plus_diff(DisasContext
*s
, TCGv_i64 dest
, target_long diff
)
145 assert(s
->pc_save
!= -1);
146 if (tb_cflags(s
->base
.tb
) & CF_PCREL
) {
147 tcg_gen_addi_i64(dest
, cpu_pc
, (s
->pc_curr
- s
->pc_save
) + diff
);
149 tcg_gen_movi_i64(dest
, s
->pc_curr
+ diff
);
153 void gen_a64_update_pc(DisasContext
*s
, target_long diff
)
155 gen_pc_plus_diff(s
, cpu_pc
, diff
);
156 s
->pc_save
= s
->pc_curr
+ diff
;
160 * Handle Top Byte Ignore (TBI) bits.
162 * If address tagging is enabled via the TCR TBI bits:
163 * + for EL2 and EL3 there is only one TBI bit, and if it is set
164 * then the address is zero-extended, clearing bits [63:56]
165 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
166 * and TBI1 controls addressses with bit 55 == 1.
167 * If the appropriate TBI bit is set for the address then
168 * the address is sign-extended from bit 55 into bits [63:56]
170 * Here We have concatenated TBI{1,0} into tbi.
172 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
173 TCGv_i64 src
, int tbi
)
176 /* Load unmodified address */
177 tcg_gen_mov_i64(dst
, src
);
178 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
179 /* Force tag byte to all zero */
180 tcg_gen_extract_i64(dst
, src
, 0, 56);
182 /* Sign-extend from bit 55. */
183 tcg_gen_sextract_i64(dst
, src
, 0, 56);
187 /* tbi0 but !tbi1: only use the extension if positive */
188 tcg_gen_and_i64(dst
, dst
, src
);
191 /* !tbi0 but tbi1: only use the extension if negative */
192 tcg_gen_or_i64(dst
, dst
, src
);
195 /* tbi0 and tbi1: always use the extension */
198 g_assert_not_reached();
203 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
206 * If address tagging is enabled for instructions via the TCR TBI bits,
207 * then loading an address into the PC will clear out any tag.
209 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
214 * Handle MTE and/or TBI.
216 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
217 * for the tag to be present in the FAR_ELx register. But for user-only
218 * mode we do not have a TLB with which to implement this, so we must
219 * remove the top byte now.
221 * Always return a fresh temporary that we can increment independently
222 * of the write-back address.
225 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
227 TCGv_i64 clean
= tcg_temp_new_i64();
228 #ifdef CONFIG_USER_ONLY
229 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
231 tcg_gen_mov_i64(clean
, addr
);
236 /* Insert a zero tag into src, with the result at dst. */
237 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
239 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
242 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
243 MMUAccessType acc
, int log2_size
)
245 gen_helper_probe_access(cpu_env
, ptr
,
246 tcg_constant_i32(acc
),
247 tcg_constant_i32(get_mem_index(s
)),
248 tcg_constant_i32(1 << log2_size
));
252 * For MTE, check a single logical or atomic access. This probes a single
253 * address, the exact one specified. The size and alignment of the access
254 * is not relevant to MTE, per se, but watchpoints do require the size,
255 * and we want to recognize those before making any other changes to state.
257 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
258 bool is_write
, bool tag_checked
,
259 int log2_size
, bool is_unpriv
,
262 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
266 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
267 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
268 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
269 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
270 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
272 ret
= tcg_temp_new_i64();
273 gen_helper_mte_check(ret
, cpu_env
, tcg_constant_i32(desc
), addr
);
277 return clean_data_tbi(s
, addr
);
280 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
281 bool tag_checked
, int log2_size
)
283 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
284 false, get_mem_index(s
));
288 * For MTE, check multiple logical sequential accesses.
290 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
291 bool tag_checked
, int size
)
293 if (tag_checked
&& s
->mte_active
[0]) {
297 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
298 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
299 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
300 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
301 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
303 ret
= tcg_temp_new_i64();
304 gen_helper_mte_check(ret
, cpu_env
, tcg_constant_i32(desc
), addr
);
308 return clean_data_tbi(s
, addr
);
311 typedef struct DisasCompare64
{
316 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
320 arm_test_cc(&c32
, cc
);
323 * Sign-extend the 32-bit value so that the GE/LT comparisons work
324 * properly. The NE/EQ comparisons are also fine with this choice.
326 c64
->cond
= c32
.cond
;
327 c64
->value
= tcg_temp_new_i64();
328 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
331 static void gen_rebuild_hflags(DisasContext
*s
)
333 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_constant_i32(s
->current_el
));
336 static void gen_exception_internal(int excp
)
338 assert(excp_is_internal(excp
));
339 gen_helper_exception_internal(cpu_env
, tcg_constant_i32(excp
));
342 static void gen_exception_internal_insn(DisasContext
*s
, int excp
)
344 gen_a64_update_pc(s
, 0);
345 gen_exception_internal(excp
);
346 s
->base
.is_jmp
= DISAS_NORETURN
;
349 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
351 gen_a64_update_pc(s
, 0);
352 gen_helper_exception_bkpt_insn(cpu_env
, tcg_constant_i32(syndrome
));
353 s
->base
.is_jmp
= DISAS_NORETURN
;
356 static void gen_step_complete_exception(DisasContext
*s
)
358 /* We just completed step of an insn. Move from Active-not-pending
359 * to Active-pending, and then also take the swstep exception.
360 * This corresponds to making the (IMPDEF) choice to prioritize
361 * swstep exceptions over asynchronous exceptions taken to an exception
362 * level where debug is disabled. This choice has the advantage that
363 * we do not need to maintain internal state corresponding to the
364 * ISV/EX syndrome bits between completion of the step and generation
365 * of the exception, and our syndrome information is always correct.
368 gen_swstep_exception(s
, 1, s
->is_ldex
);
369 s
->base
.is_jmp
= DISAS_NORETURN
;
372 static inline bool use_goto_tb(DisasContext
*s
, uint64_t dest
)
377 return translator_use_goto_tb(&s
->base
, dest
);
380 static void gen_goto_tb(DisasContext
*s
, int n
, int64_t diff
)
382 if (use_goto_tb(s
, s
->pc_curr
+ diff
)) {
384 * For pcrel, the pc must always be up-to-date on entry to
385 * the linked TB, so that it can use simple additions for all
386 * further adjustments. For !pcrel, the linked TB is compiled
387 * to know its full virtual address, so we can delay the
388 * update to pc to the unlinked path. A long chain of links
389 * can thus avoid many updates to the PC.
391 if (tb_cflags(s
->base
.tb
) & CF_PCREL
) {
392 gen_a64_update_pc(s
, diff
);
396 gen_a64_update_pc(s
, diff
);
398 tcg_gen_exit_tb(s
->base
.tb
, n
);
399 s
->base
.is_jmp
= DISAS_NORETURN
;
401 gen_a64_update_pc(s
, diff
);
403 gen_step_complete_exception(s
);
405 tcg_gen_lookup_and_goto_ptr();
406 s
->base
.is_jmp
= DISAS_NORETURN
;
412 * Register access functions
414 * These functions are used for directly accessing a register in where
415 * changes to the final register value are likely to be made. If you
416 * need to use a register for temporary calculation (e.g. index type
417 * operations) use the read_* form.
419 * B1.2.1 Register mappings
421 * In instruction register encoding 31 can refer to ZR (zero register) or
422 * the SP (stack pointer) depending on context. In QEMU's case we map SP
423 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
424 * This is the point of the _sp forms.
426 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
429 TCGv_i64 t
= tcg_temp_new_i64();
430 tcg_gen_movi_i64(t
, 0);
437 /* register access for when 31 == SP */
438 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
443 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
444 * representing the register contents. This TCGv is an auto-freed
445 * temporary so it need not be explicitly freed, and may be modified.
447 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
449 TCGv_i64 v
= tcg_temp_new_i64();
452 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
454 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
457 tcg_gen_movi_i64(v
, 0);
462 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
464 TCGv_i64 v
= tcg_temp_new_i64();
466 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
468 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
473 /* Return the offset into CPUARMState of a slice (from
474 * the least significant end) of FP register Qn (ie
476 * (Note that this is not the same mapping as for A32; see cpu.h)
478 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
480 return vec_reg_offset(s
, regno
, 0, size
);
483 /* Offset of the high half of the 128 bit vector Qn */
484 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
486 return vec_reg_offset(s
, regno
, 1, MO_64
);
489 /* Convenience accessors for reading and writing single and double
490 * FP registers. Writing clears the upper parts of the associated
491 * 128 bit vector register, as required by the architecture.
492 * Note that unlike the GP register accessors, the values returned
493 * by the read functions must be manually freed.
495 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
497 TCGv_i64 v
= tcg_temp_new_i64();
499 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
503 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
505 TCGv_i32 v
= tcg_temp_new_i32();
507 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
511 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
513 TCGv_i32 v
= tcg_temp_new_i32();
515 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
519 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
520 * If SVE is not enabled, then there are only 128 bits in the vector.
522 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
524 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
525 unsigned vsz
= vec_full_reg_size(s
);
527 /* Nop move, with side effect of clearing the tail. */
528 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
531 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
533 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
535 tcg_gen_st_i64(v
, cpu_env
, ofs
);
536 clear_vec_high(s
, false, reg
);
539 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
541 TCGv_i64 tmp
= tcg_temp_new_i64();
543 tcg_gen_extu_i32_i64(tmp
, v
);
544 write_fp_dreg(s
, reg
, tmp
);
547 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
548 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
549 GVecGen2Fn
*gvec_fn
, int vece
)
551 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
552 is_q
? 16 : 8, vec_full_reg_size(s
));
555 /* Expand a 2-operand + immediate AdvSIMD vector operation using
556 * an expander function.
558 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
559 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
561 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
562 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
565 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
566 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
567 GVecGen3Fn
*gvec_fn
, int vece
)
569 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
570 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
573 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
574 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
575 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
577 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
578 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
579 is_q
? 16 : 8, vec_full_reg_size(s
));
582 /* Expand a 2-operand operation using an out-of-line helper. */
583 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
584 int rn
, int data
, gen_helper_gvec_2
*fn
)
586 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
587 vec_full_reg_offset(s
, rn
),
588 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
591 /* Expand a 3-operand operation using an out-of-line helper. */
592 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
593 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
595 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
596 vec_full_reg_offset(s
, rn
),
597 vec_full_reg_offset(s
, rm
),
598 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
601 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
602 * an out-of-line helper.
604 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
605 int rm
, bool is_fp16
, int data
,
606 gen_helper_gvec_3_ptr
*fn
)
608 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
609 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
610 vec_full_reg_offset(s
, rn
),
611 vec_full_reg_offset(s
, rm
), fpst
,
612 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
615 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
616 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
617 int rm
, gen_helper_gvec_3_ptr
*fn
)
619 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
621 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
622 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
623 vec_full_reg_offset(s
, rn
),
624 vec_full_reg_offset(s
, rm
), qc_ptr
,
625 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
628 /* Expand a 4-operand operation using an out-of-line helper. */
629 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
630 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
632 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
633 vec_full_reg_offset(s
, rn
),
634 vec_full_reg_offset(s
, rm
),
635 vec_full_reg_offset(s
, ra
),
636 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
640 * Expand a 4-operand + fpstatus pointer + simd data value operation using
641 * an out-of-line helper.
643 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
644 int rm
, int ra
, bool is_fp16
, int data
,
645 gen_helper_gvec_4_ptr
*fn
)
647 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
648 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
649 vec_full_reg_offset(s
, rn
),
650 vec_full_reg_offset(s
, rm
),
651 vec_full_reg_offset(s
, ra
), fpst
,
652 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
655 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
656 * than the 32 bit equivalent.
658 static inline void gen_set_NZ64(TCGv_i64 result
)
660 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
661 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
664 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
665 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
668 gen_set_NZ64(result
);
670 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
671 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
673 tcg_gen_movi_i32(cpu_CF
, 0);
674 tcg_gen_movi_i32(cpu_VF
, 0);
677 /* dest = T0 + T1; compute C, N, V and Z flags */
678 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
681 TCGv_i64 result
, flag
, tmp
;
682 result
= tcg_temp_new_i64();
683 flag
= tcg_temp_new_i64();
684 tmp
= tcg_temp_new_i64();
686 tcg_gen_movi_i64(tmp
, 0);
687 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
689 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
691 gen_set_NZ64(result
);
693 tcg_gen_xor_i64(flag
, result
, t0
);
694 tcg_gen_xor_i64(tmp
, t0
, t1
);
695 tcg_gen_andc_i64(flag
, flag
, tmp
);
696 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
698 tcg_gen_mov_i64(dest
, result
);
700 /* 32 bit arithmetic */
701 TCGv_i32 t0_32
= tcg_temp_new_i32();
702 TCGv_i32 t1_32
= tcg_temp_new_i32();
703 TCGv_i32 tmp
= tcg_temp_new_i32();
705 tcg_gen_movi_i32(tmp
, 0);
706 tcg_gen_extrl_i64_i32(t0_32
, t0
);
707 tcg_gen_extrl_i64_i32(t1_32
, t1
);
708 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
709 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
710 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
711 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
712 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
713 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
717 /* dest = T0 - T1; compute C, N, V and Z flags */
718 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
721 /* 64 bit arithmetic */
722 TCGv_i64 result
, flag
, tmp
;
724 result
= tcg_temp_new_i64();
725 flag
= tcg_temp_new_i64();
726 tcg_gen_sub_i64(result
, t0
, t1
);
728 gen_set_NZ64(result
);
730 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
731 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
733 tcg_gen_xor_i64(flag
, result
, t0
);
734 tmp
= tcg_temp_new_i64();
735 tcg_gen_xor_i64(tmp
, t0
, t1
);
736 tcg_gen_and_i64(flag
, flag
, tmp
);
737 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
738 tcg_gen_mov_i64(dest
, result
);
740 /* 32 bit arithmetic */
741 TCGv_i32 t0_32
= tcg_temp_new_i32();
742 TCGv_i32 t1_32
= tcg_temp_new_i32();
745 tcg_gen_extrl_i64_i32(t0_32
, t0
);
746 tcg_gen_extrl_i64_i32(t1_32
, t1
);
747 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
748 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
749 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
750 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
751 tmp
= tcg_temp_new_i32();
752 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
753 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
754 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
758 /* dest = T0 + T1 + CF; do not compute flags. */
759 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
761 TCGv_i64 flag
= tcg_temp_new_i64();
762 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
763 tcg_gen_add_i64(dest
, t0
, t1
);
764 tcg_gen_add_i64(dest
, dest
, flag
);
767 tcg_gen_ext32u_i64(dest
, dest
);
771 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
772 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
775 TCGv_i64 result
= tcg_temp_new_i64();
776 TCGv_i64 cf_64
= tcg_temp_new_i64();
777 TCGv_i64 vf_64
= tcg_temp_new_i64();
778 TCGv_i64 tmp
= tcg_temp_new_i64();
779 TCGv_i64 zero
= tcg_constant_i64(0);
781 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
782 tcg_gen_add2_i64(result
, cf_64
, t0
, zero
, cf_64
, zero
);
783 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, zero
);
784 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
785 gen_set_NZ64(result
);
787 tcg_gen_xor_i64(vf_64
, result
, t0
);
788 tcg_gen_xor_i64(tmp
, t0
, t1
);
789 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
790 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
792 tcg_gen_mov_i64(dest
, result
);
794 TCGv_i32 t0_32
= tcg_temp_new_i32();
795 TCGv_i32 t1_32
= tcg_temp_new_i32();
796 TCGv_i32 tmp
= tcg_temp_new_i32();
797 TCGv_i32 zero
= tcg_constant_i32(0);
799 tcg_gen_extrl_i64_i32(t0_32
, t0
);
800 tcg_gen_extrl_i64_i32(t1_32
, t1
);
801 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, zero
, cpu_CF
, zero
);
802 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, zero
);
804 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
805 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
806 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
807 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
808 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
813 * Load/Store generators
817 * Store from GPR register to memory.
819 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
820 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
822 unsigned int iss_srt
,
823 bool iss_sf
, bool iss_ar
)
825 memop
= finalize_memop(s
, memop
);
826 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
831 syn
= syn_data_abort_with_iss(0,
837 0, 0, 0, 0, 0, false);
838 disas_set_insn_syndrome(s
, syn
);
842 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
843 TCGv_i64 tcg_addr
, MemOp memop
,
845 unsigned int iss_srt
,
846 bool iss_sf
, bool iss_ar
)
848 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
849 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
853 * Load from memory to GPR register
855 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
856 MemOp memop
, bool extend
, int memidx
,
857 bool iss_valid
, unsigned int iss_srt
,
858 bool iss_sf
, bool iss_ar
)
860 memop
= finalize_memop(s
, memop
);
861 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
863 if (extend
&& (memop
& MO_SIGN
)) {
864 g_assert((memop
& MO_SIZE
) <= MO_32
);
865 tcg_gen_ext32u_i64(dest
, dest
);
871 syn
= syn_data_abort_with_iss(0,
873 (memop
& MO_SIGN
) != 0,
877 0, 0, 0, 0, 0, false);
878 disas_set_insn_syndrome(s
, syn
);
882 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
883 MemOp memop
, bool extend
,
884 bool iss_valid
, unsigned int iss_srt
,
885 bool iss_sf
, bool iss_ar
)
887 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
888 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
892 * Store from FP register to memory
894 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
896 /* This writes the bottom N bits of a 128 bit wide vector to memory */
897 TCGv_i64 tmplo
= tcg_temp_new_i64();
900 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
903 mop
= finalize_memop(s
, size
);
904 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
906 bool be
= s
->be_data
== MO_BE
;
907 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
908 TCGv_i64 tmphi
= tcg_temp_new_i64();
910 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
912 mop
= s
->be_data
| MO_UQ
;
913 tcg_gen_qemu_st_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
914 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
915 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
916 tcg_gen_qemu_st_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
917 get_mem_index(s
), mop
);
922 * Load from memory to FP register
924 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
926 /* This always zero-extends and writes to a full 128 bit wide vector */
927 TCGv_i64 tmplo
= tcg_temp_new_i64();
928 TCGv_i64 tmphi
= NULL
;
932 mop
= finalize_memop(s
, size
);
933 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
935 bool be
= s
->be_data
== MO_BE
;
938 tmphi
= tcg_temp_new_i64();
939 tcg_hiaddr
= tcg_temp_new_i64();
941 mop
= s
->be_data
| MO_UQ
;
942 tcg_gen_qemu_ld_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
943 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
944 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
945 tcg_gen_qemu_ld_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
946 get_mem_index(s
), mop
);
949 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
952 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
954 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
958 * Vector load/store helpers.
960 * The principal difference between this and a FP load is that we don't
961 * zero extend as we are filling a partial chunk of the vector register.
962 * These functions don't support 128 bit loads/stores, which would be
963 * normal load/store operations.
965 * The _i32 versions are useful when operating on 32 bit quantities
966 * (eg for floating point single or using Neon helper functions).
969 /* Get value of an element within a vector register */
970 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
971 int element
, MemOp memop
)
973 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
974 switch ((unsigned)memop
) {
976 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
979 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
985 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
988 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
991 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
995 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
998 g_assert_not_reached();
1002 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1003 int element
, MemOp memop
)
1005 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1008 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1011 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1014 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1017 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1021 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1024 g_assert_not_reached();
1028 /* Set value of an element within a vector register */
1029 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1030 int element
, MemOp memop
)
1032 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1035 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1038 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1041 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1044 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1047 g_assert_not_reached();
1051 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1052 int destidx
, int element
, MemOp memop
)
1054 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1057 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1060 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1063 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1066 g_assert_not_reached();
1070 /* Store from vector register to memory */
1071 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1072 TCGv_i64 tcg_addr
, MemOp mop
)
1074 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1076 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1077 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1080 /* Load from memory to vector register */
1081 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1082 TCGv_i64 tcg_addr
, MemOp mop
)
1084 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1086 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1087 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1090 /* Check that FP/Neon access is enabled. If it is, return
1091 * true. If not, emit code to generate an appropriate exception,
1092 * and return false; the caller should not emit any code for
1093 * the instruction. Note that this check must happen after all
1094 * unallocated-encoding checks (otherwise the syndrome information
1095 * for the resulting exception will be incorrect).
1097 static bool fp_access_check_only(DisasContext
*s
)
1099 if (s
->fp_excp_el
) {
1100 assert(!s
->fp_access_checked
);
1101 s
->fp_access_checked
= true;
1103 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1104 syn_fp_access_trap(1, 0xe, false, 0),
1108 s
->fp_access_checked
= true;
1112 static bool fp_access_check(DisasContext
*s
)
1114 if (!fp_access_check_only(s
)) {
1117 if (s
->sme_trap_nonstreaming
&& s
->is_nonstreaming
) {
1118 gen_exception_insn(s
, 0, EXCP_UDEF
,
1119 syn_smetrap(SME_ET_Streaming
, false));
1126 * Check that SVE access is enabled. If it is, return true.
1127 * If not, emit code to generate an appropriate exception and return false.
1128 * This function corresponds to CheckSVEEnabled().
1130 bool sve_access_check(DisasContext
*s
)
1132 if (s
->pstate_sm
|| !dc_isar_feature(aa64_sve
, s
)) {
1133 assert(dc_isar_feature(aa64_sme
, s
));
1134 if (!sme_sm_enabled_check(s
)) {
1137 } else if (s
->sve_excp_el
) {
1138 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1139 syn_sve_access_trap(), s
->sve_excp_el
);
1142 s
->sve_access_checked
= true;
1143 return fp_access_check(s
);
1146 /* Assert that we only raise one exception per instruction. */
1147 assert(!s
->sve_access_checked
);
1148 s
->sve_access_checked
= true;
1153 * Check that SME access is enabled, raise an exception if not.
1154 * Note that this function corresponds to CheckSMEAccess and is
1155 * only used directly for cpregs.
1157 static bool sme_access_check(DisasContext
*s
)
1159 if (s
->sme_excp_el
) {
1160 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1161 syn_smetrap(SME_ET_AccessTrap
, false),
1168 /* This function corresponds to CheckSMEEnabled. */
1169 bool sme_enabled_check(DisasContext
*s
)
1172 * Note that unlike sve_excp_el, we have not constrained sme_excp_el
1173 * to be zero when fp_excp_el has priority. This is because we need
1174 * sme_excp_el by itself for cpregs access checks.
1176 if (!s
->fp_excp_el
|| s
->sme_excp_el
< s
->fp_excp_el
) {
1177 s
->fp_access_checked
= true;
1178 return sme_access_check(s
);
1180 return fp_access_check_only(s
);
1183 /* Common subroutine for CheckSMEAnd*Enabled. */
1184 bool sme_enabled_check_with_svcr(DisasContext
*s
, unsigned req
)
1186 if (!sme_enabled_check(s
)) {
1189 if (FIELD_EX64(req
, SVCR
, SM
) && !s
->pstate_sm
) {
1190 gen_exception_insn(s
, 0, EXCP_UDEF
,
1191 syn_smetrap(SME_ET_NotStreaming
, false));
1194 if (FIELD_EX64(req
, SVCR
, ZA
) && !s
->pstate_za
) {
1195 gen_exception_insn(s
, 0, EXCP_UDEF
,
1196 syn_smetrap(SME_ET_InactiveZA
, false));
1203 * This utility function is for doing register extension with an
1204 * optional shift. You will likely want to pass a temporary for the
1205 * destination register. See DecodeRegExtend() in the ARM ARM.
1207 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1208 int option
, unsigned int shift
)
1210 int extsize
= extract32(option
, 0, 2);
1211 bool is_signed
= extract32(option
, 2, 1);
1216 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1219 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1222 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1225 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1231 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1234 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1237 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1240 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1246 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1250 static inline void gen_check_sp_alignment(DisasContext
*s
)
1252 /* The AArch64 architecture mandates that (if enabled via PSTATE
1253 * or SCTLR bits) there is a check that SP is 16-aligned on every
1254 * SP-relative load or store (with an exception generated if it is not).
1255 * In line with general QEMU practice regarding misaligned accesses,
1256 * we omit these checks for the sake of guest program performance.
1257 * This function is provided as a hook so we can more easily add these
1258 * checks in future (possibly as a "favour catching guest program bugs
1259 * over speed" user selectable option).
1264 * This provides a simple table based table lookup decoder. It is
1265 * intended to be used when the relevant bits for decode are too
1266 * awkwardly placed and switch/if based logic would be confusing and
1267 * deeply nested. Since it's a linear search through the table, tables
1268 * should be kept small.
1270 * It returns the first handler where insn & mask == pattern, or
1271 * NULL if there is no match.
1272 * The table is terminated by an empty mask (i.e. 0)
1274 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1277 const AArch64DecodeTable
*tptr
= table
;
1279 while (tptr
->mask
) {
1280 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1281 return tptr
->disas_fn
;
1289 * The instruction disassembly implemented here matches
1290 * the instruction encoding classifications in chapter C4
1291 * of the ARM Architecture Reference Manual (DDI0487B_a);
1292 * classification names and decode diagrams here should generally
1293 * match up with those in the manual.
1296 /* Unconditional branch (immediate)
1298 * +----+-----------+-------------------------------------+
1299 * | op | 0 0 1 0 1 | imm26 |
1300 * +----+-----------+-------------------------------------+
1302 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1304 int64_t diff
= sextract32(insn
, 0, 26) * 4;
1306 if (insn
& (1U << 31)) {
1307 /* BL Branch with link */
1308 gen_pc_plus_diff(s
, cpu_reg(s
, 30), curr_insn_len(s
));
1311 /* B Branch / BL Branch with link */
1313 gen_goto_tb(s
, 0, diff
);
1316 /* Compare and branch (immediate)
1317 * 31 30 25 24 23 5 4 0
1318 * +----+-------------+----+---------------------+--------+
1319 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1320 * +----+-------------+----+---------------------+--------+
1322 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1324 unsigned int sf
, op
, rt
;
1329 sf
= extract32(insn
, 31, 1);
1330 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1331 rt
= extract32(insn
, 0, 5);
1332 diff
= sextract32(insn
, 5, 19) * 4;
1334 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1337 match
= gen_disas_label(s
);
1338 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1339 tcg_cmp
, 0, match
.label
);
1340 gen_goto_tb(s
, 0, 4);
1341 set_disas_label(s
, match
);
1342 gen_goto_tb(s
, 1, diff
);
1345 /* Test and branch (immediate)
1346 * 31 30 25 24 23 19 18 5 4 0
1347 * +----+-------------+----+-------+-------------+------+
1348 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1349 * +----+-------------+----+-------+-------------+------+
1351 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1353 unsigned int bit_pos
, op
, rt
;
1358 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1359 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1360 diff
= sextract32(insn
, 5, 14) * 4;
1361 rt
= extract32(insn
, 0, 5);
1363 tcg_cmp
= tcg_temp_new_i64();
1364 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1368 match
= gen_disas_label(s
);
1369 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1370 tcg_cmp
, 0, match
.label
);
1371 gen_goto_tb(s
, 0, 4);
1372 set_disas_label(s
, match
);
1373 gen_goto_tb(s
, 1, diff
);
1376 /* Conditional branch (immediate)
1377 * 31 25 24 23 5 4 3 0
1378 * +---------------+----+---------------------+----+------+
1379 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1380 * +---------------+----+---------------------+----+------+
1382 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1387 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1388 unallocated_encoding(s
);
1391 diff
= sextract32(insn
, 5, 19) * 4;
1392 cond
= extract32(insn
, 0, 4);
1396 /* genuinely conditional branches */
1397 DisasLabel match
= gen_disas_label(s
);
1398 arm_gen_test_cc(cond
, match
.label
);
1399 gen_goto_tb(s
, 0, 4);
1400 set_disas_label(s
, match
);
1401 gen_goto_tb(s
, 1, diff
);
1403 /* 0xe and 0xf are both "always" conditions */
1404 gen_goto_tb(s
, 0, diff
);
1408 /* HINT instruction group, including various allocated HINTs */
1409 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1410 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1412 unsigned int selector
= crm
<< 3 | op2
;
1415 unallocated_encoding(s
);
1420 case 0b00000: /* NOP */
1422 case 0b00011: /* WFI */
1423 s
->base
.is_jmp
= DISAS_WFI
;
1425 case 0b00001: /* YIELD */
1426 /* When running in MTTCG we don't generate jumps to the yield and
1427 * WFE helpers as it won't affect the scheduling of other vCPUs.
1428 * If we wanted to more completely model WFE/SEV so we don't busy
1429 * spin unnecessarily we would need to do something more involved.
1431 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1432 s
->base
.is_jmp
= DISAS_YIELD
;
1435 case 0b00010: /* WFE */
1436 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1437 s
->base
.is_jmp
= DISAS_WFE
;
1440 case 0b00100: /* SEV */
1441 case 0b00101: /* SEVL */
1442 case 0b00110: /* DGH */
1443 /* we treat all as NOP at least for now */
1445 case 0b00111: /* XPACLRI */
1446 if (s
->pauth_active
) {
1447 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1450 case 0b01000: /* PACIA1716 */
1451 if (s
->pauth_active
) {
1452 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1455 case 0b01010: /* PACIB1716 */
1456 if (s
->pauth_active
) {
1457 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1460 case 0b01100: /* AUTIA1716 */
1461 if (s
->pauth_active
) {
1462 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1465 case 0b01110: /* AUTIB1716 */
1466 if (s
->pauth_active
) {
1467 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1470 case 0b10000: /* ESB */
1471 /* Without RAS, we must implement this as NOP. */
1472 if (dc_isar_feature(aa64_ras
, s
)) {
1474 * QEMU does not have a source of physical SErrors,
1475 * so we are only concerned with virtual SErrors.
1476 * The pseudocode in the ARM for this case is
1477 * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
1478 * AArch64.vESBOperation();
1479 * Most of the condition can be evaluated at translation time.
1480 * Test for EL2 present, and defer test for SEL2 to runtime.
1482 if (s
->current_el
<= 1 && arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
1483 gen_helper_vesb(cpu_env
);
1487 case 0b11000: /* PACIAZ */
1488 if (s
->pauth_active
) {
1489 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1490 tcg_constant_i64(0));
1493 case 0b11001: /* PACIASP */
1494 if (s
->pauth_active
) {
1495 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1498 case 0b11010: /* PACIBZ */
1499 if (s
->pauth_active
) {
1500 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1501 tcg_constant_i64(0));
1504 case 0b11011: /* PACIBSP */
1505 if (s
->pauth_active
) {
1506 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1509 case 0b11100: /* AUTIAZ */
1510 if (s
->pauth_active
) {
1511 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1512 tcg_constant_i64(0));
1515 case 0b11101: /* AUTIASP */
1516 if (s
->pauth_active
) {
1517 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1520 case 0b11110: /* AUTIBZ */
1521 if (s
->pauth_active
) {
1522 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1523 tcg_constant_i64(0));
1526 case 0b11111: /* AUTIBSP */
1527 if (s
->pauth_active
) {
1528 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1532 /* default specified as NOP equivalent */
1537 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1539 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1542 /* CLREX, DSB, DMB, ISB */
1543 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1544 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1549 unallocated_encoding(s
);
1560 case 1: /* MBReqTypes_Reads */
1561 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1563 case 2: /* MBReqTypes_Writes */
1564 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1566 default: /* MBReqTypes_All */
1567 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1573 /* We need to break the TB after this insn to execute
1574 * a self-modified code correctly and also to take
1575 * any pending interrupts immediately.
1578 gen_goto_tb(s
, 0, 4);
1582 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1583 goto do_unallocated
;
1586 * TODO: There is no speculation barrier opcode for TCG;
1587 * MB and end the TB instead.
1589 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1590 gen_goto_tb(s
, 0, 4);
1595 unallocated_encoding(s
);
1600 static void gen_xaflag(void)
1602 TCGv_i32 z
= tcg_temp_new_i32();
1604 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1613 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1614 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1617 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1618 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1620 /* (!C & Z) << 31 -> -(Z & ~C) */
1621 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1622 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1625 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1628 static void gen_axflag(void)
1630 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1631 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1633 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1634 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1636 tcg_gen_movi_i32(cpu_NF
, 0);
1637 tcg_gen_movi_i32(cpu_VF
, 0);
1640 /* MSR (immediate) - move immediate to processor state field */
1641 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1642 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1644 int op
= op1
<< 3 | op2
;
1646 /* End the TB by default, chaining is ok. */
1647 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1650 case 0x00: /* CFINV */
1651 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1652 goto do_unallocated
;
1654 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1655 s
->base
.is_jmp
= DISAS_NEXT
;
1658 case 0x01: /* XAFlag */
1659 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1660 goto do_unallocated
;
1663 s
->base
.is_jmp
= DISAS_NEXT
;
1666 case 0x02: /* AXFlag */
1667 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1668 goto do_unallocated
;
1671 s
->base
.is_jmp
= DISAS_NEXT
;
1674 case 0x03: /* UAO */
1675 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1676 goto do_unallocated
;
1679 set_pstate_bits(PSTATE_UAO
);
1681 clear_pstate_bits(PSTATE_UAO
);
1683 gen_rebuild_hflags(s
);
1686 case 0x04: /* PAN */
1687 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1688 goto do_unallocated
;
1691 set_pstate_bits(PSTATE_PAN
);
1693 clear_pstate_bits(PSTATE_PAN
);
1695 gen_rebuild_hflags(s
);
1698 case 0x05: /* SPSel */
1699 if (s
->current_el
== 0) {
1700 goto do_unallocated
;
1702 gen_helper_msr_i_spsel(cpu_env
, tcg_constant_i32(crm
& PSTATE_SP
));
1705 case 0x19: /* SSBS */
1706 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1707 goto do_unallocated
;
1710 set_pstate_bits(PSTATE_SSBS
);
1712 clear_pstate_bits(PSTATE_SSBS
);
1714 /* Don't need to rebuild hflags since SSBS is a nop */
1717 case 0x1a: /* DIT */
1718 if (!dc_isar_feature(aa64_dit
, s
)) {
1719 goto do_unallocated
;
1722 set_pstate_bits(PSTATE_DIT
);
1724 clear_pstate_bits(PSTATE_DIT
);
1726 /* There's no need to rebuild hflags because DIT is a nop */
1729 case 0x1e: /* DAIFSet */
1730 gen_helper_msr_i_daifset(cpu_env
, tcg_constant_i32(crm
));
1733 case 0x1f: /* DAIFClear */
1734 gen_helper_msr_i_daifclear(cpu_env
, tcg_constant_i32(crm
));
1735 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1736 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1739 case 0x1c: /* TCO */
1740 if (dc_isar_feature(aa64_mte
, s
)) {
1741 /* Full MTE is enabled -- set the TCO bit as directed. */
1743 set_pstate_bits(PSTATE_TCO
);
1745 clear_pstate_bits(PSTATE_TCO
);
1747 gen_rebuild_hflags(s
);
1748 /* Many factors, including TCO, go into MTE_ACTIVE. */
1749 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1750 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1751 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1752 s
->base
.is_jmp
= DISAS_NEXT
;
1754 goto do_unallocated
;
1758 case 0x1b: /* SVCR* */
1759 if (!dc_isar_feature(aa64_sme
, s
) || crm
< 2 || crm
> 7) {
1760 goto do_unallocated
;
1762 if (sme_access_check(s
)) {
1763 int old
= s
->pstate_sm
| (s
->pstate_za
<< 1);
1764 int new = (crm
& 1) * 3;
1765 int msk
= (crm
>> 1) & 3;
1767 if ((old
^ new) & msk
) {
1768 /* At least one bit changes. */
1769 gen_helper_set_svcr(cpu_env
, tcg_constant_i32(new),
1770 tcg_constant_i32(msk
));
1772 s
->base
.is_jmp
= DISAS_NEXT
;
1779 unallocated_encoding(s
);
1784 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1786 TCGv_i32 tmp
= tcg_temp_new_i32();
1787 TCGv_i32 nzcv
= tcg_temp_new_i32();
1789 /* build bit 31, N */
1790 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1791 /* build bit 30, Z */
1792 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1793 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1794 /* build bit 29, C */
1795 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1796 /* build bit 28, V */
1797 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1798 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1799 /* generate result */
1800 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1803 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1805 TCGv_i32 nzcv
= tcg_temp_new_i32();
1807 /* take NZCV from R[t] */
1808 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1811 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1813 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1814 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1816 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1817 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1819 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1820 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1823 static void gen_sysreg_undef(DisasContext
*s
, bool isread
,
1824 uint8_t op0
, uint8_t op1
, uint8_t op2
,
1825 uint8_t crn
, uint8_t crm
, uint8_t rt
)
1828 * Generate code to emit an UNDEF with correct syndrome
1829 * information for a failed system register access.
1830 * This is EC_UNCATEGORIZED (ie a standard UNDEF) in most cases,
1831 * but if FEAT_IDST is implemented then read accesses to registers
1832 * in the feature ID space are reported with the EC_SYSTEMREGISTERTRAP
1837 if (isread
&& dc_isar_feature(aa64_ids
, s
) &&
1838 arm_cpreg_encoding_in_idspace(op0
, op1
, op2
, crn
, crm
)) {
1839 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1841 syndrome
= syn_uncategorized();
1843 gen_exception_insn(s
, 0, EXCP_UDEF
, syndrome
);
1846 /* MRS - move from system register
1847 * MSR (register) - move to system register
1850 * These are all essentially the same insn in 'read' and 'write'
1851 * versions, with varying op0 fields.
1853 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1854 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1855 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1857 uint32_t key
= ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1858 crn
, crm
, op0
, op1
, op2
);
1859 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(s
->cp_regs
, key
);
1860 TCGv_ptr tcg_ri
= NULL
;
1864 /* Unknown register; this might be a guest error or a QEMU
1865 * unimplemented feature.
1867 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1868 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1869 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1870 gen_sysreg_undef(s
, isread
, op0
, op1
, op2
, crn
, crm
, rt
);
1874 /* Check access permissions */
1875 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1876 gen_sysreg_undef(s
, isread
, op0
, op1
, op2
, crn
, crm
, rt
);
1880 if (ri
->accessfn
|| (ri
->fgt
&& s
->fgt_active
)) {
1881 /* Emit code to perform further access permissions checks at
1882 * runtime; this may result in an exception.
1886 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1887 gen_a64_update_pc(s
, 0);
1888 tcg_ri
= tcg_temp_new_ptr();
1889 gen_helper_access_check_cp_reg(tcg_ri
, cpu_env
,
1890 tcg_constant_i32(key
),
1891 tcg_constant_i32(syndrome
),
1892 tcg_constant_i32(isread
));
1893 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1895 * The readfn or writefn might raise an exception;
1896 * synchronize the CPU state in case it does.
1898 gen_a64_update_pc(s
, 0);
1901 /* Handle special cases first */
1902 switch (ri
->type
& ARM_CP_SPECIAL_MASK
) {
1908 tcg_rt
= cpu_reg(s
, rt
);
1910 gen_get_nzcv(tcg_rt
);
1912 gen_set_nzcv(tcg_rt
);
1915 case ARM_CP_CURRENTEL
:
1916 /* Reads as current EL value from pstate, which is
1917 * guaranteed to be constant by the tb flags.
1919 tcg_rt
= cpu_reg(s
, rt
);
1920 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1923 /* Writes clear the aligned block of memory which rt points into. */
1924 if (s
->mte_active
[0]) {
1927 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1928 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1929 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1931 tcg_rt
= tcg_temp_new_i64();
1932 gen_helper_mte_check_zva(tcg_rt
, cpu_env
,
1933 tcg_constant_i32(desc
), cpu_reg(s
, rt
));
1935 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1937 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1941 TCGv_i64 clean_addr
, tag
;
1944 * DC_GVA, like DC_ZVA, requires that we supply the original
1945 * pointer for an invalid page. Probe that address first.
1947 tcg_rt
= cpu_reg(s
, rt
);
1948 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1949 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1952 /* Extract the tag from the register to match STZGM. */
1953 tag
= tcg_temp_new_i64();
1954 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1955 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1959 case ARM_CP_DC_GZVA
:
1961 TCGv_i64 clean_addr
, tag
;
1963 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1964 tcg_rt
= cpu_reg(s
, rt
);
1965 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1966 gen_helper_dc_zva(cpu_env
, clean_addr
);
1969 /* Extract the tag from the register to match STZGM. */
1970 tag
= tcg_temp_new_i64();
1971 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1972 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1977 g_assert_not_reached();
1979 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check_only(s
)) {
1981 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1983 } else if ((ri
->type
& ARM_CP_SME
) && !sme_access_check(s
)) {
1987 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1991 tcg_rt
= cpu_reg(s
, rt
);
1994 if (ri
->type
& ARM_CP_CONST
) {
1995 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1996 } else if (ri
->readfn
) {
1998 tcg_ri
= gen_lookup_cp_reg(key
);
2000 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tcg_ri
);
2002 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2005 if (ri
->type
& ARM_CP_CONST
) {
2006 /* If not forbidden by access permissions, treat as WI */
2008 } else if (ri
->writefn
) {
2010 tcg_ri
= gen_lookup_cp_reg(key
);
2012 gen_helper_set_cp_reg64(cpu_env
, tcg_ri
, tcg_rt
);
2014 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2018 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
2019 /* I/O operations must end the TB here (whether read or write) */
2020 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2022 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
2024 * A write to any coprocessor regiser that ends a TB
2025 * must rebuild the hflags for the next TB.
2027 gen_rebuild_hflags(s
);
2029 * We default to ending the TB on a coprocessor register write,
2030 * but allow this to be suppressed by the register definition
2031 * (usually only necessary to work around guest bugs).
2033 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2038 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2039 * +---------------------+---+-----+-----+-------+-------+-----+------+
2040 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2041 * +---------------------+---+-----+-----+-------+-------+-----+------+
2043 static void disas_system(DisasContext
*s
, uint32_t insn
)
2045 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2046 l
= extract32(insn
, 21, 1);
2047 op0
= extract32(insn
, 19, 2);
2048 op1
= extract32(insn
, 16, 3);
2049 crn
= extract32(insn
, 12, 4);
2050 crm
= extract32(insn
, 8, 4);
2051 op2
= extract32(insn
, 5, 3);
2052 rt
= extract32(insn
, 0, 5);
2055 if (l
|| rt
!= 31) {
2056 unallocated_encoding(s
);
2060 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2061 handle_hint(s
, insn
, op1
, op2
, crm
);
2063 case 3: /* CLREX, DSB, DMB, ISB */
2064 handle_sync(s
, insn
, op1
, op2
, crm
);
2066 case 4: /* MSR (immediate) */
2067 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2070 unallocated_encoding(s
);
2075 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2078 /* Exception generation
2080 * 31 24 23 21 20 5 4 2 1 0
2081 * +-----------------+-----+------------------------+-----+----+
2082 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2083 * +-----------------------+------------------------+----------+
2085 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2087 int opc
= extract32(insn
, 21, 3);
2088 int op2_ll
= extract32(insn
, 0, 5);
2089 int imm16
= extract32(insn
, 5, 16);
2094 /* For SVC, HVC and SMC we advance the single-step state
2095 * machine before taking the exception. This is architecturally
2096 * mandated, to ensure that single-stepping a system call
2097 * instruction works properly.
2101 syndrome
= syn_aa64_svc(imm16
);
2103 gen_exception_insn_el(s
, 0, EXCP_UDEF
, syndrome
, 2);
2107 gen_exception_insn(s
, 4, EXCP_SWI
, syndrome
);
2110 if (s
->current_el
== 0) {
2111 unallocated_encoding(s
);
2114 /* The pre HVC helper handles cases when HVC gets trapped
2115 * as an undefined insn by runtime configuration.
2117 gen_a64_update_pc(s
, 0);
2118 gen_helper_pre_hvc(cpu_env
);
2120 gen_exception_insn_el(s
, 4, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
2123 if (s
->current_el
== 0) {
2124 unallocated_encoding(s
);
2127 gen_a64_update_pc(s
, 0);
2128 gen_helper_pre_smc(cpu_env
, tcg_constant_i32(syn_aa64_smc(imm16
)));
2130 gen_exception_insn_el(s
, 4, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
2133 unallocated_encoding(s
);
2139 unallocated_encoding(s
);
2143 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2147 unallocated_encoding(s
);
2150 /* HLT. This has two purposes.
2151 * Architecturally, it is an external halting debug instruction.
2152 * Since QEMU doesn't implement external debug, we treat this as
2153 * it is required for halting debug disabled: it will UNDEF.
2154 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2156 if (semihosting_enabled(s
->current_el
== 0) && imm16
== 0xf000) {
2157 gen_exception_internal_insn(s
, EXCP_SEMIHOST
);
2159 unallocated_encoding(s
);
2163 if (op2_ll
< 1 || op2_ll
> 3) {
2164 unallocated_encoding(s
);
2167 /* DCPS1, DCPS2, DCPS3 */
2168 unallocated_encoding(s
);
2171 unallocated_encoding(s
);
2176 /* Unconditional branch (register)
2177 * 31 25 24 21 20 16 15 10 9 5 4 0
2178 * +---------------+-------+-------+-------+------+-------+
2179 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2180 * +---------------+-------+-------+-------+------+-------+
2182 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2184 unsigned int opc
, op2
, op3
, rn
, op4
;
2185 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2189 opc
= extract32(insn
, 21, 4);
2190 op2
= extract32(insn
, 16, 5);
2191 op3
= extract32(insn
, 10, 6);
2192 rn
= extract32(insn
, 5, 5);
2193 op4
= extract32(insn
, 0, 5);
2196 goto do_unallocated
;
2208 goto do_unallocated
;
2210 dst
= cpu_reg(s
, rn
);
2215 if (!dc_isar_feature(aa64_pauth
, s
)) {
2216 goto do_unallocated
;
2220 if (rn
!= 0x1f || op4
!= 0x1f) {
2221 goto do_unallocated
;
2224 modifier
= cpu_X
[31];
2226 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2228 goto do_unallocated
;
2230 modifier
= tcg_constant_i64(0);
2232 if (s
->pauth_active
) {
2233 dst
= tcg_temp_new_i64();
2235 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2237 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2240 dst
= cpu_reg(s
, rn
);
2245 goto do_unallocated
;
2247 /* BLR also needs to load return address */
2249 TCGv_i64 lr
= cpu_reg(s
, 30);
2251 TCGv_i64 tmp
= tcg_temp_new_i64();
2252 tcg_gen_mov_i64(tmp
, dst
);
2255 gen_pc_plus_diff(s
, lr
, curr_insn_len(s
));
2257 gen_a64_set_pc(s
, dst
);
2262 if (!dc_isar_feature(aa64_pauth
, s
)) {
2263 goto do_unallocated
;
2265 if ((op3
& ~1) != 2) {
2266 goto do_unallocated
;
2268 btype_mod
= opc
& 1;
2269 if (s
->pauth_active
) {
2270 dst
= tcg_temp_new_i64();
2271 modifier
= cpu_reg_sp(s
, op4
);
2273 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2275 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2278 dst
= cpu_reg(s
, rn
);
2280 /* BLRAA also needs to load return address */
2282 TCGv_i64 lr
= cpu_reg(s
, 30);
2284 TCGv_i64 tmp
= tcg_temp_new_i64();
2285 tcg_gen_mov_i64(tmp
, dst
);
2288 gen_pc_plus_diff(s
, lr
, curr_insn_len(s
));
2290 gen_a64_set_pc(s
, dst
);
2294 if (s
->current_el
== 0) {
2295 goto do_unallocated
;
2300 goto do_unallocated
;
2303 gen_exception_insn_el(s
, 0, EXCP_UDEF
, syn_erettrap(op3
), 2);
2306 dst
= tcg_temp_new_i64();
2307 tcg_gen_ld_i64(dst
, cpu_env
,
2308 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2311 case 2: /* ERETAA */
2312 case 3: /* ERETAB */
2313 if (!dc_isar_feature(aa64_pauth
, s
)) {
2314 goto do_unallocated
;
2316 if (rn
!= 0x1f || op4
!= 0x1f) {
2317 goto do_unallocated
;
2319 /* The FGT trap takes precedence over an auth trap. */
2321 gen_exception_insn_el(s
, 0, EXCP_UDEF
, syn_erettrap(op3
), 2);
2324 dst
= tcg_temp_new_i64();
2325 tcg_gen_ld_i64(dst
, cpu_env
,
2326 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2327 if (s
->pauth_active
) {
2328 modifier
= cpu_X
[31];
2330 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2332 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2338 goto do_unallocated
;
2340 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2344 gen_helper_exception_return(cpu_env
, dst
);
2345 /* Must exit loop to check un-masked IRQs */
2346 s
->base
.is_jmp
= DISAS_EXIT
;
2350 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2351 goto do_unallocated
;
2353 unallocated_encoding(s
);
2359 unallocated_encoding(s
);
2363 switch (btype_mod
) {
2365 if (dc_isar_feature(aa64_bti
, s
)) {
2366 /* BR to {x16,x17} or !guard -> 1, else 3. */
2367 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2372 if (dc_isar_feature(aa64_bti
, s
)) {
2373 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2378 default: /* RET or none of the above. */
2379 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2383 s
->base
.is_jmp
= DISAS_JUMP
;
2386 /* Branches, exception generating and system instructions */
2387 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2389 switch (extract32(insn
, 25, 7)) {
2390 case 0x0a: case 0x0b:
2391 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2392 disas_uncond_b_imm(s
, insn
);
2394 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2395 disas_comp_b_imm(s
, insn
);
2397 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2398 disas_test_b_imm(s
, insn
);
2400 case 0x2a: /* Conditional branch (immediate) */
2401 disas_cond_b_imm(s
, insn
);
2403 case 0x6a: /* Exception generation / System */
2404 if (insn
& (1 << 24)) {
2405 if (extract32(insn
, 22, 2) == 0) {
2406 disas_system(s
, insn
);
2408 unallocated_encoding(s
);
2414 case 0x6b: /* Unconditional branch (register) */
2415 disas_uncond_b_reg(s
, insn
);
2418 unallocated_encoding(s
);
2424 * Load/Store exclusive instructions are implemented by remembering
2425 * the value/address loaded, and seeing if these are the same
2426 * when the store is performed. This is not actually the architecturally
2427 * mandated semantics, but it works for typical guest code sequences
2428 * and avoids having to monitor regular stores.
2430 * The store exclusive uses the atomic cmpxchg primitives to avoid
2431 * races in multi-threaded linux-user and when MTTCG softmmu is
2434 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2435 TCGv_i64 addr
, int size
, bool is_pair
)
2437 int idx
= get_mem_index(s
);
2438 MemOp memop
= s
->be_data
;
2440 g_assert(size
<= 3);
2442 g_assert(size
>= 2);
2444 /* The pair must be single-copy atomic for the doubleword. */
2445 memop
|= MO_64
| MO_ALIGN
;
2446 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2447 if (s
->be_data
== MO_LE
) {
2448 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2449 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2451 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2452 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2455 /* The pair must be single-copy atomic for *each* doubleword, not
2456 the entire quadword, however it must be quadword aligned. */
2458 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2459 memop
| MO_ALIGN_16
);
2461 TCGv_i64 addr2
= tcg_temp_new_i64();
2462 tcg_gen_addi_i64(addr2
, addr
, 8);
2463 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2465 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2466 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2469 memop
|= size
| MO_ALIGN
;
2470 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2471 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2473 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2476 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2477 TCGv_i64 addr
, int size
, int is_pair
)
2479 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2480 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2483 * [addr + datasize] = {Rt2};
2489 * env->exclusive_addr = -1;
2491 TCGLabel
*fail_label
= gen_new_label();
2492 TCGLabel
*done_label
= gen_new_label();
2495 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2497 tmp
= tcg_temp_new_i64();
2500 if (s
->be_data
== MO_LE
) {
2501 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2503 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2505 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2506 cpu_exclusive_val
, tmp
,
2508 MO_64
| MO_ALIGN
| s
->be_data
);
2509 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2511 TCGv_i128 t16
= tcg_temp_new_i128();
2512 TCGv_i128 c16
= tcg_temp_new_i128();
2515 if (s
->be_data
== MO_LE
) {
2516 tcg_gen_concat_i64_i128(t16
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2517 tcg_gen_concat_i64_i128(c16
, cpu_exclusive_val
,
2518 cpu_exclusive_high
);
2520 tcg_gen_concat_i64_i128(t16
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2521 tcg_gen_concat_i64_i128(c16
, cpu_exclusive_high
,
2525 tcg_gen_atomic_cmpxchg_i128(t16
, cpu_exclusive_addr
, c16
, t16
,
2527 MO_128
| MO_ALIGN
| s
->be_data
);
2529 a
= tcg_temp_new_i64();
2530 b
= tcg_temp_new_i64();
2531 if (s
->be_data
== MO_LE
) {
2532 tcg_gen_extr_i128_i64(a
, b
, t16
);
2534 tcg_gen_extr_i128_i64(b
, a
, t16
);
2537 tcg_gen_xor_i64(a
, a
, cpu_exclusive_val
);
2538 tcg_gen_xor_i64(b
, b
, cpu_exclusive_high
);
2539 tcg_gen_or_i64(tmp
, a
, b
);
2541 tcg_gen_setcondi_i64(TCG_COND_NE
, tmp
, tmp
, 0);
2544 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2545 cpu_reg(s
, rt
), get_mem_index(s
),
2546 size
| MO_ALIGN
| s
->be_data
);
2547 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2549 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2550 tcg_gen_br(done_label
);
2552 gen_set_label(fail_label
);
2553 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2554 gen_set_label(done_label
);
2555 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2558 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2561 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2562 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2563 int memidx
= get_mem_index(s
);
2564 TCGv_i64 clean_addr
;
2567 gen_check_sp_alignment(s
);
2569 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2570 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2571 size
| MO_ALIGN
| s
->be_data
);
2574 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2577 TCGv_i64 s1
= cpu_reg(s
, rs
);
2578 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2579 TCGv_i64 t1
= cpu_reg(s
, rt
);
2580 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2581 TCGv_i64 clean_addr
;
2582 int memidx
= get_mem_index(s
);
2585 gen_check_sp_alignment(s
);
2588 /* This is a single atomic access, despite the "pair". */
2589 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2592 TCGv_i64 cmp
= tcg_temp_new_i64();
2593 TCGv_i64 val
= tcg_temp_new_i64();
2595 if (s
->be_data
== MO_LE
) {
2596 tcg_gen_concat32_i64(val
, t1
, t2
);
2597 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2599 tcg_gen_concat32_i64(val
, t2
, t1
);
2600 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2603 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2604 MO_64
| MO_ALIGN
| s
->be_data
);
2606 if (s
->be_data
== MO_LE
) {
2607 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2609 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2612 TCGv_i128 cmp
= tcg_temp_new_i128();
2613 TCGv_i128 val
= tcg_temp_new_i128();
2615 if (s
->be_data
== MO_LE
) {
2616 tcg_gen_concat_i64_i128(val
, t1
, t2
);
2617 tcg_gen_concat_i64_i128(cmp
, s1
, s2
);
2619 tcg_gen_concat_i64_i128(val
, t2
, t1
);
2620 tcg_gen_concat_i64_i128(cmp
, s2
, s1
);
2623 tcg_gen_atomic_cmpxchg_i128(cmp
, clean_addr
, cmp
, val
, memidx
,
2624 MO_128
| MO_ALIGN
| s
->be_data
);
2626 if (s
->be_data
== MO_LE
) {
2627 tcg_gen_extr_i128_i64(s1
, s2
, cmp
);
2629 tcg_gen_extr_i128_i64(s2
, s1
, cmp
);
2634 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2635 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2637 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2639 int opc0
= extract32(opc
, 0, 1);
2643 regsize
= opc0
? 32 : 64;
2645 regsize
= size
== 3 ? 64 : 32;
2647 return regsize
== 64;
2650 /* Load/store exclusive
2652 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2653 * +-----+-------------+----+---+----+------+----+-------+------+------+
2654 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2655 * +-----+-------------+----+---+----+------+----+-------+------+------+
2657 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2658 * L: 0 -> store, 1 -> load
2659 * o2: 0 -> exclusive, 1 -> not
2660 * o1: 0 -> single register, 1 -> register pair
2661 * o0: 1 -> load-acquire/store-release, 0 -> not
2663 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2665 int rt
= extract32(insn
, 0, 5);
2666 int rn
= extract32(insn
, 5, 5);
2667 int rt2
= extract32(insn
, 10, 5);
2668 int rs
= extract32(insn
, 16, 5);
2669 int is_lasr
= extract32(insn
, 15, 1);
2670 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2671 int size
= extract32(insn
, 30, 2);
2672 TCGv_i64 clean_addr
;
2674 switch (o2_L_o1_o0
) {
2675 case 0x0: /* STXR */
2676 case 0x1: /* STLXR */
2678 gen_check_sp_alignment(s
);
2681 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2683 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2684 true, rn
!= 31, size
);
2685 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2688 case 0x4: /* LDXR */
2689 case 0x5: /* LDAXR */
2691 gen_check_sp_alignment(s
);
2693 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2694 false, rn
!= 31, size
);
2696 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2698 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2702 case 0x8: /* STLLR */
2703 if (!dc_isar_feature(aa64_lor
, s
)) {
2706 /* StoreLORelease is the same as Store-Release for QEMU. */
2708 case 0x9: /* STLR */
2709 /* Generate ISS for non-exclusive accesses including LASR. */
2711 gen_check_sp_alignment(s
);
2713 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2714 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2715 true, rn
!= 31, size
);
2716 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2717 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2718 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2721 case 0xc: /* LDLAR */
2722 if (!dc_isar_feature(aa64_lor
, s
)) {
2725 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2727 case 0xd: /* LDAR */
2728 /* Generate ISS for non-exclusive accesses including LASR. */
2730 gen_check_sp_alignment(s
);
2732 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2733 false, rn
!= 31, size
);
2734 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2735 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2736 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2737 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2740 case 0x2: case 0x3: /* CASP / STXP */
2741 if (size
& 2) { /* STXP / STLXP */
2743 gen_check_sp_alignment(s
);
2746 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2748 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2749 true, rn
!= 31, size
);
2750 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2754 && ((rt
| rs
) & 1) == 0
2755 && dc_isar_feature(aa64_atomics
, s
)) {
2757 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2762 case 0x6: case 0x7: /* CASPA / LDXP */
2763 if (size
& 2) { /* LDXP / LDAXP */
2765 gen_check_sp_alignment(s
);
2767 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2768 false, rn
!= 31, size
);
2770 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2772 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2777 && ((rt
| rs
) & 1) == 0
2778 && dc_isar_feature(aa64_atomics
, s
)) {
2779 /* CASPA / CASPAL */
2780 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2786 case 0xb: /* CASL */
2787 case 0xe: /* CASA */
2788 case 0xf: /* CASAL */
2789 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2790 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2795 unallocated_encoding(s
);
2799 * Load register (literal)
2801 * 31 30 29 27 26 25 24 23 5 4 0
2802 * +-----+-------+---+-----+-------------------+-------+
2803 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2804 * +-----+-------+---+-----+-------------------+-------+
2806 * V: 1 -> vector (simd/fp)
2807 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2808 * 10-> 32 bit signed, 11 -> prefetch
2809 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2811 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2813 int rt
= extract32(insn
, 0, 5);
2814 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2815 bool is_vector
= extract32(insn
, 26, 1);
2816 int opc
= extract32(insn
, 30, 2);
2817 bool is_signed
= false;
2819 TCGv_i64 tcg_rt
, clean_addr
;
2823 unallocated_encoding(s
);
2827 if (!fp_access_check(s
)) {
2832 /* PRFM (literal) : prefetch */
2835 size
= 2 + extract32(opc
, 0, 1);
2836 is_signed
= extract32(opc
, 1, 1);
2839 tcg_rt
= cpu_reg(s
, rt
);
2841 clean_addr
= tcg_temp_new_i64();
2842 gen_pc_plus_diff(s
, clean_addr
, imm
);
2844 do_fp_ld(s
, rt
, clean_addr
, size
);
2846 /* Only unsigned 32bit loads target 32bit registers. */
2847 bool iss_sf
= opc
!= 0;
2849 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2850 false, true, rt
, iss_sf
, false);
2855 * LDNP (Load Pair - non-temporal hint)
2856 * LDP (Load Pair - non vector)
2857 * LDPSW (Load Pair Signed Word - non vector)
2858 * STNP (Store Pair - non-temporal hint)
2859 * STP (Store Pair - non vector)
2860 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2861 * LDP (Load Pair of SIMD&FP)
2862 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2863 * STP (Store Pair of SIMD&FP)
2865 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2866 * +-----+-------+---+---+-------+---+-----------------------------+
2867 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2868 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2870 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2872 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2873 * V: 0 -> GPR, 1 -> Vector
2874 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2875 * 10 -> signed offset, 11 -> pre-index
2876 * L: 0 -> Store 1 -> Load
2878 * Rt, Rt2 = GPR or SIMD registers to be stored
2879 * Rn = general purpose register containing address
2880 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2882 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2884 int rt
= extract32(insn
, 0, 5);
2885 int rn
= extract32(insn
, 5, 5);
2886 int rt2
= extract32(insn
, 10, 5);
2887 uint64_t offset
= sextract64(insn
, 15, 7);
2888 int index
= extract32(insn
, 23, 2);
2889 bool is_vector
= extract32(insn
, 26, 1);
2890 bool is_load
= extract32(insn
, 22, 1);
2891 int opc
= extract32(insn
, 30, 2);
2893 bool is_signed
= false;
2894 bool postindex
= false;
2896 bool set_tag
= false;
2898 TCGv_i64 clean_addr
, dirty_addr
;
2903 unallocated_encoding(s
);
2909 } else if (opc
== 1 && !is_load
) {
2911 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2912 unallocated_encoding(s
);
2918 size
= 2 + extract32(opc
, 1, 1);
2919 is_signed
= extract32(opc
, 0, 1);
2920 if (!is_load
&& is_signed
) {
2921 unallocated_encoding(s
);
2927 case 1: /* post-index */
2932 /* signed offset with "non-temporal" hint. Since we don't emulate
2933 * caches we don't care about hints to the cache system about
2934 * data access patterns, and handle this identically to plain
2938 /* There is no non-temporal-hint version of LDPSW */
2939 unallocated_encoding(s
);
2944 case 2: /* signed offset, rn not updated */
2947 case 3: /* pre-index */
2953 if (is_vector
&& !fp_access_check(s
)) {
2957 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2960 gen_check_sp_alignment(s
);
2963 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2965 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2971 * TODO: We could rely on the stores below, at least for
2972 * system mode, if we arrange to add MO_ALIGN_16.
2974 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2975 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2976 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2978 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2982 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2983 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
2987 do_fp_ld(s
, rt
, clean_addr
, size
);
2989 do_fp_st(s
, rt
, clean_addr
, size
);
2991 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2993 do_fp_ld(s
, rt2
, clean_addr
, size
);
2995 do_fp_st(s
, rt2
, clean_addr
, size
);
2998 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2999 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
3002 TCGv_i64 tmp
= tcg_temp_new_i64();
3004 /* Do not modify tcg_rt before recognizing any exception
3005 * from the second load.
3007 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3008 false, false, 0, false, false);
3009 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3010 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3011 false, false, 0, false, false);
3013 tcg_gen_mov_i64(tcg_rt
, tmp
);
3015 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3016 false, 0, false, false);
3017 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3018 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3019 false, 0, false, false);
3025 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3027 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3032 * Load/store (immediate post-indexed)
3033 * Load/store (immediate pre-indexed)
3034 * Load/store (unscaled immediate)
3036 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3037 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3038 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3039 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3041 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3043 * V = 0 -> non-vector
3044 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3045 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3047 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3053 int rn
= extract32(insn
, 5, 5);
3054 int imm9
= sextract32(insn
, 12, 9);
3055 int idx
= extract32(insn
, 10, 2);
3056 bool is_signed
= false;
3057 bool is_store
= false;
3058 bool is_extended
= false;
3059 bool is_unpriv
= (idx
== 2);
3065 TCGv_i64 clean_addr
, dirty_addr
;
3068 size
|= (opc
& 2) << 1;
3069 if (size
> 4 || is_unpriv
) {
3070 unallocated_encoding(s
);
3073 is_store
= ((opc
& 1) == 0);
3074 if (!fp_access_check(s
)) {
3078 if (size
== 3 && opc
== 2) {
3079 /* PRFM - prefetch */
3081 unallocated_encoding(s
);
3086 if (opc
== 3 && size
> 1) {
3087 unallocated_encoding(s
);
3090 is_store
= (opc
== 0);
3091 is_signed
= extract32(opc
, 1, 1);
3092 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3110 g_assert_not_reached();
3113 iss_valid
= !is_vector
&& !writeback
;
3116 gen_check_sp_alignment(s
);
3119 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3121 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3124 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3125 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3126 writeback
|| rn
!= 31,
3127 size
, is_unpriv
, memidx
);
3131 do_fp_st(s
, rt
, clean_addr
, size
);
3133 do_fp_ld(s
, rt
, clean_addr
, size
);
3136 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3137 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3140 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3141 iss_valid
, rt
, iss_sf
, false);
3143 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3144 is_extended
, memidx
,
3145 iss_valid
, rt
, iss_sf
, false);
3150 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3152 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3154 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3159 * Load/store (register offset)
3161 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3162 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3163 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3164 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3167 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3168 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3170 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3171 * opc<0>: 0 -> store, 1 -> load
3172 * V: 1 -> vector/simd
3173 * opt: extend encoding (see DecodeRegExtend)
3174 * S: if S=1 then scale (essentially index by sizeof(size))
3175 * Rt: register to transfer into/out of
3176 * Rn: address register or SP for base
3177 * Rm: offset register or ZR for offset
3179 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3185 int rn
= extract32(insn
, 5, 5);
3186 int shift
= extract32(insn
, 12, 1);
3187 int rm
= extract32(insn
, 16, 5);
3188 int opt
= extract32(insn
, 13, 3);
3189 bool is_signed
= false;
3190 bool is_store
= false;
3191 bool is_extended
= false;
3193 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3195 if (extract32(opt
, 1, 1) == 0) {
3196 unallocated_encoding(s
);
3201 size
|= (opc
& 2) << 1;
3203 unallocated_encoding(s
);
3206 is_store
= !extract32(opc
, 0, 1);
3207 if (!fp_access_check(s
)) {
3211 if (size
== 3 && opc
== 2) {
3212 /* PRFM - prefetch */
3215 if (opc
== 3 && size
> 1) {
3216 unallocated_encoding(s
);
3219 is_store
= (opc
== 0);
3220 is_signed
= extract32(opc
, 1, 1);
3221 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3225 gen_check_sp_alignment(s
);
3227 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3229 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3230 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3232 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3233 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3237 do_fp_st(s
, rt
, clean_addr
, size
);
3239 do_fp_ld(s
, rt
, clean_addr
, size
);
3242 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3243 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3245 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3246 true, rt
, iss_sf
, false);
3248 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3249 is_extended
, true, rt
, iss_sf
, false);
3255 * Load/store (unsigned immediate)
3257 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3258 * +----+-------+---+-----+-----+------------+-------+------+
3259 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3260 * +----+-------+---+-----+-----+------------+-------+------+
3263 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3264 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3266 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3267 * opc<0>: 0 -> store, 1 -> load
3268 * Rn: base address register (inc SP)
3269 * Rt: target register
3271 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3277 int rn
= extract32(insn
, 5, 5);
3278 unsigned int imm12
= extract32(insn
, 10, 12);
3279 unsigned int offset
;
3281 TCGv_i64 clean_addr
, dirty_addr
;
3284 bool is_signed
= false;
3285 bool is_extended
= false;
3288 size
|= (opc
& 2) << 1;
3290 unallocated_encoding(s
);
3293 is_store
= !extract32(opc
, 0, 1);
3294 if (!fp_access_check(s
)) {
3298 if (size
== 3 && opc
== 2) {
3299 /* PRFM - prefetch */
3302 if (opc
== 3 && size
> 1) {
3303 unallocated_encoding(s
);
3306 is_store
= (opc
== 0);
3307 is_signed
= extract32(opc
, 1, 1);
3308 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3312 gen_check_sp_alignment(s
);
3314 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3315 offset
= imm12
<< size
;
3316 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3317 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3321 do_fp_st(s
, rt
, clean_addr
, size
);
3323 do_fp_ld(s
, rt
, clean_addr
, size
);
3326 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3327 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3329 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3330 true, rt
, iss_sf
, false);
3332 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3333 is_extended
, true, rt
, iss_sf
, false);
3338 /* Atomic memory operations
3340 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3341 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3342 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3343 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3345 * Rt: the result register
3346 * Rn: base address or SP
3347 * Rs: the source register for the operation
3348 * V: vector flag (always 0 as of v8.3)
3352 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3353 int size
, int rt
, bool is_vector
)
3355 int rs
= extract32(insn
, 16, 5);
3356 int rn
= extract32(insn
, 5, 5);
3357 int o3_opc
= extract32(insn
, 12, 4);
3358 bool r
= extract32(insn
, 22, 1);
3359 bool a
= extract32(insn
, 23, 1);
3360 TCGv_i64 tcg_rs
, tcg_rt
, clean_addr
;
3361 AtomicThreeOpFn
*fn
= NULL
;
3362 MemOp mop
= s
->be_data
| size
| MO_ALIGN
;
3364 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3365 unallocated_encoding(s
);
3369 case 000: /* LDADD */
3370 fn
= tcg_gen_atomic_fetch_add_i64
;
3372 case 001: /* LDCLR */
3373 fn
= tcg_gen_atomic_fetch_and_i64
;
3375 case 002: /* LDEOR */
3376 fn
= tcg_gen_atomic_fetch_xor_i64
;
3378 case 003: /* LDSET */
3379 fn
= tcg_gen_atomic_fetch_or_i64
;
3381 case 004: /* LDSMAX */
3382 fn
= tcg_gen_atomic_fetch_smax_i64
;
3385 case 005: /* LDSMIN */
3386 fn
= tcg_gen_atomic_fetch_smin_i64
;
3389 case 006: /* LDUMAX */
3390 fn
= tcg_gen_atomic_fetch_umax_i64
;
3392 case 007: /* LDUMIN */
3393 fn
= tcg_gen_atomic_fetch_umin_i64
;
3396 fn
= tcg_gen_atomic_xchg_i64
;
3398 case 014: /* LDAPR, LDAPRH, LDAPRB */
3399 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3400 rs
!= 31 || a
!= 1 || r
!= 0) {
3401 unallocated_encoding(s
);
3406 unallocated_encoding(s
);
3411 gen_check_sp_alignment(s
);
3413 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3415 if (o3_opc
== 014) {
3417 * LDAPR* are a special case because they are a simple load, not a
3418 * fetch-and-do-something op.
3419 * The architectural consistency requirements here are weaker than
3420 * full load-acquire (we only need "load-acquire processor consistent"),
3421 * but we choose to implement them as full LDAQ.
3423 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3424 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3425 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3429 tcg_rs
= read_cpu_reg(s
, rs
, true);
3430 tcg_rt
= cpu_reg(s
, rt
);
3432 if (o3_opc
== 1) { /* LDCLR */
3433 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3436 /* The tcg atomic primitives are all full barriers. Therefore we
3437 * can ignore the Acquire and Release bits of this instruction.
3439 fn(tcg_rt
, clean_addr
, tcg_rs
, get_mem_index(s
), mop
);
3441 if ((mop
& MO_SIGN
) && size
!= MO_64
) {
3442 tcg_gen_ext32u_i64(tcg_rt
, tcg_rt
);
3447 * PAC memory operations
3449 * 31 30 27 26 24 22 21 12 11 10 5 0
3450 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3451 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3452 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3454 * Rt: the result register
3455 * Rn: base address or SP
3456 * V: vector flag (always 0 as of v8.3)
3457 * M: clear for key DA, set for key DB
3458 * W: pre-indexing flag
3461 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3462 int size
, int rt
, bool is_vector
)
3464 int rn
= extract32(insn
, 5, 5);
3465 bool is_wback
= extract32(insn
, 11, 1);
3466 bool use_key_a
= !extract32(insn
, 23, 1);
3468 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3470 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3471 unallocated_encoding(s
);
3476 gen_check_sp_alignment(s
);
3478 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3480 if (s
->pauth_active
) {
3482 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3483 tcg_constant_i64(0));
3485 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3486 tcg_constant_i64(0));
3490 /* Form the 10-bit signed, scaled offset. */
3491 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3492 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3493 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3495 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3496 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3497 is_wback
|| rn
!= 31, size
);
3499 tcg_rt
= cpu_reg(s
, rt
);
3500 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3501 /* extend */ false, /* iss_valid */ !is_wback
,
3502 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3505 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3510 * LDAPR/STLR (unscaled immediate)
3512 * 31 30 24 22 21 12 10 5 0
3513 * +------+-------------+-----+---+--------+-----+----+-----+
3514 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3515 * +------+-------------+-----+---+--------+-----+----+-----+
3517 * Rt: source or destination register
3519 * imm9: unscaled immediate offset
3520 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3521 * size: size of load/store
3523 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3525 int rt
= extract32(insn
, 0, 5);
3526 int rn
= extract32(insn
, 5, 5);
3527 int offset
= sextract32(insn
, 12, 9);
3528 int opc
= extract32(insn
, 22, 2);
3529 int size
= extract32(insn
, 30, 2);
3530 TCGv_i64 clean_addr
, dirty_addr
;
3531 bool is_store
= false;
3532 bool extend
= false;
3536 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3537 unallocated_encoding(s
);
3541 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3542 mop
= size
| MO_ALIGN
;
3545 case 0: /* STLURB */
3548 case 1: /* LDAPUR* */
3550 case 2: /* LDAPURS* 64-bit variant */
3552 unallocated_encoding(s
);
3557 case 3: /* LDAPURS* 32-bit variant */
3559 unallocated_encoding(s
);
3563 extend
= true; /* zero-extend 32->64 after signed load */
3566 g_assert_not_reached();
3569 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3572 gen_check_sp_alignment(s
);
3575 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3576 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3577 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3580 /* Store-Release semantics */
3581 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3582 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3585 * Load-AcquirePC semantics; we implement as the slightly more
3586 * restrictive Load-Acquire.
3588 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3589 extend
, true, rt
, iss_sf
, true);
3590 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3594 /* Load/store register (all forms) */
3595 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3597 int rt
= extract32(insn
, 0, 5);
3598 int opc
= extract32(insn
, 22, 2);
3599 bool is_vector
= extract32(insn
, 26, 1);
3600 int size
= extract32(insn
, 30, 2);
3602 switch (extract32(insn
, 24, 2)) {
3604 if (extract32(insn
, 21, 1) == 0) {
3605 /* Load/store register (unscaled immediate)
3606 * Load/store immediate pre/post-indexed
3607 * Load/store register unprivileged
3609 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3612 switch (extract32(insn
, 10, 2)) {
3614 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3617 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3620 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3625 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3628 unallocated_encoding(s
);
3631 /* AdvSIMD load/store multiple structures
3633 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3634 * +---+---+---------------+---+-------------+--------+------+------+------+
3635 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3636 * +---+---+---------------+---+-------------+--------+------+------+------+
3638 * AdvSIMD load/store multiple structures (post-indexed)
3640 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3641 * +---+---+---------------+---+---+---------+--------+------+------+------+
3642 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3643 * +---+---+---------------+---+---+---------+--------+------+------+------+
3645 * Rt: first (or only) SIMD&FP register to be transferred
3646 * Rn: base address or SP
3647 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3649 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3651 int rt
= extract32(insn
, 0, 5);
3652 int rn
= extract32(insn
, 5, 5);
3653 int rm
= extract32(insn
, 16, 5);
3654 int size
= extract32(insn
, 10, 2);
3655 int opcode
= extract32(insn
, 12, 4);
3656 bool is_store
= !extract32(insn
, 22, 1);
3657 bool is_postidx
= extract32(insn
, 23, 1);
3658 bool is_q
= extract32(insn
, 30, 1);
3659 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3660 MemOp endian
, align
, mop
;
3662 int total
; /* total bytes */
3663 int elements
; /* elements per vector */
3664 int rpt
; /* num iterations */
3665 int selem
; /* structure elements */
3668 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3669 unallocated_encoding(s
);
3673 if (!is_postidx
&& rm
!= 0) {
3674 unallocated_encoding(s
);
3678 /* From the shared decode logic */
3709 unallocated_encoding(s
);
3713 if (size
== 3 && !is_q
&& selem
!= 1) {
3715 unallocated_encoding(s
);
3719 if (!fp_access_check(s
)) {
3724 gen_check_sp_alignment(s
);
3727 /* For our purposes, bytes are always little-endian. */
3728 endian
= s
->be_data
;
3733 total
= rpt
* selem
* (is_q
? 16 : 8);
3734 tcg_rn
= cpu_reg_sp(s
, rn
);
3737 * Issue the MTE check vs the logical repeat count, before we
3738 * promote consecutive little-endian elements below.
3740 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3744 * Consecutive little-endian elements from a single register
3745 * can be promoted to a larger little-endian operation.
3748 if (selem
== 1 && endian
== MO_LE
) {
3749 align
= pow2_align(size
);
3752 if (!s
->align_mem
) {
3755 mop
= endian
| size
| align
;
3757 elements
= (is_q
? 16 : 8) >> size
;
3758 tcg_ebytes
= tcg_constant_i64(1 << size
);
3759 for (r
= 0; r
< rpt
; r
++) {
3761 for (e
= 0; e
< elements
; e
++) {
3763 for (xs
= 0; xs
< selem
; xs
++) {
3764 int tt
= (rt
+ r
+ xs
) % 32;
3766 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3768 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3770 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3776 /* For non-quad operations, setting a slice of the low
3777 * 64 bits of the register clears the high 64 bits (in
3778 * the ARM ARM pseudocode this is implicit in the fact
3779 * that 'rval' is a 64 bit wide variable).
3780 * For quad operations, we might still need to zero the
3783 for (r
= 0; r
< rpt
* selem
; r
++) {
3784 int tt
= (rt
+ r
) % 32;
3785 clear_vec_high(s
, is_q
, tt
);
3791 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3793 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3798 /* AdvSIMD load/store single structure
3800 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3801 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3802 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3803 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3805 * AdvSIMD load/store single structure (post-indexed)
3807 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3808 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3809 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3810 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3812 * Rt: first (or only) SIMD&FP register to be transferred
3813 * Rn: base address or SP
3814 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3815 * index = encoded in Q:S:size dependent on size
3817 * lane_size = encoded in R, opc
3818 * transfer width = encoded in opc, S, size
3820 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3822 int rt
= extract32(insn
, 0, 5);
3823 int rn
= extract32(insn
, 5, 5);
3824 int rm
= extract32(insn
, 16, 5);
3825 int size
= extract32(insn
, 10, 2);
3826 int S
= extract32(insn
, 12, 1);
3827 int opc
= extract32(insn
, 13, 3);
3828 int R
= extract32(insn
, 21, 1);
3829 int is_load
= extract32(insn
, 22, 1);
3830 int is_postidx
= extract32(insn
, 23, 1);
3831 int is_q
= extract32(insn
, 30, 1);
3833 int scale
= extract32(opc
, 1, 2);
3834 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3835 bool replicate
= false;
3836 int index
= is_q
<< 3 | S
<< 2 | size
;
3838 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3841 if (extract32(insn
, 31, 1)) {
3842 unallocated_encoding(s
);
3845 if (!is_postidx
&& rm
!= 0) {
3846 unallocated_encoding(s
);
3852 if (!is_load
|| S
) {
3853 unallocated_encoding(s
);
3862 if (extract32(size
, 0, 1)) {
3863 unallocated_encoding(s
);
3869 if (extract32(size
, 1, 1)) {
3870 unallocated_encoding(s
);
3873 if (!extract32(size
, 0, 1)) {
3877 unallocated_encoding(s
);
3885 g_assert_not_reached();
3888 if (!fp_access_check(s
)) {
3893 gen_check_sp_alignment(s
);
3896 total
= selem
<< scale
;
3897 tcg_rn
= cpu_reg_sp(s
, rn
);
3899 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3901 mop
= finalize_memop(s
, scale
);
3903 tcg_ebytes
= tcg_constant_i64(1 << scale
);
3904 for (xs
= 0; xs
< selem
; xs
++) {
3906 /* Load and replicate to all elements */
3907 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3909 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3910 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3911 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3914 /* Load/store one element per register */
3916 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3918 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3921 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3927 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3929 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3935 * Load/Store memory tags
3937 * 31 30 29 24 22 21 12 10 5 0
3938 * +-----+-------------+-----+---+------+-----+------+------+
3939 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3940 * +-----+-------------+-----+---+------+-----+------+------+
3942 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3944 int rt
= extract32(insn
, 0, 5);
3945 int rn
= extract32(insn
, 5, 5);
3946 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3947 int op2
= extract32(insn
, 10, 2);
3948 int op1
= extract32(insn
, 22, 2);
3949 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3951 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3953 /* We checked insn bits [29:24,21] in the caller. */
3954 if (extract32(insn
, 30, 2) != 3) {
3955 goto do_unallocated
;
3959 * @index is a tri-state variable which has 3 states:
3960 * < 0 : post-index, writeback
3961 * = 0 : signed offset
3962 * > 0 : pre-index, writeback
3971 if (s
->current_el
== 0 || offset
!= 0) {
3972 goto do_unallocated
;
3974 is_mult
= is_zero
= true;
3994 if (s
->current_el
== 0 || offset
!= 0) {
3995 goto do_unallocated
;
4003 is_pair
= is_zero
= true;
4007 if (s
->current_el
== 0 || offset
!= 0) {
4008 goto do_unallocated
;
4010 is_mult
= is_load
= true;
4016 unallocated_encoding(s
);
4021 ? !dc_isar_feature(aa64_mte
, s
)
4022 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4023 goto do_unallocated
;
4027 gen_check_sp_alignment(s
);
4030 addr
= read_cpu_reg_sp(s
, rn
, true);
4032 /* pre-index or signed offset */
4033 tcg_gen_addi_i64(addr
, addr
, offset
);
4037 tcg_rt
= cpu_reg(s
, rt
);
4040 int size
= 4 << s
->dcz_blocksize
;
4043 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4046 * The non-tags portion of STZGM is mostly like DC_ZVA,
4047 * except the alignment happens before the access.
4049 clean_addr
= clean_data_tbi(s
, addr
);
4050 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4051 gen_helper_dc_zva(cpu_env
, clean_addr
);
4052 } else if (s
->ata
) {
4054 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4056 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4059 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4060 int size
= 4 << GMID_EL1_BS
;
4062 clean_addr
= clean_data_tbi(s
, addr
);
4063 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4064 gen_probe_access(s
, clean_addr
, acc
, size
);
4067 /* The result tags are zeros. */
4068 tcg_gen_movi_i64(tcg_rt
, 0);
4075 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4076 tcg_rt
= cpu_reg(s
, rt
);
4078 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4080 clean_addr
= clean_data_tbi(s
, addr
);
4081 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4082 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4085 tcg_rt
= cpu_reg_sp(s
, rt
);
4088 * For STG and ST2G, we need to check alignment and probe memory.
4089 * TODO: For STZG and STZ2G, we could rely on the stores below,
4090 * at least for system mode; user-only won't enforce alignment.
4093 gen_helper_st2g_stub(cpu_env
, addr
);
4095 gen_helper_stg_stub(cpu_env
, addr
);
4097 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4099 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4101 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4105 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4107 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4113 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4114 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
4115 int mem_index
= get_mem_index(s
);
4116 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4118 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4119 MO_UQ
| MO_ALIGN_16
);
4120 for (i
= 8; i
< n
; i
+= 8) {
4121 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4122 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_UQ
);
4127 /* pre-index or post-index */
4130 tcg_gen_addi_i64(addr
, addr
, offset
);
4132 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4136 /* Loads and stores */
4137 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4139 switch (extract32(insn
, 24, 6)) {
4140 case 0x08: /* Load/store exclusive */
4141 disas_ldst_excl(s
, insn
);
4143 case 0x18: case 0x1c: /* Load register (literal) */
4144 disas_ld_lit(s
, insn
);
4146 case 0x28: case 0x29:
4147 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4148 disas_ldst_pair(s
, insn
);
4150 case 0x38: case 0x39:
4151 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4152 disas_ldst_reg(s
, insn
);
4154 case 0x0c: /* AdvSIMD load/store multiple structures */
4155 disas_ldst_multiple_struct(s
, insn
);
4157 case 0x0d: /* AdvSIMD load/store single structure */
4158 disas_ldst_single_struct(s
, insn
);
4161 if (extract32(insn
, 21, 1) != 0) {
4162 disas_ldst_tag(s
, insn
);
4163 } else if (extract32(insn
, 10, 2) == 0) {
4164 disas_ldst_ldapr_stlr(s
, insn
);
4166 unallocated_encoding(s
);
4170 unallocated_encoding(s
);
4175 /* PC-rel. addressing
4176 * 31 30 29 28 24 23 5 4 0
4177 * +----+-------+-----------+-------------------+------+
4178 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4179 * +----+-------+-----------+-------------------+------+
4181 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4183 unsigned int page
, rd
;
4186 page
= extract32(insn
, 31, 1);
4187 /* SignExtend(immhi:immlo) -> offset */
4188 offset
= sextract64(insn
, 5, 19);
4189 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4190 rd
= extract32(insn
, 0, 5);
4193 /* ADRP (page based) */
4195 /* The page offset is ok for CF_PCREL. */
4196 offset
-= s
->pc_curr
& 0xfff;
4199 gen_pc_plus_diff(s
, cpu_reg(s
, rd
), offset
);
4203 * Add/subtract (immediate)
4205 * 31 30 29 28 23 22 21 10 9 5 4 0
4206 * +--+--+--+-------------+--+-------------+-----+-----+
4207 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4208 * +--+--+--+-------------+--+-------------+-----+-----+
4210 * sf: 0 -> 32bit, 1 -> 64bit
4211 * op: 0 -> add , 1 -> sub
4213 * sh: 1 -> LSL imm by 12
4215 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4217 int rd
= extract32(insn
, 0, 5);
4218 int rn
= extract32(insn
, 5, 5);
4219 uint64_t imm
= extract32(insn
, 10, 12);
4220 bool shift
= extract32(insn
, 22, 1);
4221 bool setflags
= extract32(insn
, 29, 1);
4222 bool sub_op
= extract32(insn
, 30, 1);
4223 bool is_64bit
= extract32(insn
, 31, 1);
4225 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4226 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4227 TCGv_i64 tcg_result
;
4233 tcg_result
= tcg_temp_new_i64();
4236 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4238 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4241 TCGv_i64 tcg_imm
= tcg_constant_i64(imm
);
4243 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4245 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4250 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4252 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4257 * Add/subtract (immediate, with tags)
4259 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4260 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4261 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4262 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4264 * op: 0 -> add, 1 -> sub
4266 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4268 int rd
= extract32(insn
, 0, 5);
4269 int rn
= extract32(insn
, 5, 5);
4270 int uimm4
= extract32(insn
, 10, 4);
4271 int uimm6
= extract32(insn
, 16, 6);
4272 bool sub_op
= extract32(insn
, 30, 1);
4273 TCGv_i64 tcg_rn
, tcg_rd
;
4276 /* Test all of sf=1, S=0, o2=0, o3=0. */
4277 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4278 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4279 unallocated_encoding(s
);
4283 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4288 tcg_rn
= cpu_reg_sp(s
, rn
);
4289 tcg_rd
= cpu_reg_sp(s
, rd
);
4292 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
,
4293 tcg_constant_i32(imm
),
4294 tcg_constant_i32(uimm4
));
4296 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4297 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4301 /* The input should be a value in the bottom e bits (with higher
4302 * bits zero); returns that value replicated into every element
4303 * of size e in a 64 bit integer.
4305 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4315 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4316 static inline uint64_t bitmask64(unsigned int length
)
4318 assert(length
> 0 && length
<= 64);
4319 return ~0ULL >> (64 - length
);
4322 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4323 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4324 * value (ie should cause a guest UNDEF exception), and true if they are
4325 * valid, in which case the decoded bit pattern is written to result.
4327 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4328 unsigned int imms
, unsigned int immr
)
4331 unsigned e
, levels
, s
, r
;
4334 assert(immn
< 2 && imms
< 64 && immr
< 64);
4336 /* The bit patterns we create here are 64 bit patterns which
4337 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4338 * 64 bits each. Each element contains the same value: a run
4339 * of between 1 and e-1 non-zero bits, rotated within the
4340 * element by between 0 and e-1 bits.
4342 * The element size and run length are encoded into immn (1 bit)
4343 * and imms (6 bits) as follows:
4344 * 64 bit elements: immn = 1, imms = <length of run - 1>
4345 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4346 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4347 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4348 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4349 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4350 * Notice that immn = 0, imms = 11111x is the only combination
4351 * not covered by one of the above options; this is reserved.
4352 * Further, <length of run - 1> all-ones is a reserved pattern.
4354 * In all cases the rotation is by immr % e (and immr is 6 bits).
4357 /* First determine the element size */
4358 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4360 /* This is the immn == 0, imms == 0x11111x case */
4370 /* <length of run - 1> mustn't be all-ones. */
4374 /* Create the value of one element: s+1 set bits rotated
4375 * by r within the element (which is e bits wide)...
4377 mask
= bitmask64(s
+ 1);
4379 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4380 mask
&= bitmask64(e
);
4382 /* ...then replicate the element over the whole 64 bit value */
4383 mask
= bitfield_replicate(mask
, e
);
4388 /* Logical (immediate)
4389 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4390 * +----+-----+-------------+---+------+------+------+------+
4391 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4392 * +----+-----+-------------+---+------+------+------+------+
4394 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4396 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4397 TCGv_i64 tcg_rd
, tcg_rn
;
4399 bool is_and
= false;
4401 sf
= extract32(insn
, 31, 1);
4402 opc
= extract32(insn
, 29, 2);
4403 is_n
= extract32(insn
, 22, 1);
4404 immr
= extract32(insn
, 16, 6);
4405 imms
= extract32(insn
, 10, 6);
4406 rn
= extract32(insn
, 5, 5);
4407 rd
= extract32(insn
, 0, 5);
4410 unallocated_encoding(s
);
4414 if (opc
== 0x3) { /* ANDS */
4415 tcg_rd
= cpu_reg(s
, rd
);
4417 tcg_rd
= cpu_reg_sp(s
, rd
);
4419 tcg_rn
= cpu_reg(s
, rn
);
4421 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4422 /* some immediate field values are reserved */
4423 unallocated_encoding(s
);
4428 wmask
&= 0xffffffff;
4432 case 0x3: /* ANDS */
4434 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4438 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4441 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4444 assert(FALSE
); /* must handle all above */
4448 if (!sf
&& !is_and
) {
4449 /* zero extend final result; we know we can skip this for AND
4450 * since the immediate had the high 32 bits clear.
4452 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4455 if (opc
== 3) { /* ANDS */
4456 gen_logic_CC(sf
, tcg_rd
);
4461 * Move wide (immediate)
4463 * 31 30 29 28 23 22 21 20 5 4 0
4464 * +--+-----+-------------+-----+----------------+------+
4465 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4466 * +--+-----+-------------+-----+----------------+------+
4468 * sf: 0 -> 32 bit, 1 -> 64 bit
4469 * opc: 00 -> N, 10 -> Z, 11 -> K
4470 * hw: shift/16 (0,16, and sf only 32, 48)
4472 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4474 int rd
= extract32(insn
, 0, 5);
4475 uint64_t imm
= extract32(insn
, 5, 16);
4476 int sf
= extract32(insn
, 31, 1);
4477 int opc
= extract32(insn
, 29, 2);
4478 int pos
= extract32(insn
, 21, 2) << 4;
4479 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4481 if (!sf
&& (pos
>= 32)) {
4482 unallocated_encoding(s
);
4496 tcg_gen_movi_i64(tcg_rd
, imm
);
4499 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_constant_i64(imm
), pos
, 16);
4501 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4505 unallocated_encoding(s
);
4511 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4512 * +----+-----+-------------+---+------+------+------+------+
4513 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4514 * +----+-----+-------------+---+------+------+------+------+
4516 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4518 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4519 TCGv_i64 tcg_rd
, tcg_tmp
;
4521 sf
= extract32(insn
, 31, 1);
4522 opc
= extract32(insn
, 29, 2);
4523 n
= extract32(insn
, 22, 1);
4524 ri
= extract32(insn
, 16, 6);
4525 si
= extract32(insn
, 10, 6);
4526 rn
= extract32(insn
, 5, 5);
4527 rd
= extract32(insn
, 0, 5);
4528 bitsize
= sf
? 64 : 32;
4530 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4531 unallocated_encoding(s
);
4535 tcg_rd
= cpu_reg(s
, rd
);
4537 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4538 to be smaller than bitsize, we'll never reference data outside the
4539 low 32-bits anyway. */
4540 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4542 /* Recognize simple(r) extractions. */
4544 /* Wd<s-r:0> = Wn<s:r> */
4545 len
= (si
- ri
) + 1;
4546 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4547 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4549 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4550 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4553 /* opc == 1, BFXIL fall through to deposit */
4554 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4557 /* Handle the ri > si case with a deposit
4558 * Wd<32+s-r,32-r> = Wn<s:0>
4561 pos
= (bitsize
- ri
) & (bitsize
- 1);
4564 if (opc
== 0 && len
< ri
) {
4565 /* SBFM: sign extend the destination field from len to fill
4566 the balance of the word. Let the deposit below insert all
4567 of those sign bits. */
4568 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4572 if (opc
== 1) { /* BFM, BFXIL */
4573 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4575 /* SBFM or UBFM: We start with zero, and we haven't modified
4576 any bits outside bitsize, therefore the zero-extension
4577 below is unneeded. */
4578 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4583 if (!sf
) { /* zero extend final result */
4584 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4589 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4590 * +----+------+-------------+---+----+------+--------+------+------+
4591 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4592 * +----+------+-------------+---+----+------+--------+------+------+
4594 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4596 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4598 sf
= extract32(insn
, 31, 1);
4599 n
= extract32(insn
, 22, 1);
4600 rm
= extract32(insn
, 16, 5);
4601 imm
= extract32(insn
, 10, 6);
4602 rn
= extract32(insn
, 5, 5);
4603 rd
= extract32(insn
, 0, 5);
4604 op21
= extract32(insn
, 29, 2);
4605 op0
= extract32(insn
, 21, 1);
4606 bitsize
= sf
? 64 : 32;
4608 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4609 unallocated_encoding(s
);
4611 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4613 tcg_rd
= cpu_reg(s
, rd
);
4615 if (unlikely(imm
== 0)) {
4616 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4617 * so an extract from bit 0 is a special case.
4620 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4622 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4625 tcg_rm
= cpu_reg(s
, rm
);
4626 tcg_rn
= cpu_reg(s
, rn
);
4629 /* Specialization to ROR happens in EXTRACT2. */
4630 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4632 TCGv_i32 t0
= tcg_temp_new_i32();
4634 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4636 tcg_gen_rotri_i32(t0
, t0
, imm
);
4638 TCGv_i32 t1
= tcg_temp_new_i32();
4639 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4640 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4642 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4648 /* Data processing - immediate */
4649 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4651 switch (extract32(insn
, 23, 6)) {
4652 case 0x20: case 0x21: /* PC-rel. addressing */
4653 disas_pc_rel_adr(s
, insn
);
4655 case 0x22: /* Add/subtract (immediate) */
4656 disas_add_sub_imm(s
, insn
);
4658 case 0x23: /* Add/subtract (immediate, with tags) */
4659 disas_add_sub_imm_with_tags(s
, insn
);
4661 case 0x24: /* Logical (immediate) */
4662 disas_logic_imm(s
, insn
);
4664 case 0x25: /* Move wide (immediate) */
4665 disas_movw_imm(s
, insn
);
4667 case 0x26: /* Bitfield */
4668 disas_bitfield(s
, insn
);
4670 case 0x27: /* Extract */
4671 disas_extract(s
, insn
);
4674 unallocated_encoding(s
);
4679 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4680 * Note that it is the caller's responsibility to ensure that the
4681 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4682 * mandated semantics for out of range shifts.
4684 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4685 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4687 switch (shift_type
) {
4688 case A64_SHIFT_TYPE_LSL
:
4689 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4691 case A64_SHIFT_TYPE_LSR
:
4692 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4694 case A64_SHIFT_TYPE_ASR
:
4696 tcg_gen_ext32s_i64(dst
, src
);
4698 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4700 case A64_SHIFT_TYPE_ROR
:
4702 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4705 t0
= tcg_temp_new_i32();
4706 t1
= tcg_temp_new_i32();
4707 tcg_gen_extrl_i64_i32(t0
, src
);
4708 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4709 tcg_gen_rotr_i32(t0
, t0
, t1
);
4710 tcg_gen_extu_i32_i64(dst
, t0
);
4714 assert(FALSE
); /* all shift types should be handled */
4718 if (!sf
) { /* zero extend final result */
4719 tcg_gen_ext32u_i64(dst
, dst
);
4723 /* Shift a TCGv src by immediate, put result in dst.
4724 * The shift amount must be in range (this should always be true as the
4725 * relevant instructions will UNDEF on bad shift immediates).
4727 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4728 enum a64_shift_type shift_type
, unsigned int shift_i
)
4730 assert(shift_i
< (sf
? 64 : 32));
4733 tcg_gen_mov_i64(dst
, src
);
4735 shift_reg(dst
, src
, sf
, shift_type
, tcg_constant_i64(shift_i
));
4739 /* Logical (shifted register)
4740 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4741 * +----+-----+-----------+-------+---+------+--------+------+------+
4742 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4743 * +----+-----+-----------+-------+---+------+--------+------+------+
4745 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4747 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4748 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4750 sf
= extract32(insn
, 31, 1);
4751 opc
= extract32(insn
, 29, 2);
4752 shift_type
= extract32(insn
, 22, 2);
4753 invert
= extract32(insn
, 21, 1);
4754 rm
= extract32(insn
, 16, 5);
4755 shift_amount
= extract32(insn
, 10, 6);
4756 rn
= extract32(insn
, 5, 5);
4757 rd
= extract32(insn
, 0, 5);
4759 if (!sf
&& (shift_amount
& (1 << 5))) {
4760 unallocated_encoding(s
);
4764 tcg_rd
= cpu_reg(s
, rd
);
4766 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4767 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4768 * register-register MOV and MVN, so it is worth special casing.
4770 tcg_rm
= cpu_reg(s
, rm
);
4772 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4774 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4778 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4780 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4786 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4789 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4792 tcg_rn
= cpu_reg(s
, rn
);
4794 switch (opc
| (invert
<< 2)) {
4797 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4800 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4803 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4807 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4810 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4813 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4821 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4825 gen_logic_CC(sf
, tcg_rd
);
4830 * Add/subtract (extended register)
4832 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4833 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4834 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4835 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4837 * sf: 0 -> 32bit, 1 -> 64bit
4838 * op: 0 -> add , 1 -> sub
4841 * option: extension type (see DecodeRegExtend)
4842 * imm3: optional shift to Rm
4844 * Rd = Rn + LSL(extend(Rm), amount)
4846 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4848 int rd
= extract32(insn
, 0, 5);
4849 int rn
= extract32(insn
, 5, 5);
4850 int imm3
= extract32(insn
, 10, 3);
4851 int option
= extract32(insn
, 13, 3);
4852 int rm
= extract32(insn
, 16, 5);
4853 int opt
= extract32(insn
, 22, 2);
4854 bool setflags
= extract32(insn
, 29, 1);
4855 bool sub_op
= extract32(insn
, 30, 1);
4856 bool sf
= extract32(insn
, 31, 1);
4858 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4860 TCGv_i64 tcg_result
;
4862 if (imm3
> 4 || opt
!= 0) {
4863 unallocated_encoding(s
);
4867 /* non-flag setting ops may use SP */
4869 tcg_rd
= cpu_reg_sp(s
, rd
);
4871 tcg_rd
= cpu_reg(s
, rd
);
4873 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4875 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4876 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4878 tcg_result
= tcg_temp_new_i64();
4882 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4884 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4888 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4890 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4895 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4897 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4902 * Add/subtract (shifted register)
4904 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4905 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4906 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4907 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4909 * sf: 0 -> 32bit, 1 -> 64bit
4910 * op: 0 -> add , 1 -> sub
4912 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4913 * imm6: Shift amount to apply to Rm before the add/sub
4915 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4917 int rd
= extract32(insn
, 0, 5);
4918 int rn
= extract32(insn
, 5, 5);
4919 int imm6
= extract32(insn
, 10, 6);
4920 int rm
= extract32(insn
, 16, 5);
4921 int shift_type
= extract32(insn
, 22, 2);
4922 bool setflags
= extract32(insn
, 29, 1);
4923 bool sub_op
= extract32(insn
, 30, 1);
4924 bool sf
= extract32(insn
, 31, 1);
4926 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4927 TCGv_i64 tcg_rn
, tcg_rm
;
4928 TCGv_i64 tcg_result
;
4930 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4931 unallocated_encoding(s
);
4935 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4936 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4938 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4940 tcg_result
= tcg_temp_new_i64();
4944 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4946 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4950 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4952 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4957 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4959 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4963 /* Data-processing (3 source)
4965 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4966 * +--+------+-----------+------+------+----+------+------+------+
4967 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4968 * +--+------+-----------+------+------+----+------+------+------+
4970 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4972 int rd
= extract32(insn
, 0, 5);
4973 int rn
= extract32(insn
, 5, 5);
4974 int ra
= extract32(insn
, 10, 5);
4975 int rm
= extract32(insn
, 16, 5);
4976 int op_id
= (extract32(insn
, 29, 3) << 4) |
4977 (extract32(insn
, 21, 3) << 1) |
4978 extract32(insn
, 15, 1);
4979 bool sf
= extract32(insn
, 31, 1);
4980 bool is_sub
= extract32(op_id
, 0, 1);
4981 bool is_high
= extract32(op_id
, 2, 1);
4982 bool is_signed
= false;
4987 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4989 case 0x42: /* SMADDL */
4990 case 0x43: /* SMSUBL */
4991 case 0x44: /* SMULH */
4994 case 0x0: /* MADD (32bit) */
4995 case 0x1: /* MSUB (32bit) */
4996 case 0x40: /* MADD (64bit) */
4997 case 0x41: /* MSUB (64bit) */
4998 case 0x4a: /* UMADDL */
4999 case 0x4b: /* UMSUBL */
5000 case 0x4c: /* UMULH */
5003 unallocated_encoding(s
);
5008 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5009 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5010 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5011 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5014 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5016 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5021 tcg_op1
= tcg_temp_new_i64();
5022 tcg_op2
= tcg_temp_new_i64();
5023 tcg_tmp
= tcg_temp_new_i64();
5026 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5027 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5030 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5031 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5033 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5034 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5038 if (ra
== 31 && !is_sub
) {
5039 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5040 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5042 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5044 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5046 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5051 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5055 /* Add/subtract (with carry)
5056 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5057 * +--+--+--+------------------------+------+-------------+------+-----+
5058 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5059 * +--+--+--+------------------------+------+-------------+------+-----+
5062 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5064 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5065 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5067 sf
= extract32(insn
, 31, 1);
5068 op
= extract32(insn
, 30, 1);
5069 setflags
= extract32(insn
, 29, 1);
5070 rm
= extract32(insn
, 16, 5);
5071 rn
= extract32(insn
, 5, 5);
5072 rd
= extract32(insn
, 0, 5);
5074 tcg_rd
= cpu_reg(s
, rd
);
5075 tcg_rn
= cpu_reg(s
, rn
);
5078 tcg_y
= tcg_temp_new_i64();
5079 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5081 tcg_y
= cpu_reg(s
, rm
);
5085 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5087 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5092 * Rotate right into flags
5093 * 31 30 29 21 15 10 5 4 0
5094 * +--+--+--+-----------------+--------+-----------+------+--+------+
5095 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5096 * +--+--+--+-----------------+--------+-----------+------+--+------+
5098 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5100 int mask
= extract32(insn
, 0, 4);
5101 int o2
= extract32(insn
, 4, 1);
5102 int rn
= extract32(insn
, 5, 5);
5103 int imm6
= extract32(insn
, 15, 6);
5104 int sf_op_s
= extract32(insn
, 29, 3);
5108 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5109 unallocated_encoding(s
);
5113 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5114 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5116 nzcv
= tcg_temp_new_i32();
5117 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5119 if (mask
& 8) { /* N */
5120 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5122 if (mask
& 4) { /* Z */
5123 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5124 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5126 if (mask
& 2) { /* C */
5127 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5129 if (mask
& 1) { /* V */
5130 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5135 * Evaluate into flags
5136 * 31 30 29 21 15 14 10 5 4 0
5137 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5138 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5139 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5141 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5143 int o3_mask
= extract32(insn
, 0, 5);
5144 int rn
= extract32(insn
, 5, 5);
5145 int o2
= extract32(insn
, 15, 6);
5146 int sz
= extract32(insn
, 14, 1);
5147 int sf_op_s
= extract32(insn
, 29, 3);
5151 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5152 !dc_isar_feature(aa64_condm_4
, s
)) {
5153 unallocated_encoding(s
);
5156 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5158 tmp
= tcg_temp_new_i32();
5159 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5160 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5161 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5162 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5163 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5166 /* Conditional compare (immediate / register)
5167 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5168 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5169 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5170 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5173 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5175 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5176 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5177 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5180 if (!extract32(insn
, 29, 1)) {
5181 unallocated_encoding(s
);
5184 if (insn
& (1 << 10 | 1 << 4)) {
5185 unallocated_encoding(s
);
5188 sf
= extract32(insn
, 31, 1);
5189 op
= extract32(insn
, 30, 1);
5190 is_imm
= extract32(insn
, 11, 1);
5191 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5192 cond
= extract32(insn
, 12, 4);
5193 rn
= extract32(insn
, 5, 5);
5194 nzcv
= extract32(insn
, 0, 4);
5196 /* Set T0 = !COND. */
5197 tcg_t0
= tcg_temp_new_i32();
5198 arm_test_cc(&c
, cond
);
5199 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5201 /* Load the arguments for the new comparison. */
5203 tcg_y
= tcg_temp_new_i64();
5204 tcg_gen_movi_i64(tcg_y
, y
);
5206 tcg_y
= cpu_reg(s
, y
);
5208 tcg_rn
= cpu_reg(s
, rn
);
5210 /* Set the flags for the new comparison. */
5211 tcg_tmp
= tcg_temp_new_i64();
5213 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5215 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5218 /* If COND was false, force the flags to #nzcv. Compute two masks
5219 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5220 * For tcg hosts that support ANDC, we can make do with just T1.
5221 * In either case, allow the tcg optimizer to delete any unused mask.
5223 tcg_t1
= tcg_temp_new_i32();
5224 tcg_t2
= tcg_temp_new_i32();
5225 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5226 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5228 if (nzcv
& 8) { /* N */
5229 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5231 if (TCG_TARGET_HAS_andc_i32
) {
5232 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5234 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5237 if (nzcv
& 4) { /* Z */
5238 if (TCG_TARGET_HAS_andc_i32
) {
5239 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5241 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5244 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5246 if (nzcv
& 2) { /* C */
5247 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5249 if (TCG_TARGET_HAS_andc_i32
) {
5250 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5252 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5255 if (nzcv
& 1) { /* V */
5256 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5258 if (TCG_TARGET_HAS_andc_i32
) {
5259 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5261 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5266 /* Conditional select
5267 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5268 * +----+----+---+-----------------+------+------+-----+------+------+
5269 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5270 * +----+----+---+-----------------+------+------+-----+------+------+
5272 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5274 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5275 TCGv_i64 tcg_rd
, zero
;
5278 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5279 /* S == 1 or op2<1> == 1 */
5280 unallocated_encoding(s
);
5283 sf
= extract32(insn
, 31, 1);
5284 else_inv
= extract32(insn
, 30, 1);
5285 rm
= extract32(insn
, 16, 5);
5286 cond
= extract32(insn
, 12, 4);
5287 else_inc
= extract32(insn
, 10, 1);
5288 rn
= extract32(insn
, 5, 5);
5289 rd
= extract32(insn
, 0, 5);
5291 tcg_rd
= cpu_reg(s
, rd
);
5293 a64_test_cc(&c
, cond
);
5294 zero
= tcg_constant_i64(0);
5296 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5298 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5300 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5303 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5304 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5305 if (else_inv
&& else_inc
) {
5306 tcg_gen_neg_i64(t_false
, t_false
);
5307 } else if (else_inv
) {
5308 tcg_gen_not_i64(t_false
, t_false
);
5309 } else if (else_inc
) {
5310 tcg_gen_addi_i64(t_false
, t_false
, 1);
5312 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5316 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5320 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5321 unsigned int rn
, unsigned int rd
)
5323 TCGv_i64 tcg_rd
, tcg_rn
;
5324 tcg_rd
= cpu_reg(s
, rd
);
5325 tcg_rn
= cpu_reg(s
, rn
);
5328 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5330 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5331 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5332 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5333 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5337 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5338 unsigned int rn
, unsigned int rd
)
5340 TCGv_i64 tcg_rd
, tcg_rn
;
5341 tcg_rd
= cpu_reg(s
, rd
);
5342 tcg_rn
= cpu_reg(s
, rn
);
5345 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5347 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5348 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5349 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5350 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5354 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5355 unsigned int rn
, unsigned int rd
)
5357 TCGv_i64 tcg_rd
, tcg_rn
;
5358 tcg_rd
= cpu_reg(s
, rd
);
5359 tcg_rn
= cpu_reg(s
, rn
);
5362 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5364 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5365 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5366 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5367 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5371 /* REV with sf==1, opcode==3 ("REV64") */
5372 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5373 unsigned int rn
, unsigned int rd
)
5376 unallocated_encoding(s
);
5379 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5382 /* REV with sf==0, opcode==2
5383 * REV32 (sf==1, opcode==2)
5385 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5386 unsigned int rn
, unsigned int rd
)
5388 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5389 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5392 tcg_gen_bswap64_i64(tcg_rd
, tcg_rn
);
5393 tcg_gen_rotri_i64(tcg_rd
, tcg_rd
, 32);
5395 tcg_gen_bswap32_i64(tcg_rd
, tcg_rn
, TCG_BSWAP_OZ
);
5399 /* REV16 (opcode==1) */
5400 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5401 unsigned int rn
, unsigned int rd
)
5403 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5404 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5405 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5406 TCGv_i64 mask
= tcg_constant_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5408 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5409 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5410 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5411 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5412 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5415 /* Data-processing (1 source)
5416 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5417 * +----+---+---+-----------------+---------+--------+------+------+
5418 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5419 * +----+---+---+-----------------+---------+--------+------+------+
5421 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5423 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5426 if (extract32(insn
, 29, 1)) {
5427 unallocated_encoding(s
);
5431 sf
= extract32(insn
, 31, 1);
5432 opcode
= extract32(insn
, 10, 6);
5433 opcode2
= extract32(insn
, 16, 5);
5434 rn
= extract32(insn
, 5, 5);
5435 rd
= extract32(insn
, 0, 5);
5437 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5439 switch (MAP(sf
, opcode2
, opcode
)) {
5440 case MAP(0, 0x00, 0x00): /* RBIT */
5441 case MAP(1, 0x00, 0x00):
5442 handle_rbit(s
, sf
, rn
, rd
);
5444 case MAP(0, 0x00, 0x01): /* REV16 */
5445 case MAP(1, 0x00, 0x01):
5446 handle_rev16(s
, sf
, rn
, rd
);
5448 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5449 case MAP(1, 0x00, 0x02):
5450 handle_rev32(s
, sf
, rn
, rd
);
5452 case MAP(1, 0x00, 0x03): /* REV64 */
5453 handle_rev64(s
, sf
, rn
, rd
);
5455 case MAP(0, 0x00, 0x04): /* CLZ */
5456 case MAP(1, 0x00, 0x04):
5457 handle_clz(s
, sf
, rn
, rd
);
5459 case MAP(0, 0x00, 0x05): /* CLS */
5460 case MAP(1, 0x00, 0x05):
5461 handle_cls(s
, sf
, rn
, rd
);
5463 case MAP(1, 0x01, 0x00): /* PACIA */
5464 if (s
->pauth_active
) {
5465 tcg_rd
= cpu_reg(s
, rd
);
5466 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5467 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5468 goto do_unallocated
;
5471 case MAP(1, 0x01, 0x01): /* PACIB */
5472 if (s
->pauth_active
) {
5473 tcg_rd
= cpu_reg(s
, rd
);
5474 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5475 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5476 goto do_unallocated
;
5479 case MAP(1, 0x01, 0x02): /* PACDA */
5480 if (s
->pauth_active
) {
5481 tcg_rd
= cpu_reg(s
, rd
);
5482 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5483 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5484 goto do_unallocated
;
5487 case MAP(1, 0x01, 0x03): /* PACDB */
5488 if (s
->pauth_active
) {
5489 tcg_rd
= cpu_reg(s
, rd
);
5490 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5491 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5492 goto do_unallocated
;
5495 case MAP(1, 0x01, 0x04): /* AUTIA */
5496 if (s
->pauth_active
) {
5497 tcg_rd
= cpu_reg(s
, rd
);
5498 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5499 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5500 goto do_unallocated
;
5503 case MAP(1, 0x01, 0x05): /* AUTIB */
5504 if (s
->pauth_active
) {
5505 tcg_rd
= cpu_reg(s
, rd
);
5506 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5507 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5508 goto do_unallocated
;
5511 case MAP(1, 0x01, 0x06): /* AUTDA */
5512 if (s
->pauth_active
) {
5513 tcg_rd
= cpu_reg(s
, rd
);
5514 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5515 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5516 goto do_unallocated
;
5519 case MAP(1, 0x01, 0x07): /* AUTDB */
5520 if (s
->pauth_active
) {
5521 tcg_rd
= cpu_reg(s
, rd
);
5522 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5523 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5524 goto do_unallocated
;
5527 case MAP(1, 0x01, 0x08): /* PACIZA */
5528 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5529 goto do_unallocated
;
5530 } else if (s
->pauth_active
) {
5531 tcg_rd
= cpu_reg(s
, rd
);
5532 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5535 case MAP(1, 0x01, 0x09): /* PACIZB */
5536 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5537 goto do_unallocated
;
5538 } else if (s
->pauth_active
) {
5539 tcg_rd
= cpu_reg(s
, rd
);
5540 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5543 case MAP(1, 0x01, 0x0a): /* PACDZA */
5544 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5545 goto do_unallocated
;
5546 } else if (s
->pauth_active
) {
5547 tcg_rd
= cpu_reg(s
, rd
);
5548 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5551 case MAP(1, 0x01, 0x0b): /* PACDZB */
5552 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5553 goto do_unallocated
;
5554 } else if (s
->pauth_active
) {
5555 tcg_rd
= cpu_reg(s
, rd
);
5556 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5559 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5560 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5561 goto do_unallocated
;
5562 } else if (s
->pauth_active
) {
5563 tcg_rd
= cpu_reg(s
, rd
);
5564 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5567 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5568 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5569 goto do_unallocated
;
5570 } else if (s
->pauth_active
) {
5571 tcg_rd
= cpu_reg(s
, rd
);
5572 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5575 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5576 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5577 goto do_unallocated
;
5578 } else if (s
->pauth_active
) {
5579 tcg_rd
= cpu_reg(s
, rd
);
5580 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5583 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5584 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5585 goto do_unallocated
;
5586 } else if (s
->pauth_active
) {
5587 tcg_rd
= cpu_reg(s
, rd
);
5588 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5591 case MAP(1, 0x01, 0x10): /* XPACI */
5592 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5593 goto do_unallocated
;
5594 } else if (s
->pauth_active
) {
5595 tcg_rd
= cpu_reg(s
, rd
);
5596 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5599 case MAP(1, 0x01, 0x11): /* XPACD */
5600 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5601 goto do_unallocated
;
5602 } else if (s
->pauth_active
) {
5603 tcg_rd
= cpu_reg(s
, rd
);
5604 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5609 unallocated_encoding(s
);
5616 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5617 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5619 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5620 tcg_rd
= cpu_reg(s
, rd
);
5622 if (!sf
&& is_signed
) {
5623 tcg_n
= tcg_temp_new_i64();
5624 tcg_m
= tcg_temp_new_i64();
5625 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5626 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5628 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5629 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5633 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5635 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5638 if (!sf
) { /* zero extend final result */
5639 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5643 /* LSLV, LSRV, ASRV, RORV */
5644 static void handle_shift_reg(DisasContext
*s
,
5645 enum a64_shift_type shift_type
, unsigned int sf
,
5646 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5648 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5649 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5650 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5652 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5653 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5656 /* CRC32[BHWX], CRC32C[BHWX] */
5657 static void handle_crc32(DisasContext
*s
,
5658 unsigned int sf
, unsigned int sz
, bool crc32c
,
5659 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5661 TCGv_i64 tcg_acc
, tcg_val
;
5664 if (!dc_isar_feature(aa64_crc32
, s
)
5665 || (sf
== 1 && sz
!= 3)
5666 || (sf
== 0 && sz
== 3)) {
5667 unallocated_encoding(s
);
5672 tcg_val
= cpu_reg(s
, rm
);
5686 g_assert_not_reached();
5688 tcg_val
= tcg_temp_new_i64();
5689 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5692 tcg_acc
= cpu_reg(s
, rn
);
5693 tcg_bytes
= tcg_constant_i32(1 << sz
);
5696 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5698 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5702 /* Data-processing (2 source)
5703 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5704 * +----+---+---+-----------------+------+--------+------+------+
5705 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5706 * +----+---+---+-----------------+------+--------+------+------+
5708 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5710 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5711 sf
= extract32(insn
, 31, 1);
5712 setflag
= extract32(insn
, 29, 1);
5713 rm
= extract32(insn
, 16, 5);
5714 opcode
= extract32(insn
, 10, 6);
5715 rn
= extract32(insn
, 5, 5);
5716 rd
= extract32(insn
, 0, 5);
5718 if (setflag
&& opcode
!= 0) {
5719 unallocated_encoding(s
);
5724 case 0: /* SUBP(S) */
5725 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5726 goto do_unallocated
;
5728 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5730 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5731 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5732 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5733 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5734 tcg_d
= cpu_reg(s
, rd
);
5737 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5739 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5744 handle_div(s
, false, sf
, rm
, rn
, rd
);
5747 handle_div(s
, true, sf
, rm
, rn
, rd
);
5750 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5751 goto do_unallocated
;
5754 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5755 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5757 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5762 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5763 goto do_unallocated
;
5765 TCGv_i64 t
= tcg_temp_new_i64();
5767 tcg_gen_extract_i64(t
, cpu_reg_sp(s
, rn
), 56, 4);
5768 tcg_gen_shl_i64(t
, tcg_constant_i64(1), t
);
5769 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t
);
5773 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5776 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5779 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5782 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5784 case 12: /* PACGA */
5785 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5786 goto do_unallocated
;
5788 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5789 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5798 case 23: /* CRC32 */
5800 int sz
= extract32(opcode
, 0, 2);
5801 bool crc32c
= extract32(opcode
, 2, 1);
5802 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5807 unallocated_encoding(s
);
5813 * Data processing - register
5814 * 31 30 29 28 25 21 20 16 10 0
5815 * +--+---+--+---+-------+-----+-------+-------+---------+
5816 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5817 * +--+---+--+---+-------+-----+-------+-------+---------+
5819 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5821 int op0
= extract32(insn
, 30, 1);
5822 int op1
= extract32(insn
, 28, 1);
5823 int op2
= extract32(insn
, 21, 4);
5824 int op3
= extract32(insn
, 10, 6);
5829 /* Add/sub (extended register) */
5830 disas_add_sub_ext_reg(s
, insn
);
5832 /* Add/sub (shifted register) */
5833 disas_add_sub_reg(s
, insn
);
5836 /* Logical (shifted register) */
5837 disas_logic_reg(s
, insn
);
5845 case 0x00: /* Add/subtract (with carry) */
5846 disas_adc_sbc(s
, insn
);
5849 case 0x01: /* Rotate right into flags */
5851 disas_rotate_right_into_flags(s
, insn
);
5854 case 0x02: /* Evaluate into flags */
5858 disas_evaluate_into_flags(s
, insn
);
5862 goto do_unallocated
;
5866 case 0x2: /* Conditional compare */
5867 disas_cc(s
, insn
); /* both imm and reg forms */
5870 case 0x4: /* Conditional select */
5871 disas_cond_select(s
, insn
);
5874 case 0x6: /* Data-processing */
5875 if (op0
) { /* (1 source) */
5876 disas_data_proc_1src(s
, insn
);
5877 } else { /* (2 source) */
5878 disas_data_proc_2src(s
, insn
);
5881 case 0x8 ... 0xf: /* (3 source) */
5882 disas_data_proc_3src(s
, insn
);
5887 unallocated_encoding(s
);
5892 static void handle_fp_compare(DisasContext
*s
, int size
,
5893 unsigned int rn
, unsigned int rm
,
5894 bool cmp_with_zero
, bool signal_all_nans
)
5896 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5897 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5899 if (size
== MO_64
) {
5900 TCGv_i64 tcg_vn
, tcg_vm
;
5902 tcg_vn
= read_fp_dreg(s
, rn
);
5903 if (cmp_with_zero
) {
5904 tcg_vm
= tcg_constant_i64(0);
5906 tcg_vm
= read_fp_dreg(s
, rm
);
5908 if (signal_all_nans
) {
5909 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5911 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5914 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5915 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5917 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5918 if (cmp_with_zero
) {
5919 tcg_gen_movi_i32(tcg_vm
, 0);
5921 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5926 if (signal_all_nans
) {
5927 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5929 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5933 if (signal_all_nans
) {
5934 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5936 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5940 g_assert_not_reached();
5944 gen_set_nzcv(tcg_flags
);
5947 /* Floating point compare
5948 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5949 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5950 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5951 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5953 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5955 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5958 mos
= extract32(insn
, 29, 3);
5959 type
= extract32(insn
, 22, 2);
5960 rm
= extract32(insn
, 16, 5);
5961 op
= extract32(insn
, 14, 2);
5962 rn
= extract32(insn
, 5, 5);
5963 opc
= extract32(insn
, 3, 2);
5964 op2r
= extract32(insn
, 0, 3);
5966 if (mos
|| op
|| op2r
) {
5967 unallocated_encoding(s
);
5980 if (dc_isar_feature(aa64_fp16
, s
)) {
5985 unallocated_encoding(s
);
5989 if (!fp_access_check(s
)) {
5993 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5996 /* Floating point conditional compare
5997 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5998 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5999 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6000 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6002 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6004 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6005 TCGLabel
*label_continue
= NULL
;
6008 mos
= extract32(insn
, 29, 3);
6009 type
= extract32(insn
, 22, 2);
6010 rm
= extract32(insn
, 16, 5);
6011 cond
= extract32(insn
, 12, 4);
6012 rn
= extract32(insn
, 5, 5);
6013 op
= extract32(insn
, 4, 1);
6014 nzcv
= extract32(insn
, 0, 4);
6017 unallocated_encoding(s
);
6030 if (dc_isar_feature(aa64_fp16
, s
)) {
6035 unallocated_encoding(s
);
6039 if (!fp_access_check(s
)) {
6043 if (cond
< 0x0e) { /* not always */
6044 TCGLabel
*label_match
= gen_new_label();
6045 label_continue
= gen_new_label();
6046 arm_gen_test_cc(cond
, label_match
);
6048 gen_set_nzcv(tcg_constant_i64(nzcv
<< 28));
6049 tcg_gen_br(label_continue
);
6050 gen_set_label(label_match
);
6053 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6056 gen_set_label(label_continue
);
6060 /* Floating point conditional select
6061 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6062 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6063 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6064 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6066 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6068 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6069 TCGv_i64 t_true
, t_false
;
6073 mos
= extract32(insn
, 29, 3);
6074 type
= extract32(insn
, 22, 2);
6075 rm
= extract32(insn
, 16, 5);
6076 cond
= extract32(insn
, 12, 4);
6077 rn
= extract32(insn
, 5, 5);
6078 rd
= extract32(insn
, 0, 5);
6081 unallocated_encoding(s
);
6094 if (dc_isar_feature(aa64_fp16
, s
)) {
6099 unallocated_encoding(s
);
6103 if (!fp_access_check(s
)) {
6107 /* Zero extend sreg & hreg inputs to 64 bits now. */
6108 t_true
= tcg_temp_new_i64();
6109 t_false
= tcg_temp_new_i64();
6110 read_vec_element(s
, t_true
, rn
, 0, sz
);
6111 read_vec_element(s
, t_false
, rm
, 0, sz
);
6113 a64_test_cc(&c
, cond
);
6114 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, tcg_constant_i64(0),
6117 /* Note that sregs & hregs write back zeros to the high bits,
6118 and we've already done the zero-extension. */
6119 write_fp_dreg(s
, rd
, t_true
);
6122 /* Floating-point data-processing (1 source) - half precision */
6123 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6125 TCGv_ptr fpst
= NULL
;
6126 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6127 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6130 case 0x0: /* FMOV */
6131 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6133 case 0x1: /* FABS */
6134 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6136 case 0x2: /* FNEG */
6137 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6139 case 0x3: /* FSQRT */
6140 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6141 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6143 case 0x8: /* FRINTN */
6144 case 0x9: /* FRINTP */
6145 case 0xa: /* FRINTM */
6146 case 0xb: /* FRINTZ */
6147 case 0xc: /* FRINTA */
6151 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6152 tcg_rmode
= gen_set_rmode(opcode
& 7, fpst
);
6153 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6154 gen_restore_rmode(tcg_rmode
, fpst
);
6157 case 0xe: /* FRINTX */
6158 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6159 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6161 case 0xf: /* FRINTI */
6162 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6163 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6166 g_assert_not_reached();
6169 write_fp_sreg(s
, rd
, tcg_res
);
6172 /* Floating-point data-processing (1 source) - single precision */
6173 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6175 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6176 TCGv_i32 tcg_op
, tcg_res
;
6180 tcg_op
= read_fp_sreg(s
, rn
);
6181 tcg_res
= tcg_temp_new_i32();
6184 case 0x0: /* FMOV */
6185 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6187 case 0x1: /* FABS */
6188 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6190 case 0x2: /* FNEG */
6191 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6193 case 0x3: /* FSQRT */
6194 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6196 case 0x6: /* BFCVT */
6197 gen_fpst
= gen_helper_bfcvt
;
6199 case 0x8: /* FRINTN */
6200 case 0x9: /* FRINTP */
6201 case 0xa: /* FRINTM */
6202 case 0xb: /* FRINTZ */
6203 case 0xc: /* FRINTA */
6205 gen_fpst
= gen_helper_rints
;
6207 case 0xe: /* FRINTX */
6208 gen_fpst
= gen_helper_rints_exact
;
6210 case 0xf: /* FRINTI */
6211 gen_fpst
= gen_helper_rints
;
6213 case 0x10: /* FRINT32Z */
6214 rmode
= FPROUNDING_ZERO
;
6215 gen_fpst
= gen_helper_frint32_s
;
6217 case 0x11: /* FRINT32X */
6218 gen_fpst
= gen_helper_frint32_s
;
6220 case 0x12: /* FRINT64Z */
6221 rmode
= FPROUNDING_ZERO
;
6222 gen_fpst
= gen_helper_frint64_s
;
6224 case 0x13: /* FRINT64X */
6225 gen_fpst
= gen_helper_frint64_s
;
6228 g_assert_not_reached();
6231 fpst
= fpstatus_ptr(FPST_FPCR
);
6233 TCGv_i32 tcg_rmode
= gen_set_rmode(rmode
, fpst
);
6234 gen_fpst(tcg_res
, tcg_op
, fpst
);
6235 gen_restore_rmode(tcg_rmode
, fpst
);
6237 gen_fpst(tcg_res
, tcg_op
, fpst
);
6241 write_fp_sreg(s
, rd
, tcg_res
);
6244 /* Floating-point data-processing (1 source) - double precision */
6245 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6247 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6248 TCGv_i64 tcg_op
, tcg_res
;
6253 case 0x0: /* FMOV */
6254 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6258 tcg_op
= read_fp_dreg(s
, rn
);
6259 tcg_res
= tcg_temp_new_i64();
6262 case 0x1: /* FABS */
6263 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6265 case 0x2: /* FNEG */
6266 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6268 case 0x3: /* FSQRT */
6269 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6271 case 0x8: /* FRINTN */
6272 case 0x9: /* FRINTP */
6273 case 0xa: /* FRINTM */
6274 case 0xb: /* FRINTZ */
6275 case 0xc: /* FRINTA */
6277 gen_fpst
= gen_helper_rintd
;
6279 case 0xe: /* FRINTX */
6280 gen_fpst
= gen_helper_rintd_exact
;
6282 case 0xf: /* FRINTI */
6283 gen_fpst
= gen_helper_rintd
;
6285 case 0x10: /* FRINT32Z */
6286 rmode
= FPROUNDING_ZERO
;
6287 gen_fpst
= gen_helper_frint32_d
;
6289 case 0x11: /* FRINT32X */
6290 gen_fpst
= gen_helper_frint32_d
;
6292 case 0x12: /* FRINT64Z */
6293 rmode
= FPROUNDING_ZERO
;
6294 gen_fpst
= gen_helper_frint64_d
;
6296 case 0x13: /* FRINT64X */
6297 gen_fpst
= gen_helper_frint64_d
;
6300 g_assert_not_reached();
6303 fpst
= fpstatus_ptr(FPST_FPCR
);
6305 TCGv_i32 tcg_rmode
= gen_set_rmode(rmode
, fpst
);
6306 gen_fpst(tcg_res
, tcg_op
, fpst
);
6307 gen_restore_rmode(tcg_rmode
, fpst
);
6309 gen_fpst(tcg_res
, tcg_op
, fpst
);
6313 write_fp_dreg(s
, rd
, tcg_res
);
6316 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6317 int rd
, int rn
, int dtype
, int ntype
)
6322 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6324 /* Single to double */
6325 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6326 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6327 write_fp_dreg(s
, rd
, tcg_rd
);
6329 /* Single to half */
6330 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6331 TCGv_i32 ahp
= get_ahp_flag();
6332 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6334 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6335 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6336 write_fp_sreg(s
, rd
, tcg_rd
);
6342 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6343 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6345 /* Double to single */
6346 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6348 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6349 TCGv_i32 ahp
= get_ahp_flag();
6350 /* Double to half */
6351 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6352 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6354 write_fp_sreg(s
, rd
, tcg_rd
);
6359 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6360 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6361 TCGv_i32 tcg_ahp
= get_ahp_flag();
6362 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6364 /* Half to single */
6365 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6366 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6367 write_fp_sreg(s
, rd
, tcg_rd
);
6369 /* Half to double */
6370 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6371 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6372 write_fp_dreg(s
, rd
, tcg_rd
);
6377 g_assert_not_reached();
6381 /* Floating point data-processing (1 source)
6382 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6383 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6384 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6385 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6387 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6389 int mos
= extract32(insn
, 29, 3);
6390 int type
= extract32(insn
, 22, 2);
6391 int opcode
= extract32(insn
, 15, 6);
6392 int rn
= extract32(insn
, 5, 5);
6393 int rd
= extract32(insn
, 0, 5);
6396 goto do_unallocated
;
6400 case 0x4: case 0x5: case 0x7:
6402 /* FCVT between half, single and double precision */
6403 int dtype
= extract32(opcode
, 0, 2);
6404 if (type
== 2 || dtype
== type
) {
6405 goto do_unallocated
;
6407 if (!fp_access_check(s
)) {
6411 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6415 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6416 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6417 goto do_unallocated
;
6423 /* 32-to-32 and 64-to-64 ops */
6426 if (!fp_access_check(s
)) {
6429 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6432 if (!fp_access_check(s
)) {
6435 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6438 if (!dc_isar_feature(aa64_fp16
, s
)) {
6439 goto do_unallocated
;
6442 if (!fp_access_check(s
)) {
6445 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6448 goto do_unallocated
;
6455 if (!dc_isar_feature(aa64_bf16
, s
)) {
6456 goto do_unallocated
;
6458 if (!fp_access_check(s
)) {
6461 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6464 goto do_unallocated
;
6470 unallocated_encoding(s
);
6475 /* Floating-point data-processing (2 source) - single precision */
6476 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6477 int rd
, int rn
, int rm
)
6484 tcg_res
= tcg_temp_new_i32();
6485 fpst
= fpstatus_ptr(FPST_FPCR
);
6486 tcg_op1
= read_fp_sreg(s
, rn
);
6487 tcg_op2
= read_fp_sreg(s
, rm
);
6490 case 0x0: /* FMUL */
6491 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6493 case 0x1: /* FDIV */
6494 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6496 case 0x2: /* FADD */
6497 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6499 case 0x3: /* FSUB */
6500 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6502 case 0x4: /* FMAX */
6503 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6505 case 0x5: /* FMIN */
6506 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6508 case 0x6: /* FMAXNM */
6509 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6511 case 0x7: /* FMINNM */
6512 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6514 case 0x8: /* FNMUL */
6515 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6516 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6520 write_fp_sreg(s
, rd
, tcg_res
);
6523 /* Floating-point data-processing (2 source) - double precision */
6524 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6525 int rd
, int rn
, int rm
)
6532 tcg_res
= tcg_temp_new_i64();
6533 fpst
= fpstatus_ptr(FPST_FPCR
);
6534 tcg_op1
= read_fp_dreg(s
, rn
);
6535 tcg_op2
= read_fp_dreg(s
, rm
);
6538 case 0x0: /* FMUL */
6539 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6541 case 0x1: /* FDIV */
6542 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6544 case 0x2: /* FADD */
6545 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6547 case 0x3: /* FSUB */
6548 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6550 case 0x4: /* FMAX */
6551 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6553 case 0x5: /* FMIN */
6554 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6556 case 0x6: /* FMAXNM */
6557 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6559 case 0x7: /* FMINNM */
6560 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6562 case 0x8: /* FNMUL */
6563 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6564 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6568 write_fp_dreg(s
, rd
, tcg_res
);
6571 /* Floating-point data-processing (2 source) - half precision */
6572 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6573 int rd
, int rn
, int rm
)
6580 tcg_res
= tcg_temp_new_i32();
6581 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6582 tcg_op1
= read_fp_hreg(s
, rn
);
6583 tcg_op2
= read_fp_hreg(s
, rm
);
6586 case 0x0: /* FMUL */
6587 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6589 case 0x1: /* FDIV */
6590 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6592 case 0x2: /* FADD */
6593 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6595 case 0x3: /* FSUB */
6596 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6598 case 0x4: /* FMAX */
6599 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6601 case 0x5: /* FMIN */
6602 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6604 case 0x6: /* FMAXNM */
6605 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6607 case 0x7: /* FMINNM */
6608 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6610 case 0x8: /* FNMUL */
6611 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6612 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6615 g_assert_not_reached();
6618 write_fp_sreg(s
, rd
, tcg_res
);
6621 /* Floating point data-processing (2 source)
6622 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6623 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6624 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6625 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6627 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6629 int mos
= extract32(insn
, 29, 3);
6630 int type
= extract32(insn
, 22, 2);
6631 int rd
= extract32(insn
, 0, 5);
6632 int rn
= extract32(insn
, 5, 5);
6633 int rm
= extract32(insn
, 16, 5);
6634 int opcode
= extract32(insn
, 12, 4);
6636 if (opcode
> 8 || mos
) {
6637 unallocated_encoding(s
);
6643 if (!fp_access_check(s
)) {
6646 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6649 if (!fp_access_check(s
)) {
6652 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6655 if (!dc_isar_feature(aa64_fp16
, s
)) {
6656 unallocated_encoding(s
);
6659 if (!fp_access_check(s
)) {
6662 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6665 unallocated_encoding(s
);
6669 /* Floating-point data-processing (3 source) - single precision */
6670 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6671 int rd
, int rn
, int rm
, int ra
)
6673 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6674 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6675 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6677 tcg_op1
= read_fp_sreg(s
, rn
);
6678 tcg_op2
= read_fp_sreg(s
, rm
);
6679 tcg_op3
= read_fp_sreg(s
, ra
);
6681 /* These are fused multiply-add, and must be done as one
6682 * floating point operation with no rounding between the
6683 * multiplication and addition steps.
6684 * NB that doing the negations here as separate steps is
6685 * correct : an input NaN should come out with its sign bit
6686 * flipped if it is a negated-input.
6689 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6693 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6696 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6698 write_fp_sreg(s
, rd
, tcg_res
);
6701 /* Floating-point data-processing (3 source) - double precision */
6702 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6703 int rd
, int rn
, int rm
, int ra
)
6705 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6706 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6707 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6709 tcg_op1
= read_fp_dreg(s
, rn
);
6710 tcg_op2
= read_fp_dreg(s
, rm
);
6711 tcg_op3
= read_fp_dreg(s
, ra
);
6713 /* These are fused multiply-add, and must be done as one
6714 * floating point operation with no rounding between the
6715 * multiplication and addition steps.
6716 * NB that doing the negations here as separate steps is
6717 * correct : an input NaN should come out with its sign bit
6718 * flipped if it is a negated-input.
6721 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6725 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6728 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6730 write_fp_dreg(s
, rd
, tcg_res
);
6733 /* Floating-point data-processing (3 source) - half precision */
6734 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6735 int rd
, int rn
, int rm
, int ra
)
6737 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6738 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6739 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6741 tcg_op1
= read_fp_hreg(s
, rn
);
6742 tcg_op2
= read_fp_hreg(s
, rm
);
6743 tcg_op3
= read_fp_hreg(s
, ra
);
6745 /* These are fused multiply-add, and must be done as one
6746 * floating point operation with no rounding between the
6747 * multiplication and addition steps.
6748 * NB that doing the negations here as separate steps is
6749 * correct : an input NaN should come out with its sign bit
6750 * flipped if it is a negated-input.
6753 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6757 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6760 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6762 write_fp_sreg(s
, rd
, tcg_res
);
6765 /* Floating point data-processing (3 source)
6766 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6767 * +---+---+---+-----------+------+----+------+----+------+------+------+
6768 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6769 * +---+---+---+-----------+------+----+------+----+------+------+------+
6771 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6773 int mos
= extract32(insn
, 29, 3);
6774 int type
= extract32(insn
, 22, 2);
6775 int rd
= extract32(insn
, 0, 5);
6776 int rn
= extract32(insn
, 5, 5);
6777 int ra
= extract32(insn
, 10, 5);
6778 int rm
= extract32(insn
, 16, 5);
6779 bool o0
= extract32(insn
, 15, 1);
6780 bool o1
= extract32(insn
, 21, 1);
6783 unallocated_encoding(s
);
6789 if (!fp_access_check(s
)) {
6792 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6795 if (!fp_access_check(s
)) {
6798 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6801 if (!dc_isar_feature(aa64_fp16
, s
)) {
6802 unallocated_encoding(s
);
6805 if (!fp_access_check(s
)) {
6808 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6811 unallocated_encoding(s
);
6815 /* Floating point immediate
6816 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6817 * +---+---+---+-----------+------+---+------------+-------+------+------+
6818 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6819 * +---+---+---+-----------+------+---+------------+-------+------+------+
6821 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6823 int rd
= extract32(insn
, 0, 5);
6824 int imm5
= extract32(insn
, 5, 5);
6825 int imm8
= extract32(insn
, 13, 8);
6826 int type
= extract32(insn
, 22, 2);
6827 int mos
= extract32(insn
, 29, 3);
6832 unallocated_encoding(s
);
6845 if (dc_isar_feature(aa64_fp16
, s
)) {
6850 unallocated_encoding(s
);
6854 if (!fp_access_check(s
)) {
6858 imm
= vfp_expand_imm(sz
, imm8
);
6859 write_fp_dreg(s
, rd
, tcg_constant_i64(imm
));
6862 /* Handle floating point <=> fixed point conversions. Note that we can
6863 * also deal with fp <=> integer conversions as a special case (scale == 64)
6864 * OPTME: consider handling that special case specially or at least skipping
6865 * the call to scalbn in the helpers for zero shifts.
6867 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6868 bool itof
, int rmode
, int scale
, int sf
, int type
)
6870 bool is_signed
= !(opcode
& 1);
6871 TCGv_ptr tcg_fpstatus
;
6872 TCGv_i32 tcg_shift
, tcg_single
;
6873 TCGv_i64 tcg_double
;
6875 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
6877 tcg_shift
= tcg_constant_i32(64 - scale
);
6880 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6882 TCGv_i64 tcg_extend
= tcg_temp_new_i64();
6885 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6887 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6890 tcg_int
= tcg_extend
;
6894 case 1: /* float64 */
6895 tcg_double
= tcg_temp_new_i64();
6897 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6898 tcg_shift
, tcg_fpstatus
);
6900 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6901 tcg_shift
, tcg_fpstatus
);
6903 write_fp_dreg(s
, rd
, tcg_double
);
6906 case 0: /* float32 */
6907 tcg_single
= tcg_temp_new_i32();
6909 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6910 tcg_shift
, tcg_fpstatus
);
6912 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6913 tcg_shift
, tcg_fpstatus
);
6915 write_fp_sreg(s
, rd
, tcg_single
);
6918 case 3: /* float16 */
6919 tcg_single
= tcg_temp_new_i32();
6921 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6922 tcg_shift
, tcg_fpstatus
);
6924 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6925 tcg_shift
, tcg_fpstatus
);
6927 write_fp_sreg(s
, rd
, tcg_single
);
6931 g_assert_not_reached();
6934 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6937 if (extract32(opcode
, 2, 1)) {
6938 /* There are too many rounding modes to all fit into rmode,
6939 * so FCVTA[US] is a special case.
6941 rmode
= FPROUNDING_TIEAWAY
;
6944 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
6947 case 1: /* float64 */
6948 tcg_double
= read_fp_dreg(s
, rn
);
6951 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6952 tcg_shift
, tcg_fpstatus
);
6954 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6955 tcg_shift
, tcg_fpstatus
);
6959 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6960 tcg_shift
, tcg_fpstatus
);
6962 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6963 tcg_shift
, tcg_fpstatus
);
6967 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6971 case 0: /* float32 */
6972 tcg_single
= read_fp_sreg(s
, rn
);
6975 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6976 tcg_shift
, tcg_fpstatus
);
6978 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6979 tcg_shift
, tcg_fpstatus
);
6982 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6984 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6985 tcg_shift
, tcg_fpstatus
);
6987 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6988 tcg_shift
, tcg_fpstatus
);
6990 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6994 case 3: /* float16 */
6995 tcg_single
= read_fp_sreg(s
, rn
);
6998 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6999 tcg_shift
, tcg_fpstatus
);
7001 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7002 tcg_shift
, tcg_fpstatus
);
7005 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7007 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7008 tcg_shift
, tcg_fpstatus
);
7010 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7011 tcg_shift
, tcg_fpstatus
);
7013 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7018 g_assert_not_reached();
7021 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
7025 /* Floating point <-> fixed point conversions
7026 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7027 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7028 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7029 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7031 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7033 int rd
= extract32(insn
, 0, 5);
7034 int rn
= extract32(insn
, 5, 5);
7035 int scale
= extract32(insn
, 10, 6);
7036 int opcode
= extract32(insn
, 16, 3);
7037 int rmode
= extract32(insn
, 19, 2);
7038 int type
= extract32(insn
, 22, 2);
7039 bool sbit
= extract32(insn
, 29, 1);
7040 bool sf
= extract32(insn
, 31, 1);
7043 if (sbit
|| (!sf
&& scale
< 32)) {
7044 unallocated_encoding(s
);
7049 case 0: /* float32 */
7050 case 1: /* float64 */
7052 case 3: /* float16 */
7053 if (dc_isar_feature(aa64_fp16
, s
)) {
7058 unallocated_encoding(s
);
7062 switch ((rmode
<< 3) | opcode
) {
7063 case 0x2: /* SCVTF */
7064 case 0x3: /* UCVTF */
7067 case 0x18: /* FCVTZS */
7068 case 0x19: /* FCVTZU */
7072 unallocated_encoding(s
);
7076 if (!fp_access_check(s
)) {
7080 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7083 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7085 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7086 * without conversion.
7090 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7096 tmp
= tcg_temp_new_i64();
7097 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7098 write_fp_dreg(s
, rd
, tmp
);
7102 write_fp_dreg(s
, rd
, tcg_rn
);
7105 /* 64 bit to top half. */
7106 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7107 clear_vec_high(s
, true, rd
);
7111 tmp
= tcg_temp_new_i64();
7112 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7113 write_fp_dreg(s
, rd
, tmp
);
7116 g_assert_not_reached();
7119 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7124 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7128 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7131 /* 64 bits from top half */
7132 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7136 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7139 g_assert_not_reached();
7144 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7146 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7147 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7149 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7151 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7152 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7153 tcg_gen_movi_i32(cpu_CF
, 0);
7154 tcg_gen_movi_i32(cpu_NF
, 0);
7155 tcg_gen_movi_i32(cpu_VF
, 0);
7158 /* Floating point <-> integer conversions
7159 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7160 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7161 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7162 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7164 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7166 int rd
= extract32(insn
, 0, 5);
7167 int rn
= extract32(insn
, 5, 5);
7168 int opcode
= extract32(insn
, 16, 3);
7169 int rmode
= extract32(insn
, 19, 2);
7170 int type
= extract32(insn
, 22, 2);
7171 bool sbit
= extract32(insn
, 29, 1);
7172 bool sf
= extract32(insn
, 31, 1);
7176 goto do_unallocated
;
7184 case 4: /* FCVTAS */
7185 case 5: /* FCVTAU */
7187 goto do_unallocated
;
7190 case 0: /* FCVT[NPMZ]S */
7191 case 1: /* FCVT[NPMZ]U */
7193 case 0: /* float32 */
7194 case 1: /* float64 */
7196 case 3: /* float16 */
7197 if (!dc_isar_feature(aa64_fp16
, s
)) {
7198 goto do_unallocated
;
7202 goto do_unallocated
;
7204 if (!fp_access_check(s
)) {
7207 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7211 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7212 case 0b01100110: /* FMOV half <-> 32-bit int */
7214 case 0b11100110: /* FMOV half <-> 64-bit int */
7216 if (!dc_isar_feature(aa64_fp16
, s
)) {
7217 goto do_unallocated
;
7220 case 0b00000110: /* FMOV 32-bit */
7222 case 0b10100110: /* FMOV 64-bit */
7224 case 0b11001110: /* FMOV top half of 128-bit */
7226 if (!fp_access_check(s
)) {
7230 handle_fmov(s
, rd
, rn
, type
, itof
);
7233 case 0b00111110: /* FJCVTZS */
7234 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7235 goto do_unallocated
;
7236 } else if (fp_access_check(s
)) {
7237 handle_fjcvtzs(s
, rd
, rn
);
7243 unallocated_encoding(s
);
7250 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7251 * 31 30 29 28 25 24 0
7252 * +---+---+---+---------+-----------------------------+
7253 * | | 0 | | 1 1 1 1 | |
7254 * +---+---+---+---------+-----------------------------+
7256 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7258 if (extract32(insn
, 24, 1)) {
7259 /* Floating point data-processing (3 source) */
7260 disas_fp_3src(s
, insn
);
7261 } else if (extract32(insn
, 21, 1) == 0) {
7262 /* Floating point to fixed point conversions */
7263 disas_fp_fixed_conv(s
, insn
);
7265 switch (extract32(insn
, 10, 2)) {
7267 /* Floating point conditional compare */
7268 disas_fp_ccomp(s
, insn
);
7271 /* Floating point data-processing (2 source) */
7272 disas_fp_2src(s
, insn
);
7275 /* Floating point conditional select */
7276 disas_fp_csel(s
, insn
);
7279 switch (ctz32(extract32(insn
, 12, 4))) {
7280 case 0: /* [15:12] == xxx1 */
7281 /* Floating point immediate */
7282 disas_fp_imm(s
, insn
);
7284 case 1: /* [15:12] == xx10 */
7285 /* Floating point compare */
7286 disas_fp_compare(s
, insn
);
7288 case 2: /* [15:12] == x100 */
7289 /* Floating point data-processing (1 source) */
7290 disas_fp_1src(s
, insn
);
7292 case 3: /* [15:12] == 1000 */
7293 unallocated_encoding(s
);
7295 default: /* [15:12] == 0000 */
7296 /* Floating point <-> integer conversions */
7297 disas_fp_int_conv(s
, insn
);
7305 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7308 /* Extract 64 bits from the middle of two concatenated 64 bit
7309 * vector register slices left:right. The extracted bits start
7310 * at 'pos' bits into the right (least significant) side.
7311 * We return the result in tcg_right, and guarantee not to
7314 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7315 assert(pos
> 0 && pos
< 64);
7317 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7318 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7319 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7323 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7324 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7325 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7326 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7328 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7330 int is_q
= extract32(insn
, 30, 1);
7331 int op2
= extract32(insn
, 22, 2);
7332 int imm4
= extract32(insn
, 11, 4);
7333 int rm
= extract32(insn
, 16, 5);
7334 int rn
= extract32(insn
, 5, 5);
7335 int rd
= extract32(insn
, 0, 5);
7336 int pos
= imm4
<< 3;
7337 TCGv_i64 tcg_resl
, tcg_resh
;
7339 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7340 unallocated_encoding(s
);
7344 if (!fp_access_check(s
)) {
7348 tcg_resh
= tcg_temp_new_i64();
7349 tcg_resl
= tcg_temp_new_i64();
7351 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7352 * either extracting 128 bits from a 128:128 concatenation, or
7353 * extracting 64 bits from a 64:64 concatenation.
7356 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7358 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7359 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7367 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7368 EltPosns
*elt
= eltposns
;
7375 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7377 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7380 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7381 tcg_hh
= tcg_temp_new_i64();
7382 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7383 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7387 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7389 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7391 clear_vec_high(s
, is_q
, rd
);
7395 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7396 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7397 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7398 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7400 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7402 int op2
= extract32(insn
, 22, 2);
7403 int is_q
= extract32(insn
, 30, 1);
7404 int rm
= extract32(insn
, 16, 5);
7405 int rn
= extract32(insn
, 5, 5);
7406 int rd
= extract32(insn
, 0, 5);
7407 int is_tbx
= extract32(insn
, 12, 1);
7408 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7411 unallocated_encoding(s
);
7415 if (!fp_access_check(s
)) {
7419 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7420 vec_full_reg_offset(s
, rm
), cpu_env
,
7421 is_q
? 16 : 8, vec_full_reg_size(s
),
7422 (len
<< 6) | (is_tbx
<< 5) | rn
,
7423 gen_helper_simd_tblx
);
7427 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7428 * +---+---+-------------+------+---+------+---+------------------+------+
7429 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7430 * +---+---+-------------+------+---+------+---+------------------+------+
7432 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7434 int rd
= extract32(insn
, 0, 5);
7435 int rn
= extract32(insn
, 5, 5);
7436 int rm
= extract32(insn
, 16, 5);
7437 int size
= extract32(insn
, 22, 2);
7438 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7439 * bit 2 indicates 1 vs 2 variant of the insn.
7441 int opcode
= extract32(insn
, 12, 2);
7442 bool part
= extract32(insn
, 14, 1);
7443 bool is_q
= extract32(insn
, 30, 1);
7444 int esize
= 8 << size
;
7446 int datasize
= is_q
? 128 : 64;
7447 int elements
= datasize
/ esize
;
7448 TCGv_i64 tcg_res
[2], tcg_ele
;
7450 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7451 unallocated_encoding(s
);
7455 if (!fp_access_check(s
)) {
7459 tcg_res
[0] = tcg_temp_new_i64();
7460 tcg_res
[1] = is_q
? tcg_temp_new_i64() : NULL
;
7461 tcg_ele
= tcg_temp_new_i64();
7463 for (i
= 0; i
< elements
; i
++) {
7467 case 1: /* UZP1/2 */
7469 int midpoint
= elements
/ 2;
7471 read_vec_element(s
, tcg_ele
, rn
, 2 * i
+ part
, size
);
7473 read_vec_element(s
, tcg_ele
, rm
,
7474 2 * (i
- midpoint
) + part
, size
);
7478 case 2: /* TRN1/2 */
7480 read_vec_element(s
, tcg_ele
, rm
, (i
& ~1) + part
, size
);
7482 read_vec_element(s
, tcg_ele
, rn
, (i
& ~1) + part
, size
);
7485 case 3: /* ZIP1/2 */
7487 int base
= part
* elements
/ 2;
7489 read_vec_element(s
, tcg_ele
, rm
, base
+ (i
>> 1), size
);
7491 read_vec_element(s
, tcg_ele
, rn
, base
+ (i
>> 1), size
);
7496 g_assert_not_reached();
7499 w
= (i
* esize
) / 64;
7500 o
= (i
* esize
) % 64;
7502 tcg_gen_mov_i64(tcg_res
[w
], tcg_ele
);
7504 tcg_gen_shli_i64(tcg_ele
, tcg_ele
, o
);
7505 tcg_gen_or_i64(tcg_res
[w
], tcg_res
[w
], tcg_ele
);
7509 for (i
= 0; i
<= is_q
; ++i
) {
7510 write_vec_element(s
, tcg_res
[i
], rd
, i
, MO_64
);
7512 clear_vec_high(s
, is_q
, rd
);
7516 * do_reduction_op helper
7518 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7519 * important for correct NaN propagation that we do these
7520 * operations in exactly the order specified by the pseudocode.
7522 * This is a recursive function, TCG temps should be freed by the
7523 * calling function once it is done with the values.
7525 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7526 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7528 if (esize
== size
) {
7530 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7533 /* We should have one register left here */
7534 assert(ctpop8(vmap
) == 1);
7535 element
= ctz32(vmap
);
7536 assert(element
< 8);
7538 tcg_elem
= tcg_temp_new_i32();
7539 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7542 int bits
= size
/ 2;
7543 int shift
= ctpop8(vmap
) / 2;
7544 int vmap_lo
= (vmap
>> shift
) & vmap
;
7545 int vmap_hi
= (vmap
& ~vmap_lo
);
7546 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7548 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7549 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7550 tcg_res
= tcg_temp_new_i32();
7553 case 0x0c: /* fmaxnmv half-precision */
7554 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7556 case 0x0f: /* fmaxv half-precision */
7557 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7559 case 0x1c: /* fminnmv half-precision */
7560 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7562 case 0x1f: /* fminv half-precision */
7563 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7565 case 0x2c: /* fmaxnmv */
7566 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7568 case 0x2f: /* fmaxv */
7569 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7571 case 0x3c: /* fminnmv */
7572 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7574 case 0x3f: /* fminv */
7575 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7578 g_assert_not_reached();
7584 /* AdvSIMD across lanes
7585 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7586 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7587 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7588 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7590 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7592 int rd
= extract32(insn
, 0, 5);
7593 int rn
= extract32(insn
, 5, 5);
7594 int size
= extract32(insn
, 22, 2);
7595 int opcode
= extract32(insn
, 12, 5);
7596 bool is_q
= extract32(insn
, 30, 1);
7597 bool is_u
= extract32(insn
, 29, 1);
7599 bool is_min
= false;
7603 TCGv_i64 tcg_res
, tcg_elt
;
7606 case 0x1b: /* ADDV */
7608 unallocated_encoding(s
);
7612 case 0x3: /* SADDLV, UADDLV */
7613 case 0xa: /* SMAXV, UMAXV */
7614 case 0x1a: /* SMINV, UMINV */
7615 if (size
== 3 || (size
== 2 && !is_q
)) {
7616 unallocated_encoding(s
);
7620 case 0xc: /* FMAXNMV, FMINNMV */
7621 case 0xf: /* FMAXV, FMINV */
7622 /* Bit 1 of size field encodes min vs max and the actual size
7623 * depends on the encoding of the U bit. If not set (and FP16
7624 * enabled) then we do half-precision float instead of single
7627 is_min
= extract32(size
, 1, 1);
7629 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7631 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7632 unallocated_encoding(s
);
7639 unallocated_encoding(s
);
7643 if (!fp_access_check(s
)) {
7648 elements
= (is_q
? 128 : 64) / esize
;
7650 tcg_res
= tcg_temp_new_i64();
7651 tcg_elt
= tcg_temp_new_i64();
7653 /* These instructions operate across all lanes of a vector
7654 * to produce a single result. We can guarantee that a 64
7655 * bit intermediate is sufficient:
7656 * + for [US]ADDLV the maximum element size is 32 bits, and
7657 * the result type is 64 bits
7658 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7659 * same as the element size, which is 32 bits at most
7660 * For the integer operations we can choose to work at 64
7661 * or 32 bits and truncate at the end; for simplicity
7662 * we use 64 bits always. The floating point
7663 * ops do require 32 bit intermediates, though.
7666 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7668 for (i
= 1; i
< elements
; i
++) {
7669 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7672 case 0x03: /* SADDLV / UADDLV */
7673 case 0x1b: /* ADDV */
7674 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7676 case 0x0a: /* SMAXV / UMAXV */
7678 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7680 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7683 case 0x1a: /* SMINV / UMINV */
7685 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7687 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7691 g_assert_not_reached();
7696 /* Floating point vector reduction ops which work across 32
7697 * bit (single) or 16 bit (half-precision) intermediates.
7698 * Note that correct NaN propagation requires that we do these
7699 * operations in exactly the order specified by the pseudocode.
7701 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7702 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7703 int vmap
= (1 << elements
) - 1;
7704 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7705 (is_q
? 128 : 64), vmap
, fpst
);
7706 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7709 /* Now truncate the result to the width required for the final output */
7710 if (opcode
== 0x03) {
7711 /* SADDLV, UADDLV: result is 2*esize */
7717 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7720 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7723 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7728 g_assert_not_reached();
7731 write_fp_dreg(s
, rd
, tcg_res
);
7734 /* DUP (Element, Vector)
7736 * 31 30 29 21 20 16 15 10 9 5 4 0
7737 * +---+---+-------------------+--------+-------------+------+------+
7738 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7739 * +---+---+-------------------+--------+-------------+------+------+
7741 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7743 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7746 int size
= ctz32(imm5
);
7749 if (size
> 3 || (size
== 3 && !is_q
)) {
7750 unallocated_encoding(s
);
7754 if (!fp_access_check(s
)) {
7758 index
= imm5
>> (size
+ 1);
7759 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7760 vec_reg_offset(s
, rn
, index
, size
),
7761 is_q
? 16 : 8, vec_full_reg_size(s
));
7764 /* DUP (element, scalar)
7765 * 31 21 20 16 15 10 9 5 4 0
7766 * +-----------------------+--------+-------------+------+------+
7767 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7768 * +-----------------------+--------+-------------+------+------+
7770 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7773 int size
= ctz32(imm5
);
7778 unallocated_encoding(s
);
7782 if (!fp_access_check(s
)) {
7786 index
= imm5
>> (size
+ 1);
7788 /* This instruction just extracts the specified element and
7789 * zero-extends it into the bottom of the destination register.
7791 tmp
= tcg_temp_new_i64();
7792 read_vec_element(s
, tmp
, rn
, index
, size
);
7793 write_fp_dreg(s
, rd
, tmp
);
7798 * 31 30 29 21 20 16 15 10 9 5 4 0
7799 * +---+---+-------------------+--------+-------------+------+------+
7800 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7801 * +---+---+-------------------+--------+-------------+------+------+
7803 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7805 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7808 int size
= ctz32(imm5
);
7809 uint32_t dofs
, oprsz
, maxsz
;
7811 if (size
> 3 || ((size
== 3) && !is_q
)) {
7812 unallocated_encoding(s
);
7816 if (!fp_access_check(s
)) {
7820 dofs
= vec_full_reg_offset(s
, rd
);
7821 oprsz
= is_q
? 16 : 8;
7822 maxsz
= vec_full_reg_size(s
);
7824 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7829 * 31 21 20 16 15 14 11 10 9 5 4 0
7830 * +-----------------------+--------+------------+---+------+------+
7831 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7832 * +-----------------------+--------+------------+---+------+------+
7834 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7835 * index: encoded in imm5<4:size+1>
7837 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7840 int size
= ctz32(imm5
);
7841 int src_index
, dst_index
;
7845 unallocated_encoding(s
);
7849 if (!fp_access_check(s
)) {
7853 dst_index
= extract32(imm5
, 1+size
, 5);
7854 src_index
= extract32(imm4
, size
, 4);
7856 tmp
= tcg_temp_new_i64();
7858 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7859 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7861 /* INS is considered a 128-bit write for SVE. */
7862 clear_vec_high(s
, true, rd
);
7868 * 31 21 20 16 15 10 9 5 4 0
7869 * +-----------------------+--------+-------------+------+------+
7870 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7871 * +-----------------------+--------+-------------+------+------+
7873 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7874 * index: encoded in imm5<4:size+1>
7876 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7878 int size
= ctz32(imm5
);
7882 unallocated_encoding(s
);
7886 if (!fp_access_check(s
)) {
7890 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7891 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7893 /* INS is considered a 128-bit write for SVE. */
7894 clear_vec_high(s
, true, rd
);
7901 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7902 * +---+---+-------------------+--------+-------------+------+------+
7903 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7904 * +---+---+-------------------+--------+-------------+------+------+
7906 * U: unsigned when set
7907 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7909 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7910 int rn
, int rd
, int imm5
)
7912 int size
= ctz32(imm5
);
7916 /* Check for UnallocatedEncodings */
7918 if (size
> 2 || (size
== 2 && !is_q
)) {
7919 unallocated_encoding(s
);
7924 || (size
< 3 && is_q
)
7925 || (size
== 3 && !is_q
)) {
7926 unallocated_encoding(s
);
7931 if (!fp_access_check(s
)) {
7935 element
= extract32(imm5
, 1+size
, 4);
7937 tcg_rd
= cpu_reg(s
, rd
);
7938 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7939 if (is_signed
&& !is_q
) {
7940 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7945 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7946 * +---+---+----+-----------------+------+---+------+---+------+------+
7947 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7948 * +---+---+----+-----------------+------+---+------+---+------+------+
7950 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7952 int rd
= extract32(insn
, 0, 5);
7953 int rn
= extract32(insn
, 5, 5);
7954 int imm4
= extract32(insn
, 11, 4);
7955 int op
= extract32(insn
, 29, 1);
7956 int is_q
= extract32(insn
, 30, 1);
7957 int imm5
= extract32(insn
, 16, 5);
7962 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7964 unallocated_encoding(s
);
7969 /* DUP (element - vector) */
7970 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7974 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7979 handle_simd_insg(s
, rd
, rn
, imm5
);
7981 unallocated_encoding(s
);
7986 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7987 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7990 unallocated_encoding(s
);
7996 /* AdvSIMD modified immediate
7997 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7998 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7999 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8000 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8002 * There are a number of operations that can be carried out here:
8003 * MOVI - move (shifted) imm into register
8004 * MVNI - move inverted (shifted) imm into register
8005 * ORR - bitwise OR of (shifted) imm with register
8006 * BIC - bitwise clear of (shifted) imm with register
8007 * With ARMv8.2 we also have:
8008 * FMOV half-precision
8010 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8012 int rd
= extract32(insn
, 0, 5);
8013 int cmode
= extract32(insn
, 12, 4);
8014 int o2
= extract32(insn
, 11, 1);
8015 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8016 bool is_neg
= extract32(insn
, 29, 1);
8017 bool is_q
= extract32(insn
, 30, 1);
8020 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8021 /* Check for FMOV (vector, immediate) - half-precision */
8022 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8023 unallocated_encoding(s
);
8028 if (!fp_access_check(s
)) {
8032 if (cmode
== 15 && o2
&& !is_neg
) {
8033 /* FMOV (vector, immediate) - half-precision */
8034 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8035 /* now duplicate across the lanes */
8036 imm
= dup_const(MO_16
, imm
);
8038 imm
= asimd_imm_const(abcdefgh
, cmode
, is_neg
);
8041 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8042 /* MOVI or MVNI, with MVNI negation handled above. */
8043 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8044 vec_full_reg_size(s
), imm
);
8046 /* ORR or BIC, with BIC negation to AND handled above. */
8048 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8050 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8055 /* AdvSIMD scalar copy
8056 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8057 * +-----+----+-----------------+------+---+------+---+------+------+
8058 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8059 * +-----+----+-----------------+------+---+------+---+------+------+
8061 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8063 int rd
= extract32(insn
, 0, 5);
8064 int rn
= extract32(insn
, 5, 5);
8065 int imm4
= extract32(insn
, 11, 4);
8066 int imm5
= extract32(insn
, 16, 5);
8067 int op
= extract32(insn
, 29, 1);
8069 if (op
!= 0 || imm4
!= 0) {
8070 unallocated_encoding(s
);
8074 /* DUP (element, scalar) */
8075 handle_simd_dupes(s
, rd
, rn
, imm5
);
8078 /* AdvSIMD scalar pairwise
8079 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8080 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8081 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8082 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8084 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8086 int u
= extract32(insn
, 29, 1);
8087 int size
= extract32(insn
, 22, 2);
8088 int opcode
= extract32(insn
, 12, 5);
8089 int rn
= extract32(insn
, 5, 5);
8090 int rd
= extract32(insn
, 0, 5);
8093 /* For some ops (the FP ones), size[1] is part of the encoding.
8094 * For ADDP strictly it is not but size[1] is always 1 for valid
8097 opcode
|= (extract32(size
, 1, 1) << 5);
8100 case 0x3b: /* ADDP */
8101 if (u
|| size
!= 3) {
8102 unallocated_encoding(s
);
8105 if (!fp_access_check(s
)) {
8111 case 0xc: /* FMAXNMP */
8112 case 0xd: /* FADDP */
8113 case 0xf: /* FMAXP */
8114 case 0x2c: /* FMINNMP */
8115 case 0x2f: /* FMINP */
8116 /* FP op, size[0] is 32 or 64 bit*/
8118 if (!dc_isar_feature(aa64_fp16
, s
)) {
8119 unallocated_encoding(s
);
8125 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8128 if (!fp_access_check(s
)) {
8132 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8135 unallocated_encoding(s
);
8139 if (size
== MO_64
) {
8140 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8141 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8142 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8144 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8145 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8148 case 0x3b: /* ADDP */
8149 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8151 case 0xc: /* FMAXNMP */
8152 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8154 case 0xd: /* FADDP */
8155 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8157 case 0xf: /* FMAXP */
8158 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8160 case 0x2c: /* FMINNMP */
8161 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8163 case 0x2f: /* FMINP */
8164 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8167 g_assert_not_reached();
8170 write_fp_dreg(s
, rd
, tcg_res
);
8172 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8173 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8174 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8176 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8177 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8179 if (size
== MO_16
) {
8181 case 0xc: /* FMAXNMP */
8182 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8184 case 0xd: /* FADDP */
8185 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8187 case 0xf: /* FMAXP */
8188 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8190 case 0x2c: /* FMINNMP */
8191 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8193 case 0x2f: /* FMINP */
8194 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8197 g_assert_not_reached();
8201 case 0xc: /* FMAXNMP */
8202 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8204 case 0xd: /* FADDP */
8205 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8207 case 0xf: /* FMAXP */
8208 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8210 case 0x2c: /* FMINNMP */
8211 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8213 case 0x2f: /* FMINP */
8214 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8217 g_assert_not_reached();
8221 write_fp_sreg(s
, rd
, tcg_res
);
8226 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8228 * This code is handles the common shifting code and is used by both
8229 * the vector and scalar code.
8231 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8232 TCGv_i64 tcg_rnd
, bool accumulate
,
8233 bool is_u
, int size
, int shift
)
8235 bool extended_result
= false;
8236 bool round
= tcg_rnd
!= NULL
;
8238 TCGv_i64 tcg_src_hi
;
8240 if (round
&& size
== 3) {
8241 extended_result
= true;
8242 ext_lshift
= 64 - shift
;
8243 tcg_src_hi
= tcg_temp_new_i64();
8244 } else if (shift
== 64) {
8245 if (!accumulate
&& is_u
) {
8246 /* result is zero */
8247 tcg_gen_movi_i64(tcg_res
, 0);
8252 /* Deal with the rounding step */
8254 if (extended_result
) {
8255 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
8257 /* take care of sign extending tcg_res */
8258 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8259 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8260 tcg_src
, tcg_src_hi
,
8263 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8268 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8272 /* Now do the shift right */
8273 if (round
&& extended_result
) {
8274 /* extended case, >64 bit precision required */
8275 if (ext_lshift
== 0) {
8276 /* special case, only high bits matter */
8277 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8279 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8280 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8281 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8286 /* essentially shifting in 64 zeros */
8287 tcg_gen_movi_i64(tcg_src
, 0);
8289 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8293 /* effectively extending the sign-bit */
8294 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8296 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8302 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8304 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8308 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8309 static void handle_scalar_simd_shri(DisasContext
*s
,
8310 bool is_u
, int immh
, int immb
,
8311 int opcode
, int rn
, int rd
)
8314 int immhb
= immh
<< 3 | immb
;
8315 int shift
= 2 * (8 << size
) - immhb
;
8316 bool accumulate
= false;
8318 bool insert
= false;
8323 if (!extract32(immh
, 3, 1)) {
8324 unallocated_encoding(s
);
8328 if (!fp_access_check(s
)) {
8333 case 0x02: /* SSRA / USRA (accumulate) */
8336 case 0x04: /* SRSHR / URSHR (rounding) */
8339 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8340 accumulate
= round
= true;
8342 case 0x08: /* SRI */
8348 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
8353 tcg_rn
= read_fp_dreg(s
, rn
);
8354 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8357 /* shift count same as element size is valid but does nothing;
8358 * special case to avoid potential shift by 64.
8360 int esize
= 8 << size
;
8361 if (shift
!= esize
) {
8362 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8363 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8366 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8367 accumulate
, is_u
, size
, shift
);
8370 write_fp_dreg(s
, rd
, tcg_rd
);
8373 /* SHL/SLI - Scalar shift left */
8374 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8375 int immh
, int immb
, int opcode
,
8378 int size
= 32 - clz32(immh
) - 1;
8379 int immhb
= immh
<< 3 | immb
;
8380 int shift
= immhb
- (8 << size
);
8384 if (!extract32(immh
, 3, 1)) {
8385 unallocated_encoding(s
);
8389 if (!fp_access_check(s
)) {
8393 tcg_rn
= read_fp_dreg(s
, rn
);
8394 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8397 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8399 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8402 write_fp_dreg(s
, rd
, tcg_rd
);
8405 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8406 * (signed/unsigned) narrowing */
8407 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8408 bool is_u_shift
, bool is_u_narrow
,
8409 int immh
, int immb
, int opcode
,
8412 int immhb
= immh
<< 3 | immb
;
8413 int size
= 32 - clz32(immh
) - 1;
8414 int esize
= 8 << size
;
8415 int shift
= (2 * esize
) - immhb
;
8416 int elements
= is_scalar
? 1 : (64 / esize
);
8417 bool round
= extract32(opcode
, 0, 1);
8418 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8419 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8420 TCGv_i32 tcg_rd_narrowed
;
8423 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8424 { gen_helper_neon_narrow_sat_s8
,
8425 gen_helper_neon_unarrow_sat8
},
8426 { gen_helper_neon_narrow_sat_s16
,
8427 gen_helper_neon_unarrow_sat16
},
8428 { gen_helper_neon_narrow_sat_s32
,
8429 gen_helper_neon_unarrow_sat32
},
8432 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8433 gen_helper_neon_narrow_sat_u8
,
8434 gen_helper_neon_narrow_sat_u16
,
8435 gen_helper_neon_narrow_sat_u32
,
8438 NeonGenNarrowEnvFn
*narrowfn
;
8444 if (extract32(immh
, 3, 1)) {
8445 unallocated_encoding(s
);
8449 if (!fp_access_check(s
)) {
8454 narrowfn
= unsigned_narrow_fns
[size
];
8456 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8459 tcg_rn
= tcg_temp_new_i64();
8460 tcg_rd
= tcg_temp_new_i64();
8461 tcg_rd_narrowed
= tcg_temp_new_i32();
8462 tcg_final
= tcg_temp_new_i64();
8465 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
8470 for (i
= 0; i
< elements
; i
++) {
8471 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8472 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8473 false, is_u_shift
, size
+1, shift
);
8474 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8475 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8477 tcg_gen_mov_i64(tcg_final
, tcg_rd
);
8479 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8484 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8486 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8488 clear_vec_high(s
, is_q
, rd
);
8491 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8492 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8493 bool src_unsigned
, bool dst_unsigned
,
8494 int immh
, int immb
, int rn
, int rd
)
8496 int immhb
= immh
<< 3 | immb
;
8497 int size
= 32 - clz32(immh
) - 1;
8498 int shift
= immhb
- (8 << size
);
8502 assert(!(scalar
&& is_q
));
8505 if (!is_q
&& extract32(immh
, 3, 1)) {
8506 unallocated_encoding(s
);
8510 /* Since we use the variable-shift helpers we must
8511 * replicate the shift count into each element of
8512 * the tcg_shift value.
8516 shift
|= shift
<< 8;
8519 shift
|= shift
<< 16;
8525 g_assert_not_reached();
8529 if (!fp_access_check(s
)) {
8534 TCGv_i64 tcg_shift
= tcg_constant_i64(shift
);
8535 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8536 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8537 { NULL
, gen_helper_neon_qshl_u64
},
8539 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8540 int maxpass
= is_q
? 2 : 1;
8542 for (pass
= 0; pass
< maxpass
; pass
++) {
8543 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8545 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8546 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8547 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8549 clear_vec_high(s
, is_q
, rd
);
8551 TCGv_i32 tcg_shift
= tcg_constant_i32(shift
);
8552 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8554 { gen_helper_neon_qshl_s8
,
8555 gen_helper_neon_qshl_s16
,
8556 gen_helper_neon_qshl_s32
},
8557 { gen_helper_neon_qshlu_s8
,
8558 gen_helper_neon_qshlu_s16
,
8559 gen_helper_neon_qshlu_s32
}
8561 { NULL
, NULL
, NULL
},
8562 { gen_helper_neon_qshl_u8
,
8563 gen_helper_neon_qshl_u16
,
8564 gen_helper_neon_qshl_u32
}
8567 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8568 MemOp memop
= scalar
? size
: MO_32
;
8569 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8571 for (pass
= 0; pass
< maxpass
; pass
++) {
8572 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8574 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8575 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8579 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8582 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8587 g_assert_not_reached();
8589 write_fp_sreg(s
, rd
, tcg_op
);
8591 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8596 clear_vec_high(s
, is_q
, rd
);
8601 /* Common vector code for handling integer to FP conversion */
8602 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8603 int elements
, int is_signed
,
8604 int fracbits
, int size
)
8606 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8607 TCGv_i32 tcg_shift
= NULL
;
8609 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8612 if (fracbits
|| size
== MO_64
) {
8613 tcg_shift
= tcg_constant_i32(fracbits
);
8616 if (size
== MO_64
) {
8617 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8618 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8620 for (pass
= 0; pass
< elements
; pass
++) {
8621 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8624 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8625 tcg_shift
, tcg_fpst
);
8627 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8628 tcg_shift
, tcg_fpst
);
8630 if (elements
== 1) {
8631 write_fp_dreg(s
, rd
, tcg_double
);
8633 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8637 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8638 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8640 for (pass
= 0; pass
< elements
; pass
++) {
8641 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8647 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8648 tcg_shift
, tcg_fpst
);
8650 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8651 tcg_shift
, tcg_fpst
);
8655 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8657 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8664 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8665 tcg_shift
, tcg_fpst
);
8667 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8668 tcg_shift
, tcg_fpst
);
8672 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8674 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8679 g_assert_not_reached();
8682 if (elements
== 1) {
8683 write_fp_sreg(s
, rd
, tcg_float
);
8685 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8690 clear_vec_high(s
, elements
<< size
== 16, rd
);
8693 /* UCVTF/SCVTF - Integer to FP conversion */
8694 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8695 bool is_q
, bool is_u
,
8696 int immh
, int immb
, int opcode
,
8699 int size
, elements
, fracbits
;
8700 int immhb
= immh
<< 3 | immb
;
8704 if (!is_scalar
&& !is_q
) {
8705 unallocated_encoding(s
);
8708 } else if (immh
& 4) {
8710 } else if (immh
& 2) {
8712 if (!dc_isar_feature(aa64_fp16
, s
)) {
8713 unallocated_encoding(s
);
8717 /* immh == 0 would be a failure of the decode logic */
8718 g_assert(immh
== 1);
8719 unallocated_encoding(s
);
8726 elements
= (8 << is_q
) >> size
;
8728 fracbits
= (16 << size
) - immhb
;
8730 if (!fp_access_check(s
)) {
8734 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8737 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8738 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8739 bool is_q
, bool is_u
,
8740 int immh
, int immb
, int rn
, int rd
)
8742 int immhb
= immh
<< 3 | immb
;
8743 int pass
, size
, fracbits
;
8744 TCGv_ptr tcg_fpstatus
;
8745 TCGv_i32 tcg_rmode
, tcg_shift
;
8749 if (!is_scalar
&& !is_q
) {
8750 unallocated_encoding(s
);
8753 } else if (immh
& 0x4) {
8755 } else if (immh
& 0x2) {
8757 if (!dc_isar_feature(aa64_fp16
, s
)) {
8758 unallocated_encoding(s
);
8762 /* Should have split out AdvSIMD modified immediate earlier. */
8764 unallocated_encoding(s
);
8768 if (!fp_access_check(s
)) {
8772 assert(!(is_scalar
&& is_q
));
8774 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8775 tcg_rmode
= gen_set_rmode(FPROUNDING_ZERO
, tcg_fpstatus
);
8776 fracbits
= (16 << size
) - immhb
;
8777 tcg_shift
= tcg_constant_i32(fracbits
);
8779 if (size
== MO_64
) {
8780 int maxpass
= is_scalar
? 1 : 2;
8782 for (pass
= 0; pass
< maxpass
; pass
++) {
8783 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8785 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8787 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8789 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8791 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8793 clear_vec_high(s
, is_q
, rd
);
8795 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8796 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8801 fn
= gen_helper_vfp_touhh
;
8803 fn
= gen_helper_vfp_toshh
;
8808 fn
= gen_helper_vfp_touls
;
8810 fn
= gen_helper_vfp_tosls
;
8814 g_assert_not_reached();
8817 for (pass
= 0; pass
< maxpass
; pass
++) {
8818 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8820 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8821 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8823 write_fp_sreg(s
, rd
, tcg_op
);
8825 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8829 clear_vec_high(s
, is_q
, rd
);
8833 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
8836 /* AdvSIMD scalar shift by immediate
8837 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8838 * +-----+---+-------------+------+------+--------+---+------+------+
8839 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8840 * +-----+---+-------------+------+------+--------+---+------+------+
8842 * This is the scalar version so it works on a fixed sized registers
8844 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8846 int rd
= extract32(insn
, 0, 5);
8847 int rn
= extract32(insn
, 5, 5);
8848 int opcode
= extract32(insn
, 11, 5);
8849 int immb
= extract32(insn
, 16, 3);
8850 int immh
= extract32(insn
, 19, 4);
8851 bool is_u
= extract32(insn
, 29, 1);
8854 unallocated_encoding(s
);
8859 case 0x08: /* SRI */
8861 unallocated_encoding(s
);
8865 case 0x00: /* SSHR / USHR */
8866 case 0x02: /* SSRA / USRA */
8867 case 0x04: /* SRSHR / URSHR */
8868 case 0x06: /* SRSRA / URSRA */
8869 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8871 case 0x0a: /* SHL / SLI */
8872 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8874 case 0x1c: /* SCVTF, UCVTF */
8875 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8878 case 0x10: /* SQSHRUN, SQSHRUN2 */
8879 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8881 unallocated_encoding(s
);
8884 handle_vec_simd_sqshrn(s
, true, false, false, true,
8885 immh
, immb
, opcode
, rn
, rd
);
8887 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8888 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8889 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8890 immh
, immb
, opcode
, rn
, rd
);
8892 case 0xc: /* SQSHLU */
8894 unallocated_encoding(s
);
8897 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8899 case 0xe: /* SQSHL, UQSHL */
8900 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8902 case 0x1f: /* FCVTZS, FCVTZU */
8903 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8906 unallocated_encoding(s
);
8911 /* AdvSIMD scalar three different
8912 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8913 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8914 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8915 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8917 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8919 bool is_u
= extract32(insn
, 29, 1);
8920 int size
= extract32(insn
, 22, 2);
8921 int opcode
= extract32(insn
, 12, 4);
8922 int rm
= extract32(insn
, 16, 5);
8923 int rn
= extract32(insn
, 5, 5);
8924 int rd
= extract32(insn
, 0, 5);
8927 unallocated_encoding(s
);
8932 case 0x9: /* SQDMLAL, SQDMLAL2 */
8933 case 0xb: /* SQDMLSL, SQDMLSL2 */
8934 case 0xd: /* SQDMULL, SQDMULL2 */
8935 if (size
== 0 || size
== 3) {
8936 unallocated_encoding(s
);
8941 unallocated_encoding(s
);
8945 if (!fp_access_check(s
)) {
8950 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8951 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8952 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8954 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8955 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8957 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8958 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8961 case 0xd: /* SQDMULL, SQDMULL2 */
8963 case 0xb: /* SQDMLSL, SQDMLSL2 */
8964 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8966 case 0x9: /* SQDMLAL, SQDMLAL2 */
8967 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8968 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8972 g_assert_not_reached();
8975 write_fp_dreg(s
, rd
, tcg_res
);
8977 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8978 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8979 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8981 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8982 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8985 case 0xd: /* SQDMULL, SQDMULL2 */
8987 case 0xb: /* SQDMLSL, SQDMLSL2 */
8988 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8990 case 0x9: /* SQDMLAL, SQDMLAL2 */
8992 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8993 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8994 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8999 g_assert_not_reached();
9002 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9003 write_fp_dreg(s
, rd
, tcg_res
);
9007 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9008 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9010 /* Handle 64x64->64 opcodes which are shared between the scalar
9011 * and vector 3-same groups. We cover every opcode where size == 3
9012 * is valid in either the three-reg-same (integer, not pairwise)
9013 * or scalar-three-reg-same groups.
9018 case 0x1: /* SQADD */
9020 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9022 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9025 case 0x5: /* SQSUB */
9027 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9029 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9032 case 0x6: /* CMGT, CMHI */
9033 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9034 * We implement this using setcond (test) and then negating.
9036 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9038 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9039 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9041 case 0x7: /* CMGE, CMHS */
9042 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9044 case 0x11: /* CMTST, CMEQ */
9049 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9051 case 0x8: /* SSHL, USHL */
9053 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9055 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9058 case 0x9: /* SQSHL, UQSHL */
9060 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9062 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9065 case 0xa: /* SRSHL, URSHL */
9067 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9069 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9072 case 0xb: /* SQRSHL, UQRSHL */
9074 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9076 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9079 case 0x10: /* ADD, SUB */
9081 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9083 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9087 g_assert_not_reached();
9091 /* Handle the 3-same-operands float operations; shared by the scalar
9092 * and vector encodings. The caller must filter out any encodings
9093 * not allocated for the encoding it is dealing with.
9095 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9096 int fpopcode
, int rd
, int rn
, int rm
)
9099 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9101 for (pass
= 0; pass
< elements
; pass
++) {
9104 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9105 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9106 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9108 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9109 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9112 case 0x39: /* FMLS */
9113 /* As usual for ARM, separate negation for fused multiply-add */
9114 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9116 case 0x19: /* FMLA */
9117 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9118 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9121 case 0x18: /* FMAXNM */
9122 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9124 case 0x1a: /* FADD */
9125 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9127 case 0x1b: /* FMULX */
9128 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9130 case 0x1c: /* FCMEQ */
9131 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9133 case 0x1e: /* FMAX */
9134 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9136 case 0x1f: /* FRECPS */
9137 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9139 case 0x38: /* FMINNM */
9140 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9142 case 0x3a: /* FSUB */
9143 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9145 case 0x3e: /* FMIN */
9146 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9148 case 0x3f: /* FRSQRTS */
9149 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9151 case 0x5b: /* FMUL */
9152 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9154 case 0x5c: /* FCMGE */
9155 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9157 case 0x5d: /* FACGE */
9158 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9160 case 0x5f: /* FDIV */
9161 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9163 case 0x7a: /* FABD */
9164 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9165 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9167 case 0x7c: /* FCMGT */
9168 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9170 case 0x7d: /* FACGT */
9171 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9174 g_assert_not_reached();
9177 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9180 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9181 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9182 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9184 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9185 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9188 case 0x39: /* FMLS */
9189 /* As usual for ARM, separate negation for fused multiply-add */
9190 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9192 case 0x19: /* FMLA */
9193 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9194 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9197 case 0x1a: /* FADD */
9198 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9200 case 0x1b: /* FMULX */
9201 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9203 case 0x1c: /* FCMEQ */
9204 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9206 case 0x1e: /* FMAX */
9207 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9209 case 0x1f: /* FRECPS */
9210 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9212 case 0x18: /* FMAXNM */
9213 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9215 case 0x38: /* FMINNM */
9216 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9218 case 0x3a: /* FSUB */
9219 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9221 case 0x3e: /* FMIN */
9222 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9224 case 0x3f: /* FRSQRTS */
9225 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9227 case 0x5b: /* FMUL */
9228 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9230 case 0x5c: /* FCMGE */
9231 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9233 case 0x5d: /* FACGE */
9234 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9236 case 0x5f: /* FDIV */
9237 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9239 case 0x7a: /* FABD */
9240 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9241 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9243 case 0x7c: /* FCMGT */
9244 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9246 case 0x7d: /* FACGT */
9247 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9250 g_assert_not_reached();
9253 if (elements
== 1) {
9254 /* scalar single so clear high part */
9255 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9257 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9258 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9260 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9265 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9268 /* AdvSIMD scalar three same
9269 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9270 * +-----+---+-----------+------+---+------+--------+---+------+------+
9271 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9272 * +-----+---+-----------+------+---+------+--------+---+------+------+
9274 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9276 int rd
= extract32(insn
, 0, 5);
9277 int rn
= extract32(insn
, 5, 5);
9278 int opcode
= extract32(insn
, 11, 5);
9279 int rm
= extract32(insn
, 16, 5);
9280 int size
= extract32(insn
, 22, 2);
9281 bool u
= extract32(insn
, 29, 1);
9284 if (opcode
>= 0x18) {
9285 /* Floating point: U, size[1] and opcode indicate operation */
9286 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9288 case 0x1b: /* FMULX */
9289 case 0x1f: /* FRECPS */
9290 case 0x3f: /* FRSQRTS */
9291 case 0x5d: /* FACGE */
9292 case 0x7d: /* FACGT */
9293 case 0x1c: /* FCMEQ */
9294 case 0x5c: /* FCMGE */
9295 case 0x7c: /* FCMGT */
9296 case 0x7a: /* FABD */
9299 unallocated_encoding(s
);
9303 if (!fp_access_check(s
)) {
9307 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9312 case 0x1: /* SQADD, UQADD */
9313 case 0x5: /* SQSUB, UQSUB */
9314 case 0x9: /* SQSHL, UQSHL */
9315 case 0xb: /* SQRSHL, UQRSHL */
9317 case 0x8: /* SSHL, USHL */
9318 case 0xa: /* SRSHL, URSHL */
9319 case 0x6: /* CMGT, CMHI */
9320 case 0x7: /* CMGE, CMHS */
9321 case 0x11: /* CMTST, CMEQ */
9322 case 0x10: /* ADD, SUB (vector) */
9324 unallocated_encoding(s
);
9328 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9329 if (size
!= 1 && size
!= 2) {
9330 unallocated_encoding(s
);
9335 unallocated_encoding(s
);
9339 if (!fp_access_check(s
)) {
9343 tcg_rd
= tcg_temp_new_i64();
9346 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9347 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9349 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9351 /* Do a single operation on the lowest element in the vector.
9352 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9353 * no side effects for all these operations.
9354 * OPTME: special-purpose helpers would avoid doing some
9355 * unnecessary work in the helper for the 8 and 16 bit cases.
9357 NeonGenTwoOpEnvFn
*genenvfn
;
9358 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9359 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9360 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9362 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9363 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9366 case 0x1: /* SQADD, UQADD */
9368 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9369 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9370 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9371 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9373 genenvfn
= fns
[size
][u
];
9376 case 0x5: /* SQSUB, UQSUB */
9378 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9379 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9380 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9381 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9383 genenvfn
= fns
[size
][u
];
9386 case 0x9: /* SQSHL, UQSHL */
9388 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9389 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9390 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9391 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9393 genenvfn
= fns
[size
][u
];
9396 case 0xb: /* SQRSHL, UQRSHL */
9398 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9399 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9400 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9401 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9403 genenvfn
= fns
[size
][u
];
9406 case 0x16: /* SQDMULH, SQRDMULH */
9408 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9409 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9410 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9412 assert(size
== 1 || size
== 2);
9413 genenvfn
= fns
[size
- 1][u
];
9417 g_assert_not_reached();
9420 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9421 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9424 write_fp_dreg(s
, rd
, tcg_rd
);
9427 /* AdvSIMD scalar three same FP16
9428 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9429 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9430 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9431 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9432 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9433 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9435 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9438 int rd
= extract32(insn
, 0, 5);
9439 int rn
= extract32(insn
, 5, 5);
9440 int opcode
= extract32(insn
, 11, 3);
9441 int rm
= extract32(insn
, 16, 5);
9442 bool u
= extract32(insn
, 29, 1);
9443 bool a
= extract32(insn
, 23, 1);
9444 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9451 case 0x03: /* FMULX */
9452 case 0x04: /* FCMEQ (reg) */
9453 case 0x07: /* FRECPS */
9454 case 0x0f: /* FRSQRTS */
9455 case 0x14: /* FCMGE (reg) */
9456 case 0x15: /* FACGE */
9457 case 0x1a: /* FABD */
9458 case 0x1c: /* FCMGT (reg) */
9459 case 0x1d: /* FACGT */
9462 unallocated_encoding(s
);
9466 if (!dc_isar_feature(aa64_fp16
, s
)) {
9467 unallocated_encoding(s
);
9470 if (!fp_access_check(s
)) {
9474 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9476 tcg_op1
= read_fp_hreg(s
, rn
);
9477 tcg_op2
= read_fp_hreg(s
, rm
);
9478 tcg_res
= tcg_temp_new_i32();
9481 case 0x03: /* FMULX */
9482 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9484 case 0x04: /* FCMEQ (reg) */
9485 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9487 case 0x07: /* FRECPS */
9488 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9490 case 0x0f: /* FRSQRTS */
9491 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9493 case 0x14: /* FCMGE (reg) */
9494 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9496 case 0x15: /* FACGE */
9497 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9499 case 0x1a: /* FABD */
9500 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9501 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9503 case 0x1c: /* FCMGT (reg) */
9504 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9506 case 0x1d: /* FACGT */
9507 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9510 g_assert_not_reached();
9513 write_fp_sreg(s
, rd
, tcg_res
);
9516 /* AdvSIMD scalar three same extra
9517 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9518 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9519 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9520 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9522 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9525 int rd
= extract32(insn
, 0, 5);
9526 int rn
= extract32(insn
, 5, 5);
9527 int opcode
= extract32(insn
, 11, 4);
9528 int rm
= extract32(insn
, 16, 5);
9529 int size
= extract32(insn
, 22, 2);
9530 bool u
= extract32(insn
, 29, 1);
9531 TCGv_i32 ele1
, ele2
, ele3
;
9535 switch (u
* 16 + opcode
) {
9536 case 0x10: /* SQRDMLAH (vector) */
9537 case 0x11: /* SQRDMLSH (vector) */
9538 if (size
!= 1 && size
!= 2) {
9539 unallocated_encoding(s
);
9542 feature
= dc_isar_feature(aa64_rdm
, s
);
9545 unallocated_encoding(s
);
9549 unallocated_encoding(s
);
9552 if (!fp_access_check(s
)) {
9556 /* Do a single operation on the lowest element in the vector.
9557 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9558 * with no side effects for all these operations.
9559 * OPTME: special-purpose helpers would avoid doing some
9560 * unnecessary work in the helper for the 16 bit cases.
9562 ele1
= tcg_temp_new_i32();
9563 ele2
= tcg_temp_new_i32();
9564 ele3
= tcg_temp_new_i32();
9566 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9567 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9568 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9571 case 0x0: /* SQRDMLAH */
9573 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9575 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9578 case 0x1: /* SQRDMLSH */
9580 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9582 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9586 g_assert_not_reached();
9589 res
= tcg_temp_new_i64();
9590 tcg_gen_extu_i32_i64(res
, ele3
);
9591 write_fp_dreg(s
, rd
, res
);
9594 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9595 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9596 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9598 /* Handle 64->64 opcodes which are shared between the scalar and
9599 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9600 * is valid in either group and also the double-precision fp ops.
9601 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9607 case 0x4: /* CLS, CLZ */
9609 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9611 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9615 /* This opcode is shared with CNT and RBIT but we have earlier
9616 * enforced that size == 3 if and only if this is the NOT insn.
9618 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9620 case 0x7: /* SQABS, SQNEG */
9622 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9624 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9627 case 0xa: /* CMLT */
9628 /* 64 bit integer comparison against zero, result is
9629 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9634 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9635 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9637 case 0x8: /* CMGT, CMGE */
9638 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9640 case 0x9: /* CMEQ, CMLE */
9641 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9643 case 0xb: /* ABS, NEG */
9645 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9647 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9650 case 0x2f: /* FABS */
9651 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9653 case 0x6f: /* FNEG */
9654 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9656 case 0x7f: /* FSQRT */
9657 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9659 case 0x1a: /* FCVTNS */
9660 case 0x1b: /* FCVTMS */
9661 case 0x1c: /* FCVTAS */
9662 case 0x3a: /* FCVTPS */
9663 case 0x3b: /* FCVTZS */
9664 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_constant_i32(0), tcg_fpstatus
);
9666 case 0x5a: /* FCVTNU */
9667 case 0x5b: /* FCVTMU */
9668 case 0x5c: /* FCVTAU */
9669 case 0x7a: /* FCVTPU */
9670 case 0x7b: /* FCVTZU */
9671 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_constant_i32(0), tcg_fpstatus
);
9673 case 0x18: /* FRINTN */
9674 case 0x19: /* FRINTM */
9675 case 0x38: /* FRINTP */
9676 case 0x39: /* FRINTZ */
9677 case 0x58: /* FRINTA */
9678 case 0x79: /* FRINTI */
9679 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9681 case 0x59: /* FRINTX */
9682 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9684 case 0x1e: /* FRINT32Z */
9685 case 0x5e: /* FRINT32X */
9686 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9688 case 0x1f: /* FRINT64Z */
9689 case 0x5f: /* FRINT64X */
9690 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9693 g_assert_not_reached();
9697 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9698 bool is_scalar
, bool is_u
, bool is_q
,
9699 int size
, int rn
, int rd
)
9701 bool is_double
= (size
== MO_64
);
9704 if (!fp_access_check(s
)) {
9708 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9711 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9712 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
9713 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9714 NeonGenTwoDoubleOpFn
*genfn
;
9719 case 0x2e: /* FCMLT (zero) */
9722 case 0x2c: /* FCMGT (zero) */
9723 genfn
= gen_helper_neon_cgt_f64
;
9725 case 0x2d: /* FCMEQ (zero) */
9726 genfn
= gen_helper_neon_ceq_f64
;
9728 case 0x6d: /* FCMLE (zero) */
9731 case 0x6c: /* FCMGE (zero) */
9732 genfn
= gen_helper_neon_cge_f64
;
9735 g_assert_not_reached();
9738 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9739 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9741 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9743 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9745 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9748 clear_vec_high(s
, !is_scalar
, rd
);
9750 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9751 TCGv_i32 tcg_zero
= tcg_constant_i32(0);
9752 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9753 NeonGenTwoSingleOpFn
*genfn
;
9755 int pass
, maxpasses
;
9757 if (size
== MO_16
) {
9759 case 0x2e: /* FCMLT (zero) */
9762 case 0x2c: /* FCMGT (zero) */
9763 genfn
= gen_helper_advsimd_cgt_f16
;
9765 case 0x2d: /* FCMEQ (zero) */
9766 genfn
= gen_helper_advsimd_ceq_f16
;
9768 case 0x6d: /* FCMLE (zero) */
9771 case 0x6c: /* FCMGE (zero) */
9772 genfn
= gen_helper_advsimd_cge_f16
;
9775 g_assert_not_reached();
9779 case 0x2e: /* FCMLT (zero) */
9782 case 0x2c: /* FCMGT (zero) */
9783 genfn
= gen_helper_neon_cgt_f32
;
9785 case 0x2d: /* FCMEQ (zero) */
9786 genfn
= gen_helper_neon_ceq_f32
;
9788 case 0x6d: /* FCMLE (zero) */
9791 case 0x6c: /* FCMGE (zero) */
9792 genfn
= gen_helper_neon_cge_f32
;
9795 g_assert_not_reached();
9802 int vector_size
= 8 << is_q
;
9803 maxpasses
= vector_size
>> size
;
9806 for (pass
= 0; pass
< maxpasses
; pass
++) {
9807 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9809 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9811 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9814 write_fp_sreg(s
, rd
, tcg_res
);
9816 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9821 clear_vec_high(s
, is_q
, rd
);
9826 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9827 bool is_scalar
, bool is_u
, bool is_q
,
9828 int size
, int rn
, int rd
)
9830 bool is_double
= (size
== 3);
9831 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9834 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9835 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9838 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9839 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9841 case 0x3d: /* FRECPE */
9842 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9844 case 0x3f: /* FRECPX */
9845 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9847 case 0x7d: /* FRSQRTE */
9848 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9851 g_assert_not_reached();
9853 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9855 clear_vec_high(s
, !is_scalar
, rd
);
9857 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9858 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9859 int pass
, maxpasses
;
9864 maxpasses
= is_q
? 4 : 2;
9867 for (pass
= 0; pass
< maxpasses
; pass
++) {
9868 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9871 case 0x3c: /* URECPE */
9872 gen_helper_recpe_u32(tcg_res
, tcg_op
);
9874 case 0x3d: /* FRECPE */
9875 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9877 case 0x3f: /* FRECPX */
9878 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9880 case 0x7d: /* FRSQRTE */
9881 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9884 g_assert_not_reached();
9888 write_fp_sreg(s
, rd
, tcg_res
);
9890 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9894 clear_vec_high(s
, is_q
, rd
);
9899 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9900 int opcode
, bool u
, bool is_q
,
9901 int size
, int rn
, int rd
)
9903 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9904 * in the source becomes a size element in the destination).
9907 TCGv_i32 tcg_res
[2];
9908 int destelt
= is_q
? 2 : 0;
9909 int passes
= scalar
? 1 : 2;
9912 tcg_res
[1] = tcg_constant_i32(0);
9915 for (pass
= 0; pass
< passes
; pass
++) {
9916 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9917 NeonGenNarrowFn
*genfn
= NULL
;
9918 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9921 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9923 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9925 tcg_res
[pass
] = tcg_temp_new_i32();
9928 case 0x12: /* XTN, SQXTUN */
9930 static NeonGenNarrowFn
* const xtnfns
[3] = {
9931 gen_helper_neon_narrow_u8
,
9932 gen_helper_neon_narrow_u16
,
9933 tcg_gen_extrl_i64_i32
,
9935 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9936 gen_helper_neon_unarrow_sat8
,
9937 gen_helper_neon_unarrow_sat16
,
9938 gen_helper_neon_unarrow_sat32
,
9941 genenvfn
= sqxtunfns
[size
];
9943 genfn
= xtnfns
[size
];
9947 case 0x14: /* SQXTN, UQXTN */
9949 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9950 { gen_helper_neon_narrow_sat_s8
,
9951 gen_helper_neon_narrow_sat_u8
},
9952 { gen_helper_neon_narrow_sat_s16
,
9953 gen_helper_neon_narrow_sat_u16
},
9954 { gen_helper_neon_narrow_sat_s32
,
9955 gen_helper_neon_narrow_sat_u32
},
9957 genenvfn
= fns
[size
][u
];
9960 case 0x16: /* FCVTN, FCVTN2 */
9961 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9963 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9965 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9966 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9967 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9968 TCGv_i32 ahp
= get_ahp_flag();
9970 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9971 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9972 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9973 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9976 case 0x36: /* BFCVTN, BFCVTN2 */
9978 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9979 gen_helper_bfcvt_pair(tcg_res
[pass
], tcg_op
, fpst
);
9982 case 0x56: /* FCVTXN, FCVTXN2 */
9983 /* 64 bit to 32 bit float conversion
9984 * with von Neumann rounding (round to odd)
9987 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9990 g_assert_not_reached();
9994 genfn(tcg_res
[pass
], tcg_op
);
9995 } else if (genenvfn
) {
9996 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10000 for (pass
= 0; pass
< 2; pass
++) {
10001 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10003 clear_vec_high(s
, is_q
, rd
);
10006 /* Remaining saturating accumulating ops */
10007 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10008 bool is_q
, int size
, int rn
, int rd
)
10010 bool is_double
= (size
== 3);
10013 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10014 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10017 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10018 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10019 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10021 if (is_u
) { /* USQADD */
10022 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10023 } else { /* SUQADD */
10024 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10026 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10028 clear_vec_high(s
, !is_scalar
, rd
);
10030 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10031 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10032 int pass
, maxpasses
;
10037 maxpasses
= is_q
? 4 : 2;
10040 for (pass
= 0; pass
< maxpasses
; pass
++) {
10042 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10043 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10045 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10046 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10049 if (is_u
) { /* USQADD */
10052 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10055 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10058 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10061 g_assert_not_reached();
10063 } else { /* SUQADD */
10066 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10069 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10072 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10075 g_assert_not_reached();
10080 write_vec_element(s
, tcg_constant_i64(0), rd
, 0, MO_64
);
10082 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10084 clear_vec_high(s
, is_q
, rd
);
10088 /* AdvSIMD scalar two reg misc
10089 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10090 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10091 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10092 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10094 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10096 int rd
= extract32(insn
, 0, 5);
10097 int rn
= extract32(insn
, 5, 5);
10098 int opcode
= extract32(insn
, 12, 5);
10099 int size
= extract32(insn
, 22, 2);
10100 bool u
= extract32(insn
, 29, 1);
10101 bool is_fcvt
= false;
10103 TCGv_i32 tcg_rmode
;
10104 TCGv_ptr tcg_fpstatus
;
10107 case 0x3: /* USQADD / SUQADD*/
10108 if (!fp_access_check(s
)) {
10111 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10113 case 0x7: /* SQABS / SQNEG */
10115 case 0xa: /* CMLT */
10117 unallocated_encoding(s
);
10121 case 0x8: /* CMGT, CMGE */
10122 case 0x9: /* CMEQ, CMLE */
10123 case 0xb: /* ABS, NEG */
10125 unallocated_encoding(s
);
10129 case 0x12: /* SQXTUN */
10131 unallocated_encoding(s
);
10135 case 0x14: /* SQXTN, UQXTN */
10137 unallocated_encoding(s
);
10140 if (!fp_access_check(s
)) {
10143 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10146 case 0x16 ... 0x1d:
10148 /* Floating point: U, size[1] and opcode indicate operation;
10149 * size[0] indicates single or double precision.
10151 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10152 size
= extract32(size
, 0, 1) ? 3 : 2;
10154 case 0x2c: /* FCMGT (zero) */
10155 case 0x2d: /* FCMEQ (zero) */
10156 case 0x2e: /* FCMLT (zero) */
10157 case 0x6c: /* FCMGE (zero) */
10158 case 0x6d: /* FCMLE (zero) */
10159 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10161 case 0x1d: /* SCVTF */
10162 case 0x5d: /* UCVTF */
10164 bool is_signed
= (opcode
== 0x1d);
10165 if (!fp_access_check(s
)) {
10168 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10171 case 0x3d: /* FRECPE */
10172 case 0x3f: /* FRECPX */
10173 case 0x7d: /* FRSQRTE */
10174 if (!fp_access_check(s
)) {
10177 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10179 case 0x1a: /* FCVTNS */
10180 case 0x1b: /* FCVTMS */
10181 case 0x3a: /* FCVTPS */
10182 case 0x3b: /* FCVTZS */
10183 case 0x5a: /* FCVTNU */
10184 case 0x5b: /* FCVTMU */
10185 case 0x7a: /* FCVTPU */
10186 case 0x7b: /* FCVTZU */
10188 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10190 case 0x1c: /* FCVTAS */
10191 case 0x5c: /* FCVTAU */
10192 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10194 rmode
= FPROUNDING_TIEAWAY
;
10196 case 0x56: /* FCVTXN, FCVTXN2 */
10198 unallocated_encoding(s
);
10201 if (!fp_access_check(s
)) {
10204 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10207 unallocated_encoding(s
);
10212 unallocated_encoding(s
);
10216 if (!fp_access_check(s
)) {
10221 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10222 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
10224 tcg_fpstatus
= NULL
;
10229 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10230 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10232 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10233 write_fp_dreg(s
, rd
, tcg_rd
);
10235 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10236 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10238 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10241 case 0x7: /* SQABS, SQNEG */
10243 NeonGenOneOpEnvFn
*genfn
;
10244 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10245 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10246 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10247 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10249 genfn
= fns
[size
][u
];
10250 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10253 case 0x1a: /* FCVTNS */
10254 case 0x1b: /* FCVTMS */
10255 case 0x1c: /* FCVTAS */
10256 case 0x3a: /* FCVTPS */
10257 case 0x3b: /* FCVTZS */
10258 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_constant_i32(0),
10261 case 0x5a: /* FCVTNU */
10262 case 0x5b: /* FCVTMU */
10263 case 0x5c: /* FCVTAU */
10264 case 0x7a: /* FCVTPU */
10265 case 0x7b: /* FCVTZU */
10266 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_constant_i32(0),
10270 g_assert_not_reached();
10273 write_fp_sreg(s
, rd
, tcg_rd
);
10277 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
10281 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10282 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10283 int immh
, int immb
, int opcode
, int rn
, int rd
)
10285 int size
= 32 - clz32(immh
) - 1;
10286 int immhb
= immh
<< 3 | immb
;
10287 int shift
= 2 * (8 << size
) - immhb
;
10288 GVecGen2iFn
*gvec_fn
;
10290 if (extract32(immh
, 3, 1) && !is_q
) {
10291 unallocated_encoding(s
);
10294 tcg_debug_assert(size
<= 3);
10296 if (!fp_access_check(s
)) {
10301 case 0x02: /* SSRA / USRA (accumulate) */
10302 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10305 case 0x08: /* SRI */
10306 gvec_fn
= gen_gvec_sri
;
10309 case 0x00: /* SSHR / USHR */
10311 if (shift
== 8 << size
) {
10312 /* Shift count the same size as element size produces zero. */
10313 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10314 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10317 gvec_fn
= tcg_gen_gvec_shri
;
10319 /* Shift count the same size as element size produces all sign. */
10320 if (shift
== 8 << size
) {
10323 gvec_fn
= tcg_gen_gvec_sari
;
10327 case 0x04: /* SRSHR / URSHR (rounding) */
10328 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10331 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10332 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10336 g_assert_not_reached();
10339 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10342 /* SHL/SLI - Vector shift left */
10343 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10344 int immh
, int immb
, int opcode
, int rn
, int rd
)
10346 int size
= 32 - clz32(immh
) - 1;
10347 int immhb
= immh
<< 3 | immb
;
10348 int shift
= immhb
- (8 << size
);
10350 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10351 assert(size
>= 0 && size
<= 3);
10353 if (extract32(immh
, 3, 1) && !is_q
) {
10354 unallocated_encoding(s
);
10358 if (!fp_access_check(s
)) {
10363 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10365 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10369 /* USHLL/SHLL - Vector shift left with widening */
10370 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10371 int immh
, int immb
, int opcode
, int rn
, int rd
)
10373 int size
= 32 - clz32(immh
) - 1;
10374 int immhb
= immh
<< 3 | immb
;
10375 int shift
= immhb
- (8 << size
);
10377 int esize
= 8 << size
;
10378 int elements
= dsize
/esize
;
10379 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10380 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10384 unallocated_encoding(s
);
10388 if (!fp_access_check(s
)) {
10392 /* For the LL variants the store is larger than the load,
10393 * so if rd == rn we would overwrite parts of our input.
10394 * So load everything right now and use shifts in the main loop.
10396 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10398 for (i
= 0; i
< elements
; i
++) {
10399 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10400 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10401 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10402 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10406 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10407 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10408 int immh
, int immb
, int opcode
, int rn
, int rd
)
10410 int immhb
= immh
<< 3 | immb
;
10411 int size
= 32 - clz32(immh
) - 1;
10413 int esize
= 8 << size
;
10414 int elements
= dsize
/esize
;
10415 int shift
= (2 * esize
) - immhb
;
10416 bool round
= extract32(opcode
, 0, 1);
10417 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10418 TCGv_i64 tcg_round
;
10421 if (extract32(immh
, 3, 1)) {
10422 unallocated_encoding(s
);
10426 if (!fp_access_check(s
)) {
10430 tcg_rn
= tcg_temp_new_i64();
10431 tcg_rd
= tcg_temp_new_i64();
10432 tcg_final
= tcg_temp_new_i64();
10433 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10436 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
10441 for (i
= 0; i
< elements
; i
++) {
10442 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10443 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10444 false, true, size
+1, shift
);
10446 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10450 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10452 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10455 clear_vec_high(s
, is_q
, rd
);
10459 /* AdvSIMD shift by immediate
10460 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10461 * +---+---+---+-------------+------+------+--------+---+------+------+
10462 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10463 * +---+---+---+-------------+------+------+--------+---+------+------+
10465 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10467 int rd
= extract32(insn
, 0, 5);
10468 int rn
= extract32(insn
, 5, 5);
10469 int opcode
= extract32(insn
, 11, 5);
10470 int immb
= extract32(insn
, 16, 3);
10471 int immh
= extract32(insn
, 19, 4);
10472 bool is_u
= extract32(insn
, 29, 1);
10473 bool is_q
= extract32(insn
, 30, 1);
10475 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10479 case 0x08: /* SRI */
10481 unallocated_encoding(s
);
10485 case 0x00: /* SSHR / USHR */
10486 case 0x02: /* SSRA / USRA (accumulate) */
10487 case 0x04: /* SRSHR / URSHR (rounding) */
10488 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10489 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10491 case 0x0a: /* SHL / SLI */
10492 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10494 case 0x10: /* SHRN */
10495 case 0x11: /* RSHRN / SQRSHRUN */
10497 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10500 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10503 case 0x12: /* SQSHRN / UQSHRN */
10504 case 0x13: /* SQRSHRN / UQRSHRN */
10505 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10508 case 0x14: /* SSHLL / USHLL */
10509 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10511 case 0x1c: /* SCVTF / UCVTF */
10512 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10515 case 0xc: /* SQSHLU */
10517 unallocated_encoding(s
);
10520 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10522 case 0xe: /* SQSHL, UQSHL */
10523 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10525 case 0x1f: /* FCVTZS/ FCVTZU */
10526 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10529 unallocated_encoding(s
);
10534 /* Generate code to do a "long" addition or subtraction, ie one done in
10535 * TCGv_i64 on vector lanes twice the width specified by size.
10537 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10538 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10540 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10541 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10542 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10543 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10545 NeonGenTwo64OpFn
*genfn
;
10548 genfn
= fns
[size
][is_sub
];
10549 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10552 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10553 int opcode
, int rd
, int rn
, int rm
)
10555 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10556 TCGv_i64 tcg_res
[2];
10559 tcg_res
[0] = tcg_temp_new_i64();
10560 tcg_res
[1] = tcg_temp_new_i64();
10562 /* Does this op do an adding accumulate, a subtracting accumulate,
10563 * or no accumulate at all?
10581 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10582 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10585 /* size == 2 means two 32x32->64 operations; this is worth special
10586 * casing because we can generally handle it inline.
10589 for (pass
= 0; pass
< 2; pass
++) {
10590 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10591 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10592 TCGv_i64 tcg_passres
;
10593 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10595 int elt
= pass
+ is_q
* 2;
10597 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10598 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10601 tcg_passres
= tcg_res
[pass
];
10603 tcg_passres
= tcg_temp_new_i64();
10607 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10608 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10610 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10611 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10613 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10614 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10616 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10617 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10619 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10620 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10621 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10623 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10626 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10627 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10628 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10629 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10631 case 9: /* SQDMLAL, SQDMLAL2 */
10632 case 11: /* SQDMLSL, SQDMLSL2 */
10633 case 13: /* SQDMULL, SQDMULL2 */
10634 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10635 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10636 tcg_passres
, tcg_passres
);
10639 g_assert_not_reached();
10642 if (opcode
== 9 || opcode
== 11) {
10643 /* saturating accumulate ops */
10645 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10647 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10648 tcg_res
[pass
], tcg_passres
);
10649 } else if (accop
> 0) {
10650 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10651 } else if (accop
< 0) {
10652 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10656 /* size 0 or 1, generally helper functions */
10657 for (pass
= 0; pass
< 2; pass
++) {
10658 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10659 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10660 TCGv_i64 tcg_passres
;
10661 int elt
= pass
+ is_q
* 2;
10663 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10664 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10667 tcg_passres
= tcg_res
[pass
];
10669 tcg_passres
= tcg_temp_new_i64();
10673 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10674 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10676 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10677 static NeonGenWidenFn
* const widenfns
[2][2] = {
10678 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10679 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10681 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10683 widenfn(tcg_op2_64
, tcg_op2
);
10684 widenfn(tcg_passres
, tcg_op1
);
10685 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10686 tcg_passres
, tcg_op2_64
);
10689 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10690 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10693 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10695 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10699 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10701 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10705 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10706 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10707 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10710 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10712 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10716 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10718 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10722 case 9: /* SQDMLAL, SQDMLAL2 */
10723 case 11: /* SQDMLSL, SQDMLSL2 */
10724 case 13: /* SQDMULL, SQDMULL2 */
10726 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10727 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10728 tcg_passres
, tcg_passres
);
10731 g_assert_not_reached();
10735 if (opcode
== 9 || opcode
== 11) {
10736 /* saturating accumulate ops */
10738 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10740 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10744 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10745 tcg_res
[pass
], tcg_passres
);
10751 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10752 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10755 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10756 int opcode
, int rd
, int rn
, int rm
)
10758 TCGv_i64 tcg_res
[2];
10759 int part
= is_q
? 2 : 0;
10762 for (pass
= 0; pass
< 2; pass
++) {
10763 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10764 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10765 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10766 static NeonGenWidenFn
* const widenfns
[3][2] = {
10767 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10768 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10769 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10771 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10773 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10774 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10775 widenfn(tcg_op2_wide
, tcg_op2
);
10776 tcg_res
[pass
] = tcg_temp_new_i64();
10777 gen_neon_addl(size
, (opcode
== 3),
10778 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10781 for (pass
= 0; pass
< 2; pass
++) {
10782 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10786 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10788 tcg_gen_addi_i64(in
, in
, 1U << 31);
10789 tcg_gen_extrh_i64_i32(res
, in
);
10792 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10793 int opcode
, int rd
, int rn
, int rm
)
10795 TCGv_i32 tcg_res
[2];
10796 int part
= is_q
? 2 : 0;
10799 for (pass
= 0; pass
< 2; pass
++) {
10800 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10801 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10802 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10803 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10804 { gen_helper_neon_narrow_high_u8
,
10805 gen_helper_neon_narrow_round_high_u8
},
10806 { gen_helper_neon_narrow_high_u16
,
10807 gen_helper_neon_narrow_round_high_u16
},
10808 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10810 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10812 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10813 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10815 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10817 tcg_res
[pass
] = tcg_temp_new_i32();
10818 gennarrow(tcg_res
[pass
], tcg_wideres
);
10821 for (pass
= 0; pass
< 2; pass
++) {
10822 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10824 clear_vec_high(s
, is_q
, rd
);
10827 /* AdvSIMD three different
10828 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10829 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10830 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10831 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10833 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10835 /* Instructions in this group fall into three basic classes
10836 * (in each case with the operation working on each element in
10837 * the input vectors):
10838 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10840 * (2) wide 64 x 128 -> 128
10841 * (3) narrowing 128 x 128 -> 64
10842 * Here we do initial decode, catch unallocated cases and
10843 * dispatch to separate functions for each class.
10845 int is_q
= extract32(insn
, 30, 1);
10846 int is_u
= extract32(insn
, 29, 1);
10847 int size
= extract32(insn
, 22, 2);
10848 int opcode
= extract32(insn
, 12, 4);
10849 int rm
= extract32(insn
, 16, 5);
10850 int rn
= extract32(insn
, 5, 5);
10851 int rd
= extract32(insn
, 0, 5);
10854 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10855 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10856 /* 64 x 128 -> 128 */
10858 unallocated_encoding(s
);
10861 if (!fp_access_check(s
)) {
10864 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10866 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10867 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10868 /* 128 x 128 -> 64 */
10870 unallocated_encoding(s
);
10873 if (!fp_access_check(s
)) {
10876 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10878 case 14: /* PMULL, PMULL2 */
10880 unallocated_encoding(s
);
10884 case 0: /* PMULL.P8 */
10885 if (!fp_access_check(s
)) {
10888 /* The Q field specifies lo/hi half input for this insn. */
10889 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10890 gen_helper_neon_pmull_h
);
10893 case 3: /* PMULL.P64 */
10894 if (!dc_isar_feature(aa64_pmull
, s
)) {
10895 unallocated_encoding(s
);
10898 if (!fp_access_check(s
)) {
10901 /* The Q field specifies lo/hi half input for this insn. */
10902 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10903 gen_helper_gvec_pmull_q
);
10907 unallocated_encoding(s
);
10911 case 9: /* SQDMLAL, SQDMLAL2 */
10912 case 11: /* SQDMLSL, SQDMLSL2 */
10913 case 13: /* SQDMULL, SQDMULL2 */
10914 if (is_u
|| size
== 0) {
10915 unallocated_encoding(s
);
10919 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10920 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10921 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10922 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10923 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10924 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10925 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10926 /* 64 x 64 -> 128 */
10928 unallocated_encoding(s
);
10931 if (!fp_access_check(s
)) {
10935 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10938 /* opcode 15 not allocated */
10939 unallocated_encoding(s
);
10944 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10945 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10947 int rd
= extract32(insn
, 0, 5);
10948 int rn
= extract32(insn
, 5, 5);
10949 int rm
= extract32(insn
, 16, 5);
10950 int size
= extract32(insn
, 22, 2);
10951 bool is_u
= extract32(insn
, 29, 1);
10952 bool is_q
= extract32(insn
, 30, 1);
10954 if (!fp_access_check(s
)) {
10958 switch (size
+ 4 * is_u
) {
10960 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10963 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10966 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10969 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10972 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10975 case 5: /* BSL bitwise select */
10976 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10978 case 6: /* BIT, bitwise insert if true */
10979 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10981 case 7: /* BIF, bitwise insert if false */
10982 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10986 g_assert_not_reached();
10990 /* Pairwise op subgroup of C3.6.16.
10992 * This is called directly or via the handle_3same_float for float pairwise
10993 * operations where the opcode and size are calculated differently.
10995 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10996 int size
, int rn
, int rm
, int rd
)
11001 /* Floating point operations need fpst */
11002 if (opcode
>= 0x58) {
11003 fpst
= fpstatus_ptr(FPST_FPCR
);
11008 if (!fp_access_check(s
)) {
11012 /* These operations work on the concatenated rm:rn, with each pair of
11013 * adjacent elements being operated on to produce an element in the result.
11016 TCGv_i64 tcg_res
[2];
11018 for (pass
= 0; pass
< 2; pass
++) {
11019 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11020 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11021 int passreg
= (pass
== 0) ? rn
: rm
;
11023 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11024 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11025 tcg_res
[pass
] = tcg_temp_new_i64();
11028 case 0x17: /* ADDP */
11029 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11031 case 0x58: /* FMAXNMP */
11032 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11034 case 0x5a: /* FADDP */
11035 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11037 case 0x5e: /* FMAXP */
11038 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11040 case 0x78: /* FMINNMP */
11041 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11043 case 0x7e: /* FMINP */
11044 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11047 g_assert_not_reached();
11051 for (pass
= 0; pass
< 2; pass
++) {
11052 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11055 int maxpass
= is_q
? 4 : 2;
11056 TCGv_i32 tcg_res
[4];
11058 for (pass
= 0; pass
< maxpass
; pass
++) {
11059 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11060 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11061 NeonGenTwoOpFn
*genfn
= NULL
;
11062 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11063 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11065 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11066 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11067 tcg_res
[pass
] = tcg_temp_new_i32();
11070 case 0x17: /* ADDP */
11072 static NeonGenTwoOpFn
* const fns
[3] = {
11073 gen_helper_neon_padd_u8
,
11074 gen_helper_neon_padd_u16
,
11080 case 0x14: /* SMAXP, UMAXP */
11082 static NeonGenTwoOpFn
* const fns
[3][2] = {
11083 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11084 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11085 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11087 genfn
= fns
[size
][u
];
11090 case 0x15: /* SMINP, UMINP */
11092 static NeonGenTwoOpFn
* const fns
[3][2] = {
11093 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11094 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11095 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11097 genfn
= fns
[size
][u
];
11100 /* The FP operations are all on single floats (32 bit) */
11101 case 0x58: /* FMAXNMP */
11102 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11104 case 0x5a: /* FADDP */
11105 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11107 case 0x5e: /* FMAXP */
11108 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11110 case 0x78: /* FMINNMP */
11111 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11113 case 0x7e: /* FMINP */
11114 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11117 g_assert_not_reached();
11120 /* FP ops called directly, otherwise call now */
11122 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11126 for (pass
= 0; pass
< maxpass
; pass
++) {
11127 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11129 clear_vec_high(s
, is_q
, rd
);
11133 /* Floating point op subgroup of C3.6.16. */
11134 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11136 /* For floating point ops, the U, size[1] and opcode bits
11137 * together indicate the operation. size[0] indicates single
11140 int fpopcode
= extract32(insn
, 11, 5)
11141 | (extract32(insn
, 23, 1) << 5)
11142 | (extract32(insn
, 29, 1) << 6);
11143 int is_q
= extract32(insn
, 30, 1);
11144 int size
= extract32(insn
, 22, 1);
11145 int rm
= extract32(insn
, 16, 5);
11146 int rn
= extract32(insn
, 5, 5);
11147 int rd
= extract32(insn
, 0, 5);
11149 int datasize
= is_q
? 128 : 64;
11150 int esize
= 32 << size
;
11151 int elements
= datasize
/ esize
;
11153 if (size
== 1 && !is_q
) {
11154 unallocated_encoding(s
);
11158 switch (fpopcode
) {
11159 case 0x58: /* FMAXNMP */
11160 case 0x5a: /* FADDP */
11161 case 0x5e: /* FMAXP */
11162 case 0x78: /* FMINNMP */
11163 case 0x7e: /* FMINP */
11164 if (size
&& !is_q
) {
11165 unallocated_encoding(s
);
11168 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11171 case 0x1b: /* FMULX */
11172 case 0x1f: /* FRECPS */
11173 case 0x3f: /* FRSQRTS */
11174 case 0x5d: /* FACGE */
11175 case 0x7d: /* FACGT */
11176 case 0x19: /* FMLA */
11177 case 0x39: /* FMLS */
11178 case 0x18: /* FMAXNM */
11179 case 0x1a: /* FADD */
11180 case 0x1c: /* FCMEQ */
11181 case 0x1e: /* FMAX */
11182 case 0x38: /* FMINNM */
11183 case 0x3a: /* FSUB */
11184 case 0x3e: /* FMIN */
11185 case 0x5b: /* FMUL */
11186 case 0x5c: /* FCMGE */
11187 case 0x5f: /* FDIV */
11188 case 0x7a: /* FABD */
11189 case 0x7c: /* FCMGT */
11190 if (!fp_access_check(s
)) {
11193 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11196 case 0x1d: /* FMLAL */
11197 case 0x3d: /* FMLSL */
11198 case 0x59: /* FMLAL2 */
11199 case 0x79: /* FMLSL2 */
11200 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11201 unallocated_encoding(s
);
11204 if (fp_access_check(s
)) {
11205 int is_s
= extract32(insn
, 23, 1);
11206 int is_2
= extract32(insn
, 29, 1);
11207 int data
= (is_2
<< 1) | is_s
;
11208 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11209 vec_full_reg_offset(s
, rn
),
11210 vec_full_reg_offset(s
, rm
), cpu_env
,
11211 is_q
? 16 : 8, vec_full_reg_size(s
),
11212 data
, gen_helper_gvec_fmlal_a64
);
11217 unallocated_encoding(s
);
11222 /* Integer op subgroup of C3.6.16. */
11223 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11225 int is_q
= extract32(insn
, 30, 1);
11226 int u
= extract32(insn
, 29, 1);
11227 int size
= extract32(insn
, 22, 2);
11228 int opcode
= extract32(insn
, 11, 5);
11229 int rm
= extract32(insn
, 16, 5);
11230 int rn
= extract32(insn
, 5, 5);
11231 int rd
= extract32(insn
, 0, 5);
11236 case 0x13: /* MUL, PMUL */
11237 if (u
&& size
!= 0) {
11238 unallocated_encoding(s
);
11242 case 0x0: /* SHADD, UHADD */
11243 case 0x2: /* SRHADD, URHADD */
11244 case 0x4: /* SHSUB, UHSUB */
11245 case 0xc: /* SMAX, UMAX */
11246 case 0xd: /* SMIN, UMIN */
11247 case 0xe: /* SABD, UABD */
11248 case 0xf: /* SABA, UABA */
11249 case 0x12: /* MLA, MLS */
11251 unallocated_encoding(s
);
11255 case 0x16: /* SQDMULH, SQRDMULH */
11256 if (size
== 0 || size
== 3) {
11257 unallocated_encoding(s
);
11262 if (size
== 3 && !is_q
) {
11263 unallocated_encoding(s
);
11269 if (!fp_access_check(s
)) {
11274 case 0x01: /* SQADD, UQADD */
11276 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11278 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11281 case 0x05: /* SQSUB, UQSUB */
11283 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11285 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11288 case 0x08: /* SSHL, USHL */
11290 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11292 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11295 case 0x0c: /* SMAX, UMAX */
11297 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11299 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11302 case 0x0d: /* SMIN, UMIN */
11304 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11306 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11309 case 0xe: /* SABD, UABD */
11311 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11313 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11316 case 0xf: /* SABA, UABA */
11318 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11320 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11323 case 0x10: /* ADD, SUB */
11325 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11327 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11330 case 0x13: /* MUL, PMUL */
11331 if (!u
) { /* MUL */
11332 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11333 } else { /* PMUL */
11334 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11337 case 0x12: /* MLA, MLS */
11339 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11341 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11344 case 0x16: /* SQDMULH, SQRDMULH */
11346 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11347 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11348 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11350 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11354 if (!u
) { /* CMTST */
11355 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11359 cond
= TCG_COND_EQ
;
11361 case 0x06: /* CMGT, CMHI */
11362 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11364 case 0x07: /* CMGE, CMHS */
11365 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11367 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11368 vec_full_reg_offset(s
, rn
),
11369 vec_full_reg_offset(s
, rm
),
11370 is_q
? 16 : 8, vec_full_reg_size(s
));
11376 for (pass
= 0; pass
< 2; pass
++) {
11377 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11378 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11379 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11381 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11382 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11384 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11386 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11389 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11390 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11391 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11392 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11393 NeonGenTwoOpFn
*genfn
= NULL
;
11394 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11396 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11397 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11400 case 0x0: /* SHADD, UHADD */
11402 static NeonGenTwoOpFn
* const fns
[3][2] = {
11403 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11404 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11405 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11407 genfn
= fns
[size
][u
];
11410 case 0x2: /* SRHADD, URHADD */
11412 static NeonGenTwoOpFn
* const fns
[3][2] = {
11413 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11414 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11415 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11417 genfn
= fns
[size
][u
];
11420 case 0x4: /* SHSUB, UHSUB */
11422 static NeonGenTwoOpFn
* const fns
[3][2] = {
11423 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11424 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11425 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11427 genfn
= fns
[size
][u
];
11430 case 0x9: /* SQSHL, UQSHL */
11432 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11433 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11434 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11435 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11437 genenvfn
= fns
[size
][u
];
11440 case 0xa: /* SRSHL, URSHL */
11442 static NeonGenTwoOpFn
* const fns
[3][2] = {
11443 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11444 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11445 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11447 genfn
= fns
[size
][u
];
11450 case 0xb: /* SQRSHL, UQRSHL */
11452 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11453 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11454 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11455 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11457 genenvfn
= fns
[size
][u
];
11461 g_assert_not_reached();
11465 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11467 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11470 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11473 clear_vec_high(s
, is_q
, rd
);
11476 /* AdvSIMD three same
11477 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11478 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11479 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11480 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11482 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11484 int opcode
= extract32(insn
, 11, 5);
11487 case 0x3: /* logic ops */
11488 disas_simd_3same_logic(s
, insn
);
11490 case 0x17: /* ADDP */
11491 case 0x14: /* SMAXP, UMAXP */
11492 case 0x15: /* SMINP, UMINP */
11494 /* Pairwise operations */
11495 int is_q
= extract32(insn
, 30, 1);
11496 int u
= extract32(insn
, 29, 1);
11497 int size
= extract32(insn
, 22, 2);
11498 int rm
= extract32(insn
, 16, 5);
11499 int rn
= extract32(insn
, 5, 5);
11500 int rd
= extract32(insn
, 0, 5);
11501 if (opcode
== 0x17) {
11502 if (u
|| (size
== 3 && !is_q
)) {
11503 unallocated_encoding(s
);
11508 unallocated_encoding(s
);
11512 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11515 case 0x18 ... 0x31:
11516 /* floating point ops, sz[1] and U are part of opcode */
11517 disas_simd_3same_float(s
, insn
);
11520 disas_simd_3same_int(s
, insn
);
11526 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11528 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11529 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11530 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11531 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11533 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11534 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11537 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11539 int opcode
= extract32(insn
, 11, 3);
11540 int u
= extract32(insn
, 29, 1);
11541 int a
= extract32(insn
, 23, 1);
11542 int is_q
= extract32(insn
, 30, 1);
11543 int rm
= extract32(insn
, 16, 5);
11544 int rn
= extract32(insn
, 5, 5);
11545 int rd
= extract32(insn
, 0, 5);
11547 * For these floating point ops, the U, a and opcode bits
11548 * together indicate the operation.
11550 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11551 int datasize
= is_q
? 128 : 64;
11552 int elements
= datasize
/ 16;
11557 switch (fpopcode
) {
11558 case 0x0: /* FMAXNM */
11559 case 0x1: /* FMLA */
11560 case 0x2: /* FADD */
11561 case 0x3: /* FMULX */
11562 case 0x4: /* FCMEQ */
11563 case 0x6: /* FMAX */
11564 case 0x7: /* FRECPS */
11565 case 0x8: /* FMINNM */
11566 case 0x9: /* FMLS */
11567 case 0xa: /* FSUB */
11568 case 0xe: /* FMIN */
11569 case 0xf: /* FRSQRTS */
11570 case 0x13: /* FMUL */
11571 case 0x14: /* FCMGE */
11572 case 0x15: /* FACGE */
11573 case 0x17: /* FDIV */
11574 case 0x1a: /* FABD */
11575 case 0x1c: /* FCMGT */
11576 case 0x1d: /* FACGT */
11579 case 0x10: /* FMAXNMP */
11580 case 0x12: /* FADDP */
11581 case 0x16: /* FMAXP */
11582 case 0x18: /* FMINNMP */
11583 case 0x1e: /* FMINP */
11587 unallocated_encoding(s
);
11591 if (!dc_isar_feature(aa64_fp16
, s
)) {
11592 unallocated_encoding(s
);
11596 if (!fp_access_check(s
)) {
11600 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
11603 int maxpass
= is_q
? 8 : 4;
11604 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11605 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11606 TCGv_i32 tcg_res
[8];
11608 for (pass
= 0; pass
< maxpass
; pass
++) {
11609 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11610 int passelt
= (pass
<< 1) & (maxpass
- 1);
11612 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11613 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11614 tcg_res
[pass
] = tcg_temp_new_i32();
11616 switch (fpopcode
) {
11617 case 0x10: /* FMAXNMP */
11618 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11621 case 0x12: /* FADDP */
11622 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11624 case 0x16: /* FMAXP */
11625 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11627 case 0x18: /* FMINNMP */
11628 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11631 case 0x1e: /* FMINP */
11632 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11635 g_assert_not_reached();
11639 for (pass
= 0; pass
< maxpass
; pass
++) {
11640 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11643 for (pass
= 0; pass
< elements
; pass
++) {
11644 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11645 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11646 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11648 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11649 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11651 switch (fpopcode
) {
11652 case 0x0: /* FMAXNM */
11653 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11655 case 0x1: /* FMLA */
11656 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11657 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11660 case 0x2: /* FADD */
11661 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11663 case 0x3: /* FMULX */
11664 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11666 case 0x4: /* FCMEQ */
11667 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11669 case 0x6: /* FMAX */
11670 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11672 case 0x7: /* FRECPS */
11673 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11675 case 0x8: /* FMINNM */
11676 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11678 case 0x9: /* FMLS */
11679 /* As usual for ARM, separate negation for fused multiply-add */
11680 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11681 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11682 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11685 case 0xa: /* FSUB */
11686 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11688 case 0xe: /* FMIN */
11689 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11691 case 0xf: /* FRSQRTS */
11692 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11694 case 0x13: /* FMUL */
11695 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11697 case 0x14: /* FCMGE */
11698 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11700 case 0x15: /* FACGE */
11701 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11703 case 0x17: /* FDIV */
11704 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11706 case 0x1a: /* FABD */
11707 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11708 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11710 case 0x1c: /* FCMGT */
11711 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11713 case 0x1d: /* FACGT */
11714 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11717 g_assert_not_reached();
11720 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11724 clear_vec_high(s
, is_q
, rd
);
11727 /* AdvSIMD three same extra
11728 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11729 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11730 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11731 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11733 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11735 int rd
= extract32(insn
, 0, 5);
11736 int rn
= extract32(insn
, 5, 5);
11737 int opcode
= extract32(insn
, 11, 4);
11738 int rm
= extract32(insn
, 16, 5);
11739 int size
= extract32(insn
, 22, 2);
11740 bool u
= extract32(insn
, 29, 1);
11741 bool is_q
= extract32(insn
, 30, 1);
11745 switch (u
* 16 + opcode
) {
11746 case 0x10: /* SQRDMLAH (vector) */
11747 case 0x11: /* SQRDMLSH (vector) */
11748 if (size
!= 1 && size
!= 2) {
11749 unallocated_encoding(s
);
11752 feature
= dc_isar_feature(aa64_rdm
, s
);
11754 case 0x02: /* SDOT (vector) */
11755 case 0x12: /* UDOT (vector) */
11756 if (size
!= MO_32
) {
11757 unallocated_encoding(s
);
11760 feature
= dc_isar_feature(aa64_dp
, s
);
11762 case 0x03: /* USDOT */
11763 if (size
!= MO_32
) {
11764 unallocated_encoding(s
);
11767 feature
= dc_isar_feature(aa64_i8mm
, s
);
11769 case 0x04: /* SMMLA */
11770 case 0x14: /* UMMLA */
11771 case 0x05: /* USMMLA */
11772 if (!is_q
|| size
!= MO_32
) {
11773 unallocated_encoding(s
);
11776 feature
= dc_isar_feature(aa64_i8mm
, s
);
11778 case 0x18: /* FCMLA, #0 */
11779 case 0x19: /* FCMLA, #90 */
11780 case 0x1a: /* FCMLA, #180 */
11781 case 0x1b: /* FCMLA, #270 */
11782 case 0x1c: /* FCADD, #90 */
11783 case 0x1e: /* FCADD, #270 */
11785 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11786 || (size
== 3 && !is_q
)) {
11787 unallocated_encoding(s
);
11790 feature
= dc_isar_feature(aa64_fcma
, s
);
11792 case 0x1d: /* BFMMLA */
11793 if (size
!= MO_16
|| !is_q
) {
11794 unallocated_encoding(s
);
11797 feature
= dc_isar_feature(aa64_bf16
, s
);
11801 case 1: /* BFDOT */
11802 case 3: /* BFMLAL{B,T} */
11803 feature
= dc_isar_feature(aa64_bf16
, s
);
11806 unallocated_encoding(s
);
11811 unallocated_encoding(s
);
11815 unallocated_encoding(s
);
11818 if (!fp_access_check(s
)) {
11823 case 0x0: /* SQRDMLAH (vector) */
11824 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
11827 case 0x1: /* SQRDMLSH (vector) */
11828 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
11831 case 0x2: /* SDOT / UDOT */
11832 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
11833 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11836 case 0x3: /* USDOT */
11837 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
11840 case 0x04: /* SMMLA, UMMLA */
11841 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
11842 u
? gen_helper_gvec_ummla_b
11843 : gen_helper_gvec_smmla_b
);
11845 case 0x05: /* USMMLA */
11846 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
11849 case 0x8: /* FCMLA, #0 */
11850 case 0x9: /* FCMLA, #90 */
11851 case 0xa: /* FCMLA, #180 */
11852 case 0xb: /* FCMLA, #270 */
11853 rot
= extract32(opcode
, 0, 2);
11856 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
11857 gen_helper_gvec_fcmlah
);
11860 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
11861 gen_helper_gvec_fcmlas
);
11864 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
11865 gen_helper_gvec_fcmlad
);
11868 g_assert_not_reached();
11872 case 0xc: /* FCADD, #90 */
11873 case 0xe: /* FCADD, #270 */
11874 rot
= extract32(opcode
, 1, 1);
11877 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11878 gen_helper_gvec_fcaddh
);
11881 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11882 gen_helper_gvec_fcadds
);
11885 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11886 gen_helper_gvec_fcaddd
);
11889 g_assert_not_reached();
11893 case 0xd: /* BFMMLA */
11894 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfmmla
);
11898 case 1: /* BFDOT */
11899 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfdot
);
11901 case 3: /* BFMLAL{B,T} */
11902 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, false, is_q
,
11903 gen_helper_gvec_bfmlal
);
11906 g_assert_not_reached();
11911 g_assert_not_reached();
11915 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11916 int size
, int rn
, int rd
)
11918 /* Handle 2-reg-misc ops which are widening (so each size element
11919 * in the source becomes a 2*size element in the destination.
11920 * The only instruction like this is FCVTL.
11925 /* 32 -> 64 bit fp conversion */
11926 TCGv_i64 tcg_res
[2];
11927 int srcelt
= is_q
? 2 : 0;
11929 for (pass
= 0; pass
< 2; pass
++) {
11930 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11931 tcg_res
[pass
] = tcg_temp_new_i64();
11933 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11934 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11936 for (pass
= 0; pass
< 2; pass
++) {
11937 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11940 /* 16 -> 32 bit fp conversion */
11941 int srcelt
= is_q
? 4 : 0;
11942 TCGv_i32 tcg_res
[4];
11943 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
11944 TCGv_i32 ahp
= get_ahp_flag();
11946 for (pass
= 0; pass
< 4; pass
++) {
11947 tcg_res
[pass
] = tcg_temp_new_i32();
11949 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11950 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11953 for (pass
= 0; pass
< 4; pass
++) {
11954 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11959 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11960 bool is_q
, int size
, int rn
, int rd
)
11962 int op
= (opcode
<< 1) | u
;
11963 int opsz
= op
+ size
;
11964 int grp_size
= 3 - opsz
;
11965 int dsize
= is_q
? 128 : 64;
11969 unallocated_encoding(s
);
11973 if (!fp_access_check(s
)) {
11978 /* Special case bytes, use bswap op on each group of elements */
11979 int groups
= dsize
/ (8 << grp_size
);
11981 for (i
= 0; i
< groups
; i
++) {
11982 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11984 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11985 switch (grp_size
) {
11987 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
11990 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
11993 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11996 g_assert_not_reached();
11998 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12000 clear_vec_high(s
, is_q
, rd
);
12002 int revmask
= (1 << grp_size
) - 1;
12003 int esize
= 8 << size
;
12004 int elements
= dsize
/ esize
;
12005 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12006 TCGv_i64 tcg_rd
[2];
12008 for (i
= 0; i
< 2; i
++) {
12009 tcg_rd
[i
] = tcg_temp_new_i64();
12010 tcg_gen_movi_i64(tcg_rd
[i
], 0);
12013 for (i
= 0; i
< elements
; i
++) {
12014 int e_rev
= (i
& 0xf) ^ revmask
;
12015 int w
= (e_rev
* esize
) / 64;
12016 int o
= (e_rev
* esize
) % 64;
12018 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12019 tcg_gen_deposit_i64(tcg_rd
[w
], tcg_rd
[w
], tcg_rn
, o
, esize
);
12022 for (i
= 0; i
< 2; i
++) {
12023 write_vec_element(s
, tcg_rd
[i
], rd
, i
, MO_64
);
12025 clear_vec_high(s
, true, rd
);
12029 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12030 bool is_q
, int size
, int rn
, int rd
)
12032 /* Implement the pairwise operations from 2-misc:
12033 * SADDLP, UADDLP, SADALP, UADALP.
12034 * These all add pairs of elements in the input to produce a
12035 * double-width result element in the output (possibly accumulating).
12037 bool accum
= (opcode
== 0x6);
12038 int maxpass
= is_q
? 2 : 1;
12040 TCGv_i64 tcg_res
[2];
12043 /* 32 + 32 -> 64 op */
12044 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12046 for (pass
= 0; pass
< maxpass
; pass
++) {
12047 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12048 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12050 tcg_res
[pass
] = tcg_temp_new_i64();
12052 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12053 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12054 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12056 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12057 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12061 for (pass
= 0; pass
< maxpass
; pass
++) {
12062 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12063 NeonGenOne64OpFn
*genfn
;
12064 static NeonGenOne64OpFn
* const fns
[2][2] = {
12065 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12066 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12069 genfn
= fns
[size
][u
];
12071 tcg_res
[pass
] = tcg_temp_new_i64();
12073 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12074 genfn(tcg_res
[pass
], tcg_op
);
12077 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12079 gen_helper_neon_addl_u16(tcg_res
[pass
],
12080 tcg_res
[pass
], tcg_op
);
12082 gen_helper_neon_addl_u32(tcg_res
[pass
],
12083 tcg_res
[pass
], tcg_op
);
12089 tcg_res
[1] = tcg_constant_i64(0);
12091 for (pass
= 0; pass
< 2; pass
++) {
12092 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12096 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12098 /* Implement SHLL and SHLL2 */
12100 int part
= is_q
? 2 : 0;
12101 TCGv_i64 tcg_res
[2];
12103 for (pass
= 0; pass
< 2; pass
++) {
12104 static NeonGenWidenFn
* const widenfns
[3] = {
12105 gen_helper_neon_widen_u8
,
12106 gen_helper_neon_widen_u16
,
12107 tcg_gen_extu_i32_i64
,
12109 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12110 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12112 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12113 tcg_res
[pass
] = tcg_temp_new_i64();
12114 widenfn(tcg_res
[pass
], tcg_op
);
12115 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12118 for (pass
= 0; pass
< 2; pass
++) {
12119 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12123 /* AdvSIMD two reg misc
12124 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12125 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12126 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12127 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12129 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12131 int size
= extract32(insn
, 22, 2);
12132 int opcode
= extract32(insn
, 12, 5);
12133 bool u
= extract32(insn
, 29, 1);
12134 bool is_q
= extract32(insn
, 30, 1);
12135 int rn
= extract32(insn
, 5, 5);
12136 int rd
= extract32(insn
, 0, 5);
12137 bool need_fpstatus
= false;
12139 TCGv_i32 tcg_rmode
;
12140 TCGv_ptr tcg_fpstatus
;
12143 case 0x0: /* REV64, REV32 */
12144 case 0x1: /* REV16 */
12145 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12147 case 0x5: /* CNT, NOT, RBIT */
12148 if (u
&& size
== 0) {
12151 } else if (u
&& size
== 1) {
12154 } else if (!u
&& size
== 0) {
12158 unallocated_encoding(s
);
12160 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12161 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12163 unallocated_encoding(s
);
12166 if (!fp_access_check(s
)) {
12170 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12172 case 0x4: /* CLS, CLZ */
12174 unallocated_encoding(s
);
12178 case 0x2: /* SADDLP, UADDLP */
12179 case 0x6: /* SADALP, UADALP */
12181 unallocated_encoding(s
);
12184 if (!fp_access_check(s
)) {
12187 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12189 case 0x13: /* SHLL, SHLL2 */
12190 if (u
== 0 || size
== 3) {
12191 unallocated_encoding(s
);
12194 if (!fp_access_check(s
)) {
12197 handle_shll(s
, is_q
, size
, rn
, rd
);
12199 case 0xa: /* CMLT */
12201 unallocated_encoding(s
);
12205 case 0x8: /* CMGT, CMGE */
12206 case 0x9: /* CMEQ, CMLE */
12207 case 0xb: /* ABS, NEG */
12208 if (size
== 3 && !is_q
) {
12209 unallocated_encoding(s
);
12213 case 0x3: /* SUQADD, USQADD */
12214 if (size
== 3 && !is_q
) {
12215 unallocated_encoding(s
);
12218 if (!fp_access_check(s
)) {
12221 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12223 case 0x7: /* SQABS, SQNEG */
12224 if (size
== 3 && !is_q
) {
12225 unallocated_encoding(s
);
12230 case 0x16 ... 0x1f:
12232 /* Floating point: U, size[1] and opcode indicate operation;
12233 * size[0] indicates single or double precision.
12235 int is_double
= extract32(size
, 0, 1);
12236 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12237 size
= is_double
? 3 : 2;
12239 case 0x2f: /* FABS */
12240 case 0x6f: /* FNEG */
12241 if (size
== 3 && !is_q
) {
12242 unallocated_encoding(s
);
12246 case 0x1d: /* SCVTF */
12247 case 0x5d: /* UCVTF */
12249 bool is_signed
= (opcode
== 0x1d) ? true : false;
12250 int elements
= is_double
? 2 : is_q
? 4 : 2;
12251 if (is_double
&& !is_q
) {
12252 unallocated_encoding(s
);
12255 if (!fp_access_check(s
)) {
12258 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12261 case 0x2c: /* FCMGT (zero) */
12262 case 0x2d: /* FCMEQ (zero) */
12263 case 0x2e: /* FCMLT (zero) */
12264 case 0x6c: /* FCMGE (zero) */
12265 case 0x6d: /* FCMLE (zero) */
12266 if (size
== 3 && !is_q
) {
12267 unallocated_encoding(s
);
12270 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12272 case 0x7f: /* FSQRT */
12273 if (size
== 3 && !is_q
) {
12274 unallocated_encoding(s
);
12278 case 0x1a: /* FCVTNS */
12279 case 0x1b: /* FCVTMS */
12280 case 0x3a: /* FCVTPS */
12281 case 0x3b: /* FCVTZS */
12282 case 0x5a: /* FCVTNU */
12283 case 0x5b: /* FCVTMU */
12284 case 0x7a: /* FCVTPU */
12285 case 0x7b: /* FCVTZU */
12286 need_fpstatus
= true;
12287 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12288 if (size
== 3 && !is_q
) {
12289 unallocated_encoding(s
);
12293 case 0x5c: /* FCVTAU */
12294 case 0x1c: /* FCVTAS */
12295 need_fpstatus
= true;
12296 rmode
= FPROUNDING_TIEAWAY
;
12297 if (size
== 3 && !is_q
) {
12298 unallocated_encoding(s
);
12302 case 0x3c: /* URECPE */
12304 unallocated_encoding(s
);
12308 case 0x3d: /* FRECPE */
12309 case 0x7d: /* FRSQRTE */
12310 if (size
== 3 && !is_q
) {
12311 unallocated_encoding(s
);
12314 if (!fp_access_check(s
)) {
12317 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12319 case 0x56: /* FCVTXN, FCVTXN2 */
12321 unallocated_encoding(s
);
12325 case 0x16: /* FCVTN, FCVTN2 */
12326 /* handle_2misc_narrow does a 2*size -> size operation, but these
12327 * instructions encode the source size rather than dest size.
12329 if (!fp_access_check(s
)) {
12332 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12334 case 0x36: /* BFCVTN, BFCVTN2 */
12335 if (!dc_isar_feature(aa64_bf16
, s
) || size
!= 2) {
12336 unallocated_encoding(s
);
12339 if (!fp_access_check(s
)) {
12342 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12344 case 0x17: /* FCVTL, FCVTL2 */
12345 if (!fp_access_check(s
)) {
12348 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12350 case 0x18: /* FRINTN */
12351 case 0x19: /* FRINTM */
12352 case 0x38: /* FRINTP */
12353 case 0x39: /* FRINTZ */
12354 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12356 case 0x59: /* FRINTX */
12357 case 0x79: /* FRINTI */
12358 need_fpstatus
= true;
12359 if (size
== 3 && !is_q
) {
12360 unallocated_encoding(s
);
12364 case 0x58: /* FRINTA */
12365 rmode
= FPROUNDING_TIEAWAY
;
12366 need_fpstatus
= true;
12367 if (size
== 3 && !is_q
) {
12368 unallocated_encoding(s
);
12372 case 0x7c: /* URSQRTE */
12374 unallocated_encoding(s
);
12378 case 0x1e: /* FRINT32Z */
12379 case 0x1f: /* FRINT64Z */
12380 rmode
= FPROUNDING_ZERO
;
12382 case 0x5e: /* FRINT32X */
12383 case 0x5f: /* FRINT64X */
12384 need_fpstatus
= true;
12385 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12386 unallocated_encoding(s
);
12391 unallocated_encoding(s
);
12397 unallocated_encoding(s
);
12401 if (!fp_access_check(s
)) {
12405 if (need_fpstatus
|| rmode
>= 0) {
12406 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12408 tcg_fpstatus
= NULL
;
12411 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
12418 if (u
&& size
== 0) { /* NOT */
12419 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12423 case 0x8: /* CMGT, CMGE */
12425 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12427 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12430 case 0x9: /* CMEQ, CMLE */
12432 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12434 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12437 case 0xa: /* CMLT */
12438 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12441 if (u
) { /* ABS, NEG */
12442 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12444 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12450 /* All 64-bit element operations can be shared with scalar 2misc */
12453 /* Coverity claims (size == 3 && !is_q) has been eliminated
12454 * from all paths leading to here.
12456 tcg_debug_assert(is_q
);
12457 for (pass
= 0; pass
< 2; pass
++) {
12458 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12459 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12461 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12463 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12464 tcg_rmode
, tcg_fpstatus
);
12466 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12471 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12472 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12473 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12475 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12478 /* Special cases for 32 bit elements */
12480 case 0x4: /* CLS */
12482 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12484 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12487 case 0x7: /* SQABS, SQNEG */
12489 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12491 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12494 case 0x2f: /* FABS */
12495 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12497 case 0x6f: /* FNEG */
12498 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12500 case 0x7f: /* FSQRT */
12501 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12503 case 0x1a: /* FCVTNS */
12504 case 0x1b: /* FCVTMS */
12505 case 0x1c: /* FCVTAS */
12506 case 0x3a: /* FCVTPS */
12507 case 0x3b: /* FCVTZS */
12508 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12509 tcg_constant_i32(0), tcg_fpstatus
);
12511 case 0x5a: /* FCVTNU */
12512 case 0x5b: /* FCVTMU */
12513 case 0x5c: /* FCVTAU */
12514 case 0x7a: /* FCVTPU */
12515 case 0x7b: /* FCVTZU */
12516 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12517 tcg_constant_i32(0), tcg_fpstatus
);
12519 case 0x18: /* FRINTN */
12520 case 0x19: /* FRINTM */
12521 case 0x38: /* FRINTP */
12522 case 0x39: /* FRINTZ */
12523 case 0x58: /* FRINTA */
12524 case 0x79: /* FRINTI */
12525 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12527 case 0x59: /* FRINTX */
12528 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12530 case 0x7c: /* URSQRTE */
12531 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12533 case 0x1e: /* FRINT32Z */
12534 case 0x5e: /* FRINT32X */
12535 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12537 case 0x1f: /* FRINT64Z */
12538 case 0x5f: /* FRINT64X */
12539 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12542 g_assert_not_reached();
12545 /* Use helpers for 8 and 16 bit elements */
12547 case 0x5: /* CNT, RBIT */
12548 /* For these two insns size is part of the opcode specifier
12549 * (handled earlier); they always operate on byte elements.
12552 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12554 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12557 case 0x7: /* SQABS, SQNEG */
12559 NeonGenOneOpEnvFn
*genfn
;
12560 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12561 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12562 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12564 genfn
= fns
[size
][u
];
12565 genfn(tcg_res
, cpu_env
, tcg_op
);
12568 case 0x4: /* CLS, CLZ */
12571 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12573 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12577 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12579 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12584 g_assert_not_reached();
12588 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12591 clear_vec_high(s
, is_q
, rd
);
12594 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
12598 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12600 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12601 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12602 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12603 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12604 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12605 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12607 * This actually covers two groups where scalar access is governed by
12608 * bit 28. A bunch of the instructions (float to integral) only exist
12609 * in the vector form and are un-allocated for the scalar decode. Also
12610 * in the scalar decode Q is always 1.
12612 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12614 int fpop
, opcode
, a
, u
;
12618 bool only_in_vector
= false;
12621 TCGv_i32 tcg_rmode
= NULL
;
12622 TCGv_ptr tcg_fpstatus
= NULL
;
12623 bool need_fpst
= true;
12626 if (!dc_isar_feature(aa64_fp16
, s
)) {
12627 unallocated_encoding(s
);
12631 rd
= extract32(insn
, 0, 5);
12632 rn
= extract32(insn
, 5, 5);
12634 a
= extract32(insn
, 23, 1);
12635 u
= extract32(insn
, 29, 1);
12636 is_scalar
= extract32(insn
, 28, 1);
12637 is_q
= extract32(insn
, 30, 1);
12639 opcode
= extract32(insn
, 12, 5);
12640 fpop
= deposit32(opcode
, 5, 1, a
);
12641 fpop
= deposit32(fpop
, 6, 1, u
);
12644 case 0x1d: /* SCVTF */
12645 case 0x5d: /* UCVTF */
12652 elements
= (is_q
? 8 : 4);
12655 if (!fp_access_check(s
)) {
12658 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12662 case 0x2c: /* FCMGT (zero) */
12663 case 0x2d: /* FCMEQ (zero) */
12664 case 0x2e: /* FCMLT (zero) */
12665 case 0x6c: /* FCMGE (zero) */
12666 case 0x6d: /* FCMLE (zero) */
12667 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12669 case 0x3d: /* FRECPE */
12670 case 0x3f: /* FRECPX */
12672 case 0x18: /* FRINTN */
12673 only_in_vector
= true;
12674 rmode
= FPROUNDING_TIEEVEN
;
12676 case 0x19: /* FRINTM */
12677 only_in_vector
= true;
12678 rmode
= FPROUNDING_NEGINF
;
12680 case 0x38: /* FRINTP */
12681 only_in_vector
= true;
12682 rmode
= FPROUNDING_POSINF
;
12684 case 0x39: /* FRINTZ */
12685 only_in_vector
= true;
12686 rmode
= FPROUNDING_ZERO
;
12688 case 0x58: /* FRINTA */
12689 only_in_vector
= true;
12690 rmode
= FPROUNDING_TIEAWAY
;
12692 case 0x59: /* FRINTX */
12693 case 0x79: /* FRINTI */
12694 only_in_vector
= true;
12695 /* current rounding mode */
12697 case 0x1a: /* FCVTNS */
12698 rmode
= FPROUNDING_TIEEVEN
;
12700 case 0x1b: /* FCVTMS */
12701 rmode
= FPROUNDING_NEGINF
;
12703 case 0x1c: /* FCVTAS */
12704 rmode
= FPROUNDING_TIEAWAY
;
12706 case 0x3a: /* FCVTPS */
12707 rmode
= FPROUNDING_POSINF
;
12709 case 0x3b: /* FCVTZS */
12710 rmode
= FPROUNDING_ZERO
;
12712 case 0x5a: /* FCVTNU */
12713 rmode
= FPROUNDING_TIEEVEN
;
12715 case 0x5b: /* FCVTMU */
12716 rmode
= FPROUNDING_NEGINF
;
12718 case 0x5c: /* FCVTAU */
12719 rmode
= FPROUNDING_TIEAWAY
;
12721 case 0x7a: /* FCVTPU */
12722 rmode
= FPROUNDING_POSINF
;
12724 case 0x7b: /* FCVTZU */
12725 rmode
= FPROUNDING_ZERO
;
12727 case 0x2f: /* FABS */
12728 case 0x6f: /* FNEG */
12731 case 0x7d: /* FRSQRTE */
12732 case 0x7f: /* FSQRT (vector) */
12735 unallocated_encoding(s
);
12740 /* Check additional constraints for the scalar encoding */
12743 unallocated_encoding(s
);
12746 /* FRINTxx is only in the vector form */
12747 if (only_in_vector
) {
12748 unallocated_encoding(s
);
12753 if (!fp_access_check(s
)) {
12757 if (rmode
>= 0 || need_fpst
) {
12758 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
12762 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
12766 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12767 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12770 case 0x1a: /* FCVTNS */
12771 case 0x1b: /* FCVTMS */
12772 case 0x1c: /* FCVTAS */
12773 case 0x3a: /* FCVTPS */
12774 case 0x3b: /* FCVTZS */
12775 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12777 case 0x3d: /* FRECPE */
12778 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12780 case 0x3f: /* FRECPX */
12781 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12783 case 0x5a: /* FCVTNU */
12784 case 0x5b: /* FCVTMU */
12785 case 0x5c: /* FCVTAU */
12786 case 0x7a: /* FCVTPU */
12787 case 0x7b: /* FCVTZU */
12788 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12790 case 0x6f: /* FNEG */
12791 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12793 case 0x7d: /* FRSQRTE */
12794 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12797 g_assert_not_reached();
12800 /* limit any sign extension going on */
12801 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12802 write_fp_sreg(s
, rd
, tcg_res
);
12804 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12805 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12806 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12808 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12811 case 0x1a: /* FCVTNS */
12812 case 0x1b: /* FCVTMS */
12813 case 0x1c: /* FCVTAS */
12814 case 0x3a: /* FCVTPS */
12815 case 0x3b: /* FCVTZS */
12816 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12818 case 0x3d: /* FRECPE */
12819 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12821 case 0x5a: /* FCVTNU */
12822 case 0x5b: /* FCVTMU */
12823 case 0x5c: /* FCVTAU */
12824 case 0x7a: /* FCVTPU */
12825 case 0x7b: /* FCVTZU */
12826 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12828 case 0x18: /* FRINTN */
12829 case 0x19: /* FRINTM */
12830 case 0x38: /* FRINTP */
12831 case 0x39: /* FRINTZ */
12832 case 0x58: /* FRINTA */
12833 case 0x79: /* FRINTI */
12834 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12836 case 0x59: /* FRINTX */
12837 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12839 case 0x2f: /* FABS */
12840 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12842 case 0x6f: /* FNEG */
12843 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12845 case 0x7d: /* FRSQRTE */
12846 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12848 case 0x7f: /* FSQRT */
12849 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12852 g_assert_not_reached();
12855 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12858 clear_vec_high(s
, is_q
, rd
);
12862 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
12866 /* AdvSIMD scalar x indexed element
12867 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12868 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12869 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12870 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12871 * AdvSIMD vector x indexed element
12872 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12873 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12874 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12875 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12877 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12879 /* This encoding has two kinds of instruction:
12880 * normal, where we perform elt x idxelt => elt for each
12881 * element in the vector
12882 * long, where we perform elt x idxelt and generate a result of
12883 * double the width of the input element
12884 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12886 bool is_scalar
= extract32(insn
, 28, 1);
12887 bool is_q
= extract32(insn
, 30, 1);
12888 bool u
= extract32(insn
, 29, 1);
12889 int size
= extract32(insn
, 22, 2);
12890 int l
= extract32(insn
, 21, 1);
12891 int m
= extract32(insn
, 20, 1);
12892 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12893 int rm
= extract32(insn
, 16, 4);
12894 int opcode
= extract32(insn
, 12, 4);
12895 int h
= extract32(insn
, 11, 1);
12896 int rn
= extract32(insn
, 5, 5);
12897 int rd
= extract32(insn
, 0, 5);
12898 bool is_long
= false;
12900 bool is_fp16
= false;
12904 switch (16 * u
+ opcode
) {
12905 case 0x08: /* MUL */
12906 case 0x10: /* MLA */
12907 case 0x14: /* MLS */
12909 unallocated_encoding(s
);
12913 case 0x02: /* SMLAL, SMLAL2 */
12914 case 0x12: /* UMLAL, UMLAL2 */
12915 case 0x06: /* SMLSL, SMLSL2 */
12916 case 0x16: /* UMLSL, UMLSL2 */
12917 case 0x0a: /* SMULL, SMULL2 */
12918 case 0x1a: /* UMULL, UMULL2 */
12920 unallocated_encoding(s
);
12925 case 0x03: /* SQDMLAL, SQDMLAL2 */
12926 case 0x07: /* SQDMLSL, SQDMLSL2 */
12927 case 0x0b: /* SQDMULL, SQDMULL2 */
12930 case 0x0c: /* SQDMULH */
12931 case 0x0d: /* SQRDMULH */
12933 case 0x01: /* FMLA */
12934 case 0x05: /* FMLS */
12935 case 0x09: /* FMUL */
12936 case 0x19: /* FMULX */
12939 case 0x1d: /* SQRDMLAH */
12940 case 0x1f: /* SQRDMLSH */
12941 if (!dc_isar_feature(aa64_rdm
, s
)) {
12942 unallocated_encoding(s
);
12946 case 0x0e: /* SDOT */
12947 case 0x1e: /* UDOT */
12948 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12949 unallocated_encoding(s
);
12955 case 0: /* SUDOT */
12956 case 2: /* USDOT */
12957 if (is_scalar
|| !dc_isar_feature(aa64_i8mm
, s
)) {
12958 unallocated_encoding(s
);
12963 case 1: /* BFDOT */
12964 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
12965 unallocated_encoding(s
);
12970 case 3: /* BFMLAL{B,T} */
12971 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
12972 unallocated_encoding(s
);
12975 /* can't set is_fp without other incorrect size checks */
12979 unallocated_encoding(s
);
12983 case 0x11: /* FCMLA #0 */
12984 case 0x13: /* FCMLA #90 */
12985 case 0x15: /* FCMLA #180 */
12986 case 0x17: /* FCMLA #270 */
12987 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12988 unallocated_encoding(s
);
12993 case 0x00: /* FMLAL */
12994 case 0x04: /* FMLSL */
12995 case 0x18: /* FMLAL2 */
12996 case 0x1c: /* FMLSL2 */
12997 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12998 unallocated_encoding(s
);
13002 /* is_fp, but we pass cpu_env not fp_status. */
13005 unallocated_encoding(s
);
13010 case 1: /* normal fp */
13011 /* convert insn encoded size to MemOp size */
13013 case 0: /* half-precision */
13017 case MO_32
: /* single precision */
13018 case MO_64
: /* double precision */
13021 unallocated_encoding(s
);
13026 case 2: /* complex fp */
13027 /* Each indexable element is a complex pair. */
13032 unallocated_encoding(s
);
13040 unallocated_encoding(s
);
13045 default: /* integer */
13049 unallocated_encoding(s
);
13054 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13055 unallocated_encoding(s
);
13059 /* Given MemOp size, adjust register and indexing. */
13062 index
= h
<< 2 | l
<< 1 | m
;
13065 index
= h
<< 1 | l
;
13070 unallocated_encoding(s
);
13077 g_assert_not_reached();
13080 if (!fp_access_check(s
)) {
13085 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13090 switch (16 * u
+ opcode
) {
13091 case 0x0e: /* SDOT */
13092 case 0x1e: /* UDOT */
13093 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13094 u
? gen_helper_gvec_udot_idx_b
13095 : gen_helper_gvec_sdot_idx_b
);
13098 switch (extract32(insn
, 22, 2)) {
13099 case 0: /* SUDOT */
13100 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13101 gen_helper_gvec_sudot_idx_b
);
13103 case 1: /* BFDOT */
13104 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13105 gen_helper_gvec_bfdot_idx
);
13107 case 2: /* USDOT */
13108 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13109 gen_helper_gvec_usdot_idx_b
);
13111 case 3: /* BFMLAL{B,T} */
13112 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, 0, (index
<< 1) | is_q
,
13113 gen_helper_gvec_bfmlal_idx
);
13116 g_assert_not_reached();
13117 case 0x11: /* FCMLA #0 */
13118 case 0x13: /* FCMLA #90 */
13119 case 0x15: /* FCMLA #180 */
13120 case 0x17: /* FCMLA #270 */
13122 int rot
= extract32(insn
, 13, 2);
13123 int data
= (index
<< 2) | rot
;
13124 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
13125 vec_full_reg_offset(s
, rn
),
13126 vec_full_reg_offset(s
, rm
),
13127 vec_full_reg_offset(s
, rd
), fpst
,
13128 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13130 ? gen_helper_gvec_fcmlas_idx
13131 : gen_helper_gvec_fcmlah_idx
);
13135 case 0x00: /* FMLAL */
13136 case 0x04: /* FMLSL */
13137 case 0x18: /* FMLAL2 */
13138 case 0x1c: /* FMLSL2 */
13140 int is_s
= extract32(opcode
, 2, 1);
13142 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13143 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13144 vec_full_reg_offset(s
, rn
),
13145 vec_full_reg_offset(s
, rm
), cpu_env
,
13146 is_q
? 16 : 8, vec_full_reg_size(s
),
13147 data
, gen_helper_gvec_fmlal_idx_a64
);
13151 case 0x08: /* MUL */
13152 if (!is_long
&& !is_scalar
) {
13153 static gen_helper_gvec_3
* const fns
[3] = {
13154 gen_helper_gvec_mul_idx_h
,
13155 gen_helper_gvec_mul_idx_s
,
13156 gen_helper_gvec_mul_idx_d
,
13158 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13159 vec_full_reg_offset(s
, rn
),
13160 vec_full_reg_offset(s
, rm
),
13161 is_q
? 16 : 8, vec_full_reg_size(s
),
13162 index
, fns
[size
- 1]);
13167 case 0x10: /* MLA */
13168 if (!is_long
&& !is_scalar
) {
13169 static gen_helper_gvec_4
* const fns
[3] = {
13170 gen_helper_gvec_mla_idx_h
,
13171 gen_helper_gvec_mla_idx_s
,
13172 gen_helper_gvec_mla_idx_d
,
13174 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13175 vec_full_reg_offset(s
, rn
),
13176 vec_full_reg_offset(s
, rm
),
13177 vec_full_reg_offset(s
, rd
),
13178 is_q
? 16 : 8, vec_full_reg_size(s
),
13179 index
, fns
[size
- 1]);
13184 case 0x14: /* MLS */
13185 if (!is_long
&& !is_scalar
) {
13186 static gen_helper_gvec_4
* const fns
[3] = {
13187 gen_helper_gvec_mls_idx_h
,
13188 gen_helper_gvec_mls_idx_s
,
13189 gen_helper_gvec_mls_idx_d
,
13191 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13192 vec_full_reg_offset(s
, rn
),
13193 vec_full_reg_offset(s
, rm
),
13194 vec_full_reg_offset(s
, rd
),
13195 is_q
? 16 : 8, vec_full_reg_size(s
),
13196 index
, fns
[size
- 1]);
13203 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13206 assert(is_fp
&& is_q
&& !is_long
);
13208 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13210 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13211 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13212 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13214 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13216 switch (16 * u
+ opcode
) {
13217 case 0x05: /* FMLS */
13218 /* As usual for ARM, separate negation for fused multiply-add */
13219 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13221 case 0x01: /* FMLA */
13222 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13223 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13225 case 0x09: /* FMUL */
13226 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13228 case 0x19: /* FMULX */
13229 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13232 g_assert_not_reached();
13235 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13238 clear_vec_high(s
, !is_scalar
, rd
);
13239 } else if (!is_long
) {
13240 /* 32 bit floating point, or 16 or 32 bit integer.
13241 * For the 16 bit scalar case we use the usual Neon helpers and
13242 * rely on the fact that 0 op 0 == 0 with no side effects.
13244 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13245 int pass
, maxpasses
;
13250 maxpasses
= is_q
? 4 : 2;
13253 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13255 if (size
== 1 && !is_scalar
) {
13256 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13257 * the index into both halves of the 32 bit tcg_idx and then use
13258 * the usual Neon helpers.
13260 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13263 for (pass
= 0; pass
< maxpasses
; pass
++) {
13264 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13265 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13267 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13269 switch (16 * u
+ opcode
) {
13270 case 0x08: /* MUL */
13271 case 0x10: /* MLA */
13272 case 0x14: /* MLS */
13274 static NeonGenTwoOpFn
* const fns
[2][2] = {
13275 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13276 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13278 NeonGenTwoOpFn
*genfn
;
13279 bool is_sub
= opcode
== 0x4;
13282 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13284 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13286 if (opcode
== 0x8) {
13289 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13290 genfn
= fns
[size
- 1][is_sub
];
13291 genfn(tcg_res
, tcg_op
, tcg_res
);
13294 case 0x05: /* FMLS */
13295 case 0x01: /* FMLA */
13296 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13297 is_scalar
? size
: MO_32
);
13300 if (opcode
== 0x5) {
13301 /* As usual for ARM, separate negation for fused
13303 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13306 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13309 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13314 if (opcode
== 0x5) {
13315 /* As usual for ARM, separate negation for
13316 * fused multiply-add */
13317 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13319 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13323 g_assert_not_reached();
13326 case 0x09: /* FMUL */
13330 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13333 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13338 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13341 g_assert_not_reached();
13344 case 0x19: /* FMULX */
13348 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13351 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13356 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13359 g_assert_not_reached();
13362 case 0x0c: /* SQDMULH */
13364 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13367 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13371 case 0x0d: /* SQRDMULH */
13373 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13376 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13380 case 0x1d: /* SQRDMLAH */
13381 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13382 is_scalar
? size
: MO_32
);
13384 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13385 tcg_op
, tcg_idx
, tcg_res
);
13387 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13388 tcg_op
, tcg_idx
, tcg_res
);
13391 case 0x1f: /* SQRDMLSH */
13392 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13393 is_scalar
? size
: MO_32
);
13395 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13396 tcg_op
, tcg_idx
, tcg_res
);
13398 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13399 tcg_op
, tcg_idx
, tcg_res
);
13403 g_assert_not_reached();
13407 write_fp_sreg(s
, rd
, tcg_res
);
13409 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13413 clear_vec_high(s
, is_q
, rd
);
13415 /* long ops: 16x16->32 or 32x32->64 */
13416 TCGv_i64 tcg_res
[2];
13418 bool satop
= extract32(opcode
, 0, 1);
13419 MemOp memop
= MO_32
;
13426 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13428 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13430 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13431 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13432 TCGv_i64 tcg_passres
;
13438 passelt
= pass
+ (is_q
* 2);
13441 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13443 tcg_res
[pass
] = tcg_temp_new_i64();
13445 if (opcode
== 0xa || opcode
== 0xb) {
13446 /* Non-accumulating ops */
13447 tcg_passres
= tcg_res
[pass
];
13449 tcg_passres
= tcg_temp_new_i64();
13452 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13455 /* saturating, doubling */
13456 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13457 tcg_passres
, tcg_passres
);
13460 if (opcode
== 0xa || opcode
== 0xb) {
13464 /* Accumulating op: handle accumulate step */
13465 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13468 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13469 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13471 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13472 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13474 case 0x7: /* SQDMLSL, SQDMLSL2 */
13475 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13477 case 0x3: /* SQDMLAL, SQDMLAL2 */
13478 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13483 g_assert_not_reached();
13487 clear_vec_high(s
, !is_scalar
, rd
);
13489 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13492 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13495 /* The simplest way to handle the 16x16 indexed ops is to
13496 * duplicate the index into both halves of the 32 bit tcg_idx
13497 * and then use the usual Neon helpers.
13499 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13502 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13503 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13504 TCGv_i64 tcg_passres
;
13507 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13509 read_vec_element_i32(s
, tcg_op
, rn
,
13510 pass
+ (is_q
* 2), MO_32
);
13513 tcg_res
[pass
] = tcg_temp_new_i64();
13515 if (opcode
== 0xa || opcode
== 0xb) {
13516 /* Non-accumulating ops */
13517 tcg_passres
= tcg_res
[pass
];
13519 tcg_passres
= tcg_temp_new_i64();
13522 if (memop
& MO_SIGN
) {
13523 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13525 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13528 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13529 tcg_passres
, tcg_passres
);
13532 if (opcode
== 0xa || opcode
== 0xb) {
13536 /* Accumulating op: handle accumulate step */
13537 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13540 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13541 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13544 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13545 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13548 case 0x7: /* SQDMLSL, SQDMLSL2 */
13549 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13551 case 0x3: /* SQDMLAL, SQDMLAL2 */
13552 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13557 g_assert_not_reached();
13562 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13567 tcg_res
[1] = tcg_constant_i64(0);
13570 for (pass
= 0; pass
< 2; pass
++) {
13571 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13577 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13578 * +-----------------+------+-----------+--------+-----+------+------+
13579 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13580 * +-----------------+------+-----------+--------+-----+------+------+
13582 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13584 int size
= extract32(insn
, 22, 2);
13585 int opcode
= extract32(insn
, 12, 5);
13586 int rn
= extract32(insn
, 5, 5);
13587 int rd
= extract32(insn
, 0, 5);
13589 gen_helper_gvec_2
*genfn2
= NULL
;
13590 gen_helper_gvec_3
*genfn3
= NULL
;
13592 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13593 unallocated_encoding(s
);
13598 case 0x4: /* AESE */
13600 genfn3
= gen_helper_crypto_aese
;
13602 case 0x6: /* AESMC */
13604 genfn2
= gen_helper_crypto_aesmc
;
13606 case 0x5: /* AESD */
13608 genfn3
= gen_helper_crypto_aese
;
13610 case 0x7: /* AESIMC */
13612 genfn2
= gen_helper_crypto_aesmc
;
13615 unallocated_encoding(s
);
13619 if (!fp_access_check(s
)) {
13623 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13625 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13629 /* Crypto three-reg SHA
13630 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13631 * +-----------------+------+---+------+---+--------+-----+------+------+
13632 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13633 * +-----------------+------+---+------+---+--------+-----+------+------+
13635 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13637 int size
= extract32(insn
, 22, 2);
13638 int opcode
= extract32(insn
, 12, 3);
13639 int rm
= extract32(insn
, 16, 5);
13640 int rn
= extract32(insn
, 5, 5);
13641 int rd
= extract32(insn
, 0, 5);
13642 gen_helper_gvec_3
*genfn
;
13646 unallocated_encoding(s
);
13651 case 0: /* SHA1C */
13652 genfn
= gen_helper_crypto_sha1c
;
13653 feature
= dc_isar_feature(aa64_sha1
, s
);
13655 case 1: /* SHA1P */
13656 genfn
= gen_helper_crypto_sha1p
;
13657 feature
= dc_isar_feature(aa64_sha1
, s
);
13659 case 2: /* SHA1M */
13660 genfn
= gen_helper_crypto_sha1m
;
13661 feature
= dc_isar_feature(aa64_sha1
, s
);
13663 case 3: /* SHA1SU0 */
13664 genfn
= gen_helper_crypto_sha1su0
;
13665 feature
= dc_isar_feature(aa64_sha1
, s
);
13667 case 4: /* SHA256H */
13668 genfn
= gen_helper_crypto_sha256h
;
13669 feature
= dc_isar_feature(aa64_sha256
, s
);
13671 case 5: /* SHA256H2 */
13672 genfn
= gen_helper_crypto_sha256h2
;
13673 feature
= dc_isar_feature(aa64_sha256
, s
);
13675 case 6: /* SHA256SU1 */
13676 genfn
= gen_helper_crypto_sha256su1
;
13677 feature
= dc_isar_feature(aa64_sha256
, s
);
13680 unallocated_encoding(s
);
13685 unallocated_encoding(s
);
13689 if (!fp_access_check(s
)) {
13692 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
13695 /* Crypto two-reg SHA
13696 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13697 * +-----------------+------+-----------+--------+-----+------+------+
13698 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13699 * +-----------------+------+-----------+--------+-----+------+------+
13701 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13703 int size
= extract32(insn
, 22, 2);
13704 int opcode
= extract32(insn
, 12, 5);
13705 int rn
= extract32(insn
, 5, 5);
13706 int rd
= extract32(insn
, 0, 5);
13707 gen_helper_gvec_2
*genfn
;
13711 unallocated_encoding(s
);
13716 case 0: /* SHA1H */
13717 feature
= dc_isar_feature(aa64_sha1
, s
);
13718 genfn
= gen_helper_crypto_sha1h
;
13720 case 1: /* SHA1SU1 */
13721 feature
= dc_isar_feature(aa64_sha1
, s
);
13722 genfn
= gen_helper_crypto_sha1su1
;
13724 case 2: /* SHA256SU0 */
13725 feature
= dc_isar_feature(aa64_sha256
, s
);
13726 genfn
= gen_helper_crypto_sha256su0
;
13729 unallocated_encoding(s
);
13734 unallocated_encoding(s
);
13738 if (!fp_access_check(s
)) {
13741 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
13744 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
13746 tcg_gen_rotli_i64(d
, m
, 1);
13747 tcg_gen_xor_i64(d
, d
, n
);
13750 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
13752 tcg_gen_rotli_vec(vece
, d
, m
, 1);
13753 tcg_gen_xor_vec(vece
, d
, d
, n
);
13756 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
13757 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
13759 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
13760 static const GVecGen3 op
= {
13761 .fni8
= gen_rax1_i64
,
13762 .fniv
= gen_rax1_vec
,
13763 .opt_opc
= vecop_list
,
13764 .fno
= gen_helper_crypto_rax1
,
13767 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
13770 /* Crypto three-reg SHA512
13771 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13772 * +-----------------------+------+---+---+-----+--------+------+------+
13773 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13774 * +-----------------------+------+---+---+-----+--------+------+------+
13776 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13778 int opcode
= extract32(insn
, 10, 2);
13779 int o
= extract32(insn
, 14, 1);
13780 int rm
= extract32(insn
, 16, 5);
13781 int rn
= extract32(insn
, 5, 5);
13782 int rd
= extract32(insn
, 0, 5);
13784 gen_helper_gvec_3
*oolfn
= NULL
;
13785 GVecGen3Fn
*gvecfn
= NULL
;
13789 case 0: /* SHA512H */
13790 feature
= dc_isar_feature(aa64_sha512
, s
);
13791 oolfn
= gen_helper_crypto_sha512h
;
13793 case 1: /* SHA512H2 */
13794 feature
= dc_isar_feature(aa64_sha512
, s
);
13795 oolfn
= gen_helper_crypto_sha512h2
;
13797 case 2: /* SHA512SU1 */
13798 feature
= dc_isar_feature(aa64_sha512
, s
);
13799 oolfn
= gen_helper_crypto_sha512su1
;
13802 feature
= dc_isar_feature(aa64_sha3
, s
);
13803 gvecfn
= gen_gvec_rax1
;
13806 g_assert_not_reached();
13810 case 0: /* SM3PARTW1 */
13811 feature
= dc_isar_feature(aa64_sm3
, s
);
13812 oolfn
= gen_helper_crypto_sm3partw1
;
13814 case 1: /* SM3PARTW2 */
13815 feature
= dc_isar_feature(aa64_sm3
, s
);
13816 oolfn
= gen_helper_crypto_sm3partw2
;
13818 case 2: /* SM4EKEY */
13819 feature
= dc_isar_feature(aa64_sm4
, s
);
13820 oolfn
= gen_helper_crypto_sm4ekey
;
13823 unallocated_encoding(s
);
13829 unallocated_encoding(s
);
13833 if (!fp_access_check(s
)) {
13838 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
13840 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
13844 /* Crypto two-reg SHA512
13845 * 31 12 11 10 9 5 4 0
13846 * +-----------------------------------------+--------+------+------+
13847 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13848 * +-----------------------------------------+--------+------+------+
13850 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13852 int opcode
= extract32(insn
, 10, 2);
13853 int rn
= extract32(insn
, 5, 5);
13854 int rd
= extract32(insn
, 0, 5);
13858 case 0: /* SHA512SU0 */
13859 feature
= dc_isar_feature(aa64_sha512
, s
);
13862 feature
= dc_isar_feature(aa64_sm4
, s
);
13865 unallocated_encoding(s
);
13870 unallocated_encoding(s
);
13874 if (!fp_access_check(s
)) {
13879 case 0: /* SHA512SU0 */
13880 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
13883 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
13886 g_assert_not_reached();
13890 /* Crypto four-register
13891 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13892 * +-------------------+-----+------+---+------+------+------+
13893 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13894 * +-------------------+-----+------+---+------+------+------+
13896 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13898 int op0
= extract32(insn
, 21, 2);
13899 int rm
= extract32(insn
, 16, 5);
13900 int ra
= extract32(insn
, 10, 5);
13901 int rn
= extract32(insn
, 5, 5);
13902 int rd
= extract32(insn
, 0, 5);
13908 feature
= dc_isar_feature(aa64_sha3
, s
);
13910 case 2: /* SM3SS1 */
13911 feature
= dc_isar_feature(aa64_sm3
, s
);
13914 unallocated_encoding(s
);
13919 unallocated_encoding(s
);
13923 if (!fp_access_check(s
)) {
13928 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13931 tcg_op1
= tcg_temp_new_i64();
13932 tcg_op2
= tcg_temp_new_i64();
13933 tcg_op3
= tcg_temp_new_i64();
13934 tcg_res
[0] = tcg_temp_new_i64();
13935 tcg_res
[1] = tcg_temp_new_i64();
13937 for (pass
= 0; pass
< 2; pass
++) {
13938 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13939 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13940 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13944 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13947 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13949 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13951 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13952 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13954 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13956 tcg_op1
= tcg_temp_new_i32();
13957 tcg_op2
= tcg_temp_new_i32();
13958 tcg_op3
= tcg_temp_new_i32();
13959 tcg_res
= tcg_temp_new_i32();
13960 tcg_zero
= tcg_constant_i32(0);
13962 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13963 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13964 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13966 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13967 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13968 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13969 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13971 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13972 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13973 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13974 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13979 * 31 21 20 16 15 10 9 5 4 0
13980 * +-----------------------+------+--------+------+------+
13981 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13982 * +-----------------------+------+--------+------+------+
13984 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13986 int rm
= extract32(insn
, 16, 5);
13987 int imm6
= extract32(insn
, 10, 6);
13988 int rn
= extract32(insn
, 5, 5);
13989 int rd
= extract32(insn
, 0, 5);
13991 if (!dc_isar_feature(aa64_sha3
, s
)) {
13992 unallocated_encoding(s
);
13996 if (!fp_access_check(s
)) {
14000 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
14001 vec_full_reg_offset(s
, rn
),
14002 vec_full_reg_offset(s
, rm
), imm6
, 16,
14003 vec_full_reg_size(s
));
14006 /* Crypto three-reg imm2
14007 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14008 * +-----------------------+------+-----+------+--------+------+------+
14009 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14010 * +-----------------------+------+-----+------+--------+------+------+
14012 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14014 static gen_helper_gvec_3
* const fns
[4] = {
14015 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14016 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14018 int opcode
= extract32(insn
, 10, 2);
14019 int imm2
= extract32(insn
, 12, 2);
14020 int rm
= extract32(insn
, 16, 5);
14021 int rn
= extract32(insn
, 5, 5);
14022 int rd
= extract32(insn
, 0, 5);
14024 if (!dc_isar_feature(aa64_sm3
, s
)) {
14025 unallocated_encoding(s
);
14029 if (!fp_access_check(s
)) {
14033 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14036 /* C3.6 Data processing - SIMD, inc Crypto
14038 * As the decode gets a little complex we are using a table based
14039 * approach for this part of the decode.
14041 static const AArch64DecodeTable data_proc_simd
[] = {
14042 /* pattern , mask , fn */
14043 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14044 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14045 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14046 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14047 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14048 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14049 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14050 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14051 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14052 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14053 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14054 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14055 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14056 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14057 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14058 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14059 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14060 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14061 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14062 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14063 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14064 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14065 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14066 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14067 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14068 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14069 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14070 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14071 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14072 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14073 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14074 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14075 { 0x00000000, 0x00000000, NULL
}
14078 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14080 /* Note that this is called with all non-FP cases from
14081 * table C3-6 so it must UNDEF for entries not specifically
14082 * allocated to instructions in that table.
14084 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14088 unallocated_encoding(s
);
14092 /* C3.6 Data processing - SIMD and floating point */
14093 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14095 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14096 disas_data_proc_fp(s
, insn
);
14098 /* SIMD, including crypto */
14099 disas_data_proc_simd(s
, insn
);
14104 * Include the generated SME FA64 decoder.
14107 #include "decode-sme-fa64.c.inc"
14109 static bool trans_OK(DisasContext
*s
, arg_OK
*a
)
14114 static bool trans_FAIL(DisasContext
*s
, arg_OK
*a
)
14116 s
->is_nonstreaming
= true;
14122 * @env: The cpu environment
14123 * @s: The DisasContext
14125 * Return true if the page is guarded.
14127 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14129 uint64_t addr
= s
->base
.pc_first
;
14130 #ifdef CONFIG_USER_ONLY
14131 return page_get_flags(addr
) & PAGE_BTI
;
14133 CPUTLBEntryFull
*full
;
14135 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14139 * We test this immediately after reading an insn, which means
14140 * that the TLB entry must be present and valid, and thus this
14141 * access will never raise an exception.
14143 flags
= probe_access_full(env
, addr
, 0, MMU_INST_FETCH
, mmu_idx
,
14144 false, &host
, &full
, 0);
14145 assert(!(flags
& TLB_INVALID_MASK
));
14147 return full
->guarded
;
14152 * btype_destination_ok:
14153 * @insn: The instruction at the branch destination
14154 * @bt: SCTLR_ELx.BT
14155 * @btype: PSTATE.BTYPE, and is non-zero
14157 * On a guarded page, there are a limited number of insns
14158 * that may be present at the branch target:
14159 * - branch target identifiers,
14160 * - paciasp, pacibsp,
14163 * Anything else causes a Branch Target Exception.
14165 * Return true if the branch is compatible, false to raise BTITRAP.
14167 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14169 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14171 switch (extract32(insn
, 5, 7)) {
14172 case 0b011001: /* PACIASP */
14173 case 0b011011: /* PACIBSP */
14175 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14176 * with btype == 3. Otherwise all btype are ok.
14178 return !bt
|| btype
!= 3;
14179 case 0b100000: /* BTI */
14180 /* Not compatible with any btype. */
14182 case 0b100010: /* BTI c */
14183 /* Not compatible with btype == 3 */
14185 case 0b100100: /* BTI j */
14186 /* Not compatible with btype == 2 */
14188 case 0b100110: /* BTI jc */
14189 /* Compatible with any btype. */
14193 switch (insn
& 0xffe0001fu
) {
14194 case 0xd4200000u
: /* BRK */
14195 case 0xd4400000u
: /* HLT */
14196 /* Give priority to the breakpoint exception. */
14203 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14206 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14207 CPUARMState
*env
= cpu
->env_ptr
;
14208 ARMCPU
*arm_cpu
= env_archcpu(env
);
14209 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14210 int bound
, core_mmu_idx
;
14212 dc
->isar
= &arm_cpu
->isar
;
14214 dc
->pc_save
= dc
->base
.pc_first
;
14215 dc
->aarch64
= true;
14218 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14219 dc
->condexec_mask
= 0;
14220 dc
->condexec_cond
= 0;
14221 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14222 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14223 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14224 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14225 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14226 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14227 #if !defined(CONFIG_USER_ONLY)
14228 dc
->user
= (dc
->current_el
== 0);
14230 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14231 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14232 dc
->pstate_il
= EX_TBFLAG_ANY(tb_flags
, PSTATE__IL
);
14233 dc
->fgt_active
= EX_TBFLAG_ANY(tb_flags
, FGT_ACTIVE
);
14234 dc
->fgt_svc
= EX_TBFLAG_ANY(tb_flags
, FGT_SVC
);
14235 dc
->fgt_eret
= EX_TBFLAG_A64(tb_flags
, FGT_ERET
);
14236 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14237 dc
->sme_excp_el
= EX_TBFLAG_A64(tb_flags
, SMEEXC_EL
);
14238 dc
->vl
= (EX_TBFLAG_A64(tb_flags
, VL
) + 1) * 16;
14239 dc
->svl
= (EX_TBFLAG_A64(tb_flags
, SVL
) + 1) * 16;
14240 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14241 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14242 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14243 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14244 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14245 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14246 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14247 dc
->pstate_sm
= EX_TBFLAG_A64(tb_flags
, PSTATE_SM
);
14248 dc
->pstate_za
= EX_TBFLAG_A64(tb_flags
, PSTATE_ZA
);
14249 dc
->sme_trap_nonstreaming
= EX_TBFLAG_A64(tb_flags
, SME_TRAP_NONSTREAMING
);
14251 dc
->vec_stride
= 0;
14252 dc
->cp_regs
= arm_cpu
->cp_regs
;
14253 dc
->features
= env
->features
;
14254 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14256 #ifdef CONFIG_USER_ONLY
14257 /* In sve_probe_page, we assume TBI is enabled. */
14258 tcg_debug_assert(dc
->tbid
& 1);
14261 /* Single step state. The code-generation logic here is:
14263 * generate code with no special handling for single-stepping (except
14264 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14265 * this happens anyway because those changes are all system register or
14267 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14268 * emit code for one insn
14269 * emit code to clear PSTATE.SS
14270 * emit code to generate software step exception for completed step
14271 * end TB (as usual for having generated an exception)
14272 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14273 * emit code to generate a software step exception
14276 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14277 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14278 dc
->is_ldex
= false;
14280 /* Bound the number of insns to execute to those left on the page. */
14281 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14283 /* If architectural single step active, limit to 1. */
14284 if (dc
->ss_active
) {
14287 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14290 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14294 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14296 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14297 target_ulong pc_arg
= dc
->base
.pc_next
;
14299 if (tb_cflags(dcbase
->tb
) & CF_PCREL
) {
14300 pc_arg
&= ~TARGET_PAGE_MASK
;
14302 tcg_gen_insn_start(pc_arg
, 0, 0);
14303 dc
->insn_start
= tcg_last_op();
14306 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14308 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
14309 CPUARMState
*env
= cpu
->env_ptr
;
14310 uint64_t pc
= s
->base
.pc_next
;
14313 /* Singlestep exceptions have the highest priority. */
14314 if (s
->ss_active
&& !s
->pstate_ss
) {
14315 /* Singlestep state is Active-pending.
14316 * If we're in this state at the start of a TB then either
14317 * a) we just took an exception to an EL which is being debugged
14318 * and this is the first insn in the exception handler
14319 * b) debug exceptions were masked and we just unmasked them
14320 * without changing EL (eg by clearing PSTATE.D)
14321 * In either case we're going to take a swstep exception in the
14322 * "did not step an insn" case, and so the syndrome ISV and EX
14323 * bits should be zero.
14325 assert(s
->base
.num_insns
== 1);
14326 gen_swstep_exception(s
, 0, 0);
14327 s
->base
.is_jmp
= DISAS_NORETURN
;
14328 s
->base
.pc_next
= pc
+ 4;
14334 * PC alignment fault. This has priority over the instruction abort
14335 * that we would receive from a translation fault via arm_ldl_code.
14336 * This should only be possible after an indirect branch, at the
14339 assert(s
->base
.num_insns
== 1);
14340 gen_helper_exception_pc_alignment(cpu_env
, tcg_constant_tl(pc
));
14341 s
->base
.is_jmp
= DISAS_NORETURN
;
14342 s
->base
.pc_next
= QEMU_ALIGN_UP(pc
, 4);
14347 insn
= arm_ldl_code(env
, &s
->base
, pc
, s
->sctlr_b
);
14349 s
->base
.pc_next
= pc
+ 4;
14351 s
->fp_access_checked
= false;
14352 s
->sve_access_checked
= false;
14354 if (s
->pstate_il
) {
14356 * Illegal execution state. This has priority over BTI
14357 * exceptions, but comes after instruction abort exceptions.
14359 gen_exception_insn(s
, 0, EXCP_UDEF
, syn_illegalstate());
14363 if (dc_isar_feature(aa64_bti
, s
)) {
14364 if (s
->base
.num_insns
== 1) {
14366 * At the first insn of the TB, compute s->guarded_page.
14367 * We delayed computing this until successfully reading
14368 * the first insn of the TB, above. This (mostly) ensures
14369 * that the softmmu tlb entry has been populated, and the
14370 * page table GP bit is available.
14372 * Note that we need to compute this even if btype == 0,
14373 * because this value is used for BR instructions later
14374 * where ENV is not available.
14376 s
->guarded_page
= is_guarded_page(env
, s
);
14378 /* First insn can have btype set to non-zero. */
14379 tcg_debug_assert(s
->btype
>= 0);
14382 * Note that the Branch Target Exception has fairly high
14383 * priority -- below debugging exceptions but above most
14384 * everything else. This allows us to handle this now
14385 * instead of waiting until the insn is otherwise decoded.
14389 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14390 gen_exception_insn(s
, 0, EXCP_UDEF
, syn_btitrap(s
->btype
));
14394 /* Not the first insn: btype must be 0. */
14395 tcg_debug_assert(s
->btype
== 0);
14399 s
->is_nonstreaming
= false;
14400 if (s
->sme_trap_nonstreaming
) {
14401 disas_sme_fa64(s
, insn
);
14404 switch (extract32(insn
, 25, 4)) {
14406 if (!extract32(insn
, 31, 1) || !disas_sme(s
, insn
)) {
14407 unallocated_encoding(s
);
14410 case 0x1: case 0x3: /* UNALLOCATED */
14411 unallocated_encoding(s
);
14414 if (!disas_sve(s
, insn
)) {
14415 unallocated_encoding(s
);
14418 case 0x8: case 0x9: /* Data processing - immediate */
14419 disas_data_proc_imm(s
, insn
);
14421 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14422 disas_b_exc_sys(s
, insn
);
14427 case 0xe: /* Loads and stores */
14428 disas_ldst(s
, insn
);
14431 case 0xd: /* Data processing - register */
14432 disas_data_proc_reg(s
, insn
);
14435 case 0xf: /* Data processing - SIMD and floating point */
14436 disas_data_proc_simd_fp(s
, insn
);
14439 assert(FALSE
); /* all 15 cases should be handled above */
14444 * After execution of most insns, btype is reset to 0.
14445 * Note that we set btype == -1 when the insn sets btype.
14447 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14452 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14454 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14456 if (unlikely(dc
->ss_active
)) {
14457 /* Note that this means single stepping WFI doesn't halt the CPU.
14458 * For conditional branch insns this is harmless unreachable code as
14459 * gen_goto_tb() has already handled emitting the debug exception
14460 * (and thus a tb-jump is not possible when singlestepping).
14462 switch (dc
->base
.is_jmp
) {
14464 gen_a64_update_pc(dc
, 4);
14468 gen_step_complete_exception(dc
);
14470 case DISAS_NORETURN
:
14474 switch (dc
->base
.is_jmp
) {
14476 case DISAS_TOO_MANY
:
14477 gen_goto_tb(dc
, 1, 4);
14480 case DISAS_UPDATE_EXIT
:
14481 gen_a64_update_pc(dc
, 4);
14484 tcg_gen_exit_tb(NULL
, 0);
14486 case DISAS_UPDATE_NOCHAIN
:
14487 gen_a64_update_pc(dc
, 4);
14490 tcg_gen_lookup_and_goto_ptr();
14492 case DISAS_NORETURN
:
14496 gen_a64_update_pc(dc
, 4);
14497 gen_helper_wfe(cpu_env
);
14500 gen_a64_update_pc(dc
, 4);
14501 gen_helper_yield(cpu_env
);
14505 * This is a special case because we don't want to just halt
14506 * the CPU if trying to debug across a WFI.
14508 gen_a64_update_pc(dc
, 4);
14509 gen_helper_wfi(cpu_env
, tcg_constant_i32(4));
14511 * The helper doesn't necessarily throw an exception, but we
14512 * must go back to the main loop to check for interrupts anyway.
14514 tcg_gen_exit_tb(NULL
, 0);
14520 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14521 CPUState
*cpu
, FILE *logfile
)
14523 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14525 fprintf(logfile
, "IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14526 target_disas(logfile
, cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14529 const TranslatorOps aarch64_translator_ops
= {
14530 .init_disas_context
= aarch64_tr_init_disas_context
,
14531 .tb_start
= aarch64_tr_tb_start
,
14532 .insn_start
= aarch64_tr_insn_start
,
14533 .translate_insn
= aarch64_tr_translate_insn
,
14534 .tb_stop
= aarch64_tr_tb_stop
,
14535 .disas_log
= aarch64_tr_disas_log
,