target/arm/translate-a32.h

   1 /*
   2  *  AArch32 translation, common definitions.
   3  *
   4  * Copyright (c) 2021 Linaro, Ltd.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TARGET_ARM_TRANSLATE_A64_H
  21 #define TARGET_ARM_TRANSLATE_A64_H
  22
  23 /* Prototypes for autogenerated disassembler functions */
  24 bool disas_m_nocp(DisasContext *dc, uint32_t insn);
  25 bool disas_vfp(DisasContext *s, uint32_t insn);
  26 bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
  27 bool disas_neon_dp(DisasContext *s, uint32_t insn);
  28 bool disas_neon_ls(DisasContext *s, uint32_t insn);
  29 bool disas_neon_shared(DisasContext *s, uint32_t insn);
  30
  31 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
  32 void arm_gen_condlabel(DisasContext *s);
  33 bool vfp_access_check(DisasContext *s);
  34 void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
  35 void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
  36 void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
  37 void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
  38 TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
  39 void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
  40 void gen_set_condexec(DisasContext *s);
  41 void gen_set_pc_im(DisasContext *s, target_ulong val);
  42 void gen_lookup_tb(DisasContext *s);
  43 long vfp_reg_offset(bool dp, unsigned reg);
  44 long neon_full_reg_offset(unsigned reg);
  45 long neon_element_offset(int reg, int element, MemOp memop);
  46 void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
  47
  48 static inline TCGv_i32 load_cpu_offset(int offset)
  49 {
  50     TCGv_i32 tmp = tcg_temp_new_i32();
  51     tcg_gen_ld_i32(tmp, cpu_env, offset);
  52     return tmp;
  53 }
  54
  55 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
  56
  57 static inline void store_cpu_offset(TCGv_i32 var, int offset)
  58 {
  59     tcg_gen_st_i32(var, cpu_env, offset);
  60     tcg_temp_free_i32(var);
  61 }
  62
  63 #define store_cpu_field(var, name) \
  64     store_cpu_offset(var, offsetof(CPUARMState, name))
  65
  66 /* Create a new temporary and set it to the value of a CPU register.  */
  67 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
  68 {
  69     TCGv_i32 tmp = tcg_temp_new_i32();
  70     load_reg_var(s, tmp, reg);
  71     return tmp;
  72 }
  73
  74 void store_reg(DisasContext *s, int reg, TCGv_i32 var);
  75
  76 void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
  77                               TCGv_i32 a32, int index, MemOp opc);
  78 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
  79                               TCGv_i32 a32, int index, MemOp opc);
  80 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
  81                               TCGv_i32 a32, int index, MemOp opc);
  82 void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
  83                               TCGv_i32 a32, int index, MemOp opc);
  84 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  85                      int index, MemOp opc);
  86 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  87                      int index, MemOp opc);
  88 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
  89                      int index, MemOp opc);
  90 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
  91                      int index, MemOp opc);
  92
  93 #define DO_GEN_LD(SUFF, OPC)                                            \
  94     static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
  95                                          TCGv_i32 a32, int index)       \
  96     {                                                                   \
  97         gen_aa32_ld_i32(s, val, a32, index, OPC);                       \
  98     }
  99
 100 #define DO_GEN_ST(SUFF, OPC)                                            \
 101     static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
 102                                          TCGv_i32 a32, int index)       \
 103     {                                                                   \
 104         gen_aa32_st_i32(s, val, a32, index, OPC);                       \
 105     }
 106
 107 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
 108                                  TCGv_i32 a32, int index)
 109 {
 110     gen_aa32_ld_i64(s, val, a32, index, MO_Q);
 111 }
 112
 113 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
 114                                  TCGv_i32 a32, int index)
 115 {
 116     gen_aa32_st_i64(s, val, a32, index, MO_Q);
 117 }
 118
 119 DO_GEN_LD(8u, MO_UB)
 120 DO_GEN_LD(16u, MO_UW)
 121 DO_GEN_LD(32u, MO_UL)
 122 DO_GEN_ST(8, MO_UB)
 123 DO_GEN_ST(16, MO_UW)
 124 DO_GEN_ST(32, MO_UL)
 125
 126 #undef DO_GEN_LD
 127 #undef DO_GEN_ST
 128
 129 #if defined(CONFIG_USER_ONLY)
 130 #define IS_USER(s) 1
 131 #else
 132 #define IS_USER(s) (s->user)
 133 #endif
 134
 135 /* Set NZCV flags from the high 4 bits of var.  */
 136 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
 137
 138 /* Swap low and high halfwords.  */
 139 static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
 140 {
 141     tcg_gen_rotri_i32(dest, var, 16);
 142 }
 143
 144 #endif