target/arm/translate-a32.h

   1 /*
   2  *  AArch32 translation, common definitions.
   3  *
   4  * Copyright (c) 2021 Linaro, Ltd.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TARGET_ARM_TRANSLATE_A64_H
  21 #define TARGET_ARM_TRANSLATE_A64_H
  22
  23 /* Prototypes for autogenerated disassembler functions */
  24 bool disas_m_nocp(DisasContext *dc, uint32_t insn);
  25 bool disas_mve(DisasContext *dc, uint32_t insn);
  26 bool disas_vfp(DisasContext *s, uint32_t insn);
  27 bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
  28 bool disas_neon_dp(DisasContext *s, uint32_t insn);
  29 bool disas_neon_ls(DisasContext *s, uint32_t insn);
  30 bool disas_neon_shared(DisasContext *s, uint32_t insn);
  31
  32 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
  33 void arm_gen_condlabel(DisasContext *s);
  34 bool vfp_access_check(DisasContext *s);
  35 bool vfp_access_check_m(DisasContext *s, bool skip_context_update);
  36 void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
  37 void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
  38 void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
  39 void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
  40 TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
  41 void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
  42 void gen_set_condexec(DisasContext *s);
  43 void gen_set_pc_im(DisasContext *s, target_ulong val);
  44 void gen_lookup_tb(DisasContext *s);
  45 long vfp_reg_offset(bool dp, unsigned reg);
  46 long neon_full_reg_offset(unsigned reg);
  47 long neon_element_offset(int reg, int element, MemOp memop);
  48 void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
  49 void clear_eci_state(DisasContext *s);
  50 bool mve_eci_check(DisasContext *s);
  51 void mve_update_eci(DisasContext *s);
  52 void mve_update_and_store_eci(DisasContext *s);
  53 bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
  54
  55 static inline TCGv_i32 load_cpu_offset(int offset)
  56 {
  57     TCGv_i32 tmp = tcg_temp_new_i32();
  58     tcg_gen_ld_i32(tmp, cpu_env, offset);
  59     return tmp;
  60 }
  61
  62 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
  63
  64 static inline void store_cpu_offset(TCGv_i32 var, int offset)
  65 {
  66     tcg_gen_st_i32(var, cpu_env, offset);
  67     tcg_temp_free_i32(var);
  68 }
  69
  70 #define store_cpu_field(var, name) \
  71     store_cpu_offset(var, offsetof(CPUARMState, name))
  72
  73 #define store_cpu_field_constant(val, name) \
  74     tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, offsetof(CPUARMState, name))
  75
  76 /* Create a new temporary and set it to the value of a CPU register.  */
  77 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
  78 {
  79     TCGv_i32 tmp = tcg_temp_new_i32();
  80     load_reg_var(s, tmp, reg);
  81     return tmp;
  82 }
  83
  84 void store_reg(DisasContext *s, int reg, TCGv_i32 var);
  85
  86 void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
  87                               TCGv_i32 a32, int index, MemOp opc);
  88 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
  89                               TCGv_i32 a32, int index, MemOp opc);
  90 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
  91                               TCGv_i32 a32, int index, MemOp opc);
  92 void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
  93                               TCGv_i32 a32, int index, MemOp opc);
  94 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  95                      int index, MemOp opc);
  96 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  97                      int index, MemOp opc);
  98 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
  99                      int index, MemOp opc);
 100 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
 101                      int index, MemOp opc);
 102
 103 #define DO_GEN_LD(SUFF, OPC)                                            \
 104     static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
 105                                          TCGv_i32 a32, int index)       \
 106     {                                                                   \
 107         gen_aa32_ld_i32(s, val, a32, index, OPC);                       \
 108     }
 109
 110 #define DO_GEN_ST(SUFF, OPC)                                            \
 111     static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
 112                                          TCGv_i32 a32, int index)       \
 113     {                                                                   \
 114         gen_aa32_st_i32(s, val, a32, index, OPC);                       \
 115     }
 116
 117 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
 118                                  TCGv_i32 a32, int index)
 119 {
 120     gen_aa32_ld_i64(s, val, a32, index, MO_Q);
 121 }
 122
 123 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
 124                                  TCGv_i32 a32, int index)
 125 {
 126     gen_aa32_st_i64(s, val, a32, index, MO_Q);
 127 }
 128
 129 DO_GEN_LD(8u, MO_UB)
 130 DO_GEN_LD(16u, MO_UW)
 131 DO_GEN_LD(32u, MO_UL)
 132 DO_GEN_ST(8, MO_UB)
 133 DO_GEN_ST(16, MO_UW)
 134 DO_GEN_ST(32, MO_UL)
 135
 136 #undef DO_GEN_LD
 137 #undef DO_GEN_ST
 138
 139 #if defined(CONFIG_USER_ONLY)
 140 #define IS_USER(s) 1
 141 #else
 142 #define IS_USER(s) (s->user)
 143 #endif
 144
 145 /* Set NZCV flags from the high 4 bits of var.  */
 146 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
 147
 148 /* Swap low and high halfwords.  */
 149 static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
 150 {
 151     tcg_gen_rotri_i32(dest, var, 16);
 152 }
 153
 154 #endif