4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Return a "clean" address for ADDR according to TBID.
208 * This is always a fresh temporary, as we need to be able to
209 * increment this independently of a dirty write-back address.
211 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
213 TCGv_i64 clean
= new_tmp_a64(s
);
215 * In order to get the correct value in the FAR_ELx register,
216 * we must present the memory subsystem with the "dirty" address
217 * including the TBI. In system mode we can make this work via
218 * the TLB, dropping the TBI during translation. But for user-only
219 * mode we don't have that option, and must remove the top byte now.
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 /* Insert a zero tag into src, with the result at dst. */
230 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
232 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
235 typedef struct DisasCompare64
{
240 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
244 arm_test_cc(&c32
, cc
);
246 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
247 * properly. The NE/EQ comparisons are also fine with this choice. */
248 c64
->cond
= c32
.cond
;
249 c64
->value
= tcg_temp_new_i64();
250 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
255 static void a64_free_cc(DisasCompare64
*c64
)
257 tcg_temp_free_i64(c64
->value
);
260 static void gen_exception_internal(int excp
)
262 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
264 assert(excp_is_internal(excp
));
265 gen_helper_exception_internal(cpu_env
, tcg_excp
);
266 tcg_temp_free_i32(tcg_excp
);
269 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
271 gen_a64_set_pc_im(pc
);
272 gen_exception_internal(excp
);
273 s
->base
.is_jmp
= DISAS_NORETURN
;
276 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
277 uint32_t syndrome
, uint32_t target_el
)
279 gen_a64_set_pc_im(pc
);
280 gen_exception(excp
, syndrome
, target_el
);
281 s
->base
.is_jmp
= DISAS_NORETURN
;
284 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
288 gen_a64_set_pc_im(s
->pc_curr
);
289 tcg_syn
= tcg_const_i32(syndrome
);
290 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
291 tcg_temp_free_i32(tcg_syn
);
292 s
->base
.is_jmp
= DISAS_NORETURN
;
295 static void gen_step_complete_exception(DisasContext
*s
)
297 /* We just completed step of an insn. Move from Active-not-pending
298 * to Active-pending, and then also take the swstep exception.
299 * This corresponds to making the (IMPDEF) choice to prioritize
300 * swstep exceptions over asynchronous exceptions taken to an exception
301 * level where debug is disabled. This choice has the advantage that
302 * we do not need to maintain internal state corresponding to the
303 * ISV/EX syndrome bits between completion of the step and generation
304 * of the exception, and our syndrome information is always correct.
307 gen_swstep_exception(s
, 1, s
->is_ldex
);
308 s
->base
.is_jmp
= DISAS_NORETURN
;
311 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
313 /* No direct tb linking with singlestep (either QEMU's or the ARM
314 * debug architecture kind) or deterministic io
316 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
317 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
321 #ifndef CONFIG_USER_ONLY
322 /* Only link tbs from inside the same guest page */
323 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
331 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
333 TranslationBlock
*tb
;
336 if (use_goto_tb(s
, n
, dest
)) {
338 gen_a64_set_pc_im(dest
);
339 tcg_gen_exit_tb(tb
, n
);
340 s
->base
.is_jmp
= DISAS_NORETURN
;
342 gen_a64_set_pc_im(dest
);
344 gen_step_complete_exception(s
);
345 } else if (s
->base
.singlestep_enabled
) {
346 gen_exception_internal(EXCP_DEBUG
);
348 tcg_gen_lookup_and_goto_ptr();
349 s
->base
.is_jmp
= DISAS_NORETURN
;
354 void unallocated_encoding(DisasContext
*s
)
356 /* Unallocated and reserved encodings are uncategorized */
357 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
358 default_exception_el(s
));
361 static void init_tmp_a64_array(DisasContext
*s
)
363 #ifdef CONFIG_DEBUG_TCG
364 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
366 s
->tmp_a64_count
= 0;
369 static void free_tmp_a64(DisasContext
*s
)
372 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
373 tcg_temp_free_i64(s
->tmp_a64
[i
]);
375 init_tmp_a64_array(s
);
378 TCGv_i64
new_tmp_a64(DisasContext
*s
)
380 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
381 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
384 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
386 TCGv_i64 t
= new_tmp_a64(s
);
387 tcg_gen_movi_i64(t
, 0);
392 * Register access functions
394 * These functions are used for directly accessing a register in where
395 * changes to the final register value are likely to be made. If you
396 * need to use a register for temporary calculation (e.g. index type
397 * operations) use the read_* form.
399 * B1.2.1 Register mappings
401 * In instruction register encoding 31 can refer to ZR (zero register) or
402 * the SP (stack pointer) depending on context. In QEMU's case we map SP
403 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
404 * This is the point of the _sp forms.
406 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
409 return new_tmp_a64_zero(s
);
415 /* register access for when 31 == SP */
416 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
421 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
422 * representing the register contents. This TCGv is an auto-freed
423 * temporary so it need not be explicitly freed, and may be modified.
425 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
427 TCGv_i64 v
= new_tmp_a64(s
);
430 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
432 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
435 tcg_gen_movi_i64(v
, 0);
440 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
442 TCGv_i64 v
= new_tmp_a64(s
);
444 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
446 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
451 /* Return the offset into CPUARMState of a slice (from
452 * the least significant end) of FP register Qn (ie
454 * (Note that this is not the same mapping as for A32; see cpu.h)
456 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
458 return vec_reg_offset(s
, regno
, 0, size
);
461 /* Offset of the high half of the 128 bit vector Qn */
462 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
464 return vec_reg_offset(s
, regno
, 1, MO_64
);
467 /* Convenience accessors for reading and writing single and double
468 * FP registers. Writing clears the upper parts of the associated
469 * 128 bit vector register, as required by the architecture.
470 * Note that unlike the GP register accessors, the values returned
471 * by the read functions must be manually freed.
473 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
475 TCGv_i64 v
= tcg_temp_new_i64();
477 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
481 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
483 TCGv_i32 v
= tcg_temp_new_i32();
485 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
489 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
491 TCGv_i32 v
= tcg_temp_new_i32();
493 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
497 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
498 * If SVE is not enabled, then there are only 128 bits in the vector.
500 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
502 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
503 unsigned vsz
= vec_full_reg_size(s
);
505 /* Nop move, with side effect of clearing the tail. */
506 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
509 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
511 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
513 tcg_gen_st_i64(v
, cpu_env
, ofs
);
514 clear_vec_high(s
, false, reg
);
517 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
519 TCGv_i64 tmp
= tcg_temp_new_i64();
521 tcg_gen_extu_i32_i64(tmp
, v
);
522 write_fp_dreg(s
, reg
, tmp
);
523 tcg_temp_free_i64(tmp
);
526 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
528 TCGv_ptr statusptr
= tcg_temp_new_ptr();
531 /* In A64 all instructions (both FP and Neon) use the FPCR; there
532 * is no equivalent of the A32 Neon "standard FPSCR value".
533 * However half-precision operations operate under a different
534 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
537 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
539 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
541 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
545 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
546 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
547 GVecGen2Fn
*gvec_fn
, int vece
)
549 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
550 is_q
? 16 : 8, vec_full_reg_size(s
));
553 /* Expand a 2-operand + immediate AdvSIMD vector operation using
554 * an expander function.
556 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
557 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
559 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
560 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
563 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
564 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
565 GVecGen3Fn
*gvec_fn
, int vece
)
567 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
568 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
571 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
572 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
573 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
575 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
576 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
577 is_q
? 16 : 8, vec_full_reg_size(s
));
580 /* Expand a 2-operand operation using an out-of-line helper. */
581 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
582 int rn
, int data
, gen_helper_gvec_2
*fn
)
584 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
585 vec_full_reg_offset(s
, rn
),
586 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
589 /* Expand a 3-operand operation using an out-of-line helper. */
590 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
591 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
593 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
594 vec_full_reg_offset(s
, rn
),
595 vec_full_reg_offset(s
, rm
),
596 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
599 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
600 * an out-of-line helper.
602 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
603 int rm
, bool is_fp16
, int data
,
604 gen_helper_gvec_3_ptr
*fn
)
606 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
607 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
608 vec_full_reg_offset(s
, rn
),
609 vec_full_reg_offset(s
, rm
), fpst
,
610 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
611 tcg_temp_free_ptr(fpst
);
614 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
615 * than the 32 bit equivalent.
617 static inline void gen_set_NZ64(TCGv_i64 result
)
619 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
620 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
623 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
624 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
627 gen_set_NZ64(result
);
629 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
630 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
632 tcg_gen_movi_i32(cpu_CF
, 0);
633 tcg_gen_movi_i32(cpu_VF
, 0);
636 /* dest = T0 + T1; compute C, N, V and Z flags */
637 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
640 TCGv_i64 result
, flag
, tmp
;
641 result
= tcg_temp_new_i64();
642 flag
= tcg_temp_new_i64();
643 tmp
= tcg_temp_new_i64();
645 tcg_gen_movi_i64(tmp
, 0);
646 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
648 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
650 gen_set_NZ64(result
);
652 tcg_gen_xor_i64(flag
, result
, t0
);
653 tcg_gen_xor_i64(tmp
, t0
, t1
);
654 tcg_gen_andc_i64(flag
, flag
, tmp
);
655 tcg_temp_free_i64(tmp
);
656 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
658 tcg_gen_mov_i64(dest
, result
);
659 tcg_temp_free_i64(result
);
660 tcg_temp_free_i64(flag
);
662 /* 32 bit arithmetic */
663 TCGv_i32 t0_32
= tcg_temp_new_i32();
664 TCGv_i32 t1_32
= tcg_temp_new_i32();
665 TCGv_i32 tmp
= tcg_temp_new_i32();
667 tcg_gen_movi_i32(tmp
, 0);
668 tcg_gen_extrl_i64_i32(t0_32
, t0
);
669 tcg_gen_extrl_i64_i32(t1_32
, t1
);
670 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
671 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
672 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
673 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
674 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
675 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
677 tcg_temp_free_i32(tmp
);
678 tcg_temp_free_i32(t0_32
);
679 tcg_temp_free_i32(t1_32
);
683 /* dest = T0 - T1; compute C, N, V and Z flags */
684 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
687 /* 64 bit arithmetic */
688 TCGv_i64 result
, flag
, tmp
;
690 result
= tcg_temp_new_i64();
691 flag
= tcg_temp_new_i64();
692 tcg_gen_sub_i64(result
, t0
, t1
);
694 gen_set_NZ64(result
);
696 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
697 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
699 tcg_gen_xor_i64(flag
, result
, t0
);
700 tmp
= tcg_temp_new_i64();
701 tcg_gen_xor_i64(tmp
, t0
, t1
);
702 tcg_gen_and_i64(flag
, flag
, tmp
);
703 tcg_temp_free_i64(tmp
);
704 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
705 tcg_gen_mov_i64(dest
, result
);
706 tcg_temp_free_i64(flag
);
707 tcg_temp_free_i64(result
);
709 /* 32 bit arithmetic */
710 TCGv_i32 t0_32
= tcg_temp_new_i32();
711 TCGv_i32 t1_32
= tcg_temp_new_i32();
714 tcg_gen_extrl_i64_i32(t0_32
, t0
);
715 tcg_gen_extrl_i64_i32(t1_32
, t1
);
716 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
717 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
718 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
719 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
720 tmp
= tcg_temp_new_i32();
721 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
722 tcg_temp_free_i32(t0_32
);
723 tcg_temp_free_i32(t1_32
);
724 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
725 tcg_temp_free_i32(tmp
);
726 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
730 /* dest = T0 + T1 + CF; do not compute flags. */
731 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
733 TCGv_i64 flag
= tcg_temp_new_i64();
734 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
735 tcg_gen_add_i64(dest
, t0
, t1
);
736 tcg_gen_add_i64(dest
, dest
, flag
);
737 tcg_temp_free_i64(flag
);
740 tcg_gen_ext32u_i64(dest
, dest
);
744 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
745 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
748 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
749 result
= tcg_temp_new_i64();
750 cf_64
= tcg_temp_new_i64();
751 vf_64
= tcg_temp_new_i64();
752 tmp
= tcg_const_i64(0);
754 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
755 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
756 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
757 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
758 gen_set_NZ64(result
);
760 tcg_gen_xor_i64(vf_64
, result
, t0
);
761 tcg_gen_xor_i64(tmp
, t0
, t1
);
762 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
763 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
765 tcg_gen_mov_i64(dest
, result
);
767 tcg_temp_free_i64(tmp
);
768 tcg_temp_free_i64(vf_64
);
769 tcg_temp_free_i64(cf_64
);
770 tcg_temp_free_i64(result
);
772 TCGv_i32 t0_32
, t1_32
, tmp
;
773 t0_32
= tcg_temp_new_i32();
774 t1_32
= tcg_temp_new_i32();
775 tmp
= tcg_const_i32(0);
777 tcg_gen_extrl_i64_i32(t0_32
, t0
);
778 tcg_gen_extrl_i64_i32(t1_32
, t1
);
779 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
780 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
782 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
783 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
784 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
785 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
786 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
788 tcg_temp_free_i32(tmp
);
789 tcg_temp_free_i32(t1_32
);
790 tcg_temp_free_i32(t0_32
);
795 * Load/Store generators
799 * Store from GPR register to memory.
801 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
802 TCGv_i64 tcg_addr
, int size
, int memidx
,
804 unsigned int iss_srt
,
805 bool iss_sf
, bool iss_ar
)
808 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
813 syn
= syn_data_abort_with_iss(0,
819 0, 0, 0, 0, 0, false);
820 disas_set_insn_syndrome(s
, syn
);
824 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
825 TCGv_i64 tcg_addr
, int size
,
827 unsigned int iss_srt
,
828 bool iss_sf
, bool iss_ar
)
830 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
831 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
835 * Load from memory to GPR register
837 static void do_gpr_ld_memidx(DisasContext
*s
,
838 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
839 int size
, bool is_signed
,
840 bool extend
, int memidx
,
841 bool iss_valid
, unsigned int iss_srt
,
842 bool iss_sf
, bool iss_ar
)
844 MemOp memop
= s
->be_data
+ size
;
852 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
854 if (extend
&& is_signed
) {
856 tcg_gen_ext32u_i64(dest
, dest
);
862 syn
= syn_data_abort_with_iss(0,
868 0, 0, 0, 0, 0, false);
869 disas_set_insn_syndrome(s
, syn
);
873 static void do_gpr_ld(DisasContext
*s
,
874 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
875 int size
, bool is_signed
, bool extend
,
876 bool iss_valid
, unsigned int iss_srt
,
877 bool iss_sf
, bool iss_ar
)
879 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
881 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
885 * Store from FP register to memory
887 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
889 /* This writes the bottom N bits of a 128 bit wide vector to memory */
890 TCGv_i64 tmp
= tcg_temp_new_i64();
891 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
893 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
896 bool be
= s
->be_data
== MO_BE
;
897 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
899 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
900 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
902 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
903 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
905 tcg_temp_free_i64(tcg_hiaddr
);
908 tcg_temp_free_i64(tmp
);
912 * Load from memory to FP register
914 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
916 /* This always zero-extends and writes to a full 128 bit wide vector */
917 TCGv_i64 tmplo
= tcg_temp_new_i64();
918 TCGv_i64 tmphi
= NULL
;
921 MemOp memop
= s
->be_data
+ size
;
922 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
924 bool be
= s
->be_data
== MO_BE
;
927 tmphi
= tcg_temp_new_i64();
928 tcg_hiaddr
= tcg_temp_new_i64();
930 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
931 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
933 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
935 tcg_temp_free_i64(tcg_hiaddr
);
938 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
939 tcg_temp_free_i64(tmplo
);
942 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
943 tcg_temp_free_i64(tmphi
);
945 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
949 * Vector load/store helpers.
951 * The principal difference between this and a FP load is that we don't
952 * zero extend as we are filling a partial chunk of the vector register.
953 * These functions don't support 128 bit loads/stores, which would be
954 * normal load/store operations.
956 * The _i32 versions are useful when operating on 32 bit quantities
957 * (eg for floating point single or using Neon helper functions).
960 /* Get value of an element within a vector register */
961 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
962 int element
, MemOp memop
)
964 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
967 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
979 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
986 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
989 g_assert_not_reached();
993 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
994 int element
, MemOp memop
)
996 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
999 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1005 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1008 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1015 g_assert_not_reached();
1019 /* Set value of an element within a vector register */
1020 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1021 int element
, MemOp memop
)
1023 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1026 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1032 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1035 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1038 g_assert_not_reached();
1042 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1043 int destidx
, int element
, MemOp memop
)
1045 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1048 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1051 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1054 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1057 g_assert_not_reached();
1061 /* Store from vector register to memory */
1062 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1063 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1065 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1067 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1068 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1070 tcg_temp_free_i64(tcg_tmp
);
1073 /* Load from memory to vector register */
1074 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1075 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1079 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1080 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1082 tcg_temp_free_i64(tcg_tmp
);
1085 /* Check that FP/Neon access is enabled. If it is, return
1086 * true. If not, emit code to generate an appropriate exception,
1087 * and return false; the caller should not emit any code for
1088 * the instruction. Note that this check must happen after all
1089 * unallocated-encoding checks (otherwise the syndrome information
1090 * for the resulting exception will be incorrect).
1092 static inline bool fp_access_check(DisasContext
*s
)
1094 assert(!s
->fp_access_checked
);
1095 s
->fp_access_checked
= true;
1097 if (!s
->fp_excp_el
) {
1101 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1102 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1106 /* Check that SVE access is enabled. If it is, return true.
1107 * If not, emit code to generate an appropriate exception and return false.
1109 bool sve_access_check(DisasContext
*s
)
1111 if (s
->sve_excp_el
) {
1112 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1116 return fp_access_check(s
);
1120 * This utility function is for doing register extension with an
1121 * optional shift. You will likely want to pass a temporary for the
1122 * destination register. See DecodeRegExtend() in the ARM ARM.
1124 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1125 int option
, unsigned int shift
)
1127 int extsize
= extract32(option
, 0, 2);
1128 bool is_signed
= extract32(option
, 2, 1);
1133 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1139 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1142 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1154 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1157 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1163 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1167 static inline void gen_check_sp_alignment(DisasContext
*s
)
1169 /* The AArch64 architecture mandates that (if enabled via PSTATE
1170 * or SCTLR bits) there is a check that SP is 16-aligned on every
1171 * SP-relative load or store (with an exception generated if it is not).
1172 * In line with general QEMU practice regarding misaligned accesses,
1173 * we omit these checks for the sake of guest program performance.
1174 * This function is provided as a hook so we can more easily add these
1175 * checks in future (possibly as a "favour catching guest program bugs
1176 * over speed" user selectable option).
1181 * This provides a simple table based table lookup decoder. It is
1182 * intended to be used when the relevant bits for decode are too
1183 * awkwardly placed and switch/if based logic would be confusing and
1184 * deeply nested. Since it's a linear search through the table, tables
1185 * should be kept small.
1187 * It returns the first handler where insn & mask == pattern, or
1188 * NULL if there is no match.
1189 * The table is terminated by an empty mask (i.e. 0)
1191 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1194 const AArch64DecodeTable
*tptr
= table
;
1196 while (tptr
->mask
) {
1197 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1198 return tptr
->disas_fn
;
1206 * The instruction disassembly implemented here matches
1207 * the instruction encoding classifications in chapter C4
1208 * of the ARM Architecture Reference Manual (DDI0487B_a);
1209 * classification names and decode diagrams here should generally
1210 * match up with those in the manual.
1213 /* Unconditional branch (immediate)
1215 * +----+-----------+-------------------------------------+
1216 * | op | 0 0 1 0 1 | imm26 |
1217 * +----+-----------+-------------------------------------+
1219 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1221 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1223 if (insn
& (1U << 31)) {
1224 /* BL Branch with link */
1225 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1228 /* B Branch / BL Branch with link */
1230 gen_goto_tb(s
, 0, addr
);
1233 /* Compare and branch (immediate)
1234 * 31 30 25 24 23 5 4 0
1235 * +----+-------------+----+---------------------+--------+
1236 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1237 * +----+-------------+----+---------------------+--------+
1239 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1241 unsigned int sf
, op
, rt
;
1243 TCGLabel
*label_match
;
1246 sf
= extract32(insn
, 31, 1);
1247 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1248 rt
= extract32(insn
, 0, 5);
1249 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1251 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1252 label_match
= gen_new_label();
1255 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1256 tcg_cmp
, 0, label_match
);
1258 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1259 gen_set_label(label_match
);
1260 gen_goto_tb(s
, 1, addr
);
1263 /* Test and branch (immediate)
1264 * 31 30 25 24 23 19 18 5 4 0
1265 * +----+-------------+----+-------+-------------+------+
1266 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1267 * +----+-------------+----+-------+-------------+------+
1269 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1271 unsigned int bit_pos
, op
, rt
;
1273 TCGLabel
*label_match
;
1276 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1277 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1278 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1279 rt
= extract32(insn
, 0, 5);
1281 tcg_cmp
= tcg_temp_new_i64();
1282 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1283 label_match
= gen_new_label();
1286 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1287 tcg_cmp
, 0, label_match
);
1288 tcg_temp_free_i64(tcg_cmp
);
1289 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1290 gen_set_label(label_match
);
1291 gen_goto_tb(s
, 1, addr
);
1294 /* Conditional branch (immediate)
1295 * 31 25 24 23 5 4 3 0
1296 * +---------------+----+---------------------+----+------+
1297 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1298 * +---------------+----+---------------------+----+------+
1300 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1305 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1306 unallocated_encoding(s
);
1309 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1310 cond
= extract32(insn
, 0, 4);
1314 /* genuinely conditional branches */
1315 TCGLabel
*label_match
= gen_new_label();
1316 arm_gen_test_cc(cond
, label_match
);
1317 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1318 gen_set_label(label_match
);
1319 gen_goto_tb(s
, 1, addr
);
1321 /* 0xe and 0xf are both "always" conditions */
1322 gen_goto_tb(s
, 0, addr
);
1326 /* HINT instruction group, including various allocated HINTs */
1327 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1328 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1330 unsigned int selector
= crm
<< 3 | op2
;
1333 unallocated_encoding(s
);
1338 case 0b00000: /* NOP */
1340 case 0b00011: /* WFI */
1341 s
->base
.is_jmp
= DISAS_WFI
;
1343 case 0b00001: /* YIELD */
1344 /* When running in MTTCG we don't generate jumps to the yield and
1345 * WFE helpers as it won't affect the scheduling of other vCPUs.
1346 * If we wanted to more completely model WFE/SEV so we don't busy
1347 * spin unnecessarily we would need to do something more involved.
1349 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1350 s
->base
.is_jmp
= DISAS_YIELD
;
1353 case 0b00010: /* WFE */
1354 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1355 s
->base
.is_jmp
= DISAS_WFE
;
1358 case 0b00100: /* SEV */
1359 case 0b00101: /* SEVL */
1360 /* we treat all as NOP at least for now */
1362 case 0b00111: /* XPACLRI */
1363 if (s
->pauth_active
) {
1364 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1367 case 0b01000: /* PACIA1716 */
1368 if (s
->pauth_active
) {
1369 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1372 case 0b01010: /* PACIB1716 */
1373 if (s
->pauth_active
) {
1374 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1377 case 0b01100: /* AUTIA1716 */
1378 if (s
->pauth_active
) {
1379 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1382 case 0b01110: /* AUTIB1716 */
1383 if (s
->pauth_active
) {
1384 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1387 case 0b11000: /* PACIAZ */
1388 if (s
->pauth_active
) {
1389 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1390 new_tmp_a64_zero(s
));
1393 case 0b11001: /* PACIASP */
1394 if (s
->pauth_active
) {
1395 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1398 case 0b11010: /* PACIBZ */
1399 if (s
->pauth_active
) {
1400 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1401 new_tmp_a64_zero(s
));
1404 case 0b11011: /* PACIBSP */
1405 if (s
->pauth_active
) {
1406 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1409 case 0b11100: /* AUTIAZ */
1410 if (s
->pauth_active
) {
1411 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1412 new_tmp_a64_zero(s
));
1415 case 0b11101: /* AUTIASP */
1416 if (s
->pauth_active
) {
1417 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1420 case 0b11110: /* AUTIBZ */
1421 if (s
->pauth_active
) {
1422 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1423 new_tmp_a64_zero(s
));
1426 case 0b11111: /* AUTIBSP */
1427 if (s
->pauth_active
) {
1428 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1432 /* default specified as NOP equivalent */
1437 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1439 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1442 /* CLREX, DSB, DMB, ISB */
1443 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1444 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1449 unallocated_encoding(s
);
1460 case 1: /* MBReqTypes_Reads */
1461 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1463 case 2: /* MBReqTypes_Writes */
1464 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1466 default: /* MBReqTypes_All */
1467 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1473 /* We need to break the TB after this insn to execute
1474 * a self-modified code correctly and also to take
1475 * any pending interrupts immediately.
1478 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1482 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1483 goto do_unallocated
;
1486 * TODO: There is no speculation barrier opcode for TCG;
1487 * MB and end the TB instead.
1489 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1490 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1495 unallocated_encoding(s
);
1500 static void gen_xaflag(void)
1502 TCGv_i32 z
= tcg_temp_new_i32();
1504 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1513 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1514 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1517 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1518 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1520 /* (!C & Z) << 31 -> -(Z & ~C) */
1521 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1522 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1525 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1527 tcg_temp_free_i32(z
);
1530 static void gen_axflag(void)
1532 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1533 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1535 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1536 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1538 tcg_gen_movi_i32(cpu_NF
, 0);
1539 tcg_gen_movi_i32(cpu_VF
, 0);
1542 /* MSR (immediate) - move immediate to processor state field */
1543 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1544 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1547 int op
= op1
<< 3 | op2
;
1549 /* End the TB by default, chaining is ok. */
1550 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1553 case 0x00: /* CFINV */
1554 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1555 goto do_unallocated
;
1557 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1558 s
->base
.is_jmp
= DISAS_NEXT
;
1561 case 0x01: /* XAFlag */
1562 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1563 goto do_unallocated
;
1566 s
->base
.is_jmp
= DISAS_NEXT
;
1569 case 0x02: /* AXFlag */
1570 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1571 goto do_unallocated
;
1574 s
->base
.is_jmp
= DISAS_NEXT
;
1577 case 0x03: /* UAO */
1578 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1579 goto do_unallocated
;
1582 set_pstate_bits(PSTATE_UAO
);
1584 clear_pstate_bits(PSTATE_UAO
);
1586 t1
= tcg_const_i32(s
->current_el
);
1587 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1588 tcg_temp_free_i32(t1
);
1591 case 0x04: /* PAN */
1592 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1593 goto do_unallocated
;
1596 set_pstate_bits(PSTATE_PAN
);
1598 clear_pstate_bits(PSTATE_PAN
);
1600 t1
= tcg_const_i32(s
->current_el
);
1601 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1602 tcg_temp_free_i32(t1
);
1605 case 0x05: /* SPSel */
1606 if (s
->current_el
== 0) {
1607 goto do_unallocated
;
1609 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1610 gen_helper_msr_i_spsel(cpu_env
, t1
);
1611 tcg_temp_free_i32(t1
);
1614 case 0x1e: /* DAIFSet */
1615 t1
= tcg_const_i32(crm
);
1616 gen_helper_msr_i_daifset(cpu_env
, t1
);
1617 tcg_temp_free_i32(t1
);
1620 case 0x1f: /* DAIFClear */
1621 t1
= tcg_const_i32(crm
);
1622 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1623 tcg_temp_free_i32(t1
);
1624 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1625 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1628 case 0x1c: /* TCO */
1629 if (dc_isar_feature(aa64_mte
, s
)) {
1630 /* Full MTE is enabled -- set the TCO bit as directed. */
1632 set_pstate_bits(PSTATE_TCO
);
1634 clear_pstate_bits(PSTATE_TCO
);
1636 t1
= tcg_const_i32(s
->current_el
);
1637 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1638 tcg_temp_free_i32(t1
);
1639 /* Many factors, including TCO, go into MTE_ACTIVE. */
1640 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1641 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1642 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1643 s
->base
.is_jmp
= DISAS_NEXT
;
1645 goto do_unallocated
;
1651 unallocated_encoding(s
);
1656 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1658 TCGv_i32 tmp
= tcg_temp_new_i32();
1659 TCGv_i32 nzcv
= tcg_temp_new_i32();
1661 /* build bit 31, N */
1662 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1663 /* build bit 30, Z */
1664 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1665 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1666 /* build bit 29, C */
1667 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1668 /* build bit 28, V */
1669 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1670 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1671 /* generate result */
1672 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1674 tcg_temp_free_i32(nzcv
);
1675 tcg_temp_free_i32(tmp
);
1678 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1680 TCGv_i32 nzcv
= tcg_temp_new_i32();
1682 /* take NZCV from R[t] */
1683 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1686 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1688 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1689 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1691 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1692 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1694 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1695 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1696 tcg_temp_free_i32(nzcv
);
1699 /* MRS - move from system register
1700 * MSR (register) - move to system register
1703 * These are all essentially the same insn in 'read' and 'write'
1704 * versions, with varying op0 fields.
1706 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1707 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1708 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1710 const ARMCPRegInfo
*ri
;
1713 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1714 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1715 crn
, crm
, op0
, op1
, op2
));
1718 /* Unknown register; this might be a guest error or a QEMU
1719 * unimplemented feature.
1721 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1722 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1723 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1724 unallocated_encoding(s
);
1728 /* Check access permissions */
1729 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1730 unallocated_encoding(s
);
1735 /* Emit code to perform further access permissions checks at
1736 * runtime; this may result in an exception.
1739 TCGv_i32 tcg_syn
, tcg_isread
;
1742 gen_a64_set_pc_im(s
->pc_curr
);
1743 tmpptr
= tcg_const_ptr(ri
);
1744 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1745 tcg_syn
= tcg_const_i32(syndrome
);
1746 tcg_isread
= tcg_const_i32(isread
);
1747 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1748 tcg_temp_free_ptr(tmpptr
);
1749 tcg_temp_free_i32(tcg_syn
);
1750 tcg_temp_free_i32(tcg_isread
);
1751 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1753 * The readfn or writefn might raise an exception;
1754 * synchronize the CPU state in case it does.
1756 gen_a64_set_pc_im(s
->pc_curr
);
1759 /* Handle special cases first */
1760 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1764 tcg_rt
= cpu_reg(s
, rt
);
1766 gen_get_nzcv(tcg_rt
);
1768 gen_set_nzcv(tcg_rt
);
1771 case ARM_CP_CURRENTEL
:
1772 /* Reads as current EL value from pstate, which is
1773 * guaranteed to be constant by the tb flags.
1775 tcg_rt
= cpu_reg(s
, rt
);
1776 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1779 /* Writes clear the aligned block of memory which rt points into. */
1780 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1781 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1786 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1788 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1792 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1796 tcg_rt
= cpu_reg(s
, rt
);
1799 if (ri
->type
& ARM_CP_CONST
) {
1800 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1801 } else if (ri
->readfn
) {
1803 tmpptr
= tcg_const_ptr(ri
);
1804 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1805 tcg_temp_free_ptr(tmpptr
);
1807 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1810 if (ri
->type
& ARM_CP_CONST
) {
1811 /* If not forbidden by access permissions, treat as WI */
1813 } else if (ri
->writefn
) {
1815 tmpptr
= tcg_const_ptr(ri
);
1816 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1817 tcg_temp_free_ptr(tmpptr
);
1819 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1823 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1824 /* I/O operations must end the TB here (whether read or write) */
1825 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1827 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1829 * A write to any coprocessor regiser that ends a TB
1830 * must rebuild the hflags for the next TB.
1832 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1833 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1834 tcg_temp_free_i32(tcg_el
);
1836 * We default to ending the TB on a coprocessor register write,
1837 * but allow this to be suppressed by the register definition
1838 * (usually only necessary to work around guest bugs).
1840 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1845 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1846 * +---------------------+---+-----+-----+-------+-------+-----+------+
1847 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1848 * +---------------------+---+-----+-----+-------+-------+-----+------+
1850 static void disas_system(DisasContext
*s
, uint32_t insn
)
1852 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1853 l
= extract32(insn
, 21, 1);
1854 op0
= extract32(insn
, 19, 2);
1855 op1
= extract32(insn
, 16, 3);
1856 crn
= extract32(insn
, 12, 4);
1857 crm
= extract32(insn
, 8, 4);
1858 op2
= extract32(insn
, 5, 3);
1859 rt
= extract32(insn
, 0, 5);
1862 if (l
|| rt
!= 31) {
1863 unallocated_encoding(s
);
1867 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1868 handle_hint(s
, insn
, op1
, op2
, crm
);
1870 case 3: /* CLREX, DSB, DMB, ISB */
1871 handle_sync(s
, insn
, op1
, op2
, crm
);
1873 case 4: /* MSR (immediate) */
1874 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1877 unallocated_encoding(s
);
1882 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1885 /* Exception generation
1887 * 31 24 23 21 20 5 4 2 1 0
1888 * +-----------------+-----+------------------------+-----+----+
1889 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1890 * +-----------------------+------------------------+----------+
1892 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1894 int opc
= extract32(insn
, 21, 3);
1895 int op2_ll
= extract32(insn
, 0, 5);
1896 int imm16
= extract32(insn
, 5, 16);
1901 /* For SVC, HVC and SMC we advance the single-step state
1902 * machine before taking the exception. This is architecturally
1903 * mandated, to ensure that single-stepping a system call
1904 * instruction works properly.
1909 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1910 syn_aa64_svc(imm16
), default_exception_el(s
));
1913 if (s
->current_el
== 0) {
1914 unallocated_encoding(s
);
1917 /* The pre HVC helper handles cases when HVC gets trapped
1918 * as an undefined insn by runtime configuration.
1920 gen_a64_set_pc_im(s
->pc_curr
);
1921 gen_helper_pre_hvc(cpu_env
);
1923 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1924 syn_aa64_hvc(imm16
), 2);
1927 if (s
->current_el
== 0) {
1928 unallocated_encoding(s
);
1931 gen_a64_set_pc_im(s
->pc_curr
);
1932 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1933 gen_helper_pre_smc(cpu_env
, tmp
);
1934 tcg_temp_free_i32(tmp
);
1936 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1937 syn_aa64_smc(imm16
), 3);
1940 unallocated_encoding(s
);
1946 unallocated_encoding(s
);
1950 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1954 unallocated_encoding(s
);
1957 /* HLT. This has two purposes.
1958 * Architecturally, it is an external halting debug instruction.
1959 * Since QEMU doesn't implement external debug, we treat this as
1960 * it is required for halting debug disabled: it will UNDEF.
1961 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1963 if (semihosting_enabled() && imm16
== 0xf000) {
1964 #ifndef CONFIG_USER_ONLY
1965 /* In system mode, don't allow userspace access to semihosting,
1966 * to provide some semblance of security (and for consistency
1967 * with our 32-bit semihosting).
1969 if (s
->current_el
== 0) {
1970 unsupported_encoding(s
, insn
);
1974 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1976 unsupported_encoding(s
, insn
);
1980 if (op2_ll
< 1 || op2_ll
> 3) {
1981 unallocated_encoding(s
);
1984 /* DCPS1, DCPS2, DCPS3 */
1985 unsupported_encoding(s
, insn
);
1988 unallocated_encoding(s
);
1993 /* Unconditional branch (register)
1994 * 31 25 24 21 20 16 15 10 9 5 4 0
1995 * +---------------+-------+-------+-------+------+-------+
1996 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1997 * +---------------+-------+-------+-------+------+-------+
1999 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2001 unsigned int opc
, op2
, op3
, rn
, op4
;
2002 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2006 opc
= extract32(insn
, 21, 4);
2007 op2
= extract32(insn
, 16, 5);
2008 op3
= extract32(insn
, 10, 6);
2009 rn
= extract32(insn
, 5, 5);
2010 op4
= extract32(insn
, 0, 5);
2013 goto do_unallocated
;
2025 goto do_unallocated
;
2027 dst
= cpu_reg(s
, rn
);
2032 if (!dc_isar_feature(aa64_pauth
, s
)) {
2033 goto do_unallocated
;
2037 if (rn
!= 0x1f || op4
!= 0x1f) {
2038 goto do_unallocated
;
2041 modifier
= cpu_X
[31];
2043 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2045 goto do_unallocated
;
2047 modifier
= new_tmp_a64_zero(s
);
2049 if (s
->pauth_active
) {
2050 dst
= new_tmp_a64(s
);
2052 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2054 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2057 dst
= cpu_reg(s
, rn
);
2062 goto do_unallocated
;
2064 gen_a64_set_pc(s
, dst
);
2065 /* BLR also needs to load return address */
2067 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2073 if (!dc_isar_feature(aa64_pauth
, s
)) {
2074 goto do_unallocated
;
2076 if ((op3
& ~1) != 2) {
2077 goto do_unallocated
;
2079 btype_mod
= opc
& 1;
2080 if (s
->pauth_active
) {
2081 dst
= new_tmp_a64(s
);
2082 modifier
= cpu_reg_sp(s
, op4
);
2084 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2086 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2089 dst
= cpu_reg(s
, rn
);
2091 gen_a64_set_pc(s
, dst
);
2092 /* BLRAA also needs to load return address */
2094 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2099 if (s
->current_el
== 0) {
2100 goto do_unallocated
;
2105 goto do_unallocated
;
2107 dst
= tcg_temp_new_i64();
2108 tcg_gen_ld_i64(dst
, cpu_env
,
2109 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2112 case 2: /* ERETAA */
2113 case 3: /* ERETAB */
2114 if (!dc_isar_feature(aa64_pauth
, s
)) {
2115 goto do_unallocated
;
2117 if (rn
!= 0x1f || op4
!= 0x1f) {
2118 goto do_unallocated
;
2120 dst
= tcg_temp_new_i64();
2121 tcg_gen_ld_i64(dst
, cpu_env
,
2122 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2123 if (s
->pauth_active
) {
2124 modifier
= cpu_X
[31];
2126 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2128 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2134 goto do_unallocated
;
2136 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2140 gen_helper_exception_return(cpu_env
, dst
);
2141 tcg_temp_free_i64(dst
);
2142 /* Must exit loop to check un-masked IRQs */
2143 s
->base
.is_jmp
= DISAS_EXIT
;
2147 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2148 goto do_unallocated
;
2150 unsupported_encoding(s
, insn
);
2156 unallocated_encoding(s
);
2160 switch (btype_mod
) {
2162 if (dc_isar_feature(aa64_bti
, s
)) {
2163 /* BR to {x16,x17} or !guard -> 1, else 3. */
2164 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2169 if (dc_isar_feature(aa64_bti
, s
)) {
2170 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2175 default: /* RET or none of the above. */
2176 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2180 s
->base
.is_jmp
= DISAS_JUMP
;
2183 /* Branches, exception generating and system instructions */
2184 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2186 switch (extract32(insn
, 25, 7)) {
2187 case 0x0a: case 0x0b:
2188 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2189 disas_uncond_b_imm(s
, insn
);
2191 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2192 disas_comp_b_imm(s
, insn
);
2194 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2195 disas_test_b_imm(s
, insn
);
2197 case 0x2a: /* Conditional branch (immediate) */
2198 disas_cond_b_imm(s
, insn
);
2200 case 0x6a: /* Exception generation / System */
2201 if (insn
& (1 << 24)) {
2202 if (extract32(insn
, 22, 2) == 0) {
2203 disas_system(s
, insn
);
2205 unallocated_encoding(s
);
2211 case 0x6b: /* Unconditional branch (register) */
2212 disas_uncond_b_reg(s
, insn
);
2215 unallocated_encoding(s
);
2221 * Load/Store exclusive instructions are implemented by remembering
2222 * the value/address loaded, and seeing if these are the same
2223 * when the store is performed. This is not actually the architecturally
2224 * mandated semantics, but it works for typical guest code sequences
2225 * and avoids having to monitor regular stores.
2227 * The store exclusive uses the atomic cmpxchg primitives to avoid
2228 * races in multi-threaded linux-user and when MTTCG softmmu is
2231 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2232 TCGv_i64 addr
, int size
, bool is_pair
)
2234 int idx
= get_mem_index(s
);
2235 MemOp memop
= s
->be_data
;
2237 g_assert(size
<= 3);
2239 g_assert(size
>= 2);
2241 /* The pair must be single-copy atomic for the doubleword. */
2242 memop
|= MO_64
| MO_ALIGN
;
2243 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2244 if (s
->be_data
== MO_LE
) {
2245 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2246 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2248 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2249 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2252 /* The pair must be single-copy atomic for *each* doubleword, not
2253 the entire quadword, however it must be quadword aligned. */
2255 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2256 memop
| MO_ALIGN_16
);
2258 TCGv_i64 addr2
= tcg_temp_new_i64();
2259 tcg_gen_addi_i64(addr2
, addr
, 8);
2260 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2261 tcg_temp_free_i64(addr2
);
2263 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2264 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2267 memop
|= size
| MO_ALIGN
;
2268 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2269 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2271 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2274 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2275 TCGv_i64 addr
, int size
, int is_pair
)
2277 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2278 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2281 * [addr + datasize] = {Rt2};
2287 * env->exclusive_addr = -1;
2289 TCGLabel
*fail_label
= gen_new_label();
2290 TCGLabel
*done_label
= gen_new_label();
2293 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2295 tmp
= tcg_temp_new_i64();
2298 if (s
->be_data
== MO_LE
) {
2299 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2301 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2303 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2304 cpu_exclusive_val
, tmp
,
2306 MO_64
| MO_ALIGN
| s
->be_data
);
2307 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2308 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2309 if (!HAVE_CMPXCHG128
) {
2310 gen_helper_exit_atomic(cpu_env
);
2311 s
->base
.is_jmp
= DISAS_NORETURN
;
2312 } else if (s
->be_data
== MO_LE
) {
2313 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2318 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2323 } else if (s
->be_data
== MO_LE
) {
2324 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2325 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2327 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2328 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2331 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2332 cpu_reg(s
, rt
), get_mem_index(s
),
2333 size
| MO_ALIGN
| s
->be_data
);
2334 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2336 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2337 tcg_temp_free_i64(tmp
);
2338 tcg_gen_br(done_label
);
2340 gen_set_label(fail_label
);
2341 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2342 gen_set_label(done_label
);
2343 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2346 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2349 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2350 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2351 int memidx
= get_mem_index(s
);
2352 TCGv_i64 clean_addr
;
2355 gen_check_sp_alignment(s
);
2357 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2358 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2359 size
| MO_ALIGN
| s
->be_data
);
2362 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2365 TCGv_i64 s1
= cpu_reg(s
, rs
);
2366 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2367 TCGv_i64 t1
= cpu_reg(s
, rt
);
2368 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2369 TCGv_i64 clean_addr
;
2370 int memidx
= get_mem_index(s
);
2373 gen_check_sp_alignment(s
);
2375 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2378 TCGv_i64 cmp
= tcg_temp_new_i64();
2379 TCGv_i64 val
= tcg_temp_new_i64();
2381 if (s
->be_data
== MO_LE
) {
2382 tcg_gen_concat32_i64(val
, t1
, t2
);
2383 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2385 tcg_gen_concat32_i64(val
, t2
, t1
);
2386 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2389 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2390 MO_64
| MO_ALIGN
| s
->be_data
);
2391 tcg_temp_free_i64(val
);
2393 if (s
->be_data
== MO_LE
) {
2394 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2396 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2398 tcg_temp_free_i64(cmp
);
2399 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2400 if (HAVE_CMPXCHG128
) {
2401 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2402 if (s
->be_data
== MO_LE
) {
2403 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2404 clean_addr
, t1
, t2
);
2406 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2407 clean_addr
, t1
, t2
);
2409 tcg_temp_free_i32(tcg_rs
);
2411 gen_helper_exit_atomic(cpu_env
);
2412 s
->base
.is_jmp
= DISAS_NORETURN
;
2415 TCGv_i64 d1
= tcg_temp_new_i64();
2416 TCGv_i64 d2
= tcg_temp_new_i64();
2417 TCGv_i64 a2
= tcg_temp_new_i64();
2418 TCGv_i64 c1
= tcg_temp_new_i64();
2419 TCGv_i64 c2
= tcg_temp_new_i64();
2420 TCGv_i64 zero
= tcg_const_i64(0);
2422 /* Load the two words, in memory order. */
2423 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2424 MO_64
| MO_ALIGN_16
| s
->be_data
);
2425 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2426 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2428 /* Compare the two words, also in memory order. */
2429 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2430 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2431 tcg_gen_and_i64(c2
, c2
, c1
);
2433 /* If compare equal, write back new data, else write back old data. */
2434 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2435 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2436 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2437 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2438 tcg_temp_free_i64(a2
);
2439 tcg_temp_free_i64(c1
);
2440 tcg_temp_free_i64(c2
);
2441 tcg_temp_free_i64(zero
);
2443 /* Write back the data from memory to Rs. */
2444 tcg_gen_mov_i64(s1
, d1
);
2445 tcg_gen_mov_i64(s2
, d2
);
2446 tcg_temp_free_i64(d1
);
2447 tcg_temp_free_i64(d2
);
2451 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2452 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2454 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2456 int opc0
= extract32(opc
, 0, 1);
2460 regsize
= opc0
? 32 : 64;
2462 regsize
= size
== 3 ? 64 : 32;
2464 return regsize
== 64;
2467 /* Load/store exclusive
2469 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2470 * +-----+-------------+----+---+----+------+----+-------+------+------+
2471 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2472 * +-----+-------------+----+---+----+------+----+-------+------+------+
2474 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2475 * L: 0 -> store, 1 -> load
2476 * o2: 0 -> exclusive, 1 -> not
2477 * o1: 0 -> single register, 1 -> register pair
2478 * o0: 1 -> load-acquire/store-release, 0 -> not
2480 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2482 int rt
= extract32(insn
, 0, 5);
2483 int rn
= extract32(insn
, 5, 5);
2484 int rt2
= extract32(insn
, 10, 5);
2485 int rs
= extract32(insn
, 16, 5);
2486 int is_lasr
= extract32(insn
, 15, 1);
2487 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2488 int size
= extract32(insn
, 30, 2);
2489 TCGv_i64 clean_addr
;
2491 switch (o2_L_o1_o0
) {
2492 case 0x0: /* STXR */
2493 case 0x1: /* STLXR */
2495 gen_check_sp_alignment(s
);
2498 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2500 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2501 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2504 case 0x4: /* LDXR */
2505 case 0x5: /* LDAXR */
2507 gen_check_sp_alignment(s
);
2509 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2511 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2513 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2517 case 0x8: /* STLLR */
2518 if (!dc_isar_feature(aa64_lor
, s
)) {
2521 /* StoreLORelease is the same as Store-Release for QEMU. */
2523 case 0x9: /* STLR */
2524 /* Generate ISS for non-exclusive accesses including LASR. */
2526 gen_check_sp_alignment(s
);
2528 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2529 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2530 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2531 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2534 case 0xc: /* LDLAR */
2535 if (!dc_isar_feature(aa64_lor
, s
)) {
2538 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2540 case 0xd: /* LDAR */
2541 /* Generate ISS for non-exclusive accesses including LASR. */
2543 gen_check_sp_alignment(s
);
2545 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2546 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2547 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2548 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2551 case 0x2: case 0x3: /* CASP / STXP */
2552 if (size
& 2) { /* STXP / STLXP */
2554 gen_check_sp_alignment(s
);
2557 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2559 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2560 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2564 && ((rt
| rs
) & 1) == 0
2565 && dc_isar_feature(aa64_atomics
, s
)) {
2567 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2572 case 0x6: case 0x7: /* CASPA / LDXP */
2573 if (size
& 2) { /* LDXP / LDAXP */
2575 gen_check_sp_alignment(s
);
2577 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2579 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2581 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2586 && ((rt
| rs
) & 1) == 0
2587 && dc_isar_feature(aa64_atomics
, s
)) {
2588 /* CASPA / CASPAL */
2589 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2595 case 0xb: /* CASL */
2596 case 0xe: /* CASA */
2597 case 0xf: /* CASAL */
2598 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2599 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2604 unallocated_encoding(s
);
2608 * Load register (literal)
2610 * 31 30 29 27 26 25 24 23 5 4 0
2611 * +-----+-------+---+-----+-------------------+-------+
2612 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2613 * +-----+-------+---+-----+-------------------+-------+
2615 * V: 1 -> vector (simd/fp)
2616 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2617 * 10-> 32 bit signed, 11 -> prefetch
2618 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2620 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2622 int rt
= extract32(insn
, 0, 5);
2623 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2624 bool is_vector
= extract32(insn
, 26, 1);
2625 int opc
= extract32(insn
, 30, 2);
2626 bool is_signed
= false;
2628 TCGv_i64 tcg_rt
, clean_addr
;
2632 unallocated_encoding(s
);
2636 if (!fp_access_check(s
)) {
2641 /* PRFM (literal) : prefetch */
2644 size
= 2 + extract32(opc
, 0, 1);
2645 is_signed
= extract32(opc
, 1, 1);
2648 tcg_rt
= cpu_reg(s
, rt
);
2650 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2652 do_fp_ld(s
, rt
, clean_addr
, size
);
2654 /* Only unsigned 32bit loads target 32bit registers. */
2655 bool iss_sf
= opc
!= 0;
2657 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2658 true, rt
, iss_sf
, false);
2660 tcg_temp_free_i64(clean_addr
);
2664 * LDNP (Load Pair - non-temporal hint)
2665 * LDP (Load Pair - non vector)
2666 * LDPSW (Load Pair Signed Word - non vector)
2667 * STNP (Store Pair - non-temporal hint)
2668 * STP (Store Pair - non vector)
2669 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2670 * LDP (Load Pair of SIMD&FP)
2671 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2672 * STP (Store Pair of SIMD&FP)
2674 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2675 * +-----+-------+---+---+-------+---+-----------------------------+
2676 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2677 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2679 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2681 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2682 * V: 0 -> GPR, 1 -> Vector
2683 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2684 * 10 -> signed offset, 11 -> pre-index
2685 * L: 0 -> Store 1 -> Load
2687 * Rt, Rt2 = GPR or SIMD registers to be stored
2688 * Rn = general purpose register containing address
2689 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2691 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2693 int rt
= extract32(insn
, 0, 5);
2694 int rn
= extract32(insn
, 5, 5);
2695 int rt2
= extract32(insn
, 10, 5);
2696 uint64_t offset
= sextract64(insn
, 15, 7);
2697 int index
= extract32(insn
, 23, 2);
2698 bool is_vector
= extract32(insn
, 26, 1);
2699 bool is_load
= extract32(insn
, 22, 1);
2700 int opc
= extract32(insn
, 30, 2);
2702 bool is_signed
= false;
2703 bool postindex
= false;
2706 TCGv_i64 clean_addr
, dirty_addr
;
2711 unallocated_encoding(s
);
2718 size
= 2 + extract32(opc
, 1, 1);
2719 is_signed
= extract32(opc
, 0, 1);
2720 if (!is_load
&& is_signed
) {
2721 unallocated_encoding(s
);
2727 case 1: /* post-index */
2732 /* signed offset with "non-temporal" hint. Since we don't emulate
2733 * caches we don't care about hints to the cache system about
2734 * data access patterns, and handle this identically to plain
2738 /* There is no non-temporal-hint version of LDPSW */
2739 unallocated_encoding(s
);
2744 case 2: /* signed offset, rn not updated */
2747 case 3: /* pre-index */
2753 if (is_vector
&& !fp_access_check(s
)) {
2760 gen_check_sp_alignment(s
);
2763 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2765 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2767 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2771 do_fp_ld(s
, rt
, clean_addr
, size
);
2773 do_fp_st(s
, rt
, clean_addr
, size
);
2775 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2777 do_fp_ld(s
, rt2
, clean_addr
, size
);
2779 do_fp_st(s
, rt2
, clean_addr
, size
);
2782 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2783 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2786 TCGv_i64 tmp
= tcg_temp_new_i64();
2788 /* Do not modify tcg_rt before recognizing any exception
2789 * from the second load.
2791 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2792 false, 0, false, false);
2793 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2794 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2795 false, 0, false, false);
2797 tcg_gen_mov_i64(tcg_rt
, tmp
);
2798 tcg_temp_free_i64(tmp
);
2800 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2801 false, 0, false, false);
2802 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2803 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2804 false, 0, false, false);
2810 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2812 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2817 * Load/store (immediate post-indexed)
2818 * Load/store (immediate pre-indexed)
2819 * Load/store (unscaled immediate)
2821 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2822 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2823 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2824 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2826 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2828 * V = 0 -> non-vector
2829 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2830 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2832 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2838 int rn
= extract32(insn
, 5, 5);
2839 int imm9
= sextract32(insn
, 12, 9);
2840 int idx
= extract32(insn
, 10, 2);
2841 bool is_signed
= false;
2842 bool is_store
= false;
2843 bool is_extended
= false;
2844 bool is_unpriv
= (idx
== 2);
2845 bool iss_valid
= !is_vector
;
2849 TCGv_i64 clean_addr
, dirty_addr
;
2852 size
|= (opc
& 2) << 1;
2853 if (size
> 4 || is_unpriv
) {
2854 unallocated_encoding(s
);
2857 is_store
= ((opc
& 1) == 0);
2858 if (!fp_access_check(s
)) {
2862 if (size
== 3 && opc
== 2) {
2863 /* PRFM - prefetch */
2865 unallocated_encoding(s
);
2870 if (opc
== 3 && size
> 1) {
2871 unallocated_encoding(s
);
2874 is_store
= (opc
== 0);
2875 is_signed
= extract32(opc
, 1, 1);
2876 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2894 g_assert_not_reached();
2898 gen_check_sp_alignment(s
);
2901 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2903 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2905 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2909 do_fp_st(s
, rt
, clean_addr
, size
);
2911 do_fp_ld(s
, rt
, clean_addr
, size
);
2914 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2915 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2916 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2919 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2920 iss_valid
, rt
, iss_sf
, false);
2922 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2923 is_signed
, is_extended
, memidx
,
2924 iss_valid
, rt
, iss_sf
, false);
2929 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2931 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2933 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2938 * Load/store (register offset)
2940 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2941 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2942 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2943 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2946 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2947 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2949 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2950 * opc<0>: 0 -> store, 1 -> load
2951 * V: 1 -> vector/simd
2952 * opt: extend encoding (see DecodeRegExtend)
2953 * S: if S=1 then scale (essentially index by sizeof(size))
2954 * Rt: register to transfer into/out of
2955 * Rn: address register or SP for base
2956 * Rm: offset register or ZR for offset
2958 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2964 int rn
= extract32(insn
, 5, 5);
2965 int shift
= extract32(insn
, 12, 1);
2966 int rm
= extract32(insn
, 16, 5);
2967 int opt
= extract32(insn
, 13, 3);
2968 bool is_signed
= false;
2969 bool is_store
= false;
2970 bool is_extended
= false;
2972 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2974 if (extract32(opt
, 1, 1) == 0) {
2975 unallocated_encoding(s
);
2980 size
|= (opc
& 2) << 1;
2982 unallocated_encoding(s
);
2985 is_store
= !extract32(opc
, 0, 1);
2986 if (!fp_access_check(s
)) {
2990 if (size
== 3 && opc
== 2) {
2991 /* PRFM - prefetch */
2994 if (opc
== 3 && size
> 1) {
2995 unallocated_encoding(s
);
2998 is_store
= (opc
== 0);
2999 is_signed
= extract32(opc
, 1, 1);
3000 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3004 gen_check_sp_alignment(s
);
3006 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3008 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3009 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3011 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3012 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3016 do_fp_st(s
, rt
, clean_addr
, size
);
3018 do_fp_ld(s
, rt
, clean_addr
, size
);
3021 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3022 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3024 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3025 true, rt
, iss_sf
, false);
3027 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3028 is_signed
, is_extended
,
3029 true, rt
, iss_sf
, false);
3035 * Load/store (unsigned immediate)
3037 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3038 * +----+-------+---+-----+-----+------------+-------+------+
3039 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3040 * +----+-------+---+-----+-----+------------+-------+------+
3043 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3044 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3046 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3047 * opc<0>: 0 -> store, 1 -> load
3048 * Rn: base address register (inc SP)
3049 * Rt: target register
3051 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3057 int rn
= extract32(insn
, 5, 5);
3058 unsigned int imm12
= extract32(insn
, 10, 12);
3059 unsigned int offset
;
3061 TCGv_i64 clean_addr
, dirty_addr
;
3064 bool is_signed
= false;
3065 bool is_extended
= false;
3068 size
|= (opc
& 2) << 1;
3070 unallocated_encoding(s
);
3073 is_store
= !extract32(opc
, 0, 1);
3074 if (!fp_access_check(s
)) {
3078 if (size
== 3 && opc
== 2) {
3079 /* PRFM - prefetch */
3082 if (opc
== 3 && size
> 1) {
3083 unallocated_encoding(s
);
3086 is_store
= (opc
== 0);
3087 is_signed
= extract32(opc
, 1, 1);
3088 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3092 gen_check_sp_alignment(s
);
3094 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3095 offset
= imm12
<< size
;
3096 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3097 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3101 do_fp_st(s
, rt
, clean_addr
, size
);
3103 do_fp_ld(s
, rt
, clean_addr
, size
);
3106 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3107 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3109 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3110 true, rt
, iss_sf
, false);
3112 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3113 true, rt
, iss_sf
, false);
3118 /* Atomic memory operations
3120 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3121 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3122 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3123 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3125 * Rt: the result register
3126 * Rn: base address or SP
3127 * Rs: the source register for the operation
3128 * V: vector flag (always 0 as of v8.3)
3132 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3133 int size
, int rt
, bool is_vector
)
3135 int rs
= extract32(insn
, 16, 5);
3136 int rn
= extract32(insn
, 5, 5);
3137 int o3_opc
= extract32(insn
, 12, 4);
3138 bool r
= extract32(insn
, 22, 1);
3139 bool a
= extract32(insn
, 23, 1);
3140 TCGv_i64 tcg_rs
, clean_addr
;
3141 AtomicThreeOpFn
*fn
;
3143 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3144 unallocated_encoding(s
);
3148 case 000: /* LDADD */
3149 fn
= tcg_gen_atomic_fetch_add_i64
;
3151 case 001: /* LDCLR */
3152 fn
= tcg_gen_atomic_fetch_and_i64
;
3154 case 002: /* LDEOR */
3155 fn
= tcg_gen_atomic_fetch_xor_i64
;
3157 case 003: /* LDSET */
3158 fn
= tcg_gen_atomic_fetch_or_i64
;
3160 case 004: /* LDSMAX */
3161 fn
= tcg_gen_atomic_fetch_smax_i64
;
3163 case 005: /* LDSMIN */
3164 fn
= tcg_gen_atomic_fetch_smin_i64
;
3166 case 006: /* LDUMAX */
3167 fn
= tcg_gen_atomic_fetch_umax_i64
;
3169 case 007: /* LDUMIN */
3170 fn
= tcg_gen_atomic_fetch_umin_i64
;
3173 fn
= tcg_gen_atomic_xchg_i64
;
3175 case 014: /* LDAPR, LDAPRH, LDAPRB */
3176 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3177 rs
!= 31 || a
!= 1 || r
!= 0) {
3178 unallocated_encoding(s
);
3183 unallocated_encoding(s
);
3188 gen_check_sp_alignment(s
);
3190 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3192 if (o3_opc
== 014) {
3194 * LDAPR* are a special case because they are a simple load, not a
3195 * fetch-and-do-something op.
3196 * The architectural consistency requirements here are weaker than
3197 * full load-acquire (we only need "load-acquire processor consistent"),
3198 * but we choose to implement them as full LDAQ.
3200 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3201 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3202 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3206 tcg_rs
= read_cpu_reg(s
, rs
, true);
3208 if (o3_opc
== 1) { /* LDCLR */
3209 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3212 /* The tcg atomic primitives are all full barriers. Therefore we
3213 * can ignore the Acquire and Release bits of this instruction.
3215 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3216 s
->be_data
| size
| MO_ALIGN
);
3220 * PAC memory operations
3222 * 31 30 27 26 24 22 21 12 11 10 5 0
3223 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3224 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3225 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3227 * Rt: the result register
3228 * Rn: base address or SP
3229 * V: vector flag (always 0 as of v8.3)
3230 * M: clear for key DA, set for key DB
3231 * W: pre-indexing flag
3234 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3235 int size
, int rt
, bool is_vector
)
3237 int rn
= extract32(insn
, 5, 5);
3238 bool is_wback
= extract32(insn
, 11, 1);
3239 bool use_key_a
= !extract32(insn
, 23, 1);
3241 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3243 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3244 unallocated_encoding(s
);
3249 gen_check_sp_alignment(s
);
3251 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3253 if (s
->pauth_active
) {
3255 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3257 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3261 /* Form the 10-bit signed, scaled offset. */
3262 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3263 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3264 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3266 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3267 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3269 tcg_rt
= cpu_reg(s
, rt
);
3270 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3271 /* extend */ false, /* iss_valid */ !is_wback
,
3272 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3275 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3280 * LDAPR/STLR (unscaled immediate)
3282 * 31 30 24 22 21 12 10 5 0
3283 * +------+-------------+-----+---+--------+-----+----+-----+
3284 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3285 * +------+-------------+-----+---+--------+-----+----+-----+
3287 * Rt: source or destination register
3289 * imm9: unscaled immediate offset
3290 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3291 * size: size of load/store
3293 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3295 int rt
= extract32(insn
, 0, 5);
3296 int rn
= extract32(insn
, 5, 5);
3297 int offset
= sextract32(insn
, 12, 9);
3298 int opc
= extract32(insn
, 22, 2);
3299 int size
= extract32(insn
, 30, 2);
3300 TCGv_i64 clean_addr
, dirty_addr
;
3301 bool is_store
= false;
3302 bool is_signed
= false;
3303 bool extend
= false;
3306 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3307 unallocated_encoding(s
);
3312 case 0: /* STLURB */
3315 case 1: /* LDAPUR* */
3317 case 2: /* LDAPURS* 64-bit variant */
3319 unallocated_encoding(s
);
3324 case 3: /* LDAPURS* 32-bit variant */
3326 unallocated_encoding(s
);
3330 extend
= true; /* zero-extend 32->64 after signed load */
3333 g_assert_not_reached();
3336 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3339 gen_check_sp_alignment(s
);
3342 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3343 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3344 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3347 /* Store-Release semantics */
3348 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3349 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3352 * Load-AcquirePC semantics; we implement as the slightly more
3353 * restrictive Load-Acquire.
3355 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3356 true, rt
, iss_sf
, true);
3357 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3361 /* Load/store register (all forms) */
3362 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3364 int rt
= extract32(insn
, 0, 5);
3365 int opc
= extract32(insn
, 22, 2);
3366 bool is_vector
= extract32(insn
, 26, 1);
3367 int size
= extract32(insn
, 30, 2);
3369 switch (extract32(insn
, 24, 2)) {
3371 if (extract32(insn
, 21, 1) == 0) {
3372 /* Load/store register (unscaled immediate)
3373 * Load/store immediate pre/post-indexed
3374 * Load/store register unprivileged
3376 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3379 switch (extract32(insn
, 10, 2)) {
3381 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3384 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3387 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3392 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3395 unallocated_encoding(s
);
3398 /* AdvSIMD load/store multiple structures
3400 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3401 * +---+---+---------------+---+-------------+--------+------+------+------+
3402 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3403 * +---+---+---------------+---+-------------+--------+------+------+------+
3405 * AdvSIMD load/store multiple structures (post-indexed)
3407 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3408 * +---+---+---------------+---+---+---------+--------+------+------+------+
3409 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3410 * +---+---+---------------+---+---+---------+--------+------+------+------+
3412 * Rt: first (or only) SIMD&FP register to be transferred
3413 * Rn: base address or SP
3414 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3416 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3418 int rt
= extract32(insn
, 0, 5);
3419 int rn
= extract32(insn
, 5, 5);
3420 int rm
= extract32(insn
, 16, 5);
3421 int size
= extract32(insn
, 10, 2);
3422 int opcode
= extract32(insn
, 12, 4);
3423 bool is_store
= !extract32(insn
, 22, 1);
3424 bool is_postidx
= extract32(insn
, 23, 1);
3425 bool is_q
= extract32(insn
, 30, 1);
3426 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3427 MemOp endian
= s
->be_data
;
3429 int ebytes
; /* bytes per element */
3430 int elements
; /* elements per vector */
3431 int rpt
; /* num iterations */
3432 int selem
; /* structure elements */
3435 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3436 unallocated_encoding(s
);
3440 if (!is_postidx
&& rm
!= 0) {
3441 unallocated_encoding(s
);
3445 /* From the shared decode logic */
3476 unallocated_encoding(s
);
3480 if (size
== 3 && !is_q
&& selem
!= 1) {
3482 unallocated_encoding(s
);
3486 if (!fp_access_check(s
)) {
3491 gen_check_sp_alignment(s
);
3494 /* For our purposes, bytes are always little-endian. */
3499 /* Consecutive little-endian elements from a single register
3500 * can be promoted to a larger little-endian operation.
3502 if (selem
== 1 && endian
== MO_LE
) {
3506 elements
= (is_q
? 16 : 8) / ebytes
;
3508 tcg_rn
= cpu_reg_sp(s
, rn
);
3509 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3510 tcg_ebytes
= tcg_const_i64(ebytes
);
3512 for (r
= 0; r
< rpt
; r
++) {
3514 for (e
= 0; e
< elements
; e
++) {
3516 for (xs
= 0; xs
< selem
; xs
++) {
3517 int tt
= (rt
+ r
+ xs
) % 32;
3519 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3521 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3523 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3527 tcg_temp_free_i64(tcg_ebytes
);
3530 /* For non-quad operations, setting a slice of the low
3531 * 64 bits of the register clears the high 64 bits (in
3532 * the ARM ARM pseudocode this is implicit in the fact
3533 * that 'rval' is a 64 bit wide variable).
3534 * For quad operations, we might still need to zero the
3537 for (r
= 0; r
< rpt
* selem
; r
++) {
3538 int tt
= (rt
+ r
) % 32;
3539 clear_vec_high(s
, is_q
, tt
);
3545 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3547 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3552 /* AdvSIMD load/store single structure
3554 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3555 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3556 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3557 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3559 * AdvSIMD load/store single structure (post-indexed)
3561 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3562 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3563 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3564 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3566 * Rt: first (or only) SIMD&FP register to be transferred
3567 * Rn: base address or SP
3568 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3569 * index = encoded in Q:S:size dependent on size
3571 * lane_size = encoded in R, opc
3572 * transfer width = encoded in opc, S, size
3574 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3576 int rt
= extract32(insn
, 0, 5);
3577 int rn
= extract32(insn
, 5, 5);
3578 int rm
= extract32(insn
, 16, 5);
3579 int size
= extract32(insn
, 10, 2);
3580 int S
= extract32(insn
, 12, 1);
3581 int opc
= extract32(insn
, 13, 3);
3582 int R
= extract32(insn
, 21, 1);
3583 int is_load
= extract32(insn
, 22, 1);
3584 int is_postidx
= extract32(insn
, 23, 1);
3585 int is_q
= extract32(insn
, 30, 1);
3587 int scale
= extract32(opc
, 1, 2);
3588 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3589 bool replicate
= false;
3590 int index
= is_q
<< 3 | S
<< 2 | size
;
3592 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3594 if (extract32(insn
, 31, 1)) {
3595 unallocated_encoding(s
);
3598 if (!is_postidx
&& rm
!= 0) {
3599 unallocated_encoding(s
);
3605 if (!is_load
|| S
) {
3606 unallocated_encoding(s
);
3615 if (extract32(size
, 0, 1)) {
3616 unallocated_encoding(s
);
3622 if (extract32(size
, 1, 1)) {
3623 unallocated_encoding(s
);
3626 if (!extract32(size
, 0, 1)) {
3630 unallocated_encoding(s
);
3638 g_assert_not_reached();
3641 if (!fp_access_check(s
)) {
3645 ebytes
= 1 << scale
;
3648 gen_check_sp_alignment(s
);
3651 tcg_rn
= cpu_reg_sp(s
, rn
);
3652 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3653 tcg_ebytes
= tcg_const_i64(ebytes
);
3655 for (xs
= 0; xs
< selem
; xs
++) {
3657 /* Load and replicate to all elements */
3658 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3660 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3661 get_mem_index(s
), s
->be_data
+ scale
);
3662 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3663 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3665 tcg_temp_free_i64(tcg_tmp
);
3667 /* Load/store one element per register */
3669 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3671 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3674 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3677 tcg_temp_free_i64(tcg_ebytes
);
3681 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3683 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3688 /* Loads and stores */
3689 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3691 switch (extract32(insn
, 24, 6)) {
3692 case 0x08: /* Load/store exclusive */
3693 disas_ldst_excl(s
, insn
);
3695 case 0x18: case 0x1c: /* Load register (literal) */
3696 disas_ld_lit(s
, insn
);
3698 case 0x28: case 0x29:
3699 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3700 disas_ldst_pair(s
, insn
);
3702 case 0x38: case 0x39:
3703 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3704 disas_ldst_reg(s
, insn
);
3706 case 0x0c: /* AdvSIMD load/store multiple structures */
3707 disas_ldst_multiple_struct(s
, insn
);
3709 case 0x0d: /* AdvSIMD load/store single structure */
3710 disas_ldst_single_struct(s
, insn
);
3712 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3713 if (extract32(insn
, 10, 2) != 0 ||
3714 extract32(insn
, 21, 1) != 0) {
3715 unallocated_encoding(s
);
3718 disas_ldst_ldapr_stlr(s
, insn
);
3721 unallocated_encoding(s
);
3726 /* PC-rel. addressing
3727 * 31 30 29 28 24 23 5 4 0
3728 * +----+-------+-----------+-------------------+------+
3729 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3730 * +----+-------+-----------+-------------------+------+
3732 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3734 unsigned int page
, rd
;
3738 page
= extract32(insn
, 31, 1);
3739 /* SignExtend(immhi:immlo) -> offset */
3740 offset
= sextract64(insn
, 5, 19);
3741 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3742 rd
= extract32(insn
, 0, 5);
3746 /* ADRP (page based) */
3751 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3755 * Add/subtract (immediate)
3757 * 31 30 29 28 23 22 21 10 9 5 4 0
3758 * +--+--+--+-------------+--+-------------+-----+-----+
3759 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
3760 * +--+--+--+-------------+--+-------------+-----+-----+
3762 * sf: 0 -> 32bit, 1 -> 64bit
3763 * op: 0 -> add , 1 -> sub
3765 * sh: 1 -> LSL imm by 12
3767 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3769 int rd
= extract32(insn
, 0, 5);
3770 int rn
= extract32(insn
, 5, 5);
3771 uint64_t imm
= extract32(insn
, 10, 12);
3772 bool shift
= extract32(insn
, 22, 1);
3773 bool setflags
= extract32(insn
, 29, 1);
3774 bool sub_op
= extract32(insn
, 30, 1);
3775 bool is_64bit
= extract32(insn
, 31, 1);
3777 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3778 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3779 TCGv_i64 tcg_result
;
3785 tcg_result
= tcg_temp_new_i64();
3788 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3790 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3793 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3795 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3797 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3799 tcg_temp_free_i64(tcg_imm
);
3803 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3805 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3808 tcg_temp_free_i64(tcg_result
);
3811 /* The input should be a value in the bottom e bits (with higher
3812 * bits zero); returns that value replicated into every element
3813 * of size e in a 64 bit integer.
3815 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3825 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3826 static inline uint64_t bitmask64(unsigned int length
)
3828 assert(length
> 0 && length
<= 64);
3829 return ~0ULL >> (64 - length
);
3832 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3833 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3834 * value (ie should cause a guest UNDEF exception), and true if they are
3835 * valid, in which case the decoded bit pattern is written to result.
3837 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3838 unsigned int imms
, unsigned int immr
)
3841 unsigned e
, levels
, s
, r
;
3844 assert(immn
< 2 && imms
< 64 && immr
< 64);
3846 /* The bit patterns we create here are 64 bit patterns which
3847 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3848 * 64 bits each. Each element contains the same value: a run
3849 * of between 1 and e-1 non-zero bits, rotated within the
3850 * element by between 0 and e-1 bits.
3852 * The element size and run length are encoded into immn (1 bit)
3853 * and imms (6 bits) as follows:
3854 * 64 bit elements: immn = 1, imms = <length of run - 1>
3855 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3856 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3857 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3858 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3859 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3860 * Notice that immn = 0, imms = 11111x is the only combination
3861 * not covered by one of the above options; this is reserved.
3862 * Further, <length of run - 1> all-ones is a reserved pattern.
3864 * In all cases the rotation is by immr % e (and immr is 6 bits).
3867 /* First determine the element size */
3868 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3870 /* This is the immn == 0, imms == 0x11111x case */
3880 /* <length of run - 1> mustn't be all-ones. */
3884 /* Create the value of one element: s+1 set bits rotated
3885 * by r within the element (which is e bits wide)...
3887 mask
= bitmask64(s
+ 1);
3889 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3890 mask
&= bitmask64(e
);
3892 /* ...then replicate the element over the whole 64 bit value */
3893 mask
= bitfield_replicate(mask
, e
);
3898 /* Logical (immediate)
3899 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3900 * +----+-----+-------------+---+------+------+------+------+
3901 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3902 * +----+-----+-------------+---+------+------+------+------+
3904 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3906 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3907 TCGv_i64 tcg_rd
, tcg_rn
;
3909 bool is_and
= false;
3911 sf
= extract32(insn
, 31, 1);
3912 opc
= extract32(insn
, 29, 2);
3913 is_n
= extract32(insn
, 22, 1);
3914 immr
= extract32(insn
, 16, 6);
3915 imms
= extract32(insn
, 10, 6);
3916 rn
= extract32(insn
, 5, 5);
3917 rd
= extract32(insn
, 0, 5);
3920 unallocated_encoding(s
);
3924 if (opc
== 0x3) { /* ANDS */
3925 tcg_rd
= cpu_reg(s
, rd
);
3927 tcg_rd
= cpu_reg_sp(s
, rd
);
3929 tcg_rn
= cpu_reg(s
, rn
);
3931 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3932 /* some immediate field values are reserved */
3933 unallocated_encoding(s
);
3938 wmask
&= 0xffffffff;
3942 case 0x3: /* ANDS */
3944 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3948 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3951 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3954 assert(FALSE
); /* must handle all above */
3958 if (!sf
&& !is_and
) {
3959 /* zero extend final result; we know we can skip this for AND
3960 * since the immediate had the high 32 bits clear.
3962 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3965 if (opc
== 3) { /* ANDS */
3966 gen_logic_CC(sf
, tcg_rd
);
3971 * Move wide (immediate)
3973 * 31 30 29 28 23 22 21 20 5 4 0
3974 * +--+-----+-------------+-----+----------------+------+
3975 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3976 * +--+-----+-------------+-----+----------------+------+
3978 * sf: 0 -> 32 bit, 1 -> 64 bit
3979 * opc: 00 -> N, 10 -> Z, 11 -> K
3980 * hw: shift/16 (0,16, and sf only 32, 48)
3982 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3984 int rd
= extract32(insn
, 0, 5);
3985 uint64_t imm
= extract32(insn
, 5, 16);
3986 int sf
= extract32(insn
, 31, 1);
3987 int opc
= extract32(insn
, 29, 2);
3988 int pos
= extract32(insn
, 21, 2) << 4;
3989 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3992 if (!sf
&& (pos
>= 32)) {
3993 unallocated_encoding(s
);
4007 tcg_gen_movi_i64(tcg_rd
, imm
);
4010 tcg_imm
= tcg_const_i64(imm
);
4011 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4012 tcg_temp_free_i64(tcg_imm
);
4014 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4018 unallocated_encoding(s
);
4024 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4025 * +----+-----+-------------+---+------+------+------+------+
4026 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4027 * +----+-----+-------------+---+------+------+------+------+
4029 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4031 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4032 TCGv_i64 tcg_rd
, tcg_tmp
;
4034 sf
= extract32(insn
, 31, 1);
4035 opc
= extract32(insn
, 29, 2);
4036 n
= extract32(insn
, 22, 1);
4037 ri
= extract32(insn
, 16, 6);
4038 si
= extract32(insn
, 10, 6);
4039 rn
= extract32(insn
, 5, 5);
4040 rd
= extract32(insn
, 0, 5);
4041 bitsize
= sf
? 64 : 32;
4043 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4044 unallocated_encoding(s
);
4048 tcg_rd
= cpu_reg(s
, rd
);
4050 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4051 to be smaller than bitsize, we'll never reference data outside the
4052 low 32-bits anyway. */
4053 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4055 /* Recognize simple(r) extractions. */
4057 /* Wd<s-r:0> = Wn<s:r> */
4058 len
= (si
- ri
) + 1;
4059 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4060 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4062 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4063 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4066 /* opc == 1, BFXIL fall through to deposit */
4067 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4070 /* Handle the ri > si case with a deposit
4071 * Wd<32+s-r,32-r> = Wn<s:0>
4074 pos
= (bitsize
- ri
) & (bitsize
- 1);
4077 if (opc
== 0 && len
< ri
) {
4078 /* SBFM: sign extend the destination field from len to fill
4079 the balance of the word. Let the deposit below insert all
4080 of those sign bits. */
4081 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4085 if (opc
== 1) { /* BFM, BFXIL */
4086 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4088 /* SBFM or UBFM: We start with zero, and we haven't modified
4089 any bits outside bitsize, therefore the zero-extension
4090 below is unneeded. */
4091 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4096 if (!sf
) { /* zero extend final result */
4097 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4102 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4103 * +----+------+-------------+---+----+------+--------+------+------+
4104 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4105 * +----+------+-------------+---+----+------+--------+------+------+
4107 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4109 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4111 sf
= extract32(insn
, 31, 1);
4112 n
= extract32(insn
, 22, 1);
4113 rm
= extract32(insn
, 16, 5);
4114 imm
= extract32(insn
, 10, 6);
4115 rn
= extract32(insn
, 5, 5);
4116 rd
= extract32(insn
, 0, 5);
4117 op21
= extract32(insn
, 29, 2);
4118 op0
= extract32(insn
, 21, 1);
4119 bitsize
= sf
? 64 : 32;
4121 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4122 unallocated_encoding(s
);
4124 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4126 tcg_rd
= cpu_reg(s
, rd
);
4128 if (unlikely(imm
== 0)) {
4129 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4130 * so an extract from bit 0 is a special case.
4133 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4135 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4138 tcg_rm
= cpu_reg(s
, rm
);
4139 tcg_rn
= cpu_reg(s
, rn
);
4142 /* Specialization to ROR happens in EXTRACT2. */
4143 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4145 TCGv_i32 t0
= tcg_temp_new_i32();
4147 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4149 tcg_gen_rotri_i32(t0
, t0
, imm
);
4151 TCGv_i32 t1
= tcg_temp_new_i32();
4152 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4153 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4154 tcg_temp_free_i32(t1
);
4156 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4157 tcg_temp_free_i32(t0
);
4163 /* Data processing - immediate */
4164 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4166 switch (extract32(insn
, 23, 6)) {
4167 case 0x20: case 0x21: /* PC-rel. addressing */
4168 disas_pc_rel_adr(s
, insn
);
4170 case 0x22: /* Add/subtract (immediate) */
4171 disas_add_sub_imm(s
, insn
);
4173 case 0x24: /* Logical (immediate) */
4174 disas_logic_imm(s
, insn
);
4176 case 0x25: /* Move wide (immediate) */
4177 disas_movw_imm(s
, insn
);
4179 case 0x26: /* Bitfield */
4180 disas_bitfield(s
, insn
);
4182 case 0x27: /* Extract */
4183 disas_extract(s
, insn
);
4186 unallocated_encoding(s
);
4191 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4192 * Note that it is the caller's responsibility to ensure that the
4193 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4194 * mandated semantics for out of range shifts.
4196 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4197 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4199 switch (shift_type
) {
4200 case A64_SHIFT_TYPE_LSL
:
4201 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4203 case A64_SHIFT_TYPE_LSR
:
4204 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4206 case A64_SHIFT_TYPE_ASR
:
4208 tcg_gen_ext32s_i64(dst
, src
);
4210 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4212 case A64_SHIFT_TYPE_ROR
:
4214 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4217 t0
= tcg_temp_new_i32();
4218 t1
= tcg_temp_new_i32();
4219 tcg_gen_extrl_i64_i32(t0
, src
);
4220 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4221 tcg_gen_rotr_i32(t0
, t0
, t1
);
4222 tcg_gen_extu_i32_i64(dst
, t0
);
4223 tcg_temp_free_i32(t0
);
4224 tcg_temp_free_i32(t1
);
4228 assert(FALSE
); /* all shift types should be handled */
4232 if (!sf
) { /* zero extend final result */
4233 tcg_gen_ext32u_i64(dst
, dst
);
4237 /* Shift a TCGv src by immediate, put result in dst.
4238 * The shift amount must be in range (this should always be true as the
4239 * relevant instructions will UNDEF on bad shift immediates).
4241 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4242 enum a64_shift_type shift_type
, unsigned int shift_i
)
4244 assert(shift_i
< (sf
? 64 : 32));
4247 tcg_gen_mov_i64(dst
, src
);
4249 TCGv_i64 shift_const
;
4251 shift_const
= tcg_const_i64(shift_i
);
4252 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4253 tcg_temp_free_i64(shift_const
);
4257 /* Logical (shifted register)
4258 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4259 * +----+-----+-----------+-------+---+------+--------+------+------+
4260 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4261 * +----+-----+-----------+-------+---+------+--------+------+------+
4263 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4265 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4266 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4268 sf
= extract32(insn
, 31, 1);
4269 opc
= extract32(insn
, 29, 2);
4270 shift_type
= extract32(insn
, 22, 2);
4271 invert
= extract32(insn
, 21, 1);
4272 rm
= extract32(insn
, 16, 5);
4273 shift_amount
= extract32(insn
, 10, 6);
4274 rn
= extract32(insn
, 5, 5);
4275 rd
= extract32(insn
, 0, 5);
4277 if (!sf
&& (shift_amount
& (1 << 5))) {
4278 unallocated_encoding(s
);
4282 tcg_rd
= cpu_reg(s
, rd
);
4284 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4285 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4286 * register-register MOV and MVN, so it is worth special casing.
4288 tcg_rm
= cpu_reg(s
, rm
);
4290 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4292 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4296 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4298 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4304 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4307 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4310 tcg_rn
= cpu_reg(s
, rn
);
4312 switch (opc
| (invert
<< 2)) {
4315 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4318 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4321 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4325 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4328 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4331 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4339 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4343 gen_logic_CC(sf
, tcg_rd
);
4348 * Add/subtract (extended register)
4350 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4351 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4352 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4353 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4355 * sf: 0 -> 32bit, 1 -> 64bit
4356 * op: 0 -> add , 1 -> sub
4359 * option: extension type (see DecodeRegExtend)
4360 * imm3: optional shift to Rm
4362 * Rd = Rn + LSL(extend(Rm), amount)
4364 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4366 int rd
= extract32(insn
, 0, 5);
4367 int rn
= extract32(insn
, 5, 5);
4368 int imm3
= extract32(insn
, 10, 3);
4369 int option
= extract32(insn
, 13, 3);
4370 int rm
= extract32(insn
, 16, 5);
4371 int opt
= extract32(insn
, 22, 2);
4372 bool setflags
= extract32(insn
, 29, 1);
4373 bool sub_op
= extract32(insn
, 30, 1);
4374 bool sf
= extract32(insn
, 31, 1);
4376 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4378 TCGv_i64 tcg_result
;
4380 if (imm3
> 4 || opt
!= 0) {
4381 unallocated_encoding(s
);
4385 /* non-flag setting ops may use SP */
4387 tcg_rd
= cpu_reg_sp(s
, rd
);
4389 tcg_rd
= cpu_reg(s
, rd
);
4391 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4393 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4394 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4396 tcg_result
= tcg_temp_new_i64();
4400 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4402 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4406 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4408 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4413 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4415 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4418 tcg_temp_free_i64(tcg_result
);
4422 * Add/subtract (shifted register)
4424 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4425 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4426 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4427 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4429 * sf: 0 -> 32bit, 1 -> 64bit
4430 * op: 0 -> add , 1 -> sub
4432 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4433 * imm6: Shift amount to apply to Rm before the add/sub
4435 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4437 int rd
= extract32(insn
, 0, 5);
4438 int rn
= extract32(insn
, 5, 5);
4439 int imm6
= extract32(insn
, 10, 6);
4440 int rm
= extract32(insn
, 16, 5);
4441 int shift_type
= extract32(insn
, 22, 2);
4442 bool setflags
= extract32(insn
, 29, 1);
4443 bool sub_op
= extract32(insn
, 30, 1);
4444 bool sf
= extract32(insn
, 31, 1);
4446 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4447 TCGv_i64 tcg_rn
, tcg_rm
;
4448 TCGv_i64 tcg_result
;
4450 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4451 unallocated_encoding(s
);
4455 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4456 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4458 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4460 tcg_result
= tcg_temp_new_i64();
4464 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4466 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4470 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4472 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4477 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4479 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4482 tcg_temp_free_i64(tcg_result
);
4485 /* Data-processing (3 source)
4487 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4488 * +--+------+-----------+------+------+----+------+------+------+
4489 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4490 * +--+------+-----------+------+------+----+------+------+------+
4492 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4494 int rd
= extract32(insn
, 0, 5);
4495 int rn
= extract32(insn
, 5, 5);
4496 int ra
= extract32(insn
, 10, 5);
4497 int rm
= extract32(insn
, 16, 5);
4498 int op_id
= (extract32(insn
, 29, 3) << 4) |
4499 (extract32(insn
, 21, 3) << 1) |
4500 extract32(insn
, 15, 1);
4501 bool sf
= extract32(insn
, 31, 1);
4502 bool is_sub
= extract32(op_id
, 0, 1);
4503 bool is_high
= extract32(op_id
, 2, 1);
4504 bool is_signed
= false;
4509 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4511 case 0x42: /* SMADDL */
4512 case 0x43: /* SMSUBL */
4513 case 0x44: /* SMULH */
4516 case 0x0: /* MADD (32bit) */
4517 case 0x1: /* MSUB (32bit) */
4518 case 0x40: /* MADD (64bit) */
4519 case 0x41: /* MSUB (64bit) */
4520 case 0x4a: /* UMADDL */
4521 case 0x4b: /* UMSUBL */
4522 case 0x4c: /* UMULH */
4525 unallocated_encoding(s
);
4530 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4531 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4532 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4533 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4536 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4538 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4541 tcg_temp_free_i64(low_bits
);
4545 tcg_op1
= tcg_temp_new_i64();
4546 tcg_op2
= tcg_temp_new_i64();
4547 tcg_tmp
= tcg_temp_new_i64();
4550 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4551 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4554 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4555 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4557 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4558 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4562 if (ra
== 31 && !is_sub
) {
4563 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4564 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4566 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4568 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4570 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4575 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4578 tcg_temp_free_i64(tcg_op1
);
4579 tcg_temp_free_i64(tcg_op2
);
4580 tcg_temp_free_i64(tcg_tmp
);
4583 /* Add/subtract (with carry)
4584 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4585 * +--+--+--+------------------------+------+-------------+------+-----+
4586 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4587 * +--+--+--+------------------------+------+-------------+------+-----+
4590 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4592 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4593 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4595 sf
= extract32(insn
, 31, 1);
4596 op
= extract32(insn
, 30, 1);
4597 setflags
= extract32(insn
, 29, 1);
4598 rm
= extract32(insn
, 16, 5);
4599 rn
= extract32(insn
, 5, 5);
4600 rd
= extract32(insn
, 0, 5);
4602 tcg_rd
= cpu_reg(s
, rd
);
4603 tcg_rn
= cpu_reg(s
, rn
);
4606 tcg_y
= new_tmp_a64(s
);
4607 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4609 tcg_y
= cpu_reg(s
, rm
);
4613 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4615 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4620 * Rotate right into flags
4621 * 31 30 29 21 15 10 5 4 0
4622 * +--+--+--+-----------------+--------+-----------+------+--+------+
4623 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4624 * +--+--+--+-----------------+--------+-----------+------+--+------+
4626 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4628 int mask
= extract32(insn
, 0, 4);
4629 int o2
= extract32(insn
, 4, 1);
4630 int rn
= extract32(insn
, 5, 5);
4631 int imm6
= extract32(insn
, 15, 6);
4632 int sf_op_s
= extract32(insn
, 29, 3);
4636 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4637 unallocated_encoding(s
);
4641 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4642 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4644 nzcv
= tcg_temp_new_i32();
4645 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4647 if (mask
& 8) { /* N */
4648 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4650 if (mask
& 4) { /* Z */
4651 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4652 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4654 if (mask
& 2) { /* C */
4655 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4657 if (mask
& 1) { /* V */
4658 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4661 tcg_temp_free_i32(nzcv
);
4665 * Evaluate into flags
4666 * 31 30 29 21 15 14 10 5 4 0
4667 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4668 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4669 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4671 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4673 int o3_mask
= extract32(insn
, 0, 5);
4674 int rn
= extract32(insn
, 5, 5);
4675 int o2
= extract32(insn
, 15, 6);
4676 int sz
= extract32(insn
, 14, 1);
4677 int sf_op_s
= extract32(insn
, 29, 3);
4681 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4682 !dc_isar_feature(aa64_condm_4
, s
)) {
4683 unallocated_encoding(s
);
4686 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4688 tmp
= tcg_temp_new_i32();
4689 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4690 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4691 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4692 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4693 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4694 tcg_temp_free_i32(tmp
);
4697 /* Conditional compare (immediate / register)
4698 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4699 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4700 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4701 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4704 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4706 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4707 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4708 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4711 if (!extract32(insn
, 29, 1)) {
4712 unallocated_encoding(s
);
4715 if (insn
& (1 << 10 | 1 << 4)) {
4716 unallocated_encoding(s
);
4719 sf
= extract32(insn
, 31, 1);
4720 op
= extract32(insn
, 30, 1);
4721 is_imm
= extract32(insn
, 11, 1);
4722 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4723 cond
= extract32(insn
, 12, 4);
4724 rn
= extract32(insn
, 5, 5);
4725 nzcv
= extract32(insn
, 0, 4);
4727 /* Set T0 = !COND. */
4728 tcg_t0
= tcg_temp_new_i32();
4729 arm_test_cc(&c
, cond
);
4730 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4733 /* Load the arguments for the new comparison. */
4735 tcg_y
= new_tmp_a64(s
);
4736 tcg_gen_movi_i64(tcg_y
, y
);
4738 tcg_y
= cpu_reg(s
, y
);
4740 tcg_rn
= cpu_reg(s
, rn
);
4742 /* Set the flags for the new comparison. */
4743 tcg_tmp
= tcg_temp_new_i64();
4745 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4747 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4749 tcg_temp_free_i64(tcg_tmp
);
4751 /* If COND was false, force the flags to #nzcv. Compute two masks
4752 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4753 * For tcg hosts that support ANDC, we can make do with just T1.
4754 * In either case, allow the tcg optimizer to delete any unused mask.
4756 tcg_t1
= tcg_temp_new_i32();
4757 tcg_t2
= tcg_temp_new_i32();
4758 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4759 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4761 if (nzcv
& 8) { /* N */
4762 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4764 if (TCG_TARGET_HAS_andc_i32
) {
4765 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4767 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4770 if (nzcv
& 4) { /* Z */
4771 if (TCG_TARGET_HAS_andc_i32
) {
4772 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4774 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4777 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4779 if (nzcv
& 2) { /* C */
4780 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4782 if (TCG_TARGET_HAS_andc_i32
) {
4783 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4785 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4788 if (nzcv
& 1) { /* V */
4789 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4791 if (TCG_TARGET_HAS_andc_i32
) {
4792 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4794 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4797 tcg_temp_free_i32(tcg_t0
);
4798 tcg_temp_free_i32(tcg_t1
);
4799 tcg_temp_free_i32(tcg_t2
);
4802 /* Conditional select
4803 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4804 * +----+----+---+-----------------+------+------+-----+------+------+
4805 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4806 * +----+----+---+-----------------+------+------+-----+------+------+
4808 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4810 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4811 TCGv_i64 tcg_rd
, zero
;
4814 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4815 /* S == 1 or op2<1> == 1 */
4816 unallocated_encoding(s
);
4819 sf
= extract32(insn
, 31, 1);
4820 else_inv
= extract32(insn
, 30, 1);
4821 rm
= extract32(insn
, 16, 5);
4822 cond
= extract32(insn
, 12, 4);
4823 else_inc
= extract32(insn
, 10, 1);
4824 rn
= extract32(insn
, 5, 5);
4825 rd
= extract32(insn
, 0, 5);
4827 tcg_rd
= cpu_reg(s
, rd
);
4829 a64_test_cc(&c
, cond
);
4830 zero
= tcg_const_i64(0);
4832 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4834 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4836 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4839 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4840 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4841 if (else_inv
&& else_inc
) {
4842 tcg_gen_neg_i64(t_false
, t_false
);
4843 } else if (else_inv
) {
4844 tcg_gen_not_i64(t_false
, t_false
);
4845 } else if (else_inc
) {
4846 tcg_gen_addi_i64(t_false
, t_false
, 1);
4848 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4851 tcg_temp_free_i64(zero
);
4855 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4859 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4860 unsigned int rn
, unsigned int rd
)
4862 TCGv_i64 tcg_rd
, tcg_rn
;
4863 tcg_rd
= cpu_reg(s
, rd
);
4864 tcg_rn
= cpu_reg(s
, rn
);
4867 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4869 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4870 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4871 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4872 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4873 tcg_temp_free_i32(tcg_tmp32
);
4877 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4878 unsigned int rn
, unsigned int rd
)
4880 TCGv_i64 tcg_rd
, tcg_rn
;
4881 tcg_rd
= cpu_reg(s
, rd
);
4882 tcg_rn
= cpu_reg(s
, rn
);
4885 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4887 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4888 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4889 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4890 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4891 tcg_temp_free_i32(tcg_tmp32
);
4895 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4896 unsigned int rn
, unsigned int rd
)
4898 TCGv_i64 tcg_rd
, tcg_rn
;
4899 tcg_rd
= cpu_reg(s
, rd
);
4900 tcg_rn
= cpu_reg(s
, rn
);
4903 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4905 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4906 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4907 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4908 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4909 tcg_temp_free_i32(tcg_tmp32
);
4913 /* REV with sf==1, opcode==3 ("REV64") */
4914 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4915 unsigned int rn
, unsigned int rd
)
4918 unallocated_encoding(s
);
4921 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4924 /* REV with sf==0, opcode==2
4925 * REV32 (sf==1, opcode==2)
4927 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4928 unsigned int rn
, unsigned int rd
)
4930 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4933 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4934 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4936 /* bswap32_i64 requires zero high word */
4937 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4938 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4939 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4940 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4941 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4943 tcg_temp_free_i64(tcg_tmp
);
4945 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4946 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4950 /* REV16 (opcode==1) */
4951 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4952 unsigned int rn
, unsigned int rd
)
4954 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4955 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4956 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4957 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4959 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4960 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4961 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4962 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4963 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4965 tcg_temp_free_i64(mask
);
4966 tcg_temp_free_i64(tcg_tmp
);
4969 /* Data-processing (1 source)
4970 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4971 * +----+---+---+-----------------+---------+--------+------+------+
4972 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4973 * +----+---+---+-----------------+---------+--------+------+------+
4975 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4977 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4980 if (extract32(insn
, 29, 1)) {
4981 unallocated_encoding(s
);
4985 sf
= extract32(insn
, 31, 1);
4986 opcode
= extract32(insn
, 10, 6);
4987 opcode2
= extract32(insn
, 16, 5);
4988 rn
= extract32(insn
, 5, 5);
4989 rd
= extract32(insn
, 0, 5);
4991 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4993 switch (MAP(sf
, opcode2
, opcode
)) {
4994 case MAP(0, 0x00, 0x00): /* RBIT */
4995 case MAP(1, 0x00, 0x00):
4996 handle_rbit(s
, sf
, rn
, rd
);
4998 case MAP(0, 0x00, 0x01): /* REV16 */
4999 case MAP(1, 0x00, 0x01):
5000 handle_rev16(s
, sf
, rn
, rd
);
5002 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5003 case MAP(1, 0x00, 0x02):
5004 handle_rev32(s
, sf
, rn
, rd
);
5006 case MAP(1, 0x00, 0x03): /* REV64 */
5007 handle_rev64(s
, sf
, rn
, rd
);
5009 case MAP(0, 0x00, 0x04): /* CLZ */
5010 case MAP(1, 0x00, 0x04):
5011 handle_clz(s
, sf
, rn
, rd
);
5013 case MAP(0, 0x00, 0x05): /* CLS */
5014 case MAP(1, 0x00, 0x05):
5015 handle_cls(s
, sf
, rn
, rd
);
5017 case MAP(1, 0x01, 0x00): /* PACIA */
5018 if (s
->pauth_active
) {
5019 tcg_rd
= cpu_reg(s
, rd
);
5020 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5021 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5022 goto do_unallocated
;
5025 case MAP(1, 0x01, 0x01): /* PACIB */
5026 if (s
->pauth_active
) {
5027 tcg_rd
= cpu_reg(s
, rd
);
5028 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5029 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5030 goto do_unallocated
;
5033 case MAP(1, 0x01, 0x02): /* PACDA */
5034 if (s
->pauth_active
) {
5035 tcg_rd
= cpu_reg(s
, rd
);
5036 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5037 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5038 goto do_unallocated
;
5041 case MAP(1, 0x01, 0x03): /* PACDB */
5042 if (s
->pauth_active
) {
5043 tcg_rd
= cpu_reg(s
, rd
);
5044 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5045 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5046 goto do_unallocated
;
5049 case MAP(1, 0x01, 0x04): /* AUTIA */
5050 if (s
->pauth_active
) {
5051 tcg_rd
= cpu_reg(s
, rd
);
5052 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5053 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5054 goto do_unallocated
;
5057 case MAP(1, 0x01, 0x05): /* AUTIB */
5058 if (s
->pauth_active
) {
5059 tcg_rd
= cpu_reg(s
, rd
);
5060 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5061 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5062 goto do_unallocated
;
5065 case MAP(1, 0x01, 0x06): /* AUTDA */
5066 if (s
->pauth_active
) {
5067 tcg_rd
= cpu_reg(s
, rd
);
5068 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5069 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5070 goto do_unallocated
;
5073 case MAP(1, 0x01, 0x07): /* AUTDB */
5074 if (s
->pauth_active
) {
5075 tcg_rd
= cpu_reg(s
, rd
);
5076 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5077 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5078 goto do_unallocated
;
5081 case MAP(1, 0x01, 0x08): /* PACIZA */
5082 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5083 goto do_unallocated
;
5084 } else if (s
->pauth_active
) {
5085 tcg_rd
= cpu_reg(s
, rd
);
5086 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5089 case MAP(1, 0x01, 0x09): /* PACIZB */
5090 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5091 goto do_unallocated
;
5092 } else if (s
->pauth_active
) {
5093 tcg_rd
= cpu_reg(s
, rd
);
5094 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5097 case MAP(1, 0x01, 0x0a): /* PACDZA */
5098 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5099 goto do_unallocated
;
5100 } else if (s
->pauth_active
) {
5101 tcg_rd
= cpu_reg(s
, rd
);
5102 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5105 case MAP(1, 0x01, 0x0b): /* PACDZB */
5106 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5107 goto do_unallocated
;
5108 } else if (s
->pauth_active
) {
5109 tcg_rd
= cpu_reg(s
, rd
);
5110 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5113 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5114 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5115 goto do_unallocated
;
5116 } else if (s
->pauth_active
) {
5117 tcg_rd
= cpu_reg(s
, rd
);
5118 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5121 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5122 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5123 goto do_unallocated
;
5124 } else if (s
->pauth_active
) {
5125 tcg_rd
= cpu_reg(s
, rd
);
5126 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5129 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5130 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5131 goto do_unallocated
;
5132 } else if (s
->pauth_active
) {
5133 tcg_rd
= cpu_reg(s
, rd
);
5134 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5137 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5138 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5139 goto do_unallocated
;
5140 } else if (s
->pauth_active
) {
5141 tcg_rd
= cpu_reg(s
, rd
);
5142 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5145 case MAP(1, 0x01, 0x10): /* XPACI */
5146 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5147 goto do_unallocated
;
5148 } else if (s
->pauth_active
) {
5149 tcg_rd
= cpu_reg(s
, rd
);
5150 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5153 case MAP(1, 0x01, 0x11): /* XPACD */
5154 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5155 goto do_unallocated
;
5156 } else if (s
->pauth_active
) {
5157 tcg_rd
= cpu_reg(s
, rd
);
5158 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5163 unallocated_encoding(s
);
5170 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5171 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5173 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5174 tcg_rd
= cpu_reg(s
, rd
);
5176 if (!sf
&& is_signed
) {
5177 tcg_n
= new_tmp_a64(s
);
5178 tcg_m
= new_tmp_a64(s
);
5179 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5180 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5182 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5183 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5187 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5189 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5192 if (!sf
) { /* zero extend final result */
5193 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5197 /* LSLV, LSRV, ASRV, RORV */
5198 static void handle_shift_reg(DisasContext
*s
,
5199 enum a64_shift_type shift_type
, unsigned int sf
,
5200 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5202 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5203 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5204 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5206 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5207 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5208 tcg_temp_free_i64(tcg_shift
);
5211 /* CRC32[BHWX], CRC32C[BHWX] */
5212 static void handle_crc32(DisasContext
*s
,
5213 unsigned int sf
, unsigned int sz
, bool crc32c
,
5214 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5216 TCGv_i64 tcg_acc
, tcg_val
;
5219 if (!dc_isar_feature(aa64_crc32
, s
)
5220 || (sf
== 1 && sz
!= 3)
5221 || (sf
== 0 && sz
== 3)) {
5222 unallocated_encoding(s
);
5227 tcg_val
= cpu_reg(s
, rm
);
5241 g_assert_not_reached();
5243 tcg_val
= new_tmp_a64(s
);
5244 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5247 tcg_acc
= cpu_reg(s
, rn
);
5248 tcg_bytes
= tcg_const_i32(1 << sz
);
5251 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5253 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5256 tcg_temp_free_i32(tcg_bytes
);
5259 /* Data-processing (2 source)
5260 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5261 * +----+---+---+-----------------+------+--------+------+------+
5262 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5263 * +----+---+---+-----------------+------+--------+------+------+
5265 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5267 unsigned int sf
, rm
, opcode
, rn
, rd
;
5268 sf
= extract32(insn
, 31, 1);
5269 rm
= extract32(insn
, 16, 5);
5270 opcode
= extract32(insn
, 10, 6);
5271 rn
= extract32(insn
, 5, 5);
5272 rd
= extract32(insn
, 0, 5);
5274 if (extract32(insn
, 29, 1)) {
5275 unallocated_encoding(s
);
5281 handle_div(s
, false, sf
, rm
, rn
, rd
);
5284 handle_div(s
, true, sf
, rm
, rn
, rd
);
5287 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5288 goto do_unallocated
;
5291 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5292 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5294 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5299 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5302 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5305 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5308 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5310 case 12: /* PACGA */
5311 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5312 goto do_unallocated
;
5314 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5315 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5324 case 23: /* CRC32 */
5326 int sz
= extract32(opcode
, 0, 2);
5327 bool crc32c
= extract32(opcode
, 2, 1);
5328 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5333 unallocated_encoding(s
);
5339 * Data processing - register
5340 * 31 30 29 28 25 21 20 16 10 0
5341 * +--+---+--+---+-------+-----+-------+-------+---------+
5342 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5343 * +--+---+--+---+-------+-----+-------+-------+---------+
5345 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5347 int op0
= extract32(insn
, 30, 1);
5348 int op1
= extract32(insn
, 28, 1);
5349 int op2
= extract32(insn
, 21, 4);
5350 int op3
= extract32(insn
, 10, 6);
5355 /* Add/sub (extended register) */
5356 disas_add_sub_ext_reg(s
, insn
);
5358 /* Add/sub (shifted register) */
5359 disas_add_sub_reg(s
, insn
);
5362 /* Logical (shifted register) */
5363 disas_logic_reg(s
, insn
);
5371 case 0x00: /* Add/subtract (with carry) */
5372 disas_adc_sbc(s
, insn
);
5375 case 0x01: /* Rotate right into flags */
5377 disas_rotate_right_into_flags(s
, insn
);
5380 case 0x02: /* Evaluate into flags */
5384 disas_evaluate_into_flags(s
, insn
);
5388 goto do_unallocated
;
5392 case 0x2: /* Conditional compare */
5393 disas_cc(s
, insn
); /* both imm and reg forms */
5396 case 0x4: /* Conditional select */
5397 disas_cond_select(s
, insn
);
5400 case 0x6: /* Data-processing */
5401 if (op0
) { /* (1 source) */
5402 disas_data_proc_1src(s
, insn
);
5403 } else { /* (2 source) */
5404 disas_data_proc_2src(s
, insn
);
5407 case 0x8 ... 0xf: /* (3 source) */
5408 disas_data_proc_3src(s
, insn
);
5413 unallocated_encoding(s
);
5418 static void handle_fp_compare(DisasContext
*s
, int size
,
5419 unsigned int rn
, unsigned int rm
,
5420 bool cmp_with_zero
, bool signal_all_nans
)
5422 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5423 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5425 if (size
== MO_64
) {
5426 TCGv_i64 tcg_vn
, tcg_vm
;
5428 tcg_vn
= read_fp_dreg(s
, rn
);
5429 if (cmp_with_zero
) {
5430 tcg_vm
= tcg_const_i64(0);
5432 tcg_vm
= read_fp_dreg(s
, rm
);
5434 if (signal_all_nans
) {
5435 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5437 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5439 tcg_temp_free_i64(tcg_vn
);
5440 tcg_temp_free_i64(tcg_vm
);
5442 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5443 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5445 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5446 if (cmp_with_zero
) {
5447 tcg_gen_movi_i32(tcg_vm
, 0);
5449 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5454 if (signal_all_nans
) {
5455 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5457 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5461 if (signal_all_nans
) {
5462 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5464 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5468 g_assert_not_reached();
5471 tcg_temp_free_i32(tcg_vn
);
5472 tcg_temp_free_i32(tcg_vm
);
5475 tcg_temp_free_ptr(fpst
);
5477 gen_set_nzcv(tcg_flags
);
5479 tcg_temp_free_i64(tcg_flags
);
5482 /* Floating point compare
5483 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5484 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5485 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5486 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5488 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5490 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5493 mos
= extract32(insn
, 29, 3);
5494 type
= extract32(insn
, 22, 2);
5495 rm
= extract32(insn
, 16, 5);
5496 op
= extract32(insn
, 14, 2);
5497 rn
= extract32(insn
, 5, 5);
5498 opc
= extract32(insn
, 3, 2);
5499 op2r
= extract32(insn
, 0, 3);
5501 if (mos
|| op
|| op2r
) {
5502 unallocated_encoding(s
);
5515 if (dc_isar_feature(aa64_fp16
, s
)) {
5520 unallocated_encoding(s
);
5524 if (!fp_access_check(s
)) {
5528 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5531 /* Floating point conditional compare
5532 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5533 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5534 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5535 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5537 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5539 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5541 TCGLabel
*label_continue
= NULL
;
5544 mos
= extract32(insn
, 29, 3);
5545 type
= extract32(insn
, 22, 2);
5546 rm
= extract32(insn
, 16, 5);
5547 cond
= extract32(insn
, 12, 4);
5548 rn
= extract32(insn
, 5, 5);
5549 op
= extract32(insn
, 4, 1);
5550 nzcv
= extract32(insn
, 0, 4);
5553 unallocated_encoding(s
);
5566 if (dc_isar_feature(aa64_fp16
, s
)) {
5571 unallocated_encoding(s
);
5575 if (!fp_access_check(s
)) {
5579 if (cond
< 0x0e) { /* not always */
5580 TCGLabel
*label_match
= gen_new_label();
5581 label_continue
= gen_new_label();
5582 arm_gen_test_cc(cond
, label_match
);
5584 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5585 gen_set_nzcv(tcg_flags
);
5586 tcg_temp_free_i64(tcg_flags
);
5587 tcg_gen_br(label_continue
);
5588 gen_set_label(label_match
);
5591 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5594 gen_set_label(label_continue
);
5598 /* Floating point conditional select
5599 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5600 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5601 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5602 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5604 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5606 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5607 TCGv_i64 t_true
, t_false
, t_zero
;
5611 mos
= extract32(insn
, 29, 3);
5612 type
= extract32(insn
, 22, 2);
5613 rm
= extract32(insn
, 16, 5);
5614 cond
= extract32(insn
, 12, 4);
5615 rn
= extract32(insn
, 5, 5);
5616 rd
= extract32(insn
, 0, 5);
5619 unallocated_encoding(s
);
5632 if (dc_isar_feature(aa64_fp16
, s
)) {
5637 unallocated_encoding(s
);
5641 if (!fp_access_check(s
)) {
5645 /* Zero extend sreg & hreg inputs to 64 bits now. */
5646 t_true
= tcg_temp_new_i64();
5647 t_false
= tcg_temp_new_i64();
5648 read_vec_element(s
, t_true
, rn
, 0, sz
);
5649 read_vec_element(s
, t_false
, rm
, 0, sz
);
5651 a64_test_cc(&c
, cond
);
5652 t_zero
= tcg_const_i64(0);
5653 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5654 tcg_temp_free_i64(t_zero
);
5655 tcg_temp_free_i64(t_false
);
5658 /* Note that sregs & hregs write back zeros to the high bits,
5659 and we've already done the zero-extension. */
5660 write_fp_dreg(s
, rd
, t_true
);
5661 tcg_temp_free_i64(t_true
);
5664 /* Floating-point data-processing (1 source) - half precision */
5665 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5667 TCGv_ptr fpst
= NULL
;
5668 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5669 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5672 case 0x0: /* FMOV */
5673 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5675 case 0x1: /* FABS */
5676 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5678 case 0x2: /* FNEG */
5679 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5681 case 0x3: /* FSQRT */
5682 fpst
= get_fpstatus_ptr(true);
5683 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5685 case 0x8: /* FRINTN */
5686 case 0x9: /* FRINTP */
5687 case 0xa: /* FRINTM */
5688 case 0xb: /* FRINTZ */
5689 case 0xc: /* FRINTA */
5691 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5692 fpst
= get_fpstatus_ptr(true);
5694 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5695 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5697 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5698 tcg_temp_free_i32(tcg_rmode
);
5701 case 0xe: /* FRINTX */
5702 fpst
= get_fpstatus_ptr(true);
5703 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5705 case 0xf: /* FRINTI */
5706 fpst
= get_fpstatus_ptr(true);
5707 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5713 write_fp_sreg(s
, rd
, tcg_res
);
5716 tcg_temp_free_ptr(fpst
);
5718 tcg_temp_free_i32(tcg_op
);
5719 tcg_temp_free_i32(tcg_res
);
5722 /* Floating-point data-processing (1 source) - single precision */
5723 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5725 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5726 TCGv_i32 tcg_op
, tcg_res
;
5730 tcg_op
= read_fp_sreg(s
, rn
);
5731 tcg_res
= tcg_temp_new_i32();
5734 case 0x0: /* FMOV */
5735 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5737 case 0x1: /* FABS */
5738 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5740 case 0x2: /* FNEG */
5741 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5743 case 0x3: /* FSQRT */
5744 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5746 case 0x8: /* FRINTN */
5747 case 0x9: /* FRINTP */
5748 case 0xa: /* FRINTM */
5749 case 0xb: /* FRINTZ */
5750 case 0xc: /* FRINTA */
5751 rmode
= arm_rmode_to_sf(opcode
& 7);
5752 gen_fpst
= gen_helper_rints
;
5754 case 0xe: /* FRINTX */
5755 gen_fpst
= gen_helper_rints_exact
;
5757 case 0xf: /* FRINTI */
5758 gen_fpst
= gen_helper_rints
;
5760 case 0x10: /* FRINT32Z */
5761 rmode
= float_round_to_zero
;
5762 gen_fpst
= gen_helper_frint32_s
;
5764 case 0x11: /* FRINT32X */
5765 gen_fpst
= gen_helper_frint32_s
;
5767 case 0x12: /* FRINT64Z */
5768 rmode
= float_round_to_zero
;
5769 gen_fpst
= gen_helper_frint64_s
;
5771 case 0x13: /* FRINT64X */
5772 gen_fpst
= gen_helper_frint64_s
;
5775 g_assert_not_reached();
5778 fpst
= get_fpstatus_ptr(false);
5780 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5781 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5782 gen_fpst(tcg_res
, tcg_op
, fpst
);
5783 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5784 tcg_temp_free_i32(tcg_rmode
);
5786 gen_fpst(tcg_res
, tcg_op
, fpst
);
5788 tcg_temp_free_ptr(fpst
);
5791 write_fp_sreg(s
, rd
, tcg_res
);
5792 tcg_temp_free_i32(tcg_op
);
5793 tcg_temp_free_i32(tcg_res
);
5796 /* Floating-point data-processing (1 source) - double precision */
5797 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5799 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5800 TCGv_i64 tcg_op
, tcg_res
;
5805 case 0x0: /* FMOV */
5806 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5810 tcg_op
= read_fp_dreg(s
, rn
);
5811 tcg_res
= tcg_temp_new_i64();
5814 case 0x1: /* FABS */
5815 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5817 case 0x2: /* FNEG */
5818 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5820 case 0x3: /* FSQRT */
5821 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5823 case 0x8: /* FRINTN */
5824 case 0x9: /* FRINTP */
5825 case 0xa: /* FRINTM */
5826 case 0xb: /* FRINTZ */
5827 case 0xc: /* FRINTA */
5828 rmode
= arm_rmode_to_sf(opcode
& 7);
5829 gen_fpst
= gen_helper_rintd
;
5831 case 0xe: /* FRINTX */
5832 gen_fpst
= gen_helper_rintd_exact
;
5834 case 0xf: /* FRINTI */
5835 gen_fpst
= gen_helper_rintd
;
5837 case 0x10: /* FRINT32Z */
5838 rmode
= float_round_to_zero
;
5839 gen_fpst
= gen_helper_frint32_d
;
5841 case 0x11: /* FRINT32X */
5842 gen_fpst
= gen_helper_frint32_d
;
5844 case 0x12: /* FRINT64Z */
5845 rmode
= float_round_to_zero
;
5846 gen_fpst
= gen_helper_frint64_d
;
5848 case 0x13: /* FRINT64X */
5849 gen_fpst
= gen_helper_frint64_d
;
5852 g_assert_not_reached();
5855 fpst
= get_fpstatus_ptr(false);
5857 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5858 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5859 gen_fpst(tcg_res
, tcg_op
, fpst
);
5860 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5861 tcg_temp_free_i32(tcg_rmode
);
5863 gen_fpst(tcg_res
, tcg_op
, fpst
);
5865 tcg_temp_free_ptr(fpst
);
5868 write_fp_dreg(s
, rd
, tcg_res
);
5869 tcg_temp_free_i64(tcg_op
);
5870 tcg_temp_free_i64(tcg_res
);
5873 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5874 int rd
, int rn
, int dtype
, int ntype
)
5879 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5881 /* Single to double */
5882 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5883 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5884 write_fp_dreg(s
, rd
, tcg_rd
);
5885 tcg_temp_free_i64(tcg_rd
);
5887 /* Single to half */
5888 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5889 TCGv_i32 ahp
= get_ahp_flag();
5890 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5892 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5893 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5894 write_fp_sreg(s
, rd
, tcg_rd
);
5895 tcg_temp_free_i32(tcg_rd
);
5896 tcg_temp_free_i32(ahp
);
5897 tcg_temp_free_ptr(fpst
);
5899 tcg_temp_free_i32(tcg_rn
);
5904 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5905 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5907 /* Double to single */
5908 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5910 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5911 TCGv_i32 ahp
= get_ahp_flag();
5912 /* Double to half */
5913 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5914 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5915 tcg_temp_free_ptr(fpst
);
5916 tcg_temp_free_i32(ahp
);
5918 write_fp_sreg(s
, rd
, tcg_rd
);
5919 tcg_temp_free_i32(tcg_rd
);
5920 tcg_temp_free_i64(tcg_rn
);
5925 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5926 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5927 TCGv_i32 tcg_ahp
= get_ahp_flag();
5928 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5930 /* Half to single */
5931 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5932 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5933 write_fp_sreg(s
, rd
, tcg_rd
);
5934 tcg_temp_free_i32(tcg_rd
);
5936 /* Half to double */
5937 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5938 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5939 write_fp_dreg(s
, rd
, tcg_rd
);
5940 tcg_temp_free_i64(tcg_rd
);
5942 tcg_temp_free_i32(tcg_rn
);
5943 tcg_temp_free_ptr(tcg_fpst
);
5944 tcg_temp_free_i32(tcg_ahp
);
5952 /* Floating point data-processing (1 source)
5953 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5954 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5955 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5956 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5958 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5960 int mos
= extract32(insn
, 29, 3);
5961 int type
= extract32(insn
, 22, 2);
5962 int opcode
= extract32(insn
, 15, 6);
5963 int rn
= extract32(insn
, 5, 5);
5964 int rd
= extract32(insn
, 0, 5);
5967 unallocated_encoding(s
);
5972 case 0x4: case 0x5: case 0x7:
5974 /* FCVT between half, single and double precision */
5975 int dtype
= extract32(opcode
, 0, 2);
5976 if (type
== 2 || dtype
== type
) {
5977 unallocated_encoding(s
);
5980 if (!fp_access_check(s
)) {
5984 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5988 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5989 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5990 unallocated_encoding(s
);
5997 /* 32-to-32 and 64-to-64 ops */
6000 if (!fp_access_check(s
)) {
6003 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6006 if (!fp_access_check(s
)) {
6009 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6012 if (!dc_isar_feature(aa64_fp16
, s
)) {
6013 unallocated_encoding(s
);
6017 if (!fp_access_check(s
)) {
6020 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6023 unallocated_encoding(s
);
6028 unallocated_encoding(s
);
6033 /* Floating-point data-processing (2 source) - single precision */
6034 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6035 int rd
, int rn
, int rm
)
6042 tcg_res
= tcg_temp_new_i32();
6043 fpst
= get_fpstatus_ptr(false);
6044 tcg_op1
= read_fp_sreg(s
, rn
);
6045 tcg_op2
= read_fp_sreg(s
, rm
);
6048 case 0x0: /* FMUL */
6049 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6051 case 0x1: /* FDIV */
6052 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6054 case 0x2: /* FADD */
6055 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6057 case 0x3: /* FSUB */
6058 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6060 case 0x4: /* FMAX */
6061 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6063 case 0x5: /* FMIN */
6064 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6066 case 0x6: /* FMAXNM */
6067 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6069 case 0x7: /* FMINNM */
6070 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6072 case 0x8: /* FNMUL */
6073 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6074 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6078 write_fp_sreg(s
, rd
, tcg_res
);
6080 tcg_temp_free_ptr(fpst
);
6081 tcg_temp_free_i32(tcg_op1
);
6082 tcg_temp_free_i32(tcg_op2
);
6083 tcg_temp_free_i32(tcg_res
);
6086 /* Floating-point data-processing (2 source) - double precision */
6087 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6088 int rd
, int rn
, int rm
)
6095 tcg_res
= tcg_temp_new_i64();
6096 fpst
= get_fpstatus_ptr(false);
6097 tcg_op1
= read_fp_dreg(s
, rn
);
6098 tcg_op2
= read_fp_dreg(s
, rm
);
6101 case 0x0: /* FMUL */
6102 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6104 case 0x1: /* FDIV */
6105 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6107 case 0x2: /* FADD */
6108 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6110 case 0x3: /* FSUB */
6111 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6113 case 0x4: /* FMAX */
6114 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6116 case 0x5: /* FMIN */
6117 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6119 case 0x6: /* FMAXNM */
6120 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6122 case 0x7: /* FMINNM */
6123 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6125 case 0x8: /* FNMUL */
6126 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6127 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6131 write_fp_dreg(s
, rd
, tcg_res
);
6133 tcg_temp_free_ptr(fpst
);
6134 tcg_temp_free_i64(tcg_op1
);
6135 tcg_temp_free_i64(tcg_op2
);
6136 tcg_temp_free_i64(tcg_res
);
6139 /* Floating-point data-processing (2 source) - half precision */
6140 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6141 int rd
, int rn
, int rm
)
6148 tcg_res
= tcg_temp_new_i32();
6149 fpst
= get_fpstatus_ptr(true);
6150 tcg_op1
= read_fp_hreg(s
, rn
);
6151 tcg_op2
= read_fp_hreg(s
, rm
);
6154 case 0x0: /* FMUL */
6155 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6157 case 0x1: /* FDIV */
6158 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6160 case 0x2: /* FADD */
6161 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6163 case 0x3: /* FSUB */
6164 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6166 case 0x4: /* FMAX */
6167 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6169 case 0x5: /* FMIN */
6170 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6172 case 0x6: /* FMAXNM */
6173 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6175 case 0x7: /* FMINNM */
6176 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6178 case 0x8: /* FNMUL */
6179 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6180 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6183 g_assert_not_reached();
6186 write_fp_sreg(s
, rd
, tcg_res
);
6188 tcg_temp_free_ptr(fpst
);
6189 tcg_temp_free_i32(tcg_op1
);
6190 tcg_temp_free_i32(tcg_op2
);
6191 tcg_temp_free_i32(tcg_res
);
6194 /* Floating point data-processing (2 source)
6195 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6196 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6197 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6198 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6200 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6202 int mos
= extract32(insn
, 29, 3);
6203 int type
= extract32(insn
, 22, 2);
6204 int rd
= extract32(insn
, 0, 5);
6205 int rn
= extract32(insn
, 5, 5);
6206 int rm
= extract32(insn
, 16, 5);
6207 int opcode
= extract32(insn
, 12, 4);
6209 if (opcode
> 8 || mos
) {
6210 unallocated_encoding(s
);
6216 if (!fp_access_check(s
)) {
6219 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6222 if (!fp_access_check(s
)) {
6225 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6228 if (!dc_isar_feature(aa64_fp16
, s
)) {
6229 unallocated_encoding(s
);
6232 if (!fp_access_check(s
)) {
6235 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6238 unallocated_encoding(s
);
6242 /* Floating-point data-processing (3 source) - single precision */
6243 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6244 int rd
, int rn
, int rm
, int ra
)
6246 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6247 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6248 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6250 tcg_op1
= read_fp_sreg(s
, rn
);
6251 tcg_op2
= read_fp_sreg(s
, rm
);
6252 tcg_op3
= read_fp_sreg(s
, ra
);
6254 /* These are fused multiply-add, and must be done as one
6255 * floating point operation with no rounding between the
6256 * multiplication and addition steps.
6257 * NB that doing the negations here as separate steps is
6258 * correct : an input NaN should come out with its sign bit
6259 * flipped if it is a negated-input.
6262 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6266 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6269 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6271 write_fp_sreg(s
, rd
, tcg_res
);
6273 tcg_temp_free_ptr(fpst
);
6274 tcg_temp_free_i32(tcg_op1
);
6275 tcg_temp_free_i32(tcg_op2
);
6276 tcg_temp_free_i32(tcg_op3
);
6277 tcg_temp_free_i32(tcg_res
);
6280 /* Floating-point data-processing (3 source) - double precision */
6281 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6282 int rd
, int rn
, int rm
, int ra
)
6284 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6285 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6286 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6288 tcg_op1
= read_fp_dreg(s
, rn
);
6289 tcg_op2
= read_fp_dreg(s
, rm
);
6290 tcg_op3
= read_fp_dreg(s
, ra
);
6292 /* These are fused multiply-add, and must be done as one
6293 * floating point operation with no rounding between the
6294 * multiplication and addition steps.
6295 * NB that doing the negations here as separate steps is
6296 * correct : an input NaN should come out with its sign bit
6297 * flipped if it is a negated-input.
6300 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6304 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6307 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6309 write_fp_dreg(s
, rd
, tcg_res
);
6311 tcg_temp_free_ptr(fpst
);
6312 tcg_temp_free_i64(tcg_op1
);
6313 tcg_temp_free_i64(tcg_op2
);
6314 tcg_temp_free_i64(tcg_op3
);
6315 tcg_temp_free_i64(tcg_res
);
6318 /* Floating-point data-processing (3 source) - half precision */
6319 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6320 int rd
, int rn
, int rm
, int ra
)
6322 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6323 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6324 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6326 tcg_op1
= read_fp_hreg(s
, rn
);
6327 tcg_op2
= read_fp_hreg(s
, rm
);
6328 tcg_op3
= read_fp_hreg(s
, ra
);
6330 /* These are fused multiply-add, and must be done as one
6331 * floating point operation with no rounding between the
6332 * multiplication and addition steps.
6333 * NB that doing the negations here as separate steps is
6334 * correct : an input NaN should come out with its sign bit
6335 * flipped if it is a negated-input.
6338 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6342 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6345 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6347 write_fp_sreg(s
, rd
, tcg_res
);
6349 tcg_temp_free_ptr(fpst
);
6350 tcg_temp_free_i32(tcg_op1
);
6351 tcg_temp_free_i32(tcg_op2
);
6352 tcg_temp_free_i32(tcg_op3
);
6353 tcg_temp_free_i32(tcg_res
);
6356 /* Floating point data-processing (3 source)
6357 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6358 * +---+---+---+-----------+------+----+------+----+------+------+------+
6359 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6360 * +---+---+---+-----------+------+----+------+----+------+------+------+
6362 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6364 int mos
= extract32(insn
, 29, 3);
6365 int type
= extract32(insn
, 22, 2);
6366 int rd
= extract32(insn
, 0, 5);
6367 int rn
= extract32(insn
, 5, 5);
6368 int ra
= extract32(insn
, 10, 5);
6369 int rm
= extract32(insn
, 16, 5);
6370 bool o0
= extract32(insn
, 15, 1);
6371 bool o1
= extract32(insn
, 21, 1);
6374 unallocated_encoding(s
);
6380 if (!fp_access_check(s
)) {
6383 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6386 if (!fp_access_check(s
)) {
6389 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6392 if (!dc_isar_feature(aa64_fp16
, s
)) {
6393 unallocated_encoding(s
);
6396 if (!fp_access_check(s
)) {
6399 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6402 unallocated_encoding(s
);
6406 /* Floating point immediate
6407 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6408 * +---+---+---+-----------+------+---+------------+-------+------+------+
6409 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6410 * +---+---+---+-----------+------+---+------------+-------+------+------+
6412 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6414 int rd
= extract32(insn
, 0, 5);
6415 int imm5
= extract32(insn
, 5, 5);
6416 int imm8
= extract32(insn
, 13, 8);
6417 int type
= extract32(insn
, 22, 2);
6418 int mos
= extract32(insn
, 29, 3);
6424 unallocated_encoding(s
);
6437 if (dc_isar_feature(aa64_fp16
, s
)) {
6442 unallocated_encoding(s
);
6446 if (!fp_access_check(s
)) {
6450 imm
= vfp_expand_imm(sz
, imm8
);
6452 tcg_res
= tcg_const_i64(imm
);
6453 write_fp_dreg(s
, rd
, tcg_res
);
6454 tcg_temp_free_i64(tcg_res
);
6457 /* Handle floating point <=> fixed point conversions. Note that we can
6458 * also deal with fp <=> integer conversions as a special case (scale == 64)
6459 * OPTME: consider handling that special case specially or at least skipping
6460 * the call to scalbn in the helpers for zero shifts.
6462 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6463 bool itof
, int rmode
, int scale
, int sf
, int type
)
6465 bool is_signed
= !(opcode
& 1);
6466 TCGv_ptr tcg_fpstatus
;
6467 TCGv_i32 tcg_shift
, tcg_single
;
6468 TCGv_i64 tcg_double
;
6470 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6472 tcg_shift
= tcg_const_i32(64 - scale
);
6475 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6477 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6480 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6482 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6485 tcg_int
= tcg_extend
;
6489 case 1: /* float64 */
6490 tcg_double
= tcg_temp_new_i64();
6492 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6493 tcg_shift
, tcg_fpstatus
);
6495 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6496 tcg_shift
, tcg_fpstatus
);
6498 write_fp_dreg(s
, rd
, tcg_double
);
6499 tcg_temp_free_i64(tcg_double
);
6502 case 0: /* float32 */
6503 tcg_single
= tcg_temp_new_i32();
6505 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6506 tcg_shift
, tcg_fpstatus
);
6508 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6509 tcg_shift
, tcg_fpstatus
);
6511 write_fp_sreg(s
, rd
, tcg_single
);
6512 tcg_temp_free_i32(tcg_single
);
6515 case 3: /* float16 */
6516 tcg_single
= tcg_temp_new_i32();
6518 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6519 tcg_shift
, tcg_fpstatus
);
6521 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6522 tcg_shift
, tcg_fpstatus
);
6524 write_fp_sreg(s
, rd
, tcg_single
);
6525 tcg_temp_free_i32(tcg_single
);
6529 g_assert_not_reached();
6532 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6535 if (extract32(opcode
, 2, 1)) {
6536 /* There are too many rounding modes to all fit into rmode,
6537 * so FCVTA[US] is a special case.
6539 rmode
= FPROUNDING_TIEAWAY
;
6542 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6544 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6547 case 1: /* float64 */
6548 tcg_double
= read_fp_dreg(s
, rn
);
6551 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6552 tcg_shift
, tcg_fpstatus
);
6554 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6555 tcg_shift
, tcg_fpstatus
);
6559 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6560 tcg_shift
, tcg_fpstatus
);
6562 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6563 tcg_shift
, tcg_fpstatus
);
6567 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6569 tcg_temp_free_i64(tcg_double
);
6572 case 0: /* float32 */
6573 tcg_single
= read_fp_sreg(s
, rn
);
6576 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6577 tcg_shift
, tcg_fpstatus
);
6579 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6580 tcg_shift
, tcg_fpstatus
);
6583 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6585 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6586 tcg_shift
, tcg_fpstatus
);
6588 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6589 tcg_shift
, tcg_fpstatus
);
6591 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6592 tcg_temp_free_i32(tcg_dest
);
6594 tcg_temp_free_i32(tcg_single
);
6597 case 3: /* float16 */
6598 tcg_single
= read_fp_sreg(s
, rn
);
6601 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6602 tcg_shift
, tcg_fpstatus
);
6604 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6605 tcg_shift
, tcg_fpstatus
);
6608 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6610 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6611 tcg_shift
, tcg_fpstatus
);
6613 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6614 tcg_shift
, tcg_fpstatus
);
6616 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6617 tcg_temp_free_i32(tcg_dest
);
6619 tcg_temp_free_i32(tcg_single
);
6623 g_assert_not_reached();
6626 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6627 tcg_temp_free_i32(tcg_rmode
);
6630 tcg_temp_free_ptr(tcg_fpstatus
);
6631 tcg_temp_free_i32(tcg_shift
);
6634 /* Floating point <-> fixed point conversions
6635 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6636 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6637 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6638 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6640 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6642 int rd
= extract32(insn
, 0, 5);
6643 int rn
= extract32(insn
, 5, 5);
6644 int scale
= extract32(insn
, 10, 6);
6645 int opcode
= extract32(insn
, 16, 3);
6646 int rmode
= extract32(insn
, 19, 2);
6647 int type
= extract32(insn
, 22, 2);
6648 bool sbit
= extract32(insn
, 29, 1);
6649 bool sf
= extract32(insn
, 31, 1);
6652 if (sbit
|| (!sf
&& scale
< 32)) {
6653 unallocated_encoding(s
);
6658 case 0: /* float32 */
6659 case 1: /* float64 */
6661 case 3: /* float16 */
6662 if (dc_isar_feature(aa64_fp16
, s
)) {
6667 unallocated_encoding(s
);
6671 switch ((rmode
<< 3) | opcode
) {
6672 case 0x2: /* SCVTF */
6673 case 0x3: /* UCVTF */
6676 case 0x18: /* FCVTZS */
6677 case 0x19: /* FCVTZU */
6681 unallocated_encoding(s
);
6685 if (!fp_access_check(s
)) {
6689 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6692 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6694 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6695 * without conversion.
6699 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6705 tmp
= tcg_temp_new_i64();
6706 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6707 write_fp_dreg(s
, rd
, tmp
);
6708 tcg_temp_free_i64(tmp
);
6712 write_fp_dreg(s
, rd
, tcg_rn
);
6715 /* 64 bit to top half. */
6716 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6717 clear_vec_high(s
, true, rd
);
6721 tmp
= tcg_temp_new_i64();
6722 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6723 write_fp_dreg(s
, rd
, tmp
);
6724 tcg_temp_free_i64(tmp
);
6727 g_assert_not_reached();
6730 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6735 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6739 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6742 /* 64 bits from top half */
6743 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6747 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6750 g_assert_not_reached();
6755 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6757 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6758 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6760 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6762 tcg_temp_free_ptr(fpstatus
);
6764 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6765 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6766 tcg_gen_movi_i32(cpu_CF
, 0);
6767 tcg_gen_movi_i32(cpu_NF
, 0);
6768 tcg_gen_movi_i32(cpu_VF
, 0);
6770 tcg_temp_free_i64(t
);
6773 /* Floating point <-> integer conversions
6774 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6775 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6776 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6777 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6779 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6781 int rd
= extract32(insn
, 0, 5);
6782 int rn
= extract32(insn
, 5, 5);
6783 int opcode
= extract32(insn
, 16, 3);
6784 int rmode
= extract32(insn
, 19, 2);
6785 int type
= extract32(insn
, 22, 2);
6786 bool sbit
= extract32(insn
, 29, 1);
6787 bool sf
= extract32(insn
, 31, 1);
6791 goto do_unallocated
;
6799 case 4: /* FCVTAS */
6800 case 5: /* FCVTAU */
6802 goto do_unallocated
;
6805 case 0: /* FCVT[NPMZ]S */
6806 case 1: /* FCVT[NPMZ]U */
6808 case 0: /* float32 */
6809 case 1: /* float64 */
6811 case 3: /* float16 */
6812 if (!dc_isar_feature(aa64_fp16
, s
)) {
6813 goto do_unallocated
;
6817 goto do_unallocated
;
6819 if (!fp_access_check(s
)) {
6822 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6826 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6827 case 0b01100110: /* FMOV half <-> 32-bit int */
6829 case 0b11100110: /* FMOV half <-> 64-bit int */
6831 if (!dc_isar_feature(aa64_fp16
, s
)) {
6832 goto do_unallocated
;
6835 case 0b00000110: /* FMOV 32-bit */
6837 case 0b10100110: /* FMOV 64-bit */
6839 case 0b11001110: /* FMOV top half of 128-bit */
6841 if (!fp_access_check(s
)) {
6845 handle_fmov(s
, rd
, rn
, type
, itof
);
6848 case 0b00111110: /* FJCVTZS */
6849 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6850 goto do_unallocated
;
6851 } else if (fp_access_check(s
)) {
6852 handle_fjcvtzs(s
, rd
, rn
);
6858 unallocated_encoding(s
);
6865 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6866 * 31 30 29 28 25 24 0
6867 * +---+---+---+---------+-----------------------------+
6868 * | | 0 | | 1 1 1 1 | |
6869 * +---+---+---+---------+-----------------------------+
6871 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6873 if (extract32(insn
, 24, 1)) {
6874 /* Floating point data-processing (3 source) */
6875 disas_fp_3src(s
, insn
);
6876 } else if (extract32(insn
, 21, 1) == 0) {
6877 /* Floating point to fixed point conversions */
6878 disas_fp_fixed_conv(s
, insn
);
6880 switch (extract32(insn
, 10, 2)) {
6882 /* Floating point conditional compare */
6883 disas_fp_ccomp(s
, insn
);
6886 /* Floating point data-processing (2 source) */
6887 disas_fp_2src(s
, insn
);
6890 /* Floating point conditional select */
6891 disas_fp_csel(s
, insn
);
6894 switch (ctz32(extract32(insn
, 12, 4))) {
6895 case 0: /* [15:12] == xxx1 */
6896 /* Floating point immediate */
6897 disas_fp_imm(s
, insn
);
6899 case 1: /* [15:12] == xx10 */
6900 /* Floating point compare */
6901 disas_fp_compare(s
, insn
);
6903 case 2: /* [15:12] == x100 */
6904 /* Floating point data-processing (1 source) */
6905 disas_fp_1src(s
, insn
);
6907 case 3: /* [15:12] == 1000 */
6908 unallocated_encoding(s
);
6910 default: /* [15:12] == 0000 */
6911 /* Floating point <-> integer conversions */
6912 disas_fp_int_conv(s
, insn
);
6920 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6923 /* Extract 64 bits from the middle of two concatenated 64 bit
6924 * vector register slices left:right. The extracted bits start
6925 * at 'pos' bits into the right (least significant) side.
6926 * We return the result in tcg_right, and guarantee not to
6929 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6930 assert(pos
> 0 && pos
< 64);
6932 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6933 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6934 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6936 tcg_temp_free_i64(tcg_tmp
);
6940 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6941 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6942 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6943 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6945 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6947 int is_q
= extract32(insn
, 30, 1);
6948 int op2
= extract32(insn
, 22, 2);
6949 int imm4
= extract32(insn
, 11, 4);
6950 int rm
= extract32(insn
, 16, 5);
6951 int rn
= extract32(insn
, 5, 5);
6952 int rd
= extract32(insn
, 0, 5);
6953 int pos
= imm4
<< 3;
6954 TCGv_i64 tcg_resl
, tcg_resh
;
6956 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6957 unallocated_encoding(s
);
6961 if (!fp_access_check(s
)) {
6965 tcg_resh
= tcg_temp_new_i64();
6966 tcg_resl
= tcg_temp_new_i64();
6968 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6969 * either extracting 128 bits from a 128:128 concatenation, or
6970 * extracting 64 bits from a 64:64 concatenation.
6973 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6975 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6976 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6984 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6985 EltPosns
*elt
= eltposns
;
6992 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6994 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6997 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6998 tcg_hh
= tcg_temp_new_i64();
6999 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7000 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7001 tcg_temp_free_i64(tcg_hh
);
7005 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7006 tcg_temp_free_i64(tcg_resl
);
7008 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7010 tcg_temp_free_i64(tcg_resh
);
7011 clear_vec_high(s
, is_q
, rd
);
7015 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7016 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7017 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7018 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7020 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7022 int op2
= extract32(insn
, 22, 2);
7023 int is_q
= extract32(insn
, 30, 1);
7024 int rm
= extract32(insn
, 16, 5);
7025 int rn
= extract32(insn
, 5, 5);
7026 int rd
= extract32(insn
, 0, 5);
7027 int is_tblx
= extract32(insn
, 12, 1);
7028 int len
= extract32(insn
, 13, 2);
7029 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7030 TCGv_i32 tcg_regno
, tcg_numregs
;
7033 unallocated_encoding(s
);
7037 if (!fp_access_check(s
)) {
7041 /* This does a table lookup: for every byte element in the input
7042 * we index into a table formed from up to four vector registers,
7043 * and then the output is the result of the lookups. Our helper
7044 * function does the lookup operation for a single 64 bit part of
7047 tcg_resl
= tcg_temp_new_i64();
7051 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7053 tcg_gen_movi_i64(tcg_resl
, 0);
7057 tcg_resh
= tcg_temp_new_i64();
7059 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7061 tcg_gen_movi_i64(tcg_resh
, 0);
7065 tcg_idx
= tcg_temp_new_i64();
7066 tcg_regno
= tcg_const_i32(rn
);
7067 tcg_numregs
= tcg_const_i32(len
+ 1);
7068 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7069 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7070 tcg_regno
, tcg_numregs
);
7072 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7073 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7074 tcg_regno
, tcg_numregs
);
7076 tcg_temp_free_i64(tcg_idx
);
7077 tcg_temp_free_i32(tcg_regno
);
7078 tcg_temp_free_i32(tcg_numregs
);
7080 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7081 tcg_temp_free_i64(tcg_resl
);
7084 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7085 tcg_temp_free_i64(tcg_resh
);
7087 clear_vec_high(s
, is_q
, rd
);
7091 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7092 * +---+---+-------------+------+---+------+---+------------------+------+
7093 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7094 * +---+---+-------------+------+---+------+---+------------------+------+
7096 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7098 int rd
= extract32(insn
, 0, 5);
7099 int rn
= extract32(insn
, 5, 5);
7100 int rm
= extract32(insn
, 16, 5);
7101 int size
= extract32(insn
, 22, 2);
7102 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7103 * bit 2 indicates 1 vs 2 variant of the insn.
7105 int opcode
= extract32(insn
, 12, 2);
7106 bool part
= extract32(insn
, 14, 1);
7107 bool is_q
= extract32(insn
, 30, 1);
7108 int esize
= 8 << size
;
7110 int datasize
= is_q
? 128 : 64;
7111 int elements
= datasize
/ esize
;
7112 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7114 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7115 unallocated_encoding(s
);
7119 if (!fp_access_check(s
)) {
7123 tcg_resl
= tcg_const_i64(0);
7124 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7125 tcg_res
= tcg_temp_new_i64();
7127 for (i
= 0; i
< elements
; i
++) {
7129 case 1: /* UZP1/2 */
7131 int midpoint
= elements
/ 2;
7133 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7135 read_vec_element(s
, tcg_res
, rm
,
7136 2 * (i
- midpoint
) + part
, size
);
7140 case 2: /* TRN1/2 */
7142 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7144 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7147 case 3: /* ZIP1/2 */
7149 int base
= part
* elements
/ 2;
7151 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7153 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7158 g_assert_not_reached();
7163 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7164 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7166 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7167 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7171 tcg_temp_free_i64(tcg_res
);
7173 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7174 tcg_temp_free_i64(tcg_resl
);
7177 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7178 tcg_temp_free_i64(tcg_resh
);
7180 clear_vec_high(s
, is_q
, rd
);
7184 * do_reduction_op helper
7186 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7187 * important for correct NaN propagation that we do these
7188 * operations in exactly the order specified by the pseudocode.
7190 * This is a recursive function, TCG temps should be freed by the
7191 * calling function once it is done with the values.
7193 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7194 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7196 if (esize
== size
) {
7198 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7201 /* We should have one register left here */
7202 assert(ctpop8(vmap
) == 1);
7203 element
= ctz32(vmap
);
7204 assert(element
< 8);
7206 tcg_elem
= tcg_temp_new_i32();
7207 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7210 int bits
= size
/ 2;
7211 int shift
= ctpop8(vmap
) / 2;
7212 int vmap_lo
= (vmap
>> shift
) & vmap
;
7213 int vmap_hi
= (vmap
& ~vmap_lo
);
7214 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7216 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7217 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7218 tcg_res
= tcg_temp_new_i32();
7221 case 0x0c: /* fmaxnmv half-precision */
7222 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7224 case 0x0f: /* fmaxv half-precision */
7225 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7227 case 0x1c: /* fminnmv half-precision */
7228 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7230 case 0x1f: /* fminv half-precision */
7231 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7233 case 0x2c: /* fmaxnmv */
7234 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7236 case 0x2f: /* fmaxv */
7237 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7239 case 0x3c: /* fminnmv */
7240 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7242 case 0x3f: /* fminv */
7243 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7246 g_assert_not_reached();
7249 tcg_temp_free_i32(tcg_hi
);
7250 tcg_temp_free_i32(tcg_lo
);
7255 /* AdvSIMD across lanes
7256 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7257 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7258 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7259 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7261 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7263 int rd
= extract32(insn
, 0, 5);
7264 int rn
= extract32(insn
, 5, 5);
7265 int size
= extract32(insn
, 22, 2);
7266 int opcode
= extract32(insn
, 12, 5);
7267 bool is_q
= extract32(insn
, 30, 1);
7268 bool is_u
= extract32(insn
, 29, 1);
7270 bool is_min
= false;
7274 TCGv_i64 tcg_res
, tcg_elt
;
7277 case 0x1b: /* ADDV */
7279 unallocated_encoding(s
);
7283 case 0x3: /* SADDLV, UADDLV */
7284 case 0xa: /* SMAXV, UMAXV */
7285 case 0x1a: /* SMINV, UMINV */
7286 if (size
== 3 || (size
== 2 && !is_q
)) {
7287 unallocated_encoding(s
);
7291 case 0xc: /* FMAXNMV, FMINNMV */
7292 case 0xf: /* FMAXV, FMINV */
7293 /* Bit 1 of size field encodes min vs max and the actual size
7294 * depends on the encoding of the U bit. If not set (and FP16
7295 * enabled) then we do half-precision float instead of single
7298 is_min
= extract32(size
, 1, 1);
7300 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7302 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7303 unallocated_encoding(s
);
7310 unallocated_encoding(s
);
7314 if (!fp_access_check(s
)) {
7319 elements
= (is_q
? 128 : 64) / esize
;
7321 tcg_res
= tcg_temp_new_i64();
7322 tcg_elt
= tcg_temp_new_i64();
7324 /* These instructions operate across all lanes of a vector
7325 * to produce a single result. We can guarantee that a 64
7326 * bit intermediate is sufficient:
7327 * + for [US]ADDLV the maximum element size is 32 bits, and
7328 * the result type is 64 bits
7329 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7330 * same as the element size, which is 32 bits at most
7331 * For the integer operations we can choose to work at 64
7332 * or 32 bits and truncate at the end; for simplicity
7333 * we use 64 bits always. The floating point
7334 * ops do require 32 bit intermediates, though.
7337 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7339 for (i
= 1; i
< elements
; i
++) {
7340 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7343 case 0x03: /* SADDLV / UADDLV */
7344 case 0x1b: /* ADDV */
7345 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7347 case 0x0a: /* SMAXV / UMAXV */
7349 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7351 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7354 case 0x1a: /* SMINV / UMINV */
7356 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7358 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7362 g_assert_not_reached();
7367 /* Floating point vector reduction ops which work across 32
7368 * bit (single) or 16 bit (half-precision) intermediates.
7369 * Note that correct NaN propagation requires that we do these
7370 * operations in exactly the order specified by the pseudocode.
7372 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7373 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7374 int vmap
= (1 << elements
) - 1;
7375 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7376 (is_q
? 128 : 64), vmap
, fpst
);
7377 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7378 tcg_temp_free_i32(tcg_res32
);
7379 tcg_temp_free_ptr(fpst
);
7382 tcg_temp_free_i64(tcg_elt
);
7384 /* Now truncate the result to the width required for the final output */
7385 if (opcode
== 0x03) {
7386 /* SADDLV, UADDLV: result is 2*esize */
7392 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7395 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7398 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7403 g_assert_not_reached();
7406 write_fp_dreg(s
, rd
, tcg_res
);
7407 tcg_temp_free_i64(tcg_res
);
7410 /* DUP (Element, Vector)
7412 * 31 30 29 21 20 16 15 10 9 5 4 0
7413 * +---+---+-------------------+--------+-------------+------+------+
7414 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7415 * +---+---+-------------------+--------+-------------+------+------+
7417 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7419 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7422 int size
= ctz32(imm5
);
7425 if (size
> 3 || (size
== 3 && !is_q
)) {
7426 unallocated_encoding(s
);
7430 if (!fp_access_check(s
)) {
7434 index
= imm5
>> (size
+ 1);
7435 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7436 vec_reg_offset(s
, rn
, index
, size
),
7437 is_q
? 16 : 8, vec_full_reg_size(s
));
7440 /* DUP (element, scalar)
7441 * 31 21 20 16 15 10 9 5 4 0
7442 * +-----------------------+--------+-------------+------+------+
7443 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7444 * +-----------------------+--------+-------------+------+------+
7446 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7449 int size
= ctz32(imm5
);
7454 unallocated_encoding(s
);
7458 if (!fp_access_check(s
)) {
7462 index
= imm5
>> (size
+ 1);
7464 /* This instruction just extracts the specified element and
7465 * zero-extends it into the bottom of the destination register.
7467 tmp
= tcg_temp_new_i64();
7468 read_vec_element(s
, tmp
, rn
, index
, size
);
7469 write_fp_dreg(s
, rd
, tmp
);
7470 tcg_temp_free_i64(tmp
);
7475 * 31 30 29 21 20 16 15 10 9 5 4 0
7476 * +---+---+-------------------+--------+-------------+------+------+
7477 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7478 * +---+---+-------------------+--------+-------------+------+------+
7480 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7482 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7485 int size
= ctz32(imm5
);
7486 uint32_t dofs
, oprsz
, maxsz
;
7488 if (size
> 3 || ((size
== 3) && !is_q
)) {
7489 unallocated_encoding(s
);
7493 if (!fp_access_check(s
)) {
7497 dofs
= vec_full_reg_offset(s
, rd
);
7498 oprsz
= is_q
? 16 : 8;
7499 maxsz
= vec_full_reg_size(s
);
7501 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7506 * 31 21 20 16 15 14 11 10 9 5 4 0
7507 * +-----------------------+--------+------------+---+------+------+
7508 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7509 * +-----------------------+--------+------------+---+------+------+
7511 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7512 * index: encoded in imm5<4:size+1>
7514 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7517 int size
= ctz32(imm5
);
7518 int src_index
, dst_index
;
7522 unallocated_encoding(s
);
7526 if (!fp_access_check(s
)) {
7530 dst_index
= extract32(imm5
, 1+size
, 5);
7531 src_index
= extract32(imm4
, size
, 4);
7533 tmp
= tcg_temp_new_i64();
7535 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7536 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7538 tcg_temp_free_i64(tmp
);
7540 /* INS is considered a 128-bit write for SVE. */
7541 clear_vec_high(s
, true, rd
);
7547 * 31 21 20 16 15 10 9 5 4 0
7548 * +-----------------------+--------+-------------+------+------+
7549 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7550 * +-----------------------+--------+-------------+------+------+
7552 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7553 * index: encoded in imm5<4:size+1>
7555 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7557 int size
= ctz32(imm5
);
7561 unallocated_encoding(s
);
7565 if (!fp_access_check(s
)) {
7569 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7570 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7572 /* INS is considered a 128-bit write for SVE. */
7573 clear_vec_high(s
, true, rd
);
7580 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7581 * +---+---+-------------------+--------+-------------+------+------+
7582 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7583 * +---+---+-------------------+--------+-------------+------+------+
7585 * U: unsigned when set
7586 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7588 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7589 int rn
, int rd
, int imm5
)
7591 int size
= ctz32(imm5
);
7595 /* Check for UnallocatedEncodings */
7597 if (size
> 2 || (size
== 2 && !is_q
)) {
7598 unallocated_encoding(s
);
7603 || (size
< 3 && is_q
)
7604 || (size
== 3 && !is_q
)) {
7605 unallocated_encoding(s
);
7610 if (!fp_access_check(s
)) {
7614 element
= extract32(imm5
, 1+size
, 4);
7616 tcg_rd
= cpu_reg(s
, rd
);
7617 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7618 if (is_signed
&& !is_q
) {
7619 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7624 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7625 * +---+---+----+-----------------+------+---+------+---+------+------+
7626 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7627 * +---+---+----+-----------------+------+---+------+---+------+------+
7629 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7631 int rd
= extract32(insn
, 0, 5);
7632 int rn
= extract32(insn
, 5, 5);
7633 int imm4
= extract32(insn
, 11, 4);
7634 int op
= extract32(insn
, 29, 1);
7635 int is_q
= extract32(insn
, 30, 1);
7636 int imm5
= extract32(insn
, 16, 5);
7641 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7643 unallocated_encoding(s
);
7648 /* DUP (element - vector) */
7649 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7653 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7658 handle_simd_insg(s
, rd
, rn
, imm5
);
7660 unallocated_encoding(s
);
7665 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7666 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7669 unallocated_encoding(s
);
7675 /* AdvSIMD modified immediate
7676 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7677 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7678 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7679 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7681 * There are a number of operations that can be carried out here:
7682 * MOVI - move (shifted) imm into register
7683 * MVNI - move inverted (shifted) imm into register
7684 * ORR - bitwise OR of (shifted) imm with register
7685 * BIC - bitwise clear of (shifted) imm with register
7686 * With ARMv8.2 we also have:
7687 * FMOV half-precision
7689 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7691 int rd
= extract32(insn
, 0, 5);
7692 int cmode
= extract32(insn
, 12, 4);
7693 int cmode_3_1
= extract32(cmode
, 1, 3);
7694 int cmode_0
= extract32(cmode
, 0, 1);
7695 int o2
= extract32(insn
, 11, 1);
7696 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7697 bool is_neg
= extract32(insn
, 29, 1);
7698 bool is_q
= extract32(insn
, 30, 1);
7701 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7702 /* Check for FMOV (vector, immediate) - half-precision */
7703 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7704 unallocated_encoding(s
);
7709 if (!fp_access_check(s
)) {
7713 /* See AdvSIMDExpandImm() in ARM ARM */
7714 switch (cmode_3_1
) {
7715 case 0: /* Replicate(Zeros(24):imm8, 2) */
7716 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7717 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7718 case 3: /* Replicate(imm8:Zeros(24), 2) */
7720 int shift
= cmode_3_1
* 8;
7721 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7724 case 4: /* Replicate(Zeros(8):imm8, 4) */
7725 case 5: /* Replicate(imm8:Zeros(8), 4) */
7727 int shift
= (cmode_3_1
& 0x1) * 8;
7728 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7733 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7734 imm
= (abcdefgh
<< 16) | 0xffff;
7736 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7737 imm
= (abcdefgh
<< 8) | 0xff;
7739 imm
= bitfield_replicate(imm
, 32);
7742 if (!cmode_0
&& !is_neg
) {
7743 imm
= bitfield_replicate(abcdefgh
, 8);
7744 } else if (!cmode_0
&& is_neg
) {
7747 for (i
= 0; i
< 8; i
++) {
7748 if ((abcdefgh
) & (1 << i
)) {
7749 imm
|= 0xffULL
<< (i
* 8);
7752 } else if (cmode_0
) {
7754 imm
= (abcdefgh
& 0x3f) << 48;
7755 if (abcdefgh
& 0x80) {
7756 imm
|= 0x8000000000000000ULL
;
7758 if (abcdefgh
& 0x40) {
7759 imm
|= 0x3fc0000000000000ULL
;
7761 imm
|= 0x4000000000000000ULL
;
7765 /* FMOV (vector, immediate) - half-precision */
7766 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7767 /* now duplicate across the lanes */
7768 imm
= bitfield_replicate(imm
, 16);
7770 imm
= (abcdefgh
& 0x3f) << 19;
7771 if (abcdefgh
& 0x80) {
7774 if (abcdefgh
& 0x40) {
7785 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7786 g_assert_not_reached();
7789 if (cmode_3_1
!= 7 && is_neg
) {
7793 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7794 /* MOVI or MVNI, with MVNI negation handled above. */
7795 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7796 vec_full_reg_size(s
), imm
);
7798 /* ORR or BIC, with BIC negation to AND handled above. */
7800 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7802 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7807 /* AdvSIMD scalar copy
7808 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7809 * +-----+----+-----------------+------+---+------+---+------+------+
7810 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7811 * +-----+----+-----------------+------+---+------+---+------+------+
7813 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7815 int rd
= extract32(insn
, 0, 5);
7816 int rn
= extract32(insn
, 5, 5);
7817 int imm4
= extract32(insn
, 11, 4);
7818 int imm5
= extract32(insn
, 16, 5);
7819 int op
= extract32(insn
, 29, 1);
7821 if (op
!= 0 || imm4
!= 0) {
7822 unallocated_encoding(s
);
7826 /* DUP (element, scalar) */
7827 handle_simd_dupes(s
, rd
, rn
, imm5
);
7830 /* AdvSIMD scalar pairwise
7831 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7832 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7833 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7834 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7836 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7838 int u
= extract32(insn
, 29, 1);
7839 int size
= extract32(insn
, 22, 2);
7840 int opcode
= extract32(insn
, 12, 5);
7841 int rn
= extract32(insn
, 5, 5);
7842 int rd
= extract32(insn
, 0, 5);
7845 /* For some ops (the FP ones), size[1] is part of the encoding.
7846 * For ADDP strictly it is not but size[1] is always 1 for valid
7849 opcode
|= (extract32(size
, 1, 1) << 5);
7852 case 0x3b: /* ADDP */
7853 if (u
|| size
!= 3) {
7854 unallocated_encoding(s
);
7857 if (!fp_access_check(s
)) {
7863 case 0xc: /* FMAXNMP */
7864 case 0xd: /* FADDP */
7865 case 0xf: /* FMAXP */
7866 case 0x2c: /* FMINNMP */
7867 case 0x2f: /* FMINP */
7868 /* FP op, size[0] is 32 or 64 bit*/
7870 if (!dc_isar_feature(aa64_fp16
, s
)) {
7871 unallocated_encoding(s
);
7877 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7880 if (!fp_access_check(s
)) {
7884 fpst
= get_fpstatus_ptr(size
== MO_16
);
7887 unallocated_encoding(s
);
7891 if (size
== MO_64
) {
7892 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7893 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7894 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7896 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7897 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7900 case 0x3b: /* ADDP */
7901 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7903 case 0xc: /* FMAXNMP */
7904 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7906 case 0xd: /* FADDP */
7907 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7909 case 0xf: /* FMAXP */
7910 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7912 case 0x2c: /* FMINNMP */
7913 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7915 case 0x2f: /* FMINP */
7916 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7919 g_assert_not_reached();
7922 write_fp_dreg(s
, rd
, tcg_res
);
7924 tcg_temp_free_i64(tcg_op1
);
7925 tcg_temp_free_i64(tcg_op2
);
7926 tcg_temp_free_i64(tcg_res
);
7928 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7929 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7930 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7932 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7933 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7935 if (size
== MO_16
) {
7937 case 0xc: /* FMAXNMP */
7938 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7940 case 0xd: /* FADDP */
7941 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7943 case 0xf: /* FMAXP */
7944 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7946 case 0x2c: /* FMINNMP */
7947 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7949 case 0x2f: /* FMINP */
7950 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7953 g_assert_not_reached();
7957 case 0xc: /* FMAXNMP */
7958 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7960 case 0xd: /* FADDP */
7961 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7963 case 0xf: /* FMAXP */
7964 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7966 case 0x2c: /* FMINNMP */
7967 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7969 case 0x2f: /* FMINP */
7970 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7973 g_assert_not_reached();
7977 write_fp_sreg(s
, rd
, tcg_res
);
7979 tcg_temp_free_i32(tcg_op1
);
7980 tcg_temp_free_i32(tcg_op2
);
7981 tcg_temp_free_i32(tcg_res
);
7985 tcg_temp_free_ptr(fpst
);
7990 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7992 * This code is handles the common shifting code and is used by both
7993 * the vector and scalar code.
7995 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7996 TCGv_i64 tcg_rnd
, bool accumulate
,
7997 bool is_u
, int size
, int shift
)
7999 bool extended_result
= false;
8000 bool round
= tcg_rnd
!= NULL
;
8002 TCGv_i64 tcg_src_hi
;
8004 if (round
&& size
== 3) {
8005 extended_result
= true;
8006 ext_lshift
= 64 - shift
;
8007 tcg_src_hi
= tcg_temp_new_i64();
8008 } else if (shift
== 64) {
8009 if (!accumulate
&& is_u
) {
8010 /* result is zero */
8011 tcg_gen_movi_i64(tcg_res
, 0);
8016 /* Deal with the rounding step */
8018 if (extended_result
) {
8019 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8021 /* take care of sign extending tcg_res */
8022 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8023 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8024 tcg_src
, tcg_src_hi
,
8027 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8031 tcg_temp_free_i64(tcg_zero
);
8033 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8037 /* Now do the shift right */
8038 if (round
&& extended_result
) {
8039 /* extended case, >64 bit precision required */
8040 if (ext_lshift
== 0) {
8041 /* special case, only high bits matter */
8042 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8044 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8045 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8046 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8051 /* essentially shifting in 64 zeros */
8052 tcg_gen_movi_i64(tcg_src
, 0);
8054 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8058 /* effectively extending the sign-bit */
8059 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8061 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8067 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8069 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8072 if (extended_result
) {
8073 tcg_temp_free_i64(tcg_src_hi
);
8077 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8078 static void handle_scalar_simd_shri(DisasContext
*s
,
8079 bool is_u
, int immh
, int immb
,
8080 int opcode
, int rn
, int rd
)
8083 int immhb
= immh
<< 3 | immb
;
8084 int shift
= 2 * (8 << size
) - immhb
;
8085 bool accumulate
= false;
8087 bool insert
= false;
8092 if (!extract32(immh
, 3, 1)) {
8093 unallocated_encoding(s
);
8097 if (!fp_access_check(s
)) {
8102 case 0x02: /* SSRA / USRA (accumulate) */
8105 case 0x04: /* SRSHR / URSHR (rounding) */
8108 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8109 accumulate
= round
= true;
8111 case 0x08: /* SRI */
8117 uint64_t round_const
= 1ULL << (shift
- 1);
8118 tcg_round
= tcg_const_i64(round_const
);
8123 tcg_rn
= read_fp_dreg(s
, rn
);
8124 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8127 /* shift count same as element size is valid but does nothing;
8128 * special case to avoid potential shift by 64.
8130 int esize
= 8 << size
;
8131 if (shift
!= esize
) {
8132 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8133 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8136 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8137 accumulate
, is_u
, size
, shift
);
8140 write_fp_dreg(s
, rd
, tcg_rd
);
8142 tcg_temp_free_i64(tcg_rn
);
8143 tcg_temp_free_i64(tcg_rd
);
8145 tcg_temp_free_i64(tcg_round
);
8149 /* SHL/SLI - Scalar shift left */
8150 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8151 int immh
, int immb
, int opcode
,
8154 int size
= 32 - clz32(immh
) - 1;
8155 int immhb
= immh
<< 3 | immb
;
8156 int shift
= immhb
- (8 << size
);
8157 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8158 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8160 if (!extract32(immh
, 3, 1)) {
8161 unallocated_encoding(s
);
8165 if (!fp_access_check(s
)) {
8169 tcg_rn
= read_fp_dreg(s
, rn
);
8170 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8173 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8175 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8178 write_fp_dreg(s
, rd
, tcg_rd
);
8180 tcg_temp_free_i64(tcg_rn
);
8181 tcg_temp_free_i64(tcg_rd
);
8184 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8185 * (signed/unsigned) narrowing */
8186 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8187 bool is_u_shift
, bool is_u_narrow
,
8188 int immh
, int immb
, int opcode
,
8191 int immhb
= immh
<< 3 | immb
;
8192 int size
= 32 - clz32(immh
) - 1;
8193 int esize
= 8 << size
;
8194 int shift
= (2 * esize
) - immhb
;
8195 int elements
= is_scalar
? 1 : (64 / esize
);
8196 bool round
= extract32(opcode
, 0, 1);
8197 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8198 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8199 TCGv_i32 tcg_rd_narrowed
;
8202 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8203 { gen_helper_neon_narrow_sat_s8
,
8204 gen_helper_neon_unarrow_sat8
},
8205 { gen_helper_neon_narrow_sat_s16
,
8206 gen_helper_neon_unarrow_sat16
},
8207 { gen_helper_neon_narrow_sat_s32
,
8208 gen_helper_neon_unarrow_sat32
},
8211 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8212 gen_helper_neon_narrow_sat_u8
,
8213 gen_helper_neon_narrow_sat_u16
,
8214 gen_helper_neon_narrow_sat_u32
,
8217 NeonGenNarrowEnvFn
*narrowfn
;
8223 if (extract32(immh
, 3, 1)) {
8224 unallocated_encoding(s
);
8228 if (!fp_access_check(s
)) {
8233 narrowfn
= unsigned_narrow_fns
[size
];
8235 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8238 tcg_rn
= tcg_temp_new_i64();
8239 tcg_rd
= tcg_temp_new_i64();
8240 tcg_rd_narrowed
= tcg_temp_new_i32();
8241 tcg_final
= tcg_const_i64(0);
8244 uint64_t round_const
= 1ULL << (shift
- 1);
8245 tcg_round
= tcg_const_i64(round_const
);
8250 for (i
= 0; i
< elements
; i
++) {
8251 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8252 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8253 false, is_u_shift
, size
+1, shift
);
8254 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8255 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8256 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8260 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8262 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8266 tcg_temp_free_i64(tcg_round
);
8268 tcg_temp_free_i64(tcg_rn
);
8269 tcg_temp_free_i64(tcg_rd
);
8270 tcg_temp_free_i32(tcg_rd_narrowed
);
8271 tcg_temp_free_i64(tcg_final
);
8273 clear_vec_high(s
, is_q
, rd
);
8276 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8277 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8278 bool src_unsigned
, bool dst_unsigned
,
8279 int immh
, int immb
, int rn
, int rd
)
8281 int immhb
= immh
<< 3 | immb
;
8282 int size
= 32 - clz32(immh
) - 1;
8283 int shift
= immhb
- (8 << size
);
8287 assert(!(scalar
&& is_q
));
8290 if (!is_q
&& extract32(immh
, 3, 1)) {
8291 unallocated_encoding(s
);
8295 /* Since we use the variable-shift helpers we must
8296 * replicate the shift count into each element of
8297 * the tcg_shift value.
8301 shift
|= shift
<< 8;
8304 shift
|= shift
<< 16;
8310 g_assert_not_reached();
8314 if (!fp_access_check(s
)) {
8319 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8320 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8321 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8322 { NULL
, gen_helper_neon_qshl_u64
},
8324 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8325 int maxpass
= is_q
? 2 : 1;
8327 for (pass
= 0; pass
< maxpass
; pass
++) {
8328 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8330 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8331 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8332 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8334 tcg_temp_free_i64(tcg_op
);
8336 tcg_temp_free_i64(tcg_shift
);
8337 clear_vec_high(s
, is_q
, rd
);
8339 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8340 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8342 { gen_helper_neon_qshl_s8
,
8343 gen_helper_neon_qshl_s16
,
8344 gen_helper_neon_qshl_s32
},
8345 { gen_helper_neon_qshlu_s8
,
8346 gen_helper_neon_qshlu_s16
,
8347 gen_helper_neon_qshlu_s32
}
8349 { NULL
, NULL
, NULL
},
8350 { gen_helper_neon_qshl_u8
,
8351 gen_helper_neon_qshl_u16
,
8352 gen_helper_neon_qshl_u32
}
8355 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8356 MemOp memop
= scalar
? size
: MO_32
;
8357 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8359 for (pass
= 0; pass
< maxpass
; pass
++) {
8360 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8362 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8363 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8367 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8370 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8375 g_assert_not_reached();
8377 write_fp_sreg(s
, rd
, tcg_op
);
8379 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8382 tcg_temp_free_i32(tcg_op
);
8384 tcg_temp_free_i32(tcg_shift
);
8387 clear_vec_high(s
, is_q
, rd
);
8392 /* Common vector code for handling integer to FP conversion */
8393 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8394 int elements
, int is_signed
,
8395 int fracbits
, int size
)
8397 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8398 TCGv_i32 tcg_shift
= NULL
;
8400 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8403 if (fracbits
|| size
== MO_64
) {
8404 tcg_shift
= tcg_const_i32(fracbits
);
8407 if (size
== MO_64
) {
8408 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8409 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8411 for (pass
= 0; pass
< elements
; pass
++) {
8412 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8415 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8416 tcg_shift
, tcg_fpst
);
8418 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8419 tcg_shift
, tcg_fpst
);
8421 if (elements
== 1) {
8422 write_fp_dreg(s
, rd
, tcg_double
);
8424 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8428 tcg_temp_free_i64(tcg_int64
);
8429 tcg_temp_free_i64(tcg_double
);
8432 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8433 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8435 for (pass
= 0; pass
< elements
; pass
++) {
8436 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8442 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8443 tcg_shift
, tcg_fpst
);
8445 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8446 tcg_shift
, tcg_fpst
);
8450 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8452 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8459 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8460 tcg_shift
, tcg_fpst
);
8462 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8463 tcg_shift
, tcg_fpst
);
8467 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8469 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8474 g_assert_not_reached();
8477 if (elements
== 1) {
8478 write_fp_sreg(s
, rd
, tcg_float
);
8480 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8484 tcg_temp_free_i32(tcg_int32
);
8485 tcg_temp_free_i32(tcg_float
);
8488 tcg_temp_free_ptr(tcg_fpst
);
8490 tcg_temp_free_i32(tcg_shift
);
8493 clear_vec_high(s
, elements
<< size
== 16, rd
);
8496 /* UCVTF/SCVTF - Integer to FP conversion */
8497 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8498 bool is_q
, bool is_u
,
8499 int immh
, int immb
, int opcode
,
8502 int size
, elements
, fracbits
;
8503 int immhb
= immh
<< 3 | immb
;
8507 if (!is_scalar
&& !is_q
) {
8508 unallocated_encoding(s
);
8511 } else if (immh
& 4) {
8513 } else if (immh
& 2) {
8515 if (!dc_isar_feature(aa64_fp16
, s
)) {
8516 unallocated_encoding(s
);
8520 /* immh == 0 would be a failure of the decode logic */
8521 g_assert(immh
== 1);
8522 unallocated_encoding(s
);
8529 elements
= (8 << is_q
) >> size
;
8531 fracbits
= (16 << size
) - immhb
;
8533 if (!fp_access_check(s
)) {
8537 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8540 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8541 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8542 bool is_q
, bool is_u
,
8543 int immh
, int immb
, int rn
, int rd
)
8545 int immhb
= immh
<< 3 | immb
;
8546 int pass
, size
, fracbits
;
8547 TCGv_ptr tcg_fpstatus
;
8548 TCGv_i32 tcg_rmode
, tcg_shift
;
8552 if (!is_scalar
&& !is_q
) {
8553 unallocated_encoding(s
);
8556 } else if (immh
& 0x4) {
8558 } else if (immh
& 0x2) {
8560 if (!dc_isar_feature(aa64_fp16
, s
)) {
8561 unallocated_encoding(s
);
8565 /* Should have split out AdvSIMD modified immediate earlier. */
8567 unallocated_encoding(s
);
8571 if (!fp_access_check(s
)) {
8575 assert(!(is_scalar
&& is_q
));
8577 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8578 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8579 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8580 fracbits
= (16 << size
) - immhb
;
8581 tcg_shift
= tcg_const_i32(fracbits
);
8583 if (size
== MO_64
) {
8584 int maxpass
= is_scalar
? 1 : 2;
8586 for (pass
= 0; pass
< maxpass
; pass
++) {
8587 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8589 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8591 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8593 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8595 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8596 tcg_temp_free_i64(tcg_op
);
8598 clear_vec_high(s
, is_q
, rd
);
8600 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8601 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8606 fn
= gen_helper_vfp_touhh
;
8608 fn
= gen_helper_vfp_toshh
;
8613 fn
= gen_helper_vfp_touls
;
8615 fn
= gen_helper_vfp_tosls
;
8619 g_assert_not_reached();
8622 for (pass
= 0; pass
< maxpass
; pass
++) {
8623 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8625 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8626 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8628 write_fp_sreg(s
, rd
, tcg_op
);
8630 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8632 tcg_temp_free_i32(tcg_op
);
8635 clear_vec_high(s
, is_q
, rd
);
8639 tcg_temp_free_ptr(tcg_fpstatus
);
8640 tcg_temp_free_i32(tcg_shift
);
8641 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8642 tcg_temp_free_i32(tcg_rmode
);
8645 /* AdvSIMD scalar shift by immediate
8646 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8647 * +-----+---+-------------+------+------+--------+---+------+------+
8648 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8649 * +-----+---+-------------+------+------+--------+---+------+------+
8651 * This is the scalar version so it works on a fixed sized registers
8653 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8655 int rd
= extract32(insn
, 0, 5);
8656 int rn
= extract32(insn
, 5, 5);
8657 int opcode
= extract32(insn
, 11, 5);
8658 int immb
= extract32(insn
, 16, 3);
8659 int immh
= extract32(insn
, 19, 4);
8660 bool is_u
= extract32(insn
, 29, 1);
8663 unallocated_encoding(s
);
8668 case 0x08: /* SRI */
8670 unallocated_encoding(s
);
8674 case 0x00: /* SSHR / USHR */
8675 case 0x02: /* SSRA / USRA */
8676 case 0x04: /* SRSHR / URSHR */
8677 case 0x06: /* SRSRA / URSRA */
8678 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8680 case 0x0a: /* SHL / SLI */
8681 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8683 case 0x1c: /* SCVTF, UCVTF */
8684 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8687 case 0x10: /* SQSHRUN, SQSHRUN2 */
8688 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8690 unallocated_encoding(s
);
8693 handle_vec_simd_sqshrn(s
, true, false, false, true,
8694 immh
, immb
, opcode
, rn
, rd
);
8696 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8697 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8698 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8699 immh
, immb
, opcode
, rn
, rd
);
8701 case 0xc: /* SQSHLU */
8703 unallocated_encoding(s
);
8706 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8708 case 0xe: /* SQSHL, UQSHL */
8709 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8711 case 0x1f: /* FCVTZS, FCVTZU */
8712 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8715 unallocated_encoding(s
);
8720 /* AdvSIMD scalar three different
8721 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8722 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8723 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8724 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8726 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8728 bool is_u
= extract32(insn
, 29, 1);
8729 int size
= extract32(insn
, 22, 2);
8730 int opcode
= extract32(insn
, 12, 4);
8731 int rm
= extract32(insn
, 16, 5);
8732 int rn
= extract32(insn
, 5, 5);
8733 int rd
= extract32(insn
, 0, 5);
8736 unallocated_encoding(s
);
8741 case 0x9: /* SQDMLAL, SQDMLAL2 */
8742 case 0xb: /* SQDMLSL, SQDMLSL2 */
8743 case 0xd: /* SQDMULL, SQDMULL2 */
8744 if (size
== 0 || size
== 3) {
8745 unallocated_encoding(s
);
8750 unallocated_encoding(s
);
8754 if (!fp_access_check(s
)) {
8759 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8760 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8761 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8763 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8764 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8766 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8767 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8770 case 0xd: /* SQDMULL, SQDMULL2 */
8772 case 0xb: /* SQDMLSL, SQDMLSL2 */
8773 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8775 case 0x9: /* SQDMLAL, SQDMLAL2 */
8776 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8777 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8781 g_assert_not_reached();
8784 write_fp_dreg(s
, rd
, tcg_res
);
8786 tcg_temp_free_i64(tcg_op1
);
8787 tcg_temp_free_i64(tcg_op2
);
8788 tcg_temp_free_i64(tcg_res
);
8790 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8791 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8792 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8794 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8795 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8798 case 0xd: /* SQDMULL, SQDMULL2 */
8800 case 0xb: /* SQDMLSL, SQDMLSL2 */
8801 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8803 case 0x9: /* SQDMLAL, SQDMLAL2 */
8805 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8806 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8807 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8809 tcg_temp_free_i64(tcg_op3
);
8813 g_assert_not_reached();
8816 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8817 write_fp_dreg(s
, rd
, tcg_res
);
8819 tcg_temp_free_i32(tcg_op1
);
8820 tcg_temp_free_i32(tcg_op2
);
8821 tcg_temp_free_i64(tcg_res
);
8825 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8826 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8828 /* Handle 64x64->64 opcodes which are shared between the scalar
8829 * and vector 3-same groups. We cover every opcode where size == 3
8830 * is valid in either the three-reg-same (integer, not pairwise)
8831 * or scalar-three-reg-same groups.
8836 case 0x1: /* SQADD */
8838 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8840 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8843 case 0x5: /* SQSUB */
8845 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8847 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8850 case 0x6: /* CMGT, CMHI */
8851 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8852 * We implement this using setcond (test) and then negating.
8854 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8856 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8857 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8859 case 0x7: /* CMGE, CMHS */
8860 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8862 case 0x11: /* CMTST, CMEQ */
8867 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8869 case 0x8: /* SSHL, USHL */
8871 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8873 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8876 case 0x9: /* SQSHL, UQSHL */
8878 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8880 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8883 case 0xa: /* SRSHL, URSHL */
8885 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8887 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8890 case 0xb: /* SQRSHL, UQRSHL */
8892 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8894 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8897 case 0x10: /* ADD, SUB */
8899 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8901 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8905 g_assert_not_reached();
8909 /* Handle the 3-same-operands float operations; shared by the scalar
8910 * and vector encodings. The caller must filter out any encodings
8911 * not allocated for the encoding it is dealing with.
8913 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8914 int fpopcode
, int rd
, int rn
, int rm
)
8917 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8919 for (pass
= 0; pass
< elements
; pass
++) {
8922 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8923 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8924 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8926 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8927 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8930 case 0x39: /* FMLS */
8931 /* As usual for ARM, separate negation for fused multiply-add */
8932 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8934 case 0x19: /* FMLA */
8935 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8936 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8939 case 0x18: /* FMAXNM */
8940 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8942 case 0x1a: /* FADD */
8943 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8945 case 0x1b: /* FMULX */
8946 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8948 case 0x1c: /* FCMEQ */
8949 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8951 case 0x1e: /* FMAX */
8952 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8954 case 0x1f: /* FRECPS */
8955 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8957 case 0x38: /* FMINNM */
8958 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8960 case 0x3a: /* FSUB */
8961 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8963 case 0x3e: /* FMIN */
8964 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8966 case 0x3f: /* FRSQRTS */
8967 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8969 case 0x5b: /* FMUL */
8970 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8972 case 0x5c: /* FCMGE */
8973 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8975 case 0x5d: /* FACGE */
8976 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8978 case 0x5f: /* FDIV */
8979 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8981 case 0x7a: /* FABD */
8982 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8983 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8985 case 0x7c: /* FCMGT */
8986 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8988 case 0x7d: /* FACGT */
8989 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8992 g_assert_not_reached();
8995 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8997 tcg_temp_free_i64(tcg_res
);
8998 tcg_temp_free_i64(tcg_op1
);
8999 tcg_temp_free_i64(tcg_op2
);
9002 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9003 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9004 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9006 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9007 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9010 case 0x39: /* FMLS */
9011 /* As usual for ARM, separate negation for fused multiply-add */
9012 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9014 case 0x19: /* FMLA */
9015 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9016 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9019 case 0x1a: /* FADD */
9020 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9022 case 0x1b: /* FMULX */
9023 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9025 case 0x1c: /* FCMEQ */
9026 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9028 case 0x1e: /* FMAX */
9029 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9031 case 0x1f: /* FRECPS */
9032 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9034 case 0x18: /* FMAXNM */
9035 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9037 case 0x38: /* FMINNM */
9038 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9040 case 0x3a: /* FSUB */
9041 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9043 case 0x3e: /* FMIN */
9044 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9046 case 0x3f: /* FRSQRTS */
9047 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9049 case 0x5b: /* FMUL */
9050 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9052 case 0x5c: /* FCMGE */
9053 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9055 case 0x5d: /* FACGE */
9056 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9058 case 0x5f: /* FDIV */
9059 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9061 case 0x7a: /* FABD */
9062 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9063 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9065 case 0x7c: /* FCMGT */
9066 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9068 case 0x7d: /* FACGT */
9069 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9072 g_assert_not_reached();
9075 if (elements
== 1) {
9076 /* scalar single so clear high part */
9077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9079 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9080 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9081 tcg_temp_free_i64(tcg_tmp
);
9083 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9086 tcg_temp_free_i32(tcg_res
);
9087 tcg_temp_free_i32(tcg_op1
);
9088 tcg_temp_free_i32(tcg_op2
);
9092 tcg_temp_free_ptr(fpst
);
9094 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9097 /* AdvSIMD scalar three same
9098 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9099 * +-----+---+-----------+------+---+------+--------+---+------+------+
9100 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9101 * +-----+---+-----------+------+---+------+--------+---+------+------+
9103 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9105 int rd
= extract32(insn
, 0, 5);
9106 int rn
= extract32(insn
, 5, 5);
9107 int opcode
= extract32(insn
, 11, 5);
9108 int rm
= extract32(insn
, 16, 5);
9109 int size
= extract32(insn
, 22, 2);
9110 bool u
= extract32(insn
, 29, 1);
9113 if (opcode
>= 0x18) {
9114 /* Floating point: U, size[1] and opcode indicate operation */
9115 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9117 case 0x1b: /* FMULX */
9118 case 0x1f: /* FRECPS */
9119 case 0x3f: /* FRSQRTS */
9120 case 0x5d: /* FACGE */
9121 case 0x7d: /* FACGT */
9122 case 0x1c: /* FCMEQ */
9123 case 0x5c: /* FCMGE */
9124 case 0x7c: /* FCMGT */
9125 case 0x7a: /* FABD */
9128 unallocated_encoding(s
);
9132 if (!fp_access_check(s
)) {
9136 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9141 case 0x1: /* SQADD, UQADD */
9142 case 0x5: /* SQSUB, UQSUB */
9143 case 0x9: /* SQSHL, UQSHL */
9144 case 0xb: /* SQRSHL, UQRSHL */
9146 case 0x8: /* SSHL, USHL */
9147 case 0xa: /* SRSHL, URSHL */
9148 case 0x6: /* CMGT, CMHI */
9149 case 0x7: /* CMGE, CMHS */
9150 case 0x11: /* CMTST, CMEQ */
9151 case 0x10: /* ADD, SUB (vector) */
9153 unallocated_encoding(s
);
9157 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9158 if (size
!= 1 && size
!= 2) {
9159 unallocated_encoding(s
);
9164 unallocated_encoding(s
);
9168 if (!fp_access_check(s
)) {
9172 tcg_rd
= tcg_temp_new_i64();
9175 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9176 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9178 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9179 tcg_temp_free_i64(tcg_rn
);
9180 tcg_temp_free_i64(tcg_rm
);
9182 /* Do a single operation on the lowest element in the vector.
9183 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9184 * no side effects for all these operations.
9185 * OPTME: special-purpose helpers would avoid doing some
9186 * unnecessary work in the helper for the 8 and 16 bit cases.
9188 NeonGenTwoOpEnvFn
*genenvfn
;
9189 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9190 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9191 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9193 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9194 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9197 case 0x1: /* SQADD, UQADD */
9199 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9200 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9201 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9202 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9204 genenvfn
= fns
[size
][u
];
9207 case 0x5: /* SQSUB, UQSUB */
9209 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9210 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9211 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9212 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9214 genenvfn
= fns
[size
][u
];
9217 case 0x9: /* SQSHL, UQSHL */
9219 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9220 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9221 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9222 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9224 genenvfn
= fns
[size
][u
];
9227 case 0xb: /* SQRSHL, UQRSHL */
9229 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9230 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9231 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9232 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9234 genenvfn
= fns
[size
][u
];
9237 case 0x16: /* SQDMULH, SQRDMULH */
9239 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9240 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9241 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9243 assert(size
== 1 || size
== 2);
9244 genenvfn
= fns
[size
- 1][u
];
9248 g_assert_not_reached();
9251 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9252 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9253 tcg_temp_free_i32(tcg_rd32
);
9254 tcg_temp_free_i32(tcg_rn
);
9255 tcg_temp_free_i32(tcg_rm
);
9258 write_fp_dreg(s
, rd
, tcg_rd
);
9260 tcg_temp_free_i64(tcg_rd
);
9263 /* AdvSIMD scalar three same FP16
9264 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9265 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9266 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9267 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9268 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9269 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9271 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9274 int rd
= extract32(insn
, 0, 5);
9275 int rn
= extract32(insn
, 5, 5);
9276 int opcode
= extract32(insn
, 11, 3);
9277 int rm
= extract32(insn
, 16, 5);
9278 bool u
= extract32(insn
, 29, 1);
9279 bool a
= extract32(insn
, 23, 1);
9280 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9287 case 0x03: /* FMULX */
9288 case 0x04: /* FCMEQ (reg) */
9289 case 0x07: /* FRECPS */
9290 case 0x0f: /* FRSQRTS */
9291 case 0x14: /* FCMGE (reg) */
9292 case 0x15: /* FACGE */
9293 case 0x1a: /* FABD */
9294 case 0x1c: /* FCMGT (reg) */
9295 case 0x1d: /* FACGT */
9298 unallocated_encoding(s
);
9302 if (!dc_isar_feature(aa64_fp16
, s
)) {
9303 unallocated_encoding(s
);
9306 if (!fp_access_check(s
)) {
9310 fpst
= get_fpstatus_ptr(true);
9312 tcg_op1
= read_fp_hreg(s
, rn
);
9313 tcg_op2
= read_fp_hreg(s
, rm
);
9314 tcg_res
= tcg_temp_new_i32();
9317 case 0x03: /* FMULX */
9318 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9320 case 0x04: /* FCMEQ (reg) */
9321 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9323 case 0x07: /* FRECPS */
9324 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9326 case 0x0f: /* FRSQRTS */
9327 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9329 case 0x14: /* FCMGE (reg) */
9330 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9332 case 0x15: /* FACGE */
9333 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9335 case 0x1a: /* FABD */
9336 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9337 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9339 case 0x1c: /* FCMGT (reg) */
9340 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9342 case 0x1d: /* FACGT */
9343 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9346 g_assert_not_reached();
9349 write_fp_sreg(s
, rd
, tcg_res
);
9352 tcg_temp_free_i32(tcg_res
);
9353 tcg_temp_free_i32(tcg_op1
);
9354 tcg_temp_free_i32(tcg_op2
);
9355 tcg_temp_free_ptr(fpst
);
9358 /* AdvSIMD scalar three same extra
9359 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9360 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9361 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9362 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9364 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9367 int rd
= extract32(insn
, 0, 5);
9368 int rn
= extract32(insn
, 5, 5);
9369 int opcode
= extract32(insn
, 11, 4);
9370 int rm
= extract32(insn
, 16, 5);
9371 int size
= extract32(insn
, 22, 2);
9372 bool u
= extract32(insn
, 29, 1);
9373 TCGv_i32 ele1
, ele2
, ele3
;
9377 switch (u
* 16 + opcode
) {
9378 case 0x10: /* SQRDMLAH (vector) */
9379 case 0x11: /* SQRDMLSH (vector) */
9380 if (size
!= 1 && size
!= 2) {
9381 unallocated_encoding(s
);
9384 feature
= dc_isar_feature(aa64_rdm
, s
);
9387 unallocated_encoding(s
);
9391 unallocated_encoding(s
);
9394 if (!fp_access_check(s
)) {
9398 /* Do a single operation on the lowest element in the vector.
9399 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9400 * with no side effects for all these operations.
9401 * OPTME: special-purpose helpers would avoid doing some
9402 * unnecessary work in the helper for the 16 bit cases.
9404 ele1
= tcg_temp_new_i32();
9405 ele2
= tcg_temp_new_i32();
9406 ele3
= tcg_temp_new_i32();
9408 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9409 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9410 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9413 case 0x0: /* SQRDMLAH */
9415 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9417 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9420 case 0x1: /* SQRDMLSH */
9422 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9424 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9428 g_assert_not_reached();
9430 tcg_temp_free_i32(ele1
);
9431 tcg_temp_free_i32(ele2
);
9433 res
= tcg_temp_new_i64();
9434 tcg_gen_extu_i32_i64(res
, ele3
);
9435 tcg_temp_free_i32(ele3
);
9437 write_fp_dreg(s
, rd
, res
);
9438 tcg_temp_free_i64(res
);
9441 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9442 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9443 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9445 /* Handle 64->64 opcodes which are shared between the scalar and
9446 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9447 * is valid in either group and also the double-precision fp ops.
9448 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9454 case 0x4: /* CLS, CLZ */
9456 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9458 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9462 /* This opcode is shared with CNT and RBIT but we have earlier
9463 * enforced that size == 3 if and only if this is the NOT insn.
9465 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9467 case 0x7: /* SQABS, SQNEG */
9469 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9471 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9474 case 0xa: /* CMLT */
9475 /* 64 bit integer comparison against zero, result is
9476 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9481 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9482 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9484 case 0x8: /* CMGT, CMGE */
9485 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9487 case 0x9: /* CMEQ, CMLE */
9488 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9490 case 0xb: /* ABS, NEG */
9492 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9494 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9497 case 0x2f: /* FABS */
9498 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9500 case 0x6f: /* FNEG */
9501 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9503 case 0x7f: /* FSQRT */
9504 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9506 case 0x1a: /* FCVTNS */
9507 case 0x1b: /* FCVTMS */
9508 case 0x1c: /* FCVTAS */
9509 case 0x3a: /* FCVTPS */
9510 case 0x3b: /* FCVTZS */
9512 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9513 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9514 tcg_temp_free_i32(tcg_shift
);
9517 case 0x5a: /* FCVTNU */
9518 case 0x5b: /* FCVTMU */
9519 case 0x5c: /* FCVTAU */
9520 case 0x7a: /* FCVTPU */
9521 case 0x7b: /* FCVTZU */
9523 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9524 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9525 tcg_temp_free_i32(tcg_shift
);
9528 case 0x18: /* FRINTN */
9529 case 0x19: /* FRINTM */
9530 case 0x38: /* FRINTP */
9531 case 0x39: /* FRINTZ */
9532 case 0x58: /* FRINTA */
9533 case 0x79: /* FRINTI */
9534 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9536 case 0x59: /* FRINTX */
9537 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9539 case 0x1e: /* FRINT32Z */
9540 case 0x5e: /* FRINT32X */
9541 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9543 case 0x1f: /* FRINT64Z */
9544 case 0x5f: /* FRINT64X */
9545 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9548 g_assert_not_reached();
9552 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9553 bool is_scalar
, bool is_u
, bool is_q
,
9554 int size
, int rn
, int rd
)
9556 bool is_double
= (size
== MO_64
);
9559 if (!fp_access_check(s
)) {
9563 fpst
= get_fpstatus_ptr(size
== MO_16
);
9566 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9567 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9568 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9569 NeonGenTwoDoubleOpFn
*genfn
;
9574 case 0x2e: /* FCMLT (zero) */
9577 case 0x2c: /* FCMGT (zero) */
9578 genfn
= gen_helper_neon_cgt_f64
;
9580 case 0x2d: /* FCMEQ (zero) */
9581 genfn
= gen_helper_neon_ceq_f64
;
9583 case 0x6d: /* FCMLE (zero) */
9586 case 0x6c: /* FCMGE (zero) */
9587 genfn
= gen_helper_neon_cge_f64
;
9590 g_assert_not_reached();
9593 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9594 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9596 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9598 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9600 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9602 tcg_temp_free_i64(tcg_res
);
9603 tcg_temp_free_i64(tcg_zero
);
9604 tcg_temp_free_i64(tcg_op
);
9606 clear_vec_high(s
, !is_scalar
, rd
);
9608 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9609 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9610 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9611 NeonGenTwoSingleOpFn
*genfn
;
9613 int pass
, maxpasses
;
9615 if (size
== MO_16
) {
9617 case 0x2e: /* FCMLT (zero) */
9620 case 0x2c: /* FCMGT (zero) */
9621 genfn
= gen_helper_advsimd_cgt_f16
;
9623 case 0x2d: /* FCMEQ (zero) */
9624 genfn
= gen_helper_advsimd_ceq_f16
;
9626 case 0x6d: /* FCMLE (zero) */
9629 case 0x6c: /* FCMGE (zero) */
9630 genfn
= gen_helper_advsimd_cge_f16
;
9633 g_assert_not_reached();
9637 case 0x2e: /* FCMLT (zero) */
9640 case 0x2c: /* FCMGT (zero) */
9641 genfn
= gen_helper_neon_cgt_f32
;
9643 case 0x2d: /* FCMEQ (zero) */
9644 genfn
= gen_helper_neon_ceq_f32
;
9646 case 0x6d: /* FCMLE (zero) */
9649 case 0x6c: /* FCMGE (zero) */
9650 genfn
= gen_helper_neon_cge_f32
;
9653 g_assert_not_reached();
9660 int vector_size
= 8 << is_q
;
9661 maxpasses
= vector_size
>> size
;
9664 for (pass
= 0; pass
< maxpasses
; pass
++) {
9665 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9667 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9669 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9672 write_fp_sreg(s
, rd
, tcg_res
);
9674 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9677 tcg_temp_free_i32(tcg_res
);
9678 tcg_temp_free_i32(tcg_zero
);
9679 tcg_temp_free_i32(tcg_op
);
9681 clear_vec_high(s
, is_q
, rd
);
9685 tcg_temp_free_ptr(fpst
);
9688 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9689 bool is_scalar
, bool is_u
, bool is_q
,
9690 int size
, int rn
, int rd
)
9692 bool is_double
= (size
== 3);
9693 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9696 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9697 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9700 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9701 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9703 case 0x3d: /* FRECPE */
9704 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9706 case 0x3f: /* FRECPX */
9707 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9709 case 0x7d: /* FRSQRTE */
9710 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9713 g_assert_not_reached();
9715 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9717 tcg_temp_free_i64(tcg_res
);
9718 tcg_temp_free_i64(tcg_op
);
9719 clear_vec_high(s
, !is_scalar
, rd
);
9721 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9722 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9723 int pass
, maxpasses
;
9728 maxpasses
= is_q
? 4 : 2;
9731 for (pass
= 0; pass
< maxpasses
; pass
++) {
9732 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9735 case 0x3c: /* URECPE */
9736 gen_helper_recpe_u32(tcg_res
, tcg_op
);
9738 case 0x3d: /* FRECPE */
9739 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9741 case 0x3f: /* FRECPX */
9742 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9744 case 0x7d: /* FRSQRTE */
9745 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9748 g_assert_not_reached();
9752 write_fp_sreg(s
, rd
, tcg_res
);
9754 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9757 tcg_temp_free_i32(tcg_res
);
9758 tcg_temp_free_i32(tcg_op
);
9760 clear_vec_high(s
, is_q
, rd
);
9763 tcg_temp_free_ptr(fpst
);
9766 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9767 int opcode
, bool u
, bool is_q
,
9768 int size
, int rn
, int rd
)
9770 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9771 * in the source becomes a size element in the destination).
9774 TCGv_i32 tcg_res
[2];
9775 int destelt
= is_q
? 2 : 0;
9776 int passes
= scalar
? 1 : 2;
9779 tcg_res
[1] = tcg_const_i32(0);
9782 for (pass
= 0; pass
< passes
; pass
++) {
9783 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9784 NeonGenNarrowFn
*genfn
= NULL
;
9785 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9788 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9790 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9792 tcg_res
[pass
] = tcg_temp_new_i32();
9795 case 0x12: /* XTN, SQXTUN */
9797 static NeonGenNarrowFn
* const xtnfns
[3] = {
9798 gen_helper_neon_narrow_u8
,
9799 gen_helper_neon_narrow_u16
,
9800 tcg_gen_extrl_i64_i32
,
9802 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9803 gen_helper_neon_unarrow_sat8
,
9804 gen_helper_neon_unarrow_sat16
,
9805 gen_helper_neon_unarrow_sat32
,
9808 genenvfn
= sqxtunfns
[size
];
9810 genfn
= xtnfns
[size
];
9814 case 0x14: /* SQXTN, UQXTN */
9816 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9817 { gen_helper_neon_narrow_sat_s8
,
9818 gen_helper_neon_narrow_sat_u8
},
9819 { gen_helper_neon_narrow_sat_s16
,
9820 gen_helper_neon_narrow_sat_u16
},
9821 { gen_helper_neon_narrow_sat_s32
,
9822 gen_helper_neon_narrow_sat_u32
},
9824 genenvfn
= fns
[size
][u
];
9827 case 0x16: /* FCVTN, FCVTN2 */
9828 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9830 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9832 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9833 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9834 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9835 TCGv_i32 ahp
= get_ahp_flag();
9837 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9838 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9839 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9840 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9841 tcg_temp_free_i32(tcg_lo
);
9842 tcg_temp_free_i32(tcg_hi
);
9843 tcg_temp_free_ptr(fpst
);
9844 tcg_temp_free_i32(ahp
);
9847 case 0x56: /* FCVTXN, FCVTXN2 */
9848 /* 64 bit to 32 bit float conversion
9849 * with von Neumann rounding (round to odd)
9852 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9855 g_assert_not_reached();
9859 genfn(tcg_res
[pass
], tcg_op
);
9860 } else if (genenvfn
) {
9861 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9864 tcg_temp_free_i64(tcg_op
);
9867 for (pass
= 0; pass
< 2; pass
++) {
9868 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9869 tcg_temp_free_i32(tcg_res
[pass
]);
9871 clear_vec_high(s
, is_q
, rd
);
9874 /* Remaining saturating accumulating ops */
9875 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9876 bool is_q
, int size
, int rn
, int rd
)
9878 bool is_double
= (size
== 3);
9881 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9882 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9885 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9886 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9887 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9889 if (is_u
) { /* USQADD */
9890 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9891 } else { /* SUQADD */
9892 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9894 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9896 tcg_temp_free_i64(tcg_rd
);
9897 tcg_temp_free_i64(tcg_rn
);
9898 clear_vec_high(s
, !is_scalar
, rd
);
9900 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9901 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9902 int pass
, maxpasses
;
9907 maxpasses
= is_q
? 4 : 2;
9910 for (pass
= 0; pass
< maxpasses
; pass
++) {
9912 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9913 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9915 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9916 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9919 if (is_u
) { /* USQADD */
9922 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9925 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9928 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9931 g_assert_not_reached();
9933 } else { /* SUQADD */
9936 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9939 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9942 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9945 g_assert_not_reached();
9950 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9951 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9952 tcg_temp_free_i64(tcg_zero
);
9954 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9956 tcg_temp_free_i32(tcg_rd
);
9957 tcg_temp_free_i32(tcg_rn
);
9958 clear_vec_high(s
, is_q
, rd
);
9962 /* AdvSIMD scalar two reg misc
9963 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9964 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9965 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9966 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9968 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9970 int rd
= extract32(insn
, 0, 5);
9971 int rn
= extract32(insn
, 5, 5);
9972 int opcode
= extract32(insn
, 12, 5);
9973 int size
= extract32(insn
, 22, 2);
9974 bool u
= extract32(insn
, 29, 1);
9975 bool is_fcvt
= false;
9978 TCGv_ptr tcg_fpstatus
;
9981 case 0x3: /* USQADD / SUQADD*/
9982 if (!fp_access_check(s
)) {
9985 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9987 case 0x7: /* SQABS / SQNEG */
9989 case 0xa: /* CMLT */
9991 unallocated_encoding(s
);
9995 case 0x8: /* CMGT, CMGE */
9996 case 0x9: /* CMEQ, CMLE */
9997 case 0xb: /* ABS, NEG */
9999 unallocated_encoding(s
);
10003 case 0x12: /* SQXTUN */
10005 unallocated_encoding(s
);
10009 case 0x14: /* SQXTN, UQXTN */
10011 unallocated_encoding(s
);
10014 if (!fp_access_check(s
)) {
10017 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10020 case 0x16 ... 0x1d:
10022 /* Floating point: U, size[1] and opcode indicate operation;
10023 * size[0] indicates single or double precision.
10025 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10026 size
= extract32(size
, 0, 1) ? 3 : 2;
10028 case 0x2c: /* FCMGT (zero) */
10029 case 0x2d: /* FCMEQ (zero) */
10030 case 0x2e: /* FCMLT (zero) */
10031 case 0x6c: /* FCMGE (zero) */
10032 case 0x6d: /* FCMLE (zero) */
10033 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10035 case 0x1d: /* SCVTF */
10036 case 0x5d: /* UCVTF */
10038 bool is_signed
= (opcode
== 0x1d);
10039 if (!fp_access_check(s
)) {
10042 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10045 case 0x3d: /* FRECPE */
10046 case 0x3f: /* FRECPX */
10047 case 0x7d: /* FRSQRTE */
10048 if (!fp_access_check(s
)) {
10051 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10053 case 0x1a: /* FCVTNS */
10054 case 0x1b: /* FCVTMS */
10055 case 0x3a: /* FCVTPS */
10056 case 0x3b: /* FCVTZS */
10057 case 0x5a: /* FCVTNU */
10058 case 0x5b: /* FCVTMU */
10059 case 0x7a: /* FCVTPU */
10060 case 0x7b: /* FCVTZU */
10062 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10064 case 0x1c: /* FCVTAS */
10065 case 0x5c: /* FCVTAU */
10066 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10068 rmode
= FPROUNDING_TIEAWAY
;
10070 case 0x56: /* FCVTXN, FCVTXN2 */
10072 unallocated_encoding(s
);
10075 if (!fp_access_check(s
)) {
10078 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10081 unallocated_encoding(s
);
10086 unallocated_encoding(s
);
10090 if (!fp_access_check(s
)) {
10095 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10096 tcg_fpstatus
= get_fpstatus_ptr(false);
10097 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10100 tcg_fpstatus
= NULL
;
10104 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10105 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10107 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10108 write_fp_dreg(s
, rd
, tcg_rd
);
10109 tcg_temp_free_i64(tcg_rd
);
10110 tcg_temp_free_i64(tcg_rn
);
10112 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10113 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10115 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10118 case 0x7: /* SQABS, SQNEG */
10120 NeonGenOneOpEnvFn
*genfn
;
10121 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10122 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10123 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10124 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10126 genfn
= fns
[size
][u
];
10127 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10130 case 0x1a: /* FCVTNS */
10131 case 0x1b: /* FCVTMS */
10132 case 0x1c: /* FCVTAS */
10133 case 0x3a: /* FCVTPS */
10134 case 0x3b: /* FCVTZS */
10136 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10137 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10138 tcg_temp_free_i32(tcg_shift
);
10141 case 0x5a: /* FCVTNU */
10142 case 0x5b: /* FCVTMU */
10143 case 0x5c: /* FCVTAU */
10144 case 0x7a: /* FCVTPU */
10145 case 0x7b: /* FCVTZU */
10147 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10148 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10149 tcg_temp_free_i32(tcg_shift
);
10153 g_assert_not_reached();
10156 write_fp_sreg(s
, rd
, tcg_rd
);
10157 tcg_temp_free_i32(tcg_rd
);
10158 tcg_temp_free_i32(tcg_rn
);
10162 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10163 tcg_temp_free_i32(tcg_rmode
);
10164 tcg_temp_free_ptr(tcg_fpstatus
);
10168 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10169 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10170 int immh
, int immb
, int opcode
, int rn
, int rd
)
10172 int size
= 32 - clz32(immh
) - 1;
10173 int immhb
= immh
<< 3 | immb
;
10174 int shift
= 2 * (8 << size
) - immhb
;
10175 GVecGen2iFn
*gvec_fn
;
10177 if (extract32(immh
, 3, 1) && !is_q
) {
10178 unallocated_encoding(s
);
10181 tcg_debug_assert(size
<= 3);
10183 if (!fp_access_check(s
)) {
10188 case 0x02: /* SSRA / USRA (accumulate) */
10189 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10192 case 0x08: /* SRI */
10193 gvec_fn
= gen_gvec_sri
;
10196 case 0x00: /* SSHR / USHR */
10198 if (shift
== 8 << size
) {
10199 /* Shift count the same size as element size produces zero. */
10200 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10201 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10204 gvec_fn
= tcg_gen_gvec_shri
;
10206 /* Shift count the same size as element size produces all sign. */
10207 if (shift
== 8 << size
) {
10210 gvec_fn
= tcg_gen_gvec_sari
;
10214 case 0x04: /* SRSHR / URSHR (rounding) */
10215 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10218 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10219 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10223 g_assert_not_reached();
10226 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10229 /* SHL/SLI - Vector shift left */
10230 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10231 int immh
, int immb
, int opcode
, int rn
, int rd
)
10233 int size
= 32 - clz32(immh
) - 1;
10234 int immhb
= immh
<< 3 | immb
;
10235 int shift
= immhb
- (8 << size
);
10237 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10238 assert(size
>= 0 && size
<= 3);
10240 if (extract32(immh
, 3, 1) && !is_q
) {
10241 unallocated_encoding(s
);
10245 if (!fp_access_check(s
)) {
10250 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10252 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10256 /* USHLL/SHLL - Vector shift left with widening */
10257 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10258 int immh
, int immb
, int opcode
, int rn
, int rd
)
10260 int size
= 32 - clz32(immh
) - 1;
10261 int immhb
= immh
<< 3 | immb
;
10262 int shift
= immhb
- (8 << size
);
10264 int esize
= 8 << size
;
10265 int elements
= dsize
/esize
;
10266 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10267 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10271 unallocated_encoding(s
);
10275 if (!fp_access_check(s
)) {
10279 /* For the LL variants the store is larger than the load,
10280 * so if rd == rn we would overwrite parts of our input.
10281 * So load everything right now and use shifts in the main loop.
10283 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10285 for (i
= 0; i
< elements
; i
++) {
10286 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10287 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10288 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10289 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10293 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10294 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10295 int immh
, int immb
, int opcode
, int rn
, int rd
)
10297 int immhb
= immh
<< 3 | immb
;
10298 int size
= 32 - clz32(immh
) - 1;
10300 int esize
= 8 << size
;
10301 int elements
= dsize
/esize
;
10302 int shift
= (2 * esize
) - immhb
;
10303 bool round
= extract32(opcode
, 0, 1);
10304 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10305 TCGv_i64 tcg_round
;
10308 if (extract32(immh
, 3, 1)) {
10309 unallocated_encoding(s
);
10313 if (!fp_access_check(s
)) {
10317 tcg_rn
= tcg_temp_new_i64();
10318 tcg_rd
= tcg_temp_new_i64();
10319 tcg_final
= tcg_temp_new_i64();
10320 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10323 uint64_t round_const
= 1ULL << (shift
- 1);
10324 tcg_round
= tcg_const_i64(round_const
);
10329 for (i
= 0; i
< elements
; i
++) {
10330 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10331 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10332 false, true, size
+1, shift
);
10334 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10338 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10340 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10343 tcg_temp_free_i64(tcg_round
);
10345 tcg_temp_free_i64(tcg_rn
);
10346 tcg_temp_free_i64(tcg_rd
);
10347 tcg_temp_free_i64(tcg_final
);
10349 clear_vec_high(s
, is_q
, rd
);
10353 /* AdvSIMD shift by immediate
10354 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10355 * +---+---+---+-------------+------+------+--------+---+------+------+
10356 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10357 * +---+---+---+-------------+------+------+--------+---+------+------+
10359 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10361 int rd
= extract32(insn
, 0, 5);
10362 int rn
= extract32(insn
, 5, 5);
10363 int opcode
= extract32(insn
, 11, 5);
10364 int immb
= extract32(insn
, 16, 3);
10365 int immh
= extract32(insn
, 19, 4);
10366 bool is_u
= extract32(insn
, 29, 1);
10367 bool is_q
= extract32(insn
, 30, 1);
10369 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10373 case 0x08: /* SRI */
10375 unallocated_encoding(s
);
10379 case 0x00: /* SSHR / USHR */
10380 case 0x02: /* SSRA / USRA (accumulate) */
10381 case 0x04: /* SRSHR / URSHR (rounding) */
10382 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10383 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10385 case 0x0a: /* SHL / SLI */
10386 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10388 case 0x10: /* SHRN */
10389 case 0x11: /* RSHRN / SQRSHRUN */
10391 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10394 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10397 case 0x12: /* SQSHRN / UQSHRN */
10398 case 0x13: /* SQRSHRN / UQRSHRN */
10399 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10402 case 0x14: /* SSHLL / USHLL */
10403 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10405 case 0x1c: /* SCVTF / UCVTF */
10406 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10409 case 0xc: /* SQSHLU */
10411 unallocated_encoding(s
);
10414 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10416 case 0xe: /* SQSHL, UQSHL */
10417 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10419 case 0x1f: /* FCVTZS/ FCVTZU */
10420 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10423 unallocated_encoding(s
);
10428 /* Generate code to do a "long" addition or subtraction, ie one done in
10429 * TCGv_i64 on vector lanes twice the width specified by size.
10431 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10432 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10434 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10435 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10436 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10437 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10439 NeonGenTwo64OpFn
*genfn
;
10442 genfn
= fns
[size
][is_sub
];
10443 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10446 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10447 int opcode
, int rd
, int rn
, int rm
)
10449 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10450 TCGv_i64 tcg_res
[2];
10453 tcg_res
[0] = tcg_temp_new_i64();
10454 tcg_res
[1] = tcg_temp_new_i64();
10456 /* Does this op do an adding accumulate, a subtracting accumulate,
10457 * or no accumulate at all?
10475 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10476 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10479 /* size == 2 means two 32x32->64 operations; this is worth special
10480 * casing because we can generally handle it inline.
10483 for (pass
= 0; pass
< 2; pass
++) {
10484 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10485 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10486 TCGv_i64 tcg_passres
;
10487 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10489 int elt
= pass
+ is_q
* 2;
10491 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10492 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10495 tcg_passres
= tcg_res
[pass
];
10497 tcg_passres
= tcg_temp_new_i64();
10501 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10502 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10504 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10505 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10507 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10508 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10510 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10511 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10513 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10514 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10515 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10517 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10518 tcg_temp_free_i64(tcg_tmp1
);
10519 tcg_temp_free_i64(tcg_tmp2
);
10522 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10523 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10524 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10525 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10527 case 9: /* SQDMLAL, SQDMLAL2 */
10528 case 11: /* SQDMLSL, SQDMLSL2 */
10529 case 13: /* SQDMULL, SQDMULL2 */
10530 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10531 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10532 tcg_passres
, tcg_passres
);
10535 g_assert_not_reached();
10538 if (opcode
== 9 || opcode
== 11) {
10539 /* saturating accumulate ops */
10541 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10543 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10544 tcg_res
[pass
], tcg_passres
);
10545 } else if (accop
> 0) {
10546 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10547 } else if (accop
< 0) {
10548 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10552 tcg_temp_free_i64(tcg_passres
);
10555 tcg_temp_free_i64(tcg_op1
);
10556 tcg_temp_free_i64(tcg_op2
);
10559 /* size 0 or 1, generally helper functions */
10560 for (pass
= 0; pass
< 2; pass
++) {
10561 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10562 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10563 TCGv_i64 tcg_passres
;
10564 int elt
= pass
+ is_q
* 2;
10566 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10567 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10570 tcg_passres
= tcg_res
[pass
];
10572 tcg_passres
= tcg_temp_new_i64();
10576 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10577 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10579 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10580 static NeonGenWidenFn
* const widenfns
[2][2] = {
10581 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10582 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10584 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10586 widenfn(tcg_op2_64
, tcg_op2
);
10587 widenfn(tcg_passres
, tcg_op1
);
10588 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10589 tcg_passres
, tcg_op2_64
);
10590 tcg_temp_free_i64(tcg_op2_64
);
10593 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10594 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10597 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10599 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10603 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10605 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10609 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10610 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10611 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10614 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10616 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10620 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10622 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10626 case 9: /* SQDMLAL, SQDMLAL2 */
10627 case 11: /* SQDMLSL, SQDMLSL2 */
10628 case 13: /* SQDMULL, SQDMULL2 */
10630 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10631 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10632 tcg_passres
, tcg_passres
);
10635 g_assert_not_reached();
10637 tcg_temp_free_i32(tcg_op1
);
10638 tcg_temp_free_i32(tcg_op2
);
10641 if (opcode
== 9 || opcode
== 11) {
10642 /* saturating accumulate ops */
10644 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10646 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10650 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10651 tcg_res
[pass
], tcg_passres
);
10653 tcg_temp_free_i64(tcg_passres
);
10658 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10659 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10660 tcg_temp_free_i64(tcg_res
[0]);
10661 tcg_temp_free_i64(tcg_res
[1]);
10664 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10665 int opcode
, int rd
, int rn
, int rm
)
10667 TCGv_i64 tcg_res
[2];
10668 int part
= is_q
? 2 : 0;
10671 for (pass
= 0; pass
< 2; pass
++) {
10672 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10673 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10674 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10675 static NeonGenWidenFn
* const widenfns
[3][2] = {
10676 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10677 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10678 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10680 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10682 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10683 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10684 widenfn(tcg_op2_wide
, tcg_op2
);
10685 tcg_temp_free_i32(tcg_op2
);
10686 tcg_res
[pass
] = tcg_temp_new_i64();
10687 gen_neon_addl(size
, (opcode
== 3),
10688 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10689 tcg_temp_free_i64(tcg_op1
);
10690 tcg_temp_free_i64(tcg_op2_wide
);
10693 for (pass
= 0; pass
< 2; pass
++) {
10694 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10695 tcg_temp_free_i64(tcg_res
[pass
]);
10699 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10701 tcg_gen_addi_i64(in
, in
, 1U << 31);
10702 tcg_gen_extrh_i64_i32(res
, in
);
10705 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10706 int opcode
, int rd
, int rn
, int rm
)
10708 TCGv_i32 tcg_res
[2];
10709 int part
= is_q
? 2 : 0;
10712 for (pass
= 0; pass
< 2; pass
++) {
10713 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10714 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10715 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10716 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10717 { gen_helper_neon_narrow_high_u8
,
10718 gen_helper_neon_narrow_round_high_u8
},
10719 { gen_helper_neon_narrow_high_u16
,
10720 gen_helper_neon_narrow_round_high_u16
},
10721 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10723 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10725 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10726 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10728 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10730 tcg_temp_free_i64(tcg_op1
);
10731 tcg_temp_free_i64(tcg_op2
);
10733 tcg_res
[pass
] = tcg_temp_new_i32();
10734 gennarrow(tcg_res
[pass
], tcg_wideres
);
10735 tcg_temp_free_i64(tcg_wideres
);
10738 for (pass
= 0; pass
< 2; pass
++) {
10739 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10740 tcg_temp_free_i32(tcg_res
[pass
]);
10742 clear_vec_high(s
, is_q
, rd
);
10745 /* AdvSIMD three different
10746 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10747 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10748 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10749 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10751 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10753 /* Instructions in this group fall into three basic classes
10754 * (in each case with the operation working on each element in
10755 * the input vectors):
10756 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10758 * (2) wide 64 x 128 -> 128
10759 * (3) narrowing 128 x 128 -> 64
10760 * Here we do initial decode, catch unallocated cases and
10761 * dispatch to separate functions for each class.
10763 int is_q
= extract32(insn
, 30, 1);
10764 int is_u
= extract32(insn
, 29, 1);
10765 int size
= extract32(insn
, 22, 2);
10766 int opcode
= extract32(insn
, 12, 4);
10767 int rm
= extract32(insn
, 16, 5);
10768 int rn
= extract32(insn
, 5, 5);
10769 int rd
= extract32(insn
, 0, 5);
10772 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10773 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10774 /* 64 x 128 -> 128 */
10776 unallocated_encoding(s
);
10779 if (!fp_access_check(s
)) {
10782 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10784 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10785 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10786 /* 128 x 128 -> 64 */
10788 unallocated_encoding(s
);
10791 if (!fp_access_check(s
)) {
10794 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10796 case 14: /* PMULL, PMULL2 */
10798 unallocated_encoding(s
);
10802 case 0: /* PMULL.P8 */
10803 if (!fp_access_check(s
)) {
10806 /* The Q field specifies lo/hi half input for this insn. */
10807 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10808 gen_helper_neon_pmull_h
);
10811 case 3: /* PMULL.P64 */
10812 if (!dc_isar_feature(aa64_pmull
, s
)) {
10813 unallocated_encoding(s
);
10816 if (!fp_access_check(s
)) {
10819 /* The Q field specifies lo/hi half input for this insn. */
10820 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10821 gen_helper_gvec_pmull_q
);
10825 unallocated_encoding(s
);
10829 case 9: /* SQDMLAL, SQDMLAL2 */
10830 case 11: /* SQDMLSL, SQDMLSL2 */
10831 case 13: /* SQDMULL, SQDMULL2 */
10832 if (is_u
|| size
== 0) {
10833 unallocated_encoding(s
);
10837 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10838 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10839 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10840 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10841 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10842 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10843 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10844 /* 64 x 64 -> 128 */
10846 unallocated_encoding(s
);
10849 if (!fp_access_check(s
)) {
10853 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10856 /* opcode 15 not allocated */
10857 unallocated_encoding(s
);
10862 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10863 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10865 int rd
= extract32(insn
, 0, 5);
10866 int rn
= extract32(insn
, 5, 5);
10867 int rm
= extract32(insn
, 16, 5);
10868 int size
= extract32(insn
, 22, 2);
10869 bool is_u
= extract32(insn
, 29, 1);
10870 bool is_q
= extract32(insn
, 30, 1);
10872 if (!fp_access_check(s
)) {
10876 switch (size
+ 4 * is_u
) {
10878 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10881 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10884 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10887 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10890 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10893 case 5: /* BSL bitwise select */
10894 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10896 case 6: /* BIT, bitwise insert if true */
10897 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10899 case 7: /* BIF, bitwise insert if false */
10900 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10904 g_assert_not_reached();
10908 /* Pairwise op subgroup of C3.6.16.
10910 * This is called directly or via the handle_3same_float for float pairwise
10911 * operations where the opcode and size are calculated differently.
10913 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10914 int size
, int rn
, int rm
, int rd
)
10919 /* Floating point operations need fpst */
10920 if (opcode
>= 0x58) {
10921 fpst
= get_fpstatus_ptr(false);
10926 if (!fp_access_check(s
)) {
10930 /* These operations work on the concatenated rm:rn, with each pair of
10931 * adjacent elements being operated on to produce an element in the result.
10934 TCGv_i64 tcg_res
[2];
10936 for (pass
= 0; pass
< 2; pass
++) {
10937 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10938 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10939 int passreg
= (pass
== 0) ? rn
: rm
;
10941 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10942 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10943 tcg_res
[pass
] = tcg_temp_new_i64();
10946 case 0x17: /* ADDP */
10947 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10949 case 0x58: /* FMAXNMP */
10950 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10952 case 0x5a: /* FADDP */
10953 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10955 case 0x5e: /* FMAXP */
10956 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10958 case 0x78: /* FMINNMP */
10959 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10961 case 0x7e: /* FMINP */
10962 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10965 g_assert_not_reached();
10968 tcg_temp_free_i64(tcg_op1
);
10969 tcg_temp_free_i64(tcg_op2
);
10972 for (pass
= 0; pass
< 2; pass
++) {
10973 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10974 tcg_temp_free_i64(tcg_res
[pass
]);
10977 int maxpass
= is_q
? 4 : 2;
10978 TCGv_i32 tcg_res
[4];
10980 for (pass
= 0; pass
< maxpass
; pass
++) {
10981 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10982 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10983 NeonGenTwoOpFn
*genfn
= NULL
;
10984 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10985 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10987 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10988 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10989 tcg_res
[pass
] = tcg_temp_new_i32();
10992 case 0x17: /* ADDP */
10994 static NeonGenTwoOpFn
* const fns
[3] = {
10995 gen_helper_neon_padd_u8
,
10996 gen_helper_neon_padd_u16
,
11002 case 0x14: /* SMAXP, UMAXP */
11004 static NeonGenTwoOpFn
* const fns
[3][2] = {
11005 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11006 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11007 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11009 genfn
= fns
[size
][u
];
11012 case 0x15: /* SMINP, UMINP */
11014 static NeonGenTwoOpFn
* const fns
[3][2] = {
11015 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11016 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11017 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11019 genfn
= fns
[size
][u
];
11022 /* The FP operations are all on single floats (32 bit) */
11023 case 0x58: /* FMAXNMP */
11024 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11026 case 0x5a: /* FADDP */
11027 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11029 case 0x5e: /* FMAXP */
11030 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11032 case 0x78: /* FMINNMP */
11033 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11035 case 0x7e: /* FMINP */
11036 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11039 g_assert_not_reached();
11042 /* FP ops called directly, otherwise call now */
11044 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11047 tcg_temp_free_i32(tcg_op1
);
11048 tcg_temp_free_i32(tcg_op2
);
11051 for (pass
= 0; pass
< maxpass
; pass
++) {
11052 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11053 tcg_temp_free_i32(tcg_res
[pass
]);
11055 clear_vec_high(s
, is_q
, rd
);
11059 tcg_temp_free_ptr(fpst
);
11063 /* Floating point op subgroup of C3.6.16. */
11064 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11066 /* For floating point ops, the U, size[1] and opcode bits
11067 * together indicate the operation. size[0] indicates single
11070 int fpopcode
= extract32(insn
, 11, 5)
11071 | (extract32(insn
, 23, 1) << 5)
11072 | (extract32(insn
, 29, 1) << 6);
11073 int is_q
= extract32(insn
, 30, 1);
11074 int size
= extract32(insn
, 22, 1);
11075 int rm
= extract32(insn
, 16, 5);
11076 int rn
= extract32(insn
, 5, 5);
11077 int rd
= extract32(insn
, 0, 5);
11079 int datasize
= is_q
? 128 : 64;
11080 int esize
= 32 << size
;
11081 int elements
= datasize
/ esize
;
11083 if (size
== 1 && !is_q
) {
11084 unallocated_encoding(s
);
11088 switch (fpopcode
) {
11089 case 0x58: /* FMAXNMP */
11090 case 0x5a: /* FADDP */
11091 case 0x5e: /* FMAXP */
11092 case 0x78: /* FMINNMP */
11093 case 0x7e: /* FMINP */
11094 if (size
&& !is_q
) {
11095 unallocated_encoding(s
);
11098 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11101 case 0x1b: /* FMULX */
11102 case 0x1f: /* FRECPS */
11103 case 0x3f: /* FRSQRTS */
11104 case 0x5d: /* FACGE */
11105 case 0x7d: /* FACGT */
11106 case 0x19: /* FMLA */
11107 case 0x39: /* FMLS */
11108 case 0x18: /* FMAXNM */
11109 case 0x1a: /* FADD */
11110 case 0x1c: /* FCMEQ */
11111 case 0x1e: /* FMAX */
11112 case 0x38: /* FMINNM */
11113 case 0x3a: /* FSUB */
11114 case 0x3e: /* FMIN */
11115 case 0x5b: /* FMUL */
11116 case 0x5c: /* FCMGE */
11117 case 0x5f: /* FDIV */
11118 case 0x7a: /* FABD */
11119 case 0x7c: /* FCMGT */
11120 if (!fp_access_check(s
)) {
11123 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11126 case 0x1d: /* FMLAL */
11127 case 0x3d: /* FMLSL */
11128 case 0x59: /* FMLAL2 */
11129 case 0x79: /* FMLSL2 */
11130 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11131 unallocated_encoding(s
);
11134 if (fp_access_check(s
)) {
11135 int is_s
= extract32(insn
, 23, 1);
11136 int is_2
= extract32(insn
, 29, 1);
11137 int data
= (is_2
<< 1) | is_s
;
11138 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11139 vec_full_reg_offset(s
, rn
),
11140 vec_full_reg_offset(s
, rm
), cpu_env
,
11141 is_q
? 16 : 8, vec_full_reg_size(s
),
11142 data
, gen_helper_gvec_fmlal_a64
);
11147 unallocated_encoding(s
);
11152 /* Integer op subgroup of C3.6.16. */
11153 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11155 int is_q
= extract32(insn
, 30, 1);
11156 int u
= extract32(insn
, 29, 1);
11157 int size
= extract32(insn
, 22, 2);
11158 int opcode
= extract32(insn
, 11, 5);
11159 int rm
= extract32(insn
, 16, 5);
11160 int rn
= extract32(insn
, 5, 5);
11161 int rd
= extract32(insn
, 0, 5);
11166 case 0x13: /* MUL, PMUL */
11167 if (u
&& size
!= 0) {
11168 unallocated_encoding(s
);
11172 case 0x0: /* SHADD, UHADD */
11173 case 0x2: /* SRHADD, URHADD */
11174 case 0x4: /* SHSUB, UHSUB */
11175 case 0xc: /* SMAX, UMAX */
11176 case 0xd: /* SMIN, UMIN */
11177 case 0xe: /* SABD, UABD */
11178 case 0xf: /* SABA, UABA */
11179 case 0x12: /* MLA, MLS */
11181 unallocated_encoding(s
);
11185 case 0x16: /* SQDMULH, SQRDMULH */
11186 if (size
== 0 || size
== 3) {
11187 unallocated_encoding(s
);
11192 if (size
== 3 && !is_q
) {
11193 unallocated_encoding(s
);
11199 if (!fp_access_check(s
)) {
11204 case 0x01: /* SQADD, UQADD */
11206 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11208 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11211 case 0x05: /* SQSUB, UQSUB */
11213 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11215 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11218 case 0x08: /* SSHL, USHL */
11220 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11222 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11225 case 0x0c: /* SMAX, UMAX */
11227 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11229 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11232 case 0x0d: /* SMIN, UMIN */
11234 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11236 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11239 case 0xe: /* SABD, UABD */
11241 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11243 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11246 case 0xf: /* SABA, UABA */
11248 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11250 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11253 case 0x10: /* ADD, SUB */
11255 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11257 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11260 case 0x13: /* MUL, PMUL */
11261 if (!u
) { /* MUL */
11262 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11263 } else { /* PMUL */
11264 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11267 case 0x12: /* MLA, MLS */
11269 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11271 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11275 if (!u
) { /* CMTST */
11276 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11280 cond
= TCG_COND_EQ
;
11282 case 0x06: /* CMGT, CMHI */
11283 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11285 case 0x07: /* CMGE, CMHS */
11286 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11288 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11289 vec_full_reg_offset(s
, rn
),
11290 vec_full_reg_offset(s
, rm
),
11291 is_q
? 16 : 8, vec_full_reg_size(s
));
11297 for (pass
= 0; pass
< 2; pass
++) {
11298 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11299 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11300 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11302 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11303 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11305 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11307 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11309 tcg_temp_free_i64(tcg_res
);
11310 tcg_temp_free_i64(tcg_op1
);
11311 tcg_temp_free_i64(tcg_op2
);
11314 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11315 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11316 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11317 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11318 NeonGenTwoOpFn
*genfn
= NULL
;
11319 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11321 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11322 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11325 case 0x0: /* SHADD, UHADD */
11327 static NeonGenTwoOpFn
* const fns
[3][2] = {
11328 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11329 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11330 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11332 genfn
= fns
[size
][u
];
11335 case 0x2: /* SRHADD, URHADD */
11337 static NeonGenTwoOpFn
* const fns
[3][2] = {
11338 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11339 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11340 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11342 genfn
= fns
[size
][u
];
11345 case 0x4: /* SHSUB, UHSUB */
11347 static NeonGenTwoOpFn
* const fns
[3][2] = {
11348 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11349 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11350 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11352 genfn
= fns
[size
][u
];
11355 case 0x9: /* SQSHL, UQSHL */
11357 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11358 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11359 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11360 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11362 genenvfn
= fns
[size
][u
];
11365 case 0xa: /* SRSHL, URSHL */
11367 static NeonGenTwoOpFn
* const fns
[3][2] = {
11368 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11369 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11370 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11372 genfn
= fns
[size
][u
];
11375 case 0xb: /* SQRSHL, UQRSHL */
11377 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11378 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11379 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11380 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11382 genenvfn
= fns
[size
][u
];
11385 case 0x16: /* SQDMULH, SQRDMULH */
11387 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11388 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11389 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11391 assert(size
== 1 || size
== 2);
11392 genenvfn
= fns
[size
- 1][u
];
11396 g_assert_not_reached();
11400 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11402 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11405 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11407 tcg_temp_free_i32(tcg_res
);
11408 tcg_temp_free_i32(tcg_op1
);
11409 tcg_temp_free_i32(tcg_op2
);
11412 clear_vec_high(s
, is_q
, rd
);
11415 /* AdvSIMD three same
11416 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11417 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11418 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11419 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11421 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11423 int opcode
= extract32(insn
, 11, 5);
11426 case 0x3: /* logic ops */
11427 disas_simd_3same_logic(s
, insn
);
11429 case 0x17: /* ADDP */
11430 case 0x14: /* SMAXP, UMAXP */
11431 case 0x15: /* SMINP, UMINP */
11433 /* Pairwise operations */
11434 int is_q
= extract32(insn
, 30, 1);
11435 int u
= extract32(insn
, 29, 1);
11436 int size
= extract32(insn
, 22, 2);
11437 int rm
= extract32(insn
, 16, 5);
11438 int rn
= extract32(insn
, 5, 5);
11439 int rd
= extract32(insn
, 0, 5);
11440 if (opcode
== 0x17) {
11441 if (u
|| (size
== 3 && !is_q
)) {
11442 unallocated_encoding(s
);
11447 unallocated_encoding(s
);
11451 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11454 case 0x18 ... 0x31:
11455 /* floating point ops, sz[1] and U are part of opcode */
11456 disas_simd_3same_float(s
, insn
);
11459 disas_simd_3same_int(s
, insn
);
11465 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11467 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11468 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11469 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11470 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11472 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11473 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11476 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11478 int opcode
, fpopcode
;
11479 int is_q
, u
, a
, rm
, rn
, rd
;
11480 int datasize
, elements
;
11483 bool pairwise
= false;
11485 if (!dc_isar_feature(aa64_fp16
, s
)) {
11486 unallocated_encoding(s
);
11490 if (!fp_access_check(s
)) {
11494 /* For these floating point ops, the U, a and opcode bits
11495 * together indicate the operation.
11497 opcode
= extract32(insn
, 11, 3);
11498 u
= extract32(insn
, 29, 1);
11499 a
= extract32(insn
, 23, 1);
11500 is_q
= extract32(insn
, 30, 1);
11501 rm
= extract32(insn
, 16, 5);
11502 rn
= extract32(insn
, 5, 5);
11503 rd
= extract32(insn
, 0, 5);
11505 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11506 datasize
= is_q
? 128 : 64;
11507 elements
= datasize
/ 16;
11509 switch (fpopcode
) {
11510 case 0x10: /* FMAXNMP */
11511 case 0x12: /* FADDP */
11512 case 0x16: /* FMAXP */
11513 case 0x18: /* FMINNMP */
11514 case 0x1e: /* FMINP */
11519 fpst
= get_fpstatus_ptr(true);
11522 int maxpass
= is_q
? 8 : 4;
11523 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11524 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11525 TCGv_i32 tcg_res
[8];
11527 for (pass
= 0; pass
< maxpass
; pass
++) {
11528 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11529 int passelt
= (pass
<< 1) & (maxpass
- 1);
11531 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11532 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11533 tcg_res
[pass
] = tcg_temp_new_i32();
11535 switch (fpopcode
) {
11536 case 0x10: /* FMAXNMP */
11537 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11540 case 0x12: /* FADDP */
11541 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11543 case 0x16: /* FMAXP */
11544 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11546 case 0x18: /* FMINNMP */
11547 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11550 case 0x1e: /* FMINP */
11551 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11554 g_assert_not_reached();
11558 for (pass
= 0; pass
< maxpass
; pass
++) {
11559 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11560 tcg_temp_free_i32(tcg_res
[pass
]);
11563 tcg_temp_free_i32(tcg_op1
);
11564 tcg_temp_free_i32(tcg_op2
);
11567 for (pass
= 0; pass
< elements
; pass
++) {
11568 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11569 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11570 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11572 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11573 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11575 switch (fpopcode
) {
11576 case 0x0: /* FMAXNM */
11577 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11579 case 0x1: /* FMLA */
11580 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11581 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11584 case 0x2: /* FADD */
11585 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11587 case 0x3: /* FMULX */
11588 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11590 case 0x4: /* FCMEQ */
11591 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11593 case 0x6: /* FMAX */
11594 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11596 case 0x7: /* FRECPS */
11597 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11599 case 0x8: /* FMINNM */
11600 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11602 case 0x9: /* FMLS */
11603 /* As usual for ARM, separate negation for fused multiply-add */
11604 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11605 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11606 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11609 case 0xa: /* FSUB */
11610 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11612 case 0xe: /* FMIN */
11613 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11615 case 0xf: /* FRSQRTS */
11616 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11618 case 0x13: /* FMUL */
11619 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11621 case 0x14: /* FCMGE */
11622 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11624 case 0x15: /* FACGE */
11625 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11627 case 0x17: /* FDIV */
11628 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11630 case 0x1a: /* FABD */
11631 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11632 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11634 case 0x1c: /* FCMGT */
11635 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11637 case 0x1d: /* FACGT */
11638 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11641 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11642 __func__
, insn
, fpopcode
, s
->pc_curr
);
11643 g_assert_not_reached();
11646 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11647 tcg_temp_free_i32(tcg_res
);
11648 tcg_temp_free_i32(tcg_op1
);
11649 tcg_temp_free_i32(tcg_op2
);
11653 tcg_temp_free_ptr(fpst
);
11655 clear_vec_high(s
, is_q
, rd
);
11658 /* AdvSIMD three same extra
11659 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11660 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11661 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11662 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11664 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11666 int rd
= extract32(insn
, 0, 5);
11667 int rn
= extract32(insn
, 5, 5);
11668 int opcode
= extract32(insn
, 11, 4);
11669 int rm
= extract32(insn
, 16, 5);
11670 int size
= extract32(insn
, 22, 2);
11671 bool u
= extract32(insn
, 29, 1);
11672 bool is_q
= extract32(insn
, 30, 1);
11676 switch (u
* 16 + opcode
) {
11677 case 0x10: /* SQRDMLAH (vector) */
11678 case 0x11: /* SQRDMLSH (vector) */
11679 if (size
!= 1 && size
!= 2) {
11680 unallocated_encoding(s
);
11683 feature
= dc_isar_feature(aa64_rdm
, s
);
11685 case 0x02: /* SDOT (vector) */
11686 case 0x12: /* UDOT (vector) */
11687 if (size
!= MO_32
) {
11688 unallocated_encoding(s
);
11691 feature
= dc_isar_feature(aa64_dp
, s
);
11693 case 0x18: /* FCMLA, #0 */
11694 case 0x19: /* FCMLA, #90 */
11695 case 0x1a: /* FCMLA, #180 */
11696 case 0x1b: /* FCMLA, #270 */
11697 case 0x1c: /* FCADD, #90 */
11698 case 0x1e: /* FCADD, #270 */
11700 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11701 || (size
== 3 && !is_q
)) {
11702 unallocated_encoding(s
);
11705 feature
= dc_isar_feature(aa64_fcma
, s
);
11708 unallocated_encoding(s
);
11712 unallocated_encoding(s
);
11715 if (!fp_access_check(s
)) {
11720 case 0x0: /* SQRDMLAH (vector) */
11721 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
11724 case 0x1: /* SQRDMLSH (vector) */
11725 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
11728 case 0x2: /* SDOT / UDOT */
11729 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11730 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11733 case 0x8: /* FCMLA, #0 */
11734 case 0x9: /* FCMLA, #90 */
11735 case 0xa: /* FCMLA, #180 */
11736 case 0xb: /* FCMLA, #270 */
11737 rot
= extract32(opcode
, 0, 2);
11740 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11741 gen_helper_gvec_fcmlah
);
11744 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11745 gen_helper_gvec_fcmlas
);
11748 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11749 gen_helper_gvec_fcmlad
);
11752 g_assert_not_reached();
11756 case 0xc: /* FCADD, #90 */
11757 case 0xe: /* FCADD, #270 */
11758 rot
= extract32(opcode
, 1, 1);
11761 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11762 gen_helper_gvec_fcaddh
);
11765 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11766 gen_helper_gvec_fcadds
);
11769 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11770 gen_helper_gvec_fcaddd
);
11773 g_assert_not_reached();
11778 g_assert_not_reached();
11782 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11783 int size
, int rn
, int rd
)
11785 /* Handle 2-reg-misc ops which are widening (so each size element
11786 * in the source becomes a 2*size element in the destination.
11787 * The only instruction like this is FCVTL.
11792 /* 32 -> 64 bit fp conversion */
11793 TCGv_i64 tcg_res
[2];
11794 int srcelt
= is_q
? 2 : 0;
11796 for (pass
= 0; pass
< 2; pass
++) {
11797 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11798 tcg_res
[pass
] = tcg_temp_new_i64();
11800 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11801 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11802 tcg_temp_free_i32(tcg_op
);
11804 for (pass
= 0; pass
< 2; pass
++) {
11805 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11806 tcg_temp_free_i64(tcg_res
[pass
]);
11809 /* 16 -> 32 bit fp conversion */
11810 int srcelt
= is_q
? 4 : 0;
11811 TCGv_i32 tcg_res
[4];
11812 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11813 TCGv_i32 ahp
= get_ahp_flag();
11815 for (pass
= 0; pass
< 4; pass
++) {
11816 tcg_res
[pass
] = tcg_temp_new_i32();
11818 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11819 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11822 for (pass
= 0; pass
< 4; pass
++) {
11823 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11824 tcg_temp_free_i32(tcg_res
[pass
]);
11827 tcg_temp_free_ptr(fpst
);
11828 tcg_temp_free_i32(ahp
);
11832 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11833 bool is_q
, int size
, int rn
, int rd
)
11835 int op
= (opcode
<< 1) | u
;
11836 int opsz
= op
+ size
;
11837 int grp_size
= 3 - opsz
;
11838 int dsize
= is_q
? 128 : 64;
11842 unallocated_encoding(s
);
11846 if (!fp_access_check(s
)) {
11851 /* Special case bytes, use bswap op on each group of elements */
11852 int groups
= dsize
/ (8 << grp_size
);
11854 for (i
= 0; i
< groups
; i
++) {
11855 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11857 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11858 switch (grp_size
) {
11860 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11863 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11866 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11869 g_assert_not_reached();
11871 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11872 tcg_temp_free_i64(tcg_tmp
);
11874 clear_vec_high(s
, is_q
, rd
);
11876 int revmask
= (1 << grp_size
) - 1;
11877 int esize
= 8 << size
;
11878 int elements
= dsize
/ esize
;
11879 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11880 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11881 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11883 for (i
= 0; i
< elements
; i
++) {
11884 int e_rev
= (i
& 0xf) ^ revmask
;
11885 int off
= e_rev
* esize
;
11886 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11888 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11889 tcg_rn
, off
- 64, esize
);
11891 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11894 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11895 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11897 tcg_temp_free_i64(tcg_rd_hi
);
11898 tcg_temp_free_i64(tcg_rd
);
11899 tcg_temp_free_i64(tcg_rn
);
11903 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11904 bool is_q
, int size
, int rn
, int rd
)
11906 /* Implement the pairwise operations from 2-misc:
11907 * SADDLP, UADDLP, SADALP, UADALP.
11908 * These all add pairs of elements in the input to produce a
11909 * double-width result element in the output (possibly accumulating).
11911 bool accum
= (opcode
== 0x6);
11912 int maxpass
= is_q
? 2 : 1;
11914 TCGv_i64 tcg_res
[2];
11917 /* 32 + 32 -> 64 op */
11918 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11920 for (pass
= 0; pass
< maxpass
; pass
++) {
11921 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11922 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11924 tcg_res
[pass
] = tcg_temp_new_i64();
11926 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11927 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11928 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11930 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11931 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11934 tcg_temp_free_i64(tcg_op1
);
11935 tcg_temp_free_i64(tcg_op2
);
11938 for (pass
= 0; pass
< maxpass
; pass
++) {
11939 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11940 NeonGenOne64OpFn
*genfn
;
11941 static NeonGenOne64OpFn
* const fns
[2][2] = {
11942 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11943 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11946 genfn
= fns
[size
][u
];
11948 tcg_res
[pass
] = tcg_temp_new_i64();
11950 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11951 genfn(tcg_res
[pass
], tcg_op
);
11954 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11956 gen_helper_neon_addl_u16(tcg_res
[pass
],
11957 tcg_res
[pass
], tcg_op
);
11959 gen_helper_neon_addl_u32(tcg_res
[pass
],
11960 tcg_res
[pass
], tcg_op
);
11963 tcg_temp_free_i64(tcg_op
);
11967 tcg_res
[1] = tcg_const_i64(0);
11969 for (pass
= 0; pass
< 2; pass
++) {
11970 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11971 tcg_temp_free_i64(tcg_res
[pass
]);
11975 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11977 /* Implement SHLL and SHLL2 */
11979 int part
= is_q
? 2 : 0;
11980 TCGv_i64 tcg_res
[2];
11982 for (pass
= 0; pass
< 2; pass
++) {
11983 static NeonGenWidenFn
* const widenfns
[3] = {
11984 gen_helper_neon_widen_u8
,
11985 gen_helper_neon_widen_u16
,
11986 tcg_gen_extu_i32_i64
,
11988 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11989 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11991 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11992 tcg_res
[pass
] = tcg_temp_new_i64();
11993 widenfn(tcg_res
[pass
], tcg_op
);
11994 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11996 tcg_temp_free_i32(tcg_op
);
11999 for (pass
= 0; pass
< 2; pass
++) {
12000 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12001 tcg_temp_free_i64(tcg_res
[pass
]);
12005 /* AdvSIMD two reg misc
12006 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12007 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12008 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12009 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12011 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12013 int size
= extract32(insn
, 22, 2);
12014 int opcode
= extract32(insn
, 12, 5);
12015 bool u
= extract32(insn
, 29, 1);
12016 bool is_q
= extract32(insn
, 30, 1);
12017 int rn
= extract32(insn
, 5, 5);
12018 int rd
= extract32(insn
, 0, 5);
12019 bool need_fpstatus
= false;
12020 bool need_rmode
= false;
12022 TCGv_i32 tcg_rmode
;
12023 TCGv_ptr tcg_fpstatus
;
12026 case 0x0: /* REV64, REV32 */
12027 case 0x1: /* REV16 */
12028 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12030 case 0x5: /* CNT, NOT, RBIT */
12031 if (u
&& size
== 0) {
12034 } else if (u
&& size
== 1) {
12037 } else if (!u
&& size
== 0) {
12041 unallocated_encoding(s
);
12043 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12044 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12046 unallocated_encoding(s
);
12049 if (!fp_access_check(s
)) {
12053 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12055 case 0x4: /* CLS, CLZ */
12057 unallocated_encoding(s
);
12061 case 0x2: /* SADDLP, UADDLP */
12062 case 0x6: /* SADALP, UADALP */
12064 unallocated_encoding(s
);
12067 if (!fp_access_check(s
)) {
12070 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12072 case 0x13: /* SHLL, SHLL2 */
12073 if (u
== 0 || size
== 3) {
12074 unallocated_encoding(s
);
12077 if (!fp_access_check(s
)) {
12080 handle_shll(s
, is_q
, size
, rn
, rd
);
12082 case 0xa: /* CMLT */
12084 unallocated_encoding(s
);
12088 case 0x8: /* CMGT, CMGE */
12089 case 0x9: /* CMEQ, CMLE */
12090 case 0xb: /* ABS, NEG */
12091 if (size
== 3 && !is_q
) {
12092 unallocated_encoding(s
);
12096 case 0x3: /* SUQADD, USQADD */
12097 if (size
== 3 && !is_q
) {
12098 unallocated_encoding(s
);
12101 if (!fp_access_check(s
)) {
12104 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12106 case 0x7: /* SQABS, SQNEG */
12107 if (size
== 3 && !is_q
) {
12108 unallocated_encoding(s
);
12113 case 0x16 ... 0x1f:
12115 /* Floating point: U, size[1] and opcode indicate operation;
12116 * size[0] indicates single or double precision.
12118 int is_double
= extract32(size
, 0, 1);
12119 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12120 size
= is_double
? 3 : 2;
12122 case 0x2f: /* FABS */
12123 case 0x6f: /* FNEG */
12124 if (size
== 3 && !is_q
) {
12125 unallocated_encoding(s
);
12129 case 0x1d: /* SCVTF */
12130 case 0x5d: /* UCVTF */
12132 bool is_signed
= (opcode
== 0x1d) ? true : false;
12133 int elements
= is_double
? 2 : is_q
? 4 : 2;
12134 if (is_double
&& !is_q
) {
12135 unallocated_encoding(s
);
12138 if (!fp_access_check(s
)) {
12141 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12144 case 0x2c: /* FCMGT (zero) */
12145 case 0x2d: /* FCMEQ (zero) */
12146 case 0x2e: /* FCMLT (zero) */
12147 case 0x6c: /* FCMGE (zero) */
12148 case 0x6d: /* FCMLE (zero) */
12149 if (size
== 3 && !is_q
) {
12150 unallocated_encoding(s
);
12153 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12155 case 0x7f: /* FSQRT */
12156 if (size
== 3 && !is_q
) {
12157 unallocated_encoding(s
);
12161 case 0x1a: /* FCVTNS */
12162 case 0x1b: /* FCVTMS */
12163 case 0x3a: /* FCVTPS */
12164 case 0x3b: /* FCVTZS */
12165 case 0x5a: /* FCVTNU */
12166 case 0x5b: /* FCVTMU */
12167 case 0x7a: /* FCVTPU */
12168 case 0x7b: /* FCVTZU */
12169 need_fpstatus
= true;
12171 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12172 if (size
== 3 && !is_q
) {
12173 unallocated_encoding(s
);
12177 case 0x5c: /* FCVTAU */
12178 case 0x1c: /* FCVTAS */
12179 need_fpstatus
= true;
12181 rmode
= FPROUNDING_TIEAWAY
;
12182 if (size
== 3 && !is_q
) {
12183 unallocated_encoding(s
);
12187 case 0x3c: /* URECPE */
12189 unallocated_encoding(s
);
12193 case 0x3d: /* FRECPE */
12194 case 0x7d: /* FRSQRTE */
12195 if (size
== 3 && !is_q
) {
12196 unallocated_encoding(s
);
12199 if (!fp_access_check(s
)) {
12202 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12204 case 0x56: /* FCVTXN, FCVTXN2 */
12206 unallocated_encoding(s
);
12210 case 0x16: /* FCVTN, FCVTN2 */
12211 /* handle_2misc_narrow does a 2*size -> size operation, but these
12212 * instructions encode the source size rather than dest size.
12214 if (!fp_access_check(s
)) {
12217 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12219 case 0x17: /* FCVTL, FCVTL2 */
12220 if (!fp_access_check(s
)) {
12223 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12225 case 0x18: /* FRINTN */
12226 case 0x19: /* FRINTM */
12227 case 0x38: /* FRINTP */
12228 case 0x39: /* FRINTZ */
12230 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12232 case 0x59: /* FRINTX */
12233 case 0x79: /* FRINTI */
12234 need_fpstatus
= true;
12235 if (size
== 3 && !is_q
) {
12236 unallocated_encoding(s
);
12240 case 0x58: /* FRINTA */
12242 rmode
= FPROUNDING_TIEAWAY
;
12243 need_fpstatus
= true;
12244 if (size
== 3 && !is_q
) {
12245 unallocated_encoding(s
);
12249 case 0x7c: /* URSQRTE */
12251 unallocated_encoding(s
);
12255 case 0x1e: /* FRINT32Z */
12256 case 0x1f: /* FRINT64Z */
12258 rmode
= FPROUNDING_ZERO
;
12260 case 0x5e: /* FRINT32X */
12261 case 0x5f: /* FRINT64X */
12262 need_fpstatus
= true;
12263 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12264 unallocated_encoding(s
);
12269 unallocated_encoding(s
);
12275 unallocated_encoding(s
);
12279 if (!fp_access_check(s
)) {
12283 if (need_fpstatus
|| need_rmode
) {
12284 tcg_fpstatus
= get_fpstatus_ptr(false);
12286 tcg_fpstatus
= NULL
;
12289 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12290 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12297 if (u
&& size
== 0) { /* NOT */
12298 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12302 case 0x8: /* CMGT, CMGE */
12304 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12306 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12309 case 0x9: /* CMEQ, CMLE */
12311 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12313 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12316 case 0xa: /* CMLT */
12317 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12320 if (u
) { /* ABS, NEG */
12321 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12323 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12329 /* All 64-bit element operations can be shared with scalar 2misc */
12332 /* Coverity claims (size == 3 && !is_q) has been eliminated
12333 * from all paths leading to here.
12335 tcg_debug_assert(is_q
);
12336 for (pass
= 0; pass
< 2; pass
++) {
12337 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12338 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12340 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12342 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12343 tcg_rmode
, tcg_fpstatus
);
12345 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12347 tcg_temp_free_i64(tcg_res
);
12348 tcg_temp_free_i64(tcg_op
);
12353 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12354 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12355 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12357 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12360 /* Special cases for 32 bit elements */
12362 case 0x4: /* CLS */
12364 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12366 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12369 case 0x7: /* SQABS, SQNEG */
12371 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12373 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12376 case 0x2f: /* FABS */
12377 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12379 case 0x6f: /* FNEG */
12380 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12382 case 0x7f: /* FSQRT */
12383 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12385 case 0x1a: /* FCVTNS */
12386 case 0x1b: /* FCVTMS */
12387 case 0x1c: /* FCVTAS */
12388 case 0x3a: /* FCVTPS */
12389 case 0x3b: /* FCVTZS */
12391 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12392 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12393 tcg_shift
, tcg_fpstatus
);
12394 tcg_temp_free_i32(tcg_shift
);
12397 case 0x5a: /* FCVTNU */
12398 case 0x5b: /* FCVTMU */
12399 case 0x5c: /* FCVTAU */
12400 case 0x7a: /* FCVTPU */
12401 case 0x7b: /* FCVTZU */
12403 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12404 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12405 tcg_shift
, tcg_fpstatus
);
12406 tcg_temp_free_i32(tcg_shift
);
12409 case 0x18: /* FRINTN */
12410 case 0x19: /* FRINTM */
12411 case 0x38: /* FRINTP */
12412 case 0x39: /* FRINTZ */
12413 case 0x58: /* FRINTA */
12414 case 0x79: /* FRINTI */
12415 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12417 case 0x59: /* FRINTX */
12418 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12420 case 0x7c: /* URSQRTE */
12421 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12423 case 0x1e: /* FRINT32Z */
12424 case 0x5e: /* FRINT32X */
12425 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12427 case 0x1f: /* FRINT64Z */
12428 case 0x5f: /* FRINT64X */
12429 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12432 g_assert_not_reached();
12435 /* Use helpers for 8 and 16 bit elements */
12437 case 0x5: /* CNT, RBIT */
12438 /* For these two insns size is part of the opcode specifier
12439 * (handled earlier); they always operate on byte elements.
12442 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12444 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12447 case 0x7: /* SQABS, SQNEG */
12449 NeonGenOneOpEnvFn
*genfn
;
12450 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12451 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12452 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12454 genfn
= fns
[size
][u
];
12455 genfn(tcg_res
, cpu_env
, tcg_op
);
12458 case 0x4: /* CLS, CLZ */
12461 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12463 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12467 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12469 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12474 g_assert_not_reached();
12478 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12480 tcg_temp_free_i32(tcg_res
);
12481 tcg_temp_free_i32(tcg_op
);
12484 clear_vec_high(s
, is_q
, rd
);
12487 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12488 tcg_temp_free_i32(tcg_rmode
);
12490 if (need_fpstatus
) {
12491 tcg_temp_free_ptr(tcg_fpstatus
);
12495 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12497 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12498 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12499 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12500 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12501 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12502 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12504 * This actually covers two groups where scalar access is governed by
12505 * bit 28. A bunch of the instructions (float to integral) only exist
12506 * in the vector form and are un-allocated for the scalar decode. Also
12507 * in the scalar decode Q is always 1.
12509 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12511 int fpop
, opcode
, a
, u
;
12515 bool only_in_vector
= false;
12518 TCGv_i32 tcg_rmode
= NULL
;
12519 TCGv_ptr tcg_fpstatus
= NULL
;
12520 bool need_rmode
= false;
12521 bool need_fpst
= true;
12524 if (!dc_isar_feature(aa64_fp16
, s
)) {
12525 unallocated_encoding(s
);
12529 rd
= extract32(insn
, 0, 5);
12530 rn
= extract32(insn
, 5, 5);
12532 a
= extract32(insn
, 23, 1);
12533 u
= extract32(insn
, 29, 1);
12534 is_scalar
= extract32(insn
, 28, 1);
12535 is_q
= extract32(insn
, 30, 1);
12537 opcode
= extract32(insn
, 12, 5);
12538 fpop
= deposit32(opcode
, 5, 1, a
);
12539 fpop
= deposit32(fpop
, 6, 1, u
);
12541 rd
= extract32(insn
, 0, 5);
12542 rn
= extract32(insn
, 5, 5);
12545 case 0x1d: /* SCVTF */
12546 case 0x5d: /* UCVTF */
12553 elements
= (is_q
? 8 : 4);
12556 if (!fp_access_check(s
)) {
12559 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12563 case 0x2c: /* FCMGT (zero) */
12564 case 0x2d: /* FCMEQ (zero) */
12565 case 0x2e: /* FCMLT (zero) */
12566 case 0x6c: /* FCMGE (zero) */
12567 case 0x6d: /* FCMLE (zero) */
12568 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12570 case 0x3d: /* FRECPE */
12571 case 0x3f: /* FRECPX */
12573 case 0x18: /* FRINTN */
12575 only_in_vector
= true;
12576 rmode
= FPROUNDING_TIEEVEN
;
12578 case 0x19: /* FRINTM */
12580 only_in_vector
= true;
12581 rmode
= FPROUNDING_NEGINF
;
12583 case 0x38: /* FRINTP */
12585 only_in_vector
= true;
12586 rmode
= FPROUNDING_POSINF
;
12588 case 0x39: /* FRINTZ */
12590 only_in_vector
= true;
12591 rmode
= FPROUNDING_ZERO
;
12593 case 0x58: /* FRINTA */
12595 only_in_vector
= true;
12596 rmode
= FPROUNDING_TIEAWAY
;
12598 case 0x59: /* FRINTX */
12599 case 0x79: /* FRINTI */
12600 only_in_vector
= true;
12601 /* current rounding mode */
12603 case 0x1a: /* FCVTNS */
12605 rmode
= FPROUNDING_TIEEVEN
;
12607 case 0x1b: /* FCVTMS */
12609 rmode
= FPROUNDING_NEGINF
;
12611 case 0x1c: /* FCVTAS */
12613 rmode
= FPROUNDING_TIEAWAY
;
12615 case 0x3a: /* FCVTPS */
12617 rmode
= FPROUNDING_POSINF
;
12619 case 0x3b: /* FCVTZS */
12621 rmode
= FPROUNDING_ZERO
;
12623 case 0x5a: /* FCVTNU */
12625 rmode
= FPROUNDING_TIEEVEN
;
12627 case 0x5b: /* FCVTMU */
12629 rmode
= FPROUNDING_NEGINF
;
12631 case 0x5c: /* FCVTAU */
12633 rmode
= FPROUNDING_TIEAWAY
;
12635 case 0x7a: /* FCVTPU */
12637 rmode
= FPROUNDING_POSINF
;
12639 case 0x7b: /* FCVTZU */
12641 rmode
= FPROUNDING_ZERO
;
12643 case 0x2f: /* FABS */
12644 case 0x6f: /* FNEG */
12647 case 0x7d: /* FRSQRTE */
12648 case 0x7f: /* FSQRT (vector) */
12651 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12652 g_assert_not_reached();
12656 /* Check additional constraints for the scalar encoding */
12659 unallocated_encoding(s
);
12662 /* FRINTxx is only in the vector form */
12663 if (only_in_vector
) {
12664 unallocated_encoding(s
);
12669 if (!fp_access_check(s
)) {
12673 if (need_rmode
|| need_fpst
) {
12674 tcg_fpstatus
= get_fpstatus_ptr(true);
12678 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12679 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12683 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12684 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12687 case 0x1a: /* FCVTNS */
12688 case 0x1b: /* FCVTMS */
12689 case 0x1c: /* FCVTAS */
12690 case 0x3a: /* FCVTPS */
12691 case 0x3b: /* FCVTZS */
12692 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12694 case 0x3d: /* FRECPE */
12695 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12697 case 0x3f: /* FRECPX */
12698 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12700 case 0x5a: /* FCVTNU */
12701 case 0x5b: /* FCVTMU */
12702 case 0x5c: /* FCVTAU */
12703 case 0x7a: /* FCVTPU */
12704 case 0x7b: /* FCVTZU */
12705 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12707 case 0x6f: /* FNEG */
12708 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12710 case 0x7d: /* FRSQRTE */
12711 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12714 g_assert_not_reached();
12717 /* limit any sign extension going on */
12718 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12719 write_fp_sreg(s
, rd
, tcg_res
);
12721 tcg_temp_free_i32(tcg_res
);
12722 tcg_temp_free_i32(tcg_op
);
12724 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12725 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12726 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12728 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12731 case 0x1a: /* FCVTNS */
12732 case 0x1b: /* FCVTMS */
12733 case 0x1c: /* FCVTAS */
12734 case 0x3a: /* FCVTPS */
12735 case 0x3b: /* FCVTZS */
12736 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12738 case 0x3d: /* FRECPE */
12739 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12741 case 0x5a: /* FCVTNU */
12742 case 0x5b: /* FCVTMU */
12743 case 0x5c: /* FCVTAU */
12744 case 0x7a: /* FCVTPU */
12745 case 0x7b: /* FCVTZU */
12746 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12748 case 0x18: /* FRINTN */
12749 case 0x19: /* FRINTM */
12750 case 0x38: /* FRINTP */
12751 case 0x39: /* FRINTZ */
12752 case 0x58: /* FRINTA */
12753 case 0x79: /* FRINTI */
12754 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12756 case 0x59: /* FRINTX */
12757 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12759 case 0x2f: /* FABS */
12760 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12762 case 0x6f: /* FNEG */
12763 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12765 case 0x7d: /* FRSQRTE */
12766 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12768 case 0x7f: /* FSQRT */
12769 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12772 g_assert_not_reached();
12775 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12777 tcg_temp_free_i32(tcg_res
);
12778 tcg_temp_free_i32(tcg_op
);
12781 clear_vec_high(s
, is_q
, rd
);
12785 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12786 tcg_temp_free_i32(tcg_rmode
);
12789 if (tcg_fpstatus
) {
12790 tcg_temp_free_ptr(tcg_fpstatus
);
12794 /* AdvSIMD scalar x indexed element
12795 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12796 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12797 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12798 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12799 * AdvSIMD vector x indexed element
12800 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12801 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12802 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12803 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12805 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12807 /* This encoding has two kinds of instruction:
12808 * normal, where we perform elt x idxelt => elt for each
12809 * element in the vector
12810 * long, where we perform elt x idxelt and generate a result of
12811 * double the width of the input element
12812 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12814 bool is_scalar
= extract32(insn
, 28, 1);
12815 bool is_q
= extract32(insn
, 30, 1);
12816 bool u
= extract32(insn
, 29, 1);
12817 int size
= extract32(insn
, 22, 2);
12818 int l
= extract32(insn
, 21, 1);
12819 int m
= extract32(insn
, 20, 1);
12820 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12821 int rm
= extract32(insn
, 16, 4);
12822 int opcode
= extract32(insn
, 12, 4);
12823 int h
= extract32(insn
, 11, 1);
12824 int rn
= extract32(insn
, 5, 5);
12825 int rd
= extract32(insn
, 0, 5);
12826 bool is_long
= false;
12828 bool is_fp16
= false;
12832 switch (16 * u
+ opcode
) {
12833 case 0x08: /* MUL */
12834 case 0x10: /* MLA */
12835 case 0x14: /* MLS */
12837 unallocated_encoding(s
);
12841 case 0x02: /* SMLAL, SMLAL2 */
12842 case 0x12: /* UMLAL, UMLAL2 */
12843 case 0x06: /* SMLSL, SMLSL2 */
12844 case 0x16: /* UMLSL, UMLSL2 */
12845 case 0x0a: /* SMULL, SMULL2 */
12846 case 0x1a: /* UMULL, UMULL2 */
12848 unallocated_encoding(s
);
12853 case 0x03: /* SQDMLAL, SQDMLAL2 */
12854 case 0x07: /* SQDMLSL, SQDMLSL2 */
12855 case 0x0b: /* SQDMULL, SQDMULL2 */
12858 case 0x0c: /* SQDMULH */
12859 case 0x0d: /* SQRDMULH */
12861 case 0x01: /* FMLA */
12862 case 0x05: /* FMLS */
12863 case 0x09: /* FMUL */
12864 case 0x19: /* FMULX */
12867 case 0x1d: /* SQRDMLAH */
12868 case 0x1f: /* SQRDMLSH */
12869 if (!dc_isar_feature(aa64_rdm
, s
)) {
12870 unallocated_encoding(s
);
12874 case 0x0e: /* SDOT */
12875 case 0x1e: /* UDOT */
12876 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12877 unallocated_encoding(s
);
12881 case 0x11: /* FCMLA #0 */
12882 case 0x13: /* FCMLA #90 */
12883 case 0x15: /* FCMLA #180 */
12884 case 0x17: /* FCMLA #270 */
12885 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12886 unallocated_encoding(s
);
12891 case 0x00: /* FMLAL */
12892 case 0x04: /* FMLSL */
12893 case 0x18: /* FMLAL2 */
12894 case 0x1c: /* FMLSL2 */
12895 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12896 unallocated_encoding(s
);
12900 /* is_fp, but we pass cpu_env not fp_status. */
12903 unallocated_encoding(s
);
12908 case 1: /* normal fp */
12909 /* convert insn encoded size to MemOp size */
12911 case 0: /* half-precision */
12915 case MO_32
: /* single precision */
12916 case MO_64
: /* double precision */
12919 unallocated_encoding(s
);
12924 case 2: /* complex fp */
12925 /* Each indexable element is a complex pair. */
12930 unallocated_encoding(s
);
12938 unallocated_encoding(s
);
12943 default: /* integer */
12947 unallocated_encoding(s
);
12952 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12953 unallocated_encoding(s
);
12957 /* Given MemOp size, adjust register and indexing. */
12960 index
= h
<< 2 | l
<< 1 | m
;
12963 index
= h
<< 1 | l
;
12968 unallocated_encoding(s
);
12975 g_assert_not_reached();
12978 if (!fp_access_check(s
)) {
12983 fpst
= get_fpstatus_ptr(is_fp16
);
12988 switch (16 * u
+ opcode
) {
12989 case 0x0e: /* SDOT */
12990 case 0x1e: /* UDOT */
12991 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12992 u
? gen_helper_gvec_udot_idx_b
12993 : gen_helper_gvec_sdot_idx_b
);
12995 case 0x11: /* FCMLA #0 */
12996 case 0x13: /* FCMLA #90 */
12997 case 0x15: /* FCMLA #180 */
12998 case 0x17: /* FCMLA #270 */
13000 int rot
= extract32(insn
, 13, 2);
13001 int data
= (index
<< 2) | rot
;
13002 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13003 vec_full_reg_offset(s
, rn
),
13004 vec_full_reg_offset(s
, rm
), fpst
,
13005 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13007 ? gen_helper_gvec_fcmlas_idx
13008 : gen_helper_gvec_fcmlah_idx
);
13009 tcg_temp_free_ptr(fpst
);
13013 case 0x00: /* FMLAL */
13014 case 0x04: /* FMLSL */
13015 case 0x18: /* FMLAL2 */
13016 case 0x1c: /* FMLSL2 */
13018 int is_s
= extract32(opcode
, 2, 1);
13020 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13021 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13022 vec_full_reg_offset(s
, rn
),
13023 vec_full_reg_offset(s
, rm
), cpu_env
,
13024 is_q
? 16 : 8, vec_full_reg_size(s
),
13025 data
, gen_helper_gvec_fmlal_idx_a64
);
13031 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13034 assert(is_fp
&& is_q
&& !is_long
);
13036 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13038 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13039 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13040 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13042 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13044 switch (16 * u
+ opcode
) {
13045 case 0x05: /* FMLS */
13046 /* As usual for ARM, separate negation for fused multiply-add */
13047 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13049 case 0x01: /* FMLA */
13050 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13051 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13053 case 0x09: /* FMUL */
13054 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13056 case 0x19: /* FMULX */
13057 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13060 g_assert_not_reached();
13063 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13064 tcg_temp_free_i64(tcg_op
);
13065 tcg_temp_free_i64(tcg_res
);
13068 tcg_temp_free_i64(tcg_idx
);
13069 clear_vec_high(s
, !is_scalar
, rd
);
13070 } else if (!is_long
) {
13071 /* 32 bit floating point, or 16 or 32 bit integer.
13072 * For the 16 bit scalar case we use the usual Neon helpers and
13073 * rely on the fact that 0 op 0 == 0 with no side effects.
13075 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13076 int pass
, maxpasses
;
13081 maxpasses
= is_q
? 4 : 2;
13084 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13086 if (size
== 1 && !is_scalar
) {
13087 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13088 * the index into both halves of the 32 bit tcg_idx and then use
13089 * the usual Neon helpers.
13091 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13094 for (pass
= 0; pass
< maxpasses
; pass
++) {
13095 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13096 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13098 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13100 switch (16 * u
+ opcode
) {
13101 case 0x08: /* MUL */
13102 case 0x10: /* MLA */
13103 case 0x14: /* MLS */
13105 static NeonGenTwoOpFn
* const fns
[2][2] = {
13106 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13107 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13109 NeonGenTwoOpFn
*genfn
;
13110 bool is_sub
= opcode
== 0x4;
13113 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13115 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13117 if (opcode
== 0x8) {
13120 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13121 genfn
= fns
[size
- 1][is_sub
];
13122 genfn(tcg_res
, tcg_op
, tcg_res
);
13125 case 0x05: /* FMLS */
13126 case 0x01: /* FMLA */
13127 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13128 is_scalar
? size
: MO_32
);
13131 if (opcode
== 0x5) {
13132 /* As usual for ARM, separate negation for fused
13134 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13137 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13140 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13145 if (opcode
== 0x5) {
13146 /* As usual for ARM, separate negation for
13147 * fused multiply-add */
13148 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13150 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13154 g_assert_not_reached();
13157 case 0x09: /* FMUL */
13161 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13164 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13169 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13172 g_assert_not_reached();
13175 case 0x19: /* FMULX */
13179 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13182 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13187 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13190 g_assert_not_reached();
13193 case 0x0c: /* SQDMULH */
13195 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13198 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13202 case 0x0d: /* SQRDMULH */
13204 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13207 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13211 case 0x1d: /* SQRDMLAH */
13212 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13213 is_scalar
? size
: MO_32
);
13215 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13216 tcg_op
, tcg_idx
, tcg_res
);
13218 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13219 tcg_op
, tcg_idx
, tcg_res
);
13222 case 0x1f: /* SQRDMLSH */
13223 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13224 is_scalar
? size
: MO_32
);
13226 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13227 tcg_op
, tcg_idx
, tcg_res
);
13229 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13230 tcg_op
, tcg_idx
, tcg_res
);
13234 g_assert_not_reached();
13238 write_fp_sreg(s
, rd
, tcg_res
);
13240 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13243 tcg_temp_free_i32(tcg_op
);
13244 tcg_temp_free_i32(tcg_res
);
13247 tcg_temp_free_i32(tcg_idx
);
13248 clear_vec_high(s
, is_q
, rd
);
13250 /* long ops: 16x16->32 or 32x32->64 */
13251 TCGv_i64 tcg_res
[2];
13253 bool satop
= extract32(opcode
, 0, 1);
13254 MemOp memop
= MO_32
;
13261 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13263 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13265 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13266 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13267 TCGv_i64 tcg_passres
;
13273 passelt
= pass
+ (is_q
* 2);
13276 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13278 tcg_res
[pass
] = tcg_temp_new_i64();
13280 if (opcode
== 0xa || opcode
== 0xb) {
13281 /* Non-accumulating ops */
13282 tcg_passres
= tcg_res
[pass
];
13284 tcg_passres
= tcg_temp_new_i64();
13287 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13288 tcg_temp_free_i64(tcg_op
);
13291 /* saturating, doubling */
13292 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13293 tcg_passres
, tcg_passres
);
13296 if (opcode
== 0xa || opcode
== 0xb) {
13300 /* Accumulating op: handle accumulate step */
13301 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13304 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13305 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13307 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13308 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13310 case 0x7: /* SQDMLSL, SQDMLSL2 */
13311 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13313 case 0x3: /* SQDMLAL, SQDMLAL2 */
13314 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13319 g_assert_not_reached();
13321 tcg_temp_free_i64(tcg_passres
);
13323 tcg_temp_free_i64(tcg_idx
);
13325 clear_vec_high(s
, !is_scalar
, rd
);
13327 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13330 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13333 /* The simplest way to handle the 16x16 indexed ops is to
13334 * duplicate the index into both halves of the 32 bit tcg_idx
13335 * and then use the usual Neon helpers.
13337 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13340 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13341 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13342 TCGv_i64 tcg_passres
;
13345 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13347 read_vec_element_i32(s
, tcg_op
, rn
,
13348 pass
+ (is_q
* 2), MO_32
);
13351 tcg_res
[pass
] = tcg_temp_new_i64();
13353 if (opcode
== 0xa || opcode
== 0xb) {
13354 /* Non-accumulating ops */
13355 tcg_passres
= tcg_res
[pass
];
13357 tcg_passres
= tcg_temp_new_i64();
13360 if (memop
& MO_SIGN
) {
13361 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13363 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13366 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13367 tcg_passres
, tcg_passres
);
13369 tcg_temp_free_i32(tcg_op
);
13371 if (opcode
== 0xa || opcode
== 0xb) {
13375 /* Accumulating op: handle accumulate step */
13376 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13379 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13380 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13383 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13384 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13387 case 0x7: /* SQDMLSL, SQDMLSL2 */
13388 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13390 case 0x3: /* SQDMLAL, SQDMLAL2 */
13391 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13396 g_assert_not_reached();
13398 tcg_temp_free_i64(tcg_passres
);
13400 tcg_temp_free_i32(tcg_idx
);
13403 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13408 tcg_res
[1] = tcg_const_i64(0);
13411 for (pass
= 0; pass
< 2; pass
++) {
13412 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13413 tcg_temp_free_i64(tcg_res
[pass
]);
13418 tcg_temp_free_ptr(fpst
);
13423 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13424 * +-----------------+------+-----------+--------+-----+------+------+
13425 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13426 * +-----------------+------+-----------+--------+-----+------+------+
13428 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13430 int size
= extract32(insn
, 22, 2);
13431 int opcode
= extract32(insn
, 12, 5);
13432 int rn
= extract32(insn
, 5, 5);
13433 int rd
= extract32(insn
, 0, 5);
13435 gen_helper_gvec_2
*genfn2
= NULL
;
13436 gen_helper_gvec_3
*genfn3
= NULL
;
13438 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13439 unallocated_encoding(s
);
13444 case 0x4: /* AESE */
13446 genfn3
= gen_helper_crypto_aese
;
13448 case 0x6: /* AESMC */
13450 genfn2
= gen_helper_crypto_aesmc
;
13452 case 0x5: /* AESD */
13454 genfn3
= gen_helper_crypto_aese
;
13456 case 0x7: /* AESIMC */
13458 genfn2
= gen_helper_crypto_aesmc
;
13461 unallocated_encoding(s
);
13465 if (!fp_access_check(s
)) {
13469 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13471 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13475 /* Crypto three-reg SHA
13476 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13477 * +-----------------+------+---+------+---+--------+-----+------+------+
13478 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13479 * +-----------------+------+---+------+---+--------+-----+------+------+
13481 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13483 int size
= extract32(insn
, 22, 2);
13484 int opcode
= extract32(insn
, 12, 3);
13485 int rm
= extract32(insn
, 16, 5);
13486 int rn
= extract32(insn
, 5, 5);
13487 int rd
= extract32(insn
, 0, 5);
13488 gen_helper_gvec_3
*genfn
;
13492 unallocated_encoding(s
);
13497 case 0: /* SHA1C */
13498 genfn
= gen_helper_crypto_sha1c
;
13499 feature
= dc_isar_feature(aa64_sha1
, s
);
13501 case 1: /* SHA1P */
13502 genfn
= gen_helper_crypto_sha1p
;
13503 feature
= dc_isar_feature(aa64_sha1
, s
);
13505 case 2: /* SHA1M */
13506 genfn
= gen_helper_crypto_sha1m
;
13507 feature
= dc_isar_feature(aa64_sha1
, s
);
13509 case 3: /* SHA1SU0 */
13510 genfn
= gen_helper_crypto_sha1su0
;
13511 feature
= dc_isar_feature(aa64_sha1
, s
);
13513 case 4: /* SHA256H */
13514 genfn
= gen_helper_crypto_sha256h
;
13515 feature
= dc_isar_feature(aa64_sha256
, s
);
13517 case 5: /* SHA256H2 */
13518 genfn
= gen_helper_crypto_sha256h2
;
13519 feature
= dc_isar_feature(aa64_sha256
, s
);
13521 case 6: /* SHA256SU1 */
13522 genfn
= gen_helper_crypto_sha256su1
;
13523 feature
= dc_isar_feature(aa64_sha256
, s
);
13526 unallocated_encoding(s
);
13531 unallocated_encoding(s
);
13535 if (!fp_access_check(s
)) {
13538 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
13541 /* Crypto two-reg SHA
13542 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13543 * +-----------------+------+-----------+--------+-----+------+------+
13544 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13545 * +-----------------+------+-----------+--------+-----+------+------+
13547 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13549 int size
= extract32(insn
, 22, 2);
13550 int opcode
= extract32(insn
, 12, 5);
13551 int rn
= extract32(insn
, 5, 5);
13552 int rd
= extract32(insn
, 0, 5);
13553 gen_helper_gvec_2
*genfn
;
13557 unallocated_encoding(s
);
13562 case 0: /* SHA1H */
13563 feature
= dc_isar_feature(aa64_sha1
, s
);
13564 genfn
= gen_helper_crypto_sha1h
;
13566 case 1: /* SHA1SU1 */
13567 feature
= dc_isar_feature(aa64_sha1
, s
);
13568 genfn
= gen_helper_crypto_sha1su1
;
13570 case 2: /* SHA256SU0 */
13571 feature
= dc_isar_feature(aa64_sha256
, s
);
13572 genfn
= gen_helper_crypto_sha256su0
;
13575 unallocated_encoding(s
);
13580 unallocated_encoding(s
);
13584 if (!fp_access_check(s
)) {
13587 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
13590 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
13592 tcg_gen_rotli_i64(d
, m
, 1);
13593 tcg_gen_xor_i64(d
, d
, n
);
13596 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
13598 tcg_gen_rotli_vec(vece
, d
, m
, 1);
13599 tcg_gen_xor_vec(vece
, d
, d
, n
);
13602 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
13603 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
13605 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
13606 static const GVecGen3 op
= {
13607 .fni8
= gen_rax1_i64
,
13608 .fniv
= gen_rax1_vec
,
13609 .opt_opc
= vecop_list
,
13610 .fno
= gen_helper_crypto_rax1
,
13613 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
13616 /* Crypto three-reg SHA512
13617 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13618 * +-----------------------+------+---+---+-----+--------+------+------+
13619 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13620 * +-----------------------+------+---+---+-----+--------+------+------+
13622 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13624 int opcode
= extract32(insn
, 10, 2);
13625 int o
= extract32(insn
, 14, 1);
13626 int rm
= extract32(insn
, 16, 5);
13627 int rn
= extract32(insn
, 5, 5);
13628 int rd
= extract32(insn
, 0, 5);
13630 gen_helper_gvec_3
*oolfn
= NULL
;
13631 GVecGen3Fn
*gvecfn
= NULL
;
13635 case 0: /* SHA512H */
13636 feature
= dc_isar_feature(aa64_sha512
, s
);
13637 oolfn
= gen_helper_crypto_sha512h
;
13639 case 1: /* SHA512H2 */
13640 feature
= dc_isar_feature(aa64_sha512
, s
);
13641 oolfn
= gen_helper_crypto_sha512h2
;
13643 case 2: /* SHA512SU1 */
13644 feature
= dc_isar_feature(aa64_sha512
, s
);
13645 oolfn
= gen_helper_crypto_sha512su1
;
13648 feature
= dc_isar_feature(aa64_sha3
, s
);
13649 gvecfn
= gen_gvec_rax1
;
13652 g_assert_not_reached();
13656 case 0: /* SM3PARTW1 */
13657 feature
= dc_isar_feature(aa64_sm3
, s
);
13658 oolfn
= gen_helper_crypto_sm3partw1
;
13660 case 1: /* SM3PARTW2 */
13661 feature
= dc_isar_feature(aa64_sm3
, s
);
13662 oolfn
= gen_helper_crypto_sm3partw2
;
13664 case 2: /* SM4EKEY */
13665 feature
= dc_isar_feature(aa64_sm4
, s
);
13666 oolfn
= gen_helper_crypto_sm4ekey
;
13669 unallocated_encoding(s
);
13675 unallocated_encoding(s
);
13679 if (!fp_access_check(s
)) {
13684 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
13686 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
13690 /* Crypto two-reg SHA512
13691 * 31 12 11 10 9 5 4 0
13692 * +-----------------------------------------+--------+------+------+
13693 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13694 * +-----------------------------------------+--------+------+------+
13696 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13698 int opcode
= extract32(insn
, 10, 2);
13699 int rn
= extract32(insn
, 5, 5);
13700 int rd
= extract32(insn
, 0, 5);
13704 case 0: /* SHA512SU0 */
13705 feature
= dc_isar_feature(aa64_sha512
, s
);
13708 feature
= dc_isar_feature(aa64_sm4
, s
);
13711 unallocated_encoding(s
);
13716 unallocated_encoding(s
);
13720 if (!fp_access_check(s
)) {
13725 case 0: /* SHA512SU0 */
13726 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
13729 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
13732 g_assert_not_reached();
13736 /* Crypto four-register
13737 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13738 * +-------------------+-----+------+---+------+------+------+
13739 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13740 * +-------------------+-----+------+---+------+------+------+
13742 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13744 int op0
= extract32(insn
, 21, 2);
13745 int rm
= extract32(insn
, 16, 5);
13746 int ra
= extract32(insn
, 10, 5);
13747 int rn
= extract32(insn
, 5, 5);
13748 int rd
= extract32(insn
, 0, 5);
13754 feature
= dc_isar_feature(aa64_sha3
, s
);
13756 case 2: /* SM3SS1 */
13757 feature
= dc_isar_feature(aa64_sm3
, s
);
13760 unallocated_encoding(s
);
13765 unallocated_encoding(s
);
13769 if (!fp_access_check(s
)) {
13774 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13777 tcg_op1
= tcg_temp_new_i64();
13778 tcg_op2
= tcg_temp_new_i64();
13779 tcg_op3
= tcg_temp_new_i64();
13780 tcg_res
[0] = tcg_temp_new_i64();
13781 tcg_res
[1] = tcg_temp_new_i64();
13783 for (pass
= 0; pass
< 2; pass
++) {
13784 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13785 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13786 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13790 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13793 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13795 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13797 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13798 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13800 tcg_temp_free_i64(tcg_op1
);
13801 tcg_temp_free_i64(tcg_op2
);
13802 tcg_temp_free_i64(tcg_op3
);
13803 tcg_temp_free_i64(tcg_res
[0]);
13804 tcg_temp_free_i64(tcg_res
[1]);
13806 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13808 tcg_op1
= tcg_temp_new_i32();
13809 tcg_op2
= tcg_temp_new_i32();
13810 tcg_op3
= tcg_temp_new_i32();
13811 tcg_res
= tcg_temp_new_i32();
13812 tcg_zero
= tcg_const_i32(0);
13814 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13815 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13816 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13818 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13819 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13820 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13821 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13823 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13824 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13825 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13826 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13828 tcg_temp_free_i32(tcg_op1
);
13829 tcg_temp_free_i32(tcg_op2
);
13830 tcg_temp_free_i32(tcg_op3
);
13831 tcg_temp_free_i32(tcg_res
);
13832 tcg_temp_free_i32(tcg_zero
);
13837 * 31 21 20 16 15 10 9 5 4 0
13838 * +-----------------------+------+--------+------+------+
13839 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13840 * +-----------------------+------+--------+------+------+
13842 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13844 int rm
= extract32(insn
, 16, 5);
13845 int imm6
= extract32(insn
, 10, 6);
13846 int rn
= extract32(insn
, 5, 5);
13847 int rd
= extract32(insn
, 0, 5);
13848 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13851 if (!dc_isar_feature(aa64_sha3
, s
)) {
13852 unallocated_encoding(s
);
13856 if (!fp_access_check(s
)) {
13860 tcg_op1
= tcg_temp_new_i64();
13861 tcg_op2
= tcg_temp_new_i64();
13862 tcg_res
[0] = tcg_temp_new_i64();
13863 tcg_res
[1] = tcg_temp_new_i64();
13865 for (pass
= 0; pass
< 2; pass
++) {
13866 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13867 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13869 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13870 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13872 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13873 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13875 tcg_temp_free_i64(tcg_op1
);
13876 tcg_temp_free_i64(tcg_op2
);
13877 tcg_temp_free_i64(tcg_res
[0]);
13878 tcg_temp_free_i64(tcg_res
[1]);
13881 /* Crypto three-reg imm2
13882 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13883 * +-----------------------+------+-----+------+--------+------+------+
13884 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13885 * +-----------------------+------+-----+------+--------+------+------+
13887 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13889 static gen_helper_gvec_3
* const fns
[4] = {
13890 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
13891 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
13893 int opcode
= extract32(insn
, 10, 2);
13894 int imm2
= extract32(insn
, 12, 2);
13895 int rm
= extract32(insn
, 16, 5);
13896 int rn
= extract32(insn
, 5, 5);
13897 int rd
= extract32(insn
, 0, 5);
13899 if (!dc_isar_feature(aa64_sm3
, s
)) {
13900 unallocated_encoding(s
);
13904 if (!fp_access_check(s
)) {
13908 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
13911 /* C3.6 Data processing - SIMD, inc Crypto
13913 * As the decode gets a little complex we are using a table based
13914 * approach for this part of the decode.
13916 static const AArch64DecodeTable data_proc_simd
[] = {
13917 /* pattern , mask , fn */
13918 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13919 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13920 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13921 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13922 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13923 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13924 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13925 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13926 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13927 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13928 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13929 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13930 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13931 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13932 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13933 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13934 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13935 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13936 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13937 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13938 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13939 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13940 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13941 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13942 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13943 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13944 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13945 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13946 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13947 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13948 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13949 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13950 { 0x00000000, 0x00000000, NULL
}
13953 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13955 /* Note that this is called with all non-FP cases from
13956 * table C3-6 so it must UNDEF for entries not specifically
13957 * allocated to instructions in that table.
13959 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13963 unallocated_encoding(s
);
13967 /* C3.6 Data processing - SIMD and floating point */
13968 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13970 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13971 disas_data_proc_fp(s
, insn
);
13973 /* SIMD, including crypto */
13974 disas_data_proc_simd(s
, insn
);
13980 * @env: The cpu environment
13981 * @s: The DisasContext
13983 * Return true if the page is guarded.
13985 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13987 #ifdef CONFIG_USER_ONLY
13988 return false; /* FIXME */
13990 uint64_t addr
= s
->base
.pc_first
;
13991 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13992 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13993 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13996 * We test this immediately after reading an insn, which means
13997 * that any normal page must be in the TLB. The only exception
13998 * would be for executing from flash or device memory, which
13999 * does not retain the TLB entry.
14001 * FIXME: Assume false for those, for now. We could use
14002 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14003 * table entry even for that case.
14005 return (tlb_hit(entry
->addr_code
, addr
) &&
14006 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14011 * btype_destination_ok:
14012 * @insn: The instruction at the branch destination
14013 * @bt: SCTLR_ELx.BT
14014 * @btype: PSTATE.BTYPE, and is non-zero
14016 * On a guarded page, there are a limited number of insns
14017 * that may be present at the branch target:
14018 * - branch target identifiers,
14019 * - paciasp, pacibsp,
14022 * Anything else causes a Branch Target Exception.
14024 * Return true if the branch is compatible, false to raise BTITRAP.
14026 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14028 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14030 switch (extract32(insn
, 5, 7)) {
14031 case 0b011001: /* PACIASP */
14032 case 0b011011: /* PACIBSP */
14034 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14035 * with btype == 3. Otherwise all btype are ok.
14037 return !bt
|| btype
!= 3;
14038 case 0b100000: /* BTI */
14039 /* Not compatible with any btype. */
14041 case 0b100010: /* BTI c */
14042 /* Not compatible with btype == 3 */
14044 case 0b100100: /* BTI j */
14045 /* Not compatible with btype == 2 */
14047 case 0b100110: /* BTI jc */
14048 /* Compatible with any btype. */
14052 switch (insn
& 0xffe0001fu
) {
14053 case 0xd4200000u
: /* BRK */
14054 case 0xd4400000u
: /* HLT */
14055 /* Give priority to the breakpoint exception. */
14062 /* C3.1 A64 instruction index by encoding */
14063 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14067 s
->pc_curr
= s
->base
.pc_next
;
14068 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14070 s
->base
.pc_next
+= 4;
14072 s
->fp_access_checked
= false;
14074 if (dc_isar_feature(aa64_bti
, s
)) {
14075 if (s
->base
.num_insns
== 1) {
14077 * At the first insn of the TB, compute s->guarded_page.
14078 * We delayed computing this until successfully reading
14079 * the first insn of the TB, above. This (mostly) ensures
14080 * that the softmmu tlb entry has been populated, and the
14081 * page table GP bit is available.
14083 * Note that we need to compute this even if btype == 0,
14084 * because this value is used for BR instructions later
14085 * where ENV is not available.
14087 s
->guarded_page
= is_guarded_page(env
, s
);
14089 /* First insn can have btype set to non-zero. */
14090 tcg_debug_assert(s
->btype
>= 0);
14093 * Note that the Branch Target Exception has fairly high
14094 * priority -- below debugging exceptions but above most
14095 * everything else. This allows us to handle this now
14096 * instead of waiting until the insn is otherwise decoded.
14100 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14101 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14102 syn_btitrap(s
->btype
),
14103 default_exception_el(s
));
14107 /* Not the first insn: btype must be 0. */
14108 tcg_debug_assert(s
->btype
== 0);
14112 switch (extract32(insn
, 25, 4)) {
14113 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14114 unallocated_encoding(s
);
14117 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14118 unallocated_encoding(s
);
14121 case 0x8: case 0x9: /* Data processing - immediate */
14122 disas_data_proc_imm(s
, insn
);
14124 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14125 disas_b_exc_sys(s
, insn
);
14130 case 0xe: /* Loads and stores */
14131 disas_ldst(s
, insn
);
14134 case 0xd: /* Data processing - register */
14135 disas_data_proc_reg(s
, insn
);
14138 case 0xf: /* Data processing - SIMD and floating point */
14139 disas_data_proc_simd_fp(s
, insn
);
14142 assert(FALSE
); /* all 15 cases should be handled above */
14146 /* if we allocated any temporaries, free them here */
14150 * After execution of most insns, btype is reset to 0.
14151 * Note that we set btype == -1 when the insn sets btype.
14153 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14158 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14161 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14162 CPUARMState
*env
= cpu
->env_ptr
;
14163 ARMCPU
*arm_cpu
= env_archcpu(env
);
14164 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14165 int bound
, core_mmu_idx
;
14167 dc
->isar
= &arm_cpu
->isar
;
14171 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14172 * there is no secure EL1, so we route exceptions to EL3.
14174 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14175 !arm_el_is_aa64(env
, 3);
14178 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14179 dc
->condexec_mask
= 0;
14180 dc
->condexec_cond
= 0;
14181 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14182 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14183 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14184 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14185 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14186 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14187 #if !defined(CONFIG_USER_ONLY)
14188 dc
->user
= (dc
->current_el
== 0);
14190 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14191 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14192 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14193 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14194 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14195 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14196 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14197 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14198 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14199 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14201 dc
->vec_stride
= 0;
14202 dc
->cp_regs
= arm_cpu
->cp_regs
;
14203 dc
->features
= env
->features
;
14205 /* Single step state. The code-generation logic here is:
14207 * generate code with no special handling for single-stepping (except
14208 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14209 * this happens anyway because those changes are all system register or
14211 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14212 * emit code for one insn
14213 * emit code to clear PSTATE.SS
14214 * emit code to generate software step exception for completed step
14215 * end TB (as usual for having generated an exception)
14216 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14217 * emit code to generate a software step exception
14220 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14221 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14222 dc
->is_ldex
= false;
14223 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14225 /* Bound the number of insns to execute to those left on the page. */
14226 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14228 /* If architectural single step active, limit to 1. */
14229 if (dc
->ss_active
) {
14232 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14234 init_tmp_a64_array(dc
);
14237 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14241 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14243 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14245 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14246 dc
->insn_start
= tcg_last_op();
14249 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14250 const CPUBreakpoint
*bp
)
14252 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14254 if (bp
->flags
& BP_CPU
) {
14255 gen_a64_set_pc_im(dc
->base
.pc_next
);
14256 gen_helper_check_breakpoints(cpu_env
);
14257 /* End the TB early; it likely won't be executed */
14258 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14260 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14261 /* The address covered by the breakpoint must be
14262 included in [tb->pc, tb->pc + tb->size) in order
14263 to for it to be properly cleared -- thus we
14264 increment the PC here so that the logic setting
14265 tb->size below does the right thing. */
14266 dc
->base
.pc_next
+= 4;
14267 dc
->base
.is_jmp
= DISAS_NORETURN
;
14273 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14275 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14276 CPUARMState
*env
= cpu
->env_ptr
;
14278 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14279 /* Singlestep state is Active-pending.
14280 * If we're in this state at the start of a TB then either
14281 * a) we just took an exception to an EL which is being debugged
14282 * and this is the first insn in the exception handler
14283 * b) debug exceptions were masked and we just unmasked them
14284 * without changing EL (eg by clearing PSTATE.D)
14285 * In either case we're going to take a swstep exception in the
14286 * "did not step an insn" case, and so the syndrome ISV and EX
14287 * bits should be zero.
14289 assert(dc
->base
.num_insns
== 1);
14290 gen_swstep_exception(dc
, 0, 0);
14291 dc
->base
.is_jmp
= DISAS_NORETURN
;
14293 disas_a64_insn(env
, dc
);
14296 translator_loop_temp_check(&dc
->base
);
14299 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14301 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14303 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14304 /* Note that this means single stepping WFI doesn't halt the CPU.
14305 * For conditional branch insns this is harmless unreachable code as
14306 * gen_goto_tb() has already handled emitting the debug exception
14307 * (and thus a tb-jump is not possible when singlestepping).
14309 switch (dc
->base
.is_jmp
) {
14311 gen_a64_set_pc_im(dc
->base
.pc_next
);
14315 if (dc
->base
.singlestep_enabled
) {
14316 gen_exception_internal(EXCP_DEBUG
);
14318 gen_step_complete_exception(dc
);
14321 case DISAS_NORETURN
:
14325 switch (dc
->base
.is_jmp
) {
14327 case DISAS_TOO_MANY
:
14328 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14331 case DISAS_UPDATE_EXIT
:
14332 gen_a64_set_pc_im(dc
->base
.pc_next
);
14335 tcg_gen_exit_tb(NULL
, 0);
14337 case DISAS_UPDATE_NOCHAIN
:
14338 gen_a64_set_pc_im(dc
->base
.pc_next
);
14341 tcg_gen_lookup_and_goto_ptr();
14343 case DISAS_NORETURN
:
14347 gen_a64_set_pc_im(dc
->base
.pc_next
);
14348 gen_helper_wfe(cpu_env
);
14351 gen_a64_set_pc_im(dc
->base
.pc_next
);
14352 gen_helper_yield(cpu_env
);
14356 /* This is a special case because we don't want to just halt the CPU
14357 * if trying to debug across a WFI.
14359 TCGv_i32 tmp
= tcg_const_i32(4);
14361 gen_a64_set_pc_im(dc
->base
.pc_next
);
14362 gen_helper_wfi(cpu_env
, tmp
);
14363 tcg_temp_free_i32(tmp
);
14364 /* The helper doesn't necessarily throw an exception, but we
14365 * must go back to the main loop to check for interrupts anyway.
14367 tcg_gen_exit_tb(NULL
, 0);
14374 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14377 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14379 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14380 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14383 const TranslatorOps aarch64_translator_ops
= {
14384 .init_disas_context
= aarch64_tr_init_disas_context
,
14385 .tb_start
= aarch64_tr_tb_start
,
14386 .insn_start
= aarch64_tr_insn_start
,
14387 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14388 .translate_insn
= aarch64_tr_translate_insn
,
14389 .tb_stop
= aarch64_tr_tb_stop
,
14390 .disas_log
= aarch64_tr_disas_log
,